1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156 }; 157 158 } // end anonymous namespace 159 160 static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173 } 174 175 // Forward declare these because the autogenerated code will reference them. 176 // Definitions are further down. 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus 186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, 211 const void *Decoder); 212 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 223 unsigned RegNo, 224 uint64_t Address, 225 const void *Decoder); 226 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 237 unsigned RegNo, uint64_t Address, 238 const void *Decoder); 239 240 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 251 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 256 unsigned Insn, 257 uint64_t Address, 258 const void *Decoder); 259 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 268 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 269 unsigned Insn, 270 uint64_t Adddress, 271 const void *Decoder); 272 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 template<int shift> 345 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 398 unsigned Val, 399 uint64_t Address, 400 const void *Decoder); 401 402 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 403 uint64_t Address, const void *Decoder); 404 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 417 uint64_t Address, const void *Decoder); 418 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 421 uint64_t Address, const void *Decoder); 422 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 423 uint64_t Address, const void* Decoder); 424 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 425 uint64_t Address, const void* Decoder); 426 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void* Decoder); 428 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void* Decoder); 430 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 431 uint64_t Address, const void *Decoder); 432 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 433 uint64_t Address, const void *Decoder); 434 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 435 uint64_t Address, const void *Decoder); 436 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 437 uint64_t Address, 438 const void *Decoder); 439 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443 template<int shift> 444 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 447 uint64_t Address, const void *Decoder); 448 template<int shift> 449 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 450 uint64_t Address, const void *Decoder); 451 template<int shift, int WriteBack> 452 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 453 uint64_t Address, const void *Decoder); 454 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 457 uint64_t Address, const void *Decoder); 458 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 461 uint64_t Address, const void *Decoder); 462 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 473 uint64_t Address, const void *Decoder); 474 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 475 uint64_t Address, const void *Decoder); 476 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 477 uint64_t Address, const void *Decoder); 478 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 479 uint64_t Address, const void *Decoder); 480 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 481 uint64_t Address, const void *Decoder); 482 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 483 uint64_t Address, const void *Decoder); 484 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 489 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 490 uint64_t Address, const void *Decoder); 491 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 492 uint64_t Address, const void *Decoder); 493 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 494 uint64_t Address, const void *Decoder); 495 496 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 497 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 498 uint64_t Address, const void *Decoder); 499 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 500 uint64_t Address, 501 const void *Decoder); 502 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const void *Decoder); 505 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 506 const void *Decoder); 507 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 508 uint64_t Address, 509 const void *Decoder); 510 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 511 const void *Decoder); 512 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 513 uint64_t Address, const void *Decoder); 514 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, const void *Decoder); 516 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 517 uint64_t Address, 518 const void *Decoder); 519 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 520 uint64_t Address, 521 const void *Decoder); 522 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 523 uint64_t Address, 524 const void *Decoder); 525 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 526 unsigned Val, 527 uint64_t Address, 528 const void *Decoder); 529 template<bool Writeback> 530 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 531 uint64_t Address, 532 const void *Decoder); 533 template<int shift> 534 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 535 uint64_t Address, const void *Decoder); 536 template<int shift> 537 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 538 uint64_t Address, const void *Decoder); 539 template<int shift> 540 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 541 uint64_t Address, const void *Decoder); 542 template<unsigned MinLog, unsigned MaxLog> 543 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 544 uint64_t Address, 545 const void *Decoder); 546 template<unsigned start> 547 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 548 uint64_t Address, 549 const void *Decoder); 550 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 551 uint64_t Address, 552 const void *Decoder); 553 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 554 uint64_t Address, 555 const void *Decoder); 556 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 557 uint64_t Address, const void *Decoder); 558 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 559 uint64_t Address, const void *Decoder); 560 template<bool scalar, OperandDecoder predicate_decoder> 561 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 562 uint64_t Address, const void *Decoder); 563 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 564 uint64_t Address, const void *Decoder); 565 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 566 uint64_t Address, const void *Decoder); 567 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 568 uint64_t Address, 569 const void *Decoder); 570 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 571 uint64_t Address, const void *Decoder); 572 573 #include "ARMGenDisassemblerTables.inc" 574 575 static MCDisassembler *createARMDisassembler(const Target &T, 576 const MCSubtargetInfo &STI, 577 MCContext &Ctx) { 578 return new ARMDisassembler(STI, Ctx); 579 } 580 581 // Post-decoding checks 582 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 583 uint64_t Address, raw_ostream &CS, 584 uint32_t Insn, 585 DecodeStatus Result) { 586 switch (MI.getOpcode()) { 587 case ARM::HVC: { 588 // HVC is undefined if condition = 0xf otherwise upredictable 589 // if condition != 0xe 590 uint32_t Cond = (Insn >> 28) & 0xF; 591 if (Cond == 0xF) 592 return MCDisassembler::Fail; 593 if (Cond != 0xE) 594 return MCDisassembler::SoftFail; 595 return Result; 596 } 597 case ARM::t2ADDri: 598 case ARM::t2ADDri12: 599 case ARM::t2ADDrr: 600 case ARM::t2ADDrs: 601 case ARM::t2SUBri: 602 case ARM::t2SUBri12: 603 case ARM::t2SUBrr: 604 case ARM::t2SUBrs: 605 if (MI.getOperand(0).getReg() == ARM::SP && 606 MI.getOperand(1).getReg() != ARM::SP) 607 return MCDisassembler::SoftFail; 608 return Result; 609 default: return Result; 610 } 611 } 612 613 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 614 ArrayRef<uint8_t> Bytes, 615 uint64_t Address, 616 raw_ostream &CS) const { 617 if (STI.getFeatureBits()[ARM::ModeThumb]) 618 return getThumbInstruction(MI, Size, Bytes, Address, CS); 619 return getARMInstruction(MI, Size, Bytes, Address, CS); 620 } 621 622 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 623 ArrayRef<uint8_t> Bytes, 624 uint64_t Address, 625 raw_ostream &CS) const { 626 CommentStream = &CS; 627 628 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 629 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 630 "mode!"); 631 632 // We want to read exactly 4 bytes of data. 633 if (Bytes.size() < 4) { 634 Size = 0; 635 return MCDisassembler::Fail; 636 } 637 638 // Encoded as a small-endian 32-bit word in the stream. 639 uint32_t Insn = 640 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 641 642 // Calling the auto-generated decoder function. 643 DecodeStatus Result = 644 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 645 if (Result != MCDisassembler::Fail) { 646 Size = 4; 647 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 648 } 649 650 struct DecodeTable { 651 const uint8_t *P; 652 bool DecodePred; 653 }; 654 655 const DecodeTable Tables[] = { 656 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 657 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 658 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 659 {DecoderTablev8Crypto32, false}, 660 }; 661 662 for (auto Table : Tables) { 663 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 664 if (Result != MCDisassembler::Fail) { 665 Size = 4; 666 // Add a fake predicate operand, because we share these instruction 667 // definitions with Thumb2 where these instructions are predicable. 668 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 669 return MCDisassembler::Fail; 670 return Result; 671 } 672 } 673 674 Result = 675 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 676 if (Result != MCDisassembler::Fail) { 677 Size = 4; 678 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 679 } 680 681 Size = 4; 682 return MCDisassembler::Fail; 683 } 684 685 namespace llvm { 686 687 extern const MCInstrDesc ARMInsts[]; 688 689 } // end namespace llvm 690 691 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 692 /// immediate Value in the MCInst. The immediate Value has had any PC 693 /// adjustment made by the caller. If the instruction is a branch instruction 694 /// then isBranch is true, else false. If the getOpInfo() function was set as 695 /// part of the setupForSymbolicDisassembly() call then that function is called 696 /// to get any symbolic information at the Address for this instruction. If 697 /// that returns non-zero then the symbolic information it returns is used to 698 /// create an MCExpr and that is added as an operand to the MCInst. If 699 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 700 /// Value is done and if a symbol is found an MCExpr is created with that, else 701 /// an MCExpr with Value is created. This function returns true if it adds an 702 /// operand to the MCInst and false otherwise. 703 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 704 bool isBranch, uint64_t InstSize, 705 MCInst &MI, const void *Decoder) { 706 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 707 // FIXME: Does it make sense for value to be negative? 708 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 709 /* Offset */ 0, InstSize); 710 } 711 712 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 713 /// referenced by a load instruction with the base register that is the Pc. 714 /// These can often be values in a literal pool near the Address of the 715 /// instruction. The Address of the instruction and its immediate Value are 716 /// used as a possible literal pool entry. The SymbolLookUp call back will 717 /// return the name of a symbol referenced by the literal pool's entry if 718 /// the referenced address is that of a symbol. Or it will return a pointer to 719 /// a literal 'C' string if the referenced address of the literal pool's entry 720 /// is an address into a section with 'C' string literals. 721 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 722 const void *Decoder) { 723 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 724 Dis->tryAddingPcLoadReferenceComment(Value, Address); 725 } 726 727 // Thumb1 instructions don't have explicit S bits. Rather, they 728 // implicitly set CPSR. Since it's not represented in the encoding, the 729 // auto-generated decoder won't inject the CPSR operand. We need to fix 730 // that as a post-pass. 731 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 732 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 733 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 734 MCInst::iterator I = MI.begin(); 735 for (unsigned i = 0; i < NumOps; ++i, ++I) { 736 if (I == MI.end()) break; 737 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 738 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 739 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 740 return; 741 } 742 } 743 744 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 745 } 746 747 static bool isVectorPredicable(unsigned Opcode) { 748 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 749 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 750 for (unsigned i = 0; i < NumOps; ++i) { 751 if (ARM::isVpred(OpInfo[i].OperandType)) 752 return true; 753 } 754 return false; 755 } 756 757 // Most Thumb instructions don't have explicit predicates in the 758 // encoding, but rather get their predicates from IT context. We need 759 // to fix up the predicate operands using this context information as a 760 // post-pass. 761 MCDisassembler::DecodeStatus 762 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 763 MCDisassembler::DecodeStatus S = Success; 764 765 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 766 767 // A few instructions actually have predicates encoded in them. Don't 768 // try to overwrite it if we're seeing one of those. 769 switch (MI.getOpcode()) { 770 case ARM::tBcc: 771 case ARM::t2Bcc: 772 case ARM::tCBZ: 773 case ARM::tCBNZ: 774 case ARM::tCPS: 775 case ARM::t2CPS3p: 776 case ARM::t2CPS2p: 777 case ARM::t2CPS1p: 778 case ARM::t2CSEL: 779 case ARM::t2CSINC: 780 case ARM::t2CSINV: 781 case ARM::t2CSNEG: 782 case ARM::tMOVSr: 783 case ARM::tSETEND: 784 // Some instructions (mostly conditional branches) are not 785 // allowed in IT blocks. 786 if (ITBlock.instrInITBlock()) 787 S = SoftFail; 788 else 789 return Success; 790 break; 791 case ARM::t2HINT: 792 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 793 S = SoftFail; 794 break; 795 case ARM::tB: 796 case ARM::t2B: 797 case ARM::t2TBB: 798 case ARM::t2TBH: 799 // Some instructions (mostly unconditional branches) can 800 // only appears at the end of, or outside of, an IT. 801 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 802 S = SoftFail; 803 break; 804 default: 805 break; 806 } 807 808 // Warn on non-VPT predicable instruction in a VPT block and a VPT 809 // predicable instruction in an IT block 810 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 811 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 812 S = SoftFail; 813 814 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 815 // assume a predicate of AL. 816 unsigned CC = ARMCC::AL; 817 unsigned VCC = ARMVCC::None; 818 if (ITBlock.instrInITBlock()) { 819 CC = ITBlock.getITCC(); 820 ITBlock.advanceITState(); 821 } else if (VPTBlock.instrInVPTBlock()) { 822 VCC = VPTBlock.getVPTPred(); 823 VPTBlock.advanceVPTState(); 824 } 825 826 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 827 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 828 829 MCInst::iterator CCI = MI.begin(); 830 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 831 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 832 } 833 834 if (ARMInsts[MI.getOpcode()].isPredicable()) { 835 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 836 ++CCI; 837 if (CC == ARMCC::AL) 838 MI.insert(CCI, MCOperand::createReg(0)); 839 else 840 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 841 } else if (CC != ARMCC::AL) { 842 Check(S, SoftFail); 843 } 844 845 MCInst::iterator VCCI = MI.begin(); 846 unsigned VCCPos; 847 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 848 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 849 } 850 851 if (isVectorPredicable(MI.getOpcode())) { 852 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 853 ++VCCI; 854 if (VCC == ARMVCC::None) 855 MI.insert(VCCI, MCOperand::createReg(0)); 856 else 857 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 858 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 859 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 860 VCCPos + 2, MCOI::TIED_TO); 861 assert(TiedOp >= 0 && 862 "Inactive register in vpred_r is not tied to an output!"); 863 MI.insert(VCCI, MI.getOperand(TiedOp)); 864 } 865 } else if (VCC != ARMVCC::None) { 866 Check(S, SoftFail); 867 } 868 869 return S; 870 } 871 872 // Thumb VFP instructions are a special case. Because we share their 873 // encodings between ARM and Thumb modes, and they are predicable in ARM 874 // mode, the auto-generated decoder will give them an (incorrect) 875 // predicate operand. We need to rewrite these operands based on the IT 876 // context as a post-pass. 877 void ARMDisassembler::UpdateThumbVFPPredicate( 878 DecodeStatus &S, MCInst &MI) const { 879 unsigned CC; 880 CC = ITBlock.getITCC(); 881 if (CC == 0xF) 882 CC = ARMCC::AL; 883 if (ITBlock.instrInITBlock()) 884 ITBlock.advanceITState(); 885 else if (VPTBlock.instrInVPTBlock()) { 886 CC = VPTBlock.getVPTPred(); 887 VPTBlock.advanceVPTState(); 888 } 889 890 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 891 MCInst::iterator I = MI.begin(); 892 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 893 for (unsigned i = 0; i < NumOps; ++i, ++I) { 894 if (OpInfo[i].isPredicate() ) { 895 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 896 Check(S, SoftFail); 897 I->setImm(CC); 898 ++I; 899 if (CC == ARMCC::AL) 900 I->setReg(0); 901 else 902 I->setReg(ARM::CPSR); 903 return; 904 } 905 } 906 } 907 908 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 909 ArrayRef<uint8_t> Bytes, 910 uint64_t Address, 911 raw_ostream &CS) const { 912 CommentStream = &CS; 913 914 assert(STI.getFeatureBits()[ARM::ModeThumb] && 915 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 916 917 // We want to read exactly 2 bytes of data. 918 if (Bytes.size() < 2) { 919 Size = 0; 920 return MCDisassembler::Fail; 921 } 922 923 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 924 DecodeStatus Result = 925 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 926 if (Result != MCDisassembler::Fail) { 927 Size = 2; 928 Check(Result, AddThumbPredicate(MI)); 929 return Result; 930 } 931 932 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 933 STI); 934 if (Result) { 935 Size = 2; 936 bool InITBlock = ITBlock.instrInITBlock(); 937 Check(Result, AddThumbPredicate(MI)); 938 AddThumb1SBit(MI, InITBlock); 939 return Result; 940 } 941 942 Result = 943 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 944 if (Result != MCDisassembler::Fail) { 945 Size = 2; 946 947 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 948 // the Thumb predicate. 949 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 950 Result = MCDisassembler::SoftFail; 951 952 Check(Result, AddThumbPredicate(MI)); 953 954 // If we find an IT instruction, we need to parse its condition 955 // code and mask operands so that we can apply them correctly 956 // to the subsequent instructions. 957 if (MI.getOpcode() == ARM::t2IT) { 958 unsigned Firstcond = MI.getOperand(0).getImm(); 959 unsigned Mask = MI.getOperand(1).getImm(); 960 ITBlock.setITState(Firstcond, Mask); 961 962 // An IT instruction that would give a 'NV' predicate is unpredictable. 963 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 964 CS << "unpredictable IT predicate sequence"; 965 } 966 967 return Result; 968 } 969 970 // We want to read exactly 4 bytes of data. 971 if (Bytes.size() < 4) { 972 Size = 0; 973 return MCDisassembler::Fail; 974 } 975 976 uint32_t Insn32 = 977 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 978 979 Result = 980 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 981 if (Result != MCDisassembler::Fail) { 982 Size = 4; 983 984 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 985 // the VPT predicate. 986 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 987 Result = MCDisassembler::SoftFail; 988 989 Check(Result, AddThumbPredicate(MI)); 990 991 if (isVPTOpcode(MI.getOpcode())) { 992 unsigned Mask = MI.getOperand(0).getImm(); 993 VPTBlock.setVPTState(Mask); 994 } 995 996 return Result; 997 } 998 999 Result = 1000 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1001 if (Result != MCDisassembler::Fail) { 1002 Size = 4; 1003 bool InITBlock = ITBlock.instrInITBlock(); 1004 Check(Result, AddThumbPredicate(MI)); 1005 AddThumb1SBit(MI, InITBlock); 1006 return Result; 1007 } 1008 1009 Result = 1010 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1011 if (Result != MCDisassembler::Fail) { 1012 Size = 4; 1013 Check(Result, AddThumbPredicate(MI)); 1014 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1015 } 1016 1017 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1018 Result = 1019 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1020 if (Result != MCDisassembler::Fail) { 1021 Size = 4; 1022 UpdateThumbVFPPredicate(Result, MI); 1023 return Result; 1024 } 1025 } 1026 1027 Result = 1028 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1029 if (Result != MCDisassembler::Fail) { 1030 Size = 4; 1031 return Result; 1032 } 1033 1034 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1035 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1036 STI); 1037 if (Result != MCDisassembler::Fail) { 1038 Size = 4; 1039 Check(Result, AddThumbPredicate(MI)); 1040 return Result; 1041 } 1042 } 1043 1044 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1045 uint32_t NEONLdStInsn = Insn32; 1046 NEONLdStInsn &= 0xF0FFFFFF; 1047 NEONLdStInsn |= 0x04000000; 1048 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1049 Address, this, STI); 1050 if (Result != MCDisassembler::Fail) { 1051 Size = 4; 1052 Check(Result, AddThumbPredicate(MI)); 1053 return Result; 1054 } 1055 } 1056 1057 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1058 uint32_t NEONDataInsn = Insn32; 1059 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1060 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1061 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1062 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1063 Address, this, STI); 1064 if (Result != MCDisassembler::Fail) { 1065 Size = 4; 1066 Check(Result, AddThumbPredicate(MI)); 1067 return Result; 1068 } 1069 1070 uint32_t NEONCryptoInsn = Insn32; 1071 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1072 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1073 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1074 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1075 Address, this, STI); 1076 if (Result != MCDisassembler::Fail) { 1077 Size = 4; 1078 return Result; 1079 } 1080 1081 uint32_t NEONv8Insn = Insn32; 1082 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1083 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1084 this, STI); 1085 if (Result != MCDisassembler::Fail) { 1086 Size = 4; 1087 return Result; 1088 } 1089 } 1090 1091 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1092 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1093 ? DecoderTableThumb2CDE32 1094 : DecoderTableThumb2CoProc32; 1095 Result = 1096 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1097 if (Result != MCDisassembler::Fail) { 1098 Size = 4; 1099 Check(Result, AddThumbPredicate(MI)); 1100 return Result; 1101 } 1102 1103 Size = 0; 1104 return MCDisassembler::Fail; 1105 } 1106 1107 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1108 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1109 createARMDisassembler); 1110 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1111 createARMDisassembler); 1112 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1113 createARMDisassembler); 1114 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1115 createARMDisassembler); 1116 } 1117 1118 static const uint16_t GPRDecoderTable[] = { 1119 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1120 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1121 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1122 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1123 }; 1124 1125 static const uint16_t CLRMGPRDecoderTable[] = { 1126 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1127 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1128 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1129 ARM::R12, 0, ARM::LR, ARM::APSR 1130 }; 1131 1132 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1133 uint64_t Address, const void *Decoder) { 1134 if (RegNo > 15) 1135 return MCDisassembler::Fail; 1136 1137 unsigned Register = GPRDecoderTable[RegNo]; 1138 Inst.addOperand(MCOperand::createReg(Register)); 1139 return MCDisassembler::Success; 1140 } 1141 1142 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1143 uint64_t Address, 1144 const void *Decoder) { 1145 if (RegNo > 15) 1146 return MCDisassembler::Fail; 1147 1148 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1149 if (Register == 0) 1150 return MCDisassembler::Fail; 1151 1152 Inst.addOperand(MCOperand::createReg(Register)); 1153 return MCDisassembler::Success; 1154 } 1155 1156 static DecodeStatus 1157 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1158 uint64_t Address, const void *Decoder) { 1159 DecodeStatus S = MCDisassembler::Success; 1160 1161 if (RegNo == 15) 1162 S = MCDisassembler::SoftFail; 1163 1164 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1165 1166 return S; 1167 } 1168 1169 static DecodeStatus 1170 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1171 uint64_t Address, const void *Decoder) { 1172 DecodeStatus S = MCDisassembler::Success; 1173 1174 if (RegNo == 15) 1175 { 1176 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1177 return MCDisassembler::Success; 1178 } 1179 1180 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1181 return S; 1182 } 1183 1184 static DecodeStatus 1185 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1186 uint64_t Address, const void *Decoder) { 1187 DecodeStatus S = MCDisassembler::Success; 1188 1189 if (RegNo == 15) 1190 { 1191 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1192 return MCDisassembler::Success; 1193 } 1194 1195 if (RegNo == 13) 1196 Check(S, MCDisassembler::SoftFail); 1197 1198 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1199 return S; 1200 } 1201 1202 static DecodeStatus 1203 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1204 uint64_t Address, const void *Decoder) { 1205 DecodeStatus S = MCDisassembler::Success; 1206 if (RegNo == 13) 1207 return MCDisassembler::Fail; 1208 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1209 return S; 1210 } 1211 1212 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1213 uint64_t Address, const void *Decoder) { 1214 if (RegNo > 7) 1215 return MCDisassembler::Fail; 1216 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1217 } 1218 1219 static const uint16_t GPRPairDecoderTable[] = { 1220 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1221 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1222 }; 1223 1224 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1225 uint64_t Address, const void *Decoder) { 1226 DecodeStatus S = MCDisassembler::Success; 1227 1228 if (RegNo > 13) 1229 return MCDisassembler::Fail; 1230 1231 if ((RegNo & 1) || RegNo == 0xe) 1232 S = MCDisassembler::SoftFail; 1233 1234 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1235 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1236 return S; 1237 } 1238 1239 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 1240 uint64_t Address, const void *Decoder) { 1241 if (RegNo > 13) 1242 return MCDisassembler::Fail; 1243 1244 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1245 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1246 1247 if ((RegNo & 1) || RegNo > 10) 1248 return MCDisassembler::SoftFail; 1249 return MCDisassembler::Success; 1250 } 1251 1252 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1253 uint64_t Address, 1254 const void *Decoder) { 1255 if (RegNo != 13) 1256 return MCDisassembler::Fail; 1257 1258 unsigned Register = GPRDecoderTable[RegNo]; 1259 Inst.addOperand(MCOperand::createReg(Register)); 1260 return MCDisassembler::Success; 1261 } 1262 1263 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1264 uint64_t Address, const void *Decoder) { 1265 unsigned Register = 0; 1266 switch (RegNo) { 1267 case 0: 1268 Register = ARM::R0; 1269 break; 1270 case 1: 1271 Register = ARM::R1; 1272 break; 1273 case 2: 1274 Register = ARM::R2; 1275 break; 1276 case 3: 1277 Register = ARM::R3; 1278 break; 1279 case 9: 1280 Register = ARM::R9; 1281 break; 1282 case 12: 1283 Register = ARM::R12; 1284 break; 1285 default: 1286 return MCDisassembler::Fail; 1287 } 1288 1289 Inst.addOperand(MCOperand::createReg(Register)); 1290 return MCDisassembler::Success; 1291 } 1292 1293 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1294 uint64_t Address, const void *Decoder) { 1295 DecodeStatus S = MCDisassembler::Success; 1296 1297 const FeatureBitset &featureBits = 1298 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1299 1300 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1301 S = MCDisassembler::SoftFail; 1302 1303 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1304 return S; 1305 } 1306 1307 static const uint16_t SPRDecoderTable[] = { 1308 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1309 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1310 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1311 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1312 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1313 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1314 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1315 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1316 }; 1317 1318 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1319 uint64_t Address, const void *Decoder) { 1320 if (RegNo > 31) 1321 return MCDisassembler::Fail; 1322 1323 unsigned Register = SPRDecoderTable[RegNo]; 1324 Inst.addOperand(MCOperand::createReg(Register)); 1325 return MCDisassembler::Success; 1326 } 1327 1328 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1329 uint64_t Address, const void *Decoder) { 1330 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1331 } 1332 1333 static const uint16_t DPRDecoderTable[] = { 1334 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1335 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1336 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1337 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1338 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1339 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1340 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1341 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1342 }; 1343 1344 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1345 uint64_t Address, const void *Decoder) { 1346 const FeatureBitset &featureBits = 1347 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1348 1349 bool hasD32 = featureBits[ARM::FeatureD32]; 1350 1351 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1352 return MCDisassembler::Fail; 1353 1354 unsigned Register = DPRDecoderTable[RegNo]; 1355 Inst.addOperand(MCOperand::createReg(Register)); 1356 return MCDisassembler::Success; 1357 } 1358 1359 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1360 uint64_t Address, const void *Decoder) { 1361 if (RegNo > 7) 1362 return MCDisassembler::Fail; 1363 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1364 } 1365 1366 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1367 uint64_t Address, const void *Decoder) { 1368 if (RegNo > 15) 1369 return MCDisassembler::Fail; 1370 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1371 } 1372 1373 static DecodeStatus 1374 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1375 uint64_t Address, const void *Decoder) { 1376 if (RegNo > 15) 1377 return MCDisassembler::Fail; 1378 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1379 } 1380 1381 static const uint16_t QPRDecoderTable[] = { 1382 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1383 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1384 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1385 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1386 }; 1387 1388 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1389 uint64_t Address, const void *Decoder) { 1390 if (RegNo > 31 || (RegNo & 1) != 0) 1391 return MCDisassembler::Fail; 1392 RegNo >>= 1; 1393 1394 unsigned Register = QPRDecoderTable[RegNo]; 1395 Inst.addOperand(MCOperand::createReg(Register)); 1396 return MCDisassembler::Success; 1397 } 1398 1399 static const uint16_t DPairDecoderTable[] = { 1400 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1401 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1402 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1403 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1404 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1405 ARM::Q15 1406 }; 1407 1408 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1409 uint64_t Address, const void *Decoder) { 1410 if (RegNo > 30) 1411 return MCDisassembler::Fail; 1412 1413 unsigned Register = DPairDecoderTable[RegNo]; 1414 Inst.addOperand(MCOperand::createReg(Register)); 1415 return MCDisassembler::Success; 1416 } 1417 1418 static const uint16_t DPairSpacedDecoderTable[] = { 1419 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1420 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1421 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1422 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1423 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1424 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1425 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1426 ARM::D28_D30, ARM::D29_D31 1427 }; 1428 1429 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1430 unsigned RegNo, 1431 uint64_t Address, 1432 const void *Decoder) { 1433 if (RegNo > 29) 1434 return MCDisassembler::Fail; 1435 1436 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1437 Inst.addOperand(MCOperand::createReg(Register)); 1438 return MCDisassembler::Success; 1439 } 1440 1441 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1442 uint64_t Address, const void *Decoder) { 1443 DecodeStatus S = MCDisassembler::Success; 1444 if (Val == 0xF) return MCDisassembler::Fail; 1445 // AL predicate is not allowed on Thumb1 branches. 1446 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1447 return MCDisassembler::Fail; 1448 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1449 Check(S, MCDisassembler::SoftFail); 1450 Inst.addOperand(MCOperand::createImm(Val)); 1451 if (Val == ARMCC::AL) { 1452 Inst.addOperand(MCOperand::createReg(0)); 1453 } else 1454 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1455 return S; 1456 } 1457 1458 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1459 uint64_t Address, const void *Decoder) { 1460 if (Val) 1461 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1462 else 1463 Inst.addOperand(MCOperand::createReg(0)); 1464 return MCDisassembler::Success; 1465 } 1466 1467 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1468 uint64_t Address, const void *Decoder) { 1469 DecodeStatus S = MCDisassembler::Success; 1470 1471 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1472 unsigned type = fieldFromInstruction(Val, 5, 2); 1473 unsigned imm = fieldFromInstruction(Val, 7, 5); 1474 1475 // Register-immediate 1476 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1477 return MCDisassembler::Fail; 1478 1479 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1480 switch (type) { 1481 case 0: 1482 Shift = ARM_AM::lsl; 1483 break; 1484 case 1: 1485 Shift = ARM_AM::lsr; 1486 break; 1487 case 2: 1488 Shift = ARM_AM::asr; 1489 break; 1490 case 3: 1491 Shift = ARM_AM::ror; 1492 break; 1493 } 1494 1495 if (Shift == ARM_AM::ror && imm == 0) 1496 Shift = ARM_AM::rrx; 1497 1498 unsigned Op = Shift | (imm << 3); 1499 Inst.addOperand(MCOperand::createImm(Op)); 1500 1501 return S; 1502 } 1503 1504 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1505 uint64_t Address, const void *Decoder) { 1506 DecodeStatus S = MCDisassembler::Success; 1507 1508 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1509 unsigned type = fieldFromInstruction(Val, 5, 2); 1510 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1511 1512 // Register-register 1513 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1514 return MCDisassembler::Fail; 1515 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1516 return MCDisassembler::Fail; 1517 1518 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1519 switch (type) { 1520 case 0: 1521 Shift = ARM_AM::lsl; 1522 break; 1523 case 1: 1524 Shift = ARM_AM::lsr; 1525 break; 1526 case 2: 1527 Shift = ARM_AM::asr; 1528 break; 1529 case 3: 1530 Shift = ARM_AM::ror; 1531 break; 1532 } 1533 1534 Inst.addOperand(MCOperand::createImm(Shift)); 1535 1536 return S; 1537 } 1538 1539 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1540 uint64_t Address, const void *Decoder) { 1541 DecodeStatus S = MCDisassembler::Success; 1542 1543 bool NeedDisjointWriteback = false; 1544 unsigned WritebackReg = 0; 1545 bool CLRM = false; 1546 switch (Inst.getOpcode()) { 1547 default: 1548 break; 1549 case ARM::LDMIA_UPD: 1550 case ARM::LDMDB_UPD: 1551 case ARM::LDMIB_UPD: 1552 case ARM::LDMDA_UPD: 1553 case ARM::t2LDMIA_UPD: 1554 case ARM::t2LDMDB_UPD: 1555 case ARM::t2STMIA_UPD: 1556 case ARM::t2STMDB_UPD: 1557 NeedDisjointWriteback = true; 1558 WritebackReg = Inst.getOperand(0).getReg(); 1559 break; 1560 case ARM::t2CLRM: 1561 CLRM = true; 1562 break; 1563 } 1564 1565 // Empty register lists are not allowed. 1566 if (Val == 0) return MCDisassembler::Fail; 1567 for (unsigned i = 0; i < 16; ++i) { 1568 if (Val & (1 << i)) { 1569 if (CLRM) { 1570 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1571 return MCDisassembler::Fail; 1572 } 1573 } else { 1574 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1575 return MCDisassembler::Fail; 1576 // Writeback not allowed if Rn is in the target list. 1577 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1578 Check(S, MCDisassembler::SoftFail); 1579 } 1580 } 1581 } 1582 1583 return S; 1584 } 1585 1586 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1587 uint64_t Address, const void *Decoder) { 1588 DecodeStatus S = MCDisassembler::Success; 1589 1590 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1591 unsigned regs = fieldFromInstruction(Val, 0, 8); 1592 1593 // In case of unpredictable encoding, tweak the operands. 1594 if (regs == 0 || (Vd + regs) > 32) { 1595 regs = Vd + regs > 32 ? 32 - Vd : regs; 1596 regs = std::max( 1u, regs); 1597 S = MCDisassembler::SoftFail; 1598 } 1599 1600 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1601 return MCDisassembler::Fail; 1602 for (unsigned i = 0; i < (regs - 1); ++i) { 1603 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1604 return MCDisassembler::Fail; 1605 } 1606 1607 return S; 1608 } 1609 1610 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1611 uint64_t Address, const void *Decoder) { 1612 DecodeStatus S = MCDisassembler::Success; 1613 1614 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1615 unsigned regs = fieldFromInstruction(Val, 1, 7); 1616 1617 // In case of unpredictable encoding, tweak the operands. 1618 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1619 regs = Vd + regs > 32 ? 32 - Vd : regs; 1620 regs = std::max( 1u, regs); 1621 regs = std::min(16u, regs); 1622 S = MCDisassembler::SoftFail; 1623 } 1624 1625 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1626 return MCDisassembler::Fail; 1627 for (unsigned i = 0; i < (regs - 1); ++i) { 1628 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1629 return MCDisassembler::Fail; 1630 } 1631 1632 return S; 1633 } 1634 1635 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1636 uint64_t Address, const void *Decoder) { 1637 // This operand encodes a mask of contiguous zeros between a specified MSB 1638 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1639 // the mask of all bits LSB-and-lower, and then xor them to create 1640 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1641 // create the final mask. 1642 unsigned msb = fieldFromInstruction(Val, 5, 5); 1643 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1644 1645 DecodeStatus S = MCDisassembler::Success; 1646 if (lsb > msb) { 1647 Check(S, MCDisassembler::SoftFail); 1648 // The check above will cause the warning for the "potentially undefined 1649 // instruction encoding" but we can't build a bad MCOperand value here 1650 // with a lsb > msb or else printing the MCInst will cause a crash. 1651 lsb = msb; 1652 } 1653 1654 uint32_t msb_mask = 0xFFFFFFFF; 1655 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1656 uint32_t lsb_mask = (1U << lsb) - 1; 1657 1658 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1659 return S; 1660 } 1661 1662 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1663 uint64_t Address, const void *Decoder) { 1664 DecodeStatus S = MCDisassembler::Success; 1665 1666 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1667 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1668 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1669 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1670 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1671 unsigned U = fieldFromInstruction(Insn, 23, 1); 1672 const FeatureBitset &featureBits = 1673 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1674 1675 switch (Inst.getOpcode()) { 1676 case ARM::LDC_OFFSET: 1677 case ARM::LDC_PRE: 1678 case ARM::LDC_POST: 1679 case ARM::LDC_OPTION: 1680 case ARM::LDCL_OFFSET: 1681 case ARM::LDCL_PRE: 1682 case ARM::LDCL_POST: 1683 case ARM::LDCL_OPTION: 1684 case ARM::STC_OFFSET: 1685 case ARM::STC_PRE: 1686 case ARM::STC_POST: 1687 case ARM::STC_OPTION: 1688 case ARM::STCL_OFFSET: 1689 case ARM::STCL_PRE: 1690 case ARM::STCL_POST: 1691 case ARM::STCL_OPTION: 1692 case ARM::t2LDC_OFFSET: 1693 case ARM::t2LDC_PRE: 1694 case ARM::t2LDC_POST: 1695 case ARM::t2LDC_OPTION: 1696 case ARM::t2LDCL_OFFSET: 1697 case ARM::t2LDCL_PRE: 1698 case ARM::t2LDCL_POST: 1699 case ARM::t2LDCL_OPTION: 1700 case ARM::t2STC_OFFSET: 1701 case ARM::t2STC_PRE: 1702 case ARM::t2STC_POST: 1703 case ARM::t2STC_OPTION: 1704 case ARM::t2STCL_OFFSET: 1705 case ARM::t2STCL_PRE: 1706 case ARM::t2STCL_POST: 1707 case ARM::t2STCL_OPTION: 1708 case ARM::t2LDC2_OFFSET: 1709 case ARM::t2LDC2L_OFFSET: 1710 case ARM::t2LDC2_PRE: 1711 case ARM::t2LDC2L_PRE: 1712 case ARM::t2STC2_OFFSET: 1713 case ARM::t2STC2L_OFFSET: 1714 case ARM::t2STC2_PRE: 1715 case ARM::t2STC2L_PRE: 1716 case ARM::LDC2_OFFSET: 1717 case ARM::LDC2L_OFFSET: 1718 case ARM::LDC2_PRE: 1719 case ARM::LDC2L_PRE: 1720 case ARM::STC2_OFFSET: 1721 case ARM::STC2L_OFFSET: 1722 case ARM::STC2_PRE: 1723 case ARM::STC2L_PRE: 1724 case ARM::t2LDC2_OPTION: 1725 case ARM::t2STC2_OPTION: 1726 case ARM::t2LDC2_POST: 1727 case ARM::t2LDC2L_POST: 1728 case ARM::t2STC2_POST: 1729 case ARM::t2STC2L_POST: 1730 case ARM::LDC2_POST: 1731 case ARM::LDC2L_POST: 1732 case ARM::STC2_POST: 1733 case ARM::STC2L_POST: 1734 if (coproc == 0xA || coproc == 0xB || 1735 (featureBits[ARM::HasV8_1MMainlineOps] && 1736 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1737 coproc == 0xE || coproc == 0xF))) 1738 return MCDisassembler::Fail; 1739 break; 1740 default: 1741 break; 1742 } 1743 1744 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1745 return MCDisassembler::Fail; 1746 1747 Inst.addOperand(MCOperand::createImm(coproc)); 1748 Inst.addOperand(MCOperand::createImm(CRd)); 1749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1750 return MCDisassembler::Fail; 1751 1752 switch (Inst.getOpcode()) { 1753 case ARM::t2LDC2_OFFSET: 1754 case ARM::t2LDC2L_OFFSET: 1755 case ARM::t2LDC2_PRE: 1756 case ARM::t2LDC2L_PRE: 1757 case ARM::t2STC2_OFFSET: 1758 case ARM::t2STC2L_OFFSET: 1759 case ARM::t2STC2_PRE: 1760 case ARM::t2STC2L_PRE: 1761 case ARM::LDC2_OFFSET: 1762 case ARM::LDC2L_OFFSET: 1763 case ARM::LDC2_PRE: 1764 case ARM::LDC2L_PRE: 1765 case ARM::STC2_OFFSET: 1766 case ARM::STC2L_OFFSET: 1767 case ARM::STC2_PRE: 1768 case ARM::STC2L_PRE: 1769 case ARM::t2LDC_OFFSET: 1770 case ARM::t2LDCL_OFFSET: 1771 case ARM::t2LDC_PRE: 1772 case ARM::t2LDCL_PRE: 1773 case ARM::t2STC_OFFSET: 1774 case ARM::t2STCL_OFFSET: 1775 case ARM::t2STC_PRE: 1776 case ARM::t2STCL_PRE: 1777 case ARM::LDC_OFFSET: 1778 case ARM::LDCL_OFFSET: 1779 case ARM::LDC_PRE: 1780 case ARM::LDCL_PRE: 1781 case ARM::STC_OFFSET: 1782 case ARM::STCL_OFFSET: 1783 case ARM::STC_PRE: 1784 case ARM::STCL_PRE: 1785 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1786 Inst.addOperand(MCOperand::createImm(imm)); 1787 break; 1788 case ARM::t2LDC2_POST: 1789 case ARM::t2LDC2L_POST: 1790 case ARM::t2STC2_POST: 1791 case ARM::t2STC2L_POST: 1792 case ARM::LDC2_POST: 1793 case ARM::LDC2L_POST: 1794 case ARM::STC2_POST: 1795 case ARM::STC2L_POST: 1796 case ARM::t2LDC_POST: 1797 case ARM::t2LDCL_POST: 1798 case ARM::t2STC_POST: 1799 case ARM::t2STCL_POST: 1800 case ARM::LDC_POST: 1801 case ARM::LDCL_POST: 1802 case ARM::STC_POST: 1803 case ARM::STCL_POST: 1804 imm |= U << 8; 1805 LLVM_FALLTHROUGH; 1806 default: 1807 // The 'option' variant doesn't encode 'U' in the immediate since 1808 // the immediate is unsigned [0,255]. 1809 Inst.addOperand(MCOperand::createImm(imm)); 1810 break; 1811 } 1812 1813 switch (Inst.getOpcode()) { 1814 case ARM::LDC_OFFSET: 1815 case ARM::LDC_PRE: 1816 case ARM::LDC_POST: 1817 case ARM::LDC_OPTION: 1818 case ARM::LDCL_OFFSET: 1819 case ARM::LDCL_PRE: 1820 case ARM::LDCL_POST: 1821 case ARM::LDCL_OPTION: 1822 case ARM::STC_OFFSET: 1823 case ARM::STC_PRE: 1824 case ARM::STC_POST: 1825 case ARM::STC_OPTION: 1826 case ARM::STCL_OFFSET: 1827 case ARM::STCL_PRE: 1828 case ARM::STCL_POST: 1829 case ARM::STCL_OPTION: 1830 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1831 return MCDisassembler::Fail; 1832 break; 1833 default: 1834 break; 1835 } 1836 1837 return S; 1838 } 1839 1840 static DecodeStatus 1841 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1842 uint64_t Address, const void *Decoder) { 1843 DecodeStatus S = MCDisassembler::Success; 1844 1845 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1846 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1847 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1848 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1849 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1850 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1851 unsigned P = fieldFromInstruction(Insn, 24, 1); 1852 unsigned W = fieldFromInstruction(Insn, 21, 1); 1853 1854 // On stores, the writeback operand precedes Rt. 1855 switch (Inst.getOpcode()) { 1856 case ARM::STR_POST_IMM: 1857 case ARM::STR_POST_REG: 1858 case ARM::STRB_POST_IMM: 1859 case ARM::STRB_POST_REG: 1860 case ARM::STRT_POST_REG: 1861 case ARM::STRT_POST_IMM: 1862 case ARM::STRBT_POST_REG: 1863 case ARM::STRBT_POST_IMM: 1864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1865 return MCDisassembler::Fail; 1866 break; 1867 default: 1868 break; 1869 } 1870 1871 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1872 return MCDisassembler::Fail; 1873 1874 // On loads, the writeback operand comes after Rt. 1875 switch (Inst.getOpcode()) { 1876 case ARM::LDR_POST_IMM: 1877 case ARM::LDR_POST_REG: 1878 case ARM::LDRB_POST_IMM: 1879 case ARM::LDRB_POST_REG: 1880 case ARM::LDRBT_POST_REG: 1881 case ARM::LDRBT_POST_IMM: 1882 case ARM::LDRT_POST_REG: 1883 case ARM::LDRT_POST_IMM: 1884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1885 return MCDisassembler::Fail; 1886 break; 1887 default: 1888 break; 1889 } 1890 1891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1892 return MCDisassembler::Fail; 1893 1894 ARM_AM::AddrOpc Op = ARM_AM::add; 1895 if (!fieldFromInstruction(Insn, 23, 1)) 1896 Op = ARM_AM::sub; 1897 1898 bool writeback = (P == 0) || (W == 1); 1899 unsigned idx_mode = 0; 1900 if (P && writeback) 1901 idx_mode = ARMII::IndexModePre; 1902 else if (!P && writeback) 1903 idx_mode = ARMII::IndexModePost; 1904 1905 if (writeback && (Rn == 15 || Rn == Rt)) 1906 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1907 1908 if (reg) { 1909 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1910 return MCDisassembler::Fail; 1911 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1912 switch( fieldFromInstruction(Insn, 5, 2)) { 1913 case 0: 1914 Opc = ARM_AM::lsl; 1915 break; 1916 case 1: 1917 Opc = ARM_AM::lsr; 1918 break; 1919 case 2: 1920 Opc = ARM_AM::asr; 1921 break; 1922 case 3: 1923 Opc = ARM_AM::ror; 1924 break; 1925 default: 1926 return MCDisassembler::Fail; 1927 } 1928 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1929 if (Opc == ARM_AM::ror && amt == 0) 1930 Opc = ARM_AM::rrx; 1931 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1932 1933 Inst.addOperand(MCOperand::createImm(imm)); 1934 } else { 1935 Inst.addOperand(MCOperand::createReg(0)); 1936 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1937 Inst.addOperand(MCOperand::createImm(tmp)); 1938 } 1939 1940 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1941 return MCDisassembler::Fail; 1942 1943 return S; 1944 } 1945 1946 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1947 uint64_t Address, const void *Decoder) { 1948 DecodeStatus S = MCDisassembler::Success; 1949 1950 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1951 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1952 unsigned type = fieldFromInstruction(Val, 5, 2); 1953 unsigned imm = fieldFromInstruction(Val, 7, 5); 1954 unsigned U = fieldFromInstruction(Val, 12, 1); 1955 1956 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1957 switch (type) { 1958 case 0: 1959 ShOp = ARM_AM::lsl; 1960 break; 1961 case 1: 1962 ShOp = ARM_AM::lsr; 1963 break; 1964 case 2: 1965 ShOp = ARM_AM::asr; 1966 break; 1967 case 3: 1968 ShOp = ARM_AM::ror; 1969 break; 1970 } 1971 1972 if (ShOp == ARM_AM::ror && imm == 0) 1973 ShOp = ARM_AM::rrx; 1974 1975 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1976 return MCDisassembler::Fail; 1977 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1978 return MCDisassembler::Fail; 1979 unsigned shift; 1980 if (U) 1981 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1982 else 1983 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1984 Inst.addOperand(MCOperand::createImm(shift)); 1985 1986 return S; 1987 } 1988 1989 static DecodeStatus 1990 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1991 uint64_t Address, const void *Decoder) { 1992 DecodeStatus S = MCDisassembler::Success; 1993 1994 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1995 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1996 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1997 unsigned type = fieldFromInstruction(Insn, 22, 1); 1998 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1999 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2000 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2001 unsigned W = fieldFromInstruction(Insn, 21, 1); 2002 unsigned P = fieldFromInstruction(Insn, 24, 1); 2003 unsigned Rt2 = Rt + 1; 2004 2005 bool writeback = (W == 1) | (P == 0); 2006 2007 // For {LD,ST}RD, Rt must be even, else undefined. 2008 switch (Inst.getOpcode()) { 2009 case ARM::STRD: 2010 case ARM::STRD_PRE: 2011 case ARM::STRD_POST: 2012 case ARM::LDRD: 2013 case ARM::LDRD_PRE: 2014 case ARM::LDRD_POST: 2015 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2016 break; 2017 default: 2018 break; 2019 } 2020 switch (Inst.getOpcode()) { 2021 case ARM::STRD: 2022 case ARM::STRD_PRE: 2023 case ARM::STRD_POST: 2024 if (P == 0 && W == 1) 2025 S = MCDisassembler::SoftFail; 2026 2027 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2028 S = MCDisassembler::SoftFail; 2029 if (type && Rm == 15) 2030 S = MCDisassembler::SoftFail; 2031 if (Rt2 == 15) 2032 S = MCDisassembler::SoftFail; 2033 if (!type && fieldFromInstruction(Insn, 8, 4)) 2034 S = MCDisassembler::SoftFail; 2035 break; 2036 case ARM::STRH: 2037 case ARM::STRH_PRE: 2038 case ARM::STRH_POST: 2039 if (Rt == 15) 2040 S = MCDisassembler::SoftFail; 2041 if (writeback && (Rn == 15 || Rn == Rt)) 2042 S = MCDisassembler::SoftFail; 2043 if (!type && Rm == 15) 2044 S = MCDisassembler::SoftFail; 2045 break; 2046 case ARM::LDRD: 2047 case ARM::LDRD_PRE: 2048 case ARM::LDRD_POST: 2049 if (type && Rn == 15) { 2050 if (Rt2 == 15) 2051 S = MCDisassembler::SoftFail; 2052 break; 2053 } 2054 if (P == 0 && W == 1) 2055 S = MCDisassembler::SoftFail; 2056 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2057 S = MCDisassembler::SoftFail; 2058 if (!type && writeback && Rn == 15) 2059 S = MCDisassembler::SoftFail; 2060 if (writeback && (Rn == Rt || Rn == Rt2)) 2061 S = MCDisassembler::SoftFail; 2062 break; 2063 case ARM::LDRH: 2064 case ARM::LDRH_PRE: 2065 case ARM::LDRH_POST: 2066 if (type && Rn == 15) { 2067 if (Rt == 15) 2068 S = MCDisassembler::SoftFail; 2069 break; 2070 } 2071 if (Rt == 15) 2072 S = MCDisassembler::SoftFail; 2073 if (!type && Rm == 15) 2074 S = MCDisassembler::SoftFail; 2075 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2076 S = MCDisassembler::SoftFail; 2077 break; 2078 case ARM::LDRSH: 2079 case ARM::LDRSH_PRE: 2080 case ARM::LDRSH_POST: 2081 case ARM::LDRSB: 2082 case ARM::LDRSB_PRE: 2083 case ARM::LDRSB_POST: 2084 if (type && Rn == 15) { 2085 if (Rt == 15) 2086 S = MCDisassembler::SoftFail; 2087 break; 2088 } 2089 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2090 S = MCDisassembler::SoftFail; 2091 if (!type && (Rt == 15 || Rm == 15)) 2092 S = MCDisassembler::SoftFail; 2093 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2094 S = MCDisassembler::SoftFail; 2095 break; 2096 default: 2097 break; 2098 } 2099 2100 if (writeback) { // Writeback 2101 if (P) 2102 U |= ARMII::IndexModePre << 9; 2103 else 2104 U |= ARMII::IndexModePost << 9; 2105 2106 // On stores, the writeback operand precedes Rt. 2107 switch (Inst.getOpcode()) { 2108 case ARM::STRD: 2109 case ARM::STRD_PRE: 2110 case ARM::STRD_POST: 2111 case ARM::STRH: 2112 case ARM::STRH_PRE: 2113 case ARM::STRH_POST: 2114 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2115 return MCDisassembler::Fail; 2116 break; 2117 default: 2118 break; 2119 } 2120 } 2121 2122 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2123 return MCDisassembler::Fail; 2124 switch (Inst.getOpcode()) { 2125 case ARM::STRD: 2126 case ARM::STRD_PRE: 2127 case ARM::STRD_POST: 2128 case ARM::LDRD: 2129 case ARM::LDRD_PRE: 2130 case ARM::LDRD_POST: 2131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2132 return MCDisassembler::Fail; 2133 break; 2134 default: 2135 break; 2136 } 2137 2138 if (writeback) { 2139 // On loads, the writeback operand comes after Rt. 2140 switch (Inst.getOpcode()) { 2141 case ARM::LDRD: 2142 case ARM::LDRD_PRE: 2143 case ARM::LDRD_POST: 2144 case ARM::LDRH: 2145 case ARM::LDRH_PRE: 2146 case ARM::LDRH_POST: 2147 case ARM::LDRSH: 2148 case ARM::LDRSH_PRE: 2149 case ARM::LDRSH_POST: 2150 case ARM::LDRSB: 2151 case ARM::LDRSB_PRE: 2152 case ARM::LDRSB_POST: 2153 case ARM::LDRHTr: 2154 case ARM::LDRSBTr: 2155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2156 return MCDisassembler::Fail; 2157 break; 2158 default: 2159 break; 2160 } 2161 } 2162 2163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2164 return MCDisassembler::Fail; 2165 2166 if (type) { 2167 Inst.addOperand(MCOperand::createReg(0)); 2168 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2169 } else { 2170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2171 return MCDisassembler::Fail; 2172 Inst.addOperand(MCOperand::createImm(U)); 2173 } 2174 2175 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2176 return MCDisassembler::Fail; 2177 2178 return S; 2179 } 2180 2181 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2182 uint64_t Address, const void *Decoder) { 2183 DecodeStatus S = MCDisassembler::Success; 2184 2185 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2186 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2187 2188 switch (mode) { 2189 case 0: 2190 mode = ARM_AM::da; 2191 break; 2192 case 1: 2193 mode = ARM_AM::ia; 2194 break; 2195 case 2: 2196 mode = ARM_AM::db; 2197 break; 2198 case 3: 2199 mode = ARM_AM::ib; 2200 break; 2201 } 2202 2203 Inst.addOperand(MCOperand::createImm(mode)); 2204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2205 return MCDisassembler::Fail; 2206 2207 return S; 2208 } 2209 2210 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2211 uint64_t Address, const void *Decoder) { 2212 DecodeStatus S = MCDisassembler::Success; 2213 2214 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2215 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2216 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2217 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2218 2219 if (pred == 0xF) 2220 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2221 2222 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2223 return MCDisassembler::Fail; 2224 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2225 return MCDisassembler::Fail; 2226 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2227 return MCDisassembler::Fail; 2228 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2229 return MCDisassembler::Fail; 2230 return S; 2231 } 2232 2233 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2234 unsigned Insn, 2235 uint64_t Address, const void *Decoder) { 2236 DecodeStatus S = MCDisassembler::Success; 2237 2238 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2239 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2240 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2241 2242 if (pred == 0xF) { 2243 // Ambiguous with RFE and SRS 2244 switch (Inst.getOpcode()) { 2245 case ARM::LDMDA: 2246 Inst.setOpcode(ARM::RFEDA); 2247 break; 2248 case ARM::LDMDA_UPD: 2249 Inst.setOpcode(ARM::RFEDA_UPD); 2250 break; 2251 case ARM::LDMDB: 2252 Inst.setOpcode(ARM::RFEDB); 2253 break; 2254 case ARM::LDMDB_UPD: 2255 Inst.setOpcode(ARM::RFEDB_UPD); 2256 break; 2257 case ARM::LDMIA: 2258 Inst.setOpcode(ARM::RFEIA); 2259 break; 2260 case ARM::LDMIA_UPD: 2261 Inst.setOpcode(ARM::RFEIA_UPD); 2262 break; 2263 case ARM::LDMIB: 2264 Inst.setOpcode(ARM::RFEIB); 2265 break; 2266 case ARM::LDMIB_UPD: 2267 Inst.setOpcode(ARM::RFEIB_UPD); 2268 break; 2269 case ARM::STMDA: 2270 Inst.setOpcode(ARM::SRSDA); 2271 break; 2272 case ARM::STMDA_UPD: 2273 Inst.setOpcode(ARM::SRSDA_UPD); 2274 break; 2275 case ARM::STMDB: 2276 Inst.setOpcode(ARM::SRSDB); 2277 break; 2278 case ARM::STMDB_UPD: 2279 Inst.setOpcode(ARM::SRSDB_UPD); 2280 break; 2281 case ARM::STMIA: 2282 Inst.setOpcode(ARM::SRSIA); 2283 break; 2284 case ARM::STMIA_UPD: 2285 Inst.setOpcode(ARM::SRSIA_UPD); 2286 break; 2287 case ARM::STMIB: 2288 Inst.setOpcode(ARM::SRSIB); 2289 break; 2290 case ARM::STMIB_UPD: 2291 Inst.setOpcode(ARM::SRSIB_UPD); 2292 break; 2293 default: 2294 return MCDisassembler::Fail; 2295 } 2296 2297 // For stores (which become SRS's, the only operand is the mode. 2298 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2299 // Check SRS encoding constraints 2300 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2301 fieldFromInstruction(Insn, 20, 1) == 0)) 2302 return MCDisassembler::Fail; 2303 2304 Inst.addOperand( 2305 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2306 return S; 2307 } 2308 2309 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2310 } 2311 2312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2313 return MCDisassembler::Fail; 2314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2315 return MCDisassembler::Fail; // Tied 2316 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2317 return MCDisassembler::Fail; 2318 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2319 return MCDisassembler::Fail; 2320 2321 return S; 2322 } 2323 2324 // Check for UNPREDICTABLE predicated ESB instruction 2325 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2326 uint64_t Address, const void *Decoder) { 2327 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2328 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2329 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2330 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2331 2332 DecodeStatus S = MCDisassembler::Success; 2333 2334 Inst.addOperand(MCOperand::createImm(imm8)); 2335 2336 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2337 return MCDisassembler::Fail; 2338 2339 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2340 // so all predicates should be allowed. 2341 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2342 S = MCDisassembler::SoftFail; 2343 2344 return S; 2345 } 2346 2347 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2348 uint64_t Address, const void *Decoder) { 2349 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2350 unsigned M = fieldFromInstruction(Insn, 17, 1); 2351 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2352 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2353 2354 DecodeStatus S = MCDisassembler::Success; 2355 2356 // This decoder is called from multiple location that do not check 2357 // the full encoding is valid before they do. 2358 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2359 fieldFromInstruction(Insn, 16, 1) != 0 || 2360 fieldFromInstruction(Insn, 20, 8) != 0x10) 2361 return MCDisassembler::Fail; 2362 2363 // imod == '01' --> UNPREDICTABLE 2364 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2365 // return failure here. The '01' imod value is unprintable, so there's 2366 // nothing useful we could do even if we returned UNPREDICTABLE. 2367 2368 if (imod == 1) return MCDisassembler::Fail; 2369 2370 if (imod && M) { 2371 Inst.setOpcode(ARM::CPS3p); 2372 Inst.addOperand(MCOperand::createImm(imod)); 2373 Inst.addOperand(MCOperand::createImm(iflags)); 2374 Inst.addOperand(MCOperand::createImm(mode)); 2375 } else if (imod && !M) { 2376 Inst.setOpcode(ARM::CPS2p); 2377 Inst.addOperand(MCOperand::createImm(imod)); 2378 Inst.addOperand(MCOperand::createImm(iflags)); 2379 if (mode) S = MCDisassembler::SoftFail; 2380 } else if (!imod && M) { 2381 Inst.setOpcode(ARM::CPS1p); 2382 Inst.addOperand(MCOperand::createImm(mode)); 2383 if (iflags) S = MCDisassembler::SoftFail; 2384 } else { 2385 // imod == '00' && M == '0' --> UNPREDICTABLE 2386 Inst.setOpcode(ARM::CPS1p); 2387 Inst.addOperand(MCOperand::createImm(mode)); 2388 S = MCDisassembler::SoftFail; 2389 } 2390 2391 return S; 2392 } 2393 2394 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2395 uint64_t Address, const void *Decoder) { 2396 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2397 unsigned M = fieldFromInstruction(Insn, 8, 1); 2398 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2399 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2400 2401 DecodeStatus S = MCDisassembler::Success; 2402 2403 // imod == '01' --> UNPREDICTABLE 2404 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2405 // return failure here. The '01' imod value is unprintable, so there's 2406 // nothing useful we could do even if we returned UNPREDICTABLE. 2407 2408 if (imod == 1) return MCDisassembler::Fail; 2409 2410 if (imod && M) { 2411 Inst.setOpcode(ARM::t2CPS3p); 2412 Inst.addOperand(MCOperand::createImm(imod)); 2413 Inst.addOperand(MCOperand::createImm(iflags)); 2414 Inst.addOperand(MCOperand::createImm(mode)); 2415 } else if (imod && !M) { 2416 Inst.setOpcode(ARM::t2CPS2p); 2417 Inst.addOperand(MCOperand::createImm(imod)); 2418 Inst.addOperand(MCOperand::createImm(iflags)); 2419 if (mode) S = MCDisassembler::SoftFail; 2420 } else if (!imod && M) { 2421 Inst.setOpcode(ARM::t2CPS1p); 2422 Inst.addOperand(MCOperand::createImm(mode)); 2423 if (iflags) S = MCDisassembler::SoftFail; 2424 } else { 2425 // imod == '00' && M == '0' --> this is a HINT instruction 2426 int imm = fieldFromInstruction(Insn, 0, 8); 2427 // HINT are defined only for immediate in [0..4] 2428 if(imm > 4) return MCDisassembler::Fail; 2429 Inst.setOpcode(ARM::t2HINT); 2430 Inst.addOperand(MCOperand::createImm(imm)); 2431 } 2432 2433 return S; 2434 } 2435 2436 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2437 uint64_t Address, const void *Decoder) { 2438 DecodeStatus S = MCDisassembler::Success; 2439 2440 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2441 unsigned imm = 0; 2442 2443 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2444 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2445 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2446 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2447 2448 if (Inst.getOpcode() == ARM::t2MOVTi16) 2449 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2450 return MCDisassembler::Fail; 2451 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2452 return MCDisassembler::Fail; 2453 2454 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2455 Inst.addOperand(MCOperand::createImm(imm)); 2456 2457 return S; 2458 } 2459 2460 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2461 uint64_t Address, const void *Decoder) { 2462 DecodeStatus S = MCDisassembler::Success; 2463 2464 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2465 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2466 unsigned imm = 0; 2467 2468 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2469 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2470 2471 if (Inst.getOpcode() == ARM::MOVTi16) 2472 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2473 return MCDisassembler::Fail; 2474 2475 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2476 return MCDisassembler::Fail; 2477 2478 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2479 Inst.addOperand(MCOperand::createImm(imm)); 2480 2481 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2482 return MCDisassembler::Fail; 2483 2484 return S; 2485 } 2486 2487 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2488 uint64_t Address, const void *Decoder) { 2489 DecodeStatus S = MCDisassembler::Success; 2490 2491 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2492 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2493 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2494 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2495 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2496 2497 if (pred == 0xF) 2498 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2499 2500 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2501 return MCDisassembler::Fail; 2502 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2503 return MCDisassembler::Fail; 2504 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2505 return MCDisassembler::Fail; 2506 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2507 return MCDisassembler::Fail; 2508 2509 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 2512 return S; 2513 } 2514 2515 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2516 uint64_t Address, const void *Decoder) { 2517 DecodeStatus S = MCDisassembler::Success; 2518 2519 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2520 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2521 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2522 2523 if (Pred == 0xF) 2524 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2525 2526 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2527 return MCDisassembler::Fail; 2528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2529 return MCDisassembler::Fail; 2530 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2531 return MCDisassembler::Fail; 2532 2533 return S; 2534 } 2535 2536 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2537 uint64_t Address, const void *Decoder) { 2538 DecodeStatus S = MCDisassembler::Success; 2539 2540 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2541 2542 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2543 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2544 2545 if (!FeatureBits[ARM::HasV8_1aOps] || 2546 !FeatureBits[ARM::HasV8Ops]) 2547 return MCDisassembler::Fail; 2548 2549 // Decoder can be called from DecodeTST, which does not check the full 2550 // encoding is valid. 2551 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2552 fieldFromInstruction(Insn, 4,4) != 0) 2553 return MCDisassembler::Fail; 2554 if (fieldFromInstruction(Insn, 10,10) != 0 || 2555 fieldFromInstruction(Insn, 0,4) != 0) 2556 S = MCDisassembler::SoftFail; 2557 2558 Inst.setOpcode(ARM::SETPAN); 2559 Inst.addOperand(MCOperand::createImm(Imm)); 2560 2561 return S; 2562 } 2563 2564 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2565 uint64_t Address, const void *Decoder) { 2566 DecodeStatus S = MCDisassembler::Success; 2567 2568 unsigned add = fieldFromInstruction(Val, 12, 1); 2569 unsigned imm = fieldFromInstruction(Val, 0, 12); 2570 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2571 2572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2573 return MCDisassembler::Fail; 2574 2575 if (!add) imm *= -1; 2576 if (imm == 0 && !add) imm = INT32_MIN; 2577 Inst.addOperand(MCOperand::createImm(imm)); 2578 if (Rn == 15) 2579 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2580 2581 return S; 2582 } 2583 2584 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2585 uint64_t Address, const void *Decoder) { 2586 DecodeStatus S = MCDisassembler::Success; 2587 2588 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2589 // U == 1 to add imm, 0 to subtract it. 2590 unsigned U = fieldFromInstruction(Val, 8, 1); 2591 unsigned imm = fieldFromInstruction(Val, 0, 8); 2592 2593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2594 return MCDisassembler::Fail; 2595 2596 if (U) 2597 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2598 else 2599 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2600 2601 return S; 2602 } 2603 2604 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2605 uint64_t Address, const void *Decoder) { 2606 DecodeStatus S = MCDisassembler::Success; 2607 2608 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2609 // U == 1 to add imm, 0 to subtract it. 2610 unsigned U = fieldFromInstruction(Val, 8, 1); 2611 unsigned imm = fieldFromInstruction(Val, 0, 8); 2612 2613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2614 return MCDisassembler::Fail; 2615 2616 if (U) 2617 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2618 else 2619 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2620 2621 return S; 2622 } 2623 2624 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2625 uint64_t Address, const void *Decoder) { 2626 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2627 } 2628 2629 static DecodeStatus 2630 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2631 uint64_t Address, const void *Decoder) { 2632 DecodeStatus Status = MCDisassembler::Success; 2633 2634 // Note the J1 and J2 values are from the encoded instruction. So here 2635 // change them to I1 and I2 values via as documented: 2636 // I1 = NOT(J1 EOR S); 2637 // I2 = NOT(J2 EOR S); 2638 // and build the imm32 with one trailing zero as documented: 2639 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2640 unsigned S = fieldFromInstruction(Insn, 26, 1); 2641 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2642 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2643 unsigned I1 = !(J1 ^ S); 2644 unsigned I2 = !(J2 ^ S); 2645 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2646 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2647 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2648 int imm32 = SignExtend32<25>(tmp << 1); 2649 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2650 true, 4, Inst, Decoder)) 2651 Inst.addOperand(MCOperand::createImm(imm32)); 2652 2653 return Status; 2654 } 2655 2656 static DecodeStatus 2657 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2658 uint64_t Address, const void *Decoder) { 2659 DecodeStatus S = MCDisassembler::Success; 2660 2661 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2662 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2663 2664 if (pred == 0xF) { 2665 Inst.setOpcode(ARM::BLXi); 2666 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2667 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2668 true, 4, Inst, Decoder)) 2669 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2670 return S; 2671 } 2672 2673 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2674 true, 4, Inst, Decoder)) 2675 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2676 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2677 return MCDisassembler::Fail; 2678 2679 return S; 2680 } 2681 2682 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2683 uint64_t Address, const void *Decoder) { 2684 DecodeStatus S = MCDisassembler::Success; 2685 2686 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2687 unsigned align = fieldFromInstruction(Val, 4, 2); 2688 2689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2690 return MCDisassembler::Fail; 2691 if (!align) 2692 Inst.addOperand(MCOperand::createImm(0)); 2693 else 2694 Inst.addOperand(MCOperand::createImm(4 << align)); 2695 2696 return S; 2697 } 2698 2699 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2700 uint64_t Address, const void *Decoder) { 2701 DecodeStatus S = MCDisassembler::Success; 2702 2703 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2704 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2705 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2706 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2707 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2708 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2709 2710 // First output register 2711 switch (Inst.getOpcode()) { 2712 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2713 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2714 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2715 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2716 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2717 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2718 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2719 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2720 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2721 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 break; 2724 case ARM::VLD2b16: 2725 case ARM::VLD2b32: 2726 case ARM::VLD2b8: 2727 case ARM::VLD2b16wb_fixed: 2728 case ARM::VLD2b16wb_register: 2729 case ARM::VLD2b32wb_fixed: 2730 case ARM::VLD2b32wb_register: 2731 case ARM::VLD2b8wb_fixed: 2732 case ARM::VLD2b8wb_register: 2733 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2734 return MCDisassembler::Fail; 2735 break; 2736 default: 2737 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 } 2740 2741 // Second output register 2742 switch (Inst.getOpcode()) { 2743 case ARM::VLD3d8: 2744 case ARM::VLD3d16: 2745 case ARM::VLD3d32: 2746 case ARM::VLD3d8_UPD: 2747 case ARM::VLD3d16_UPD: 2748 case ARM::VLD3d32_UPD: 2749 case ARM::VLD4d8: 2750 case ARM::VLD4d16: 2751 case ARM::VLD4d32: 2752 case ARM::VLD4d8_UPD: 2753 case ARM::VLD4d16_UPD: 2754 case ARM::VLD4d32_UPD: 2755 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2756 return MCDisassembler::Fail; 2757 break; 2758 case ARM::VLD3q8: 2759 case ARM::VLD3q16: 2760 case ARM::VLD3q32: 2761 case ARM::VLD3q8_UPD: 2762 case ARM::VLD3q16_UPD: 2763 case ARM::VLD3q32_UPD: 2764 case ARM::VLD4q8: 2765 case ARM::VLD4q16: 2766 case ARM::VLD4q32: 2767 case ARM::VLD4q8_UPD: 2768 case ARM::VLD4q16_UPD: 2769 case ARM::VLD4q32_UPD: 2770 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2771 return MCDisassembler::Fail; 2772 break; 2773 default: 2774 break; 2775 } 2776 2777 // Third output register 2778 switch(Inst.getOpcode()) { 2779 case ARM::VLD3d8: 2780 case ARM::VLD3d16: 2781 case ARM::VLD3d32: 2782 case ARM::VLD3d8_UPD: 2783 case ARM::VLD3d16_UPD: 2784 case ARM::VLD3d32_UPD: 2785 case ARM::VLD4d8: 2786 case ARM::VLD4d16: 2787 case ARM::VLD4d32: 2788 case ARM::VLD4d8_UPD: 2789 case ARM::VLD4d16_UPD: 2790 case ARM::VLD4d32_UPD: 2791 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2792 return MCDisassembler::Fail; 2793 break; 2794 case ARM::VLD3q8: 2795 case ARM::VLD3q16: 2796 case ARM::VLD3q32: 2797 case ARM::VLD3q8_UPD: 2798 case ARM::VLD3q16_UPD: 2799 case ARM::VLD3q32_UPD: 2800 case ARM::VLD4q8: 2801 case ARM::VLD4q16: 2802 case ARM::VLD4q32: 2803 case ARM::VLD4q8_UPD: 2804 case ARM::VLD4q16_UPD: 2805 case ARM::VLD4q32_UPD: 2806 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2807 return MCDisassembler::Fail; 2808 break; 2809 default: 2810 break; 2811 } 2812 2813 // Fourth output register 2814 switch (Inst.getOpcode()) { 2815 case ARM::VLD4d8: 2816 case ARM::VLD4d16: 2817 case ARM::VLD4d32: 2818 case ARM::VLD4d8_UPD: 2819 case ARM::VLD4d16_UPD: 2820 case ARM::VLD4d32_UPD: 2821 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2822 return MCDisassembler::Fail; 2823 break; 2824 case ARM::VLD4q8: 2825 case ARM::VLD4q16: 2826 case ARM::VLD4q32: 2827 case ARM::VLD4q8_UPD: 2828 case ARM::VLD4q16_UPD: 2829 case ARM::VLD4q32_UPD: 2830 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2831 return MCDisassembler::Fail; 2832 break; 2833 default: 2834 break; 2835 } 2836 2837 // Writeback operand 2838 switch (Inst.getOpcode()) { 2839 case ARM::VLD1d8wb_fixed: 2840 case ARM::VLD1d16wb_fixed: 2841 case ARM::VLD1d32wb_fixed: 2842 case ARM::VLD1d64wb_fixed: 2843 case ARM::VLD1d8wb_register: 2844 case ARM::VLD1d16wb_register: 2845 case ARM::VLD1d32wb_register: 2846 case ARM::VLD1d64wb_register: 2847 case ARM::VLD1q8wb_fixed: 2848 case ARM::VLD1q16wb_fixed: 2849 case ARM::VLD1q32wb_fixed: 2850 case ARM::VLD1q64wb_fixed: 2851 case ARM::VLD1q8wb_register: 2852 case ARM::VLD1q16wb_register: 2853 case ARM::VLD1q32wb_register: 2854 case ARM::VLD1q64wb_register: 2855 case ARM::VLD1d8Twb_fixed: 2856 case ARM::VLD1d8Twb_register: 2857 case ARM::VLD1d16Twb_fixed: 2858 case ARM::VLD1d16Twb_register: 2859 case ARM::VLD1d32Twb_fixed: 2860 case ARM::VLD1d32Twb_register: 2861 case ARM::VLD1d64Twb_fixed: 2862 case ARM::VLD1d64Twb_register: 2863 case ARM::VLD1d8Qwb_fixed: 2864 case ARM::VLD1d8Qwb_register: 2865 case ARM::VLD1d16Qwb_fixed: 2866 case ARM::VLD1d16Qwb_register: 2867 case ARM::VLD1d32Qwb_fixed: 2868 case ARM::VLD1d32Qwb_register: 2869 case ARM::VLD1d64Qwb_fixed: 2870 case ARM::VLD1d64Qwb_register: 2871 case ARM::VLD2d8wb_fixed: 2872 case ARM::VLD2d16wb_fixed: 2873 case ARM::VLD2d32wb_fixed: 2874 case ARM::VLD2q8wb_fixed: 2875 case ARM::VLD2q16wb_fixed: 2876 case ARM::VLD2q32wb_fixed: 2877 case ARM::VLD2d8wb_register: 2878 case ARM::VLD2d16wb_register: 2879 case ARM::VLD2d32wb_register: 2880 case ARM::VLD2q8wb_register: 2881 case ARM::VLD2q16wb_register: 2882 case ARM::VLD2q32wb_register: 2883 case ARM::VLD2b8wb_fixed: 2884 case ARM::VLD2b16wb_fixed: 2885 case ARM::VLD2b32wb_fixed: 2886 case ARM::VLD2b8wb_register: 2887 case ARM::VLD2b16wb_register: 2888 case ARM::VLD2b32wb_register: 2889 Inst.addOperand(MCOperand::createImm(0)); 2890 break; 2891 case ARM::VLD3d8_UPD: 2892 case ARM::VLD3d16_UPD: 2893 case ARM::VLD3d32_UPD: 2894 case ARM::VLD3q8_UPD: 2895 case ARM::VLD3q16_UPD: 2896 case ARM::VLD3q32_UPD: 2897 case ARM::VLD4d8_UPD: 2898 case ARM::VLD4d16_UPD: 2899 case ARM::VLD4d32_UPD: 2900 case ARM::VLD4q8_UPD: 2901 case ARM::VLD4q16_UPD: 2902 case ARM::VLD4q32_UPD: 2903 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2904 return MCDisassembler::Fail; 2905 break; 2906 default: 2907 break; 2908 } 2909 2910 // AddrMode6 Base (register+alignment) 2911 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2912 return MCDisassembler::Fail; 2913 2914 // AddrMode6 Offset (register) 2915 switch (Inst.getOpcode()) { 2916 default: 2917 // The below have been updated to have explicit am6offset split 2918 // between fixed and register offset. For those instructions not 2919 // yet updated, we need to add an additional reg0 operand for the 2920 // fixed variant. 2921 // 2922 // The fixed offset encodes as Rm == 0xd, so we check for that. 2923 if (Rm == 0xd) { 2924 Inst.addOperand(MCOperand::createReg(0)); 2925 break; 2926 } 2927 // Fall through to handle the register offset variant. 2928 LLVM_FALLTHROUGH; 2929 case ARM::VLD1d8wb_fixed: 2930 case ARM::VLD1d16wb_fixed: 2931 case ARM::VLD1d32wb_fixed: 2932 case ARM::VLD1d64wb_fixed: 2933 case ARM::VLD1d8Twb_fixed: 2934 case ARM::VLD1d16Twb_fixed: 2935 case ARM::VLD1d32Twb_fixed: 2936 case ARM::VLD1d64Twb_fixed: 2937 case ARM::VLD1d8Qwb_fixed: 2938 case ARM::VLD1d16Qwb_fixed: 2939 case ARM::VLD1d32Qwb_fixed: 2940 case ARM::VLD1d64Qwb_fixed: 2941 case ARM::VLD1d8wb_register: 2942 case ARM::VLD1d16wb_register: 2943 case ARM::VLD1d32wb_register: 2944 case ARM::VLD1d64wb_register: 2945 case ARM::VLD1q8wb_fixed: 2946 case ARM::VLD1q16wb_fixed: 2947 case ARM::VLD1q32wb_fixed: 2948 case ARM::VLD1q64wb_fixed: 2949 case ARM::VLD1q8wb_register: 2950 case ARM::VLD1q16wb_register: 2951 case ARM::VLD1q32wb_register: 2952 case ARM::VLD1q64wb_register: 2953 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2954 // variant encodes Rm == 0xf. Anything else is a register offset post- 2955 // increment and we need to add the register operand to the instruction. 2956 if (Rm != 0xD && Rm != 0xF && 2957 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2958 return MCDisassembler::Fail; 2959 break; 2960 case ARM::VLD2d8wb_fixed: 2961 case ARM::VLD2d16wb_fixed: 2962 case ARM::VLD2d32wb_fixed: 2963 case ARM::VLD2b8wb_fixed: 2964 case ARM::VLD2b16wb_fixed: 2965 case ARM::VLD2b32wb_fixed: 2966 case ARM::VLD2q8wb_fixed: 2967 case ARM::VLD2q16wb_fixed: 2968 case ARM::VLD2q32wb_fixed: 2969 break; 2970 } 2971 2972 return S; 2973 } 2974 2975 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2976 uint64_t Address, const void *Decoder) { 2977 unsigned type = fieldFromInstruction(Insn, 8, 4); 2978 unsigned align = fieldFromInstruction(Insn, 4, 2); 2979 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2980 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2981 if (type == 10 && align == 3) return MCDisassembler::Fail; 2982 2983 unsigned load = fieldFromInstruction(Insn, 21, 1); 2984 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2985 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2986 } 2987 2988 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2989 uint64_t Address, const void *Decoder) { 2990 unsigned size = fieldFromInstruction(Insn, 6, 2); 2991 if (size == 3) return MCDisassembler::Fail; 2992 2993 unsigned type = fieldFromInstruction(Insn, 8, 4); 2994 unsigned align = fieldFromInstruction(Insn, 4, 2); 2995 if (type == 8 && align == 3) return MCDisassembler::Fail; 2996 if (type == 9 && align == 3) return MCDisassembler::Fail; 2997 2998 unsigned load = fieldFromInstruction(Insn, 21, 1); 2999 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3000 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3001 } 3002 3003 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3004 uint64_t Address, const void *Decoder) { 3005 unsigned size = fieldFromInstruction(Insn, 6, 2); 3006 if (size == 3) return MCDisassembler::Fail; 3007 3008 unsigned align = fieldFromInstruction(Insn, 4, 2); 3009 if (align & 2) return MCDisassembler::Fail; 3010 3011 unsigned load = fieldFromInstruction(Insn, 21, 1); 3012 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3013 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3014 } 3015 3016 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3017 uint64_t Address, const void *Decoder) { 3018 unsigned size = fieldFromInstruction(Insn, 6, 2); 3019 if (size == 3) return MCDisassembler::Fail; 3020 3021 unsigned load = fieldFromInstruction(Insn, 21, 1); 3022 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3023 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3024 } 3025 3026 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3027 uint64_t Address, const void *Decoder) { 3028 DecodeStatus S = MCDisassembler::Success; 3029 3030 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3031 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3032 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3033 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3034 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3035 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3036 3037 // Writeback Operand 3038 switch (Inst.getOpcode()) { 3039 case ARM::VST1d8wb_fixed: 3040 case ARM::VST1d16wb_fixed: 3041 case ARM::VST1d32wb_fixed: 3042 case ARM::VST1d64wb_fixed: 3043 case ARM::VST1d8wb_register: 3044 case ARM::VST1d16wb_register: 3045 case ARM::VST1d32wb_register: 3046 case ARM::VST1d64wb_register: 3047 case ARM::VST1q8wb_fixed: 3048 case ARM::VST1q16wb_fixed: 3049 case ARM::VST1q32wb_fixed: 3050 case ARM::VST1q64wb_fixed: 3051 case ARM::VST1q8wb_register: 3052 case ARM::VST1q16wb_register: 3053 case ARM::VST1q32wb_register: 3054 case ARM::VST1q64wb_register: 3055 case ARM::VST1d8Twb_fixed: 3056 case ARM::VST1d16Twb_fixed: 3057 case ARM::VST1d32Twb_fixed: 3058 case ARM::VST1d64Twb_fixed: 3059 case ARM::VST1d8Twb_register: 3060 case ARM::VST1d16Twb_register: 3061 case ARM::VST1d32Twb_register: 3062 case ARM::VST1d64Twb_register: 3063 case ARM::VST1d8Qwb_fixed: 3064 case ARM::VST1d16Qwb_fixed: 3065 case ARM::VST1d32Qwb_fixed: 3066 case ARM::VST1d64Qwb_fixed: 3067 case ARM::VST1d8Qwb_register: 3068 case ARM::VST1d16Qwb_register: 3069 case ARM::VST1d32Qwb_register: 3070 case ARM::VST1d64Qwb_register: 3071 case ARM::VST2d8wb_fixed: 3072 case ARM::VST2d16wb_fixed: 3073 case ARM::VST2d32wb_fixed: 3074 case ARM::VST2d8wb_register: 3075 case ARM::VST2d16wb_register: 3076 case ARM::VST2d32wb_register: 3077 case ARM::VST2q8wb_fixed: 3078 case ARM::VST2q16wb_fixed: 3079 case ARM::VST2q32wb_fixed: 3080 case ARM::VST2q8wb_register: 3081 case ARM::VST2q16wb_register: 3082 case ARM::VST2q32wb_register: 3083 case ARM::VST2b8wb_fixed: 3084 case ARM::VST2b16wb_fixed: 3085 case ARM::VST2b32wb_fixed: 3086 case ARM::VST2b8wb_register: 3087 case ARM::VST2b16wb_register: 3088 case ARM::VST2b32wb_register: 3089 if (Rm == 0xF) 3090 return MCDisassembler::Fail; 3091 Inst.addOperand(MCOperand::createImm(0)); 3092 break; 3093 case ARM::VST3d8_UPD: 3094 case ARM::VST3d16_UPD: 3095 case ARM::VST3d32_UPD: 3096 case ARM::VST3q8_UPD: 3097 case ARM::VST3q16_UPD: 3098 case ARM::VST3q32_UPD: 3099 case ARM::VST4d8_UPD: 3100 case ARM::VST4d16_UPD: 3101 case ARM::VST4d32_UPD: 3102 case ARM::VST4q8_UPD: 3103 case ARM::VST4q16_UPD: 3104 case ARM::VST4q32_UPD: 3105 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 break; 3108 default: 3109 break; 3110 } 3111 3112 // AddrMode6 Base (register+alignment) 3113 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3114 return MCDisassembler::Fail; 3115 3116 // AddrMode6 Offset (register) 3117 switch (Inst.getOpcode()) { 3118 default: 3119 if (Rm == 0xD) 3120 Inst.addOperand(MCOperand::createReg(0)); 3121 else if (Rm != 0xF) { 3122 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3123 return MCDisassembler::Fail; 3124 } 3125 break; 3126 case ARM::VST1d8wb_fixed: 3127 case ARM::VST1d16wb_fixed: 3128 case ARM::VST1d32wb_fixed: 3129 case ARM::VST1d64wb_fixed: 3130 case ARM::VST1q8wb_fixed: 3131 case ARM::VST1q16wb_fixed: 3132 case ARM::VST1q32wb_fixed: 3133 case ARM::VST1q64wb_fixed: 3134 case ARM::VST1d8Twb_fixed: 3135 case ARM::VST1d16Twb_fixed: 3136 case ARM::VST1d32Twb_fixed: 3137 case ARM::VST1d64Twb_fixed: 3138 case ARM::VST1d8Qwb_fixed: 3139 case ARM::VST1d16Qwb_fixed: 3140 case ARM::VST1d32Qwb_fixed: 3141 case ARM::VST1d64Qwb_fixed: 3142 case ARM::VST2d8wb_fixed: 3143 case ARM::VST2d16wb_fixed: 3144 case ARM::VST2d32wb_fixed: 3145 case ARM::VST2q8wb_fixed: 3146 case ARM::VST2q16wb_fixed: 3147 case ARM::VST2q32wb_fixed: 3148 case ARM::VST2b8wb_fixed: 3149 case ARM::VST2b16wb_fixed: 3150 case ARM::VST2b32wb_fixed: 3151 break; 3152 } 3153 3154 // First input register 3155 switch (Inst.getOpcode()) { 3156 case ARM::VST1q16: 3157 case ARM::VST1q32: 3158 case ARM::VST1q64: 3159 case ARM::VST1q8: 3160 case ARM::VST1q16wb_fixed: 3161 case ARM::VST1q16wb_register: 3162 case ARM::VST1q32wb_fixed: 3163 case ARM::VST1q32wb_register: 3164 case ARM::VST1q64wb_fixed: 3165 case ARM::VST1q64wb_register: 3166 case ARM::VST1q8wb_fixed: 3167 case ARM::VST1q8wb_register: 3168 case ARM::VST2d16: 3169 case ARM::VST2d32: 3170 case ARM::VST2d8: 3171 case ARM::VST2d16wb_fixed: 3172 case ARM::VST2d16wb_register: 3173 case ARM::VST2d32wb_fixed: 3174 case ARM::VST2d32wb_register: 3175 case ARM::VST2d8wb_fixed: 3176 case ARM::VST2d8wb_register: 3177 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3178 return MCDisassembler::Fail; 3179 break; 3180 case ARM::VST2b16: 3181 case ARM::VST2b32: 3182 case ARM::VST2b8: 3183 case ARM::VST2b16wb_fixed: 3184 case ARM::VST2b16wb_register: 3185 case ARM::VST2b32wb_fixed: 3186 case ARM::VST2b32wb_register: 3187 case ARM::VST2b8wb_fixed: 3188 case ARM::VST2b8wb_register: 3189 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 break; 3192 default: 3193 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3194 return MCDisassembler::Fail; 3195 } 3196 3197 // Second input register 3198 switch (Inst.getOpcode()) { 3199 case ARM::VST3d8: 3200 case ARM::VST3d16: 3201 case ARM::VST3d32: 3202 case ARM::VST3d8_UPD: 3203 case ARM::VST3d16_UPD: 3204 case ARM::VST3d32_UPD: 3205 case ARM::VST4d8: 3206 case ARM::VST4d16: 3207 case ARM::VST4d32: 3208 case ARM::VST4d8_UPD: 3209 case ARM::VST4d16_UPD: 3210 case ARM::VST4d32_UPD: 3211 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3212 return MCDisassembler::Fail; 3213 break; 3214 case ARM::VST3q8: 3215 case ARM::VST3q16: 3216 case ARM::VST3q32: 3217 case ARM::VST3q8_UPD: 3218 case ARM::VST3q16_UPD: 3219 case ARM::VST3q32_UPD: 3220 case ARM::VST4q8: 3221 case ARM::VST4q16: 3222 case ARM::VST4q32: 3223 case ARM::VST4q8_UPD: 3224 case ARM::VST4q16_UPD: 3225 case ARM::VST4q32_UPD: 3226 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3227 return MCDisassembler::Fail; 3228 break; 3229 default: 3230 break; 3231 } 3232 3233 // Third input register 3234 switch (Inst.getOpcode()) { 3235 case ARM::VST3d8: 3236 case ARM::VST3d16: 3237 case ARM::VST3d32: 3238 case ARM::VST3d8_UPD: 3239 case ARM::VST3d16_UPD: 3240 case ARM::VST3d32_UPD: 3241 case ARM::VST4d8: 3242 case ARM::VST4d16: 3243 case ARM::VST4d32: 3244 case ARM::VST4d8_UPD: 3245 case ARM::VST4d16_UPD: 3246 case ARM::VST4d32_UPD: 3247 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3248 return MCDisassembler::Fail; 3249 break; 3250 case ARM::VST3q8: 3251 case ARM::VST3q16: 3252 case ARM::VST3q32: 3253 case ARM::VST3q8_UPD: 3254 case ARM::VST3q16_UPD: 3255 case ARM::VST3q32_UPD: 3256 case ARM::VST4q8: 3257 case ARM::VST4q16: 3258 case ARM::VST4q32: 3259 case ARM::VST4q8_UPD: 3260 case ARM::VST4q16_UPD: 3261 case ARM::VST4q32_UPD: 3262 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3263 return MCDisassembler::Fail; 3264 break; 3265 default: 3266 break; 3267 } 3268 3269 // Fourth input register 3270 switch (Inst.getOpcode()) { 3271 case ARM::VST4d8: 3272 case ARM::VST4d16: 3273 case ARM::VST4d32: 3274 case ARM::VST4d8_UPD: 3275 case ARM::VST4d16_UPD: 3276 case ARM::VST4d32_UPD: 3277 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3278 return MCDisassembler::Fail; 3279 break; 3280 case ARM::VST4q8: 3281 case ARM::VST4q16: 3282 case ARM::VST4q32: 3283 case ARM::VST4q8_UPD: 3284 case ARM::VST4q16_UPD: 3285 case ARM::VST4q32_UPD: 3286 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3287 return MCDisassembler::Fail; 3288 break; 3289 default: 3290 break; 3291 } 3292 3293 return S; 3294 } 3295 3296 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3297 uint64_t Address, const void *Decoder) { 3298 DecodeStatus S = MCDisassembler::Success; 3299 3300 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3301 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3302 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3303 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3304 unsigned align = fieldFromInstruction(Insn, 4, 1); 3305 unsigned size = fieldFromInstruction(Insn, 6, 2); 3306 3307 if (size == 0 && align == 1) 3308 return MCDisassembler::Fail; 3309 align *= (1 << size); 3310 3311 switch (Inst.getOpcode()) { 3312 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3313 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3314 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3315 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3316 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3317 return MCDisassembler::Fail; 3318 break; 3319 default: 3320 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3321 return MCDisassembler::Fail; 3322 break; 3323 } 3324 if (Rm != 0xF) { 3325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 } 3328 3329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3330 return MCDisassembler::Fail; 3331 Inst.addOperand(MCOperand::createImm(align)); 3332 3333 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3334 // variant encodes Rm == 0xf. Anything else is a register offset post- 3335 // increment and we need to add the register operand to the instruction. 3336 if (Rm != 0xD && Rm != 0xF && 3337 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3338 return MCDisassembler::Fail; 3339 3340 return S; 3341 } 3342 3343 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3344 uint64_t Address, const void *Decoder) { 3345 DecodeStatus S = MCDisassembler::Success; 3346 3347 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3348 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3349 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3350 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3351 unsigned align = fieldFromInstruction(Insn, 4, 1); 3352 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3353 align *= 2*size; 3354 3355 switch (Inst.getOpcode()) { 3356 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3357 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3358 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3359 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3360 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3361 return MCDisassembler::Fail; 3362 break; 3363 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3364 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3365 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3366 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3367 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3368 return MCDisassembler::Fail; 3369 break; 3370 default: 3371 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3372 return MCDisassembler::Fail; 3373 break; 3374 } 3375 3376 if (Rm != 0xF) 3377 Inst.addOperand(MCOperand::createImm(0)); 3378 3379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3380 return MCDisassembler::Fail; 3381 Inst.addOperand(MCOperand::createImm(align)); 3382 3383 if (Rm != 0xD && Rm != 0xF) { 3384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3385 return MCDisassembler::Fail; 3386 } 3387 3388 return S; 3389 } 3390 3391 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3392 uint64_t Address, const void *Decoder) { 3393 DecodeStatus S = MCDisassembler::Success; 3394 3395 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3396 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3397 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3398 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3399 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3400 3401 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3402 return MCDisassembler::Fail; 3403 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3404 return MCDisassembler::Fail; 3405 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3406 return MCDisassembler::Fail; 3407 if (Rm != 0xF) { 3408 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 } 3411 3412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3413 return MCDisassembler::Fail; 3414 Inst.addOperand(MCOperand::createImm(0)); 3415 3416 if (Rm == 0xD) 3417 Inst.addOperand(MCOperand::createReg(0)); 3418 else if (Rm != 0xF) { 3419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3420 return MCDisassembler::Fail; 3421 } 3422 3423 return S; 3424 } 3425 3426 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3427 uint64_t Address, const void *Decoder) { 3428 DecodeStatus S = MCDisassembler::Success; 3429 3430 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3431 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3432 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3433 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3434 unsigned size = fieldFromInstruction(Insn, 6, 2); 3435 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3436 unsigned align = fieldFromInstruction(Insn, 4, 1); 3437 3438 if (size == 0x3) { 3439 if (align == 0) 3440 return MCDisassembler::Fail; 3441 align = 16; 3442 } else { 3443 if (size == 2) { 3444 align *= 8; 3445 } else { 3446 size = 1 << size; 3447 align *= 4*size; 3448 } 3449 } 3450 3451 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3452 return MCDisassembler::Fail; 3453 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3454 return MCDisassembler::Fail; 3455 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3456 return MCDisassembler::Fail; 3457 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3458 return MCDisassembler::Fail; 3459 if (Rm != 0xF) { 3460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 } 3463 3464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 Inst.addOperand(MCOperand::createImm(align)); 3467 3468 if (Rm == 0xD) 3469 Inst.addOperand(MCOperand::createReg(0)); 3470 else if (Rm != 0xF) { 3471 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3472 return MCDisassembler::Fail; 3473 } 3474 3475 return S; 3476 } 3477 3478 static DecodeStatus 3479 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3480 uint64_t Address, const void *Decoder) { 3481 DecodeStatus S = MCDisassembler::Success; 3482 3483 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3484 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3485 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3486 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3487 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3488 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3489 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3490 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3491 3492 if (Q) { 3493 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3494 return MCDisassembler::Fail; 3495 } else { 3496 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3497 return MCDisassembler::Fail; 3498 } 3499 3500 Inst.addOperand(MCOperand::createImm(imm)); 3501 3502 switch (Inst.getOpcode()) { 3503 case ARM::VORRiv4i16: 3504 case ARM::VORRiv2i32: 3505 case ARM::VBICiv4i16: 3506 case ARM::VBICiv2i32: 3507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 break; 3510 case ARM::VORRiv8i16: 3511 case ARM::VORRiv4i32: 3512 case ARM::VBICiv8i16: 3513 case ARM::VBICiv4i32: 3514 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3515 return MCDisassembler::Fail; 3516 break; 3517 default: 3518 break; 3519 } 3520 3521 return S; 3522 } 3523 3524 static DecodeStatus 3525 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3526 uint64_t Address, const void *Decoder) { 3527 DecodeStatus S = MCDisassembler::Success; 3528 3529 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3530 fieldFromInstruction(Insn, 13, 3)); 3531 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3532 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3533 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3534 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3535 imm |= cmode << 8; 3536 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3537 3538 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3539 return MCDisassembler::Fail; 3540 3541 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3542 return MCDisassembler::Fail; 3543 3544 Inst.addOperand(MCOperand::createImm(imm)); 3545 3546 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3547 Inst.addOperand(MCOperand::createReg(0)); 3548 Inst.addOperand(MCOperand::createImm(0)); 3549 3550 return S; 3551 } 3552 3553 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3554 uint64_t Address, const void *Decoder) { 3555 DecodeStatus S = MCDisassembler::Success; 3556 3557 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3558 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3559 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3562 3563 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3564 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3565 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3566 return MCDisassembler::Fail; 3567 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3568 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3569 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3570 return MCDisassembler::Fail; 3571 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3572 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3573 Inst.addOperand(MCOperand::createImm(Qd)); 3574 3575 return S; 3576 } 3577 3578 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3579 uint64_t Address, const void *Decoder) { 3580 DecodeStatus S = MCDisassembler::Success; 3581 3582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3583 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3584 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3585 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3586 unsigned size = fieldFromInstruction(Insn, 18, 2); 3587 3588 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3589 return MCDisassembler::Fail; 3590 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3591 return MCDisassembler::Fail; 3592 Inst.addOperand(MCOperand::createImm(8 << size)); 3593 3594 return S; 3595 } 3596 3597 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3598 uint64_t Address, const void *Decoder) { 3599 Inst.addOperand(MCOperand::createImm(8 - Val)); 3600 return MCDisassembler::Success; 3601 } 3602 3603 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3604 uint64_t Address, const void *Decoder) { 3605 Inst.addOperand(MCOperand::createImm(16 - Val)); 3606 return MCDisassembler::Success; 3607 } 3608 3609 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3610 uint64_t Address, const void *Decoder) { 3611 Inst.addOperand(MCOperand::createImm(32 - Val)); 3612 return MCDisassembler::Success; 3613 } 3614 3615 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3616 uint64_t Address, const void *Decoder) { 3617 Inst.addOperand(MCOperand::createImm(64 - Val)); 3618 return MCDisassembler::Success; 3619 } 3620 3621 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3622 uint64_t Address, const void *Decoder) { 3623 DecodeStatus S = MCDisassembler::Success; 3624 3625 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3626 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3627 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3628 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3629 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3630 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3631 unsigned op = fieldFromInstruction(Insn, 6, 1); 3632 3633 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 if (op) { 3636 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3637 return MCDisassembler::Fail; // Writeback 3638 } 3639 3640 switch (Inst.getOpcode()) { 3641 case ARM::VTBL2: 3642 case ARM::VTBX2: 3643 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3644 return MCDisassembler::Fail; 3645 break; 3646 default: 3647 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3648 return MCDisassembler::Fail; 3649 } 3650 3651 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3652 return MCDisassembler::Fail; 3653 3654 return S; 3655 } 3656 3657 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3658 uint64_t Address, const void *Decoder) { 3659 DecodeStatus S = MCDisassembler::Success; 3660 3661 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3662 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3663 3664 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3665 return MCDisassembler::Fail; 3666 3667 switch(Inst.getOpcode()) { 3668 default: 3669 return MCDisassembler::Fail; 3670 case ARM::tADR: 3671 break; // tADR does not explicitly represent the PC as an operand. 3672 case ARM::tADDrSPi: 3673 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3674 break; 3675 } 3676 3677 Inst.addOperand(MCOperand::createImm(imm)); 3678 return S; 3679 } 3680 3681 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3682 uint64_t Address, const void *Decoder) { 3683 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3684 true, 2, Inst, Decoder)) 3685 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3686 return MCDisassembler::Success; 3687 } 3688 3689 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3690 uint64_t Address, const void *Decoder) { 3691 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3692 true, 4, Inst, Decoder)) 3693 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3694 return MCDisassembler::Success; 3695 } 3696 3697 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3698 uint64_t Address, const void *Decoder) { 3699 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3700 true, 2, Inst, Decoder)) 3701 Inst.addOperand(MCOperand::createImm(Val << 1)); 3702 return MCDisassembler::Success; 3703 } 3704 3705 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3706 uint64_t Address, const void *Decoder) { 3707 DecodeStatus S = MCDisassembler::Success; 3708 3709 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3710 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3711 3712 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3713 return MCDisassembler::Fail; 3714 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3715 return MCDisassembler::Fail; 3716 3717 return S; 3718 } 3719 3720 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3721 uint64_t Address, const void *Decoder) { 3722 DecodeStatus S = MCDisassembler::Success; 3723 3724 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3725 unsigned imm = fieldFromInstruction(Val, 3, 5); 3726 3727 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3728 return MCDisassembler::Fail; 3729 Inst.addOperand(MCOperand::createImm(imm)); 3730 3731 return S; 3732 } 3733 3734 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3735 uint64_t Address, const void *Decoder) { 3736 unsigned imm = Val << 2; 3737 3738 Inst.addOperand(MCOperand::createImm(imm)); 3739 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3740 3741 return MCDisassembler::Success; 3742 } 3743 3744 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3745 uint64_t Address, const void *Decoder) { 3746 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3747 Inst.addOperand(MCOperand::createImm(Val)); 3748 3749 return MCDisassembler::Success; 3750 } 3751 3752 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3753 uint64_t Address, const void *Decoder) { 3754 DecodeStatus S = MCDisassembler::Success; 3755 3756 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3757 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3758 unsigned imm = fieldFromInstruction(Val, 0, 2); 3759 3760 // Thumb stores cannot use PC as dest register. 3761 switch (Inst.getOpcode()) { 3762 case ARM::t2STRHs: 3763 case ARM::t2STRBs: 3764 case ARM::t2STRs: 3765 if (Rn == 15) 3766 return MCDisassembler::Fail; 3767 break; 3768 default: 3769 break; 3770 } 3771 3772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3773 return MCDisassembler::Fail; 3774 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3775 return MCDisassembler::Fail; 3776 Inst.addOperand(MCOperand::createImm(imm)); 3777 3778 return S; 3779 } 3780 3781 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3782 uint64_t Address, const void *Decoder) { 3783 DecodeStatus S = MCDisassembler::Success; 3784 3785 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3786 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3787 3788 const FeatureBitset &featureBits = 3789 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3790 3791 bool hasMP = featureBits[ARM::FeatureMP]; 3792 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3793 3794 if (Rn == 15) { 3795 switch (Inst.getOpcode()) { 3796 case ARM::t2LDRBs: 3797 Inst.setOpcode(ARM::t2LDRBpci); 3798 break; 3799 case ARM::t2LDRHs: 3800 Inst.setOpcode(ARM::t2LDRHpci); 3801 break; 3802 case ARM::t2LDRSHs: 3803 Inst.setOpcode(ARM::t2LDRSHpci); 3804 break; 3805 case ARM::t2LDRSBs: 3806 Inst.setOpcode(ARM::t2LDRSBpci); 3807 break; 3808 case ARM::t2LDRs: 3809 Inst.setOpcode(ARM::t2LDRpci); 3810 break; 3811 case ARM::t2PLDs: 3812 Inst.setOpcode(ARM::t2PLDpci); 3813 break; 3814 case ARM::t2PLIs: 3815 Inst.setOpcode(ARM::t2PLIpci); 3816 break; 3817 default: 3818 return MCDisassembler::Fail; 3819 } 3820 3821 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3822 } 3823 3824 if (Rt == 15) { 3825 switch (Inst.getOpcode()) { 3826 case ARM::t2LDRSHs: 3827 return MCDisassembler::Fail; 3828 case ARM::t2LDRHs: 3829 Inst.setOpcode(ARM::t2PLDWs); 3830 break; 3831 case ARM::t2LDRSBs: 3832 Inst.setOpcode(ARM::t2PLIs); 3833 break; 3834 default: 3835 break; 3836 } 3837 } 3838 3839 switch (Inst.getOpcode()) { 3840 case ARM::t2PLDs: 3841 break; 3842 case ARM::t2PLIs: 3843 if (!hasV7Ops) 3844 return MCDisassembler::Fail; 3845 break; 3846 case ARM::t2PLDWs: 3847 if (!hasV7Ops || !hasMP) 3848 return MCDisassembler::Fail; 3849 break; 3850 default: 3851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3852 return MCDisassembler::Fail; 3853 } 3854 3855 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3856 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3857 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3858 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3859 return MCDisassembler::Fail; 3860 3861 return S; 3862 } 3863 3864 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3865 uint64_t Address, const void* Decoder) { 3866 DecodeStatus S = MCDisassembler::Success; 3867 3868 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3869 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3870 unsigned U = fieldFromInstruction(Insn, 9, 1); 3871 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3872 imm |= (U << 8); 3873 imm |= (Rn << 9); 3874 unsigned add = fieldFromInstruction(Insn, 9, 1); 3875 3876 const FeatureBitset &featureBits = 3877 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3878 3879 bool hasMP = featureBits[ARM::FeatureMP]; 3880 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3881 3882 if (Rn == 15) { 3883 switch (Inst.getOpcode()) { 3884 case ARM::t2LDRi8: 3885 Inst.setOpcode(ARM::t2LDRpci); 3886 break; 3887 case ARM::t2LDRBi8: 3888 Inst.setOpcode(ARM::t2LDRBpci); 3889 break; 3890 case ARM::t2LDRSBi8: 3891 Inst.setOpcode(ARM::t2LDRSBpci); 3892 break; 3893 case ARM::t2LDRHi8: 3894 Inst.setOpcode(ARM::t2LDRHpci); 3895 break; 3896 case ARM::t2LDRSHi8: 3897 Inst.setOpcode(ARM::t2LDRSHpci); 3898 break; 3899 case ARM::t2PLDi8: 3900 Inst.setOpcode(ARM::t2PLDpci); 3901 break; 3902 case ARM::t2PLIi8: 3903 Inst.setOpcode(ARM::t2PLIpci); 3904 break; 3905 default: 3906 return MCDisassembler::Fail; 3907 } 3908 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3909 } 3910 3911 if (Rt == 15) { 3912 switch (Inst.getOpcode()) { 3913 case ARM::t2LDRSHi8: 3914 return MCDisassembler::Fail; 3915 case ARM::t2LDRHi8: 3916 if (!add) 3917 Inst.setOpcode(ARM::t2PLDWi8); 3918 break; 3919 case ARM::t2LDRSBi8: 3920 Inst.setOpcode(ARM::t2PLIi8); 3921 break; 3922 default: 3923 break; 3924 } 3925 } 3926 3927 switch (Inst.getOpcode()) { 3928 case ARM::t2PLDi8: 3929 break; 3930 case ARM::t2PLIi8: 3931 if (!hasV7Ops) 3932 return MCDisassembler::Fail; 3933 break; 3934 case ARM::t2PLDWi8: 3935 if (!hasV7Ops || !hasMP) 3936 return MCDisassembler::Fail; 3937 break; 3938 default: 3939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3940 return MCDisassembler::Fail; 3941 } 3942 3943 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3944 return MCDisassembler::Fail; 3945 return S; 3946 } 3947 3948 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3949 uint64_t Address, const void* Decoder) { 3950 DecodeStatus S = MCDisassembler::Success; 3951 3952 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3953 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3954 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3955 imm |= (Rn << 13); 3956 3957 const FeatureBitset &featureBits = 3958 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3959 3960 bool hasMP = featureBits[ARM::FeatureMP]; 3961 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3962 3963 if (Rn == 15) { 3964 switch (Inst.getOpcode()) { 3965 case ARM::t2LDRi12: 3966 Inst.setOpcode(ARM::t2LDRpci); 3967 break; 3968 case ARM::t2LDRHi12: 3969 Inst.setOpcode(ARM::t2LDRHpci); 3970 break; 3971 case ARM::t2LDRSHi12: 3972 Inst.setOpcode(ARM::t2LDRSHpci); 3973 break; 3974 case ARM::t2LDRBi12: 3975 Inst.setOpcode(ARM::t2LDRBpci); 3976 break; 3977 case ARM::t2LDRSBi12: 3978 Inst.setOpcode(ARM::t2LDRSBpci); 3979 break; 3980 case ARM::t2PLDi12: 3981 Inst.setOpcode(ARM::t2PLDpci); 3982 break; 3983 case ARM::t2PLIi12: 3984 Inst.setOpcode(ARM::t2PLIpci); 3985 break; 3986 default: 3987 return MCDisassembler::Fail; 3988 } 3989 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3990 } 3991 3992 if (Rt == 15) { 3993 switch (Inst.getOpcode()) { 3994 case ARM::t2LDRSHi12: 3995 return MCDisassembler::Fail; 3996 case ARM::t2LDRHi12: 3997 Inst.setOpcode(ARM::t2PLDWi12); 3998 break; 3999 case ARM::t2LDRSBi12: 4000 Inst.setOpcode(ARM::t2PLIi12); 4001 break; 4002 default: 4003 break; 4004 } 4005 } 4006 4007 switch (Inst.getOpcode()) { 4008 case ARM::t2PLDi12: 4009 break; 4010 case ARM::t2PLIi12: 4011 if (!hasV7Ops) 4012 return MCDisassembler::Fail; 4013 break; 4014 case ARM::t2PLDWi12: 4015 if (!hasV7Ops || !hasMP) 4016 return MCDisassembler::Fail; 4017 break; 4018 default: 4019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 } 4022 4023 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4024 return MCDisassembler::Fail; 4025 return S; 4026 } 4027 4028 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4029 uint64_t Address, const void* Decoder) { 4030 DecodeStatus S = MCDisassembler::Success; 4031 4032 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4033 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4034 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4035 imm |= (Rn << 9); 4036 4037 if (Rn == 15) { 4038 switch (Inst.getOpcode()) { 4039 case ARM::t2LDRT: 4040 Inst.setOpcode(ARM::t2LDRpci); 4041 break; 4042 case ARM::t2LDRBT: 4043 Inst.setOpcode(ARM::t2LDRBpci); 4044 break; 4045 case ARM::t2LDRHT: 4046 Inst.setOpcode(ARM::t2LDRHpci); 4047 break; 4048 case ARM::t2LDRSBT: 4049 Inst.setOpcode(ARM::t2LDRSBpci); 4050 break; 4051 case ARM::t2LDRSHT: 4052 Inst.setOpcode(ARM::t2LDRSHpci); 4053 break; 4054 default: 4055 return MCDisassembler::Fail; 4056 } 4057 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4058 } 4059 4060 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4061 return MCDisassembler::Fail; 4062 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4063 return MCDisassembler::Fail; 4064 return S; 4065 } 4066 4067 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4068 uint64_t Address, const void* Decoder) { 4069 DecodeStatus S = MCDisassembler::Success; 4070 4071 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4072 unsigned U = fieldFromInstruction(Insn, 23, 1); 4073 int imm = fieldFromInstruction(Insn, 0, 12); 4074 4075 const FeatureBitset &featureBits = 4076 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4077 4078 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4079 4080 if (Rt == 15) { 4081 switch (Inst.getOpcode()) { 4082 case ARM::t2LDRBpci: 4083 case ARM::t2LDRHpci: 4084 Inst.setOpcode(ARM::t2PLDpci); 4085 break; 4086 case ARM::t2LDRSBpci: 4087 Inst.setOpcode(ARM::t2PLIpci); 4088 break; 4089 case ARM::t2LDRSHpci: 4090 return MCDisassembler::Fail; 4091 default: 4092 break; 4093 } 4094 } 4095 4096 switch(Inst.getOpcode()) { 4097 case ARM::t2PLDpci: 4098 break; 4099 case ARM::t2PLIpci: 4100 if (!hasV7Ops) 4101 return MCDisassembler::Fail; 4102 break; 4103 default: 4104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4105 return MCDisassembler::Fail; 4106 } 4107 4108 if (!U) { 4109 // Special case for #-0. 4110 if (imm == 0) 4111 imm = INT32_MIN; 4112 else 4113 imm = -imm; 4114 } 4115 Inst.addOperand(MCOperand::createImm(imm)); 4116 4117 return S; 4118 } 4119 4120 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4121 uint64_t Address, const void *Decoder) { 4122 if (Val == 0) 4123 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4124 else { 4125 int imm = Val & 0xFF; 4126 4127 if (!(Val & 0x100)) imm *= -1; 4128 Inst.addOperand(MCOperand::createImm(imm * 4)); 4129 } 4130 4131 return MCDisassembler::Success; 4132 } 4133 4134 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4135 const void *Decoder) { 4136 if (Val == 0) 4137 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4138 else { 4139 int imm = Val & 0x7F; 4140 4141 if (!(Val & 0x80)) 4142 imm *= -1; 4143 Inst.addOperand(MCOperand::createImm(imm * 4)); 4144 } 4145 4146 return MCDisassembler::Success; 4147 } 4148 4149 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4150 uint64_t Address, const void *Decoder) { 4151 DecodeStatus S = MCDisassembler::Success; 4152 4153 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4154 unsigned imm = fieldFromInstruction(Val, 0, 9); 4155 4156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4157 return MCDisassembler::Fail; 4158 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4159 return MCDisassembler::Fail; 4160 4161 return S; 4162 } 4163 4164 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4165 uint64_t Address, 4166 const void *Decoder) { 4167 DecodeStatus S = MCDisassembler::Success; 4168 4169 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4170 unsigned imm = fieldFromInstruction(Val, 0, 8); 4171 4172 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4173 return MCDisassembler::Fail; 4174 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4175 return MCDisassembler::Fail; 4176 4177 return S; 4178 } 4179 4180 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4181 uint64_t Address, const void *Decoder) { 4182 DecodeStatus S = MCDisassembler::Success; 4183 4184 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4185 unsigned imm = fieldFromInstruction(Val, 0, 8); 4186 4187 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4188 return MCDisassembler::Fail; 4189 4190 Inst.addOperand(MCOperand::createImm(imm)); 4191 4192 return S; 4193 } 4194 4195 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4196 uint64_t Address, const void *Decoder) { 4197 int imm = Val & 0xFF; 4198 if (Val == 0) 4199 imm = INT32_MIN; 4200 else if (!(Val & 0x100)) 4201 imm *= -1; 4202 Inst.addOperand(MCOperand::createImm(imm)); 4203 4204 return MCDisassembler::Success; 4205 } 4206 4207 template<int shift> 4208 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4209 uint64_t Address, const void *Decoder) { 4210 int imm = Val & 0x7F; 4211 if (Val == 0) 4212 imm = INT32_MIN; 4213 else if (!(Val & 0x80)) 4214 imm *= -1; 4215 if (imm != INT32_MIN) 4216 imm *= (1U << shift); 4217 Inst.addOperand(MCOperand::createImm(imm)); 4218 4219 return MCDisassembler::Success; 4220 } 4221 4222 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4223 uint64_t Address, const void *Decoder) { 4224 DecodeStatus S = MCDisassembler::Success; 4225 4226 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4227 unsigned imm = fieldFromInstruction(Val, 0, 9); 4228 4229 // Thumb stores cannot use PC as dest register. 4230 switch (Inst.getOpcode()) { 4231 case ARM::t2STRT: 4232 case ARM::t2STRBT: 4233 case ARM::t2STRHT: 4234 case ARM::t2STRi8: 4235 case ARM::t2STRHi8: 4236 case ARM::t2STRBi8: 4237 if (Rn == 15) 4238 return MCDisassembler::Fail; 4239 break; 4240 default: 4241 break; 4242 } 4243 4244 // Some instructions always use an additive offset. 4245 switch (Inst.getOpcode()) { 4246 case ARM::t2LDRT: 4247 case ARM::t2LDRBT: 4248 case ARM::t2LDRHT: 4249 case ARM::t2LDRSBT: 4250 case ARM::t2LDRSHT: 4251 case ARM::t2STRT: 4252 case ARM::t2STRBT: 4253 case ARM::t2STRHT: 4254 imm |= 0x100; 4255 break; 4256 default: 4257 break; 4258 } 4259 4260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4261 return MCDisassembler::Fail; 4262 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4263 return MCDisassembler::Fail; 4264 4265 return S; 4266 } 4267 4268 template<int shift> 4269 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4270 uint64_t Address, 4271 const void *Decoder) { 4272 DecodeStatus S = MCDisassembler::Success; 4273 4274 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4275 unsigned imm = fieldFromInstruction(Val, 0, 8); 4276 4277 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4278 return MCDisassembler::Fail; 4279 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4280 return MCDisassembler::Fail; 4281 4282 return S; 4283 } 4284 4285 template<int shift, int WriteBack> 4286 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4287 uint64_t Address, 4288 const void *Decoder) { 4289 DecodeStatus S = MCDisassembler::Success; 4290 4291 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4292 unsigned imm = fieldFromInstruction(Val, 0, 8); 4293 if (WriteBack) { 4294 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4297 return MCDisassembler::Fail; 4298 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4299 return MCDisassembler::Fail; 4300 4301 return S; 4302 } 4303 4304 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4305 uint64_t Address, const void *Decoder) { 4306 DecodeStatus S = MCDisassembler::Success; 4307 4308 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4309 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4310 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4311 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4312 addr |= Rn << 9; 4313 unsigned load = fieldFromInstruction(Insn, 20, 1); 4314 4315 if (Rn == 15) { 4316 switch (Inst.getOpcode()) { 4317 case ARM::t2LDR_PRE: 4318 case ARM::t2LDR_POST: 4319 Inst.setOpcode(ARM::t2LDRpci); 4320 break; 4321 case ARM::t2LDRB_PRE: 4322 case ARM::t2LDRB_POST: 4323 Inst.setOpcode(ARM::t2LDRBpci); 4324 break; 4325 case ARM::t2LDRH_PRE: 4326 case ARM::t2LDRH_POST: 4327 Inst.setOpcode(ARM::t2LDRHpci); 4328 break; 4329 case ARM::t2LDRSB_PRE: 4330 case ARM::t2LDRSB_POST: 4331 if (Rt == 15) 4332 Inst.setOpcode(ARM::t2PLIpci); 4333 else 4334 Inst.setOpcode(ARM::t2LDRSBpci); 4335 break; 4336 case ARM::t2LDRSH_PRE: 4337 case ARM::t2LDRSH_POST: 4338 Inst.setOpcode(ARM::t2LDRSHpci); 4339 break; 4340 default: 4341 return MCDisassembler::Fail; 4342 } 4343 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4344 } 4345 4346 if (!load) { 4347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4348 return MCDisassembler::Fail; 4349 } 4350 4351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4352 return MCDisassembler::Fail; 4353 4354 if (load) { 4355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4356 return MCDisassembler::Fail; 4357 } 4358 4359 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4360 return MCDisassembler::Fail; 4361 4362 return S; 4363 } 4364 4365 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4366 uint64_t Address, const void *Decoder) { 4367 DecodeStatus S = MCDisassembler::Success; 4368 4369 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4370 unsigned imm = fieldFromInstruction(Val, 0, 12); 4371 4372 // Thumb stores cannot use PC as dest register. 4373 switch (Inst.getOpcode()) { 4374 case ARM::t2STRi12: 4375 case ARM::t2STRBi12: 4376 case ARM::t2STRHi12: 4377 if (Rn == 15) 4378 return MCDisassembler::Fail; 4379 break; 4380 default: 4381 break; 4382 } 4383 4384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4385 return MCDisassembler::Fail; 4386 Inst.addOperand(MCOperand::createImm(imm)); 4387 4388 return S; 4389 } 4390 4391 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4392 uint64_t Address, const void *Decoder) { 4393 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4394 4395 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4396 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4397 Inst.addOperand(MCOperand::createImm(imm)); 4398 4399 return MCDisassembler::Success; 4400 } 4401 4402 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4403 uint64_t Address, const void *Decoder) { 4404 DecodeStatus S = MCDisassembler::Success; 4405 4406 if (Inst.getOpcode() == ARM::tADDrSP) { 4407 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4408 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4409 4410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4411 return MCDisassembler::Fail; 4412 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4414 return MCDisassembler::Fail; 4415 } else if (Inst.getOpcode() == ARM::tADDspr) { 4416 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4417 4418 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4419 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4421 return MCDisassembler::Fail; 4422 } 4423 4424 return S; 4425 } 4426 4427 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4428 uint64_t Address, const void *Decoder) { 4429 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4430 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4431 4432 Inst.addOperand(MCOperand::createImm(imod)); 4433 Inst.addOperand(MCOperand::createImm(flags)); 4434 4435 return MCDisassembler::Success; 4436 } 4437 4438 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4439 uint64_t Address, const void *Decoder) { 4440 DecodeStatus S = MCDisassembler::Success; 4441 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4442 unsigned add = fieldFromInstruction(Insn, 4, 1); 4443 4444 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4445 return MCDisassembler::Fail; 4446 Inst.addOperand(MCOperand::createImm(add)); 4447 4448 return S; 4449 } 4450 4451 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4452 uint64_t Address, const void *Decoder) { 4453 DecodeStatus S = MCDisassembler::Success; 4454 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4455 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4456 4457 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4458 return MCDisassembler::Fail; 4459 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4460 return MCDisassembler::Fail; 4461 4462 return S; 4463 } 4464 4465 template<int shift> 4466 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4467 uint64_t Address, const void *Decoder) { 4468 DecodeStatus S = MCDisassembler::Success; 4469 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4470 int imm = fieldFromInstruction(Insn, 0, 7); 4471 4472 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4473 return MCDisassembler::Fail; 4474 4475 if(!fieldFromInstruction(Insn, 7, 1)) { 4476 if (imm == 0) 4477 imm = INT32_MIN; // indicate -0 4478 else 4479 imm *= -1; 4480 } 4481 if (imm != INT32_MIN) 4482 imm *= (1U << shift); 4483 Inst.addOperand(MCOperand::createImm(imm)); 4484 4485 return S; 4486 } 4487 4488 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4489 uint64_t Address, const void *Decoder) { 4490 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4491 // Note only one trailing zero not two. Also the J1 and J2 values are from 4492 // the encoded instruction. So here change to I1 and I2 values via: 4493 // I1 = NOT(J1 EOR S); 4494 // I2 = NOT(J2 EOR S); 4495 // and build the imm32 with two trailing zeros as documented: 4496 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4497 unsigned S = (Val >> 23) & 1; 4498 unsigned J1 = (Val >> 22) & 1; 4499 unsigned J2 = (Val >> 21) & 1; 4500 unsigned I1 = !(J1 ^ S); 4501 unsigned I2 = !(J2 ^ S); 4502 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4503 int imm32 = SignExtend32<25>(tmp << 1); 4504 4505 if (!tryAddingSymbolicOperand(Address, 4506 (Address & ~2u) + imm32 + 4, 4507 true, 4, Inst, Decoder)) 4508 Inst.addOperand(MCOperand::createImm(imm32)); 4509 return MCDisassembler::Success; 4510 } 4511 4512 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4513 uint64_t Address, const void *Decoder) { 4514 if (Val == 0xA || Val == 0xB) 4515 return MCDisassembler::Fail; 4516 4517 const FeatureBitset &featureBits = 4518 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4519 4520 if (!isValidCoprocessorNumber(Val, featureBits)) 4521 return MCDisassembler::Fail; 4522 4523 Inst.addOperand(MCOperand::createImm(Val)); 4524 return MCDisassembler::Success; 4525 } 4526 4527 static DecodeStatus 4528 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4529 uint64_t Address, const void *Decoder) { 4530 DecodeStatus S = MCDisassembler::Success; 4531 4532 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4533 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4534 4535 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4537 return MCDisassembler::Fail; 4538 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4539 return MCDisassembler::Fail; 4540 return S; 4541 } 4542 4543 static DecodeStatus 4544 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4545 uint64_t Address, const void *Decoder) { 4546 DecodeStatus S = MCDisassembler::Success; 4547 4548 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4549 if (pred == 0xE || pred == 0xF) { 4550 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4551 switch (opc) { 4552 default: 4553 return MCDisassembler::Fail; 4554 case 0xf3bf8f4: 4555 Inst.setOpcode(ARM::t2DSB); 4556 break; 4557 case 0xf3bf8f5: 4558 Inst.setOpcode(ARM::t2DMB); 4559 break; 4560 case 0xf3bf8f6: 4561 Inst.setOpcode(ARM::t2ISB); 4562 break; 4563 } 4564 4565 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4566 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4567 } 4568 4569 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4570 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4571 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4572 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4573 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4574 4575 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4576 return MCDisassembler::Fail; 4577 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4578 return MCDisassembler::Fail; 4579 4580 return S; 4581 } 4582 4583 // Decode a shifted immediate operand. These basically consist 4584 // of an 8-bit value, and a 4-bit directive that specifies either 4585 // a splat operation or a rotation. 4586 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4587 uint64_t Address, const void *Decoder) { 4588 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4589 if (ctrl == 0) { 4590 unsigned byte = fieldFromInstruction(Val, 8, 2); 4591 unsigned imm = fieldFromInstruction(Val, 0, 8); 4592 switch (byte) { 4593 case 0: 4594 Inst.addOperand(MCOperand::createImm(imm)); 4595 break; 4596 case 1: 4597 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4598 break; 4599 case 2: 4600 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4601 break; 4602 case 3: 4603 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4604 (imm << 8) | imm)); 4605 break; 4606 } 4607 } else { 4608 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4609 unsigned rot = fieldFromInstruction(Val, 7, 5); 4610 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4611 Inst.addOperand(MCOperand::createImm(imm)); 4612 } 4613 4614 return MCDisassembler::Success; 4615 } 4616 4617 static DecodeStatus 4618 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4619 uint64_t Address, const void *Decoder) { 4620 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4621 true, 2, Inst, Decoder)) 4622 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4623 return MCDisassembler::Success; 4624 } 4625 4626 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4627 uint64_t Address, 4628 const void *Decoder) { 4629 // Val is passed in as S:J1:J2:imm10:imm11 4630 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4631 // the encoded instruction. So here change to I1 and I2 values via: 4632 // I1 = NOT(J1 EOR S); 4633 // I2 = NOT(J2 EOR S); 4634 // and build the imm32 with one trailing zero as documented: 4635 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4636 unsigned S = (Val >> 23) & 1; 4637 unsigned J1 = (Val >> 22) & 1; 4638 unsigned J2 = (Val >> 21) & 1; 4639 unsigned I1 = !(J1 ^ S); 4640 unsigned I2 = !(J2 ^ S); 4641 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4642 int imm32 = SignExtend32<25>(tmp << 1); 4643 4644 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4645 true, 4, Inst, Decoder)) 4646 Inst.addOperand(MCOperand::createImm(imm32)); 4647 return MCDisassembler::Success; 4648 } 4649 4650 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4651 uint64_t Address, const void *Decoder) { 4652 if (Val & ~0xf) 4653 return MCDisassembler::Fail; 4654 4655 Inst.addOperand(MCOperand::createImm(Val)); 4656 return MCDisassembler::Success; 4657 } 4658 4659 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4660 uint64_t Address, const void *Decoder) { 4661 if (Val & ~0xf) 4662 return MCDisassembler::Fail; 4663 4664 Inst.addOperand(MCOperand::createImm(Val)); 4665 return MCDisassembler::Success; 4666 } 4667 4668 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4669 uint64_t Address, const void *Decoder) { 4670 DecodeStatus S = MCDisassembler::Success; 4671 const FeatureBitset &FeatureBits = 4672 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4673 4674 if (FeatureBits[ARM::FeatureMClass]) { 4675 unsigned ValLow = Val & 0xff; 4676 4677 // Validate the SYSm value first. 4678 switch (ValLow) { 4679 case 0: // apsr 4680 case 1: // iapsr 4681 case 2: // eapsr 4682 case 3: // xpsr 4683 case 5: // ipsr 4684 case 6: // epsr 4685 case 7: // iepsr 4686 case 8: // msp 4687 case 9: // psp 4688 case 16: // primask 4689 case 20: // control 4690 break; 4691 case 17: // basepri 4692 case 18: // basepri_max 4693 case 19: // faultmask 4694 if (!(FeatureBits[ARM::HasV7Ops])) 4695 // Values basepri, basepri_max and faultmask are only valid for v7m. 4696 return MCDisassembler::Fail; 4697 break; 4698 case 0x8a: // msplim_ns 4699 case 0x8b: // psplim_ns 4700 case 0x91: // basepri_ns 4701 case 0x93: // faultmask_ns 4702 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4703 return MCDisassembler::Fail; 4704 LLVM_FALLTHROUGH; 4705 case 10: // msplim 4706 case 11: // psplim 4707 case 0x88: // msp_ns 4708 case 0x89: // psp_ns 4709 case 0x90: // primask_ns 4710 case 0x94: // control_ns 4711 case 0x98: // sp_ns 4712 if (!(FeatureBits[ARM::Feature8MSecExt])) 4713 return MCDisassembler::Fail; 4714 break; 4715 default: 4716 // Architecturally defined as unpredictable 4717 S = MCDisassembler::SoftFail; 4718 break; 4719 } 4720 4721 if (Inst.getOpcode() == ARM::t2MSR_M) { 4722 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4723 if (!(FeatureBits[ARM::HasV7Ops])) { 4724 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4725 // unpredictable. 4726 if (Mask != 2) 4727 S = MCDisassembler::SoftFail; 4728 } 4729 else { 4730 // The ARMv7-M architecture stores an additional 2-bit mask value in 4731 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4732 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4733 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4734 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4735 // only if the processor includes the DSP extension. 4736 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4737 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4738 S = MCDisassembler::SoftFail; 4739 } 4740 } 4741 } else { 4742 // A/R class 4743 if (Val == 0) 4744 return MCDisassembler::Fail; 4745 } 4746 Inst.addOperand(MCOperand::createImm(Val)); 4747 return S; 4748 } 4749 4750 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4751 uint64_t Address, const void *Decoder) { 4752 unsigned R = fieldFromInstruction(Val, 5, 1); 4753 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4754 4755 // The table of encodings for these banked registers comes from B9.2.3 of the 4756 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4757 // neater. So by fiat, these values are UNPREDICTABLE: 4758 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4759 return MCDisassembler::Fail; 4760 4761 Inst.addOperand(MCOperand::createImm(Val)); 4762 return MCDisassembler::Success; 4763 } 4764 4765 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4766 uint64_t Address, const void *Decoder) { 4767 DecodeStatus S = MCDisassembler::Success; 4768 4769 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4770 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4771 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4772 4773 if (Rn == 0xF) 4774 S = MCDisassembler::SoftFail; 4775 4776 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4777 return MCDisassembler::Fail; 4778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4779 return MCDisassembler::Fail; 4780 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4781 return MCDisassembler::Fail; 4782 4783 return S; 4784 } 4785 4786 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4787 uint64_t Address, 4788 const void *Decoder) { 4789 DecodeStatus S = MCDisassembler::Success; 4790 4791 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4792 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4793 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4794 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4795 4796 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4797 return MCDisassembler::Fail; 4798 4799 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4800 S = MCDisassembler::SoftFail; 4801 4802 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4803 return MCDisassembler::Fail; 4804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4805 return MCDisassembler::Fail; 4806 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4807 return MCDisassembler::Fail; 4808 4809 return S; 4810 } 4811 4812 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4813 uint64_t Address, const void *Decoder) { 4814 DecodeStatus S = MCDisassembler::Success; 4815 4816 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4817 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4818 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4819 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4820 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4821 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4822 4823 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4824 4825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4826 return MCDisassembler::Fail; 4827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4828 return MCDisassembler::Fail; 4829 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4830 return MCDisassembler::Fail; 4831 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4832 return MCDisassembler::Fail; 4833 4834 return S; 4835 } 4836 4837 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4838 uint64_t Address, const void *Decoder) { 4839 DecodeStatus S = MCDisassembler::Success; 4840 4841 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4842 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4843 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4844 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4845 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4846 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4847 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4848 4849 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4850 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4851 4852 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4853 return MCDisassembler::Fail; 4854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4855 return MCDisassembler::Fail; 4856 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4857 return MCDisassembler::Fail; 4858 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4859 return MCDisassembler::Fail; 4860 4861 return S; 4862 } 4863 4864 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4865 uint64_t Address, const void *Decoder) { 4866 DecodeStatus S = MCDisassembler::Success; 4867 4868 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4869 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4870 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4871 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4872 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4873 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4874 4875 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4876 4877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4878 return MCDisassembler::Fail; 4879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4880 return MCDisassembler::Fail; 4881 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4882 return MCDisassembler::Fail; 4883 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4884 return MCDisassembler::Fail; 4885 4886 return S; 4887 } 4888 4889 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4890 uint64_t Address, const void *Decoder) { 4891 DecodeStatus S = MCDisassembler::Success; 4892 4893 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4894 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4895 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4896 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4897 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4898 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4899 4900 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4901 4902 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4903 return MCDisassembler::Fail; 4904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4905 return MCDisassembler::Fail; 4906 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4907 return MCDisassembler::Fail; 4908 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4909 return MCDisassembler::Fail; 4910 4911 return S; 4912 } 4913 4914 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4915 uint64_t Address, const void *Decoder) { 4916 DecodeStatus S = MCDisassembler::Success; 4917 4918 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4919 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4920 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4921 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4922 unsigned size = fieldFromInstruction(Insn, 10, 2); 4923 4924 unsigned align = 0; 4925 unsigned index = 0; 4926 switch (size) { 4927 default: 4928 return MCDisassembler::Fail; 4929 case 0: 4930 if (fieldFromInstruction(Insn, 4, 1)) 4931 return MCDisassembler::Fail; // UNDEFINED 4932 index = fieldFromInstruction(Insn, 5, 3); 4933 break; 4934 case 1: 4935 if (fieldFromInstruction(Insn, 5, 1)) 4936 return MCDisassembler::Fail; // UNDEFINED 4937 index = fieldFromInstruction(Insn, 6, 2); 4938 if (fieldFromInstruction(Insn, 4, 1)) 4939 align = 2; 4940 break; 4941 case 2: 4942 if (fieldFromInstruction(Insn, 6, 1)) 4943 return MCDisassembler::Fail; // UNDEFINED 4944 index = fieldFromInstruction(Insn, 7, 1); 4945 4946 switch (fieldFromInstruction(Insn, 4, 2)) { 4947 case 0 : 4948 align = 0; break; 4949 case 3: 4950 align = 4; break; 4951 default: 4952 return MCDisassembler::Fail; 4953 } 4954 break; 4955 } 4956 4957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4958 return MCDisassembler::Fail; 4959 if (Rm != 0xF) { // Writeback 4960 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4961 return MCDisassembler::Fail; 4962 } 4963 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4964 return MCDisassembler::Fail; 4965 Inst.addOperand(MCOperand::createImm(align)); 4966 if (Rm != 0xF) { 4967 if (Rm != 0xD) { 4968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4969 return MCDisassembler::Fail; 4970 } else 4971 Inst.addOperand(MCOperand::createReg(0)); 4972 } 4973 4974 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4975 return MCDisassembler::Fail; 4976 Inst.addOperand(MCOperand::createImm(index)); 4977 4978 return S; 4979 } 4980 4981 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4982 uint64_t Address, const void *Decoder) { 4983 DecodeStatus S = MCDisassembler::Success; 4984 4985 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4986 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4987 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4988 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4989 unsigned size = fieldFromInstruction(Insn, 10, 2); 4990 4991 unsigned align = 0; 4992 unsigned index = 0; 4993 switch (size) { 4994 default: 4995 return MCDisassembler::Fail; 4996 case 0: 4997 if (fieldFromInstruction(Insn, 4, 1)) 4998 return MCDisassembler::Fail; // UNDEFINED 4999 index = fieldFromInstruction(Insn, 5, 3); 5000 break; 5001 case 1: 5002 if (fieldFromInstruction(Insn, 5, 1)) 5003 return MCDisassembler::Fail; // UNDEFINED 5004 index = fieldFromInstruction(Insn, 6, 2); 5005 if (fieldFromInstruction(Insn, 4, 1)) 5006 align = 2; 5007 break; 5008 case 2: 5009 if (fieldFromInstruction(Insn, 6, 1)) 5010 return MCDisassembler::Fail; // UNDEFINED 5011 index = fieldFromInstruction(Insn, 7, 1); 5012 5013 switch (fieldFromInstruction(Insn, 4, 2)) { 5014 case 0: 5015 align = 0; break; 5016 case 3: 5017 align = 4; break; 5018 default: 5019 return MCDisassembler::Fail; 5020 } 5021 break; 5022 } 5023 5024 if (Rm != 0xF) { // Writeback 5025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5026 return MCDisassembler::Fail; 5027 } 5028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5029 return MCDisassembler::Fail; 5030 Inst.addOperand(MCOperand::createImm(align)); 5031 if (Rm != 0xF) { 5032 if (Rm != 0xD) { 5033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5034 return MCDisassembler::Fail; 5035 } else 5036 Inst.addOperand(MCOperand::createReg(0)); 5037 } 5038 5039 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5040 return MCDisassembler::Fail; 5041 Inst.addOperand(MCOperand::createImm(index)); 5042 5043 return S; 5044 } 5045 5046 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5047 uint64_t Address, const void *Decoder) { 5048 DecodeStatus S = MCDisassembler::Success; 5049 5050 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5051 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5052 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5053 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5054 unsigned size = fieldFromInstruction(Insn, 10, 2); 5055 5056 unsigned align = 0; 5057 unsigned index = 0; 5058 unsigned inc = 1; 5059 switch (size) { 5060 default: 5061 return MCDisassembler::Fail; 5062 case 0: 5063 index = fieldFromInstruction(Insn, 5, 3); 5064 if (fieldFromInstruction(Insn, 4, 1)) 5065 align = 2; 5066 break; 5067 case 1: 5068 index = fieldFromInstruction(Insn, 6, 2); 5069 if (fieldFromInstruction(Insn, 4, 1)) 5070 align = 4; 5071 if (fieldFromInstruction(Insn, 5, 1)) 5072 inc = 2; 5073 break; 5074 case 2: 5075 if (fieldFromInstruction(Insn, 5, 1)) 5076 return MCDisassembler::Fail; // UNDEFINED 5077 index = fieldFromInstruction(Insn, 7, 1); 5078 if (fieldFromInstruction(Insn, 4, 1) != 0) 5079 align = 8; 5080 if (fieldFromInstruction(Insn, 6, 1)) 5081 inc = 2; 5082 break; 5083 } 5084 5085 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5086 return MCDisassembler::Fail; 5087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5088 return MCDisassembler::Fail; 5089 if (Rm != 0xF) { // Writeback 5090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5091 return MCDisassembler::Fail; 5092 } 5093 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5094 return MCDisassembler::Fail; 5095 Inst.addOperand(MCOperand::createImm(align)); 5096 if (Rm != 0xF) { 5097 if (Rm != 0xD) { 5098 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5099 return MCDisassembler::Fail; 5100 } else 5101 Inst.addOperand(MCOperand::createReg(0)); 5102 } 5103 5104 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5105 return MCDisassembler::Fail; 5106 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5107 return MCDisassembler::Fail; 5108 Inst.addOperand(MCOperand::createImm(index)); 5109 5110 return S; 5111 } 5112 5113 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5114 uint64_t Address, const void *Decoder) { 5115 DecodeStatus S = MCDisassembler::Success; 5116 5117 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5118 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5119 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5120 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5121 unsigned size = fieldFromInstruction(Insn, 10, 2); 5122 5123 unsigned align = 0; 5124 unsigned index = 0; 5125 unsigned inc = 1; 5126 switch (size) { 5127 default: 5128 return MCDisassembler::Fail; 5129 case 0: 5130 index = fieldFromInstruction(Insn, 5, 3); 5131 if (fieldFromInstruction(Insn, 4, 1)) 5132 align = 2; 5133 break; 5134 case 1: 5135 index = fieldFromInstruction(Insn, 6, 2); 5136 if (fieldFromInstruction(Insn, 4, 1)) 5137 align = 4; 5138 if (fieldFromInstruction(Insn, 5, 1)) 5139 inc = 2; 5140 break; 5141 case 2: 5142 if (fieldFromInstruction(Insn, 5, 1)) 5143 return MCDisassembler::Fail; // UNDEFINED 5144 index = fieldFromInstruction(Insn, 7, 1); 5145 if (fieldFromInstruction(Insn, 4, 1) != 0) 5146 align = 8; 5147 if (fieldFromInstruction(Insn, 6, 1)) 5148 inc = 2; 5149 break; 5150 } 5151 5152 if (Rm != 0xF) { // Writeback 5153 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5154 return MCDisassembler::Fail; 5155 } 5156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5157 return MCDisassembler::Fail; 5158 Inst.addOperand(MCOperand::createImm(align)); 5159 if (Rm != 0xF) { 5160 if (Rm != 0xD) { 5161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5162 return MCDisassembler::Fail; 5163 } else 5164 Inst.addOperand(MCOperand::createReg(0)); 5165 } 5166 5167 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5168 return MCDisassembler::Fail; 5169 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5170 return MCDisassembler::Fail; 5171 Inst.addOperand(MCOperand::createImm(index)); 5172 5173 return S; 5174 } 5175 5176 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5177 uint64_t Address, const void *Decoder) { 5178 DecodeStatus S = MCDisassembler::Success; 5179 5180 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5181 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5182 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5183 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5184 unsigned size = fieldFromInstruction(Insn, 10, 2); 5185 5186 unsigned align = 0; 5187 unsigned index = 0; 5188 unsigned inc = 1; 5189 switch (size) { 5190 default: 5191 return MCDisassembler::Fail; 5192 case 0: 5193 if (fieldFromInstruction(Insn, 4, 1)) 5194 return MCDisassembler::Fail; // UNDEFINED 5195 index = fieldFromInstruction(Insn, 5, 3); 5196 break; 5197 case 1: 5198 if (fieldFromInstruction(Insn, 4, 1)) 5199 return MCDisassembler::Fail; // UNDEFINED 5200 index = fieldFromInstruction(Insn, 6, 2); 5201 if (fieldFromInstruction(Insn, 5, 1)) 5202 inc = 2; 5203 break; 5204 case 2: 5205 if (fieldFromInstruction(Insn, 4, 2)) 5206 return MCDisassembler::Fail; // UNDEFINED 5207 index = fieldFromInstruction(Insn, 7, 1); 5208 if (fieldFromInstruction(Insn, 6, 1)) 5209 inc = 2; 5210 break; 5211 } 5212 5213 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5214 return MCDisassembler::Fail; 5215 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5216 return MCDisassembler::Fail; 5217 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5218 return MCDisassembler::Fail; 5219 5220 if (Rm != 0xF) { // Writeback 5221 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5222 return MCDisassembler::Fail; 5223 } 5224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5225 return MCDisassembler::Fail; 5226 Inst.addOperand(MCOperand::createImm(align)); 5227 if (Rm != 0xF) { 5228 if (Rm != 0xD) { 5229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5230 return MCDisassembler::Fail; 5231 } else 5232 Inst.addOperand(MCOperand::createReg(0)); 5233 } 5234 5235 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5236 return MCDisassembler::Fail; 5237 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5238 return MCDisassembler::Fail; 5239 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5240 return MCDisassembler::Fail; 5241 Inst.addOperand(MCOperand::createImm(index)); 5242 5243 return S; 5244 } 5245 5246 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5247 uint64_t Address, const void *Decoder) { 5248 DecodeStatus S = MCDisassembler::Success; 5249 5250 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5251 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5252 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5253 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5254 unsigned size = fieldFromInstruction(Insn, 10, 2); 5255 5256 unsigned align = 0; 5257 unsigned index = 0; 5258 unsigned inc = 1; 5259 switch (size) { 5260 default: 5261 return MCDisassembler::Fail; 5262 case 0: 5263 if (fieldFromInstruction(Insn, 4, 1)) 5264 return MCDisassembler::Fail; // UNDEFINED 5265 index = fieldFromInstruction(Insn, 5, 3); 5266 break; 5267 case 1: 5268 if (fieldFromInstruction(Insn, 4, 1)) 5269 return MCDisassembler::Fail; // UNDEFINED 5270 index = fieldFromInstruction(Insn, 6, 2); 5271 if (fieldFromInstruction(Insn, 5, 1)) 5272 inc = 2; 5273 break; 5274 case 2: 5275 if (fieldFromInstruction(Insn, 4, 2)) 5276 return MCDisassembler::Fail; // UNDEFINED 5277 index = fieldFromInstruction(Insn, 7, 1); 5278 if (fieldFromInstruction(Insn, 6, 1)) 5279 inc = 2; 5280 break; 5281 } 5282 5283 if (Rm != 0xF) { // Writeback 5284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5285 return MCDisassembler::Fail; 5286 } 5287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5288 return MCDisassembler::Fail; 5289 Inst.addOperand(MCOperand::createImm(align)); 5290 if (Rm != 0xF) { 5291 if (Rm != 0xD) { 5292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5293 return MCDisassembler::Fail; 5294 } else 5295 Inst.addOperand(MCOperand::createReg(0)); 5296 } 5297 5298 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5299 return MCDisassembler::Fail; 5300 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5301 return MCDisassembler::Fail; 5302 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5303 return MCDisassembler::Fail; 5304 Inst.addOperand(MCOperand::createImm(index)); 5305 5306 return S; 5307 } 5308 5309 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5310 uint64_t Address, const void *Decoder) { 5311 DecodeStatus S = MCDisassembler::Success; 5312 5313 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5314 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5315 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5316 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5317 unsigned size = fieldFromInstruction(Insn, 10, 2); 5318 5319 unsigned align = 0; 5320 unsigned index = 0; 5321 unsigned inc = 1; 5322 switch (size) { 5323 default: 5324 return MCDisassembler::Fail; 5325 case 0: 5326 if (fieldFromInstruction(Insn, 4, 1)) 5327 align = 4; 5328 index = fieldFromInstruction(Insn, 5, 3); 5329 break; 5330 case 1: 5331 if (fieldFromInstruction(Insn, 4, 1)) 5332 align = 8; 5333 index = fieldFromInstruction(Insn, 6, 2); 5334 if (fieldFromInstruction(Insn, 5, 1)) 5335 inc = 2; 5336 break; 5337 case 2: 5338 switch (fieldFromInstruction(Insn, 4, 2)) { 5339 case 0: 5340 align = 0; break; 5341 case 3: 5342 return MCDisassembler::Fail; 5343 default: 5344 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5345 } 5346 5347 index = fieldFromInstruction(Insn, 7, 1); 5348 if (fieldFromInstruction(Insn, 6, 1)) 5349 inc = 2; 5350 break; 5351 } 5352 5353 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5354 return MCDisassembler::Fail; 5355 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5356 return MCDisassembler::Fail; 5357 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5358 return MCDisassembler::Fail; 5359 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5360 return MCDisassembler::Fail; 5361 5362 if (Rm != 0xF) { // Writeback 5363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5364 return MCDisassembler::Fail; 5365 } 5366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5367 return MCDisassembler::Fail; 5368 Inst.addOperand(MCOperand::createImm(align)); 5369 if (Rm != 0xF) { 5370 if (Rm != 0xD) { 5371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5372 return MCDisassembler::Fail; 5373 } else 5374 Inst.addOperand(MCOperand::createReg(0)); 5375 } 5376 5377 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5378 return MCDisassembler::Fail; 5379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5380 return MCDisassembler::Fail; 5381 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5382 return MCDisassembler::Fail; 5383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5384 return MCDisassembler::Fail; 5385 Inst.addOperand(MCOperand::createImm(index)); 5386 5387 return S; 5388 } 5389 5390 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5391 uint64_t Address, const void *Decoder) { 5392 DecodeStatus S = MCDisassembler::Success; 5393 5394 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5395 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5396 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5397 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5398 unsigned size = fieldFromInstruction(Insn, 10, 2); 5399 5400 unsigned align = 0; 5401 unsigned index = 0; 5402 unsigned inc = 1; 5403 switch (size) { 5404 default: 5405 return MCDisassembler::Fail; 5406 case 0: 5407 if (fieldFromInstruction(Insn, 4, 1)) 5408 align = 4; 5409 index = fieldFromInstruction(Insn, 5, 3); 5410 break; 5411 case 1: 5412 if (fieldFromInstruction(Insn, 4, 1)) 5413 align = 8; 5414 index = fieldFromInstruction(Insn, 6, 2); 5415 if (fieldFromInstruction(Insn, 5, 1)) 5416 inc = 2; 5417 break; 5418 case 2: 5419 switch (fieldFromInstruction(Insn, 4, 2)) { 5420 case 0: 5421 align = 0; break; 5422 case 3: 5423 return MCDisassembler::Fail; 5424 default: 5425 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5426 } 5427 5428 index = fieldFromInstruction(Insn, 7, 1); 5429 if (fieldFromInstruction(Insn, 6, 1)) 5430 inc = 2; 5431 break; 5432 } 5433 5434 if (Rm != 0xF) { // Writeback 5435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5436 return MCDisassembler::Fail; 5437 } 5438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5439 return MCDisassembler::Fail; 5440 Inst.addOperand(MCOperand::createImm(align)); 5441 if (Rm != 0xF) { 5442 if (Rm != 0xD) { 5443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5444 return MCDisassembler::Fail; 5445 } else 5446 Inst.addOperand(MCOperand::createReg(0)); 5447 } 5448 5449 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5450 return MCDisassembler::Fail; 5451 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5452 return MCDisassembler::Fail; 5453 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5454 return MCDisassembler::Fail; 5455 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5456 return MCDisassembler::Fail; 5457 Inst.addOperand(MCOperand::createImm(index)); 5458 5459 return S; 5460 } 5461 5462 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5463 uint64_t Address, const void *Decoder) { 5464 DecodeStatus S = MCDisassembler::Success; 5465 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5466 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5467 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5468 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5469 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5470 5471 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5472 S = MCDisassembler::SoftFail; 5473 5474 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5475 return MCDisassembler::Fail; 5476 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5477 return MCDisassembler::Fail; 5478 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5479 return MCDisassembler::Fail; 5480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5481 return MCDisassembler::Fail; 5482 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5483 return MCDisassembler::Fail; 5484 5485 return S; 5486 } 5487 5488 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5489 uint64_t Address, const void *Decoder) { 5490 DecodeStatus S = MCDisassembler::Success; 5491 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5492 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5493 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5494 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5495 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5496 5497 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5498 S = MCDisassembler::SoftFail; 5499 5500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5501 return MCDisassembler::Fail; 5502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5503 return MCDisassembler::Fail; 5504 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5505 return MCDisassembler::Fail; 5506 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5507 return MCDisassembler::Fail; 5508 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5509 return MCDisassembler::Fail; 5510 5511 return S; 5512 } 5513 5514 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5515 uint64_t Address, const void *Decoder) { 5516 DecodeStatus S = MCDisassembler::Success; 5517 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5518 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5519 5520 if (pred == 0xF) { 5521 pred = 0xE; 5522 S = MCDisassembler::SoftFail; 5523 } 5524 5525 if (mask == 0x0) 5526 return MCDisassembler::Fail; 5527 5528 // IT masks are encoded as a sequence of replacement low-order bits 5529 // for the condition code. So if the low bit of the starting 5530 // condition code is 1, then we have to flip all the bits above the 5531 // terminating bit (which is the lowest 1 bit). 5532 if (pred & 1) { 5533 unsigned LowBit = mask & -mask; 5534 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5535 mask ^= BitsAboveLowBit; 5536 } 5537 5538 Inst.addOperand(MCOperand::createImm(pred)); 5539 Inst.addOperand(MCOperand::createImm(mask)); 5540 return S; 5541 } 5542 5543 static DecodeStatus 5544 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5545 uint64_t Address, const void *Decoder) { 5546 DecodeStatus S = MCDisassembler::Success; 5547 5548 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5549 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5550 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5551 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5552 unsigned W = fieldFromInstruction(Insn, 21, 1); 5553 unsigned U = fieldFromInstruction(Insn, 23, 1); 5554 unsigned P = fieldFromInstruction(Insn, 24, 1); 5555 bool writeback = (W == 1) | (P == 0); 5556 5557 addr |= (U << 8) | (Rn << 9); 5558 5559 if (writeback && (Rn == Rt || Rn == Rt2)) 5560 Check(S, MCDisassembler::SoftFail); 5561 if (Rt == Rt2) 5562 Check(S, MCDisassembler::SoftFail); 5563 5564 // Rt 5565 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5566 return MCDisassembler::Fail; 5567 // Rt2 5568 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5569 return MCDisassembler::Fail; 5570 // Writeback operand 5571 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5572 return MCDisassembler::Fail; 5573 // addr 5574 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5575 return MCDisassembler::Fail; 5576 5577 return S; 5578 } 5579 5580 static DecodeStatus 5581 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5582 uint64_t Address, const void *Decoder) { 5583 DecodeStatus S = MCDisassembler::Success; 5584 5585 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5586 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5587 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5588 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5589 unsigned W = fieldFromInstruction(Insn, 21, 1); 5590 unsigned U = fieldFromInstruction(Insn, 23, 1); 5591 unsigned P = fieldFromInstruction(Insn, 24, 1); 5592 bool writeback = (W == 1) | (P == 0); 5593 5594 addr |= (U << 8) | (Rn << 9); 5595 5596 if (writeback && (Rn == Rt || Rn == Rt2)) 5597 Check(S, MCDisassembler::SoftFail); 5598 5599 // Writeback operand 5600 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5601 return MCDisassembler::Fail; 5602 // Rt 5603 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5604 return MCDisassembler::Fail; 5605 // Rt2 5606 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5607 return MCDisassembler::Fail; 5608 // addr 5609 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5610 return MCDisassembler::Fail; 5611 5612 return S; 5613 } 5614 5615 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5616 uint64_t Address, const void *Decoder) { 5617 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5618 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5619 if (sign1 != sign2) return MCDisassembler::Fail; 5620 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5621 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5622 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5623 5624 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5625 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5626 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5627 // If sign, then it is decreasing the address. 5628 if (sign1) { 5629 // Following ARMv7 Architecture Manual, when the offset 5630 // is zero, it is decoded as a subw, not as a adr.w 5631 if (!Val) { 5632 Inst.setOpcode(ARM::t2SUBri12); 5633 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5634 } else 5635 Val = -Val; 5636 } 5637 Inst.addOperand(MCOperand::createImm(Val)); 5638 return S; 5639 } 5640 5641 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5642 uint64_t Address, 5643 const void *Decoder) { 5644 DecodeStatus S = MCDisassembler::Success; 5645 5646 // Shift of "asr #32" is not allowed in Thumb2 mode. 5647 if (Val == 0x20) S = MCDisassembler::Fail; 5648 Inst.addOperand(MCOperand::createImm(Val)); 5649 return S; 5650 } 5651 5652 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5653 uint64_t Address, const void *Decoder) { 5654 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5655 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5656 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5657 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5658 5659 if (pred == 0xF) 5660 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5661 5662 DecodeStatus S = MCDisassembler::Success; 5663 5664 if (Rt == Rn || Rn == Rt2) 5665 S = MCDisassembler::SoftFail; 5666 5667 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5668 return MCDisassembler::Fail; 5669 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5670 return MCDisassembler::Fail; 5671 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5672 return MCDisassembler::Fail; 5673 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5674 return MCDisassembler::Fail; 5675 5676 return S; 5677 } 5678 5679 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5680 uint64_t Address, const void *Decoder) { 5681 const FeatureBitset &featureBits = 5682 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5683 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5684 5685 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5686 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5687 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5688 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5689 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5690 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5691 unsigned op = fieldFromInstruction(Insn, 5, 1); 5692 5693 DecodeStatus S = MCDisassembler::Success; 5694 5695 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5696 if (!(imm & 0x38)) { 5697 if (cmode == 0xF) { 5698 if (op == 1) return MCDisassembler::Fail; 5699 Inst.setOpcode(ARM::VMOVv2f32); 5700 } 5701 if (hasFullFP16) { 5702 if (cmode == 0xE) { 5703 if (op == 1) { 5704 Inst.setOpcode(ARM::VMOVv1i64); 5705 } else { 5706 Inst.setOpcode(ARM::VMOVv8i8); 5707 } 5708 } 5709 if (cmode == 0xD) { 5710 if (op == 1) { 5711 Inst.setOpcode(ARM::VMVNv2i32); 5712 } else { 5713 Inst.setOpcode(ARM::VMOVv2i32); 5714 } 5715 } 5716 if (cmode == 0xC) { 5717 if (op == 1) { 5718 Inst.setOpcode(ARM::VMVNv2i32); 5719 } else { 5720 Inst.setOpcode(ARM::VMOVv2i32); 5721 } 5722 } 5723 } 5724 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5725 } 5726 5727 if (!(imm & 0x20)) return MCDisassembler::Fail; 5728 5729 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5730 return MCDisassembler::Fail; 5731 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5732 return MCDisassembler::Fail; 5733 Inst.addOperand(MCOperand::createImm(64 - imm)); 5734 5735 return S; 5736 } 5737 5738 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5739 uint64_t Address, const void *Decoder) { 5740 const FeatureBitset &featureBits = 5741 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5742 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5743 5744 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5745 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5746 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5747 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5748 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5749 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5750 unsigned op = fieldFromInstruction(Insn, 5, 1); 5751 5752 DecodeStatus S = MCDisassembler::Success; 5753 5754 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5755 if (!(imm & 0x38)) { 5756 if (cmode == 0xF) { 5757 if (op == 1) return MCDisassembler::Fail; 5758 Inst.setOpcode(ARM::VMOVv4f32); 5759 } 5760 if (hasFullFP16) { 5761 if (cmode == 0xE) { 5762 if (op == 1) { 5763 Inst.setOpcode(ARM::VMOVv2i64); 5764 } else { 5765 Inst.setOpcode(ARM::VMOVv16i8); 5766 } 5767 } 5768 if (cmode == 0xD) { 5769 if (op == 1) { 5770 Inst.setOpcode(ARM::VMVNv4i32); 5771 } else { 5772 Inst.setOpcode(ARM::VMOVv4i32); 5773 } 5774 } 5775 if (cmode == 0xC) { 5776 if (op == 1) { 5777 Inst.setOpcode(ARM::VMVNv4i32); 5778 } else { 5779 Inst.setOpcode(ARM::VMOVv4i32); 5780 } 5781 } 5782 } 5783 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5784 } 5785 5786 if (!(imm & 0x20)) return MCDisassembler::Fail; 5787 5788 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5789 return MCDisassembler::Fail; 5790 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5791 return MCDisassembler::Fail; 5792 Inst.addOperand(MCOperand::createImm(64 - imm)); 5793 5794 return S; 5795 } 5796 5797 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5798 unsigned Insn, 5799 uint64_t Address, 5800 const void *Decoder) { 5801 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5802 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5803 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5804 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5805 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5806 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5807 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5808 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5809 5810 DecodeStatus S = MCDisassembler::Success; 5811 5812 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5813 5814 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5815 return MCDisassembler::Fail; 5816 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5817 return MCDisassembler::Fail; 5818 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5819 return MCDisassembler::Fail; 5820 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5821 return MCDisassembler::Fail; 5822 // The lane index does not have any bits in the encoding, because it can only 5823 // be 0. 5824 Inst.addOperand(MCOperand::createImm(0)); 5825 Inst.addOperand(MCOperand::createImm(rotate)); 5826 5827 return S; 5828 } 5829 5830 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5831 uint64_t Address, const void *Decoder) { 5832 DecodeStatus S = MCDisassembler::Success; 5833 5834 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5835 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5836 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5837 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5838 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5839 5840 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5841 S = MCDisassembler::SoftFail; 5842 5843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5844 return MCDisassembler::Fail; 5845 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5846 return MCDisassembler::Fail; 5847 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5848 return MCDisassembler::Fail; 5849 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5850 return MCDisassembler::Fail; 5851 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5852 return MCDisassembler::Fail; 5853 5854 return S; 5855 } 5856 5857 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5858 uint64_t Address, const void *Decoder) { 5859 DecodeStatus S = MCDisassembler::Success; 5860 5861 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5862 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5863 unsigned cop = fieldFromInstruction(Val, 8, 4); 5864 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5865 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5866 5867 if ((cop & ~0x1) == 0xa) 5868 return MCDisassembler::Fail; 5869 5870 if (Rt == Rt2) 5871 S = MCDisassembler::SoftFail; 5872 5873 // We have to check if the instruction is MRRC2 5874 // or MCRR2 when constructing the operands for 5875 // Inst. Reason is because MRRC2 stores to two 5876 // registers so it's tablegen desc has has two 5877 // outputs whereas MCRR doesn't store to any 5878 // registers so all of it's operands are listed 5879 // as inputs, therefore the operand order for 5880 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5881 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5882 5883 if (Inst.getOpcode() == ARM::MRRC2) { 5884 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5885 return MCDisassembler::Fail; 5886 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5887 return MCDisassembler::Fail; 5888 } 5889 Inst.addOperand(MCOperand::createImm(cop)); 5890 Inst.addOperand(MCOperand::createImm(opc1)); 5891 if (Inst.getOpcode() == ARM::MCRR2) { 5892 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5893 return MCDisassembler::Fail; 5894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5895 return MCDisassembler::Fail; 5896 } 5897 Inst.addOperand(MCOperand::createImm(CRm)); 5898 5899 return S; 5900 } 5901 5902 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5903 uint64_t Address, 5904 const void *Decoder) { 5905 const FeatureBitset &featureBits = 5906 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5907 DecodeStatus S = MCDisassembler::Success; 5908 5909 // Add explicit operand for the destination sysreg, for cases where 5910 // we have to model it for code generation purposes. 5911 switch (Inst.getOpcode()) { 5912 case ARM::VMSR_FPSCR_NZCVQC: 5913 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5914 break; 5915 case ARM::VMSR_P0: 5916 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5917 break; 5918 } 5919 5920 if (Inst.getOpcode() != ARM::FMSTAT) { 5921 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5922 5923 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5924 if (Rt == 13 || Rt == 15) 5925 S = MCDisassembler::SoftFail; 5926 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5927 } else 5928 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5929 } 5930 5931 // Add explicit operand for the source sysreg, similarly to above. 5932 switch (Inst.getOpcode()) { 5933 case ARM::VMRS_FPSCR_NZCVQC: 5934 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5935 break; 5936 case ARM::VMRS_P0: 5937 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5938 break; 5939 } 5940 5941 if (featureBits[ARM::ModeThumb]) { 5942 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5943 Inst.addOperand(MCOperand::createReg(0)); 5944 } else { 5945 unsigned pred = fieldFromInstruction(Val, 28, 4); 5946 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5947 return MCDisassembler::Fail; 5948 } 5949 5950 return S; 5951 } 5952 5953 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5954 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5955 uint64_t Address, 5956 const void *Decoder) { 5957 DecodeStatus S = MCDisassembler::Success; 5958 if (Val == 0 && !zeroPermitted) 5959 S = MCDisassembler::Fail; 5960 5961 uint64_t DecVal; 5962 if (isSigned) 5963 DecVal = SignExtend32<size + 1>(Val << 1); 5964 else 5965 DecVal = (Val << 1); 5966 5967 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5968 Decoder)) 5969 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5970 return S; 5971 } 5972 5973 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5974 uint64_t Address, 5975 const void *Decoder) { 5976 5977 uint64_t LocImm = Inst.getOperand(0).getImm(); 5978 Val = LocImm + (2 << Val); 5979 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5980 Decoder)) 5981 Inst.addOperand(MCOperand::createImm(Val)); 5982 return MCDisassembler::Success; 5983 } 5984 5985 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5986 uint64_t Address, 5987 const void *Decoder) { 5988 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5989 return MCDisassembler::Fail; 5990 Inst.addOperand(MCOperand::createImm(Val)); 5991 return MCDisassembler::Success; 5992 } 5993 5994 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5995 const void *Decoder) { 5996 DecodeStatus S = MCDisassembler::Success; 5997 5998 if (Inst.getOpcode() == ARM::MVE_LCTP) 5999 return S; 6000 6001 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6002 fieldFromInstruction(Insn, 1, 10) << 1; 6003 switch (Inst.getOpcode()) { 6004 case ARM::t2LEUpdate: 6005 case ARM::MVE_LETP: 6006 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6007 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6008 LLVM_FALLTHROUGH; 6009 case ARM::t2LE: 6010 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6011 Inst, Imm, Address, Decoder))) 6012 return MCDisassembler::Fail; 6013 break; 6014 case ARM::t2WLS: 6015 case ARM::MVE_WLSTP_8: 6016 case ARM::MVE_WLSTP_16: 6017 case ARM::MVE_WLSTP_32: 6018 case ARM::MVE_WLSTP_64: 6019 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6020 if (!Check(S, 6021 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6022 Address, Decoder)) || 6023 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6024 Inst, Imm, Address, Decoder))) 6025 return MCDisassembler::Fail; 6026 break; 6027 case ARM::t2DLS: 6028 case ARM::MVE_DLSTP_8: 6029 case ARM::MVE_DLSTP_16: 6030 case ARM::MVE_DLSTP_32: 6031 case ARM::MVE_DLSTP_64: 6032 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6033 if (Rn == 0xF) { 6034 // Enforce all the rest of the instruction bits in LCTP, which 6035 // won't have been reliably checked based on LCTP's own tablegen 6036 // record, because we came to this decode by a roundabout route. 6037 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6038 if ((Insn & ~SBZMask) != CanonicalLCTP) 6039 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6040 if (Insn != CanonicalLCTP) 6041 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6042 6043 Inst.setOpcode(ARM::MVE_LCTP); 6044 } else { 6045 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6046 if (!Check(S, DecoderGPRRegisterClass(Inst, 6047 fieldFromInstruction(Insn, 16, 4), 6048 Address, Decoder))) 6049 return MCDisassembler::Fail; 6050 } 6051 break; 6052 } 6053 return S; 6054 } 6055 6056 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6057 uint64_t Address, 6058 const void *Decoder) { 6059 DecodeStatus S = MCDisassembler::Success; 6060 6061 if (Val == 0) 6062 Val = 32; 6063 6064 Inst.addOperand(MCOperand::createImm(Val)); 6065 6066 return S; 6067 } 6068 6069 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6070 uint64_t Address, const void *Decoder) { 6071 if ((RegNo) + 1 > 11) 6072 return MCDisassembler::Fail; 6073 6074 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6075 Inst.addOperand(MCOperand::createReg(Register)); 6076 return MCDisassembler::Success; 6077 } 6078 6079 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6080 uint64_t Address, const void *Decoder) { 6081 if ((RegNo) > 14) 6082 return MCDisassembler::Fail; 6083 6084 unsigned Register = GPRDecoderTable[(RegNo)]; 6085 Inst.addOperand(MCOperand::createReg(Register)); 6086 return MCDisassembler::Success; 6087 } 6088 6089 static DecodeStatus 6090 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6091 uint64_t Address, const void *Decoder) { 6092 if (RegNo == 15) { 6093 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6094 return MCDisassembler::Success; 6095 } 6096 6097 unsigned Register = GPRDecoderTable[RegNo]; 6098 Inst.addOperand(MCOperand::createReg(Register)); 6099 6100 if (RegNo == 13) 6101 return MCDisassembler::SoftFail; 6102 6103 return MCDisassembler::Success; 6104 } 6105 6106 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6107 const void *Decoder) { 6108 DecodeStatus S = MCDisassembler::Success; 6109 6110 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6111 Inst.addOperand(MCOperand::createReg(0)); 6112 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6113 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6114 (fieldFromInstruction(Insn, 12, 4) << 8) | 6115 (fieldFromInstruction(Insn, 22, 1) << 12); 6116 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6117 return MCDisassembler::Fail; 6118 } 6119 } else { 6120 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6121 (fieldFromInstruction(Insn, 22, 1) << 8) | 6122 (fieldFromInstruction(Insn, 12, 4) << 9); 6123 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6124 return MCDisassembler::Fail; 6125 } 6126 } 6127 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6128 6129 return S; 6130 } 6131 6132 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6133 uint64_t Address, 6134 const void *Decoder) { 6135 if (RegNo > 7) 6136 return MCDisassembler::Fail; 6137 6138 unsigned Register = QPRDecoderTable[RegNo]; 6139 Inst.addOperand(MCOperand::createReg(Register)); 6140 return MCDisassembler::Success; 6141 } 6142 6143 static const uint16_t QQPRDecoderTable[] = { 6144 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6145 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6146 }; 6147 6148 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6149 uint64_t Address, 6150 const void *Decoder) { 6151 if (RegNo > 6) 6152 return MCDisassembler::Fail; 6153 6154 unsigned Register = QQPRDecoderTable[RegNo]; 6155 Inst.addOperand(MCOperand::createReg(Register)); 6156 return MCDisassembler::Success; 6157 } 6158 6159 static const uint16_t QQQQPRDecoderTable[] = { 6160 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6161 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6162 }; 6163 6164 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6165 uint64_t Address, 6166 const void *Decoder) { 6167 if (RegNo > 4) 6168 return MCDisassembler::Fail; 6169 6170 unsigned Register = QQQQPRDecoderTable[RegNo]; 6171 Inst.addOperand(MCOperand::createReg(Register)); 6172 return MCDisassembler::Success; 6173 } 6174 6175 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6176 uint64_t Address, 6177 const void *Decoder) { 6178 DecodeStatus S = MCDisassembler::Success; 6179 6180 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6181 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6182 // 't' as 0 and finish with a 1. 6183 unsigned Imm = 0; 6184 // We always start with a 't'. 6185 unsigned CurBit = 0; 6186 for (int i = 3; i >= 0; --i) { 6187 // If the bit we are looking at is not the same as last one, invert the 6188 // CurBit, if it is the same leave it as is. 6189 CurBit ^= (Val >> i) & 1U; 6190 6191 // Encode the CurBit at the right place in the immediate. 6192 Imm |= (CurBit << i); 6193 6194 // If we are done, finish the encoding with a 1. 6195 if ((Val & ~(~0U << i)) == 0) { 6196 Imm |= 1U << i; 6197 break; 6198 } 6199 } 6200 6201 Inst.addOperand(MCOperand::createImm(Imm)); 6202 6203 return S; 6204 } 6205 6206 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6207 uint64_t Address, const void *Decoder) { 6208 // The vpred_r operand type includes an MQPR register field derived 6209 // from the encoding. But we don't actually want to add an operand 6210 // to the MCInst at this stage, because AddThumbPredicate will do it 6211 // later, and will infer the register number from the TIED_TO 6212 // constraint. So this is a deliberately empty decoder method that 6213 // will inhibit the auto-generated disassembly code from adding an 6214 // operand at all. 6215 return MCDisassembler::Success; 6216 } 6217 6218 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6219 unsigned Val, 6220 uint64_t Address, 6221 const void *Decoder) { 6222 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6223 return MCDisassembler::Success; 6224 } 6225 6226 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6227 unsigned Val, 6228 uint64_t Address, 6229 const void *Decoder) { 6230 unsigned Code; 6231 switch (Val & 0x3) { 6232 case 0: 6233 Code = ARMCC::GE; 6234 break; 6235 case 1: 6236 Code = ARMCC::LT; 6237 break; 6238 case 2: 6239 Code = ARMCC::GT; 6240 break; 6241 case 3: 6242 Code = ARMCC::LE; 6243 break; 6244 } 6245 Inst.addOperand(MCOperand::createImm(Code)); 6246 return MCDisassembler::Success; 6247 } 6248 6249 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6250 unsigned Val, 6251 uint64_t Address, 6252 const void *Decoder) { 6253 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6254 return MCDisassembler::Success; 6255 } 6256 6257 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6258 uint64_t Address, 6259 const void *Decoder) { 6260 unsigned Code; 6261 switch (Val) { 6262 default: 6263 return MCDisassembler::Fail; 6264 case 0: 6265 Code = ARMCC::EQ; 6266 break; 6267 case 1: 6268 Code = ARMCC::NE; 6269 break; 6270 case 4: 6271 Code = ARMCC::GE; 6272 break; 6273 case 5: 6274 Code = ARMCC::LT; 6275 break; 6276 case 6: 6277 Code = ARMCC::GT; 6278 break; 6279 case 7: 6280 Code = ARMCC::LE; 6281 break; 6282 } 6283 6284 Inst.addOperand(MCOperand::createImm(Code)); 6285 return MCDisassembler::Success; 6286 } 6287 6288 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6289 uint64_t Address, const void *Decoder) { 6290 DecodeStatus S = MCDisassembler::Success; 6291 6292 unsigned DecodedVal = 64 - Val; 6293 6294 switch (Inst.getOpcode()) { 6295 case ARM::MVE_VCVTf16s16_fix: 6296 case ARM::MVE_VCVTs16f16_fix: 6297 case ARM::MVE_VCVTf16u16_fix: 6298 case ARM::MVE_VCVTu16f16_fix: 6299 if (DecodedVal > 16) 6300 return MCDisassembler::Fail; 6301 break; 6302 case ARM::MVE_VCVTf32s32_fix: 6303 case ARM::MVE_VCVTs32f32_fix: 6304 case ARM::MVE_VCVTf32u32_fix: 6305 case ARM::MVE_VCVTu32f32_fix: 6306 if (DecodedVal > 32) 6307 return MCDisassembler::Fail; 6308 break; 6309 } 6310 6311 Inst.addOperand(MCOperand::createImm(64 - Val)); 6312 6313 return S; 6314 } 6315 6316 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6317 switch (Opcode) { 6318 case ARM::VSTR_P0_off: 6319 case ARM::VSTR_P0_pre: 6320 case ARM::VSTR_P0_post: 6321 case ARM::VLDR_P0_off: 6322 case ARM::VLDR_P0_pre: 6323 case ARM::VLDR_P0_post: 6324 return ARM::P0; 6325 default: 6326 return 0; 6327 } 6328 } 6329 6330 template<bool Writeback> 6331 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6332 uint64_t Address, 6333 const void *Decoder) { 6334 switch (Inst.getOpcode()) { 6335 case ARM::VSTR_FPSCR_pre: 6336 case ARM::VSTR_FPSCR_NZCVQC_pre: 6337 case ARM::VLDR_FPSCR_pre: 6338 case ARM::VLDR_FPSCR_NZCVQC_pre: 6339 case ARM::VSTR_FPSCR_off: 6340 case ARM::VSTR_FPSCR_NZCVQC_off: 6341 case ARM::VLDR_FPSCR_off: 6342 case ARM::VLDR_FPSCR_NZCVQC_off: 6343 case ARM::VSTR_FPSCR_post: 6344 case ARM::VSTR_FPSCR_NZCVQC_post: 6345 case ARM::VLDR_FPSCR_post: 6346 case ARM::VLDR_FPSCR_NZCVQC_post: 6347 const FeatureBitset &featureBits = 6348 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6349 6350 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6351 return MCDisassembler::Fail; 6352 } 6353 6354 DecodeStatus S = MCDisassembler::Success; 6355 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6356 Inst.addOperand(MCOperand::createReg(Sysreg)); 6357 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6358 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6359 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6360 6361 if (Writeback) { 6362 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6363 return MCDisassembler::Fail; 6364 } 6365 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6366 return MCDisassembler::Fail; 6367 6368 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6369 Inst.addOperand(MCOperand::createReg(0)); 6370 6371 return S; 6372 } 6373 6374 static inline DecodeStatus DecodeMVE_MEM_pre( 6375 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6376 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6377 DecodeStatus S = MCDisassembler::Success; 6378 6379 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6380 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6381 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6382 6383 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6384 return MCDisassembler::Fail; 6385 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6386 return MCDisassembler::Fail; 6387 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6388 return MCDisassembler::Fail; 6389 6390 return S; 6391 } 6392 6393 template <int shift> 6394 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6395 uint64_t Address, const void *Decoder) { 6396 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6397 fieldFromInstruction(Val, 16, 3), 6398 DecodetGPRRegisterClass, 6399 DecodeTAddrModeImm7<shift>); 6400 } 6401 6402 template <int shift> 6403 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6404 uint64_t Address, const void *Decoder) { 6405 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6406 fieldFromInstruction(Val, 16, 4), 6407 DecoderGPRRegisterClass, 6408 DecodeT2AddrModeImm7<shift,1>); 6409 } 6410 6411 template <int shift> 6412 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6413 uint64_t Address, const void *Decoder) { 6414 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6415 fieldFromInstruction(Val, 17, 3), 6416 DecodeMQPRRegisterClass, 6417 DecodeMveAddrModeQ<shift>); 6418 } 6419 6420 template<unsigned MinLog, unsigned MaxLog> 6421 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6422 uint64_t Address, 6423 const void *Decoder) { 6424 DecodeStatus S = MCDisassembler::Success; 6425 6426 if (Val < MinLog || Val > MaxLog) 6427 return MCDisassembler::Fail; 6428 6429 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6430 return S; 6431 } 6432 6433 template<unsigned start> 6434 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6435 uint64_t Address, 6436 const void *Decoder) { 6437 DecodeStatus S = MCDisassembler::Success; 6438 6439 Inst.addOperand(MCOperand::createImm(start + Val)); 6440 6441 return S; 6442 } 6443 6444 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6445 uint64_t Address, const void *Decoder) { 6446 DecodeStatus S = MCDisassembler::Success; 6447 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6448 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6449 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6450 fieldFromInstruction(Insn, 13, 3)); 6451 unsigned index = fieldFromInstruction(Insn, 4, 1); 6452 6453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6454 return MCDisassembler::Fail; 6455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6456 return MCDisassembler::Fail; 6457 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6458 return MCDisassembler::Fail; 6459 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6460 return MCDisassembler::Fail; 6461 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6462 return MCDisassembler::Fail; 6463 6464 return S; 6465 } 6466 6467 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6468 uint64_t Address, const void *Decoder) { 6469 DecodeStatus S = MCDisassembler::Success; 6470 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6471 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6472 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6473 fieldFromInstruction(Insn, 13, 3)); 6474 unsigned index = fieldFromInstruction(Insn, 4, 1); 6475 6476 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6477 return MCDisassembler::Fail; 6478 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6479 return MCDisassembler::Fail; 6480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6481 return MCDisassembler::Fail; 6482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6483 return MCDisassembler::Fail; 6484 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6485 return MCDisassembler::Fail; 6486 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6487 return MCDisassembler::Fail; 6488 6489 return S; 6490 } 6491 6492 static DecodeStatus DecodeMVEOverlappingLongShift( 6493 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6494 DecodeStatus S = MCDisassembler::Success; 6495 6496 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6497 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6498 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6499 6500 if (RdaHi == 14) { 6501 // This value of RdaHi (really indicating pc, because RdaHi has to 6502 // be an odd-numbered register, so the low bit will be set by the 6503 // decode function below) indicates that we must decode as SQRSHR 6504 // or UQRSHL, which both have a single Rda register field with all 6505 // four bits. 6506 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6507 6508 switch (Inst.getOpcode()) { 6509 case ARM::MVE_ASRLr: 6510 case ARM::MVE_SQRSHRL: 6511 Inst.setOpcode(ARM::MVE_SQRSHR); 6512 break; 6513 case ARM::MVE_LSLLr: 6514 case ARM::MVE_UQRSHLL: 6515 Inst.setOpcode(ARM::MVE_UQRSHL); 6516 break; 6517 default: 6518 llvm_unreachable("Unexpected starting opcode!"); 6519 } 6520 6521 // Rda as output parameter 6522 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6523 return MCDisassembler::Fail; 6524 6525 // Rda again as input parameter 6526 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6527 return MCDisassembler::Fail; 6528 6529 // Rm, the amount to shift by 6530 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6531 return MCDisassembler::Fail; 6532 6533 if (fieldFromInstruction (Insn, 6, 3) != 4) 6534 return MCDisassembler::SoftFail; 6535 6536 if (Rda == Rm) 6537 return MCDisassembler::SoftFail; 6538 6539 return S; 6540 } 6541 6542 // Otherwise, we decode as whichever opcode our caller has already 6543 // put into Inst. Those all look the same: 6544 6545 // RdaLo,RdaHi as output parameters 6546 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6547 return MCDisassembler::Fail; 6548 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6549 return MCDisassembler::Fail; 6550 6551 // RdaLo,RdaHi again as input parameters 6552 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6553 return MCDisassembler::Fail; 6554 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6555 return MCDisassembler::Fail; 6556 6557 // Rm, the amount to shift by 6558 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6559 return MCDisassembler::Fail; 6560 6561 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6562 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6563 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6564 // Saturate, the bit position for saturation 6565 Inst.addOperand(MCOperand::createImm(Saturate)); 6566 } 6567 6568 return S; 6569 } 6570 6571 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6572 const void *Decoder) { 6573 DecodeStatus S = MCDisassembler::Success; 6574 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6575 fieldFromInstruction(Insn, 13, 3)); 6576 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6577 fieldFromInstruction(Insn, 1, 3)); 6578 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6579 6580 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6581 return MCDisassembler::Fail; 6582 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6583 return MCDisassembler::Fail; 6584 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6585 return MCDisassembler::Fail; 6586 6587 return S; 6588 } 6589 6590 template<bool scalar, OperandDecoder predicate_decoder> 6591 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6592 const void *Decoder) { 6593 DecodeStatus S = MCDisassembler::Success; 6594 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6595 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6596 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6597 return MCDisassembler::Fail; 6598 6599 unsigned fc; 6600 6601 if (scalar) { 6602 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6603 fieldFromInstruction(Insn, 7, 1) | 6604 fieldFromInstruction(Insn, 5, 1) << 1; 6605 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6606 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6607 return MCDisassembler::Fail; 6608 } else { 6609 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6610 fieldFromInstruction(Insn, 7, 1) | 6611 fieldFromInstruction(Insn, 0, 1) << 1; 6612 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6613 fieldFromInstruction(Insn, 1, 3); 6614 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6615 return MCDisassembler::Fail; 6616 } 6617 6618 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6619 return MCDisassembler::Fail; 6620 6621 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6622 Inst.addOperand(MCOperand::createReg(0)); 6623 Inst.addOperand(MCOperand::createImm(0)); 6624 6625 return S; 6626 } 6627 6628 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6629 const void *Decoder) { 6630 DecodeStatus S = MCDisassembler::Success; 6631 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6632 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6633 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6634 return MCDisassembler::Fail; 6635 return S; 6636 } 6637 6638 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6639 const void *Decoder) { 6640 DecodeStatus S = MCDisassembler::Success; 6641 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6642 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6643 return S; 6644 } 6645 6646 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6647 uint64_t Address, const void *Decoder) { 6648 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6649 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6650 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6651 fieldFromInstruction(Insn, 12, 3) << 8 | 6652 fieldFromInstruction(Insn, 0, 8); 6653 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6654 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6655 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6656 unsigned S = fieldFromInstruction(Insn, 20, 1); 6657 if (sign1 != sign2) 6658 return MCDisassembler::Fail; 6659 6660 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6661 DecodeStatus DS = MCDisassembler::Success; 6662 if ((!Check(DS, 6663 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6664 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6665 return MCDisassembler::Fail; 6666 if (TypeT3) { 6667 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6668 S = 0; 6669 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6670 } else { 6671 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6672 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6673 return MCDisassembler::Fail; 6674 } 6675 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6676 return MCDisassembler::Fail; 6677 6678 Inst.addOperand(MCOperand::createReg(0)); // pred 6679 6680 return DS; 6681 } 6682