1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "llvm/MC/MCContext.h" 14 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 15 #include "llvm/MC/MCFixedLenDisassembler.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCSubtargetInfo.h" 19 #include "llvm/MC/SubtargetFeature.h" 20 #include "llvm/Support/Compiler.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <algorithm> 26 #include <cassert> 27 #include <cstdint> 28 #include <vector> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "arm-disassembler" 33 34 typedef MCDisassembler::DecodeStatus DecodeStatus; 35 36 namespace { 37 38 // Handles the condition code status of instructions in IT blocks 39 class ITStatus 40 { 41 public: 42 // Returns the condition code for instruction in IT block 43 unsigned getITCC() { 44 unsigned CC = ARMCC::AL; 45 if (instrInITBlock()) 46 CC = ITStates.back(); 47 return CC; 48 } 49 50 // Advances the IT block state to the next T or E 51 void advanceITState() { 52 ITStates.pop_back(); 53 } 54 55 // Returns true if the current instruction is in an IT block 56 bool instrInITBlock() { 57 return !ITStates.empty(); 58 } 59 60 // Returns true if current instruction is the last instruction in an IT block 61 bool instrLastInITBlock() { 62 return ITStates.size() == 1; 63 } 64 65 // Called when decoding an IT instruction. Sets the IT state for the following 66 // instructions that for the IT block. Firstcond and Mask correspond to the 67 // fields in the IT instruction encoding. 68 void setITState(char Firstcond, char Mask) { 69 // (3 - the number of trailing zeros) is the number of then / else. 70 unsigned CondBit0 = Firstcond & 1; 71 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 72 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 73 assert(NumTZ <= 3 && "Invalid IT mask!"); 74 // push condition codes onto the stack the correct order for the pops 75 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 76 bool T = ((Mask >> Pos) & 1) == CondBit0; 77 if (T) 78 ITStates.push_back(CCBits); 79 else 80 ITStates.push_back(CCBits ^ 1); 81 } 82 ITStates.push_back(CCBits); 83 } 84 85 private: 86 std::vector<unsigned char> ITStates; 87 }; 88 89 /// ARM disassembler for all ARM platforms. 90 class ARMDisassembler : public MCDisassembler { 91 public: 92 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 93 MCDisassembler(STI, Ctx) { 94 } 95 96 ~ARMDisassembler() override = default; 97 98 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 99 ArrayRef<uint8_t> Bytes, uint64_t Address, 100 raw_ostream &VStream, 101 raw_ostream &CStream) const override; 102 }; 103 104 /// Thumb disassembler for all Thumb platforms. 105 class ThumbDisassembler : public MCDisassembler { 106 public: 107 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 108 MCDisassembler(STI, Ctx) { 109 } 110 111 ~ThumbDisassembler() override = default; 112 113 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 114 ArrayRef<uint8_t> Bytes, uint64_t Address, 115 raw_ostream &VStream, 116 raw_ostream &CStream) const override; 117 118 private: 119 mutable ITStatus ITBlock; 120 DecodeStatus AddThumbPredicate(MCInst&) const; 121 void UpdateThumbVFPPredicate(MCInst&) const; 122 }; 123 124 } // end anonymous namespace 125 126 static bool Check(DecodeStatus &Out, DecodeStatus In) { 127 switch (In) { 128 case MCDisassembler::Success: 129 // Out stays the same. 130 return true; 131 case MCDisassembler::SoftFail: 132 Out = In; 133 return true; 134 case MCDisassembler::Fail: 135 Out = In; 136 return false; 137 } 138 llvm_unreachable("Invalid DecodeStatus!"); 139 } 140 141 // Forward declare these because the autogenerated code will reference them. 142 // Definitions are further down. 143 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 146 unsigned RegNo, uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 149 unsigned RegNo, uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 174 unsigned RegNo, uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 188 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 193 unsigned Insn, 194 uint64_t Address, 195 const void *Decoder); 196 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 203 uint64_t Address, const void *Decoder); 204 205 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 206 unsigned Insn, 207 uint64_t Adddress, 208 const void *Decoder); 209 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 322 uint64_t Address, const void *Decoder); 323 324 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void* Decoder); 346 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void* Decoder); 348 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void* Decoder); 350 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 397 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 402 #include "ARMGenDisassemblerTables.inc" 403 404 static MCDisassembler *createARMDisassembler(const Target &T, 405 const MCSubtargetInfo &STI, 406 MCContext &Ctx) { 407 return new ARMDisassembler(STI, Ctx); 408 } 409 410 static MCDisassembler *createThumbDisassembler(const Target &T, 411 const MCSubtargetInfo &STI, 412 MCContext &Ctx) { 413 return new ThumbDisassembler(STI, Ctx); 414 } 415 416 // Post-decoding checks 417 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 418 uint64_t Address, raw_ostream &OS, 419 raw_ostream &CS, 420 uint32_t Insn, 421 DecodeStatus Result) { 422 switch (MI.getOpcode()) { 423 case ARM::HVC: { 424 // HVC is undefined if condition = 0xf otherwise upredictable 425 // if condition != 0xe 426 uint32_t Cond = (Insn >> 28) & 0xF; 427 if (Cond == 0xF) 428 return MCDisassembler::Fail; 429 if (Cond != 0xE) 430 return MCDisassembler::SoftFail; 431 return Result; 432 } 433 default: return Result; 434 } 435 } 436 437 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 438 ArrayRef<uint8_t> Bytes, 439 uint64_t Address, raw_ostream &OS, 440 raw_ostream &CS) const { 441 CommentStream = &CS; 442 443 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 444 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 445 "mode!"); 446 447 // We want to read exactly 4 bytes of data. 448 if (Bytes.size() < 4) { 449 Size = 0; 450 return MCDisassembler::Fail; 451 } 452 453 // Encoded as a small-endian 32-bit word in the stream. 454 uint32_t Insn = 455 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 456 457 // Calling the auto-generated decoder function. 458 DecodeStatus Result = 459 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 460 if (Result != MCDisassembler::Fail) { 461 Size = 4; 462 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 463 } 464 465 struct DecodeTable { 466 const uint8_t *P; 467 bool DecodePred; 468 }; 469 470 const DecodeTable Tables[] = { 471 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 472 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 473 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 474 {DecoderTablev8Crypto32, false}, 475 }; 476 477 for (auto Table : Tables) { 478 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 479 if (Result != MCDisassembler::Fail) { 480 Size = 4; 481 // Add a fake predicate operand, because we share these instruction 482 // definitions with Thumb2 where these instructions are predicable. 483 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 484 return MCDisassembler::Fail; 485 return Result; 486 } 487 } 488 489 Result = 490 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 491 if (Result != MCDisassembler::Fail) { 492 Size = 4; 493 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 494 } 495 496 Size = 4; 497 return MCDisassembler::Fail; 498 } 499 500 namespace llvm { 501 502 extern const MCInstrDesc ARMInsts[]; 503 504 } // end namespace llvm 505 506 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 507 /// immediate Value in the MCInst. The immediate Value has had any PC 508 /// adjustment made by the caller. If the instruction is a branch instruction 509 /// then isBranch is true, else false. If the getOpInfo() function was set as 510 /// part of the setupForSymbolicDisassembly() call then that function is called 511 /// to get any symbolic information at the Address for this instruction. If 512 /// that returns non-zero then the symbolic information it returns is used to 513 /// create an MCExpr and that is added as an operand to the MCInst. If 514 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 515 /// Value is done and if a symbol is found an MCExpr is created with that, else 516 /// an MCExpr with Value is created. This function returns true if it adds an 517 /// operand to the MCInst and false otherwise. 518 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 519 bool isBranch, uint64_t InstSize, 520 MCInst &MI, const void *Decoder) { 521 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 522 // FIXME: Does it make sense for value to be negative? 523 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 524 /* Offset */ 0, InstSize); 525 } 526 527 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 528 /// referenced by a load instruction with the base register that is the Pc. 529 /// These can often be values in a literal pool near the Address of the 530 /// instruction. The Address of the instruction and its immediate Value are 531 /// used as a possible literal pool entry. The SymbolLookUp call back will 532 /// return the name of a symbol referenced by the literal pool's entry if 533 /// the referenced address is that of a symbol. Or it will return a pointer to 534 /// a literal 'C' string if the referenced address of the literal pool's entry 535 /// is an address into a section with 'C' string literals. 536 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 537 const void *Decoder) { 538 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 539 Dis->tryAddingPcLoadReferenceComment(Value, Address); 540 } 541 542 // Thumb1 instructions don't have explicit S bits. Rather, they 543 // implicitly set CPSR. Since it's not represented in the encoding, the 544 // auto-generated decoder won't inject the CPSR operand. We need to fix 545 // that as a post-pass. 546 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 547 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 548 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 549 MCInst::iterator I = MI.begin(); 550 for (unsigned i = 0; i < NumOps; ++i, ++I) { 551 if (I == MI.end()) break; 552 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 553 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 554 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 555 return; 556 } 557 } 558 559 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 560 } 561 562 // Most Thumb instructions don't have explicit predicates in the 563 // encoding, but rather get their predicates from IT context. We need 564 // to fix up the predicate operands using this context information as a 565 // post-pass. 566 MCDisassembler::DecodeStatus 567 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 568 MCDisassembler::DecodeStatus S = Success; 569 570 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 571 572 // A few instructions actually have predicates encoded in them. Don't 573 // try to overwrite it if we're seeing one of those. 574 switch (MI.getOpcode()) { 575 case ARM::tBcc: 576 case ARM::t2Bcc: 577 case ARM::tCBZ: 578 case ARM::tCBNZ: 579 case ARM::tCPS: 580 case ARM::t2CPS3p: 581 case ARM::t2CPS2p: 582 case ARM::t2CPS1p: 583 case ARM::tMOVSr: 584 case ARM::tSETEND: 585 // Some instructions (mostly conditional branches) are not 586 // allowed in IT blocks. 587 if (ITBlock.instrInITBlock()) 588 S = SoftFail; 589 else 590 return Success; 591 break; 592 case ARM::t2HINT: 593 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 594 S = SoftFail; 595 break; 596 case ARM::tB: 597 case ARM::t2B: 598 case ARM::t2TBB: 599 case ARM::t2TBH: 600 // Some instructions (mostly unconditional branches) can 601 // only appears at the end of, or outside of, an IT. 602 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 603 S = SoftFail; 604 break; 605 default: 606 break; 607 } 608 609 // If we're in an IT block, base the predicate on that. Otherwise, 610 // assume a predicate of AL. 611 unsigned CC; 612 CC = ITBlock.getITCC(); 613 if (CC == 0xF) 614 CC = ARMCC::AL; 615 if (ITBlock.instrInITBlock()) 616 ITBlock.advanceITState(); 617 618 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 619 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 620 MCInst::iterator I = MI.begin(); 621 for (unsigned i = 0; i < NumOps; ++i, ++I) { 622 if (I == MI.end()) break; 623 if (OpInfo[i].isPredicate()) { 624 I = MI.insert(I, MCOperand::createImm(CC)); 625 ++I; 626 if (CC == ARMCC::AL) 627 MI.insert(I, MCOperand::createReg(0)); 628 else 629 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 630 return S; 631 } 632 } 633 634 I = MI.insert(I, MCOperand::createImm(CC)); 635 ++I; 636 if (CC == ARMCC::AL) 637 MI.insert(I, MCOperand::createReg(0)); 638 else 639 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 640 641 return S; 642 } 643 644 // Thumb VFP instructions are a special case. Because we share their 645 // encodings between ARM and Thumb modes, and they are predicable in ARM 646 // mode, the auto-generated decoder will give them an (incorrect) 647 // predicate operand. We need to rewrite these operands based on the IT 648 // context as a post-pass. 649 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 650 unsigned CC; 651 CC = ITBlock.getITCC(); 652 if (ITBlock.instrInITBlock()) 653 ITBlock.advanceITState(); 654 655 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 656 MCInst::iterator I = MI.begin(); 657 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 658 for (unsigned i = 0; i < NumOps; ++i, ++I) { 659 if (OpInfo[i].isPredicate() ) { 660 I->setImm(CC); 661 ++I; 662 if (CC == ARMCC::AL) 663 I->setReg(0); 664 else 665 I->setReg(ARM::CPSR); 666 return; 667 } 668 } 669 } 670 671 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 672 ArrayRef<uint8_t> Bytes, 673 uint64_t Address, 674 raw_ostream &OS, 675 raw_ostream &CS) const { 676 CommentStream = &CS; 677 678 assert(STI.getFeatureBits()[ARM::ModeThumb] && 679 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 680 681 // We want to read exactly 2 bytes of data. 682 if (Bytes.size() < 2) { 683 Size = 0; 684 return MCDisassembler::Fail; 685 } 686 687 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 688 DecodeStatus Result = 689 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 690 if (Result != MCDisassembler::Fail) { 691 Size = 2; 692 Check(Result, AddThumbPredicate(MI)); 693 return Result; 694 } 695 696 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 697 STI); 698 if (Result) { 699 Size = 2; 700 bool InITBlock = ITBlock.instrInITBlock(); 701 Check(Result, AddThumbPredicate(MI)); 702 AddThumb1SBit(MI, InITBlock); 703 return Result; 704 } 705 706 Result = 707 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 708 if (Result != MCDisassembler::Fail) { 709 Size = 2; 710 711 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 712 // the Thumb predicate. 713 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 714 Result = MCDisassembler::SoftFail; 715 716 Check(Result, AddThumbPredicate(MI)); 717 718 // If we find an IT instruction, we need to parse its condition 719 // code and mask operands so that we can apply them correctly 720 // to the subsequent instructions. 721 if (MI.getOpcode() == ARM::t2IT) { 722 723 unsigned Firstcond = MI.getOperand(0).getImm(); 724 unsigned Mask = MI.getOperand(1).getImm(); 725 ITBlock.setITState(Firstcond, Mask); 726 } 727 728 return Result; 729 } 730 731 // We want to read exactly 4 bytes of data. 732 if (Bytes.size() < 4) { 733 Size = 0; 734 return MCDisassembler::Fail; 735 } 736 737 uint32_t Insn32 = 738 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 739 Result = 740 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 741 if (Result != MCDisassembler::Fail) { 742 Size = 4; 743 bool InITBlock = ITBlock.instrInITBlock(); 744 Check(Result, AddThumbPredicate(MI)); 745 AddThumb1SBit(MI, InITBlock); 746 return Result; 747 } 748 749 Result = 750 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 751 if (Result != MCDisassembler::Fail) { 752 Size = 4; 753 Check(Result, AddThumbPredicate(MI)); 754 return Result; 755 } 756 757 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 758 Result = 759 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 760 if (Result != MCDisassembler::Fail) { 761 Size = 4; 762 UpdateThumbVFPPredicate(MI); 763 return Result; 764 } 765 } 766 767 Result = 768 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 769 if (Result != MCDisassembler::Fail) { 770 Size = 4; 771 return Result; 772 } 773 774 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 775 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 776 STI); 777 if (Result != MCDisassembler::Fail) { 778 Size = 4; 779 Check(Result, AddThumbPredicate(MI)); 780 return Result; 781 } 782 } 783 784 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 785 uint32_t NEONLdStInsn = Insn32; 786 NEONLdStInsn &= 0xF0FFFFFF; 787 NEONLdStInsn |= 0x04000000; 788 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 789 Address, this, STI); 790 if (Result != MCDisassembler::Fail) { 791 Size = 4; 792 Check(Result, AddThumbPredicate(MI)); 793 return Result; 794 } 795 } 796 797 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 798 uint32_t NEONDataInsn = Insn32; 799 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 800 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 801 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 802 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 803 Address, this, STI); 804 if (Result != MCDisassembler::Fail) { 805 Size = 4; 806 Check(Result, AddThumbPredicate(MI)); 807 return Result; 808 } 809 810 uint32_t NEONCryptoInsn = Insn32; 811 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 812 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 813 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 814 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 815 Address, this, STI); 816 if (Result != MCDisassembler::Fail) { 817 Size = 4; 818 return Result; 819 } 820 821 uint32_t NEONv8Insn = Insn32; 822 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 823 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 824 this, STI); 825 if (Result != MCDisassembler::Fail) { 826 Size = 4; 827 return Result; 828 } 829 } 830 831 Result = 832 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 833 if (Result != MCDisassembler::Fail) { 834 Size = 4; 835 Check(Result, AddThumbPredicate(MI)); 836 return Result; 837 } 838 839 Size = 0; 840 return MCDisassembler::Fail; 841 } 842 843 extern "C" void LLVMInitializeARMDisassembler() { 844 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 845 createARMDisassembler); 846 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 847 createARMDisassembler); 848 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 849 createThumbDisassembler); 850 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 851 createThumbDisassembler); 852 } 853 854 static const uint16_t GPRDecoderTable[] = { 855 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 856 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 857 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 858 ARM::R12, ARM::SP, ARM::LR, ARM::PC 859 }; 860 861 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 862 uint64_t Address, const void *Decoder) { 863 if (RegNo > 15) 864 return MCDisassembler::Fail; 865 866 unsigned Register = GPRDecoderTable[RegNo]; 867 Inst.addOperand(MCOperand::createReg(Register)); 868 return MCDisassembler::Success; 869 } 870 871 static DecodeStatus 872 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 873 uint64_t Address, const void *Decoder) { 874 DecodeStatus S = MCDisassembler::Success; 875 876 if (RegNo == 15) 877 S = MCDisassembler::SoftFail; 878 879 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 880 881 return S; 882 } 883 884 static DecodeStatus 885 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 886 uint64_t Address, const void *Decoder) { 887 DecodeStatus S = MCDisassembler::Success; 888 889 if (RegNo == 15) 890 { 891 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 892 return MCDisassembler::Success; 893 } 894 895 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 896 return S; 897 } 898 899 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 900 uint64_t Address, const void *Decoder) { 901 if (RegNo > 7) 902 return MCDisassembler::Fail; 903 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 904 } 905 906 static const uint16_t GPRPairDecoderTable[] = { 907 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 908 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 909 }; 910 911 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 912 uint64_t Address, const void *Decoder) { 913 DecodeStatus S = MCDisassembler::Success; 914 915 if (RegNo > 13) 916 return MCDisassembler::Fail; 917 918 if ((RegNo & 1) || RegNo == 0xe) 919 S = MCDisassembler::SoftFail; 920 921 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 922 Inst.addOperand(MCOperand::createReg(RegisterPair)); 923 return S; 924 } 925 926 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 927 uint64_t Address, const void *Decoder) { 928 unsigned Register = 0; 929 switch (RegNo) { 930 case 0: 931 Register = ARM::R0; 932 break; 933 case 1: 934 Register = ARM::R1; 935 break; 936 case 2: 937 Register = ARM::R2; 938 break; 939 case 3: 940 Register = ARM::R3; 941 break; 942 case 9: 943 Register = ARM::R9; 944 break; 945 case 12: 946 Register = ARM::R12; 947 break; 948 default: 949 return MCDisassembler::Fail; 950 } 951 952 Inst.addOperand(MCOperand::createReg(Register)); 953 return MCDisassembler::Success; 954 } 955 956 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 957 uint64_t Address, const void *Decoder) { 958 DecodeStatus S = MCDisassembler::Success; 959 960 const FeatureBitset &featureBits = 961 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 962 963 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 964 S = MCDisassembler::SoftFail; 965 966 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 967 return S; 968 } 969 970 static const uint16_t SPRDecoderTable[] = { 971 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 972 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 973 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 974 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 975 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 976 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 977 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 978 ARM::S28, ARM::S29, ARM::S30, ARM::S31 979 }; 980 981 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 982 uint64_t Address, const void *Decoder) { 983 if (RegNo > 31) 984 return MCDisassembler::Fail; 985 986 unsigned Register = SPRDecoderTable[RegNo]; 987 Inst.addOperand(MCOperand::createReg(Register)); 988 return MCDisassembler::Success; 989 } 990 991 static const uint16_t DPRDecoderTable[] = { 992 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 993 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 994 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 995 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 996 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 997 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 998 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 999 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1000 }; 1001 1002 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1003 uint64_t Address, const void *Decoder) { 1004 const FeatureBitset &featureBits = 1005 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1006 1007 bool hasD16 = featureBits[ARM::FeatureD16]; 1008 1009 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1010 return MCDisassembler::Fail; 1011 1012 unsigned Register = DPRDecoderTable[RegNo]; 1013 Inst.addOperand(MCOperand::createReg(Register)); 1014 return MCDisassembler::Success; 1015 } 1016 1017 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1018 uint64_t Address, const void *Decoder) { 1019 if (RegNo > 7) 1020 return MCDisassembler::Fail; 1021 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1022 } 1023 1024 static DecodeStatus 1025 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1026 uint64_t Address, const void *Decoder) { 1027 if (RegNo > 15) 1028 return MCDisassembler::Fail; 1029 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1030 } 1031 1032 static const uint16_t QPRDecoderTable[] = { 1033 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1034 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1035 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1036 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1037 }; 1038 1039 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1040 uint64_t Address, const void *Decoder) { 1041 if (RegNo > 31 || (RegNo & 1) != 0) 1042 return MCDisassembler::Fail; 1043 RegNo >>= 1; 1044 1045 unsigned Register = QPRDecoderTable[RegNo]; 1046 Inst.addOperand(MCOperand::createReg(Register)); 1047 return MCDisassembler::Success; 1048 } 1049 1050 static const uint16_t DPairDecoderTable[] = { 1051 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1052 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1053 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1054 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1055 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1056 ARM::Q15 1057 }; 1058 1059 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1060 uint64_t Address, const void *Decoder) { 1061 if (RegNo > 30) 1062 return MCDisassembler::Fail; 1063 1064 unsigned Register = DPairDecoderTable[RegNo]; 1065 Inst.addOperand(MCOperand::createReg(Register)); 1066 return MCDisassembler::Success; 1067 } 1068 1069 static const uint16_t DPairSpacedDecoderTable[] = { 1070 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1071 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1072 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1073 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1074 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1075 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1076 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1077 ARM::D28_D30, ARM::D29_D31 1078 }; 1079 1080 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1081 unsigned RegNo, 1082 uint64_t Address, 1083 const void *Decoder) { 1084 if (RegNo > 29) 1085 return MCDisassembler::Fail; 1086 1087 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1088 Inst.addOperand(MCOperand::createReg(Register)); 1089 return MCDisassembler::Success; 1090 } 1091 1092 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1093 uint64_t Address, const void *Decoder) { 1094 if (Val == 0xF) return MCDisassembler::Fail; 1095 // AL predicate is not allowed on Thumb1 branches. 1096 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1097 return MCDisassembler::Fail; 1098 Inst.addOperand(MCOperand::createImm(Val)); 1099 if (Val == ARMCC::AL) { 1100 Inst.addOperand(MCOperand::createReg(0)); 1101 } else 1102 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1103 return MCDisassembler::Success; 1104 } 1105 1106 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1107 uint64_t Address, const void *Decoder) { 1108 if (Val) 1109 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1110 else 1111 Inst.addOperand(MCOperand::createReg(0)); 1112 return MCDisassembler::Success; 1113 } 1114 1115 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1116 uint64_t Address, const void *Decoder) { 1117 DecodeStatus S = MCDisassembler::Success; 1118 1119 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1120 unsigned type = fieldFromInstruction(Val, 5, 2); 1121 unsigned imm = fieldFromInstruction(Val, 7, 5); 1122 1123 // Register-immediate 1124 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1125 return MCDisassembler::Fail; 1126 1127 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1128 switch (type) { 1129 case 0: 1130 Shift = ARM_AM::lsl; 1131 break; 1132 case 1: 1133 Shift = ARM_AM::lsr; 1134 break; 1135 case 2: 1136 Shift = ARM_AM::asr; 1137 break; 1138 case 3: 1139 Shift = ARM_AM::ror; 1140 break; 1141 } 1142 1143 if (Shift == ARM_AM::ror && imm == 0) 1144 Shift = ARM_AM::rrx; 1145 1146 unsigned Op = Shift | (imm << 3); 1147 Inst.addOperand(MCOperand::createImm(Op)); 1148 1149 return S; 1150 } 1151 1152 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1153 uint64_t Address, const void *Decoder) { 1154 DecodeStatus S = MCDisassembler::Success; 1155 1156 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1157 unsigned type = fieldFromInstruction(Val, 5, 2); 1158 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1159 1160 // Register-register 1161 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1162 return MCDisassembler::Fail; 1163 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1164 return MCDisassembler::Fail; 1165 1166 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1167 switch (type) { 1168 case 0: 1169 Shift = ARM_AM::lsl; 1170 break; 1171 case 1: 1172 Shift = ARM_AM::lsr; 1173 break; 1174 case 2: 1175 Shift = ARM_AM::asr; 1176 break; 1177 case 3: 1178 Shift = ARM_AM::ror; 1179 break; 1180 } 1181 1182 Inst.addOperand(MCOperand::createImm(Shift)); 1183 1184 return S; 1185 } 1186 1187 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1188 uint64_t Address, const void *Decoder) { 1189 DecodeStatus S = MCDisassembler::Success; 1190 1191 bool NeedDisjointWriteback = false; 1192 unsigned WritebackReg = 0; 1193 switch (Inst.getOpcode()) { 1194 default: 1195 break; 1196 case ARM::LDMIA_UPD: 1197 case ARM::LDMDB_UPD: 1198 case ARM::LDMIB_UPD: 1199 case ARM::LDMDA_UPD: 1200 case ARM::t2LDMIA_UPD: 1201 case ARM::t2LDMDB_UPD: 1202 case ARM::t2STMIA_UPD: 1203 case ARM::t2STMDB_UPD: 1204 NeedDisjointWriteback = true; 1205 WritebackReg = Inst.getOperand(0).getReg(); 1206 break; 1207 } 1208 1209 // Empty register lists are not allowed. 1210 if (Val == 0) return MCDisassembler::Fail; 1211 for (unsigned i = 0; i < 16; ++i) { 1212 if (Val & (1 << i)) { 1213 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1214 return MCDisassembler::Fail; 1215 // Writeback not allowed if Rn is in the target list. 1216 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1217 Check(S, MCDisassembler::SoftFail); 1218 } 1219 } 1220 1221 return S; 1222 } 1223 1224 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1225 uint64_t Address, const void *Decoder) { 1226 DecodeStatus S = MCDisassembler::Success; 1227 1228 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1229 unsigned regs = fieldFromInstruction(Val, 0, 8); 1230 1231 // In case of unpredictable encoding, tweak the operands. 1232 if (regs == 0 || (Vd + regs) > 32) { 1233 regs = Vd + regs > 32 ? 32 - Vd : regs; 1234 regs = std::max( 1u, regs); 1235 S = MCDisassembler::SoftFail; 1236 } 1237 1238 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1239 return MCDisassembler::Fail; 1240 for (unsigned i = 0; i < (regs - 1); ++i) { 1241 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1242 return MCDisassembler::Fail; 1243 } 1244 1245 return S; 1246 } 1247 1248 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1249 uint64_t Address, const void *Decoder) { 1250 DecodeStatus S = MCDisassembler::Success; 1251 1252 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1253 unsigned regs = fieldFromInstruction(Val, 1, 7); 1254 1255 // In case of unpredictable encoding, tweak the operands. 1256 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1257 regs = Vd + regs > 32 ? 32 - Vd : regs; 1258 regs = std::max( 1u, regs); 1259 regs = std::min(16u, regs); 1260 S = MCDisassembler::SoftFail; 1261 } 1262 1263 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1264 return MCDisassembler::Fail; 1265 for (unsigned i = 0; i < (regs - 1); ++i) { 1266 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1267 return MCDisassembler::Fail; 1268 } 1269 1270 return S; 1271 } 1272 1273 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1274 uint64_t Address, const void *Decoder) { 1275 // This operand encodes a mask of contiguous zeros between a specified MSB 1276 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1277 // the mask of all bits LSB-and-lower, and then xor them to create 1278 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1279 // create the final mask. 1280 unsigned msb = fieldFromInstruction(Val, 5, 5); 1281 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1282 1283 DecodeStatus S = MCDisassembler::Success; 1284 if (lsb > msb) { 1285 Check(S, MCDisassembler::SoftFail); 1286 // The check above will cause the warning for the "potentially undefined 1287 // instruction encoding" but we can't build a bad MCOperand value here 1288 // with a lsb > msb or else printing the MCInst will cause a crash. 1289 lsb = msb; 1290 } 1291 1292 uint32_t msb_mask = 0xFFFFFFFF; 1293 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1294 uint32_t lsb_mask = (1U << lsb) - 1; 1295 1296 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1297 return S; 1298 } 1299 1300 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1301 uint64_t Address, const void *Decoder) { 1302 DecodeStatus S = MCDisassembler::Success; 1303 1304 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1305 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1306 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1307 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1308 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1309 unsigned U = fieldFromInstruction(Insn, 23, 1); 1310 1311 switch (Inst.getOpcode()) { 1312 case ARM::LDC_OFFSET: 1313 case ARM::LDC_PRE: 1314 case ARM::LDC_POST: 1315 case ARM::LDC_OPTION: 1316 case ARM::LDCL_OFFSET: 1317 case ARM::LDCL_PRE: 1318 case ARM::LDCL_POST: 1319 case ARM::LDCL_OPTION: 1320 case ARM::STC_OFFSET: 1321 case ARM::STC_PRE: 1322 case ARM::STC_POST: 1323 case ARM::STC_OPTION: 1324 case ARM::STCL_OFFSET: 1325 case ARM::STCL_PRE: 1326 case ARM::STCL_POST: 1327 case ARM::STCL_OPTION: 1328 case ARM::t2LDC_OFFSET: 1329 case ARM::t2LDC_PRE: 1330 case ARM::t2LDC_POST: 1331 case ARM::t2LDC_OPTION: 1332 case ARM::t2LDCL_OFFSET: 1333 case ARM::t2LDCL_PRE: 1334 case ARM::t2LDCL_POST: 1335 case ARM::t2LDCL_OPTION: 1336 case ARM::t2STC_OFFSET: 1337 case ARM::t2STC_PRE: 1338 case ARM::t2STC_POST: 1339 case ARM::t2STC_OPTION: 1340 case ARM::t2STCL_OFFSET: 1341 case ARM::t2STCL_PRE: 1342 case ARM::t2STCL_POST: 1343 case ARM::t2STCL_OPTION: 1344 if (coproc == 0xA || coproc == 0xB) 1345 return MCDisassembler::Fail; 1346 break; 1347 default: 1348 break; 1349 } 1350 1351 const FeatureBitset &featureBits = 1352 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1353 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1354 return MCDisassembler::Fail; 1355 1356 Inst.addOperand(MCOperand::createImm(coproc)); 1357 Inst.addOperand(MCOperand::createImm(CRd)); 1358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1359 return MCDisassembler::Fail; 1360 1361 switch (Inst.getOpcode()) { 1362 case ARM::t2LDC2_OFFSET: 1363 case ARM::t2LDC2L_OFFSET: 1364 case ARM::t2LDC2_PRE: 1365 case ARM::t2LDC2L_PRE: 1366 case ARM::t2STC2_OFFSET: 1367 case ARM::t2STC2L_OFFSET: 1368 case ARM::t2STC2_PRE: 1369 case ARM::t2STC2L_PRE: 1370 case ARM::LDC2_OFFSET: 1371 case ARM::LDC2L_OFFSET: 1372 case ARM::LDC2_PRE: 1373 case ARM::LDC2L_PRE: 1374 case ARM::STC2_OFFSET: 1375 case ARM::STC2L_OFFSET: 1376 case ARM::STC2_PRE: 1377 case ARM::STC2L_PRE: 1378 case ARM::t2LDC_OFFSET: 1379 case ARM::t2LDCL_OFFSET: 1380 case ARM::t2LDC_PRE: 1381 case ARM::t2LDCL_PRE: 1382 case ARM::t2STC_OFFSET: 1383 case ARM::t2STCL_OFFSET: 1384 case ARM::t2STC_PRE: 1385 case ARM::t2STCL_PRE: 1386 case ARM::LDC_OFFSET: 1387 case ARM::LDCL_OFFSET: 1388 case ARM::LDC_PRE: 1389 case ARM::LDCL_PRE: 1390 case ARM::STC_OFFSET: 1391 case ARM::STCL_OFFSET: 1392 case ARM::STC_PRE: 1393 case ARM::STCL_PRE: 1394 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1395 Inst.addOperand(MCOperand::createImm(imm)); 1396 break; 1397 case ARM::t2LDC2_POST: 1398 case ARM::t2LDC2L_POST: 1399 case ARM::t2STC2_POST: 1400 case ARM::t2STC2L_POST: 1401 case ARM::LDC2_POST: 1402 case ARM::LDC2L_POST: 1403 case ARM::STC2_POST: 1404 case ARM::STC2L_POST: 1405 case ARM::t2LDC_POST: 1406 case ARM::t2LDCL_POST: 1407 case ARM::t2STC_POST: 1408 case ARM::t2STCL_POST: 1409 case ARM::LDC_POST: 1410 case ARM::LDCL_POST: 1411 case ARM::STC_POST: 1412 case ARM::STCL_POST: 1413 imm |= U << 8; 1414 LLVM_FALLTHROUGH; 1415 default: 1416 // The 'option' variant doesn't encode 'U' in the immediate since 1417 // the immediate is unsigned [0,255]. 1418 Inst.addOperand(MCOperand::createImm(imm)); 1419 break; 1420 } 1421 1422 switch (Inst.getOpcode()) { 1423 case ARM::LDC_OFFSET: 1424 case ARM::LDC_PRE: 1425 case ARM::LDC_POST: 1426 case ARM::LDC_OPTION: 1427 case ARM::LDCL_OFFSET: 1428 case ARM::LDCL_PRE: 1429 case ARM::LDCL_POST: 1430 case ARM::LDCL_OPTION: 1431 case ARM::STC_OFFSET: 1432 case ARM::STC_PRE: 1433 case ARM::STC_POST: 1434 case ARM::STC_OPTION: 1435 case ARM::STCL_OFFSET: 1436 case ARM::STCL_PRE: 1437 case ARM::STCL_POST: 1438 case ARM::STCL_OPTION: 1439 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1440 return MCDisassembler::Fail; 1441 break; 1442 default: 1443 break; 1444 } 1445 1446 return S; 1447 } 1448 1449 static DecodeStatus 1450 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1451 uint64_t Address, const void *Decoder) { 1452 DecodeStatus S = MCDisassembler::Success; 1453 1454 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1455 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1456 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1457 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1458 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1459 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1460 unsigned P = fieldFromInstruction(Insn, 24, 1); 1461 unsigned W = fieldFromInstruction(Insn, 21, 1); 1462 1463 // On stores, the writeback operand precedes Rt. 1464 switch (Inst.getOpcode()) { 1465 case ARM::STR_POST_IMM: 1466 case ARM::STR_POST_REG: 1467 case ARM::STRB_POST_IMM: 1468 case ARM::STRB_POST_REG: 1469 case ARM::STRT_POST_REG: 1470 case ARM::STRT_POST_IMM: 1471 case ARM::STRBT_POST_REG: 1472 case ARM::STRBT_POST_IMM: 1473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1474 return MCDisassembler::Fail; 1475 break; 1476 default: 1477 break; 1478 } 1479 1480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1481 return MCDisassembler::Fail; 1482 1483 // On loads, the writeback operand comes after Rt. 1484 switch (Inst.getOpcode()) { 1485 case ARM::LDR_POST_IMM: 1486 case ARM::LDR_POST_REG: 1487 case ARM::LDRB_POST_IMM: 1488 case ARM::LDRB_POST_REG: 1489 case ARM::LDRBT_POST_REG: 1490 case ARM::LDRBT_POST_IMM: 1491 case ARM::LDRT_POST_REG: 1492 case ARM::LDRT_POST_IMM: 1493 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1494 return MCDisassembler::Fail; 1495 break; 1496 default: 1497 break; 1498 } 1499 1500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1501 return MCDisassembler::Fail; 1502 1503 ARM_AM::AddrOpc Op = ARM_AM::add; 1504 if (!fieldFromInstruction(Insn, 23, 1)) 1505 Op = ARM_AM::sub; 1506 1507 bool writeback = (P == 0) || (W == 1); 1508 unsigned idx_mode = 0; 1509 if (P && writeback) 1510 idx_mode = ARMII::IndexModePre; 1511 else if (!P && writeback) 1512 idx_mode = ARMII::IndexModePost; 1513 1514 if (writeback && (Rn == 15 || Rn == Rt)) 1515 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1516 1517 if (reg) { 1518 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1519 return MCDisassembler::Fail; 1520 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1521 switch( fieldFromInstruction(Insn, 5, 2)) { 1522 case 0: 1523 Opc = ARM_AM::lsl; 1524 break; 1525 case 1: 1526 Opc = ARM_AM::lsr; 1527 break; 1528 case 2: 1529 Opc = ARM_AM::asr; 1530 break; 1531 case 3: 1532 Opc = ARM_AM::ror; 1533 break; 1534 default: 1535 return MCDisassembler::Fail; 1536 } 1537 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1538 if (Opc == ARM_AM::ror && amt == 0) 1539 Opc = ARM_AM::rrx; 1540 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1541 1542 Inst.addOperand(MCOperand::createImm(imm)); 1543 } else { 1544 Inst.addOperand(MCOperand::createReg(0)); 1545 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1546 Inst.addOperand(MCOperand::createImm(tmp)); 1547 } 1548 1549 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1550 return MCDisassembler::Fail; 1551 1552 return S; 1553 } 1554 1555 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1556 uint64_t Address, const void *Decoder) { 1557 DecodeStatus S = MCDisassembler::Success; 1558 1559 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1560 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1561 unsigned type = fieldFromInstruction(Val, 5, 2); 1562 unsigned imm = fieldFromInstruction(Val, 7, 5); 1563 unsigned U = fieldFromInstruction(Val, 12, 1); 1564 1565 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1566 switch (type) { 1567 case 0: 1568 ShOp = ARM_AM::lsl; 1569 break; 1570 case 1: 1571 ShOp = ARM_AM::lsr; 1572 break; 1573 case 2: 1574 ShOp = ARM_AM::asr; 1575 break; 1576 case 3: 1577 ShOp = ARM_AM::ror; 1578 break; 1579 } 1580 1581 if (ShOp == ARM_AM::ror && imm == 0) 1582 ShOp = ARM_AM::rrx; 1583 1584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1585 return MCDisassembler::Fail; 1586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1587 return MCDisassembler::Fail; 1588 unsigned shift; 1589 if (U) 1590 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1591 else 1592 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1593 Inst.addOperand(MCOperand::createImm(shift)); 1594 1595 return S; 1596 } 1597 1598 static DecodeStatus 1599 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1600 uint64_t Address, const void *Decoder) { 1601 DecodeStatus S = MCDisassembler::Success; 1602 1603 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1604 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1605 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1606 unsigned type = fieldFromInstruction(Insn, 22, 1); 1607 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1608 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1609 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1610 unsigned W = fieldFromInstruction(Insn, 21, 1); 1611 unsigned P = fieldFromInstruction(Insn, 24, 1); 1612 unsigned Rt2 = Rt + 1; 1613 1614 bool writeback = (W == 1) | (P == 0); 1615 1616 // For {LD,ST}RD, Rt must be even, else undefined. 1617 switch (Inst.getOpcode()) { 1618 case ARM::STRD: 1619 case ARM::STRD_PRE: 1620 case ARM::STRD_POST: 1621 case ARM::LDRD: 1622 case ARM::LDRD_PRE: 1623 case ARM::LDRD_POST: 1624 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1625 break; 1626 default: 1627 break; 1628 } 1629 switch (Inst.getOpcode()) { 1630 case ARM::STRD: 1631 case ARM::STRD_PRE: 1632 case ARM::STRD_POST: 1633 if (P == 0 && W == 1) 1634 S = MCDisassembler::SoftFail; 1635 1636 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1637 S = MCDisassembler::SoftFail; 1638 if (type && Rm == 15) 1639 S = MCDisassembler::SoftFail; 1640 if (Rt2 == 15) 1641 S = MCDisassembler::SoftFail; 1642 if (!type && fieldFromInstruction(Insn, 8, 4)) 1643 S = MCDisassembler::SoftFail; 1644 break; 1645 case ARM::STRH: 1646 case ARM::STRH_PRE: 1647 case ARM::STRH_POST: 1648 if (Rt == 15) 1649 S = MCDisassembler::SoftFail; 1650 if (writeback && (Rn == 15 || Rn == Rt)) 1651 S = MCDisassembler::SoftFail; 1652 if (!type && Rm == 15) 1653 S = MCDisassembler::SoftFail; 1654 break; 1655 case ARM::LDRD: 1656 case ARM::LDRD_PRE: 1657 case ARM::LDRD_POST: 1658 if (type && Rn == 15) { 1659 if (Rt2 == 15) 1660 S = MCDisassembler::SoftFail; 1661 break; 1662 } 1663 if (P == 0 && W == 1) 1664 S = MCDisassembler::SoftFail; 1665 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1666 S = MCDisassembler::SoftFail; 1667 if (!type && writeback && Rn == 15) 1668 S = MCDisassembler::SoftFail; 1669 if (writeback && (Rn == Rt || Rn == Rt2)) 1670 S = MCDisassembler::SoftFail; 1671 break; 1672 case ARM::LDRH: 1673 case ARM::LDRH_PRE: 1674 case ARM::LDRH_POST: 1675 if (type && Rn == 15) { 1676 if (Rt == 15) 1677 S = MCDisassembler::SoftFail; 1678 break; 1679 } 1680 if (Rt == 15) 1681 S = MCDisassembler::SoftFail; 1682 if (!type && Rm == 15) 1683 S = MCDisassembler::SoftFail; 1684 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1685 S = MCDisassembler::SoftFail; 1686 break; 1687 case ARM::LDRSH: 1688 case ARM::LDRSH_PRE: 1689 case ARM::LDRSH_POST: 1690 case ARM::LDRSB: 1691 case ARM::LDRSB_PRE: 1692 case ARM::LDRSB_POST: 1693 if (type && Rn == 15) { 1694 if (Rt == 15) 1695 S = MCDisassembler::SoftFail; 1696 break; 1697 } 1698 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1699 S = MCDisassembler::SoftFail; 1700 if (!type && (Rt == 15 || Rm == 15)) 1701 S = MCDisassembler::SoftFail; 1702 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1703 S = MCDisassembler::SoftFail; 1704 break; 1705 default: 1706 break; 1707 } 1708 1709 if (writeback) { // Writeback 1710 if (P) 1711 U |= ARMII::IndexModePre << 9; 1712 else 1713 U |= ARMII::IndexModePost << 9; 1714 1715 // On stores, the writeback operand precedes Rt. 1716 switch (Inst.getOpcode()) { 1717 case ARM::STRD: 1718 case ARM::STRD_PRE: 1719 case ARM::STRD_POST: 1720 case ARM::STRH: 1721 case ARM::STRH_PRE: 1722 case ARM::STRH_POST: 1723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1724 return MCDisassembler::Fail; 1725 break; 1726 default: 1727 break; 1728 } 1729 } 1730 1731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1732 return MCDisassembler::Fail; 1733 switch (Inst.getOpcode()) { 1734 case ARM::STRD: 1735 case ARM::STRD_PRE: 1736 case ARM::STRD_POST: 1737 case ARM::LDRD: 1738 case ARM::LDRD_PRE: 1739 case ARM::LDRD_POST: 1740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1741 return MCDisassembler::Fail; 1742 break; 1743 default: 1744 break; 1745 } 1746 1747 if (writeback) { 1748 // On loads, the writeback operand comes after Rt. 1749 switch (Inst.getOpcode()) { 1750 case ARM::LDRD: 1751 case ARM::LDRD_PRE: 1752 case ARM::LDRD_POST: 1753 case ARM::LDRH: 1754 case ARM::LDRH_PRE: 1755 case ARM::LDRH_POST: 1756 case ARM::LDRSH: 1757 case ARM::LDRSH_PRE: 1758 case ARM::LDRSH_POST: 1759 case ARM::LDRSB: 1760 case ARM::LDRSB_PRE: 1761 case ARM::LDRSB_POST: 1762 case ARM::LDRHTr: 1763 case ARM::LDRSBTr: 1764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1765 return MCDisassembler::Fail; 1766 break; 1767 default: 1768 break; 1769 } 1770 } 1771 1772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1773 return MCDisassembler::Fail; 1774 1775 if (type) { 1776 Inst.addOperand(MCOperand::createReg(0)); 1777 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1778 } else { 1779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1780 return MCDisassembler::Fail; 1781 Inst.addOperand(MCOperand::createImm(U)); 1782 } 1783 1784 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1785 return MCDisassembler::Fail; 1786 1787 return S; 1788 } 1789 1790 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1791 uint64_t Address, const void *Decoder) { 1792 DecodeStatus S = MCDisassembler::Success; 1793 1794 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1795 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1796 1797 switch (mode) { 1798 case 0: 1799 mode = ARM_AM::da; 1800 break; 1801 case 1: 1802 mode = ARM_AM::ia; 1803 break; 1804 case 2: 1805 mode = ARM_AM::db; 1806 break; 1807 case 3: 1808 mode = ARM_AM::ib; 1809 break; 1810 } 1811 1812 Inst.addOperand(MCOperand::createImm(mode)); 1813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1814 return MCDisassembler::Fail; 1815 1816 return S; 1817 } 1818 1819 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1820 uint64_t Address, const void *Decoder) { 1821 DecodeStatus S = MCDisassembler::Success; 1822 1823 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1824 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1825 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1826 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1827 1828 if (pred == 0xF) 1829 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1830 1831 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1832 return MCDisassembler::Fail; 1833 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1834 return MCDisassembler::Fail; 1835 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1836 return MCDisassembler::Fail; 1837 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1838 return MCDisassembler::Fail; 1839 return S; 1840 } 1841 1842 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1843 unsigned Insn, 1844 uint64_t Address, const void *Decoder) { 1845 DecodeStatus S = MCDisassembler::Success; 1846 1847 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1848 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1849 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1850 1851 if (pred == 0xF) { 1852 // Ambiguous with RFE and SRS 1853 switch (Inst.getOpcode()) { 1854 case ARM::LDMDA: 1855 Inst.setOpcode(ARM::RFEDA); 1856 break; 1857 case ARM::LDMDA_UPD: 1858 Inst.setOpcode(ARM::RFEDA_UPD); 1859 break; 1860 case ARM::LDMDB: 1861 Inst.setOpcode(ARM::RFEDB); 1862 break; 1863 case ARM::LDMDB_UPD: 1864 Inst.setOpcode(ARM::RFEDB_UPD); 1865 break; 1866 case ARM::LDMIA: 1867 Inst.setOpcode(ARM::RFEIA); 1868 break; 1869 case ARM::LDMIA_UPD: 1870 Inst.setOpcode(ARM::RFEIA_UPD); 1871 break; 1872 case ARM::LDMIB: 1873 Inst.setOpcode(ARM::RFEIB); 1874 break; 1875 case ARM::LDMIB_UPD: 1876 Inst.setOpcode(ARM::RFEIB_UPD); 1877 break; 1878 case ARM::STMDA: 1879 Inst.setOpcode(ARM::SRSDA); 1880 break; 1881 case ARM::STMDA_UPD: 1882 Inst.setOpcode(ARM::SRSDA_UPD); 1883 break; 1884 case ARM::STMDB: 1885 Inst.setOpcode(ARM::SRSDB); 1886 break; 1887 case ARM::STMDB_UPD: 1888 Inst.setOpcode(ARM::SRSDB_UPD); 1889 break; 1890 case ARM::STMIA: 1891 Inst.setOpcode(ARM::SRSIA); 1892 break; 1893 case ARM::STMIA_UPD: 1894 Inst.setOpcode(ARM::SRSIA_UPD); 1895 break; 1896 case ARM::STMIB: 1897 Inst.setOpcode(ARM::SRSIB); 1898 break; 1899 case ARM::STMIB_UPD: 1900 Inst.setOpcode(ARM::SRSIB_UPD); 1901 break; 1902 default: 1903 return MCDisassembler::Fail; 1904 } 1905 1906 // For stores (which become SRS's, the only operand is the mode. 1907 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1908 // Check SRS encoding constraints 1909 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1910 fieldFromInstruction(Insn, 20, 1) == 0)) 1911 return MCDisassembler::Fail; 1912 1913 Inst.addOperand( 1914 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1915 return S; 1916 } 1917 1918 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1919 } 1920 1921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1922 return MCDisassembler::Fail; 1923 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1924 return MCDisassembler::Fail; // Tied 1925 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1926 return MCDisassembler::Fail; 1927 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1928 return MCDisassembler::Fail; 1929 1930 return S; 1931 } 1932 1933 // Check for UNPREDICTABLE predicated ESB instruction 1934 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 1935 uint64_t Address, const void *Decoder) { 1936 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1937 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 1938 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 1939 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 1940 1941 DecodeStatus S = MCDisassembler::Success; 1942 1943 Inst.addOperand(MCOperand::createImm(imm8)); 1944 1945 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1946 return MCDisassembler::Fail; 1947 1948 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 1949 // so all predicates should be allowed. 1950 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 1951 S = MCDisassembler::SoftFail; 1952 1953 return S; 1954 } 1955 1956 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1957 uint64_t Address, const void *Decoder) { 1958 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1959 unsigned M = fieldFromInstruction(Insn, 17, 1); 1960 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1961 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1962 1963 DecodeStatus S = MCDisassembler::Success; 1964 1965 // This decoder is called from multiple location that do not check 1966 // the full encoding is valid before they do. 1967 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1968 fieldFromInstruction(Insn, 16, 1) != 0 || 1969 fieldFromInstruction(Insn, 20, 8) != 0x10) 1970 return MCDisassembler::Fail; 1971 1972 // imod == '01' --> UNPREDICTABLE 1973 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1974 // return failure here. The '01' imod value is unprintable, so there's 1975 // nothing useful we could do even if we returned UNPREDICTABLE. 1976 1977 if (imod == 1) return MCDisassembler::Fail; 1978 1979 if (imod && M) { 1980 Inst.setOpcode(ARM::CPS3p); 1981 Inst.addOperand(MCOperand::createImm(imod)); 1982 Inst.addOperand(MCOperand::createImm(iflags)); 1983 Inst.addOperand(MCOperand::createImm(mode)); 1984 } else if (imod && !M) { 1985 Inst.setOpcode(ARM::CPS2p); 1986 Inst.addOperand(MCOperand::createImm(imod)); 1987 Inst.addOperand(MCOperand::createImm(iflags)); 1988 if (mode) S = MCDisassembler::SoftFail; 1989 } else if (!imod && M) { 1990 Inst.setOpcode(ARM::CPS1p); 1991 Inst.addOperand(MCOperand::createImm(mode)); 1992 if (iflags) S = MCDisassembler::SoftFail; 1993 } else { 1994 // imod == '00' && M == '0' --> UNPREDICTABLE 1995 Inst.setOpcode(ARM::CPS1p); 1996 Inst.addOperand(MCOperand::createImm(mode)); 1997 S = MCDisassembler::SoftFail; 1998 } 1999 2000 return S; 2001 } 2002 2003 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2004 uint64_t Address, const void *Decoder) { 2005 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2006 unsigned M = fieldFromInstruction(Insn, 8, 1); 2007 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2008 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2009 2010 DecodeStatus S = MCDisassembler::Success; 2011 2012 // imod == '01' --> UNPREDICTABLE 2013 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2014 // return failure here. The '01' imod value is unprintable, so there's 2015 // nothing useful we could do even if we returned UNPREDICTABLE. 2016 2017 if (imod == 1) return MCDisassembler::Fail; 2018 2019 if (imod && M) { 2020 Inst.setOpcode(ARM::t2CPS3p); 2021 Inst.addOperand(MCOperand::createImm(imod)); 2022 Inst.addOperand(MCOperand::createImm(iflags)); 2023 Inst.addOperand(MCOperand::createImm(mode)); 2024 } else if (imod && !M) { 2025 Inst.setOpcode(ARM::t2CPS2p); 2026 Inst.addOperand(MCOperand::createImm(imod)); 2027 Inst.addOperand(MCOperand::createImm(iflags)); 2028 if (mode) S = MCDisassembler::SoftFail; 2029 } else if (!imod && M) { 2030 Inst.setOpcode(ARM::t2CPS1p); 2031 Inst.addOperand(MCOperand::createImm(mode)); 2032 if (iflags) S = MCDisassembler::SoftFail; 2033 } else { 2034 // imod == '00' && M == '0' --> this is a HINT instruction 2035 int imm = fieldFromInstruction(Insn, 0, 8); 2036 // HINT are defined only for immediate in [0..4] 2037 if(imm > 4) return MCDisassembler::Fail; 2038 Inst.setOpcode(ARM::t2HINT); 2039 Inst.addOperand(MCOperand::createImm(imm)); 2040 } 2041 2042 return S; 2043 } 2044 2045 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2046 uint64_t Address, const void *Decoder) { 2047 DecodeStatus S = MCDisassembler::Success; 2048 2049 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2050 unsigned imm = 0; 2051 2052 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2053 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2054 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2055 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2056 2057 if (Inst.getOpcode() == ARM::t2MOVTi16) 2058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2059 return MCDisassembler::Fail; 2060 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2061 return MCDisassembler::Fail; 2062 2063 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2064 Inst.addOperand(MCOperand::createImm(imm)); 2065 2066 return S; 2067 } 2068 2069 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2070 uint64_t Address, const void *Decoder) { 2071 DecodeStatus S = MCDisassembler::Success; 2072 2073 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2074 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2075 unsigned imm = 0; 2076 2077 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2078 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2079 2080 if (Inst.getOpcode() == ARM::MOVTi16) 2081 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2082 return MCDisassembler::Fail; 2083 2084 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2085 return MCDisassembler::Fail; 2086 2087 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2088 Inst.addOperand(MCOperand::createImm(imm)); 2089 2090 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2091 return MCDisassembler::Fail; 2092 2093 return S; 2094 } 2095 2096 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2097 uint64_t Address, const void *Decoder) { 2098 DecodeStatus S = MCDisassembler::Success; 2099 2100 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2101 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2102 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2103 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2104 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2105 2106 if (pred == 0xF) 2107 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2108 2109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2114 return MCDisassembler::Fail; 2115 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2116 return MCDisassembler::Fail; 2117 2118 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2119 return MCDisassembler::Fail; 2120 2121 return S; 2122 } 2123 2124 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2125 uint64_t Address, const void *Decoder) { 2126 DecodeStatus S = MCDisassembler::Success; 2127 2128 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2129 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2130 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2131 2132 if (Pred == 0xF) 2133 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2134 2135 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2136 return MCDisassembler::Fail; 2137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2138 return MCDisassembler::Fail; 2139 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2140 return MCDisassembler::Fail; 2141 2142 return S; 2143 } 2144 2145 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2146 uint64_t Address, const void *Decoder) { 2147 DecodeStatus S = MCDisassembler::Success; 2148 2149 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2150 2151 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2152 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2153 2154 if (!FeatureBits[ARM::HasV8_1aOps] || 2155 !FeatureBits[ARM::HasV8Ops]) 2156 return MCDisassembler::Fail; 2157 2158 // Decoder can be called from DecodeTST, which does not check the full 2159 // encoding is valid. 2160 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2161 fieldFromInstruction(Insn, 4,4) != 0) 2162 return MCDisassembler::Fail; 2163 if (fieldFromInstruction(Insn, 10,10) != 0 || 2164 fieldFromInstruction(Insn, 0,4) != 0) 2165 S = MCDisassembler::SoftFail; 2166 2167 Inst.setOpcode(ARM::SETPAN); 2168 Inst.addOperand(MCOperand::createImm(Imm)); 2169 2170 return S; 2171 } 2172 2173 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2174 uint64_t Address, const void *Decoder) { 2175 DecodeStatus S = MCDisassembler::Success; 2176 2177 unsigned add = fieldFromInstruction(Val, 12, 1); 2178 unsigned imm = fieldFromInstruction(Val, 0, 12); 2179 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2180 2181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2182 return MCDisassembler::Fail; 2183 2184 if (!add) imm *= -1; 2185 if (imm == 0 && !add) imm = INT32_MIN; 2186 Inst.addOperand(MCOperand::createImm(imm)); 2187 if (Rn == 15) 2188 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2189 2190 return S; 2191 } 2192 2193 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2194 uint64_t Address, const void *Decoder) { 2195 DecodeStatus S = MCDisassembler::Success; 2196 2197 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2198 // U == 1 to add imm, 0 to subtract it. 2199 unsigned U = fieldFromInstruction(Val, 8, 1); 2200 unsigned imm = fieldFromInstruction(Val, 0, 8); 2201 2202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2203 return MCDisassembler::Fail; 2204 2205 if (U) 2206 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2207 else 2208 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2209 2210 return S; 2211 } 2212 2213 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2214 uint64_t Address, const void *Decoder) { 2215 DecodeStatus S = MCDisassembler::Success; 2216 2217 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2218 // U == 1 to add imm, 0 to subtract it. 2219 unsigned U = fieldFromInstruction(Val, 8, 1); 2220 unsigned imm = fieldFromInstruction(Val, 0, 8); 2221 2222 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2223 return MCDisassembler::Fail; 2224 2225 if (U) 2226 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2227 else 2228 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2229 2230 return S; 2231 } 2232 2233 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2234 uint64_t Address, const void *Decoder) { 2235 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2236 } 2237 2238 static DecodeStatus 2239 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2240 uint64_t Address, const void *Decoder) { 2241 DecodeStatus Status = MCDisassembler::Success; 2242 2243 // Note the J1 and J2 values are from the encoded instruction. So here 2244 // change them to I1 and I2 values via as documented: 2245 // I1 = NOT(J1 EOR S); 2246 // I2 = NOT(J2 EOR S); 2247 // and build the imm32 with one trailing zero as documented: 2248 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2249 unsigned S = fieldFromInstruction(Insn, 26, 1); 2250 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2251 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2252 unsigned I1 = !(J1 ^ S); 2253 unsigned I2 = !(J2 ^ S); 2254 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2255 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2256 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2257 int imm32 = SignExtend32<25>(tmp << 1); 2258 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2259 true, 4, Inst, Decoder)) 2260 Inst.addOperand(MCOperand::createImm(imm32)); 2261 2262 return Status; 2263 } 2264 2265 static DecodeStatus 2266 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2267 uint64_t Address, const void *Decoder) { 2268 DecodeStatus S = MCDisassembler::Success; 2269 2270 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2271 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2272 2273 if (pred == 0xF) { 2274 Inst.setOpcode(ARM::BLXi); 2275 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2276 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2277 true, 4, Inst, Decoder)) 2278 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2279 return S; 2280 } 2281 2282 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2283 true, 4, Inst, Decoder)) 2284 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2285 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2286 return MCDisassembler::Fail; 2287 2288 return S; 2289 } 2290 2291 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2292 uint64_t Address, const void *Decoder) { 2293 DecodeStatus S = MCDisassembler::Success; 2294 2295 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2296 unsigned align = fieldFromInstruction(Val, 4, 2); 2297 2298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2299 return MCDisassembler::Fail; 2300 if (!align) 2301 Inst.addOperand(MCOperand::createImm(0)); 2302 else 2303 Inst.addOperand(MCOperand::createImm(4 << align)); 2304 2305 return S; 2306 } 2307 2308 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2309 uint64_t Address, const void *Decoder) { 2310 DecodeStatus S = MCDisassembler::Success; 2311 2312 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2313 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2314 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2315 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2316 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2317 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2318 2319 // First output register 2320 switch (Inst.getOpcode()) { 2321 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2322 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2323 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2324 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2325 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2326 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2327 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2328 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2329 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2330 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2331 return MCDisassembler::Fail; 2332 break; 2333 case ARM::VLD2b16: 2334 case ARM::VLD2b32: 2335 case ARM::VLD2b8: 2336 case ARM::VLD2b16wb_fixed: 2337 case ARM::VLD2b16wb_register: 2338 case ARM::VLD2b32wb_fixed: 2339 case ARM::VLD2b32wb_register: 2340 case ARM::VLD2b8wb_fixed: 2341 case ARM::VLD2b8wb_register: 2342 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2343 return MCDisassembler::Fail; 2344 break; 2345 default: 2346 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2347 return MCDisassembler::Fail; 2348 } 2349 2350 // Second output register 2351 switch (Inst.getOpcode()) { 2352 case ARM::VLD3d8: 2353 case ARM::VLD3d16: 2354 case ARM::VLD3d32: 2355 case ARM::VLD3d8_UPD: 2356 case ARM::VLD3d16_UPD: 2357 case ARM::VLD3d32_UPD: 2358 case ARM::VLD4d8: 2359 case ARM::VLD4d16: 2360 case ARM::VLD4d32: 2361 case ARM::VLD4d8_UPD: 2362 case ARM::VLD4d16_UPD: 2363 case ARM::VLD4d32_UPD: 2364 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2365 return MCDisassembler::Fail; 2366 break; 2367 case ARM::VLD3q8: 2368 case ARM::VLD3q16: 2369 case ARM::VLD3q32: 2370 case ARM::VLD3q8_UPD: 2371 case ARM::VLD3q16_UPD: 2372 case ARM::VLD3q32_UPD: 2373 case ARM::VLD4q8: 2374 case ARM::VLD4q16: 2375 case ARM::VLD4q32: 2376 case ARM::VLD4q8_UPD: 2377 case ARM::VLD4q16_UPD: 2378 case ARM::VLD4q32_UPD: 2379 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2380 return MCDisassembler::Fail; 2381 default: 2382 break; 2383 } 2384 2385 // Third output register 2386 switch(Inst.getOpcode()) { 2387 case ARM::VLD3d8: 2388 case ARM::VLD3d16: 2389 case ARM::VLD3d32: 2390 case ARM::VLD3d8_UPD: 2391 case ARM::VLD3d16_UPD: 2392 case ARM::VLD3d32_UPD: 2393 case ARM::VLD4d8: 2394 case ARM::VLD4d16: 2395 case ARM::VLD4d32: 2396 case ARM::VLD4d8_UPD: 2397 case ARM::VLD4d16_UPD: 2398 case ARM::VLD4d32_UPD: 2399 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2400 return MCDisassembler::Fail; 2401 break; 2402 case ARM::VLD3q8: 2403 case ARM::VLD3q16: 2404 case ARM::VLD3q32: 2405 case ARM::VLD3q8_UPD: 2406 case ARM::VLD3q16_UPD: 2407 case ARM::VLD3q32_UPD: 2408 case ARM::VLD4q8: 2409 case ARM::VLD4q16: 2410 case ARM::VLD4q32: 2411 case ARM::VLD4q8_UPD: 2412 case ARM::VLD4q16_UPD: 2413 case ARM::VLD4q32_UPD: 2414 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2415 return MCDisassembler::Fail; 2416 break; 2417 default: 2418 break; 2419 } 2420 2421 // Fourth output register 2422 switch (Inst.getOpcode()) { 2423 case ARM::VLD4d8: 2424 case ARM::VLD4d16: 2425 case ARM::VLD4d32: 2426 case ARM::VLD4d8_UPD: 2427 case ARM::VLD4d16_UPD: 2428 case ARM::VLD4d32_UPD: 2429 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2430 return MCDisassembler::Fail; 2431 break; 2432 case ARM::VLD4q8: 2433 case ARM::VLD4q16: 2434 case ARM::VLD4q32: 2435 case ARM::VLD4q8_UPD: 2436 case ARM::VLD4q16_UPD: 2437 case ARM::VLD4q32_UPD: 2438 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2439 return MCDisassembler::Fail; 2440 break; 2441 default: 2442 break; 2443 } 2444 2445 // Writeback operand 2446 switch (Inst.getOpcode()) { 2447 case ARM::VLD1d8wb_fixed: 2448 case ARM::VLD1d16wb_fixed: 2449 case ARM::VLD1d32wb_fixed: 2450 case ARM::VLD1d64wb_fixed: 2451 case ARM::VLD1d8wb_register: 2452 case ARM::VLD1d16wb_register: 2453 case ARM::VLD1d32wb_register: 2454 case ARM::VLD1d64wb_register: 2455 case ARM::VLD1q8wb_fixed: 2456 case ARM::VLD1q16wb_fixed: 2457 case ARM::VLD1q32wb_fixed: 2458 case ARM::VLD1q64wb_fixed: 2459 case ARM::VLD1q8wb_register: 2460 case ARM::VLD1q16wb_register: 2461 case ARM::VLD1q32wb_register: 2462 case ARM::VLD1q64wb_register: 2463 case ARM::VLD1d8Twb_fixed: 2464 case ARM::VLD1d8Twb_register: 2465 case ARM::VLD1d16Twb_fixed: 2466 case ARM::VLD1d16Twb_register: 2467 case ARM::VLD1d32Twb_fixed: 2468 case ARM::VLD1d32Twb_register: 2469 case ARM::VLD1d64Twb_fixed: 2470 case ARM::VLD1d64Twb_register: 2471 case ARM::VLD1d8Qwb_fixed: 2472 case ARM::VLD1d8Qwb_register: 2473 case ARM::VLD1d16Qwb_fixed: 2474 case ARM::VLD1d16Qwb_register: 2475 case ARM::VLD1d32Qwb_fixed: 2476 case ARM::VLD1d32Qwb_register: 2477 case ARM::VLD1d64Qwb_fixed: 2478 case ARM::VLD1d64Qwb_register: 2479 case ARM::VLD2d8wb_fixed: 2480 case ARM::VLD2d16wb_fixed: 2481 case ARM::VLD2d32wb_fixed: 2482 case ARM::VLD2q8wb_fixed: 2483 case ARM::VLD2q16wb_fixed: 2484 case ARM::VLD2q32wb_fixed: 2485 case ARM::VLD2d8wb_register: 2486 case ARM::VLD2d16wb_register: 2487 case ARM::VLD2d32wb_register: 2488 case ARM::VLD2q8wb_register: 2489 case ARM::VLD2q16wb_register: 2490 case ARM::VLD2q32wb_register: 2491 case ARM::VLD2b8wb_fixed: 2492 case ARM::VLD2b16wb_fixed: 2493 case ARM::VLD2b32wb_fixed: 2494 case ARM::VLD2b8wb_register: 2495 case ARM::VLD2b16wb_register: 2496 case ARM::VLD2b32wb_register: 2497 Inst.addOperand(MCOperand::createImm(0)); 2498 break; 2499 case ARM::VLD3d8_UPD: 2500 case ARM::VLD3d16_UPD: 2501 case ARM::VLD3d32_UPD: 2502 case ARM::VLD3q8_UPD: 2503 case ARM::VLD3q16_UPD: 2504 case ARM::VLD3q32_UPD: 2505 case ARM::VLD4d8_UPD: 2506 case ARM::VLD4d16_UPD: 2507 case ARM::VLD4d32_UPD: 2508 case ARM::VLD4q8_UPD: 2509 case ARM::VLD4q16_UPD: 2510 case ARM::VLD4q32_UPD: 2511 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2512 return MCDisassembler::Fail; 2513 break; 2514 default: 2515 break; 2516 } 2517 2518 // AddrMode6 Base (register+alignment) 2519 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2520 return MCDisassembler::Fail; 2521 2522 // AddrMode6 Offset (register) 2523 switch (Inst.getOpcode()) { 2524 default: 2525 // The below have been updated to have explicit am6offset split 2526 // between fixed and register offset. For those instructions not 2527 // yet updated, we need to add an additional reg0 operand for the 2528 // fixed variant. 2529 // 2530 // The fixed offset encodes as Rm == 0xd, so we check for that. 2531 if (Rm == 0xd) { 2532 Inst.addOperand(MCOperand::createReg(0)); 2533 break; 2534 } 2535 // Fall through to handle the register offset variant. 2536 LLVM_FALLTHROUGH; 2537 case ARM::VLD1d8wb_fixed: 2538 case ARM::VLD1d16wb_fixed: 2539 case ARM::VLD1d32wb_fixed: 2540 case ARM::VLD1d64wb_fixed: 2541 case ARM::VLD1d8Twb_fixed: 2542 case ARM::VLD1d16Twb_fixed: 2543 case ARM::VLD1d32Twb_fixed: 2544 case ARM::VLD1d64Twb_fixed: 2545 case ARM::VLD1d8Qwb_fixed: 2546 case ARM::VLD1d16Qwb_fixed: 2547 case ARM::VLD1d32Qwb_fixed: 2548 case ARM::VLD1d64Qwb_fixed: 2549 case ARM::VLD1d8wb_register: 2550 case ARM::VLD1d16wb_register: 2551 case ARM::VLD1d32wb_register: 2552 case ARM::VLD1d64wb_register: 2553 case ARM::VLD1q8wb_fixed: 2554 case ARM::VLD1q16wb_fixed: 2555 case ARM::VLD1q32wb_fixed: 2556 case ARM::VLD1q64wb_fixed: 2557 case ARM::VLD1q8wb_register: 2558 case ARM::VLD1q16wb_register: 2559 case ARM::VLD1q32wb_register: 2560 case ARM::VLD1q64wb_register: 2561 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2562 // variant encodes Rm == 0xf. Anything else is a register offset post- 2563 // increment and we need to add the register operand to the instruction. 2564 if (Rm != 0xD && Rm != 0xF && 2565 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2566 return MCDisassembler::Fail; 2567 break; 2568 case ARM::VLD2d8wb_fixed: 2569 case ARM::VLD2d16wb_fixed: 2570 case ARM::VLD2d32wb_fixed: 2571 case ARM::VLD2b8wb_fixed: 2572 case ARM::VLD2b16wb_fixed: 2573 case ARM::VLD2b32wb_fixed: 2574 case ARM::VLD2q8wb_fixed: 2575 case ARM::VLD2q16wb_fixed: 2576 case ARM::VLD2q32wb_fixed: 2577 break; 2578 } 2579 2580 return S; 2581 } 2582 2583 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2584 uint64_t Address, const void *Decoder) { 2585 unsigned type = fieldFromInstruction(Insn, 8, 4); 2586 unsigned align = fieldFromInstruction(Insn, 4, 2); 2587 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2588 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2589 if (type == 10 && align == 3) return MCDisassembler::Fail; 2590 2591 unsigned load = fieldFromInstruction(Insn, 21, 1); 2592 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2593 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2594 } 2595 2596 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2597 uint64_t Address, const void *Decoder) { 2598 unsigned size = fieldFromInstruction(Insn, 6, 2); 2599 if (size == 3) return MCDisassembler::Fail; 2600 2601 unsigned type = fieldFromInstruction(Insn, 8, 4); 2602 unsigned align = fieldFromInstruction(Insn, 4, 2); 2603 if (type == 8 && align == 3) return MCDisassembler::Fail; 2604 if (type == 9 && align == 3) return MCDisassembler::Fail; 2605 2606 unsigned load = fieldFromInstruction(Insn, 21, 1); 2607 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2608 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2609 } 2610 2611 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2612 uint64_t Address, const void *Decoder) { 2613 unsigned size = fieldFromInstruction(Insn, 6, 2); 2614 if (size == 3) return MCDisassembler::Fail; 2615 2616 unsigned align = fieldFromInstruction(Insn, 4, 2); 2617 if (align & 2) return MCDisassembler::Fail; 2618 2619 unsigned load = fieldFromInstruction(Insn, 21, 1); 2620 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2621 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2622 } 2623 2624 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2625 uint64_t Address, const void *Decoder) { 2626 unsigned size = fieldFromInstruction(Insn, 6, 2); 2627 if (size == 3) return MCDisassembler::Fail; 2628 2629 unsigned load = fieldFromInstruction(Insn, 21, 1); 2630 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2631 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2632 } 2633 2634 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2635 uint64_t Address, const void *Decoder) { 2636 DecodeStatus S = MCDisassembler::Success; 2637 2638 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2639 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2640 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2641 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2642 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2643 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2644 2645 // Writeback Operand 2646 switch (Inst.getOpcode()) { 2647 case ARM::VST1d8wb_fixed: 2648 case ARM::VST1d16wb_fixed: 2649 case ARM::VST1d32wb_fixed: 2650 case ARM::VST1d64wb_fixed: 2651 case ARM::VST1d8wb_register: 2652 case ARM::VST1d16wb_register: 2653 case ARM::VST1d32wb_register: 2654 case ARM::VST1d64wb_register: 2655 case ARM::VST1q8wb_fixed: 2656 case ARM::VST1q16wb_fixed: 2657 case ARM::VST1q32wb_fixed: 2658 case ARM::VST1q64wb_fixed: 2659 case ARM::VST1q8wb_register: 2660 case ARM::VST1q16wb_register: 2661 case ARM::VST1q32wb_register: 2662 case ARM::VST1q64wb_register: 2663 case ARM::VST1d8Twb_fixed: 2664 case ARM::VST1d16Twb_fixed: 2665 case ARM::VST1d32Twb_fixed: 2666 case ARM::VST1d64Twb_fixed: 2667 case ARM::VST1d8Twb_register: 2668 case ARM::VST1d16Twb_register: 2669 case ARM::VST1d32Twb_register: 2670 case ARM::VST1d64Twb_register: 2671 case ARM::VST1d8Qwb_fixed: 2672 case ARM::VST1d16Qwb_fixed: 2673 case ARM::VST1d32Qwb_fixed: 2674 case ARM::VST1d64Qwb_fixed: 2675 case ARM::VST1d8Qwb_register: 2676 case ARM::VST1d16Qwb_register: 2677 case ARM::VST1d32Qwb_register: 2678 case ARM::VST1d64Qwb_register: 2679 case ARM::VST2d8wb_fixed: 2680 case ARM::VST2d16wb_fixed: 2681 case ARM::VST2d32wb_fixed: 2682 case ARM::VST2d8wb_register: 2683 case ARM::VST2d16wb_register: 2684 case ARM::VST2d32wb_register: 2685 case ARM::VST2q8wb_fixed: 2686 case ARM::VST2q16wb_fixed: 2687 case ARM::VST2q32wb_fixed: 2688 case ARM::VST2q8wb_register: 2689 case ARM::VST2q16wb_register: 2690 case ARM::VST2q32wb_register: 2691 case ARM::VST2b8wb_fixed: 2692 case ARM::VST2b16wb_fixed: 2693 case ARM::VST2b32wb_fixed: 2694 case ARM::VST2b8wb_register: 2695 case ARM::VST2b16wb_register: 2696 case ARM::VST2b32wb_register: 2697 if (Rm == 0xF) 2698 return MCDisassembler::Fail; 2699 Inst.addOperand(MCOperand::createImm(0)); 2700 break; 2701 case ARM::VST3d8_UPD: 2702 case ARM::VST3d16_UPD: 2703 case ARM::VST3d32_UPD: 2704 case ARM::VST3q8_UPD: 2705 case ARM::VST3q16_UPD: 2706 case ARM::VST3q32_UPD: 2707 case ARM::VST4d8_UPD: 2708 case ARM::VST4d16_UPD: 2709 case ARM::VST4d32_UPD: 2710 case ARM::VST4q8_UPD: 2711 case ARM::VST4q16_UPD: 2712 case ARM::VST4q32_UPD: 2713 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 break; 2716 default: 2717 break; 2718 } 2719 2720 // AddrMode6 Base (register+alignment) 2721 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 2724 // AddrMode6 Offset (register) 2725 switch (Inst.getOpcode()) { 2726 default: 2727 if (Rm == 0xD) 2728 Inst.addOperand(MCOperand::createReg(0)); 2729 else if (Rm != 0xF) { 2730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 } 2733 break; 2734 case ARM::VST1d8wb_fixed: 2735 case ARM::VST1d16wb_fixed: 2736 case ARM::VST1d32wb_fixed: 2737 case ARM::VST1d64wb_fixed: 2738 case ARM::VST1q8wb_fixed: 2739 case ARM::VST1q16wb_fixed: 2740 case ARM::VST1q32wb_fixed: 2741 case ARM::VST1q64wb_fixed: 2742 case ARM::VST1d8Twb_fixed: 2743 case ARM::VST1d16Twb_fixed: 2744 case ARM::VST1d32Twb_fixed: 2745 case ARM::VST1d64Twb_fixed: 2746 case ARM::VST1d8Qwb_fixed: 2747 case ARM::VST1d16Qwb_fixed: 2748 case ARM::VST1d32Qwb_fixed: 2749 case ARM::VST1d64Qwb_fixed: 2750 case ARM::VST2d8wb_fixed: 2751 case ARM::VST2d16wb_fixed: 2752 case ARM::VST2d32wb_fixed: 2753 case ARM::VST2q8wb_fixed: 2754 case ARM::VST2q16wb_fixed: 2755 case ARM::VST2q32wb_fixed: 2756 case ARM::VST2b8wb_fixed: 2757 case ARM::VST2b16wb_fixed: 2758 case ARM::VST2b32wb_fixed: 2759 break; 2760 } 2761 2762 2763 // First input register 2764 switch (Inst.getOpcode()) { 2765 case ARM::VST1q16: 2766 case ARM::VST1q32: 2767 case ARM::VST1q64: 2768 case ARM::VST1q8: 2769 case ARM::VST1q16wb_fixed: 2770 case ARM::VST1q16wb_register: 2771 case ARM::VST1q32wb_fixed: 2772 case ARM::VST1q32wb_register: 2773 case ARM::VST1q64wb_fixed: 2774 case ARM::VST1q64wb_register: 2775 case ARM::VST1q8wb_fixed: 2776 case ARM::VST1q8wb_register: 2777 case ARM::VST2d16: 2778 case ARM::VST2d32: 2779 case ARM::VST2d8: 2780 case ARM::VST2d16wb_fixed: 2781 case ARM::VST2d16wb_register: 2782 case ARM::VST2d32wb_fixed: 2783 case ARM::VST2d32wb_register: 2784 case ARM::VST2d8wb_fixed: 2785 case ARM::VST2d8wb_register: 2786 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2787 return MCDisassembler::Fail; 2788 break; 2789 case ARM::VST2b16: 2790 case ARM::VST2b32: 2791 case ARM::VST2b8: 2792 case ARM::VST2b16wb_fixed: 2793 case ARM::VST2b16wb_register: 2794 case ARM::VST2b32wb_fixed: 2795 case ARM::VST2b32wb_register: 2796 case ARM::VST2b8wb_fixed: 2797 case ARM::VST2b8wb_register: 2798 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2799 return MCDisassembler::Fail; 2800 break; 2801 default: 2802 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2803 return MCDisassembler::Fail; 2804 } 2805 2806 // Second input register 2807 switch (Inst.getOpcode()) { 2808 case ARM::VST3d8: 2809 case ARM::VST3d16: 2810 case ARM::VST3d32: 2811 case ARM::VST3d8_UPD: 2812 case ARM::VST3d16_UPD: 2813 case ARM::VST3d32_UPD: 2814 case ARM::VST4d8: 2815 case ARM::VST4d16: 2816 case ARM::VST4d32: 2817 case ARM::VST4d8_UPD: 2818 case ARM::VST4d16_UPD: 2819 case ARM::VST4d32_UPD: 2820 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2821 return MCDisassembler::Fail; 2822 break; 2823 case ARM::VST3q8: 2824 case ARM::VST3q16: 2825 case ARM::VST3q32: 2826 case ARM::VST3q8_UPD: 2827 case ARM::VST3q16_UPD: 2828 case ARM::VST3q32_UPD: 2829 case ARM::VST4q8: 2830 case ARM::VST4q16: 2831 case ARM::VST4q32: 2832 case ARM::VST4q8_UPD: 2833 case ARM::VST4q16_UPD: 2834 case ARM::VST4q32_UPD: 2835 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 break; 2838 default: 2839 break; 2840 } 2841 2842 // Third input register 2843 switch (Inst.getOpcode()) { 2844 case ARM::VST3d8: 2845 case ARM::VST3d16: 2846 case ARM::VST3d32: 2847 case ARM::VST3d8_UPD: 2848 case ARM::VST3d16_UPD: 2849 case ARM::VST3d32_UPD: 2850 case ARM::VST4d8: 2851 case ARM::VST4d16: 2852 case ARM::VST4d32: 2853 case ARM::VST4d8_UPD: 2854 case ARM::VST4d16_UPD: 2855 case ARM::VST4d32_UPD: 2856 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2857 return MCDisassembler::Fail; 2858 break; 2859 case ARM::VST3q8: 2860 case ARM::VST3q16: 2861 case ARM::VST3q32: 2862 case ARM::VST3q8_UPD: 2863 case ARM::VST3q16_UPD: 2864 case ARM::VST3q32_UPD: 2865 case ARM::VST4q8: 2866 case ARM::VST4q16: 2867 case ARM::VST4q32: 2868 case ARM::VST4q8_UPD: 2869 case ARM::VST4q16_UPD: 2870 case ARM::VST4q32_UPD: 2871 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2872 return MCDisassembler::Fail; 2873 break; 2874 default: 2875 break; 2876 } 2877 2878 // Fourth input register 2879 switch (Inst.getOpcode()) { 2880 case ARM::VST4d8: 2881 case ARM::VST4d16: 2882 case ARM::VST4d32: 2883 case ARM::VST4d8_UPD: 2884 case ARM::VST4d16_UPD: 2885 case ARM::VST4d32_UPD: 2886 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2887 return MCDisassembler::Fail; 2888 break; 2889 case ARM::VST4q8: 2890 case ARM::VST4q16: 2891 case ARM::VST4q32: 2892 case ARM::VST4q8_UPD: 2893 case ARM::VST4q16_UPD: 2894 case ARM::VST4q32_UPD: 2895 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2896 return MCDisassembler::Fail; 2897 break; 2898 default: 2899 break; 2900 } 2901 2902 return S; 2903 } 2904 2905 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2906 uint64_t Address, const void *Decoder) { 2907 DecodeStatus S = MCDisassembler::Success; 2908 2909 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2910 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2911 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2912 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2913 unsigned align = fieldFromInstruction(Insn, 4, 1); 2914 unsigned size = fieldFromInstruction(Insn, 6, 2); 2915 2916 if (size == 0 && align == 1) 2917 return MCDisassembler::Fail; 2918 align *= (1 << size); 2919 2920 switch (Inst.getOpcode()) { 2921 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2922 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2923 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2924 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2925 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2926 return MCDisassembler::Fail; 2927 break; 2928 default: 2929 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2930 return MCDisassembler::Fail; 2931 break; 2932 } 2933 if (Rm != 0xF) { 2934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2935 return MCDisassembler::Fail; 2936 } 2937 2938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2939 return MCDisassembler::Fail; 2940 Inst.addOperand(MCOperand::createImm(align)); 2941 2942 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2943 // variant encodes Rm == 0xf. Anything else is a register offset post- 2944 // increment and we need to add the register operand to the instruction. 2945 if (Rm != 0xD && Rm != 0xF && 2946 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2947 return MCDisassembler::Fail; 2948 2949 return S; 2950 } 2951 2952 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2953 uint64_t Address, const void *Decoder) { 2954 DecodeStatus S = MCDisassembler::Success; 2955 2956 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2957 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2958 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2959 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2960 unsigned align = fieldFromInstruction(Insn, 4, 1); 2961 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2962 align *= 2*size; 2963 2964 switch (Inst.getOpcode()) { 2965 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2966 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2967 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2968 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2969 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2970 return MCDisassembler::Fail; 2971 break; 2972 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2973 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2974 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2975 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2976 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2977 return MCDisassembler::Fail; 2978 break; 2979 default: 2980 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2981 return MCDisassembler::Fail; 2982 break; 2983 } 2984 2985 if (Rm != 0xF) 2986 Inst.addOperand(MCOperand::createImm(0)); 2987 2988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2989 return MCDisassembler::Fail; 2990 Inst.addOperand(MCOperand::createImm(align)); 2991 2992 if (Rm != 0xD && Rm != 0xF) { 2993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2994 return MCDisassembler::Fail; 2995 } 2996 2997 return S; 2998 } 2999 3000 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3001 uint64_t Address, const void *Decoder) { 3002 DecodeStatus S = MCDisassembler::Success; 3003 3004 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3005 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3006 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3007 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3008 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3009 3010 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3011 return MCDisassembler::Fail; 3012 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3013 return MCDisassembler::Fail; 3014 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3015 return MCDisassembler::Fail; 3016 if (Rm != 0xF) { 3017 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3018 return MCDisassembler::Fail; 3019 } 3020 3021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3022 return MCDisassembler::Fail; 3023 Inst.addOperand(MCOperand::createImm(0)); 3024 3025 if (Rm == 0xD) 3026 Inst.addOperand(MCOperand::createReg(0)); 3027 else if (Rm != 0xF) { 3028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3029 return MCDisassembler::Fail; 3030 } 3031 3032 return S; 3033 } 3034 3035 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3036 uint64_t Address, const void *Decoder) { 3037 DecodeStatus S = MCDisassembler::Success; 3038 3039 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3040 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3041 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3042 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3043 unsigned size = fieldFromInstruction(Insn, 6, 2); 3044 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3045 unsigned align = fieldFromInstruction(Insn, 4, 1); 3046 3047 if (size == 0x3) { 3048 if (align == 0) 3049 return MCDisassembler::Fail; 3050 align = 16; 3051 } else { 3052 if (size == 2) { 3053 align *= 8; 3054 } else { 3055 size = 1 << size; 3056 align *= 4*size; 3057 } 3058 } 3059 3060 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3061 return MCDisassembler::Fail; 3062 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3065 return MCDisassembler::Fail; 3066 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3067 return MCDisassembler::Fail; 3068 if (Rm != 0xF) { 3069 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3070 return MCDisassembler::Fail; 3071 } 3072 3073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3074 return MCDisassembler::Fail; 3075 Inst.addOperand(MCOperand::createImm(align)); 3076 3077 if (Rm == 0xD) 3078 Inst.addOperand(MCOperand::createReg(0)); 3079 else if (Rm != 0xF) { 3080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3081 return MCDisassembler::Fail; 3082 } 3083 3084 return S; 3085 } 3086 3087 static DecodeStatus 3088 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3089 uint64_t Address, const void *Decoder) { 3090 DecodeStatus S = MCDisassembler::Success; 3091 3092 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3093 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3094 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3095 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3096 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3097 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3098 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3099 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3100 3101 if (Q) { 3102 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3103 return MCDisassembler::Fail; 3104 } else { 3105 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 } 3108 3109 Inst.addOperand(MCOperand::createImm(imm)); 3110 3111 switch (Inst.getOpcode()) { 3112 case ARM::VORRiv4i16: 3113 case ARM::VORRiv2i32: 3114 case ARM::VBICiv4i16: 3115 case ARM::VBICiv2i32: 3116 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3117 return MCDisassembler::Fail; 3118 break; 3119 case ARM::VORRiv8i16: 3120 case ARM::VORRiv4i32: 3121 case ARM::VBICiv8i16: 3122 case ARM::VBICiv4i32: 3123 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 break; 3126 default: 3127 break; 3128 } 3129 3130 return S; 3131 } 3132 3133 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3134 uint64_t Address, const void *Decoder) { 3135 DecodeStatus S = MCDisassembler::Success; 3136 3137 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3138 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3139 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3140 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3141 unsigned size = fieldFromInstruction(Insn, 18, 2); 3142 3143 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3144 return MCDisassembler::Fail; 3145 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3146 return MCDisassembler::Fail; 3147 Inst.addOperand(MCOperand::createImm(8 << size)); 3148 3149 return S; 3150 } 3151 3152 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3153 uint64_t Address, const void *Decoder) { 3154 Inst.addOperand(MCOperand::createImm(8 - Val)); 3155 return MCDisassembler::Success; 3156 } 3157 3158 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3159 uint64_t Address, const void *Decoder) { 3160 Inst.addOperand(MCOperand::createImm(16 - Val)); 3161 return MCDisassembler::Success; 3162 } 3163 3164 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3165 uint64_t Address, const void *Decoder) { 3166 Inst.addOperand(MCOperand::createImm(32 - Val)); 3167 return MCDisassembler::Success; 3168 } 3169 3170 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3171 uint64_t Address, const void *Decoder) { 3172 Inst.addOperand(MCOperand::createImm(64 - Val)); 3173 return MCDisassembler::Success; 3174 } 3175 3176 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3177 uint64_t Address, const void *Decoder) { 3178 DecodeStatus S = MCDisassembler::Success; 3179 3180 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3181 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3182 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3183 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3184 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3185 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3186 unsigned op = fieldFromInstruction(Insn, 6, 1); 3187 3188 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3189 return MCDisassembler::Fail; 3190 if (op) { 3191 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3192 return MCDisassembler::Fail; // Writeback 3193 } 3194 3195 switch (Inst.getOpcode()) { 3196 case ARM::VTBL2: 3197 case ARM::VTBX2: 3198 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3199 return MCDisassembler::Fail; 3200 break; 3201 default: 3202 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3203 return MCDisassembler::Fail; 3204 } 3205 3206 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3207 return MCDisassembler::Fail; 3208 3209 return S; 3210 } 3211 3212 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3213 uint64_t Address, const void *Decoder) { 3214 DecodeStatus S = MCDisassembler::Success; 3215 3216 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3217 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3218 3219 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3220 return MCDisassembler::Fail; 3221 3222 switch(Inst.getOpcode()) { 3223 default: 3224 return MCDisassembler::Fail; 3225 case ARM::tADR: 3226 break; // tADR does not explicitly represent the PC as an operand. 3227 case ARM::tADDrSPi: 3228 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3229 break; 3230 } 3231 3232 Inst.addOperand(MCOperand::createImm(imm)); 3233 return S; 3234 } 3235 3236 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3237 uint64_t Address, const void *Decoder) { 3238 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3239 true, 2, Inst, Decoder)) 3240 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3241 return MCDisassembler::Success; 3242 } 3243 3244 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3245 uint64_t Address, const void *Decoder) { 3246 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3247 true, 4, Inst, Decoder)) 3248 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3249 return MCDisassembler::Success; 3250 } 3251 3252 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3253 uint64_t Address, const void *Decoder) { 3254 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3255 true, 2, Inst, Decoder)) 3256 Inst.addOperand(MCOperand::createImm(Val << 1)); 3257 return MCDisassembler::Success; 3258 } 3259 3260 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3261 uint64_t Address, const void *Decoder) { 3262 DecodeStatus S = MCDisassembler::Success; 3263 3264 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3265 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3266 3267 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3268 return MCDisassembler::Fail; 3269 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3270 return MCDisassembler::Fail; 3271 3272 return S; 3273 } 3274 3275 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3276 uint64_t Address, const void *Decoder) { 3277 DecodeStatus S = MCDisassembler::Success; 3278 3279 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3280 unsigned imm = fieldFromInstruction(Val, 3, 5); 3281 3282 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 Inst.addOperand(MCOperand::createImm(imm)); 3285 3286 return S; 3287 } 3288 3289 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3290 uint64_t Address, const void *Decoder) { 3291 unsigned imm = Val << 2; 3292 3293 Inst.addOperand(MCOperand::createImm(imm)); 3294 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3295 3296 return MCDisassembler::Success; 3297 } 3298 3299 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3300 uint64_t Address, const void *Decoder) { 3301 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3302 Inst.addOperand(MCOperand::createImm(Val)); 3303 3304 return MCDisassembler::Success; 3305 } 3306 3307 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3308 uint64_t Address, const void *Decoder) { 3309 DecodeStatus S = MCDisassembler::Success; 3310 3311 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3312 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3313 unsigned imm = fieldFromInstruction(Val, 0, 2); 3314 3315 // Thumb stores cannot use PC as dest register. 3316 switch (Inst.getOpcode()) { 3317 case ARM::t2STRHs: 3318 case ARM::t2STRBs: 3319 case ARM::t2STRs: 3320 if (Rn == 15) 3321 return MCDisassembler::Fail; 3322 default: 3323 break; 3324 } 3325 3326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3327 return MCDisassembler::Fail; 3328 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3329 return MCDisassembler::Fail; 3330 Inst.addOperand(MCOperand::createImm(imm)); 3331 3332 return S; 3333 } 3334 3335 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3336 uint64_t Address, const void *Decoder) { 3337 DecodeStatus S = MCDisassembler::Success; 3338 3339 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3340 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3341 3342 const FeatureBitset &featureBits = 3343 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3344 3345 bool hasMP = featureBits[ARM::FeatureMP]; 3346 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3347 3348 if (Rn == 15) { 3349 switch (Inst.getOpcode()) { 3350 case ARM::t2LDRBs: 3351 Inst.setOpcode(ARM::t2LDRBpci); 3352 break; 3353 case ARM::t2LDRHs: 3354 Inst.setOpcode(ARM::t2LDRHpci); 3355 break; 3356 case ARM::t2LDRSHs: 3357 Inst.setOpcode(ARM::t2LDRSHpci); 3358 break; 3359 case ARM::t2LDRSBs: 3360 Inst.setOpcode(ARM::t2LDRSBpci); 3361 break; 3362 case ARM::t2LDRs: 3363 Inst.setOpcode(ARM::t2LDRpci); 3364 break; 3365 case ARM::t2PLDs: 3366 Inst.setOpcode(ARM::t2PLDpci); 3367 break; 3368 case ARM::t2PLIs: 3369 Inst.setOpcode(ARM::t2PLIpci); 3370 break; 3371 default: 3372 return MCDisassembler::Fail; 3373 } 3374 3375 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3376 } 3377 3378 if (Rt == 15) { 3379 switch (Inst.getOpcode()) { 3380 case ARM::t2LDRSHs: 3381 return MCDisassembler::Fail; 3382 case ARM::t2LDRHs: 3383 Inst.setOpcode(ARM::t2PLDWs); 3384 break; 3385 case ARM::t2LDRSBs: 3386 Inst.setOpcode(ARM::t2PLIs); 3387 default: 3388 break; 3389 } 3390 } 3391 3392 switch (Inst.getOpcode()) { 3393 case ARM::t2PLDs: 3394 break; 3395 case ARM::t2PLIs: 3396 if (!hasV7Ops) 3397 return MCDisassembler::Fail; 3398 break; 3399 case ARM::t2PLDWs: 3400 if (!hasV7Ops || !hasMP) 3401 return MCDisassembler::Fail; 3402 break; 3403 default: 3404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3405 return MCDisassembler::Fail; 3406 } 3407 3408 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3409 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3410 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3411 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3412 return MCDisassembler::Fail; 3413 3414 return S; 3415 } 3416 3417 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3418 uint64_t Address, const void* Decoder) { 3419 DecodeStatus S = MCDisassembler::Success; 3420 3421 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3422 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3423 unsigned U = fieldFromInstruction(Insn, 9, 1); 3424 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3425 imm |= (U << 8); 3426 imm |= (Rn << 9); 3427 unsigned add = fieldFromInstruction(Insn, 9, 1); 3428 3429 const FeatureBitset &featureBits = 3430 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3431 3432 bool hasMP = featureBits[ARM::FeatureMP]; 3433 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3434 3435 if (Rn == 15) { 3436 switch (Inst.getOpcode()) { 3437 case ARM::t2LDRi8: 3438 Inst.setOpcode(ARM::t2LDRpci); 3439 break; 3440 case ARM::t2LDRBi8: 3441 Inst.setOpcode(ARM::t2LDRBpci); 3442 break; 3443 case ARM::t2LDRSBi8: 3444 Inst.setOpcode(ARM::t2LDRSBpci); 3445 break; 3446 case ARM::t2LDRHi8: 3447 Inst.setOpcode(ARM::t2LDRHpci); 3448 break; 3449 case ARM::t2LDRSHi8: 3450 Inst.setOpcode(ARM::t2LDRSHpci); 3451 break; 3452 case ARM::t2PLDi8: 3453 Inst.setOpcode(ARM::t2PLDpci); 3454 break; 3455 case ARM::t2PLIi8: 3456 Inst.setOpcode(ARM::t2PLIpci); 3457 break; 3458 default: 3459 return MCDisassembler::Fail; 3460 } 3461 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3462 } 3463 3464 if (Rt == 15) { 3465 switch (Inst.getOpcode()) { 3466 case ARM::t2LDRSHi8: 3467 return MCDisassembler::Fail; 3468 case ARM::t2LDRHi8: 3469 if (!add) 3470 Inst.setOpcode(ARM::t2PLDWi8); 3471 break; 3472 case ARM::t2LDRSBi8: 3473 Inst.setOpcode(ARM::t2PLIi8); 3474 break; 3475 default: 3476 break; 3477 } 3478 } 3479 3480 switch (Inst.getOpcode()) { 3481 case ARM::t2PLDi8: 3482 break; 3483 case ARM::t2PLIi8: 3484 if (!hasV7Ops) 3485 return MCDisassembler::Fail; 3486 break; 3487 case ARM::t2PLDWi8: 3488 if (!hasV7Ops || !hasMP) 3489 return MCDisassembler::Fail; 3490 break; 3491 default: 3492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3493 return MCDisassembler::Fail; 3494 } 3495 3496 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3497 return MCDisassembler::Fail; 3498 return S; 3499 } 3500 3501 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3502 uint64_t Address, const void* Decoder) { 3503 DecodeStatus S = MCDisassembler::Success; 3504 3505 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3506 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3507 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3508 imm |= (Rn << 13); 3509 3510 const FeatureBitset &featureBits = 3511 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3512 3513 bool hasMP = featureBits[ARM::FeatureMP]; 3514 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3515 3516 if (Rn == 15) { 3517 switch (Inst.getOpcode()) { 3518 case ARM::t2LDRi12: 3519 Inst.setOpcode(ARM::t2LDRpci); 3520 break; 3521 case ARM::t2LDRHi12: 3522 Inst.setOpcode(ARM::t2LDRHpci); 3523 break; 3524 case ARM::t2LDRSHi12: 3525 Inst.setOpcode(ARM::t2LDRSHpci); 3526 break; 3527 case ARM::t2LDRBi12: 3528 Inst.setOpcode(ARM::t2LDRBpci); 3529 break; 3530 case ARM::t2LDRSBi12: 3531 Inst.setOpcode(ARM::t2LDRSBpci); 3532 break; 3533 case ARM::t2PLDi12: 3534 Inst.setOpcode(ARM::t2PLDpci); 3535 break; 3536 case ARM::t2PLIi12: 3537 Inst.setOpcode(ARM::t2PLIpci); 3538 break; 3539 default: 3540 return MCDisassembler::Fail; 3541 } 3542 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3543 } 3544 3545 if (Rt == 15) { 3546 switch (Inst.getOpcode()) { 3547 case ARM::t2LDRSHi12: 3548 return MCDisassembler::Fail; 3549 case ARM::t2LDRHi12: 3550 Inst.setOpcode(ARM::t2PLDWi12); 3551 break; 3552 case ARM::t2LDRSBi12: 3553 Inst.setOpcode(ARM::t2PLIi12); 3554 break; 3555 default: 3556 break; 3557 } 3558 } 3559 3560 switch (Inst.getOpcode()) { 3561 case ARM::t2PLDi12: 3562 break; 3563 case ARM::t2PLIi12: 3564 if (!hasV7Ops) 3565 return MCDisassembler::Fail; 3566 break; 3567 case ARM::t2PLDWi12: 3568 if (!hasV7Ops || !hasMP) 3569 return MCDisassembler::Fail; 3570 break; 3571 default: 3572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 } 3575 3576 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3577 return MCDisassembler::Fail; 3578 return S; 3579 } 3580 3581 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3582 uint64_t Address, const void* Decoder) { 3583 DecodeStatus S = MCDisassembler::Success; 3584 3585 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3586 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3587 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3588 imm |= (Rn << 9); 3589 3590 if (Rn == 15) { 3591 switch (Inst.getOpcode()) { 3592 case ARM::t2LDRT: 3593 Inst.setOpcode(ARM::t2LDRpci); 3594 break; 3595 case ARM::t2LDRBT: 3596 Inst.setOpcode(ARM::t2LDRBpci); 3597 break; 3598 case ARM::t2LDRHT: 3599 Inst.setOpcode(ARM::t2LDRHpci); 3600 break; 3601 case ARM::t2LDRSBT: 3602 Inst.setOpcode(ARM::t2LDRSBpci); 3603 break; 3604 case ARM::t2LDRSHT: 3605 Inst.setOpcode(ARM::t2LDRSHpci); 3606 break; 3607 default: 3608 return MCDisassembler::Fail; 3609 } 3610 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3611 } 3612 3613 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3614 return MCDisassembler::Fail; 3615 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3616 return MCDisassembler::Fail; 3617 return S; 3618 } 3619 3620 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3621 uint64_t Address, const void* Decoder) { 3622 DecodeStatus S = MCDisassembler::Success; 3623 3624 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3625 unsigned U = fieldFromInstruction(Insn, 23, 1); 3626 int imm = fieldFromInstruction(Insn, 0, 12); 3627 3628 const FeatureBitset &featureBits = 3629 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3630 3631 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3632 3633 if (Rt == 15) { 3634 switch (Inst.getOpcode()) { 3635 case ARM::t2LDRBpci: 3636 case ARM::t2LDRHpci: 3637 Inst.setOpcode(ARM::t2PLDpci); 3638 break; 3639 case ARM::t2LDRSBpci: 3640 Inst.setOpcode(ARM::t2PLIpci); 3641 break; 3642 case ARM::t2LDRSHpci: 3643 return MCDisassembler::Fail; 3644 default: 3645 break; 3646 } 3647 } 3648 3649 switch(Inst.getOpcode()) { 3650 case ARM::t2PLDpci: 3651 break; 3652 case ARM::t2PLIpci: 3653 if (!hasV7Ops) 3654 return MCDisassembler::Fail; 3655 break; 3656 default: 3657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3658 return MCDisassembler::Fail; 3659 } 3660 3661 if (!U) { 3662 // Special case for #-0. 3663 if (imm == 0) 3664 imm = INT32_MIN; 3665 else 3666 imm = -imm; 3667 } 3668 Inst.addOperand(MCOperand::createImm(imm)); 3669 3670 return S; 3671 } 3672 3673 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3674 uint64_t Address, const void *Decoder) { 3675 if (Val == 0) 3676 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3677 else { 3678 int imm = Val & 0xFF; 3679 3680 if (!(Val & 0x100)) imm *= -1; 3681 Inst.addOperand(MCOperand::createImm(imm * 4)); 3682 } 3683 3684 return MCDisassembler::Success; 3685 } 3686 3687 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3688 uint64_t Address, const void *Decoder) { 3689 DecodeStatus S = MCDisassembler::Success; 3690 3691 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3692 unsigned imm = fieldFromInstruction(Val, 0, 9); 3693 3694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3695 return MCDisassembler::Fail; 3696 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3697 return MCDisassembler::Fail; 3698 3699 return S; 3700 } 3701 3702 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3703 uint64_t Address, const void *Decoder) { 3704 DecodeStatus S = MCDisassembler::Success; 3705 3706 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3707 unsigned imm = fieldFromInstruction(Val, 0, 8); 3708 3709 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3710 return MCDisassembler::Fail; 3711 3712 Inst.addOperand(MCOperand::createImm(imm)); 3713 3714 return S; 3715 } 3716 3717 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3718 uint64_t Address, const void *Decoder) { 3719 int imm = Val & 0xFF; 3720 if (Val == 0) 3721 imm = INT32_MIN; 3722 else if (!(Val & 0x100)) 3723 imm *= -1; 3724 Inst.addOperand(MCOperand::createImm(imm)); 3725 3726 return MCDisassembler::Success; 3727 } 3728 3729 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3730 uint64_t Address, const void *Decoder) { 3731 DecodeStatus S = MCDisassembler::Success; 3732 3733 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3734 unsigned imm = fieldFromInstruction(Val, 0, 9); 3735 3736 // Thumb stores cannot use PC as dest register. 3737 switch (Inst.getOpcode()) { 3738 case ARM::t2STRT: 3739 case ARM::t2STRBT: 3740 case ARM::t2STRHT: 3741 case ARM::t2STRi8: 3742 case ARM::t2STRHi8: 3743 case ARM::t2STRBi8: 3744 if (Rn == 15) 3745 return MCDisassembler::Fail; 3746 break; 3747 default: 3748 break; 3749 } 3750 3751 // Some instructions always use an additive offset. 3752 switch (Inst.getOpcode()) { 3753 case ARM::t2LDRT: 3754 case ARM::t2LDRBT: 3755 case ARM::t2LDRHT: 3756 case ARM::t2LDRSBT: 3757 case ARM::t2LDRSHT: 3758 case ARM::t2STRT: 3759 case ARM::t2STRBT: 3760 case ARM::t2STRHT: 3761 imm |= 0x100; 3762 break; 3763 default: 3764 break; 3765 } 3766 3767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3768 return MCDisassembler::Fail; 3769 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3770 return MCDisassembler::Fail; 3771 3772 return S; 3773 } 3774 3775 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3776 uint64_t Address, const void *Decoder) { 3777 DecodeStatus S = MCDisassembler::Success; 3778 3779 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3780 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3781 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3782 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3783 addr |= Rn << 9; 3784 unsigned load = fieldFromInstruction(Insn, 20, 1); 3785 3786 if (Rn == 15) { 3787 switch (Inst.getOpcode()) { 3788 case ARM::t2LDR_PRE: 3789 case ARM::t2LDR_POST: 3790 Inst.setOpcode(ARM::t2LDRpci); 3791 break; 3792 case ARM::t2LDRB_PRE: 3793 case ARM::t2LDRB_POST: 3794 Inst.setOpcode(ARM::t2LDRBpci); 3795 break; 3796 case ARM::t2LDRH_PRE: 3797 case ARM::t2LDRH_POST: 3798 Inst.setOpcode(ARM::t2LDRHpci); 3799 break; 3800 case ARM::t2LDRSB_PRE: 3801 case ARM::t2LDRSB_POST: 3802 if (Rt == 15) 3803 Inst.setOpcode(ARM::t2PLIpci); 3804 else 3805 Inst.setOpcode(ARM::t2LDRSBpci); 3806 break; 3807 case ARM::t2LDRSH_PRE: 3808 case ARM::t2LDRSH_POST: 3809 Inst.setOpcode(ARM::t2LDRSHpci); 3810 break; 3811 default: 3812 return MCDisassembler::Fail; 3813 } 3814 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3815 } 3816 3817 if (!load) { 3818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3819 return MCDisassembler::Fail; 3820 } 3821 3822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3823 return MCDisassembler::Fail; 3824 3825 if (load) { 3826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3827 return MCDisassembler::Fail; 3828 } 3829 3830 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3831 return MCDisassembler::Fail; 3832 3833 return S; 3834 } 3835 3836 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3837 uint64_t Address, const void *Decoder) { 3838 DecodeStatus S = MCDisassembler::Success; 3839 3840 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3841 unsigned imm = fieldFromInstruction(Val, 0, 12); 3842 3843 // Thumb stores cannot use PC as dest register. 3844 switch (Inst.getOpcode()) { 3845 case ARM::t2STRi12: 3846 case ARM::t2STRBi12: 3847 case ARM::t2STRHi12: 3848 if (Rn == 15) 3849 return MCDisassembler::Fail; 3850 default: 3851 break; 3852 } 3853 3854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3855 return MCDisassembler::Fail; 3856 Inst.addOperand(MCOperand::createImm(imm)); 3857 3858 return S; 3859 } 3860 3861 3862 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3863 uint64_t Address, const void *Decoder) { 3864 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3865 3866 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3867 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3868 Inst.addOperand(MCOperand::createImm(imm)); 3869 3870 return MCDisassembler::Success; 3871 } 3872 3873 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3874 uint64_t Address, const void *Decoder) { 3875 DecodeStatus S = MCDisassembler::Success; 3876 3877 if (Inst.getOpcode() == ARM::tADDrSP) { 3878 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3879 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3880 3881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3882 return MCDisassembler::Fail; 3883 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3885 return MCDisassembler::Fail; 3886 } else if (Inst.getOpcode() == ARM::tADDspr) { 3887 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3888 3889 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3890 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3892 return MCDisassembler::Fail; 3893 } 3894 3895 return S; 3896 } 3897 3898 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3899 uint64_t Address, const void *Decoder) { 3900 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3901 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3902 3903 Inst.addOperand(MCOperand::createImm(imod)); 3904 Inst.addOperand(MCOperand::createImm(flags)); 3905 3906 return MCDisassembler::Success; 3907 } 3908 3909 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3910 uint64_t Address, const void *Decoder) { 3911 DecodeStatus S = MCDisassembler::Success; 3912 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3913 unsigned add = fieldFromInstruction(Insn, 4, 1); 3914 3915 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3916 return MCDisassembler::Fail; 3917 Inst.addOperand(MCOperand::createImm(add)); 3918 3919 return S; 3920 } 3921 3922 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3923 uint64_t Address, const void *Decoder) { 3924 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3925 // Note only one trailing zero not two. Also the J1 and J2 values are from 3926 // the encoded instruction. So here change to I1 and I2 values via: 3927 // I1 = NOT(J1 EOR S); 3928 // I2 = NOT(J2 EOR S); 3929 // and build the imm32 with two trailing zeros as documented: 3930 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3931 unsigned S = (Val >> 23) & 1; 3932 unsigned J1 = (Val >> 22) & 1; 3933 unsigned J2 = (Val >> 21) & 1; 3934 unsigned I1 = !(J1 ^ S); 3935 unsigned I2 = !(J2 ^ S); 3936 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3937 int imm32 = SignExtend32<25>(tmp << 1); 3938 3939 if (!tryAddingSymbolicOperand(Address, 3940 (Address & ~2u) + imm32 + 4, 3941 true, 4, Inst, Decoder)) 3942 Inst.addOperand(MCOperand::createImm(imm32)); 3943 return MCDisassembler::Success; 3944 } 3945 3946 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3947 uint64_t Address, const void *Decoder) { 3948 if (Val == 0xA || Val == 0xB) 3949 return MCDisassembler::Fail; 3950 3951 const FeatureBitset &featureBits = 3952 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3953 3954 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 3955 return MCDisassembler::Fail; 3956 3957 Inst.addOperand(MCOperand::createImm(Val)); 3958 return MCDisassembler::Success; 3959 } 3960 3961 static DecodeStatus 3962 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3963 uint64_t Address, const void *Decoder) { 3964 DecodeStatus S = MCDisassembler::Success; 3965 3966 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3967 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3968 3969 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3970 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3971 return MCDisassembler::Fail; 3972 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3973 return MCDisassembler::Fail; 3974 return S; 3975 } 3976 3977 static DecodeStatus 3978 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3979 uint64_t Address, const void *Decoder) { 3980 DecodeStatus S = MCDisassembler::Success; 3981 3982 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3983 if (pred == 0xE || pred == 0xF) { 3984 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3985 switch (opc) { 3986 default: 3987 return MCDisassembler::Fail; 3988 case 0xf3bf8f4: 3989 Inst.setOpcode(ARM::t2DSB); 3990 break; 3991 case 0xf3bf8f5: 3992 Inst.setOpcode(ARM::t2DMB); 3993 break; 3994 case 0xf3bf8f6: 3995 Inst.setOpcode(ARM::t2ISB); 3996 break; 3997 } 3998 3999 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4000 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4001 } 4002 4003 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4004 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4005 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4006 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4007 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4008 4009 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4010 return MCDisassembler::Fail; 4011 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 4014 return S; 4015 } 4016 4017 // Decode a shifted immediate operand. These basically consist 4018 // of an 8-bit value, and a 4-bit directive that specifies either 4019 // a splat operation or a rotation. 4020 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4021 uint64_t Address, const void *Decoder) { 4022 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4023 if (ctrl == 0) { 4024 unsigned byte = fieldFromInstruction(Val, 8, 2); 4025 unsigned imm = fieldFromInstruction(Val, 0, 8); 4026 switch (byte) { 4027 case 0: 4028 Inst.addOperand(MCOperand::createImm(imm)); 4029 break; 4030 case 1: 4031 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4032 break; 4033 case 2: 4034 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4035 break; 4036 case 3: 4037 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4038 (imm << 8) | imm)); 4039 break; 4040 } 4041 } else { 4042 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4043 unsigned rot = fieldFromInstruction(Val, 7, 5); 4044 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4045 Inst.addOperand(MCOperand::createImm(imm)); 4046 } 4047 4048 return MCDisassembler::Success; 4049 } 4050 4051 static DecodeStatus 4052 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4053 uint64_t Address, const void *Decoder) { 4054 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4055 true, 2, Inst, Decoder)) 4056 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4057 return MCDisassembler::Success; 4058 } 4059 4060 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4061 uint64_t Address, 4062 const void *Decoder) { 4063 // Val is passed in as S:J1:J2:imm10:imm11 4064 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4065 // the encoded instruction. So here change to I1 and I2 values via: 4066 // I1 = NOT(J1 EOR S); 4067 // I2 = NOT(J2 EOR S); 4068 // and build the imm32 with one trailing zero as documented: 4069 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4070 unsigned S = (Val >> 23) & 1; 4071 unsigned J1 = (Val >> 22) & 1; 4072 unsigned J2 = (Val >> 21) & 1; 4073 unsigned I1 = !(J1 ^ S); 4074 unsigned I2 = !(J2 ^ S); 4075 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4076 int imm32 = SignExtend32<25>(tmp << 1); 4077 4078 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4079 true, 4, Inst, Decoder)) 4080 Inst.addOperand(MCOperand::createImm(imm32)); 4081 return MCDisassembler::Success; 4082 } 4083 4084 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4085 uint64_t Address, const void *Decoder) { 4086 if (Val & ~0xf) 4087 return MCDisassembler::Fail; 4088 4089 Inst.addOperand(MCOperand::createImm(Val)); 4090 return MCDisassembler::Success; 4091 } 4092 4093 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4094 uint64_t Address, const void *Decoder) { 4095 if (Val & ~0xf) 4096 return MCDisassembler::Fail; 4097 4098 Inst.addOperand(MCOperand::createImm(Val)); 4099 return MCDisassembler::Success; 4100 } 4101 4102 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4103 uint64_t Address, const void *Decoder) { 4104 DecodeStatus S = MCDisassembler::Success; 4105 const FeatureBitset &FeatureBits = 4106 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4107 4108 if (FeatureBits[ARM::FeatureMClass]) { 4109 unsigned ValLow = Val & 0xff; 4110 4111 // Validate the SYSm value first. 4112 switch (ValLow) { 4113 case 0: // apsr 4114 case 1: // iapsr 4115 case 2: // eapsr 4116 case 3: // xpsr 4117 case 5: // ipsr 4118 case 6: // epsr 4119 case 7: // iepsr 4120 case 8: // msp 4121 case 9: // psp 4122 case 16: // primask 4123 case 20: // control 4124 break; 4125 case 17: // basepri 4126 case 18: // basepri_max 4127 case 19: // faultmask 4128 if (!(FeatureBits[ARM::HasV7Ops])) 4129 // Values basepri, basepri_max and faultmask are only valid for v7m. 4130 return MCDisassembler::Fail; 4131 break; 4132 case 0x8a: // msplim_ns 4133 case 0x8b: // psplim_ns 4134 case 0x91: // basepri_ns 4135 case 0x92: // basepri_max_ns 4136 case 0x93: // faultmask_ns 4137 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4138 return MCDisassembler::Fail; 4139 LLVM_FALLTHROUGH; 4140 case 10: // msplim 4141 case 11: // psplim 4142 case 0x88: // msp_ns 4143 case 0x89: // psp_ns 4144 case 0x90: // primask_ns 4145 case 0x94: // control_ns 4146 case 0x98: // sp_ns 4147 if (!(FeatureBits[ARM::Feature8MSecExt])) 4148 return MCDisassembler::Fail; 4149 break; 4150 default: 4151 return MCDisassembler::Fail; 4152 } 4153 4154 if (Inst.getOpcode() == ARM::t2MSR_M) { 4155 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4156 if (!(FeatureBits[ARM::HasV7Ops])) { 4157 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4158 // unpredictable. 4159 if (Mask != 2) 4160 S = MCDisassembler::SoftFail; 4161 } 4162 else { 4163 // The ARMv7-M architecture stores an additional 2-bit mask value in 4164 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4165 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4166 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4167 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4168 // only if the processor includes the DSP extension. 4169 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4170 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4171 S = MCDisassembler::SoftFail; 4172 } 4173 } 4174 } else { 4175 // A/R class 4176 if (Val == 0) 4177 return MCDisassembler::Fail; 4178 } 4179 Inst.addOperand(MCOperand::createImm(Val)); 4180 return S; 4181 } 4182 4183 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4184 uint64_t Address, const void *Decoder) { 4185 4186 unsigned R = fieldFromInstruction(Val, 5, 1); 4187 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4188 4189 // The table of encodings for these banked registers comes from B9.2.3 of the 4190 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4191 // neater. So by fiat, these values are UNPREDICTABLE: 4192 if (!R) { 4193 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 4194 SysM == 0x1a || SysM == 0x1b) 4195 return MCDisassembler::SoftFail; 4196 } else { 4197 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 4198 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 4199 return MCDisassembler::SoftFail; 4200 } 4201 4202 Inst.addOperand(MCOperand::createImm(Val)); 4203 return MCDisassembler::Success; 4204 } 4205 4206 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4207 uint64_t Address, const void *Decoder) { 4208 DecodeStatus S = MCDisassembler::Success; 4209 4210 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4211 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4212 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4213 4214 if (Rn == 0xF) 4215 S = MCDisassembler::SoftFail; 4216 4217 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4218 return MCDisassembler::Fail; 4219 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4220 return MCDisassembler::Fail; 4221 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4222 return MCDisassembler::Fail; 4223 4224 return S; 4225 } 4226 4227 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4228 uint64_t Address, 4229 const void *Decoder) { 4230 DecodeStatus S = MCDisassembler::Success; 4231 4232 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4233 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4234 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4235 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4236 4237 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 4240 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4241 S = MCDisassembler::SoftFail; 4242 4243 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4246 return MCDisassembler::Fail; 4247 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4248 return MCDisassembler::Fail; 4249 4250 return S; 4251 } 4252 4253 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4254 uint64_t Address, const void *Decoder) { 4255 DecodeStatus S = MCDisassembler::Success; 4256 4257 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4258 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4259 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4260 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4261 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4262 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4263 4264 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4265 4266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4267 return MCDisassembler::Fail; 4268 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4271 return MCDisassembler::Fail; 4272 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4273 return MCDisassembler::Fail; 4274 4275 return S; 4276 } 4277 4278 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4279 uint64_t Address, const void *Decoder) { 4280 DecodeStatus S = MCDisassembler::Success; 4281 4282 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4283 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4284 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4285 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4286 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4287 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4288 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4289 4290 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4291 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4292 4293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4294 return MCDisassembler::Fail; 4295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4296 return MCDisassembler::Fail; 4297 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4298 return MCDisassembler::Fail; 4299 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 4302 return S; 4303 } 4304 4305 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4306 uint64_t Address, const void *Decoder) { 4307 DecodeStatus S = MCDisassembler::Success; 4308 4309 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4310 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4311 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4312 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4313 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4314 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4315 4316 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4317 4318 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4319 return MCDisassembler::Fail; 4320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4321 return MCDisassembler::Fail; 4322 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4323 return MCDisassembler::Fail; 4324 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4325 return MCDisassembler::Fail; 4326 4327 return S; 4328 } 4329 4330 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4331 uint64_t Address, const void *Decoder) { 4332 DecodeStatus S = MCDisassembler::Success; 4333 4334 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4335 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4336 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4337 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4338 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4339 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4340 4341 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4342 4343 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4344 return MCDisassembler::Fail; 4345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4346 return MCDisassembler::Fail; 4347 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4348 return MCDisassembler::Fail; 4349 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4350 return MCDisassembler::Fail; 4351 4352 return S; 4353 } 4354 4355 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4356 uint64_t Address, const void *Decoder) { 4357 DecodeStatus S = MCDisassembler::Success; 4358 4359 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4360 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4361 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4362 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4363 unsigned size = fieldFromInstruction(Insn, 10, 2); 4364 4365 unsigned align = 0; 4366 unsigned index = 0; 4367 switch (size) { 4368 default: 4369 return MCDisassembler::Fail; 4370 case 0: 4371 if (fieldFromInstruction(Insn, 4, 1)) 4372 return MCDisassembler::Fail; // UNDEFINED 4373 index = fieldFromInstruction(Insn, 5, 3); 4374 break; 4375 case 1: 4376 if (fieldFromInstruction(Insn, 5, 1)) 4377 return MCDisassembler::Fail; // UNDEFINED 4378 index = fieldFromInstruction(Insn, 6, 2); 4379 if (fieldFromInstruction(Insn, 4, 1)) 4380 align = 2; 4381 break; 4382 case 2: 4383 if (fieldFromInstruction(Insn, 6, 1)) 4384 return MCDisassembler::Fail; // UNDEFINED 4385 index = fieldFromInstruction(Insn, 7, 1); 4386 4387 switch (fieldFromInstruction(Insn, 4, 2)) { 4388 case 0 : 4389 align = 0; break; 4390 case 3: 4391 align = 4; break; 4392 default: 4393 return MCDisassembler::Fail; 4394 } 4395 break; 4396 } 4397 4398 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4399 return MCDisassembler::Fail; 4400 if (Rm != 0xF) { // Writeback 4401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4402 return MCDisassembler::Fail; 4403 } 4404 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4405 return MCDisassembler::Fail; 4406 Inst.addOperand(MCOperand::createImm(align)); 4407 if (Rm != 0xF) { 4408 if (Rm != 0xD) { 4409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4410 return MCDisassembler::Fail; 4411 } else 4412 Inst.addOperand(MCOperand::createReg(0)); 4413 } 4414 4415 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4416 return MCDisassembler::Fail; 4417 Inst.addOperand(MCOperand::createImm(index)); 4418 4419 return S; 4420 } 4421 4422 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4423 uint64_t Address, const void *Decoder) { 4424 DecodeStatus S = MCDisassembler::Success; 4425 4426 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4427 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4428 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4429 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4430 unsigned size = fieldFromInstruction(Insn, 10, 2); 4431 4432 unsigned align = 0; 4433 unsigned index = 0; 4434 switch (size) { 4435 default: 4436 return MCDisassembler::Fail; 4437 case 0: 4438 if (fieldFromInstruction(Insn, 4, 1)) 4439 return MCDisassembler::Fail; // UNDEFINED 4440 index = fieldFromInstruction(Insn, 5, 3); 4441 break; 4442 case 1: 4443 if (fieldFromInstruction(Insn, 5, 1)) 4444 return MCDisassembler::Fail; // UNDEFINED 4445 index = fieldFromInstruction(Insn, 6, 2); 4446 if (fieldFromInstruction(Insn, 4, 1)) 4447 align = 2; 4448 break; 4449 case 2: 4450 if (fieldFromInstruction(Insn, 6, 1)) 4451 return MCDisassembler::Fail; // UNDEFINED 4452 index = fieldFromInstruction(Insn, 7, 1); 4453 4454 switch (fieldFromInstruction(Insn, 4, 2)) { 4455 case 0: 4456 align = 0; break; 4457 case 3: 4458 align = 4; break; 4459 default: 4460 return MCDisassembler::Fail; 4461 } 4462 break; 4463 } 4464 4465 if (Rm != 0xF) { // Writeback 4466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4467 return MCDisassembler::Fail; 4468 } 4469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4470 return MCDisassembler::Fail; 4471 Inst.addOperand(MCOperand::createImm(align)); 4472 if (Rm != 0xF) { 4473 if (Rm != 0xD) { 4474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4475 return MCDisassembler::Fail; 4476 } else 4477 Inst.addOperand(MCOperand::createReg(0)); 4478 } 4479 4480 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4481 return MCDisassembler::Fail; 4482 Inst.addOperand(MCOperand::createImm(index)); 4483 4484 return S; 4485 } 4486 4487 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4488 uint64_t Address, const void *Decoder) { 4489 DecodeStatus S = MCDisassembler::Success; 4490 4491 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4492 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4493 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4494 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4495 unsigned size = fieldFromInstruction(Insn, 10, 2); 4496 4497 unsigned align = 0; 4498 unsigned index = 0; 4499 unsigned inc = 1; 4500 switch (size) { 4501 default: 4502 return MCDisassembler::Fail; 4503 case 0: 4504 index = fieldFromInstruction(Insn, 5, 3); 4505 if (fieldFromInstruction(Insn, 4, 1)) 4506 align = 2; 4507 break; 4508 case 1: 4509 index = fieldFromInstruction(Insn, 6, 2); 4510 if (fieldFromInstruction(Insn, 4, 1)) 4511 align = 4; 4512 if (fieldFromInstruction(Insn, 5, 1)) 4513 inc = 2; 4514 break; 4515 case 2: 4516 if (fieldFromInstruction(Insn, 5, 1)) 4517 return MCDisassembler::Fail; // UNDEFINED 4518 index = fieldFromInstruction(Insn, 7, 1); 4519 if (fieldFromInstruction(Insn, 4, 1) != 0) 4520 align = 8; 4521 if (fieldFromInstruction(Insn, 6, 1)) 4522 inc = 2; 4523 break; 4524 } 4525 4526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4527 return MCDisassembler::Fail; 4528 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4529 return MCDisassembler::Fail; 4530 if (Rm != 0xF) { // Writeback 4531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4532 return MCDisassembler::Fail; 4533 } 4534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4535 return MCDisassembler::Fail; 4536 Inst.addOperand(MCOperand::createImm(align)); 4537 if (Rm != 0xF) { 4538 if (Rm != 0xD) { 4539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4540 return MCDisassembler::Fail; 4541 } else 4542 Inst.addOperand(MCOperand::createReg(0)); 4543 } 4544 4545 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4546 return MCDisassembler::Fail; 4547 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4548 return MCDisassembler::Fail; 4549 Inst.addOperand(MCOperand::createImm(index)); 4550 4551 return S; 4552 } 4553 4554 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4555 uint64_t Address, const void *Decoder) { 4556 DecodeStatus S = MCDisassembler::Success; 4557 4558 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4559 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4560 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4561 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4562 unsigned size = fieldFromInstruction(Insn, 10, 2); 4563 4564 unsigned align = 0; 4565 unsigned index = 0; 4566 unsigned inc = 1; 4567 switch (size) { 4568 default: 4569 return MCDisassembler::Fail; 4570 case 0: 4571 index = fieldFromInstruction(Insn, 5, 3); 4572 if (fieldFromInstruction(Insn, 4, 1)) 4573 align = 2; 4574 break; 4575 case 1: 4576 index = fieldFromInstruction(Insn, 6, 2); 4577 if (fieldFromInstruction(Insn, 4, 1)) 4578 align = 4; 4579 if (fieldFromInstruction(Insn, 5, 1)) 4580 inc = 2; 4581 break; 4582 case 2: 4583 if (fieldFromInstruction(Insn, 5, 1)) 4584 return MCDisassembler::Fail; // UNDEFINED 4585 index = fieldFromInstruction(Insn, 7, 1); 4586 if (fieldFromInstruction(Insn, 4, 1) != 0) 4587 align = 8; 4588 if (fieldFromInstruction(Insn, 6, 1)) 4589 inc = 2; 4590 break; 4591 } 4592 4593 if (Rm != 0xF) { // Writeback 4594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4595 return MCDisassembler::Fail; 4596 } 4597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4598 return MCDisassembler::Fail; 4599 Inst.addOperand(MCOperand::createImm(align)); 4600 if (Rm != 0xF) { 4601 if (Rm != 0xD) { 4602 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4603 return MCDisassembler::Fail; 4604 } else 4605 Inst.addOperand(MCOperand::createReg(0)); 4606 } 4607 4608 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4609 return MCDisassembler::Fail; 4610 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4611 return MCDisassembler::Fail; 4612 Inst.addOperand(MCOperand::createImm(index)); 4613 4614 return S; 4615 } 4616 4617 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4618 uint64_t Address, const void *Decoder) { 4619 DecodeStatus S = MCDisassembler::Success; 4620 4621 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4622 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4623 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4624 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4625 unsigned size = fieldFromInstruction(Insn, 10, 2); 4626 4627 unsigned align = 0; 4628 unsigned index = 0; 4629 unsigned inc = 1; 4630 switch (size) { 4631 default: 4632 return MCDisassembler::Fail; 4633 case 0: 4634 if (fieldFromInstruction(Insn, 4, 1)) 4635 return MCDisassembler::Fail; // UNDEFINED 4636 index = fieldFromInstruction(Insn, 5, 3); 4637 break; 4638 case 1: 4639 if (fieldFromInstruction(Insn, 4, 1)) 4640 return MCDisassembler::Fail; // UNDEFINED 4641 index = fieldFromInstruction(Insn, 6, 2); 4642 if (fieldFromInstruction(Insn, 5, 1)) 4643 inc = 2; 4644 break; 4645 case 2: 4646 if (fieldFromInstruction(Insn, 4, 2)) 4647 return MCDisassembler::Fail; // UNDEFINED 4648 index = fieldFromInstruction(Insn, 7, 1); 4649 if (fieldFromInstruction(Insn, 6, 1)) 4650 inc = 2; 4651 break; 4652 } 4653 4654 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4655 return MCDisassembler::Fail; 4656 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4657 return MCDisassembler::Fail; 4658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4659 return MCDisassembler::Fail; 4660 4661 if (Rm != 0xF) { // Writeback 4662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4663 return MCDisassembler::Fail; 4664 } 4665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4666 return MCDisassembler::Fail; 4667 Inst.addOperand(MCOperand::createImm(align)); 4668 if (Rm != 0xF) { 4669 if (Rm != 0xD) { 4670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4671 return MCDisassembler::Fail; 4672 } else 4673 Inst.addOperand(MCOperand::createReg(0)); 4674 } 4675 4676 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4677 return MCDisassembler::Fail; 4678 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 Inst.addOperand(MCOperand::createImm(index)); 4683 4684 return S; 4685 } 4686 4687 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4688 uint64_t Address, const void *Decoder) { 4689 DecodeStatus S = MCDisassembler::Success; 4690 4691 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4692 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4693 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4694 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4695 unsigned size = fieldFromInstruction(Insn, 10, 2); 4696 4697 unsigned align = 0; 4698 unsigned index = 0; 4699 unsigned inc = 1; 4700 switch (size) { 4701 default: 4702 return MCDisassembler::Fail; 4703 case 0: 4704 if (fieldFromInstruction(Insn, 4, 1)) 4705 return MCDisassembler::Fail; // UNDEFINED 4706 index = fieldFromInstruction(Insn, 5, 3); 4707 break; 4708 case 1: 4709 if (fieldFromInstruction(Insn, 4, 1)) 4710 return MCDisassembler::Fail; // UNDEFINED 4711 index = fieldFromInstruction(Insn, 6, 2); 4712 if (fieldFromInstruction(Insn, 5, 1)) 4713 inc = 2; 4714 break; 4715 case 2: 4716 if (fieldFromInstruction(Insn, 4, 2)) 4717 return MCDisassembler::Fail; // UNDEFINED 4718 index = fieldFromInstruction(Insn, 7, 1); 4719 if (fieldFromInstruction(Insn, 6, 1)) 4720 inc = 2; 4721 break; 4722 } 4723 4724 if (Rm != 0xF) { // Writeback 4725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4726 return MCDisassembler::Fail; 4727 } 4728 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4729 return MCDisassembler::Fail; 4730 Inst.addOperand(MCOperand::createImm(align)); 4731 if (Rm != 0xF) { 4732 if (Rm != 0xD) { 4733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4734 return MCDisassembler::Fail; 4735 } else 4736 Inst.addOperand(MCOperand::createReg(0)); 4737 } 4738 4739 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4740 return MCDisassembler::Fail; 4741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4744 return MCDisassembler::Fail; 4745 Inst.addOperand(MCOperand::createImm(index)); 4746 4747 return S; 4748 } 4749 4750 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4751 uint64_t Address, const void *Decoder) { 4752 DecodeStatus S = MCDisassembler::Success; 4753 4754 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4755 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4756 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4757 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4758 unsigned size = fieldFromInstruction(Insn, 10, 2); 4759 4760 unsigned align = 0; 4761 unsigned index = 0; 4762 unsigned inc = 1; 4763 switch (size) { 4764 default: 4765 return MCDisassembler::Fail; 4766 case 0: 4767 if (fieldFromInstruction(Insn, 4, 1)) 4768 align = 4; 4769 index = fieldFromInstruction(Insn, 5, 3); 4770 break; 4771 case 1: 4772 if (fieldFromInstruction(Insn, 4, 1)) 4773 align = 8; 4774 index = fieldFromInstruction(Insn, 6, 2); 4775 if (fieldFromInstruction(Insn, 5, 1)) 4776 inc = 2; 4777 break; 4778 case 2: 4779 switch (fieldFromInstruction(Insn, 4, 2)) { 4780 case 0: 4781 align = 0; break; 4782 case 3: 4783 return MCDisassembler::Fail; 4784 default: 4785 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4786 } 4787 4788 index = fieldFromInstruction(Insn, 7, 1); 4789 if (fieldFromInstruction(Insn, 6, 1)) 4790 inc = 2; 4791 break; 4792 } 4793 4794 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4795 return MCDisassembler::Fail; 4796 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4797 return MCDisassembler::Fail; 4798 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4799 return MCDisassembler::Fail; 4800 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4801 return MCDisassembler::Fail; 4802 4803 if (Rm != 0xF) { // Writeback 4804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4805 return MCDisassembler::Fail; 4806 } 4807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4808 return MCDisassembler::Fail; 4809 Inst.addOperand(MCOperand::createImm(align)); 4810 if (Rm != 0xF) { 4811 if (Rm != 0xD) { 4812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4813 return MCDisassembler::Fail; 4814 } else 4815 Inst.addOperand(MCOperand::createReg(0)); 4816 } 4817 4818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4819 return MCDisassembler::Fail; 4820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4821 return MCDisassembler::Fail; 4822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4823 return MCDisassembler::Fail; 4824 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4825 return MCDisassembler::Fail; 4826 Inst.addOperand(MCOperand::createImm(index)); 4827 4828 return S; 4829 } 4830 4831 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4832 uint64_t Address, const void *Decoder) { 4833 DecodeStatus S = MCDisassembler::Success; 4834 4835 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4836 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4837 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4838 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4839 unsigned size = fieldFromInstruction(Insn, 10, 2); 4840 4841 unsigned align = 0; 4842 unsigned index = 0; 4843 unsigned inc = 1; 4844 switch (size) { 4845 default: 4846 return MCDisassembler::Fail; 4847 case 0: 4848 if (fieldFromInstruction(Insn, 4, 1)) 4849 align = 4; 4850 index = fieldFromInstruction(Insn, 5, 3); 4851 break; 4852 case 1: 4853 if (fieldFromInstruction(Insn, 4, 1)) 4854 align = 8; 4855 index = fieldFromInstruction(Insn, 6, 2); 4856 if (fieldFromInstruction(Insn, 5, 1)) 4857 inc = 2; 4858 break; 4859 case 2: 4860 switch (fieldFromInstruction(Insn, 4, 2)) { 4861 case 0: 4862 align = 0; break; 4863 case 3: 4864 return MCDisassembler::Fail; 4865 default: 4866 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4867 } 4868 4869 index = fieldFromInstruction(Insn, 7, 1); 4870 if (fieldFromInstruction(Insn, 6, 1)) 4871 inc = 2; 4872 break; 4873 } 4874 4875 if (Rm != 0xF) { // Writeback 4876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4877 return MCDisassembler::Fail; 4878 } 4879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4880 return MCDisassembler::Fail; 4881 Inst.addOperand(MCOperand::createImm(align)); 4882 if (Rm != 0xF) { 4883 if (Rm != 0xD) { 4884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4885 return MCDisassembler::Fail; 4886 } else 4887 Inst.addOperand(MCOperand::createReg(0)); 4888 } 4889 4890 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4891 return MCDisassembler::Fail; 4892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4893 return MCDisassembler::Fail; 4894 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4895 return MCDisassembler::Fail; 4896 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4897 return MCDisassembler::Fail; 4898 Inst.addOperand(MCOperand::createImm(index)); 4899 4900 return S; 4901 } 4902 4903 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4904 uint64_t Address, const void *Decoder) { 4905 DecodeStatus S = MCDisassembler::Success; 4906 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4907 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4908 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4909 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4910 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4911 4912 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4913 S = MCDisassembler::SoftFail; 4914 4915 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4916 return MCDisassembler::Fail; 4917 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4918 return MCDisassembler::Fail; 4919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4920 return MCDisassembler::Fail; 4921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4922 return MCDisassembler::Fail; 4923 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4924 return MCDisassembler::Fail; 4925 4926 return S; 4927 } 4928 4929 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4930 uint64_t Address, const void *Decoder) { 4931 DecodeStatus S = MCDisassembler::Success; 4932 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4933 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4934 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4935 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4936 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4937 4938 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4939 S = MCDisassembler::SoftFail; 4940 4941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4942 return MCDisassembler::Fail; 4943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4944 return MCDisassembler::Fail; 4945 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4946 return MCDisassembler::Fail; 4947 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4948 return MCDisassembler::Fail; 4949 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4950 return MCDisassembler::Fail; 4951 4952 return S; 4953 } 4954 4955 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4956 uint64_t Address, const void *Decoder) { 4957 DecodeStatus S = MCDisassembler::Success; 4958 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4959 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4960 4961 if (pred == 0xF) { 4962 pred = 0xE; 4963 S = MCDisassembler::SoftFail; 4964 } 4965 4966 if (mask == 0x0) 4967 return MCDisassembler::Fail; 4968 4969 Inst.addOperand(MCOperand::createImm(pred)); 4970 Inst.addOperand(MCOperand::createImm(mask)); 4971 return S; 4972 } 4973 4974 static DecodeStatus 4975 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4976 uint64_t Address, const void *Decoder) { 4977 DecodeStatus S = MCDisassembler::Success; 4978 4979 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4980 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4981 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4982 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4983 unsigned W = fieldFromInstruction(Insn, 21, 1); 4984 unsigned U = fieldFromInstruction(Insn, 23, 1); 4985 unsigned P = fieldFromInstruction(Insn, 24, 1); 4986 bool writeback = (W == 1) | (P == 0); 4987 4988 addr |= (U << 8) | (Rn << 9); 4989 4990 if (writeback && (Rn == Rt || Rn == Rt2)) 4991 Check(S, MCDisassembler::SoftFail); 4992 if (Rt == Rt2) 4993 Check(S, MCDisassembler::SoftFail); 4994 4995 // Rt 4996 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4997 return MCDisassembler::Fail; 4998 // Rt2 4999 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5000 return MCDisassembler::Fail; 5001 // Writeback operand 5002 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5003 return MCDisassembler::Fail; 5004 // addr 5005 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5006 return MCDisassembler::Fail; 5007 5008 return S; 5009 } 5010 5011 static DecodeStatus 5012 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5013 uint64_t Address, const void *Decoder) { 5014 DecodeStatus S = MCDisassembler::Success; 5015 5016 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5017 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5018 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5019 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5020 unsigned W = fieldFromInstruction(Insn, 21, 1); 5021 unsigned U = fieldFromInstruction(Insn, 23, 1); 5022 unsigned P = fieldFromInstruction(Insn, 24, 1); 5023 bool writeback = (W == 1) | (P == 0); 5024 5025 addr |= (U << 8) | (Rn << 9); 5026 5027 if (writeback && (Rn == Rt || Rn == Rt2)) 5028 Check(S, MCDisassembler::SoftFail); 5029 5030 // Writeback operand 5031 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5032 return MCDisassembler::Fail; 5033 // Rt 5034 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5035 return MCDisassembler::Fail; 5036 // Rt2 5037 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5038 return MCDisassembler::Fail; 5039 // addr 5040 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5041 return MCDisassembler::Fail; 5042 5043 return S; 5044 } 5045 5046 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5047 uint64_t Address, const void *Decoder) { 5048 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5049 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5050 if (sign1 != sign2) return MCDisassembler::Fail; 5051 5052 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5053 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5054 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5055 Val |= sign1 << 12; 5056 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5057 5058 return MCDisassembler::Success; 5059 } 5060 5061 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5062 uint64_t Address, 5063 const void *Decoder) { 5064 DecodeStatus S = MCDisassembler::Success; 5065 5066 // Shift of "asr #32" is not allowed in Thumb2 mode. 5067 if (Val == 0x20) S = MCDisassembler::Fail; 5068 Inst.addOperand(MCOperand::createImm(Val)); 5069 return S; 5070 } 5071 5072 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5073 uint64_t Address, const void *Decoder) { 5074 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5075 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5076 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5077 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5078 5079 if (pred == 0xF) 5080 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5081 5082 DecodeStatus S = MCDisassembler::Success; 5083 5084 if (Rt == Rn || Rn == Rt2) 5085 S = MCDisassembler::SoftFail; 5086 5087 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5088 return MCDisassembler::Fail; 5089 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5090 return MCDisassembler::Fail; 5091 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5092 return MCDisassembler::Fail; 5093 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5094 return MCDisassembler::Fail; 5095 5096 return S; 5097 } 5098 5099 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5100 uint64_t Address, const void *Decoder) { 5101 const FeatureBitset &featureBits = 5102 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5103 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5104 5105 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5106 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5107 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5108 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5109 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5110 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5111 unsigned op = fieldFromInstruction(Insn, 5, 1); 5112 5113 DecodeStatus S = MCDisassembler::Success; 5114 5115 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5116 if (!(imm & 0x38)) { 5117 if (cmode == 0xF) { 5118 if (op == 1) return MCDisassembler::Fail; 5119 Inst.setOpcode(ARM::VMOVv2f32); 5120 } 5121 if (hasFullFP16) { 5122 if (cmode == 0xE) { 5123 if (op == 1) { 5124 Inst.setOpcode(ARM::VMOVv1i64); 5125 } else { 5126 Inst.setOpcode(ARM::VMOVv8i8); 5127 } 5128 } 5129 if (cmode == 0xD) { 5130 if (op == 1) { 5131 Inst.setOpcode(ARM::VMVNv2i32); 5132 } else { 5133 Inst.setOpcode(ARM::VMOVv2i32); 5134 } 5135 } 5136 if (cmode == 0xC) { 5137 if (op == 1) { 5138 Inst.setOpcode(ARM::VMVNv2i32); 5139 } else { 5140 Inst.setOpcode(ARM::VMOVv2i32); 5141 } 5142 } 5143 } 5144 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5145 } 5146 5147 if (!(imm & 0x20)) return MCDisassembler::Fail; 5148 5149 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5150 return MCDisassembler::Fail; 5151 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5152 return MCDisassembler::Fail; 5153 Inst.addOperand(MCOperand::createImm(64 - imm)); 5154 5155 return S; 5156 } 5157 5158 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5159 uint64_t Address, const void *Decoder) { 5160 const FeatureBitset &featureBits = 5161 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5162 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5163 5164 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5165 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5166 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5167 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5168 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5169 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5170 unsigned op = fieldFromInstruction(Insn, 5, 1); 5171 5172 DecodeStatus S = MCDisassembler::Success; 5173 5174 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5175 if (!(imm & 0x38)) { 5176 if (cmode == 0xF) { 5177 if (op == 1) return MCDisassembler::Fail; 5178 Inst.setOpcode(ARM::VMOVv4f32); 5179 } 5180 if (hasFullFP16) { 5181 if (cmode == 0xE) { 5182 if (op == 1) { 5183 Inst.setOpcode(ARM::VMOVv2i64); 5184 } else { 5185 Inst.setOpcode(ARM::VMOVv16i8); 5186 } 5187 } 5188 if (cmode == 0xD) { 5189 if (op == 1) { 5190 Inst.setOpcode(ARM::VMVNv4i32); 5191 } else { 5192 Inst.setOpcode(ARM::VMOVv4i32); 5193 } 5194 } 5195 if (cmode == 0xC) { 5196 if (op == 1) { 5197 Inst.setOpcode(ARM::VMVNv4i32); 5198 } else { 5199 Inst.setOpcode(ARM::VMOVv4i32); 5200 } 5201 } 5202 } 5203 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5204 } 5205 5206 if (!(imm & 0x20)) return MCDisassembler::Fail; 5207 5208 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5209 return MCDisassembler::Fail; 5210 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5211 return MCDisassembler::Fail; 5212 Inst.addOperand(MCOperand::createImm(64 - imm)); 5213 5214 return S; 5215 } 5216 5217 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5218 uint64_t Address, const void *Decoder) { 5219 DecodeStatus S = MCDisassembler::Success; 5220 5221 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5222 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5223 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5224 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5225 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5226 5227 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5228 S = MCDisassembler::SoftFail; 5229 5230 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5231 return MCDisassembler::Fail; 5232 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5233 return MCDisassembler::Fail; 5234 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5235 return MCDisassembler::Fail; 5236 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5237 return MCDisassembler::Fail; 5238 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5239 return MCDisassembler::Fail; 5240 5241 return S; 5242 } 5243 5244 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5245 uint64_t Address, const void *Decoder) { 5246 DecodeStatus S = MCDisassembler::Success; 5247 5248 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5249 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5250 unsigned cop = fieldFromInstruction(Val, 8, 4); 5251 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5252 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5253 5254 if ((cop & ~0x1) == 0xa) 5255 return MCDisassembler::Fail; 5256 5257 if (Rt == Rt2) 5258 S = MCDisassembler::SoftFail; 5259 5260 // We have to check if the instruction is MRRC2 5261 // or MCRR2 when constructing the operands for 5262 // Inst. Reason is because MRRC2 stores to two 5263 // registers so it's tablegen desc has has two 5264 // outputs whereas MCRR doesn't store to any 5265 // registers so all of it's operands are listed 5266 // as inputs, therefore the operand order for 5267 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5268 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5269 5270 if (Inst.getOpcode() == ARM::MRRC2) { 5271 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5272 return MCDisassembler::Fail; 5273 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5274 return MCDisassembler::Fail; 5275 } 5276 Inst.addOperand(MCOperand::createImm(cop)); 5277 Inst.addOperand(MCOperand::createImm(opc1)); 5278 if (Inst.getOpcode() == ARM::MCRR2) { 5279 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5280 return MCDisassembler::Fail; 5281 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5282 return MCDisassembler::Fail; 5283 } 5284 Inst.addOperand(MCOperand::createImm(CRm)); 5285 5286 return S; 5287 } 5288