1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156 }; 157 158 } // end anonymous namespace 159 160 static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173 } 174 175 // Forward declare these because the autogenerated code will reference them. 176 // Definitions are further down. 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 186 unsigned RegNo, uint64_t Address, 187 const void *Decoder); 188 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 195 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 205 uint64_t Address, 206 const void *Decoder); 207 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 218 unsigned RegNo, 219 uint64_t Address, 220 const void *Decoder); 221 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 232 unsigned RegNo, uint64_t Address, 233 const void *Decoder); 234 235 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 246 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 251 unsigned Insn, 252 uint64_t Address, 253 const void *Decoder); 254 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 261 uint64_t Address, const void *Decoder); 262 263 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 264 unsigned Insn, 265 uint64_t Adddress, 266 const void *Decoder); 267 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339 template<int shift> 340 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 393 unsigned Val, 394 uint64_t Address, 395 const void *Decoder); 396 397 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 408 uint64_t Address, const void *Decoder); 409 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 410 uint64_t Address, const void *Decoder); 411 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 412 uint64_t Address, const void *Decoder); 413 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 414 uint64_t Address, const void *Decoder); 415 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 416 uint64_t Address, const void *Decoder); 417 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 418 uint64_t Address, const void* Decoder); 419 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 420 uint64_t Address, const void* Decoder); 421 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 422 uint64_t Address, const void* Decoder); 423 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 424 uint64_t Address, const void* Decoder); 425 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 426 uint64_t Address, const void *Decoder); 427 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 428 uint64_t Address, const void *Decoder); 429 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 430 uint64_t Address, const void *Decoder); 431 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 432 uint64_t Address, 433 const void *Decoder); 434 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 435 uint64_t Address, const void *Decoder); 436 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 437 uint64_t Address, const void *Decoder); 438 template<int shift> 439 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443 template<int shift> 444 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 template<int shift, int WriteBack> 447 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 448 uint64_t Address, const void *Decoder); 449 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 450 uint64_t Address, const void *Decoder); 451 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 452 uint64_t Address, const void *Decoder); 453 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 454 uint64_t Address, const void *Decoder); 455 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 456 uint64_t Address, const void *Decoder); 457 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 458 uint64_t Address, const void *Decoder); 459 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 460 uint64_t Address, const void *Decoder); 461 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 462 uint64_t Address, const void *Decoder); 463 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 464 uint64_t Address, const void *Decoder); 465 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 466 uint64_t Address, const void *Decoder); 467 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 468 uint64_t Address, const void *Decoder); 469 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 470 uint64_t Address, const void *Decoder); 471 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 472 uint64_t Address, const void *Decoder); 473 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 474 uint64_t Address, const void *Decoder); 475 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 476 uint64_t Address, const void *Decoder); 477 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 478 uint64_t Address, const void *Decoder); 479 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 480 uint64_t Address, const void *Decoder); 481 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 482 uint64_t Address, const void *Decoder); 483 484 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 489 uint64_t Address, const void *Decoder); 490 491 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 492 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 493 uint64_t Address, const void *Decoder); 494 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 495 uint64_t Address, 496 const void *Decoder); 497 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 498 uint64_t Address, 499 const void *Decoder); 500 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 501 const void *Decoder); 502 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const void *Decoder); 505 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 506 const void *Decoder); 507 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 508 uint64_t Address, const void *Decoder); 509 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 510 uint64_t Address, const void *Decoder); 511 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 512 uint64_t Address, 513 const void *Decoder); 514 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, 516 const void *Decoder); 517 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 518 uint64_t Address, 519 const void *Decoder); 520 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 521 unsigned Val, 522 uint64_t Address, 523 const void *Decoder); 524 template<bool Writeback> 525 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 526 uint64_t Address, 527 const void *Decoder); 528 template<int shift> 529 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 530 uint64_t Address, const void *Decoder); 531 template<int shift> 532 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 533 uint64_t Address, const void *Decoder); 534 template<int shift> 535 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 536 uint64_t Address, const void *Decoder); 537 template<unsigned MinLog, unsigned MaxLog> 538 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 539 uint64_t Address, 540 const void *Decoder); 541 template<unsigned start> 542 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 543 uint64_t Address, 544 const void *Decoder); 545 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 546 uint64_t Address, 547 const void *Decoder); 548 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 549 uint64_t Address, 550 const void *Decoder); 551 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 552 uint64_t Address, const void *Decoder); 553 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 554 uint64_t Address, const void *Decoder); 555 template<bool scalar, OperandDecoder predicate_decoder> 556 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 557 uint64_t Address, const void *Decoder); 558 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 559 uint64_t Address, const void *Decoder); 560 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 561 uint64_t Address, const void *Decoder); 562 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 563 uint64_t Address, 564 const void *Decoder); 565 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 566 uint64_t Address, const void *Decoder); 567 568 #include "ARMGenDisassemblerTables.inc" 569 570 static MCDisassembler *createARMDisassembler(const Target &T, 571 const MCSubtargetInfo &STI, 572 MCContext &Ctx) { 573 return new ARMDisassembler(STI, Ctx); 574 } 575 576 // Post-decoding checks 577 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 578 uint64_t Address, raw_ostream &CS, 579 uint32_t Insn, 580 DecodeStatus Result) { 581 switch (MI.getOpcode()) { 582 case ARM::HVC: { 583 // HVC is undefined if condition = 0xf otherwise upredictable 584 // if condition != 0xe 585 uint32_t Cond = (Insn >> 28) & 0xF; 586 if (Cond == 0xF) 587 return MCDisassembler::Fail; 588 if (Cond != 0xE) 589 return MCDisassembler::SoftFail; 590 return Result; 591 } 592 case ARM::t2ADDri: 593 case ARM::t2ADDri12: 594 case ARM::t2ADDrr: 595 case ARM::t2ADDrs: 596 case ARM::t2SUBri: 597 case ARM::t2SUBri12: 598 case ARM::t2SUBrr: 599 case ARM::t2SUBrs: 600 if (MI.getOperand(0).getReg() == ARM::SP && 601 MI.getOperand(1).getReg() != ARM::SP) 602 return MCDisassembler::SoftFail; 603 return Result; 604 default: return Result; 605 } 606 } 607 608 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 609 ArrayRef<uint8_t> Bytes, 610 uint64_t Address, 611 raw_ostream &CS) const { 612 if (STI.getFeatureBits()[ARM::ModeThumb]) 613 return getThumbInstruction(MI, Size, Bytes, Address, CS); 614 return getARMInstruction(MI, Size, Bytes, Address, CS); 615 } 616 617 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 618 ArrayRef<uint8_t> Bytes, 619 uint64_t Address, 620 raw_ostream &CS) const { 621 CommentStream = &CS; 622 623 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 624 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 625 "mode!"); 626 627 // We want to read exactly 4 bytes of data. 628 if (Bytes.size() < 4) { 629 Size = 0; 630 return MCDisassembler::Fail; 631 } 632 633 // Encoded as a small-endian 32-bit word in the stream. 634 uint32_t Insn = 635 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 636 637 // Calling the auto-generated decoder function. 638 DecodeStatus Result = 639 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 640 if (Result != MCDisassembler::Fail) { 641 Size = 4; 642 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 643 } 644 645 struct DecodeTable { 646 const uint8_t *P; 647 bool DecodePred; 648 }; 649 650 const DecodeTable Tables[] = { 651 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 652 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 653 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 654 {DecoderTablev8Crypto32, false}, 655 }; 656 657 for (auto Table : Tables) { 658 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 659 if (Result != MCDisassembler::Fail) { 660 Size = 4; 661 // Add a fake predicate operand, because we share these instruction 662 // definitions with Thumb2 where these instructions are predicable. 663 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 664 return MCDisassembler::Fail; 665 return Result; 666 } 667 } 668 669 Result = 670 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 671 if (Result != MCDisassembler::Fail) { 672 Size = 4; 673 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 674 } 675 676 Size = 4; 677 return MCDisassembler::Fail; 678 } 679 680 namespace llvm { 681 682 extern const MCInstrDesc ARMInsts[]; 683 684 } // end namespace llvm 685 686 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 687 /// immediate Value in the MCInst. The immediate Value has had any PC 688 /// adjustment made by the caller. If the instruction is a branch instruction 689 /// then isBranch is true, else false. If the getOpInfo() function was set as 690 /// part of the setupForSymbolicDisassembly() call then that function is called 691 /// to get any symbolic information at the Address for this instruction. If 692 /// that returns non-zero then the symbolic information it returns is used to 693 /// create an MCExpr and that is added as an operand to the MCInst. If 694 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 695 /// Value is done and if a symbol is found an MCExpr is created with that, else 696 /// an MCExpr with Value is created. This function returns true if it adds an 697 /// operand to the MCInst and false otherwise. 698 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 699 bool isBranch, uint64_t InstSize, 700 MCInst &MI, const void *Decoder) { 701 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 702 // FIXME: Does it make sense for value to be negative? 703 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 704 /* Offset */ 0, InstSize); 705 } 706 707 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 708 /// referenced by a load instruction with the base register that is the Pc. 709 /// These can often be values in a literal pool near the Address of the 710 /// instruction. The Address of the instruction and its immediate Value are 711 /// used as a possible literal pool entry. The SymbolLookUp call back will 712 /// return the name of a symbol referenced by the literal pool's entry if 713 /// the referenced address is that of a symbol. Or it will return a pointer to 714 /// a literal 'C' string if the referenced address of the literal pool's entry 715 /// is an address into a section with 'C' string literals. 716 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 717 const void *Decoder) { 718 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 719 Dis->tryAddingPcLoadReferenceComment(Value, Address); 720 } 721 722 // Thumb1 instructions don't have explicit S bits. Rather, they 723 // implicitly set CPSR. Since it's not represented in the encoding, the 724 // auto-generated decoder won't inject the CPSR operand. We need to fix 725 // that as a post-pass. 726 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 727 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 728 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 729 MCInst::iterator I = MI.begin(); 730 for (unsigned i = 0; i < NumOps; ++i, ++I) { 731 if (I == MI.end()) break; 732 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 733 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 734 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 735 return; 736 } 737 } 738 739 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 740 } 741 742 static bool isVectorPredicable(unsigned Opcode) { 743 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 744 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 745 for (unsigned i = 0; i < NumOps; ++i) { 746 if (ARM::isVpred(OpInfo[i].OperandType)) 747 return true; 748 } 749 return false; 750 } 751 752 // Most Thumb instructions don't have explicit predicates in the 753 // encoding, but rather get their predicates from IT context. We need 754 // to fix up the predicate operands using this context information as a 755 // post-pass. 756 MCDisassembler::DecodeStatus 757 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 758 MCDisassembler::DecodeStatus S = Success; 759 760 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 761 762 // A few instructions actually have predicates encoded in them. Don't 763 // try to overwrite it if we're seeing one of those. 764 switch (MI.getOpcode()) { 765 case ARM::tBcc: 766 case ARM::t2Bcc: 767 case ARM::tCBZ: 768 case ARM::tCBNZ: 769 case ARM::tCPS: 770 case ARM::t2CPS3p: 771 case ARM::t2CPS2p: 772 case ARM::t2CPS1p: 773 case ARM::t2CSEL: 774 case ARM::t2CSINC: 775 case ARM::t2CSINV: 776 case ARM::t2CSNEG: 777 case ARM::tMOVSr: 778 case ARM::tSETEND: 779 // Some instructions (mostly conditional branches) are not 780 // allowed in IT blocks. 781 if (ITBlock.instrInITBlock()) 782 S = SoftFail; 783 else 784 return Success; 785 break; 786 case ARM::t2HINT: 787 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 788 S = SoftFail; 789 break; 790 case ARM::tB: 791 case ARM::t2B: 792 case ARM::t2TBB: 793 case ARM::t2TBH: 794 // Some instructions (mostly unconditional branches) can 795 // only appears at the end of, or outside of, an IT. 796 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 797 S = SoftFail; 798 break; 799 default: 800 break; 801 } 802 803 // Warn on non-VPT predicable instruction in a VPT block and a VPT 804 // predicable instruction in an IT block 805 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 806 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 807 S = SoftFail; 808 809 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 810 // assume a predicate of AL. 811 unsigned CC = ARMCC::AL; 812 unsigned VCC = ARMVCC::None; 813 if (ITBlock.instrInITBlock()) { 814 CC = ITBlock.getITCC(); 815 ITBlock.advanceITState(); 816 } else if (VPTBlock.instrInVPTBlock()) { 817 VCC = VPTBlock.getVPTPred(); 818 VPTBlock.advanceVPTState(); 819 } 820 821 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 822 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 823 824 MCInst::iterator CCI = MI.begin(); 825 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 826 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 827 } 828 829 if (ARMInsts[MI.getOpcode()].isPredicable()) { 830 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 831 ++CCI; 832 if (CC == ARMCC::AL) 833 MI.insert(CCI, MCOperand::createReg(0)); 834 else 835 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 836 } else if (CC != ARMCC::AL) { 837 Check(S, SoftFail); 838 } 839 840 MCInst::iterator VCCI = MI.begin(); 841 unsigned VCCPos; 842 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 843 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 844 } 845 846 if (isVectorPredicable(MI.getOpcode())) { 847 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 848 ++VCCI; 849 if (VCC == ARMVCC::None) 850 MI.insert(VCCI, MCOperand::createReg(0)); 851 else 852 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 853 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 854 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 855 VCCPos + 2, MCOI::TIED_TO); 856 assert(TiedOp >= 0 && 857 "Inactive register in vpred_r is not tied to an output!"); 858 MI.insert(VCCI, MI.getOperand(TiedOp)); 859 } 860 } else if (VCC != ARMVCC::None) { 861 Check(S, SoftFail); 862 } 863 864 return S; 865 } 866 867 // Thumb VFP instructions are a special case. Because we share their 868 // encodings between ARM and Thumb modes, and they are predicable in ARM 869 // mode, the auto-generated decoder will give them an (incorrect) 870 // predicate operand. We need to rewrite these operands based on the IT 871 // context as a post-pass. 872 void ARMDisassembler::UpdateThumbVFPPredicate( 873 DecodeStatus &S, MCInst &MI) const { 874 unsigned CC; 875 CC = ITBlock.getITCC(); 876 if (CC == 0xF) 877 CC = ARMCC::AL; 878 if (ITBlock.instrInITBlock()) 879 ITBlock.advanceITState(); 880 else if (VPTBlock.instrInVPTBlock()) { 881 CC = VPTBlock.getVPTPred(); 882 VPTBlock.advanceVPTState(); 883 } 884 885 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 886 MCInst::iterator I = MI.begin(); 887 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 888 for (unsigned i = 0; i < NumOps; ++i, ++I) { 889 if (OpInfo[i].isPredicate() ) { 890 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 891 Check(S, SoftFail); 892 I->setImm(CC); 893 ++I; 894 if (CC == ARMCC::AL) 895 I->setReg(0); 896 else 897 I->setReg(ARM::CPSR); 898 return; 899 } 900 } 901 } 902 903 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 904 ArrayRef<uint8_t> Bytes, 905 uint64_t Address, 906 raw_ostream &CS) const { 907 CommentStream = &CS; 908 909 assert(STI.getFeatureBits()[ARM::ModeThumb] && 910 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 911 912 // We want to read exactly 2 bytes of data. 913 if (Bytes.size() < 2) { 914 Size = 0; 915 return MCDisassembler::Fail; 916 } 917 918 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 919 DecodeStatus Result = 920 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 921 if (Result != MCDisassembler::Fail) { 922 Size = 2; 923 Check(Result, AddThumbPredicate(MI)); 924 return Result; 925 } 926 927 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 928 STI); 929 if (Result) { 930 Size = 2; 931 bool InITBlock = ITBlock.instrInITBlock(); 932 Check(Result, AddThumbPredicate(MI)); 933 AddThumb1SBit(MI, InITBlock); 934 return Result; 935 } 936 937 Result = 938 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 939 if (Result != MCDisassembler::Fail) { 940 Size = 2; 941 942 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 943 // the Thumb predicate. 944 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 945 Result = MCDisassembler::SoftFail; 946 947 Check(Result, AddThumbPredicate(MI)); 948 949 // If we find an IT instruction, we need to parse its condition 950 // code and mask operands so that we can apply them correctly 951 // to the subsequent instructions. 952 if (MI.getOpcode() == ARM::t2IT) { 953 unsigned Firstcond = MI.getOperand(0).getImm(); 954 unsigned Mask = MI.getOperand(1).getImm(); 955 ITBlock.setITState(Firstcond, Mask); 956 957 // An IT instruction that would give a 'NV' predicate is unpredictable. 958 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 959 CS << "unpredictable IT predicate sequence"; 960 } 961 962 return Result; 963 } 964 965 // We want to read exactly 4 bytes of data. 966 if (Bytes.size() < 4) { 967 Size = 0; 968 return MCDisassembler::Fail; 969 } 970 971 uint32_t Insn32 = 972 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 973 974 Result = 975 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 976 if (Result != MCDisassembler::Fail) { 977 Size = 4; 978 979 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 980 // the VPT predicate. 981 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 982 Result = MCDisassembler::SoftFail; 983 984 Check(Result, AddThumbPredicate(MI)); 985 986 if (isVPTOpcode(MI.getOpcode())) { 987 unsigned Mask = MI.getOperand(0).getImm(); 988 VPTBlock.setVPTState(Mask); 989 } 990 991 return Result; 992 } 993 994 Result = 995 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 996 if (Result != MCDisassembler::Fail) { 997 Size = 4; 998 bool InITBlock = ITBlock.instrInITBlock(); 999 Check(Result, AddThumbPredicate(MI)); 1000 AddThumb1SBit(MI, InITBlock); 1001 return Result; 1002 } 1003 1004 Result = 1005 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1006 if (Result != MCDisassembler::Fail) { 1007 Size = 4; 1008 Check(Result, AddThumbPredicate(MI)); 1009 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1010 } 1011 1012 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1013 Result = 1014 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1015 if (Result != MCDisassembler::Fail) { 1016 Size = 4; 1017 UpdateThumbVFPPredicate(Result, MI); 1018 return Result; 1019 } 1020 } 1021 1022 Result = 1023 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1024 if (Result != MCDisassembler::Fail) { 1025 Size = 4; 1026 return Result; 1027 } 1028 1029 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1030 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1031 STI); 1032 if (Result != MCDisassembler::Fail) { 1033 Size = 4; 1034 Check(Result, AddThumbPredicate(MI)); 1035 return Result; 1036 } 1037 } 1038 1039 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1040 uint32_t NEONLdStInsn = Insn32; 1041 NEONLdStInsn &= 0xF0FFFFFF; 1042 NEONLdStInsn |= 0x04000000; 1043 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1044 Address, this, STI); 1045 if (Result != MCDisassembler::Fail) { 1046 Size = 4; 1047 Check(Result, AddThumbPredicate(MI)); 1048 return Result; 1049 } 1050 } 1051 1052 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1053 uint32_t NEONDataInsn = Insn32; 1054 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1055 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1056 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1057 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1058 Address, this, STI); 1059 if (Result != MCDisassembler::Fail) { 1060 Size = 4; 1061 Check(Result, AddThumbPredicate(MI)); 1062 return Result; 1063 } 1064 1065 uint32_t NEONCryptoInsn = Insn32; 1066 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1067 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1068 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1069 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1070 Address, this, STI); 1071 if (Result != MCDisassembler::Fail) { 1072 Size = 4; 1073 return Result; 1074 } 1075 1076 uint32_t NEONv8Insn = Insn32; 1077 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1078 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1079 this, STI); 1080 if (Result != MCDisassembler::Fail) { 1081 Size = 4; 1082 return Result; 1083 } 1084 } 1085 1086 Result = 1087 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1088 if (Result != MCDisassembler::Fail) { 1089 Size = 4; 1090 Check(Result, AddThumbPredicate(MI)); 1091 return Result; 1092 } 1093 1094 Size = 0; 1095 return MCDisassembler::Fail; 1096 } 1097 1098 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1099 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1100 createARMDisassembler); 1101 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1102 createARMDisassembler); 1103 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1104 createARMDisassembler); 1105 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1106 createARMDisassembler); 1107 } 1108 1109 static const uint16_t GPRDecoderTable[] = { 1110 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1111 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1112 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1113 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1114 }; 1115 1116 static const uint16_t CLRMGPRDecoderTable[] = { 1117 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1118 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1119 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1120 ARM::R12, 0, ARM::LR, ARM::APSR 1121 }; 1122 1123 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1124 uint64_t Address, const void *Decoder) { 1125 if (RegNo > 15) 1126 return MCDisassembler::Fail; 1127 1128 unsigned Register = GPRDecoderTable[RegNo]; 1129 Inst.addOperand(MCOperand::createReg(Register)); 1130 return MCDisassembler::Success; 1131 } 1132 1133 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1134 uint64_t Address, 1135 const void *Decoder) { 1136 if (RegNo > 15) 1137 return MCDisassembler::Fail; 1138 1139 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1140 if (Register == 0) 1141 return MCDisassembler::Fail; 1142 1143 Inst.addOperand(MCOperand::createReg(Register)); 1144 return MCDisassembler::Success; 1145 } 1146 1147 static DecodeStatus 1148 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1149 uint64_t Address, const void *Decoder) { 1150 DecodeStatus S = MCDisassembler::Success; 1151 1152 if (RegNo == 15) 1153 S = MCDisassembler::SoftFail; 1154 1155 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1156 1157 return S; 1158 } 1159 1160 static DecodeStatus 1161 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1162 uint64_t Address, const void *Decoder) { 1163 DecodeStatus S = MCDisassembler::Success; 1164 1165 if (RegNo == 15) 1166 { 1167 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1168 return MCDisassembler::Success; 1169 } 1170 1171 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1172 return S; 1173 } 1174 1175 static DecodeStatus 1176 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1177 uint64_t Address, const void *Decoder) { 1178 DecodeStatus S = MCDisassembler::Success; 1179 1180 if (RegNo == 15) 1181 { 1182 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1183 return MCDisassembler::Success; 1184 } 1185 1186 if (RegNo == 13) 1187 Check(S, MCDisassembler::SoftFail); 1188 1189 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1190 return S; 1191 } 1192 1193 static DecodeStatus 1194 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1195 uint64_t Address, const void *Decoder) { 1196 DecodeStatus S = MCDisassembler::Success; 1197 if (RegNo == 13) 1198 return MCDisassembler::Fail; 1199 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1200 return S; 1201 } 1202 1203 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1204 uint64_t Address, const void *Decoder) { 1205 if (RegNo > 7) 1206 return MCDisassembler::Fail; 1207 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1208 } 1209 1210 static const uint16_t GPRPairDecoderTable[] = { 1211 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1212 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1213 }; 1214 1215 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1216 uint64_t Address, const void *Decoder) { 1217 DecodeStatus S = MCDisassembler::Success; 1218 1219 if (RegNo > 13) 1220 return MCDisassembler::Fail; 1221 1222 if ((RegNo & 1) || RegNo == 0xe) 1223 S = MCDisassembler::SoftFail; 1224 1225 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1226 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1227 return S; 1228 } 1229 1230 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1231 uint64_t Address, 1232 const void *Decoder) { 1233 if (RegNo != 13) 1234 return MCDisassembler::Fail; 1235 1236 unsigned Register = GPRDecoderTable[RegNo]; 1237 Inst.addOperand(MCOperand::createReg(Register)); 1238 return MCDisassembler::Success; 1239 } 1240 1241 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1242 uint64_t Address, const void *Decoder) { 1243 unsigned Register = 0; 1244 switch (RegNo) { 1245 case 0: 1246 Register = ARM::R0; 1247 break; 1248 case 1: 1249 Register = ARM::R1; 1250 break; 1251 case 2: 1252 Register = ARM::R2; 1253 break; 1254 case 3: 1255 Register = ARM::R3; 1256 break; 1257 case 9: 1258 Register = ARM::R9; 1259 break; 1260 case 12: 1261 Register = ARM::R12; 1262 break; 1263 default: 1264 return MCDisassembler::Fail; 1265 } 1266 1267 Inst.addOperand(MCOperand::createReg(Register)); 1268 return MCDisassembler::Success; 1269 } 1270 1271 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1272 uint64_t Address, const void *Decoder) { 1273 DecodeStatus S = MCDisassembler::Success; 1274 1275 const FeatureBitset &featureBits = 1276 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1277 1278 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1279 S = MCDisassembler::SoftFail; 1280 1281 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1282 return S; 1283 } 1284 1285 static const uint16_t SPRDecoderTable[] = { 1286 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1287 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1288 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1289 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1290 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1291 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1292 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1293 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1294 }; 1295 1296 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1297 uint64_t Address, const void *Decoder) { 1298 if (RegNo > 31) 1299 return MCDisassembler::Fail; 1300 1301 unsigned Register = SPRDecoderTable[RegNo]; 1302 Inst.addOperand(MCOperand::createReg(Register)); 1303 return MCDisassembler::Success; 1304 } 1305 1306 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1307 uint64_t Address, const void *Decoder) { 1308 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1309 } 1310 1311 static const uint16_t DPRDecoderTable[] = { 1312 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1313 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1314 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1315 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1316 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1317 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1318 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1319 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1320 }; 1321 1322 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1323 uint64_t Address, const void *Decoder) { 1324 const FeatureBitset &featureBits = 1325 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1326 1327 bool hasD32 = featureBits[ARM::FeatureD32]; 1328 1329 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1330 return MCDisassembler::Fail; 1331 1332 unsigned Register = DPRDecoderTable[RegNo]; 1333 Inst.addOperand(MCOperand::createReg(Register)); 1334 return MCDisassembler::Success; 1335 } 1336 1337 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1338 uint64_t Address, const void *Decoder) { 1339 if (RegNo > 7) 1340 return MCDisassembler::Fail; 1341 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1342 } 1343 1344 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1345 uint64_t Address, const void *Decoder) { 1346 if (RegNo > 15) 1347 return MCDisassembler::Fail; 1348 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1349 } 1350 1351 static DecodeStatus 1352 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1353 uint64_t Address, const void *Decoder) { 1354 if (RegNo > 15) 1355 return MCDisassembler::Fail; 1356 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1357 } 1358 1359 static const uint16_t QPRDecoderTable[] = { 1360 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1361 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1362 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1363 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1364 }; 1365 1366 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1367 uint64_t Address, const void *Decoder) { 1368 if (RegNo > 31 || (RegNo & 1) != 0) 1369 return MCDisassembler::Fail; 1370 RegNo >>= 1; 1371 1372 unsigned Register = QPRDecoderTable[RegNo]; 1373 Inst.addOperand(MCOperand::createReg(Register)); 1374 return MCDisassembler::Success; 1375 } 1376 1377 static const uint16_t DPairDecoderTable[] = { 1378 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1379 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1380 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1381 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1382 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1383 ARM::Q15 1384 }; 1385 1386 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1387 uint64_t Address, const void *Decoder) { 1388 if (RegNo > 30) 1389 return MCDisassembler::Fail; 1390 1391 unsigned Register = DPairDecoderTable[RegNo]; 1392 Inst.addOperand(MCOperand::createReg(Register)); 1393 return MCDisassembler::Success; 1394 } 1395 1396 static const uint16_t DPairSpacedDecoderTable[] = { 1397 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1398 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1399 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1400 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1401 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1402 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1403 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1404 ARM::D28_D30, ARM::D29_D31 1405 }; 1406 1407 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1408 unsigned RegNo, 1409 uint64_t Address, 1410 const void *Decoder) { 1411 if (RegNo > 29) 1412 return MCDisassembler::Fail; 1413 1414 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1415 Inst.addOperand(MCOperand::createReg(Register)); 1416 return MCDisassembler::Success; 1417 } 1418 1419 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1420 uint64_t Address, const void *Decoder) { 1421 DecodeStatus S = MCDisassembler::Success; 1422 if (Val == 0xF) return MCDisassembler::Fail; 1423 // AL predicate is not allowed on Thumb1 branches. 1424 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1425 return MCDisassembler::Fail; 1426 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1427 Check(S, MCDisassembler::SoftFail); 1428 Inst.addOperand(MCOperand::createImm(Val)); 1429 if (Val == ARMCC::AL) { 1430 Inst.addOperand(MCOperand::createReg(0)); 1431 } else 1432 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1433 return S; 1434 } 1435 1436 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1437 uint64_t Address, const void *Decoder) { 1438 if (Val) 1439 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1440 else 1441 Inst.addOperand(MCOperand::createReg(0)); 1442 return MCDisassembler::Success; 1443 } 1444 1445 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1446 uint64_t Address, const void *Decoder) { 1447 DecodeStatus S = MCDisassembler::Success; 1448 1449 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1450 unsigned type = fieldFromInstruction(Val, 5, 2); 1451 unsigned imm = fieldFromInstruction(Val, 7, 5); 1452 1453 // Register-immediate 1454 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1455 return MCDisassembler::Fail; 1456 1457 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1458 switch (type) { 1459 case 0: 1460 Shift = ARM_AM::lsl; 1461 break; 1462 case 1: 1463 Shift = ARM_AM::lsr; 1464 break; 1465 case 2: 1466 Shift = ARM_AM::asr; 1467 break; 1468 case 3: 1469 Shift = ARM_AM::ror; 1470 break; 1471 } 1472 1473 if (Shift == ARM_AM::ror && imm == 0) 1474 Shift = ARM_AM::rrx; 1475 1476 unsigned Op = Shift | (imm << 3); 1477 Inst.addOperand(MCOperand::createImm(Op)); 1478 1479 return S; 1480 } 1481 1482 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1483 uint64_t Address, const void *Decoder) { 1484 DecodeStatus S = MCDisassembler::Success; 1485 1486 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1487 unsigned type = fieldFromInstruction(Val, 5, 2); 1488 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1489 1490 // Register-register 1491 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1492 return MCDisassembler::Fail; 1493 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1494 return MCDisassembler::Fail; 1495 1496 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1497 switch (type) { 1498 case 0: 1499 Shift = ARM_AM::lsl; 1500 break; 1501 case 1: 1502 Shift = ARM_AM::lsr; 1503 break; 1504 case 2: 1505 Shift = ARM_AM::asr; 1506 break; 1507 case 3: 1508 Shift = ARM_AM::ror; 1509 break; 1510 } 1511 1512 Inst.addOperand(MCOperand::createImm(Shift)); 1513 1514 return S; 1515 } 1516 1517 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1518 uint64_t Address, const void *Decoder) { 1519 DecodeStatus S = MCDisassembler::Success; 1520 1521 bool NeedDisjointWriteback = false; 1522 unsigned WritebackReg = 0; 1523 bool CLRM = false; 1524 switch (Inst.getOpcode()) { 1525 default: 1526 break; 1527 case ARM::LDMIA_UPD: 1528 case ARM::LDMDB_UPD: 1529 case ARM::LDMIB_UPD: 1530 case ARM::LDMDA_UPD: 1531 case ARM::t2LDMIA_UPD: 1532 case ARM::t2LDMDB_UPD: 1533 case ARM::t2STMIA_UPD: 1534 case ARM::t2STMDB_UPD: 1535 NeedDisjointWriteback = true; 1536 WritebackReg = Inst.getOperand(0).getReg(); 1537 break; 1538 case ARM::t2CLRM: 1539 CLRM = true; 1540 break; 1541 } 1542 1543 // Empty register lists are not allowed. 1544 if (Val == 0) return MCDisassembler::Fail; 1545 for (unsigned i = 0; i < 16; ++i) { 1546 if (Val & (1 << i)) { 1547 if (CLRM) { 1548 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1549 return MCDisassembler::Fail; 1550 } 1551 } else { 1552 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1553 return MCDisassembler::Fail; 1554 // Writeback not allowed if Rn is in the target list. 1555 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1556 Check(S, MCDisassembler::SoftFail); 1557 } 1558 } 1559 } 1560 1561 return S; 1562 } 1563 1564 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1565 uint64_t Address, const void *Decoder) { 1566 DecodeStatus S = MCDisassembler::Success; 1567 1568 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1569 unsigned regs = fieldFromInstruction(Val, 0, 8); 1570 1571 // In case of unpredictable encoding, tweak the operands. 1572 if (regs == 0 || (Vd + regs) > 32) { 1573 regs = Vd + regs > 32 ? 32 - Vd : regs; 1574 regs = std::max( 1u, regs); 1575 S = MCDisassembler::SoftFail; 1576 } 1577 1578 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1579 return MCDisassembler::Fail; 1580 for (unsigned i = 0; i < (regs - 1); ++i) { 1581 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1582 return MCDisassembler::Fail; 1583 } 1584 1585 return S; 1586 } 1587 1588 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1589 uint64_t Address, const void *Decoder) { 1590 DecodeStatus S = MCDisassembler::Success; 1591 1592 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1593 unsigned regs = fieldFromInstruction(Val, 1, 7); 1594 1595 // In case of unpredictable encoding, tweak the operands. 1596 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1597 regs = Vd + regs > 32 ? 32 - Vd : regs; 1598 regs = std::max( 1u, regs); 1599 regs = std::min(16u, regs); 1600 S = MCDisassembler::SoftFail; 1601 } 1602 1603 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1604 return MCDisassembler::Fail; 1605 for (unsigned i = 0; i < (regs - 1); ++i) { 1606 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1607 return MCDisassembler::Fail; 1608 } 1609 1610 return S; 1611 } 1612 1613 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1614 uint64_t Address, const void *Decoder) { 1615 // This operand encodes a mask of contiguous zeros between a specified MSB 1616 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1617 // the mask of all bits LSB-and-lower, and then xor them to create 1618 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1619 // create the final mask. 1620 unsigned msb = fieldFromInstruction(Val, 5, 5); 1621 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1622 1623 DecodeStatus S = MCDisassembler::Success; 1624 if (lsb > msb) { 1625 Check(S, MCDisassembler::SoftFail); 1626 // The check above will cause the warning for the "potentially undefined 1627 // instruction encoding" but we can't build a bad MCOperand value here 1628 // with a lsb > msb or else printing the MCInst will cause a crash. 1629 lsb = msb; 1630 } 1631 1632 uint32_t msb_mask = 0xFFFFFFFF; 1633 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1634 uint32_t lsb_mask = (1U << lsb) - 1; 1635 1636 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1637 return S; 1638 } 1639 1640 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1641 uint64_t Address, const void *Decoder) { 1642 DecodeStatus S = MCDisassembler::Success; 1643 1644 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1645 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1646 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1647 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1648 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1649 unsigned U = fieldFromInstruction(Insn, 23, 1); 1650 const FeatureBitset &featureBits = 1651 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1652 1653 switch (Inst.getOpcode()) { 1654 case ARM::LDC_OFFSET: 1655 case ARM::LDC_PRE: 1656 case ARM::LDC_POST: 1657 case ARM::LDC_OPTION: 1658 case ARM::LDCL_OFFSET: 1659 case ARM::LDCL_PRE: 1660 case ARM::LDCL_POST: 1661 case ARM::LDCL_OPTION: 1662 case ARM::STC_OFFSET: 1663 case ARM::STC_PRE: 1664 case ARM::STC_POST: 1665 case ARM::STC_OPTION: 1666 case ARM::STCL_OFFSET: 1667 case ARM::STCL_PRE: 1668 case ARM::STCL_POST: 1669 case ARM::STCL_OPTION: 1670 case ARM::t2LDC_OFFSET: 1671 case ARM::t2LDC_PRE: 1672 case ARM::t2LDC_POST: 1673 case ARM::t2LDC_OPTION: 1674 case ARM::t2LDCL_OFFSET: 1675 case ARM::t2LDCL_PRE: 1676 case ARM::t2LDCL_POST: 1677 case ARM::t2LDCL_OPTION: 1678 case ARM::t2STC_OFFSET: 1679 case ARM::t2STC_PRE: 1680 case ARM::t2STC_POST: 1681 case ARM::t2STC_OPTION: 1682 case ARM::t2STCL_OFFSET: 1683 case ARM::t2STCL_PRE: 1684 case ARM::t2STCL_POST: 1685 case ARM::t2STCL_OPTION: 1686 case ARM::t2LDC2_OFFSET: 1687 case ARM::t2LDC2L_OFFSET: 1688 case ARM::t2LDC2_PRE: 1689 case ARM::t2LDC2L_PRE: 1690 case ARM::t2STC2_OFFSET: 1691 case ARM::t2STC2L_OFFSET: 1692 case ARM::t2STC2_PRE: 1693 case ARM::t2STC2L_PRE: 1694 case ARM::LDC2_OFFSET: 1695 case ARM::LDC2L_OFFSET: 1696 case ARM::LDC2_PRE: 1697 case ARM::LDC2L_PRE: 1698 case ARM::STC2_OFFSET: 1699 case ARM::STC2L_OFFSET: 1700 case ARM::STC2_PRE: 1701 case ARM::STC2L_PRE: 1702 case ARM::t2LDC2_OPTION: 1703 case ARM::t2STC2_OPTION: 1704 case ARM::t2LDC2_POST: 1705 case ARM::t2LDC2L_POST: 1706 case ARM::t2STC2_POST: 1707 case ARM::t2STC2L_POST: 1708 case ARM::LDC2_POST: 1709 case ARM::LDC2L_POST: 1710 case ARM::STC2_POST: 1711 case ARM::STC2L_POST: 1712 if (coproc == 0xA || coproc == 0xB || 1713 (featureBits[ARM::HasV8_1MMainlineOps] && 1714 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1715 coproc == 0xE || coproc == 0xF))) 1716 return MCDisassembler::Fail; 1717 break; 1718 default: 1719 break; 1720 } 1721 1722 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1723 return MCDisassembler::Fail; 1724 1725 Inst.addOperand(MCOperand::createImm(coproc)); 1726 Inst.addOperand(MCOperand::createImm(CRd)); 1727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1728 return MCDisassembler::Fail; 1729 1730 switch (Inst.getOpcode()) { 1731 case ARM::t2LDC2_OFFSET: 1732 case ARM::t2LDC2L_OFFSET: 1733 case ARM::t2LDC2_PRE: 1734 case ARM::t2LDC2L_PRE: 1735 case ARM::t2STC2_OFFSET: 1736 case ARM::t2STC2L_OFFSET: 1737 case ARM::t2STC2_PRE: 1738 case ARM::t2STC2L_PRE: 1739 case ARM::LDC2_OFFSET: 1740 case ARM::LDC2L_OFFSET: 1741 case ARM::LDC2_PRE: 1742 case ARM::LDC2L_PRE: 1743 case ARM::STC2_OFFSET: 1744 case ARM::STC2L_OFFSET: 1745 case ARM::STC2_PRE: 1746 case ARM::STC2L_PRE: 1747 case ARM::t2LDC_OFFSET: 1748 case ARM::t2LDCL_OFFSET: 1749 case ARM::t2LDC_PRE: 1750 case ARM::t2LDCL_PRE: 1751 case ARM::t2STC_OFFSET: 1752 case ARM::t2STCL_OFFSET: 1753 case ARM::t2STC_PRE: 1754 case ARM::t2STCL_PRE: 1755 case ARM::LDC_OFFSET: 1756 case ARM::LDCL_OFFSET: 1757 case ARM::LDC_PRE: 1758 case ARM::LDCL_PRE: 1759 case ARM::STC_OFFSET: 1760 case ARM::STCL_OFFSET: 1761 case ARM::STC_PRE: 1762 case ARM::STCL_PRE: 1763 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1764 Inst.addOperand(MCOperand::createImm(imm)); 1765 break; 1766 case ARM::t2LDC2_POST: 1767 case ARM::t2LDC2L_POST: 1768 case ARM::t2STC2_POST: 1769 case ARM::t2STC2L_POST: 1770 case ARM::LDC2_POST: 1771 case ARM::LDC2L_POST: 1772 case ARM::STC2_POST: 1773 case ARM::STC2L_POST: 1774 case ARM::t2LDC_POST: 1775 case ARM::t2LDCL_POST: 1776 case ARM::t2STC_POST: 1777 case ARM::t2STCL_POST: 1778 case ARM::LDC_POST: 1779 case ARM::LDCL_POST: 1780 case ARM::STC_POST: 1781 case ARM::STCL_POST: 1782 imm |= U << 8; 1783 LLVM_FALLTHROUGH; 1784 default: 1785 // The 'option' variant doesn't encode 'U' in the immediate since 1786 // the immediate is unsigned [0,255]. 1787 Inst.addOperand(MCOperand::createImm(imm)); 1788 break; 1789 } 1790 1791 switch (Inst.getOpcode()) { 1792 case ARM::LDC_OFFSET: 1793 case ARM::LDC_PRE: 1794 case ARM::LDC_POST: 1795 case ARM::LDC_OPTION: 1796 case ARM::LDCL_OFFSET: 1797 case ARM::LDCL_PRE: 1798 case ARM::LDCL_POST: 1799 case ARM::LDCL_OPTION: 1800 case ARM::STC_OFFSET: 1801 case ARM::STC_PRE: 1802 case ARM::STC_POST: 1803 case ARM::STC_OPTION: 1804 case ARM::STCL_OFFSET: 1805 case ARM::STCL_PRE: 1806 case ARM::STCL_POST: 1807 case ARM::STCL_OPTION: 1808 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1809 return MCDisassembler::Fail; 1810 break; 1811 default: 1812 break; 1813 } 1814 1815 return S; 1816 } 1817 1818 static DecodeStatus 1819 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1820 uint64_t Address, const void *Decoder) { 1821 DecodeStatus S = MCDisassembler::Success; 1822 1823 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1824 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1825 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1826 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1827 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1828 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1829 unsigned P = fieldFromInstruction(Insn, 24, 1); 1830 unsigned W = fieldFromInstruction(Insn, 21, 1); 1831 1832 // On stores, the writeback operand precedes Rt. 1833 switch (Inst.getOpcode()) { 1834 case ARM::STR_POST_IMM: 1835 case ARM::STR_POST_REG: 1836 case ARM::STRB_POST_IMM: 1837 case ARM::STRB_POST_REG: 1838 case ARM::STRT_POST_REG: 1839 case ARM::STRT_POST_IMM: 1840 case ARM::STRBT_POST_REG: 1841 case ARM::STRBT_POST_IMM: 1842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1843 return MCDisassembler::Fail; 1844 break; 1845 default: 1846 break; 1847 } 1848 1849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1850 return MCDisassembler::Fail; 1851 1852 // On loads, the writeback operand comes after Rt. 1853 switch (Inst.getOpcode()) { 1854 case ARM::LDR_POST_IMM: 1855 case ARM::LDR_POST_REG: 1856 case ARM::LDRB_POST_IMM: 1857 case ARM::LDRB_POST_REG: 1858 case ARM::LDRBT_POST_REG: 1859 case ARM::LDRBT_POST_IMM: 1860 case ARM::LDRT_POST_REG: 1861 case ARM::LDRT_POST_IMM: 1862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1863 return MCDisassembler::Fail; 1864 break; 1865 default: 1866 break; 1867 } 1868 1869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1870 return MCDisassembler::Fail; 1871 1872 ARM_AM::AddrOpc Op = ARM_AM::add; 1873 if (!fieldFromInstruction(Insn, 23, 1)) 1874 Op = ARM_AM::sub; 1875 1876 bool writeback = (P == 0) || (W == 1); 1877 unsigned idx_mode = 0; 1878 if (P && writeback) 1879 idx_mode = ARMII::IndexModePre; 1880 else if (!P && writeback) 1881 idx_mode = ARMII::IndexModePost; 1882 1883 if (writeback && (Rn == 15 || Rn == Rt)) 1884 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1885 1886 if (reg) { 1887 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1888 return MCDisassembler::Fail; 1889 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1890 switch( fieldFromInstruction(Insn, 5, 2)) { 1891 case 0: 1892 Opc = ARM_AM::lsl; 1893 break; 1894 case 1: 1895 Opc = ARM_AM::lsr; 1896 break; 1897 case 2: 1898 Opc = ARM_AM::asr; 1899 break; 1900 case 3: 1901 Opc = ARM_AM::ror; 1902 break; 1903 default: 1904 return MCDisassembler::Fail; 1905 } 1906 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1907 if (Opc == ARM_AM::ror && amt == 0) 1908 Opc = ARM_AM::rrx; 1909 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1910 1911 Inst.addOperand(MCOperand::createImm(imm)); 1912 } else { 1913 Inst.addOperand(MCOperand::createReg(0)); 1914 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1915 Inst.addOperand(MCOperand::createImm(tmp)); 1916 } 1917 1918 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1919 return MCDisassembler::Fail; 1920 1921 return S; 1922 } 1923 1924 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1925 uint64_t Address, const void *Decoder) { 1926 DecodeStatus S = MCDisassembler::Success; 1927 1928 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1929 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1930 unsigned type = fieldFromInstruction(Val, 5, 2); 1931 unsigned imm = fieldFromInstruction(Val, 7, 5); 1932 unsigned U = fieldFromInstruction(Val, 12, 1); 1933 1934 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1935 switch (type) { 1936 case 0: 1937 ShOp = ARM_AM::lsl; 1938 break; 1939 case 1: 1940 ShOp = ARM_AM::lsr; 1941 break; 1942 case 2: 1943 ShOp = ARM_AM::asr; 1944 break; 1945 case 3: 1946 ShOp = ARM_AM::ror; 1947 break; 1948 } 1949 1950 if (ShOp == ARM_AM::ror && imm == 0) 1951 ShOp = ARM_AM::rrx; 1952 1953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1954 return MCDisassembler::Fail; 1955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1956 return MCDisassembler::Fail; 1957 unsigned shift; 1958 if (U) 1959 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1960 else 1961 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1962 Inst.addOperand(MCOperand::createImm(shift)); 1963 1964 return S; 1965 } 1966 1967 static DecodeStatus 1968 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1969 uint64_t Address, const void *Decoder) { 1970 DecodeStatus S = MCDisassembler::Success; 1971 1972 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1973 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1974 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1975 unsigned type = fieldFromInstruction(Insn, 22, 1); 1976 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1977 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1978 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1979 unsigned W = fieldFromInstruction(Insn, 21, 1); 1980 unsigned P = fieldFromInstruction(Insn, 24, 1); 1981 unsigned Rt2 = Rt + 1; 1982 1983 bool writeback = (W == 1) | (P == 0); 1984 1985 // For {LD,ST}RD, Rt must be even, else undefined. 1986 switch (Inst.getOpcode()) { 1987 case ARM::STRD: 1988 case ARM::STRD_PRE: 1989 case ARM::STRD_POST: 1990 case ARM::LDRD: 1991 case ARM::LDRD_PRE: 1992 case ARM::LDRD_POST: 1993 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1994 break; 1995 default: 1996 break; 1997 } 1998 switch (Inst.getOpcode()) { 1999 case ARM::STRD: 2000 case ARM::STRD_PRE: 2001 case ARM::STRD_POST: 2002 if (P == 0 && W == 1) 2003 S = MCDisassembler::SoftFail; 2004 2005 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2006 S = MCDisassembler::SoftFail; 2007 if (type && Rm == 15) 2008 S = MCDisassembler::SoftFail; 2009 if (Rt2 == 15) 2010 S = MCDisassembler::SoftFail; 2011 if (!type && fieldFromInstruction(Insn, 8, 4)) 2012 S = MCDisassembler::SoftFail; 2013 break; 2014 case ARM::STRH: 2015 case ARM::STRH_PRE: 2016 case ARM::STRH_POST: 2017 if (Rt == 15) 2018 S = MCDisassembler::SoftFail; 2019 if (writeback && (Rn == 15 || Rn == Rt)) 2020 S = MCDisassembler::SoftFail; 2021 if (!type && Rm == 15) 2022 S = MCDisassembler::SoftFail; 2023 break; 2024 case ARM::LDRD: 2025 case ARM::LDRD_PRE: 2026 case ARM::LDRD_POST: 2027 if (type && Rn == 15) { 2028 if (Rt2 == 15) 2029 S = MCDisassembler::SoftFail; 2030 break; 2031 } 2032 if (P == 0 && W == 1) 2033 S = MCDisassembler::SoftFail; 2034 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2035 S = MCDisassembler::SoftFail; 2036 if (!type && writeback && Rn == 15) 2037 S = MCDisassembler::SoftFail; 2038 if (writeback && (Rn == Rt || Rn == Rt2)) 2039 S = MCDisassembler::SoftFail; 2040 break; 2041 case ARM::LDRH: 2042 case ARM::LDRH_PRE: 2043 case ARM::LDRH_POST: 2044 if (type && Rn == 15) { 2045 if (Rt == 15) 2046 S = MCDisassembler::SoftFail; 2047 break; 2048 } 2049 if (Rt == 15) 2050 S = MCDisassembler::SoftFail; 2051 if (!type && Rm == 15) 2052 S = MCDisassembler::SoftFail; 2053 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2054 S = MCDisassembler::SoftFail; 2055 break; 2056 case ARM::LDRSH: 2057 case ARM::LDRSH_PRE: 2058 case ARM::LDRSH_POST: 2059 case ARM::LDRSB: 2060 case ARM::LDRSB_PRE: 2061 case ARM::LDRSB_POST: 2062 if (type && Rn == 15) { 2063 if (Rt == 15) 2064 S = MCDisassembler::SoftFail; 2065 break; 2066 } 2067 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2068 S = MCDisassembler::SoftFail; 2069 if (!type && (Rt == 15 || Rm == 15)) 2070 S = MCDisassembler::SoftFail; 2071 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2072 S = MCDisassembler::SoftFail; 2073 break; 2074 default: 2075 break; 2076 } 2077 2078 if (writeback) { // Writeback 2079 if (P) 2080 U |= ARMII::IndexModePre << 9; 2081 else 2082 U |= ARMII::IndexModePost << 9; 2083 2084 // On stores, the writeback operand precedes Rt. 2085 switch (Inst.getOpcode()) { 2086 case ARM::STRD: 2087 case ARM::STRD_PRE: 2088 case ARM::STRD_POST: 2089 case ARM::STRH: 2090 case ARM::STRH_PRE: 2091 case ARM::STRH_POST: 2092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2093 return MCDisassembler::Fail; 2094 break; 2095 default: 2096 break; 2097 } 2098 } 2099 2100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2101 return MCDisassembler::Fail; 2102 switch (Inst.getOpcode()) { 2103 case ARM::STRD: 2104 case ARM::STRD_PRE: 2105 case ARM::STRD_POST: 2106 case ARM::LDRD: 2107 case ARM::LDRD_PRE: 2108 case ARM::LDRD_POST: 2109 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 break; 2112 default: 2113 break; 2114 } 2115 2116 if (writeback) { 2117 // On loads, the writeback operand comes after Rt. 2118 switch (Inst.getOpcode()) { 2119 case ARM::LDRD: 2120 case ARM::LDRD_PRE: 2121 case ARM::LDRD_POST: 2122 case ARM::LDRH: 2123 case ARM::LDRH_PRE: 2124 case ARM::LDRH_POST: 2125 case ARM::LDRSH: 2126 case ARM::LDRSH_PRE: 2127 case ARM::LDRSH_POST: 2128 case ARM::LDRSB: 2129 case ARM::LDRSB_PRE: 2130 case ARM::LDRSB_POST: 2131 case ARM::LDRHTr: 2132 case ARM::LDRSBTr: 2133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2134 return MCDisassembler::Fail; 2135 break; 2136 default: 2137 break; 2138 } 2139 } 2140 2141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2142 return MCDisassembler::Fail; 2143 2144 if (type) { 2145 Inst.addOperand(MCOperand::createReg(0)); 2146 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2147 } else { 2148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2149 return MCDisassembler::Fail; 2150 Inst.addOperand(MCOperand::createImm(U)); 2151 } 2152 2153 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2154 return MCDisassembler::Fail; 2155 2156 return S; 2157 } 2158 2159 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2160 uint64_t Address, const void *Decoder) { 2161 DecodeStatus S = MCDisassembler::Success; 2162 2163 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2164 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2165 2166 switch (mode) { 2167 case 0: 2168 mode = ARM_AM::da; 2169 break; 2170 case 1: 2171 mode = ARM_AM::ia; 2172 break; 2173 case 2: 2174 mode = ARM_AM::db; 2175 break; 2176 case 3: 2177 mode = ARM_AM::ib; 2178 break; 2179 } 2180 2181 Inst.addOperand(MCOperand::createImm(mode)); 2182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2183 return MCDisassembler::Fail; 2184 2185 return S; 2186 } 2187 2188 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2189 uint64_t Address, const void *Decoder) { 2190 DecodeStatus S = MCDisassembler::Success; 2191 2192 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2193 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2194 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2195 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2196 2197 if (pred == 0xF) 2198 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2199 2200 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2201 return MCDisassembler::Fail; 2202 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2203 return MCDisassembler::Fail; 2204 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2205 return MCDisassembler::Fail; 2206 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2207 return MCDisassembler::Fail; 2208 return S; 2209 } 2210 2211 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2212 unsigned Insn, 2213 uint64_t Address, const void *Decoder) { 2214 DecodeStatus S = MCDisassembler::Success; 2215 2216 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2217 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2218 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2219 2220 if (pred == 0xF) { 2221 // Ambiguous with RFE and SRS 2222 switch (Inst.getOpcode()) { 2223 case ARM::LDMDA: 2224 Inst.setOpcode(ARM::RFEDA); 2225 break; 2226 case ARM::LDMDA_UPD: 2227 Inst.setOpcode(ARM::RFEDA_UPD); 2228 break; 2229 case ARM::LDMDB: 2230 Inst.setOpcode(ARM::RFEDB); 2231 break; 2232 case ARM::LDMDB_UPD: 2233 Inst.setOpcode(ARM::RFEDB_UPD); 2234 break; 2235 case ARM::LDMIA: 2236 Inst.setOpcode(ARM::RFEIA); 2237 break; 2238 case ARM::LDMIA_UPD: 2239 Inst.setOpcode(ARM::RFEIA_UPD); 2240 break; 2241 case ARM::LDMIB: 2242 Inst.setOpcode(ARM::RFEIB); 2243 break; 2244 case ARM::LDMIB_UPD: 2245 Inst.setOpcode(ARM::RFEIB_UPD); 2246 break; 2247 case ARM::STMDA: 2248 Inst.setOpcode(ARM::SRSDA); 2249 break; 2250 case ARM::STMDA_UPD: 2251 Inst.setOpcode(ARM::SRSDA_UPD); 2252 break; 2253 case ARM::STMDB: 2254 Inst.setOpcode(ARM::SRSDB); 2255 break; 2256 case ARM::STMDB_UPD: 2257 Inst.setOpcode(ARM::SRSDB_UPD); 2258 break; 2259 case ARM::STMIA: 2260 Inst.setOpcode(ARM::SRSIA); 2261 break; 2262 case ARM::STMIA_UPD: 2263 Inst.setOpcode(ARM::SRSIA_UPD); 2264 break; 2265 case ARM::STMIB: 2266 Inst.setOpcode(ARM::SRSIB); 2267 break; 2268 case ARM::STMIB_UPD: 2269 Inst.setOpcode(ARM::SRSIB_UPD); 2270 break; 2271 default: 2272 return MCDisassembler::Fail; 2273 } 2274 2275 // For stores (which become SRS's, the only operand is the mode. 2276 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2277 // Check SRS encoding constraints 2278 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2279 fieldFromInstruction(Insn, 20, 1) == 0)) 2280 return MCDisassembler::Fail; 2281 2282 Inst.addOperand( 2283 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2284 return S; 2285 } 2286 2287 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2288 } 2289 2290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2291 return MCDisassembler::Fail; 2292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2293 return MCDisassembler::Fail; // Tied 2294 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2295 return MCDisassembler::Fail; 2296 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2297 return MCDisassembler::Fail; 2298 2299 return S; 2300 } 2301 2302 // Check for UNPREDICTABLE predicated ESB instruction 2303 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2304 uint64_t Address, const void *Decoder) { 2305 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2306 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2307 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2308 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2309 2310 DecodeStatus S = MCDisassembler::Success; 2311 2312 Inst.addOperand(MCOperand::createImm(imm8)); 2313 2314 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2315 return MCDisassembler::Fail; 2316 2317 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2318 // so all predicates should be allowed. 2319 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2320 S = MCDisassembler::SoftFail; 2321 2322 return S; 2323 } 2324 2325 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2326 uint64_t Address, const void *Decoder) { 2327 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2328 unsigned M = fieldFromInstruction(Insn, 17, 1); 2329 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2330 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2331 2332 DecodeStatus S = MCDisassembler::Success; 2333 2334 // This decoder is called from multiple location that do not check 2335 // the full encoding is valid before they do. 2336 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2337 fieldFromInstruction(Insn, 16, 1) != 0 || 2338 fieldFromInstruction(Insn, 20, 8) != 0x10) 2339 return MCDisassembler::Fail; 2340 2341 // imod == '01' --> UNPREDICTABLE 2342 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2343 // return failure here. The '01' imod value is unprintable, so there's 2344 // nothing useful we could do even if we returned UNPREDICTABLE. 2345 2346 if (imod == 1) return MCDisassembler::Fail; 2347 2348 if (imod && M) { 2349 Inst.setOpcode(ARM::CPS3p); 2350 Inst.addOperand(MCOperand::createImm(imod)); 2351 Inst.addOperand(MCOperand::createImm(iflags)); 2352 Inst.addOperand(MCOperand::createImm(mode)); 2353 } else if (imod && !M) { 2354 Inst.setOpcode(ARM::CPS2p); 2355 Inst.addOperand(MCOperand::createImm(imod)); 2356 Inst.addOperand(MCOperand::createImm(iflags)); 2357 if (mode) S = MCDisassembler::SoftFail; 2358 } else if (!imod && M) { 2359 Inst.setOpcode(ARM::CPS1p); 2360 Inst.addOperand(MCOperand::createImm(mode)); 2361 if (iflags) S = MCDisassembler::SoftFail; 2362 } else { 2363 // imod == '00' && M == '0' --> UNPREDICTABLE 2364 Inst.setOpcode(ARM::CPS1p); 2365 Inst.addOperand(MCOperand::createImm(mode)); 2366 S = MCDisassembler::SoftFail; 2367 } 2368 2369 return S; 2370 } 2371 2372 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2373 uint64_t Address, const void *Decoder) { 2374 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2375 unsigned M = fieldFromInstruction(Insn, 8, 1); 2376 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2377 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2378 2379 DecodeStatus S = MCDisassembler::Success; 2380 2381 // imod == '01' --> UNPREDICTABLE 2382 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2383 // return failure here. The '01' imod value is unprintable, so there's 2384 // nothing useful we could do even if we returned UNPREDICTABLE. 2385 2386 if (imod == 1) return MCDisassembler::Fail; 2387 2388 if (imod && M) { 2389 Inst.setOpcode(ARM::t2CPS3p); 2390 Inst.addOperand(MCOperand::createImm(imod)); 2391 Inst.addOperand(MCOperand::createImm(iflags)); 2392 Inst.addOperand(MCOperand::createImm(mode)); 2393 } else if (imod && !M) { 2394 Inst.setOpcode(ARM::t2CPS2p); 2395 Inst.addOperand(MCOperand::createImm(imod)); 2396 Inst.addOperand(MCOperand::createImm(iflags)); 2397 if (mode) S = MCDisassembler::SoftFail; 2398 } else if (!imod && M) { 2399 Inst.setOpcode(ARM::t2CPS1p); 2400 Inst.addOperand(MCOperand::createImm(mode)); 2401 if (iflags) S = MCDisassembler::SoftFail; 2402 } else { 2403 // imod == '00' && M == '0' --> this is a HINT instruction 2404 int imm = fieldFromInstruction(Insn, 0, 8); 2405 // HINT are defined only for immediate in [0..4] 2406 if(imm > 4) return MCDisassembler::Fail; 2407 Inst.setOpcode(ARM::t2HINT); 2408 Inst.addOperand(MCOperand::createImm(imm)); 2409 } 2410 2411 return S; 2412 } 2413 2414 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2415 uint64_t Address, const void *Decoder) { 2416 DecodeStatus S = MCDisassembler::Success; 2417 2418 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2419 unsigned imm = 0; 2420 2421 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2422 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2423 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2424 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2425 2426 if (Inst.getOpcode() == ARM::t2MOVTi16) 2427 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2430 return MCDisassembler::Fail; 2431 2432 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2433 Inst.addOperand(MCOperand::createImm(imm)); 2434 2435 return S; 2436 } 2437 2438 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2439 uint64_t Address, const void *Decoder) { 2440 DecodeStatus S = MCDisassembler::Success; 2441 2442 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2443 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2444 unsigned imm = 0; 2445 2446 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2447 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2448 2449 if (Inst.getOpcode() == ARM::MOVTi16) 2450 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2451 return MCDisassembler::Fail; 2452 2453 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2454 return MCDisassembler::Fail; 2455 2456 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2457 Inst.addOperand(MCOperand::createImm(imm)); 2458 2459 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2460 return MCDisassembler::Fail; 2461 2462 return S; 2463 } 2464 2465 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2466 uint64_t Address, const void *Decoder) { 2467 DecodeStatus S = MCDisassembler::Success; 2468 2469 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2470 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2471 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2472 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2473 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2474 2475 if (pred == 0xF) 2476 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2477 2478 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2479 return MCDisassembler::Fail; 2480 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2481 return MCDisassembler::Fail; 2482 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2483 return MCDisassembler::Fail; 2484 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2485 return MCDisassembler::Fail; 2486 2487 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2488 return MCDisassembler::Fail; 2489 2490 return S; 2491 } 2492 2493 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2494 uint64_t Address, const void *Decoder) { 2495 DecodeStatus S = MCDisassembler::Success; 2496 2497 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2498 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2499 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2500 2501 if (Pred == 0xF) 2502 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2503 2504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2505 return MCDisassembler::Fail; 2506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2507 return MCDisassembler::Fail; 2508 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2509 return MCDisassembler::Fail; 2510 2511 return S; 2512 } 2513 2514 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2515 uint64_t Address, const void *Decoder) { 2516 DecodeStatus S = MCDisassembler::Success; 2517 2518 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2519 2520 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2521 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2522 2523 if (!FeatureBits[ARM::HasV8_1aOps] || 2524 !FeatureBits[ARM::HasV8Ops]) 2525 return MCDisassembler::Fail; 2526 2527 // Decoder can be called from DecodeTST, which does not check the full 2528 // encoding is valid. 2529 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2530 fieldFromInstruction(Insn, 4,4) != 0) 2531 return MCDisassembler::Fail; 2532 if (fieldFromInstruction(Insn, 10,10) != 0 || 2533 fieldFromInstruction(Insn, 0,4) != 0) 2534 S = MCDisassembler::SoftFail; 2535 2536 Inst.setOpcode(ARM::SETPAN); 2537 Inst.addOperand(MCOperand::createImm(Imm)); 2538 2539 return S; 2540 } 2541 2542 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2543 uint64_t Address, const void *Decoder) { 2544 DecodeStatus S = MCDisassembler::Success; 2545 2546 unsigned add = fieldFromInstruction(Val, 12, 1); 2547 unsigned imm = fieldFromInstruction(Val, 0, 12); 2548 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2549 2550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2551 return MCDisassembler::Fail; 2552 2553 if (!add) imm *= -1; 2554 if (imm == 0 && !add) imm = INT32_MIN; 2555 Inst.addOperand(MCOperand::createImm(imm)); 2556 if (Rn == 15) 2557 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2558 2559 return S; 2560 } 2561 2562 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2563 uint64_t Address, const void *Decoder) { 2564 DecodeStatus S = MCDisassembler::Success; 2565 2566 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2567 // U == 1 to add imm, 0 to subtract it. 2568 unsigned U = fieldFromInstruction(Val, 8, 1); 2569 unsigned imm = fieldFromInstruction(Val, 0, 8); 2570 2571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2572 return MCDisassembler::Fail; 2573 2574 if (U) 2575 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2576 else 2577 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2578 2579 return S; 2580 } 2581 2582 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2583 uint64_t Address, const void *Decoder) { 2584 DecodeStatus S = MCDisassembler::Success; 2585 2586 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2587 // U == 1 to add imm, 0 to subtract it. 2588 unsigned U = fieldFromInstruction(Val, 8, 1); 2589 unsigned imm = fieldFromInstruction(Val, 0, 8); 2590 2591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2592 return MCDisassembler::Fail; 2593 2594 if (U) 2595 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2596 else 2597 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2598 2599 return S; 2600 } 2601 2602 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2603 uint64_t Address, const void *Decoder) { 2604 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2605 } 2606 2607 static DecodeStatus 2608 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2609 uint64_t Address, const void *Decoder) { 2610 DecodeStatus Status = MCDisassembler::Success; 2611 2612 // Note the J1 and J2 values are from the encoded instruction. So here 2613 // change them to I1 and I2 values via as documented: 2614 // I1 = NOT(J1 EOR S); 2615 // I2 = NOT(J2 EOR S); 2616 // and build the imm32 with one trailing zero as documented: 2617 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2618 unsigned S = fieldFromInstruction(Insn, 26, 1); 2619 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2620 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2621 unsigned I1 = !(J1 ^ S); 2622 unsigned I2 = !(J2 ^ S); 2623 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2624 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2625 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2626 int imm32 = SignExtend32<25>(tmp << 1); 2627 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2628 true, 4, Inst, Decoder)) 2629 Inst.addOperand(MCOperand::createImm(imm32)); 2630 2631 return Status; 2632 } 2633 2634 static DecodeStatus 2635 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2636 uint64_t Address, const void *Decoder) { 2637 DecodeStatus S = MCDisassembler::Success; 2638 2639 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2640 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2641 2642 if (pred == 0xF) { 2643 Inst.setOpcode(ARM::BLXi); 2644 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2645 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2646 true, 4, Inst, Decoder)) 2647 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2648 return S; 2649 } 2650 2651 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2652 true, 4, Inst, Decoder)) 2653 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2654 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2655 return MCDisassembler::Fail; 2656 2657 return S; 2658 } 2659 2660 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2661 uint64_t Address, const void *Decoder) { 2662 DecodeStatus S = MCDisassembler::Success; 2663 2664 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2665 unsigned align = fieldFromInstruction(Val, 4, 2); 2666 2667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2668 return MCDisassembler::Fail; 2669 if (!align) 2670 Inst.addOperand(MCOperand::createImm(0)); 2671 else 2672 Inst.addOperand(MCOperand::createImm(4 << align)); 2673 2674 return S; 2675 } 2676 2677 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2678 uint64_t Address, const void *Decoder) { 2679 DecodeStatus S = MCDisassembler::Success; 2680 2681 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2682 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2683 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2684 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2685 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2686 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2687 2688 // First output register 2689 switch (Inst.getOpcode()) { 2690 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2691 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2692 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2693 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2694 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2695 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2696 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2697 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2698 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2699 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2700 return MCDisassembler::Fail; 2701 break; 2702 case ARM::VLD2b16: 2703 case ARM::VLD2b32: 2704 case ARM::VLD2b8: 2705 case ARM::VLD2b16wb_fixed: 2706 case ARM::VLD2b16wb_register: 2707 case ARM::VLD2b32wb_fixed: 2708 case ARM::VLD2b32wb_register: 2709 case ARM::VLD2b8wb_fixed: 2710 case ARM::VLD2b8wb_register: 2711 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2712 return MCDisassembler::Fail; 2713 break; 2714 default: 2715 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2716 return MCDisassembler::Fail; 2717 } 2718 2719 // Second output register 2720 switch (Inst.getOpcode()) { 2721 case ARM::VLD3d8: 2722 case ARM::VLD3d16: 2723 case ARM::VLD3d32: 2724 case ARM::VLD3d8_UPD: 2725 case ARM::VLD3d16_UPD: 2726 case ARM::VLD3d32_UPD: 2727 case ARM::VLD4d8: 2728 case ARM::VLD4d16: 2729 case ARM::VLD4d32: 2730 case ARM::VLD4d8_UPD: 2731 case ARM::VLD4d16_UPD: 2732 case ARM::VLD4d32_UPD: 2733 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2734 return MCDisassembler::Fail; 2735 break; 2736 case ARM::VLD3q8: 2737 case ARM::VLD3q16: 2738 case ARM::VLD3q32: 2739 case ARM::VLD3q8_UPD: 2740 case ARM::VLD3q16_UPD: 2741 case ARM::VLD3q32_UPD: 2742 case ARM::VLD4q8: 2743 case ARM::VLD4q16: 2744 case ARM::VLD4q32: 2745 case ARM::VLD4q8_UPD: 2746 case ARM::VLD4q16_UPD: 2747 case ARM::VLD4q32_UPD: 2748 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 break; 2751 default: 2752 break; 2753 } 2754 2755 // Third output register 2756 switch(Inst.getOpcode()) { 2757 case ARM::VLD3d8: 2758 case ARM::VLD3d16: 2759 case ARM::VLD3d32: 2760 case ARM::VLD3d8_UPD: 2761 case ARM::VLD3d16_UPD: 2762 case ARM::VLD3d32_UPD: 2763 case ARM::VLD4d8: 2764 case ARM::VLD4d16: 2765 case ARM::VLD4d32: 2766 case ARM::VLD4d8_UPD: 2767 case ARM::VLD4d16_UPD: 2768 case ARM::VLD4d32_UPD: 2769 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2770 return MCDisassembler::Fail; 2771 break; 2772 case ARM::VLD3q8: 2773 case ARM::VLD3q16: 2774 case ARM::VLD3q32: 2775 case ARM::VLD3q8_UPD: 2776 case ARM::VLD3q16_UPD: 2777 case ARM::VLD3q32_UPD: 2778 case ARM::VLD4q8: 2779 case ARM::VLD4q16: 2780 case ARM::VLD4q32: 2781 case ARM::VLD4q8_UPD: 2782 case ARM::VLD4q16_UPD: 2783 case ARM::VLD4q32_UPD: 2784 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2785 return MCDisassembler::Fail; 2786 break; 2787 default: 2788 break; 2789 } 2790 2791 // Fourth output register 2792 switch (Inst.getOpcode()) { 2793 case ARM::VLD4d8: 2794 case ARM::VLD4d16: 2795 case ARM::VLD4d32: 2796 case ARM::VLD4d8_UPD: 2797 case ARM::VLD4d16_UPD: 2798 case ARM::VLD4d32_UPD: 2799 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 break; 2802 case ARM::VLD4q8: 2803 case ARM::VLD4q16: 2804 case ARM::VLD4q32: 2805 case ARM::VLD4q8_UPD: 2806 case ARM::VLD4q16_UPD: 2807 case ARM::VLD4q32_UPD: 2808 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2809 return MCDisassembler::Fail; 2810 break; 2811 default: 2812 break; 2813 } 2814 2815 // Writeback operand 2816 switch (Inst.getOpcode()) { 2817 case ARM::VLD1d8wb_fixed: 2818 case ARM::VLD1d16wb_fixed: 2819 case ARM::VLD1d32wb_fixed: 2820 case ARM::VLD1d64wb_fixed: 2821 case ARM::VLD1d8wb_register: 2822 case ARM::VLD1d16wb_register: 2823 case ARM::VLD1d32wb_register: 2824 case ARM::VLD1d64wb_register: 2825 case ARM::VLD1q8wb_fixed: 2826 case ARM::VLD1q16wb_fixed: 2827 case ARM::VLD1q32wb_fixed: 2828 case ARM::VLD1q64wb_fixed: 2829 case ARM::VLD1q8wb_register: 2830 case ARM::VLD1q16wb_register: 2831 case ARM::VLD1q32wb_register: 2832 case ARM::VLD1q64wb_register: 2833 case ARM::VLD1d8Twb_fixed: 2834 case ARM::VLD1d8Twb_register: 2835 case ARM::VLD1d16Twb_fixed: 2836 case ARM::VLD1d16Twb_register: 2837 case ARM::VLD1d32Twb_fixed: 2838 case ARM::VLD1d32Twb_register: 2839 case ARM::VLD1d64Twb_fixed: 2840 case ARM::VLD1d64Twb_register: 2841 case ARM::VLD1d8Qwb_fixed: 2842 case ARM::VLD1d8Qwb_register: 2843 case ARM::VLD1d16Qwb_fixed: 2844 case ARM::VLD1d16Qwb_register: 2845 case ARM::VLD1d32Qwb_fixed: 2846 case ARM::VLD1d32Qwb_register: 2847 case ARM::VLD1d64Qwb_fixed: 2848 case ARM::VLD1d64Qwb_register: 2849 case ARM::VLD2d8wb_fixed: 2850 case ARM::VLD2d16wb_fixed: 2851 case ARM::VLD2d32wb_fixed: 2852 case ARM::VLD2q8wb_fixed: 2853 case ARM::VLD2q16wb_fixed: 2854 case ARM::VLD2q32wb_fixed: 2855 case ARM::VLD2d8wb_register: 2856 case ARM::VLD2d16wb_register: 2857 case ARM::VLD2d32wb_register: 2858 case ARM::VLD2q8wb_register: 2859 case ARM::VLD2q16wb_register: 2860 case ARM::VLD2q32wb_register: 2861 case ARM::VLD2b8wb_fixed: 2862 case ARM::VLD2b16wb_fixed: 2863 case ARM::VLD2b32wb_fixed: 2864 case ARM::VLD2b8wb_register: 2865 case ARM::VLD2b16wb_register: 2866 case ARM::VLD2b32wb_register: 2867 Inst.addOperand(MCOperand::createImm(0)); 2868 break; 2869 case ARM::VLD3d8_UPD: 2870 case ARM::VLD3d16_UPD: 2871 case ARM::VLD3d32_UPD: 2872 case ARM::VLD3q8_UPD: 2873 case ARM::VLD3q16_UPD: 2874 case ARM::VLD3q32_UPD: 2875 case ARM::VLD4d8_UPD: 2876 case ARM::VLD4d16_UPD: 2877 case ARM::VLD4d32_UPD: 2878 case ARM::VLD4q8_UPD: 2879 case ARM::VLD4q16_UPD: 2880 case ARM::VLD4q32_UPD: 2881 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2882 return MCDisassembler::Fail; 2883 break; 2884 default: 2885 break; 2886 } 2887 2888 // AddrMode6 Base (register+alignment) 2889 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2890 return MCDisassembler::Fail; 2891 2892 // AddrMode6 Offset (register) 2893 switch (Inst.getOpcode()) { 2894 default: 2895 // The below have been updated to have explicit am6offset split 2896 // between fixed and register offset. For those instructions not 2897 // yet updated, we need to add an additional reg0 operand for the 2898 // fixed variant. 2899 // 2900 // The fixed offset encodes as Rm == 0xd, so we check for that. 2901 if (Rm == 0xd) { 2902 Inst.addOperand(MCOperand::createReg(0)); 2903 break; 2904 } 2905 // Fall through to handle the register offset variant. 2906 LLVM_FALLTHROUGH; 2907 case ARM::VLD1d8wb_fixed: 2908 case ARM::VLD1d16wb_fixed: 2909 case ARM::VLD1d32wb_fixed: 2910 case ARM::VLD1d64wb_fixed: 2911 case ARM::VLD1d8Twb_fixed: 2912 case ARM::VLD1d16Twb_fixed: 2913 case ARM::VLD1d32Twb_fixed: 2914 case ARM::VLD1d64Twb_fixed: 2915 case ARM::VLD1d8Qwb_fixed: 2916 case ARM::VLD1d16Qwb_fixed: 2917 case ARM::VLD1d32Qwb_fixed: 2918 case ARM::VLD1d64Qwb_fixed: 2919 case ARM::VLD1d8wb_register: 2920 case ARM::VLD1d16wb_register: 2921 case ARM::VLD1d32wb_register: 2922 case ARM::VLD1d64wb_register: 2923 case ARM::VLD1q8wb_fixed: 2924 case ARM::VLD1q16wb_fixed: 2925 case ARM::VLD1q32wb_fixed: 2926 case ARM::VLD1q64wb_fixed: 2927 case ARM::VLD1q8wb_register: 2928 case ARM::VLD1q16wb_register: 2929 case ARM::VLD1q32wb_register: 2930 case ARM::VLD1q64wb_register: 2931 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2932 // variant encodes Rm == 0xf. Anything else is a register offset post- 2933 // increment and we need to add the register operand to the instruction. 2934 if (Rm != 0xD && Rm != 0xF && 2935 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2936 return MCDisassembler::Fail; 2937 break; 2938 case ARM::VLD2d8wb_fixed: 2939 case ARM::VLD2d16wb_fixed: 2940 case ARM::VLD2d32wb_fixed: 2941 case ARM::VLD2b8wb_fixed: 2942 case ARM::VLD2b16wb_fixed: 2943 case ARM::VLD2b32wb_fixed: 2944 case ARM::VLD2q8wb_fixed: 2945 case ARM::VLD2q16wb_fixed: 2946 case ARM::VLD2q32wb_fixed: 2947 break; 2948 } 2949 2950 return S; 2951 } 2952 2953 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2954 uint64_t Address, const void *Decoder) { 2955 unsigned type = fieldFromInstruction(Insn, 8, 4); 2956 unsigned align = fieldFromInstruction(Insn, 4, 2); 2957 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2958 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2959 if (type == 10 && align == 3) return MCDisassembler::Fail; 2960 2961 unsigned load = fieldFromInstruction(Insn, 21, 1); 2962 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2963 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2964 } 2965 2966 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2967 uint64_t Address, const void *Decoder) { 2968 unsigned size = fieldFromInstruction(Insn, 6, 2); 2969 if (size == 3) return MCDisassembler::Fail; 2970 2971 unsigned type = fieldFromInstruction(Insn, 8, 4); 2972 unsigned align = fieldFromInstruction(Insn, 4, 2); 2973 if (type == 8 && align == 3) return MCDisassembler::Fail; 2974 if (type == 9 && align == 3) return MCDisassembler::Fail; 2975 2976 unsigned load = fieldFromInstruction(Insn, 21, 1); 2977 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2978 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2979 } 2980 2981 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2982 uint64_t Address, const void *Decoder) { 2983 unsigned size = fieldFromInstruction(Insn, 6, 2); 2984 if (size == 3) return MCDisassembler::Fail; 2985 2986 unsigned align = fieldFromInstruction(Insn, 4, 2); 2987 if (align & 2) return MCDisassembler::Fail; 2988 2989 unsigned load = fieldFromInstruction(Insn, 21, 1); 2990 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2991 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2992 } 2993 2994 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2995 uint64_t Address, const void *Decoder) { 2996 unsigned size = fieldFromInstruction(Insn, 6, 2); 2997 if (size == 3) return MCDisassembler::Fail; 2998 2999 unsigned load = fieldFromInstruction(Insn, 21, 1); 3000 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3001 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3002 } 3003 3004 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3005 uint64_t Address, const void *Decoder) { 3006 DecodeStatus S = MCDisassembler::Success; 3007 3008 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3009 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3010 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3011 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3012 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3013 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3014 3015 // Writeback Operand 3016 switch (Inst.getOpcode()) { 3017 case ARM::VST1d8wb_fixed: 3018 case ARM::VST1d16wb_fixed: 3019 case ARM::VST1d32wb_fixed: 3020 case ARM::VST1d64wb_fixed: 3021 case ARM::VST1d8wb_register: 3022 case ARM::VST1d16wb_register: 3023 case ARM::VST1d32wb_register: 3024 case ARM::VST1d64wb_register: 3025 case ARM::VST1q8wb_fixed: 3026 case ARM::VST1q16wb_fixed: 3027 case ARM::VST1q32wb_fixed: 3028 case ARM::VST1q64wb_fixed: 3029 case ARM::VST1q8wb_register: 3030 case ARM::VST1q16wb_register: 3031 case ARM::VST1q32wb_register: 3032 case ARM::VST1q64wb_register: 3033 case ARM::VST1d8Twb_fixed: 3034 case ARM::VST1d16Twb_fixed: 3035 case ARM::VST1d32Twb_fixed: 3036 case ARM::VST1d64Twb_fixed: 3037 case ARM::VST1d8Twb_register: 3038 case ARM::VST1d16Twb_register: 3039 case ARM::VST1d32Twb_register: 3040 case ARM::VST1d64Twb_register: 3041 case ARM::VST1d8Qwb_fixed: 3042 case ARM::VST1d16Qwb_fixed: 3043 case ARM::VST1d32Qwb_fixed: 3044 case ARM::VST1d64Qwb_fixed: 3045 case ARM::VST1d8Qwb_register: 3046 case ARM::VST1d16Qwb_register: 3047 case ARM::VST1d32Qwb_register: 3048 case ARM::VST1d64Qwb_register: 3049 case ARM::VST2d8wb_fixed: 3050 case ARM::VST2d16wb_fixed: 3051 case ARM::VST2d32wb_fixed: 3052 case ARM::VST2d8wb_register: 3053 case ARM::VST2d16wb_register: 3054 case ARM::VST2d32wb_register: 3055 case ARM::VST2q8wb_fixed: 3056 case ARM::VST2q16wb_fixed: 3057 case ARM::VST2q32wb_fixed: 3058 case ARM::VST2q8wb_register: 3059 case ARM::VST2q16wb_register: 3060 case ARM::VST2q32wb_register: 3061 case ARM::VST2b8wb_fixed: 3062 case ARM::VST2b16wb_fixed: 3063 case ARM::VST2b32wb_fixed: 3064 case ARM::VST2b8wb_register: 3065 case ARM::VST2b16wb_register: 3066 case ARM::VST2b32wb_register: 3067 if (Rm == 0xF) 3068 return MCDisassembler::Fail; 3069 Inst.addOperand(MCOperand::createImm(0)); 3070 break; 3071 case ARM::VST3d8_UPD: 3072 case ARM::VST3d16_UPD: 3073 case ARM::VST3d32_UPD: 3074 case ARM::VST3q8_UPD: 3075 case ARM::VST3q16_UPD: 3076 case ARM::VST3q32_UPD: 3077 case ARM::VST4d8_UPD: 3078 case ARM::VST4d16_UPD: 3079 case ARM::VST4d32_UPD: 3080 case ARM::VST4q8_UPD: 3081 case ARM::VST4q16_UPD: 3082 case ARM::VST4q32_UPD: 3083 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3084 return MCDisassembler::Fail; 3085 break; 3086 default: 3087 break; 3088 } 3089 3090 // AddrMode6 Base (register+alignment) 3091 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3092 return MCDisassembler::Fail; 3093 3094 // AddrMode6 Offset (register) 3095 switch (Inst.getOpcode()) { 3096 default: 3097 if (Rm == 0xD) 3098 Inst.addOperand(MCOperand::createReg(0)); 3099 else if (Rm != 0xF) { 3100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3101 return MCDisassembler::Fail; 3102 } 3103 break; 3104 case ARM::VST1d8wb_fixed: 3105 case ARM::VST1d16wb_fixed: 3106 case ARM::VST1d32wb_fixed: 3107 case ARM::VST1d64wb_fixed: 3108 case ARM::VST1q8wb_fixed: 3109 case ARM::VST1q16wb_fixed: 3110 case ARM::VST1q32wb_fixed: 3111 case ARM::VST1q64wb_fixed: 3112 case ARM::VST1d8Twb_fixed: 3113 case ARM::VST1d16Twb_fixed: 3114 case ARM::VST1d32Twb_fixed: 3115 case ARM::VST1d64Twb_fixed: 3116 case ARM::VST1d8Qwb_fixed: 3117 case ARM::VST1d16Qwb_fixed: 3118 case ARM::VST1d32Qwb_fixed: 3119 case ARM::VST1d64Qwb_fixed: 3120 case ARM::VST2d8wb_fixed: 3121 case ARM::VST2d16wb_fixed: 3122 case ARM::VST2d32wb_fixed: 3123 case ARM::VST2q8wb_fixed: 3124 case ARM::VST2q16wb_fixed: 3125 case ARM::VST2q32wb_fixed: 3126 case ARM::VST2b8wb_fixed: 3127 case ARM::VST2b16wb_fixed: 3128 case ARM::VST2b32wb_fixed: 3129 break; 3130 } 3131 3132 // First input register 3133 switch (Inst.getOpcode()) { 3134 case ARM::VST1q16: 3135 case ARM::VST1q32: 3136 case ARM::VST1q64: 3137 case ARM::VST1q8: 3138 case ARM::VST1q16wb_fixed: 3139 case ARM::VST1q16wb_register: 3140 case ARM::VST1q32wb_fixed: 3141 case ARM::VST1q32wb_register: 3142 case ARM::VST1q64wb_fixed: 3143 case ARM::VST1q64wb_register: 3144 case ARM::VST1q8wb_fixed: 3145 case ARM::VST1q8wb_register: 3146 case ARM::VST2d16: 3147 case ARM::VST2d32: 3148 case ARM::VST2d8: 3149 case ARM::VST2d16wb_fixed: 3150 case ARM::VST2d16wb_register: 3151 case ARM::VST2d32wb_fixed: 3152 case ARM::VST2d32wb_register: 3153 case ARM::VST2d8wb_fixed: 3154 case ARM::VST2d8wb_register: 3155 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3156 return MCDisassembler::Fail; 3157 break; 3158 case ARM::VST2b16: 3159 case ARM::VST2b32: 3160 case ARM::VST2b8: 3161 case ARM::VST2b16wb_fixed: 3162 case ARM::VST2b16wb_register: 3163 case ARM::VST2b32wb_fixed: 3164 case ARM::VST2b32wb_register: 3165 case ARM::VST2b8wb_fixed: 3166 case ARM::VST2b8wb_register: 3167 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3168 return MCDisassembler::Fail; 3169 break; 3170 default: 3171 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3172 return MCDisassembler::Fail; 3173 } 3174 3175 // Second input register 3176 switch (Inst.getOpcode()) { 3177 case ARM::VST3d8: 3178 case ARM::VST3d16: 3179 case ARM::VST3d32: 3180 case ARM::VST3d8_UPD: 3181 case ARM::VST3d16_UPD: 3182 case ARM::VST3d32_UPD: 3183 case ARM::VST4d8: 3184 case ARM::VST4d16: 3185 case ARM::VST4d32: 3186 case ARM::VST4d8_UPD: 3187 case ARM::VST4d16_UPD: 3188 case ARM::VST4d32_UPD: 3189 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 break; 3192 case ARM::VST3q8: 3193 case ARM::VST3q16: 3194 case ARM::VST3q32: 3195 case ARM::VST3q8_UPD: 3196 case ARM::VST3q16_UPD: 3197 case ARM::VST3q32_UPD: 3198 case ARM::VST4q8: 3199 case ARM::VST4q16: 3200 case ARM::VST4q32: 3201 case ARM::VST4q8_UPD: 3202 case ARM::VST4q16_UPD: 3203 case ARM::VST4q32_UPD: 3204 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3205 return MCDisassembler::Fail; 3206 break; 3207 default: 3208 break; 3209 } 3210 3211 // Third input register 3212 switch (Inst.getOpcode()) { 3213 case ARM::VST3d8: 3214 case ARM::VST3d16: 3215 case ARM::VST3d32: 3216 case ARM::VST3d8_UPD: 3217 case ARM::VST3d16_UPD: 3218 case ARM::VST3d32_UPD: 3219 case ARM::VST4d8: 3220 case ARM::VST4d16: 3221 case ARM::VST4d32: 3222 case ARM::VST4d8_UPD: 3223 case ARM::VST4d16_UPD: 3224 case ARM::VST4d32_UPD: 3225 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3226 return MCDisassembler::Fail; 3227 break; 3228 case ARM::VST3q8: 3229 case ARM::VST3q16: 3230 case ARM::VST3q32: 3231 case ARM::VST3q8_UPD: 3232 case ARM::VST3q16_UPD: 3233 case ARM::VST3q32_UPD: 3234 case ARM::VST4q8: 3235 case ARM::VST4q16: 3236 case ARM::VST4q32: 3237 case ARM::VST4q8_UPD: 3238 case ARM::VST4q16_UPD: 3239 case ARM::VST4q32_UPD: 3240 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3241 return MCDisassembler::Fail; 3242 break; 3243 default: 3244 break; 3245 } 3246 3247 // Fourth input register 3248 switch (Inst.getOpcode()) { 3249 case ARM::VST4d8: 3250 case ARM::VST4d16: 3251 case ARM::VST4d32: 3252 case ARM::VST4d8_UPD: 3253 case ARM::VST4d16_UPD: 3254 case ARM::VST4d32_UPD: 3255 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3256 return MCDisassembler::Fail; 3257 break; 3258 case ARM::VST4q8: 3259 case ARM::VST4q16: 3260 case ARM::VST4q32: 3261 case ARM::VST4q8_UPD: 3262 case ARM::VST4q16_UPD: 3263 case ARM::VST4q32_UPD: 3264 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3265 return MCDisassembler::Fail; 3266 break; 3267 default: 3268 break; 3269 } 3270 3271 return S; 3272 } 3273 3274 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3275 uint64_t Address, const void *Decoder) { 3276 DecodeStatus S = MCDisassembler::Success; 3277 3278 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3279 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3280 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3281 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3282 unsigned align = fieldFromInstruction(Insn, 4, 1); 3283 unsigned size = fieldFromInstruction(Insn, 6, 2); 3284 3285 if (size == 0 && align == 1) 3286 return MCDisassembler::Fail; 3287 align *= (1 << size); 3288 3289 switch (Inst.getOpcode()) { 3290 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3291 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3292 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3293 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3294 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 break; 3297 default: 3298 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3299 return MCDisassembler::Fail; 3300 break; 3301 } 3302 if (Rm != 0xF) { 3303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3304 return MCDisassembler::Fail; 3305 } 3306 3307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3308 return MCDisassembler::Fail; 3309 Inst.addOperand(MCOperand::createImm(align)); 3310 3311 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3312 // variant encodes Rm == 0xf. Anything else is a register offset post- 3313 // increment and we need to add the register operand to the instruction. 3314 if (Rm != 0xD && Rm != 0xF && 3315 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3316 return MCDisassembler::Fail; 3317 3318 return S; 3319 } 3320 3321 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3322 uint64_t Address, const void *Decoder) { 3323 DecodeStatus S = MCDisassembler::Success; 3324 3325 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3326 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3327 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3328 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3329 unsigned align = fieldFromInstruction(Insn, 4, 1); 3330 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3331 align *= 2*size; 3332 3333 switch (Inst.getOpcode()) { 3334 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3335 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3336 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3337 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3338 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3339 return MCDisassembler::Fail; 3340 break; 3341 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3342 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3343 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3344 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3345 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3346 return MCDisassembler::Fail; 3347 break; 3348 default: 3349 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 break; 3352 } 3353 3354 if (Rm != 0xF) 3355 Inst.addOperand(MCOperand::createImm(0)); 3356 3357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 Inst.addOperand(MCOperand::createImm(align)); 3360 3361 if (Rm != 0xD && Rm != 0xF) { 3362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3363 return MCDisassembler::Fail; 3364 } 3365 3366 return S; 3367 } 3368 3369 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3370 uint64_t Address, const void *Decoder) { 3371 DecodeStatus S = MCDisassembler::Success; 3372 3373 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3374 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3375 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3376 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3377 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3378 3379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3380 return MCDisassembler::Fail; 3381 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3382 return MCDisassembler::Fail; 3383 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3384 return MCDisassembler::Fail; 3385 if (Rm != 0xF) { 3386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3387 return MCDisassembler::Fail; 3388 } 3389 3390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3391 return MCDisassembler::Fail; 3392 Inst.addOperand(MCOperand::createImm(0)); 3393 3394 if (Rm == 0xD) 3395 Inst.addOperand(MCOperand::createReg(0)); 3396 else if (Rm != 0xF) { 3397 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3398 return MCDisassembler::Fail; 3399 } 3400 3401 return S; 3402 } 3403 3404 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3405 uint64_t Address, const void *Decoder) { 3406 DecodeStatus S = MCDisassembler::Success; 3407 3408 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3409 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3410 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3411 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3412 unsigned size = fieldFromInstruction(Insn, 6, 2); 3413 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3414 unsigned align = fieldFromInstruction(Insn, 4, 1); 3415 3416 if (size == 0x3) { 3417 if (align == 0) 3418 return MCDisassembler::Fail; 3419 align = 16; 3420 } else { 3421 if (size == 2) { 3422 align *= 8; 3423 } else { 3424 size = 1 << size; 3425 align *= 4*size; 3426 } 3427 } 3428 3429 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3430 return MCDisassembler::Fail; 3431 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3432 return MCDisassembler::Fail; 3433 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3436 return MCDisassembler::Fail; 3437 if (Rm != 0xF) { 3438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3439 return MCDisassembler::Fail; 3440 } 3441 3442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3443 return MCDisassembler::Fail; 3444 Inst.addOperand(MCOperand::createImm(align)); 3445 3446 if (Rm == 0xD) 3447 Inst.addOperand(MCOperand::createReg(0)); 3448 else if (Rm != 0xF) { 3449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3450 return MCDisassembler::Fail; 3451 } 3452 3453 return S; 3454 } 3455 3456 static DecodeStatus 3457 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3458 uint64_t Address, const void *Decoder) { 3459 DecodeStatus S = MCDisassembler::Success; 3460 3461 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3462 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3463 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3464 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3465 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3466 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3467 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3468 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3469 3470 if (Q) { 3471 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3472 return MCDisassembler::Fail; 3473 } else { 3474 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3475 return MCDisassembler::Fail; 3476 } 3477 3478 Inst.addOperand(MCOperand::createImm(imm)); 3479 3480 switch (Inst.getOpcode()) { 3481 case ARM::VORRiv4i16: 3482 case ARM::VORRiv2i32: 3483 case ARM::VBICiv4i16: 3484 case ARM::VBICiv2i32: 3485 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3486 return MCDisassembler::Fail; 3487 break; 3488 case ARM::VORRiv8i16: 3489 case ARM::VORRiv4i32: 3490 case ARM::VBICiv8i16: 3491 case ARM::VBICiv4i32: 3492 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3493 return MCDisassembler::Fail; 3494 break; 3495 default: 3496 break; 3497 } 3498 3499 return S; 3500 } 3501 3502 static DecodeStatus 3503 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3504 uint64_t Address, const void *Decoder) { 3505 DecodeStatus S = MCDisassembler::Success; 3506 3507 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3508 fieldFromInstruction(Insn, 13, 3)); 3509 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3510 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3511 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3512 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3513 imm |= cmode << 8; 3514 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3515 3516 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3517 return MCDisassembler::Fail; 3518 3519 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3520 return MCDisassembler::Fail; 3521 3522 Inst.addOperand(MCOperand::createImm(imm)); 3523 3524 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3525 Inst.addOperand(MCOperand::createReg(0)); 3526 Inst.addOperand(MCOperand::createImm(0)); 3527 3528 return S; 3529 } 3530 3531 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3532 uint64_t Address, const void *Decoder) { 3533 DecodeStatus S = MCDisassembler::Success; 3534 3535 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3536 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3537 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3538 return MCDisassembler::Fail; 3539 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3540 3541 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3542 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3543 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3544 return MCDisassembler::Fail; 3545 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3546 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3547 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3548 return MCDisassembler::Fail; 3549 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3550 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3551 Inst.addOperand(MCOperand::createImm(Qd)); 3552 3553 return S; 3554 } 3555 3556 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3557 uint64_t Address, const void *Decoder) { 3558 DecodeStatus S = MCDisassembler::Success; 3559 3560 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3561 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3562 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3563 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3564 unsigned size = fieldFromInstruction(Insn, 18, 2); 3565 3566 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3567 return MCDisassembler::Fail; 3568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3569 return MCDisassembler::Fail; 3570 Inst.addOperand(MCOperand::createImm(8 << size)); 3571 3572 return S; 3573 } 3574 3575 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3576 uint64_t Address, const void *Decoder) { 3577 Inst.addOperand(MCOperand::createImm(8 - Val)); 3578 return MCDisassembler::Success; 3579 } 3580 3581 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3582 uint64_t Address, const void *Decoder) { 3583 Inst.addOperand(MCOperand::createImm(16 - Val)); 3584 return MCDisassembler::Success; 3585 } 3586 3587 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3588 uint64_t Address, const void *Decoder) { 3589 Inst.addOperand(MCOperand::createImm(32 - Val)); 3590 return MCDisassembler::Success; 3591 } 3592 3593 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3594 uint64_t Address, const void *Decoder) { 3595 Inst.addOperand(MCOperand::createImm(64 - Val)); 3596 return MCDisassembler::Success; 3597 } 3598 3599 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3600 uint64_t Address, const void *Decoder) { 3601 DecodeStatus S = MCDisassembler::Success; 3602 3603 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3604 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3605 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3606 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3607 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3608 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3609 unsigned op = fieldFromInstruction(Insn, 6, 1); 3610 3611 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3612 return MCDisassembler::Fail; 3613 if (op) { 3614 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3615 return MCDisassembler::Fail; // Writeback 3616 } 3617 3618 switch (Inst.getOpcode()) { 3619 case ARM::VTBL2: 3620 case ARM::VTBX2: 3621 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3622 return MCDisassembler::Fail; 3623 break; 3624 default: 3625 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3626 return MCDisassembler::Fail; 3627 } 3628 3629 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3630 return MCDisassembler::Fail; 3631 3632 return S; 3633 } 3634 3635 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3636 uint64_t Address, const void *Decoder) { 3637 DecodeStatus S = MCDisassembler::Success; 3638 3639 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3640 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3641 3642 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 3645 switch(Inst.getOpcode()) { 3646 default: 3647 return MCDisassembler::Fail; 3648 case ARM::tADR: 3649 break; // tADR does not explicitly represent the PC as an operand. 3650 case ARM::tADDrSPi: 3651 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3652 break; 3653 } 3654 3655 Inst.addOperand(MCOperand::createImm(imm)); 3656 return S; 3657 } 3658 3659 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3660 uint64_t Address, const void *Decoder) { 3661 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3662 true, 2, Inst, Decoder)) 3663 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3664 return MCDisassembler::Success; 3665 } 3666 3667 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3668 uint64_t Address, const void *Decoder) { 3669 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3670 true, 4, Inst, Decoder)) 3671 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3672 return MCDisassembler::Success; 3673 } 3674 3675 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3676 uint64_t Address, const void *Decoder) { 3677 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3678 true, 2, Inst, Decoder)) 3679 Inst.addOperand(MCOperand::createImm(Val << 1)); 3680 return MCDisassembler::Success; 3681 } 3682 3683 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3684 uint64_t Address, const void *Decoder) { 3685 DecodeStatus S = MCDisassembler::Success; 3686 3687 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3688 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3689 3690 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3691 return MCDisassembler::Fail; 3692 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3693 return MCDisassembler::Fail; 3694 3695 return S; 3696 } 3697 3698 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3699 uint64_t Address, const void *Decoder) { 3700 DecodeStatus S = MCDisassembler::Success; 3701 3702 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3703 unsigned imm = fieldFromInstruction(Val, 3, 5); 3704 3705 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3706 return MCDisassembler::Fail; 3707 Inst.addOperand(MCOperand::createImm(imm)); 3708 3709 return S; 3710 } 3711 3712 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3713 uint64_t Address, const void *Decoder) { 3714 unsigned imm = Val << 2; 3715 3716 Inst.addOperand(MCOperand::createImm(imm)); 3717 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3718 3719 return MCDisassembler::Success; 3720 } 3721 3722 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3723 uint64_t Address, const void *Decoder) { 3724 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3725 Inst.addOperand(MCOperand::createImm(Val)); 3726 3727 return MCDisassembler::Success; 3728 } 3729 3730 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3731 uint64_t Address, const void *Decoder) { 3732 DecodeStatus S = MCDisassembler::Success; 3733 3734 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3735 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3736 unsigned imm = fieldFromInstruction(Val, 0, 2); 3737 3738 // Thumb stores cannot use PC as dest register. 3739 switch (Inst.getOpcode()) { 3740 case ARM::t2STRHs: 3741 case ARM::t2STRBs: 3742 case ARM::t2STRs: 3743 if (Rn == 15) 3744 return MCDisassembler::Fail; 3745 break; 3746 default: 3747 break; 3748 } 3749 3750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3751 return MCDisassembler::Fail; 3752 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3753 return MCDisassembler::Fail; 3754 Inst.addOperand(MCOperand::createImm(imm)); 3755 3756 return S; 3757 } 3758 3759 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3760 uint64_t Address, const void *Decoder) { 3761 DecodeStatus S = MCDisassembler::Success; 3762 3763 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3764 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3765 3766 const FeatureBitset &featureBits = 3767 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3768 3769 bool hasMP = featureBits[ARM::FeatureMP]; 3770 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3771 3772 if (Rn == 15) { 3773 switch (Inst.getOpcode()) { 3774 case ARM::t2LDRBs: 3775 Inst.setOpcode(ARM::t2LDRBpci); 3776 break; 3777 case ARM::t2LDRHs: 3778 Inst.setOpcode(ARM::t2LDRHpci); 3779 break; 3780 case ARM::t2LDRSHs: 3781 Inst.setOpcode(ARM::t2LDRSHpci); 3782 break; 3783 case ARM::t2LDRSBs: 3784 Inst.setOpcode(ARM::t2LDRSBpci); 3785 break; 3786 case ARM::t2LDRs: 3787 Inst.setOpcode(ARM::t2LDRpci); 3788 break; 3789 case ARM::t2PLDs: 3790 Inst.setOpcode(ARM::t2PLDpci); 3791 break; 3792 case ARM::t2PLIs: 3793 Inst.setOpcode(ARM::t2PLIpci); 3794 break; 3795 default: 3796 return MCDisassembler::Fail; 3797 } 3798 3799 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3800 } 3801 3802 if (Rt == 15) { 3803 switch (Inst.getOpcode()) { 3804 case ARM::t2LDRSHs: 3805 return MCDisassembler::Fail; 3806 case ARM::t2LDRHs: 3807 Inst.setOpcode(ARM::t2PLDWs); 3808 break; 3809 case ARM::t2LDRSBs: 3810 Inst.setOpcode(ARM::t2PLIs); 3811 break; 3812 default: 3813 break; 3814 } 3815 } 3816 3817 switch (Inst.getOpcode()) { 3818 case ARM::t2PLDs: 3819 break; 3820 case ARM::t2PLIs: 3821 if (!hasV7Ops) 3822 return MCDisassembler::Fail; 3823 break; 3824 case ARM::t2PLDWs: 3825 if (!hasV7Ops || !hasMP) 3826 return MCDisassembler::Fail; 3827 break; 3828 default: 3829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3830 return MCDisassembler::Fail; 3831 } 3832 3833 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3834 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3835 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3836 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3837 return MCDisassembler::Fail; 3838 3839 return S; 3840 } 3841 3842 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3843 uint64_t Address, const void* Decoder) { 3844 DecodeStatus S = MCDisassembler::Success; 3845 3846 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3847 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3848 unsigned U = fieldFromInstruction(Insn, 9, 1); 3849 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3850 imm |= (U << 8); 3851 imm |= (Rn << 9); 3852 unsigned add = fieldFromInstruction(Insn, 9, 1); 3853 3854 const FeatureBitset &featureBits = 3855 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3856 3857 bool hasMP = featureBits[ARM::FeatureMP]; 3858 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3859 3860 if (Rn == 15) { 3861 switch (Inst.getOpcode()) { 3862 case ARM::t2LDRi8: 3863 Inst.setOpcode(ARM::t2LDRpci); 3864 break; 3865 case ARM::t2LDRBi8: 3866 Inst.setOpcode(ARM::t2LDRBpci); 3867 break; 3868 case ARM::t2LDRSBi8: 3869 Inst.setOpcode(ARM::t2LDRSBpci); 3870 break; 3871 case ARM::t2LDRHi8: 3872 Inst.setOpcode(ARM::t2LDRHpci); 3873 break; 3874 case ARM::t2LDRSHi8: 3875 Inst.setOpcode(ARM::t2LDRSHpci); 3876 break; 3877 case ARM::t2PLDi8: 3878 Inst.setOpcode(ARM::t2PLDpci); 3879 break; 3880 case ARM::t2PLIi8: 3881 Inst.setOpcode(ARM::t2PLIpci); 3882 break; 3883 default: 3884 return MCDisassembler::Fail; 3885 } 3886 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3887 } 3888 3889 if (Rt == 15) { 3890 switch (Inst.getOpcode()) { 3891 case ARM::t2LDRSHi8: 3892 return MCDisassembler::Fail; 3893 case ARM::t2LDRHi8: 3894 if (!add) 3895 Inst.setOpcode(ARM::t2PLDWi8); 3896 break; 3897 case ARM::t2LDRSBi8: 3898 Inst.setOpcode(ARM::t2PLIi8); 3899 break; 3900 default: 3901 break; 3902 } 3903 } 3904 3905 switch (Inst.getOpcode()) { 3906 case ARM::t2PLDi8: 3907 break; 3908 case ARM::t2PLIi8: 3909 if (!hasV7Ops) 3910 return MCDisassembler::Fail; 3911 break; 3912 case ARM::t2PLDWi8: 3913 if (!hasV7Ops || !hasMP) 3914 return MCDisassembler::Fail; 3915 break; 3916 default: 3917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3918 return MCDisassembler::Fail; 3919 } 3920 3921 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3922 return MCDisassembler::Fail; 3923 return S; 3924 } 3925 3926 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3927 uint64_t Address, const void* Decoder) { 3928 DecodeStatus S = MCDisassembler::Success; 3929 3930 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3931 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3932 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3933 imm |= (Rn << 13); 3934 3935 const FeatureBitset &featureBits = 3936 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3937 3938 bool hasMP = featureBits[ARM::FeatureMP]; 3939 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3940 3941 if (Rn == 15) { 3942 switch (Inst.getOpcode()) { 3943 case ARM::t2LDRi12: 3944 Inst.setOpcode(ARM::t2LDRpci); 3945 break; 3946 case ARM::t2LDRHi12: 3947 Inst.setOpcode(ARM::t2LDRHpci); 3948 break; 3949 case ARM::t2LDRSHi12: 3950 Inst.setOpcode(ARM::t2LDRSHpci); 3951 break; 3952 case ARM::t2LDRBi12: 3953 Inst.setOpcode(ARM::t2LDRBpci); 3954 break; 3955 case ARM::t2LDRSBi12: 3956 Inst.setOpcode(ARM::t2LDRSBpci); 3957 break; 3958 case ARM::t2PLDi12: 3959 Inst.setOpcode(ARM::t2PLDpci); 3960 break; 3961 case ARM::t2PLIi12: 3962 Inst.setOpcode(ARM::t2PLIpci); 3963 break; 3964 default: 3965 return MCDisassembler::Fail; 3966 } 3967 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3968 } 3969 3970 if (Rt == 15) { 3971 switch (Inst.getOpcode()) { 3972 case ARM::t2LDRSHi12: 3973 return MCDisassembler::Fail; 3974 case ARM::t2LDRHi12: 3975 Inst.setOpcode(ARM::t2PLDWi12); 3976 break; 3977 case ARM::t2LDRSBi12: 3978 Inst.setOpcode(ARM::t2PLIi12); 3979 break; 3980 default: 3981 break; 3982 } 3983 } 3984 3985 switch (Inst.getOpcode()) { 3986 case ARM::t2PLDi12: 3987 break; 3988 case ARM::t2PLIi12: 3989 if (!hasV7Ops) 3990 return MCDisassembler::Fail; 3991 break; 3992 case ARM::t2PLDWi12: 3993 if (!hasV7Ops || !hasMP) 3994 return MCDisassembler::Fail; 3995 break; 3996 default: 3997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3998 return MCDisassembler::Fail; 3999 } 4000 4001 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4002 return MCDisassembler::Fail; 4003 return S; 4004 } 4005 4006 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4007 uint64_t Address, const void* Decoder) { 4008 DecodeStatus S = MCDisassembler::Success; 4009 4010 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4011 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4012 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4013 imm |= (Rn << 9); 4014 4015 if (Rn == 15) { 4016 switch (Inst.getOpcode()) { 4017 case ARM::t2LDRT: 4018 Inst.setOpcode(ARM::t2LDRpci); 4019 break; 4020 case ARM::t2LDRBT: 4021 Inst.setOpcode(ARM::t2LDRBpci); 4022 break; 4023 case ARM::t2LDRHT: 4024 Inst.setOpcode(ARM::t2LDRHpci); 4025 break; 4026 case ARM::t2LDRSBT: 4027 Inst.setOpcode(ARM::t2LDRSBpci); 4028 break; 4029 case ARM::t2LDRSHT: 4030 Inst.setOpcode(ARM::t2LDRSHpci); 4031 break; 4032 default: 4033 return MCDisassembler::Fail; 4034 } 4035 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4036 } 4037 4038 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4039 return MCDisassembler::Fail; 4040 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4041 return MCDisassembler::Fail; 4042 return S; 4043 } 4044 4045 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4046 uint64_t Address, const void* Decoder) { 4047 DecodeStatus S = MCDisassembler::Success; 4048 4049 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4050 unsigned U = fieldFromInstruction(Insn, 23, 1); 4051 int imm = fieldFromInstruction(Insn, 0, 12); 4052 4053 const FeatureBitset &featureBits = 4054 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4055 4056 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4057 4058 if (Rt == 15) { 4059 switch (Inst.getOpcode()) { 4060 case ARM::t2LDRBpci: 4061 case ARM::t2LDRHpci: 4062 Inst.setOpcode(ARM::t2PLDpci); 4063 break; 4064 case ARM::t2LDRSBpci: 4065 Inst.setOpcode(ARM::t2PLIpci); 4066 break; 4067 case ARM::t2LDRSHpci: 4068 return MCDisassembler::Fail; 4069 default: 4070 break; 4071 } 4072 } 4073 4074 switch(Inst.getOpcode()) { 4075 case ARM::t2PLDpci: 4076 break; 4077 case ARM::t2PLIpci: 4078 if (!hasV7Ops) 4079 return MCDisassembler::Fail; 4080 break; 4081 default: 4082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4083 return MCDisassembler::Fail; 4084 } 4085 4086 if (!U) { 4087 // Special case for #-0. 4088 if (imm == 0) 4089 imm = INT32_MIN; 4090 else 4091 imm = -imm; 4092 } 4093 Inst.addOperand(MCOperand::createImm(imm)); 4094 4095 return S; 4096 } 4097 4098 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4099 uint64_t Address, const void *Decoder) { 4100 if (Val == 0) 4101 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4102 else { 4103 int imm = Val & 0xFF; 4104 4105 if (!(Val & 0x100)) imm *= -1; 4106 Inst.addOperand(MCOperand::createImm(imm * 4)); 4107 } 4108 4109 return MCDisassembler::Success; 4110 } 4111 4112 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4113 const void *Decoder) { 4114 if (Val == 0) 4115 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4116 else { 4117 int imm = Val & 0x7F; 4118 4119 if (!(Val & 0x80)) 4120 imm *= -1; 4121 Inst.addOperand(MCOperand::createImm(imm * 4)); 4122 } 4123 4124 return MCDisassembler::Success; 4125 } 4126 4127 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4128 uint64_t Address, const void *Decoder) { 4129 DecodeStatus S = MCDisassembler::Success; 4130 4131 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4132 unsigned imm = fieldFromInstruction(Val, 0, 9); 4133 4134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4135 return MCDisassembler::Fail; 4136 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4137 return MCDisassembler::Fail; 4138 4139 return S; 4140 } 4141 4142 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4143 uint64_t Address, 4144 const void *Decoder) { 4145 DecodeStatus S = MCDisassembler::Success; 4146 4147 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4148 unsigned imm = fieldFromInstruction(Val, 0, 8); 4149 4150 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4151 return MCDisassembler::Fail; 4152 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 4155 return S; 4156 } 4157 4158 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4159 uint64_t Address, const void *Decoder) { 4160 DecodeStatus S = MCDisassembler::Success; 4161 4162 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4163 unsigned imm = fieldFromInstruction(Val, 0, 8); 4164 4165 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4166 return MCDisassembler::Fail; 4167 4168 Inst.addOperand(MCOperand::createImm(imm)); 4169 4170 return S; 4171 } 4172 4173 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4174 uint64_t Address, const void *Decoder) { 4175 int imm = Val & 0xFF; 4176 if (Val == 0) 4177 imm = INT32_MIN; 4178 else if (!(Val & 0x100)) 4179 imm *= -1; 4180 Inst.addOperand(MCOperand::createImm(imm)); 4181 4182 return MCDisassembler::Success; 4183 } 4184 4185 template<int shift> 4186 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4187 uint64_t Address, const void *Decoder) { 4188 int imm = Val & 0x7F; 4189 if (Val == 0) 4190 imm = INT32_MIN; 4191 else if (!(Val & 0x80)) 4192 imm *= -1; 4193 if (imm != INT32_MIN) 4194 imm *= (1U << shift); 4195 Inst.addOperand(MCOperand::createImm(imm)); 4196 4197 return MCDisassembler::Success; 4198 } 4199 4200 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4201 uint64_t Address, const void *Decoder) { 4202 DecodeStatus S = MCDisassembler::Success; 4203 4204 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4205 unsigned imm = fieldFromInstruction(Val, 0, 9); 4206 4207 // Thumb stores cannot use PC as dest register. 4208 switch (Inst.getOpcode()) { 4209 case ARM::t2STRT: 4210 case ARM::t2STRBT: 4211 case ARM::t2STRHT: 4212 case ARM::t2STRi8: 4213 case ARM::t2STRHi8: 4214 case ARM::t2STRBi8: 4215 if (Rn == 15) 4216 return MCDisassembler::Fail; 4217 break; 4218 default: 4219 break; 4220 } 4221 4222 // Some instructions always use an additive offset. 4223 switch (Inst.getOpcode()) { 4224 case ARM::t2LDRT: 4225 case ARM::t2LDRBT: 4226 case ARM::t2LDRHT: 4227 case ARM::t2LDRSBT: 4228 case ARM::t2LDRSHT: 4229 case ARM::t2STRT: 4230 case ARM::t2STRBT: 4231 case ARM::t2STRHT: 4232 imm |= 0x100; 4233 break; 4234 default: 4235 break; 4236 } 4237 4238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4239 return MCDisassembler::Fail; 4240 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4241 return MCDisassembler::Fail; 4242 4243 return S; 4244 } 4245 4246 template<int shift> 4247 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4248 uint64_t Address, 4249 const void *Decoder) { 4250 DecodeStatus S = MCDisassembler::Success; 4251 4252 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4253 unsigned imm = fieldFromInstruction(Val, 0, 8); 4254 4255 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4256 return MCDisassembler::Fail; 4257 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4258 return MCDisassembler::Fail; 4259 4260 return S; 4261 } 4262 4263 template<int shift, int WriteBack> 4264 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4265 uint64_t Address, 4266 const void *Decoder) { 4267 DecodeStatus S = MCDisassembler::Success; 4268 4269 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4270 unsigned imm = fieldFromInstruction(Val, 0, 8); 4271 if (WriteBack) { 4272 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4273 return MCDisassembler::Fail; 4274 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4275 return MCDisassembler::Fail; 4276 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4277 return MCDisassembler::Fail; 4278 4279 return S; 4280 } 4281 4282 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4283 uint64_t Address, const void *Decoder) { 4284 DecodeStatus S = MCDisassembler::Success; 4285 4286 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4287 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4288 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4289 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4290 addr |= Rn << 9; 4291 unsigned load = fieldFromInstruction(Insn, 20, 1); 4292 4293 if (Rn == 15) { 4294 switch (Inst.getOpcode()) { 4295 case ARM::t2LDR_PRE: 4296 case ARM::t2LDR_POST: 4297 Inst.setOpcode(ARM::t2LDRpci); 4298 break; 4299 case ARM::t2LDRB_PRE: 4300 case ARM::t2LDRB_POST: 4301 Inst.setOpcode(ARM::t2LDRBpci); 4302 break; 4303 case ARM::t2LDRH_PRE: 4304 case ARM::t2LDRH_POST: 4305 Inst.setOpcode(ARM::t2LDRHpci); 4306 break; 4307 case ARM::t2LDRSB_PRE: 4308 case ARM::t2LDRSB_POST: 4309 if (Rt == 15) 4310 Inst.setOpcode(ARM::t2PLIpci); 4311 else 4312 Inst.setOpcode(ARM::t2LDRSBpci); 4313 break; 4314 case ARM::t2LDRSH_PRE: 4315 case ARM::t2LDRSH_POST: 4316 Inst.setOpcode(ARM::t2LDRSHpci); 4317 break; 4318 default: 4319 return MCDisassembler::Fail; 4320 } 4321 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4322 } 4323 4324 if (!load) { 4325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4326 return MCDisassembler::Fail; 4327 } 4328 4329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4330 return MCDisassembler::Fail; 4331 4332 if (load) { 4333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4334 return MCDisassembler::Fail; 4335 } 4336 4337 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4338 return MCDisassembler::Fail; 4339 4340 return S; 4341 } 4342 4343 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4344 uint64_t Address, const void *Decoder) { 4345 DecodeStatus S = MCDisassembler::Success; 4346 4347 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4348 unsigned imm = fieldFromInstruction(Val, 0, 12); 4349 4350 // Thumb stores cannot use PC as dest register. 4351 switch (Inst.getOpcode()) { 4352 case ARM::t2STRi12: 4353 case ARM::t2STRBi12: 4354 case ARM::t2STRHi12: 4355 if (Rn == 15) 4356 return MCDisassembler::Fail; 4357 break; 4358 default: 4359 break; 4360 } 4361 4362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 Inst.addOperand(MCOperand::createImm(imm)); 4365 4366 return S; 4367 } 4368 4369 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4370 uint64_t Address, const void *Decoder) { 4371 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4372 4373 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4374 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4375 Inst.addOperand(MCOperand::createImm(imm)); 4376 4377 return MCDisassembler::Success; 4378 } 4379 4380 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4381 uint64_t Address, const void *Decoder) { 4382 DecodeStatus S = MCDisassembler::Success; 4383 4384 if (Inst.getOpcode() == ARM::tADDrSP) { 4385 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4386 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4387 4388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4389 return MCDisassembler::Fail; 4390 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4392 return MCDisassembler::Fail; 4393 } else if (Inst.getOpcode() == ARM::tADDspr) { 4394 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4395 4396 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4397 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4398 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4399 return MCDisassembler::Fail; 4400 } 4401 4402 return S; 4403 } 4404 4405 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4406 uint64_t Address, const void *Decoder) { 4407 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4408 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4409 4410 Inst.addOperand(MCOperand::createImm(imod)); 4411 Inst.addOperand(MCOperand::createImm(flags)); 4412 4413 return MCDisassembler::Success; 4414 } 4415 4416 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4417 uint64_t Address, const void *Decoder) { 4418 DecodeStatus S = MCDisassembler::Success; 4419 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4420 unsigned add = fieldFromInstruction(Insn, 4, 1); 4421 4422 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4423 return MCDisassembler::Fail; 4424 Inst.addOperand(MCOperand::createImm(add)); 4425 4426 return S; 4427 } 4428 4429 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4430 uint64_t Address, const void *Decoder) { 4431 DecodeStatus S = MCDisassembler::Success; 4432 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4433 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4434 4435 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4436 return MCDisassembler::Fail; 4437 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4438 return MCDisassembler::Fail; 4439 4440 return S; 4441 } 4442 4443 template<int shift> 4444 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4445 uint64_t Address, const void *Decoder) { 4446 DecodeStatus S = MCDisassembler::Success; 4447 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4448 int imm = fieldFromInstruction(Insn, 0, 7); 4449 4450 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4451 return MCDisassembler::Fail; 4452 4453 if(!fieldFromInstruction(Insn, 7, 1)) { 4454 if (imm == 0) 4455 imm = INT32_MIN; // indicate -0 4456 else 4457 imm *= -1; 4458 } 4459 if (imm != INT32_MIN) 4460 imm *= (1U << shift); 4461 Inst.addOperand(MCOperand::createImm(imm)); 4462 4463 return S; 4464 } 4465 4466 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4467 uint64_t Address, const void *Decoder) { 4468 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4469 // Note only one trailing zero not two. Also the J1 and J2 values are from 4470 // the encoded instruction. So here change to I1 and I2 values via: 4471 // I1 = NOT(J1 EOR S); 4472 // I2 = NOT(J2 EOR S); 4473 // and build the imm32 with two trailing zeros as documented: 4474 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4475 unsigned S = (Val >> 23) & 1; 4476 unsigned J1 = (Val >> 22) & 1; 4477 unsigned J2 = (Val >> 21) & 1; 4478 unsigned I1 = !(J1 ^ S); 4479 unsigned I2 = !(J2 ^ S); 4480 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4481 int imm32 = SignExtend32<25>(tmp << 1); 4482 4483 if (!tryAddingSymbolicOperand(Address, 4484 (Address & ~2u) + imm32 + 4, 4485 true, 4, Inst, Decoder)) 4486 Inst.addOperand(MCOperand::createImm(imm32)); 4487 return MCDisassembler::Success; 4488 } 4489 4490 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4491 uint64_t Address, const void *Decoder) { 4492 if (Val == 0xA || Val == 0xB) 4493 return MCDisassembler::Fail; 4494 4495 const FeatureBitset &featureBits = 4496 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4497 4498 if (!isValidCoprocessorNumber(Val, featureBits)) 4499 return MCDisassembler::Fail; 4500 4501 Inst.addOperand(MCOperand::createImm(Val)); 4502 return MCDisassembler::Success; 4503 } 4504 4505 static DecodeStatus 4506 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4507 uint64_t Address, const void *Decoder) { 4508 DecodeStatus S = MCDisassembler::Success; 4509 4510 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4511 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4512 4513 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4515 return MCDisassembler::Fail; 4516 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4517 return MCDisassembler::Fail; 4518 return S; 4519 } 4520 4521 static DecodeStatus 4522 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4523 uint64_t Address, const void *Decoder) { 4524 DecodeStatus S = MCDisassembler::Success; 4525 4526 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4527 if (pred == 0xE || pred == 0xF) { 4528 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4529 switch (opc) { 4530 default: 4531 return MCDisassembler::Fail; 4532 case 0xf3bf8f4: 4533 Inst.setOpcode(ARM::t2DSB); 4534 break; 4535 case 0xf3bf8f5: 4536 Inst.setOpcode(ARM::t2DMB); 4537 break; 4538 case 0xf3bf8f6: 4539 Inst.setOpcode(ARM::t2ISB); 4540 break; 4541 } 4542 4543 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4544 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4545 } 4546 4547 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4548 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4549 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4550 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4551 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4552 4553 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4554 return MCDisassembler::Fail; 4555 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4556 return MCDisassembler::Fail; 4557 4558 return S; 4559 } 4560 4561 // Decode a shifted immediate operand. These basically consist 4562 // of an 8-bit value, and a 4-bit directive that specifies either 4563 // a splat operation or a rotation. 4564 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4565 uint64_t Address, const void *Decoder) { 4566 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4567 if (ctrl == 0) { 4568 unsigned byte = fieldFromInstruction(Val, 8, 2); 4569 unsigned imm = fieldFromInstruction(Val, 0, 8); 4570 switch (byte) { 4571 case 0: 4572 Inst.addOperand(MCOperand::createImm(imm)); 4573 break; 4574 case 1: 4575 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4576 break; 4577 case 2: 4578 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4579 break; 4580 case 3: 4581 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4582 (imm << 8) | imm)); 4583 break; 4584 } 4585 } else { 4586 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4587 unsigned rot = fieldFromInstruction(Val, 7, 5); 4588 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4589 Inst.addOperand(MCOperand::createImm(imm)); 4590 } 4591 4592 return MCDisassembler::Success; 4593 } 4594 4595 static DecodeStatus 4596 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4597 uint64_t Address, const void *Decoder) { 4598 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4599 true, 2, Inst, Decoder)) 4600 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4601 return MCDisassembler::Success; 4602 } 4603 4604 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4605 uint64_t Address, 4606 const void *Decoder) { 4607 // Val is passed in as S:J1:J2:imm10:imm11 4608 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4609 // the encoded instruction. So here change to I1 and I2 values via: 4610 // I1 = NOT(J1 EOR S); 4611 // I2 = NOT(J2 EOR S); 4612 // and build the imm32 with one trailing zero as documented: 4613 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4614 unsigned S = (Val >> 23) & 1; 4615 unsigned J1 = (Val >> 22) & 1; 4616 unsigned J2 = (Val >> 21) & 1; 4617 unsigned I1 = !(J1 ^ S); 4618 unsigned I2 = !(J2 ^ S); 4619 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4620 int imm32 = SignExtend32<25>(tmp << 1); 4621 4622 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4623 true, 4, Inst, Decoder)) 4624 Inst.addOperand(MCOperand::createImm(imm32)); 4625 return MCDisassembler::Success; 4626 } 4627 4628 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4629 uint64_t Address, const void *Decoder) { 4630 if (Val & ~0xf) 4631 return MCDisassembler::Fail; 4632 4633 Inst.addOperand(MCOperand::createImm(Val)); 4634 return MCDisassembler::Success; 4635 } 4636 4637 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4638 uint64_t Address, const void *Decoder) { 4639 if (Val & ~0xf) 4640 return MCDisassembler::Fail; 4641 4642 Inst.addOperand(MCOperand::createImm(Val)); 4643 return MCDisassembler::Success; 4644 } 4645 4646 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4647 uint64_t Address, const void *Decoder) { 4648 DecodeStatus S = MCDisassembler::Success; 4649 const FeatureBitset &FeatureBits = 4650 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4651 4652 if (FeatureBits[ARM::FeatureMClass]) { 4653 unsigned ValLow = Val & 0xff; 4654 4655 // Validate the SYSm value first. 4656 switch (ValLow) { 4657 case 0: // apsr 4658 case 1: // iapsr 4659 case 2: // eapsr 4660 case 3: // xpsr 4661 case 5: // ipsr 4662 case 6: // epsr 4663 case 7: // iepsr 4664 case 8: // msp 4665 case 9: // psp 4666 case 16: // primask 4667 case 20: // control 4668 break; 4669 case 17: // basepri 4670 case 18: // basepri_max 4671 case 19: // faultmask 4672 if (!(FeatureBits[ARM::HasV7Ops])) 4673 // Values basepri, basepri_max and faultmask are only valid for v7m. 4674 return MCDisassembler::Fail; 4675 break; 4676 case 0x8a: // msplim_ns 4677 case 0x8b: // psplim_ns 4678 case 0x91: // basepri_ns 4679 case 0x93: // faultmask_ns 4680 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4681 return MCDisassembler::Fail; 4682 LLVM_FALLTHROUGH; 4683 case 10: // msplim 4684 case 11: // psplim 4685 case 0x88: // msp_ns 4686 case 0x89: // psp_ns 4687 case 0x90: // primask_ns 4688 case 0x94: // control_ns 4689 case 0x98: // sp_ns 4690 if (!(FeatureBits[ARM::Feature8MSecExt])) 4691 return MCDisassembler::Fail; 4692 break; 4693 default: 4694 // Architecturally defined as unpredictable 4695 S = MCDisassembler::SoftFail; 4696 break; 4697 } 4698 4699 if (Inst.getOpcode() == ARM::t2MSR_M) { 4700 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4701 if (!(FeatureBits[ARM::HasV7Ops])) { 4702 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4703 // unpredictable. 4704 if (Mask != 2) 4705 S = MCDisassembler::SoftFail; 4706 } 4707 else { 4708 // The ARMv7-M architecture stores an additional 2-bit mask value in 4709 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4710 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4711 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4712 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4713 // only if the processor includes the DSP extension. 4714 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4715 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4716 S = MCDisassembler::SoftFail; 4717 } 4718 } 4719 } else { 4720 // A/R class 4721 if (Val == 0) 4722 return MCDisassembler::Fail; 4723 } 4724 Inst.addOperand(MCOperand::createImm(Val)); 4725 return S; 4726 } 4727 4728 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4729 uint64_t Address, const void *Decoder) { 4730 unsigned R = fieldFromInstruction(Val, 5, 1); 4731 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4732 4733 // The table of encodings for these banked registers comes from B9.2.3 of the 4734 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4735 // neater. So by fiat, these values are UNPREDICTABLE: 4736 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4737 return MCDisassembler::Fail; 4738 4739 Inst.addOperand(MCOperand::createImm(Val)); 4740 return MCDisassembler::Success; 4741 } 4742 4743 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4744 uint64_t Address, const void *Decoder) { 4745 DecodeStatus S = MCDisassembler::Success; 4746 4747 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4748 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4749 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4750 4751 if (Rn == 0xF) 4752 S = MCDisassembler::SoftFail; 4753 4754 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4755 return MCDisassembler::Fail; 4756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4757 return MCDisassembler::Fail; 4758 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4759 return MCDisassembler::Fail; 4760 4761 return S; 4762 } 4763 4764 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4765 uint64_t Address, 4766 const void *Decoder) { 4767 DecodeStatus S = MCDisassembler::Success; 4768 4769 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4770 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4771 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4772 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4773 4774 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4775 return MCDisassembler::Fail; 4776 4777 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4778 S = MCDisassembler::SoftFail; 4779 4780 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4781 return MCDisassembler::Fail; 4782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4783 return MCDisassembler::Fail; 4784 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4785 return MCDisassembler::Fail; 4786 4787 return S; 4788 } 4789 4790 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4791 uint64_t Address, const void *Decoder) { 4792 DecodeStatus S = MCDisassembler::Success; 4793 4794 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4795 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4796 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4797 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4798 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4799 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4800 4801 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4802 4803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4804 return MCDisassembler::Fail; 4805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4806 return MCDisassembler::Fail; 4807 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4808 return MCDisassembler::Fail; 4809 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4810 return MCDisassembler::Fail; 4811 4812 return S; 4813 } 4814 4815 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4816 uint64_t Address, const void *Decoder) { 4817 DecodeStatus S = MCDisassembler::Success; 4818 4819 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4820 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4821 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4822 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4823 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4824 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4825 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4826 4827 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4828 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4829 4830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4831 return MCDisassembler::Fail; 4832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4833 return MCDisassembler::Fail; 4834 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4835 return MCDisassembler::Fail; 4836 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4837 return MCDisassembler::Fail; 4838 4839 return S; 4840 } 4841 4842 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4843 uint64_t Address, const void *Decoder) { 4844 DecodeStatus S = MCDisassembler::Success; 4845 4846 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4847 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4848 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4849 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4850 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4851 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4852 4853 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4854 4855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4856 return MCDisassembler::Fail; 4857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4858 return MCDisassembler::Fail; 4859 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4860 return MCDisassembler::Fail; 4861 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 4864 return S; 4865 } 4866 4867 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4868 uint64_t Address, const void *Decoder) { 4869 DecodeStatus S = MCDisassembler::Success; 4870 4871 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4872 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4873 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4874 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4875 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4876 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4877 4878 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4879 4880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4881 return MCDisassembler::Fail; 4882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4883 return MCDisassembler::Fail; 4884 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4885 return MCDisassembler::Fail; 4886 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4887 return MCDisassembler::Fail; 4888 4889 return S; 4890 } 4891 4892 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4893 uint64_t Address, const void *Decoder) { 4894 DecodeStatus S = MCDisassembler::Success; 4895 4896 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4897 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4898 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4899 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4900 unsigned size = fieldFromInstruction(Insn, 10, 2); 4901 4902 unsigned align = 0; 4903 unsigned index = 0; 4904 switch (size) { 4905 default: 4906 return MCDisassembler::Fail; 4907 case 0: 4908 if (fieldFromInstruction(Insn, 4, 1)) 4909 return MCDisassembler::Fail; // UNDEFINED 4910 index = fieldFromInstruction(Insn, 5, 3); 4911 break; 4912 case 1: 4913 if (fieldFromInstruction(Insn, 5, 1)) 4914 return MCDisassembler::Fail; // UNDEFINED 4915 index = fieldFromInstruction(Insn, 6, 2); 4916 if (fieldFromInstruction(Insn, 4, 1)) 4917 align = 2; 4918 break; 4919 case 2: 4920 if (fieldFromInstruction(Insn, 6, 1)) 4921 return MCDisassembler::Fail; // UNDEFINED 4922 index = fieldFromInstruction(Insn, 7, 1); 4923 4924 switch (fieldFromInstruction(Insn, 4, 2)) { 4925 case 0 : 4926 align = 0; break; 4927 case 3: 4928 align = 4; break; 4929 default: 4930 return MCDisassembler::Fail; 4931 } 4932 break; 4933 } 4934 4935 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4936 return MCDisassembler::Fail; 4937 if (Rm != 0xF) { // Writeback 4938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4939 return MCDisassembler::Fail; 4940 } 4941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4942 return MCDisassembler::Fail; 4943 Inst.addOperand(MCOperand::createImm(align)); 4944 if (Rm != 0xF) { 4945 if (Rm != 0xD) { 4946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4947 return MCDisassembler::Fail; 4948 } else 4949 Inst.addOperand(MCOperand::createReg(0)); 4950 } 4951 4952 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4953 return MCDisassembler::Fail; 4954 Inst.addOperand(MCOperand::createImm(index)); 4955 4956 return S; 4957 } 4958 4959 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4960 uint64_t Address, const void *Decoder) { 4961 DecodeStatus S = MCDisassembler::Success; 4962 4963 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4964 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4965 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4966 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4967 unsigned size = fieldFromInstruction(Insn, 10, 2); 4968 4969 unsigned align = 0; 4970 unsigned index = 0; 4971 switch (size) { 4972 default: 4973 return MCDisassembler::Fail; 4974 case 0: 4975 if (fieldFromInstruction(Insn, 4, 1)) 4976 return MCDisassembler::Fail; // UNDEFINED 4977 index = fieldFromInstruction(Insn, 5, 3); 4978 break; 4979 case 1: 4980 if (fieldFromInstruction(Insn, 5, 1)) 4981 return MCDisassembler::Fail; // UNDEFINED 4982 index = fieldFromInstruction(Insn, 6, 2); 4983 if (fieldFromInstruction(Insn, 4, 1)) 4984 align = 2; 4985 break; 4986 case 2: 4987 if (fieldFromInstruction(Insn, 6, 1)) 4988 return MCDisassembler::Fail; // UNDEFINED 4989 index = fieldFromInstruction(Insn, 7, 1); 4990 4991 switch (fieldFromInstruction(Insn, 4, 2)) { 4992 case 0: 4993 align = 0; break; 4994 case 3: 4995 align = 4; break; 4996 default: 4997 return MCDisassembler::Fail; 4998 } 4999 break; 5000 } 5001 5002 if (Rm != 0xF) { // Writeback 5003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5004 return MCDisassembler::Fail; 5005 } 5006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5007 return MCDisassembler::Fail; 5008 Inst.addOperand(MCOperand::createImm(align)); 5009 if (Rm != 0xF) { 5010 if (Rm != 0xD) { 5011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5012 return MCDisassembler::Fail; 5013 } else 5014 Inst.addOperand(MCOperand::createReg(0)); 5015 } 5016 5017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5018 return MCDisassembler::Fail; 5019 Inst.addOperand(MCOperand::createImm(index)); 5020 5021 return S; 5022 } 5023 5024 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5025 uint64_t Address, const void *Decoder) { 5026 DecodeStatus S = MCDisassembler::Success; 5027 5028 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5029 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5030 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5031 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5032 unsigned size = fieldFromInstruction(Insn, 10, 2); 5033 5034 unsigned align = 0; 5035 unsigned index = 0; 5036 unsigned inc = 1; 5037 switch (size) { 5038 default: 5039 return MCDisassembler::Fail; 5040 case 0: 5041 index = fieldFromInstruction(Insn, 5, 3); 5042 if (fieldFromInstruction(Insn, 4, 1)) 5043 align = 2; 5044 break; 5045 case 1: 5046 index = fieldFromInstruction(Insn, 6, 2); 5047 if (fieldFromInstruction(Insn, 4, 1)) 5048 align = 4; 5049 if (fieldFromInstruction(Insn, 5, 1)) 5050 inc = 2; 5051 break; 5052 case 2: 5053 if (fieldFromInstruction(Insn, 5, 1)) 5054 return MCDisassembler::Fail; // UNDEFINED 5055 index = fieldFromInstruction(Insn, 7, 1); 5056 if (fieldFromInstruction(Insn, 4, 1) != 0) 5057 align = 8; 5058 if (fieldFromInstruction(Insn, 6, 1)) 5059 inc = 2; 5060 break; 5061 } 5062 5063 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5064 return MCDisassembler::Fail; 5065 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5066 return MCDisassembler::Fail; 5067 if (Rm != 0xF) { // Writeback 5068 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5069 return MCDisassembler::Fail; 5070 } 5071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5072 return MCDisassembler::Fail; 5073 Inst.addOperand(MCOperand::createImm(align)); 5074 if (Rm != 0xF) { 5075 if (Rm != 0xD) { 5076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5077 return MCDisassembler::Fail; 5078 } else 5079 Inst.addOperand(MCOperand::createReg(0)); 5080 } 5081 5082 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5083 return MCDisassembler::Fail; 5084 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5085 return MCDisassembler::Fail; 5086 Inst.addOperand(MCOperand::createImm(index)); 5087 5088 return S; 5089 } 5090 5091 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5092 uint64_t Address, const void *Decoder) { 5093 DecodeStatus S = MCDisassembler::Success; 5094 5095 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5096 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5097 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5098 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5099 unsigned size = fieldFromInstruction(Insn, 10, 2); 5100 5101 unsigned align = 0; 5102 unsigned index = 0; 5103 unsigned inc = 1; 5104 switch (size) { 5105 default: 5106 return MCDisassembler::Fail; 5107 case 0: 5108 index = fieldFromInstruction(Insn, 5, 3); 5109 if (fieldFromInstruction(Insn, 4, 1)) 5110 align = 2; 5111 break; 5112 case 1: 5113 index = fieldFromInstruction(Insn, 6, 2); 5114 if (fieldFromInstruction(Insn, 4, 1)) 5115 align = 4; 5116 if (fieldFromInstruction(Insn, 5, 1)) 5117 inc = 2; 5118 break; 5119 case 2: 5120 if (fieldFromInstruction(Insn, 5, 1)) 5121 return MCDisassembler::Fail; // UNDEFINED 5122 index = fieldFromInstruction(Insn, 7, 1); 5123 if (fieldFromInstruction(Insn, 4, 1) != 0) 5124 align = 8; 5125 if (fieldFromInstruction(Insn, 6, 1)) 5126 inc = 2; 5127 break; 5128 } 5129 5130 if (Rm != 0xF) { // Writeback 5131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5132 return MCDisassembler::Fail; 5133 } 5134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5135 return MCDisassembler::Fail; 5136 Inst.addOperand(MCOperand::createImm(align)); 5137 if (Rm != 0xF) { 5138 if (Rm != 0xD) { 5139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5140 return MCDisassembler::Fail; 5141 } else 5142 Inst.addOperand(MCOperand::createReg(0)); 5143 } 5144 5145 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5146 return MCDisassembler::Fail; 5147 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5148 return MCDisassembler::Fail; 5149 Inst.addOperand(MCOperand::createImm(index)); 5150 5151 return S; 5152 } 5153 5154 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5155 uint64_t Address, const void *Decoder) { 5156 DecodeStatus S = MCDisassembler::Success; 5157 5158 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5159 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5160 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5161 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5162 unsigned size = fieldFromInstruction(Insn, 10, 2); 5163 5164 unsigned align = 0; 5165 unsigned index = 0; 5166 unsigned inc = 1; 5167 switch (size) { 5168 default: 5169 return MCDisassembler::Fail; 5170 case 0: 5171 if (fieldFromInstruction(Insn, 4, 1)) 5172 return MCDisassembler::Fail; // UNDEFINED 5173 index = fieldFromInstruction(Insn, 5, 3); 5174 break; 5175 case 1: 5176 if (fieldFromInstruction(Insn, 4, 1)) 5177 return MCDisassembler::Fail; // UNDEFINED 5178 index = fieldFromInstruction(Insn, 6, 2); 5179 if (fieldFromInstruction(Insn, 5, 1)) 5180 inc = 2; 5181 break; 5182 case 2: 5183 if (fieldFromInstruction(Insn, 4, 2)) 5184 return MCDisassembler::Fail; // UNDEFINED 5185 index = fieldFromInstruction(Insn, 7, 1); 5186 if (fieldFromInstruction(Insn, 6, 1)) 5187 inc = 2; 5188 break; 5189 } 5190 5191 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5192 return MCDisassembler::Fail; 5193 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5194 return MCDisassembler::Fail; 5195 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5196 return MCDisassembler::Fail; 5197 5198 if (Rm != 0xF) { // Writeback 5199 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5200 return MCDisassembler::Fail; 5201 } 5202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5203 return MCDisassembler::Fail; 5204 Inst.addOperand(MCOperand::createImm(align)); 5205 if (Rm != 0xF) { 5206 if (Rm != 0xD) { 5207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5208 return MCDisassembler::Fail; 5209 } else 5210 Inst.addOperand(MCOperand::createReg(0)); 5211 } 5212 5213 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5214 return MCDisassembler::Fail; 5215 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5216 return MCDisassembler::Fail; 5217 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5218 return MCDisassembler::Fail; 5219 Inst.addOperand(MCOperand::createImm(index)); 5220 5221 return S; 5222 } 5223 5224 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5225 uint64_t Address, const void *Decoder) { 5226 DecodeStatus S = MCDisassembler::Success; 5227 5228 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5229 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5230 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5231 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5232 unsigned size = fieldFromInstruction(Insn, 10, 2); 5233 5234 unsigned align = 0; 5235 unsigned index = 0; 5236 unsigned inc = 1; 5237 switch (size) { 5238 default: 5239 return MCDisassembler::Fail; 5240 case 0: 5241 if (fieldFromInstruction(Insn, 4, 1)) 5242 return MCDisassembler::Fail; // UNDEFINED 5243 index = fieldFromInstruction(Insn, 5, 3); 5244 break; 5245 case 1: 5246 if (fieldFromInstruction(Insn, 4, 1)) 5247 return MCDisassembler::Fail; // UNDEFINED 5248 index = fieldFromInstruction(Insn, 6, 2); 5249 if (fieldFromInstruction(Insn, 5, 1)) 5250 inc = 2; 5251 break; 5252 case 2: 5253 if (fieldFromInstruction(Insn, 4, 2)) 5254 return MCDisassembler::Fail; // UNDEFINED 5255 index = fieldFromInstruction(Insn, 7, 1); 5256 if (fieldFromInstruction(Insn, 6, 1)) 5257 inc = 2; 5258 break; 5259 } 5260 5261 if (Rm != 0xF) { // Writeback 5262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5263 return MCDisassembler::Fail; 5264 } 5265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5266 return MCDisassembler::Fail; 5267 Inst.addOperand(MCOperand::createImm(align)); 5268 if (Rm != 0xF) { 5269 if (Rm != 0xD) { 5270 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5271 return MCDisassembler::Fail; 5272 } else 5273 Inst.addOperand(MCOperand::createReg(0)); 5274 } 5275 5276 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5277 return MCDisassembler::Fail; 5278 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5279 return MCDisassembler::Fail; 5280 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5281 return MCDisassembler::Fail; 5282 Inst.addOperand(MCOperand::createImm(index)); 5283 5284 return S; 5285 } 5286 5287 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5288 uint64_t Address, const void *Decoder) { 5289 DecodeStatus S = MCDisassembler::Success; 5290 5291 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5292 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5293 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5294 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5295 unsigned size = fieldFromInstruction(Insn, 10, 2); 5296 5297 unsigned align = 0; 5298 unsigned index = 0; 5299 unsigned inc = 1; 5300 switch (size) { 5301 default: 5302 return MCDisassembler::Fail; 5303 case 0: 5304 if (fieldFromInstruction(Insn, 4, 1)) 5305 align = 4; 5306 index = fieldFromInstruction(Insn, 5, 3); 5307 break; 5308 case 1: 5309 if (fieldFromInstruction(Insn, 4, 1)) 5310 align = 8; 5311 index = fieldFromInstruction(Insn, 6, 2); 5312 if (fieldFromInstruction(Insn, 5, 1)) 5313 inc = 2; 5314 break; 5315 case 2: 5316 switch (fieldFromInstruction(Insn, 4, 2)) { 5317 case 0: 5318 align = 0; break; 5319 case 3: 5320 return MCDisassembler::Fail; 5321 default: 5322 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5323 } 5324 5325 index = fieldFromInstruction(Insn, 7, 1); 5326 if (fieldFromInstruction(Insn, 6, 1)) 5327 inc = 2; 5328 break; 5329 } 5330 5331 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5332 return MCDisassembler::Fail; 5333 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5334 return MCDisassembler::Fail; 5335 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5336 return MCDisassembler::Fail; 5337 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5338 return MCDisassembler::Fail; 5339 5340 if (Rm != 0xF) { // Writeback 5341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5342 return MCDisassembler::Fail; 5343 } 5344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5345 return MCDisassembler::Fail; 5346 Inst.addOperand(MCOperand::createImm(align)); 5347 if (Rm != 0xF) { 5348 if (Rm != 0xD) { 5349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5350 return MCDisassembler::Fail; 5351 } else 5352 Inst.addOperand(MCOperand::createReg(0)); 5353 } 5354 5355 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5356 return MCDisassembler::Fail; 5357 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5358 return MCDisassembler::Fail; 5359 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5360 return MCDisassembler::Fail; 5361 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5362 return MCDisassembler::Fail; 5363 Inst.addOperand(MCOperand::createImm(index)); 5364 5365 return S; 5366 } 5367 5368 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5369 uint64_t Address, const void *Decoder) { 5370 DecodeStatus S = MCDisassembler::Success; 5371 5372 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5373 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5374 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5375 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5376 unsigned size = fieldFromInstruction(Insn, 10, 2); 5377 5378 unsigned align = 0; 5379 unsigned index = 0; 5380 unsigned inc = 1; 5381 switch (size) { 5382 default: 5383 return MCDisassembler::Fail; 5384 case 0: 5385 if (fieldFromInstruction(Insn, 4, 1)) 5386 align = 4; 5387 index = fieldFromInstruction(Insn, 5, 3); 5388 break; 5389 case 1: 5390 if (fieldFromInstruction(Insn, 4, 1)) 5391 align = 8; 5392 index = fieldFromInstruction(Insn, 6, 2); 5393 if (fieldFromInstruction(Insn, 5, 1)) 5394 inc = 2; 5395 break; 5396 case 2: 5397 switch (fieldFromInstruction(Insn, 4, 2)) { 5398 case 0: 5399 align = 0; break; 5400 case 3: 5401 return MCDisassembler::Fail; 5402 default: 5403 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5404 } 5405 5406 index = fieldFromInstruction(Insn, 7, 1); 5407 if (fieldFromInstruction(Insn, 6, 1)) 5408 inc = 2; 5409 break; 5410 } 5411 5412 if (Rm != 0xF) { // Writeback 5413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5414 return MCDisassembler::Fail; 5415 } 5416 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5417 return MCDisassembler::Fail; 5418 Inst.addOperand(MCOperand::createImm(align)); 5419 if (Rm != 0xF) { 5420 if (Rm != 0xD) { 5421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5422 return MCDisassembler::Fail; 5423 } else 5424 Inst.addOperand(MCOperand::createReg(0)); 5425 } 5426 5427 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5428 return MCDisassembler::Fail; 5429 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5430 return MCDisassembler::Fail; 5431 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5432 return MCDisassembler::Fail; 5433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5434 return MCDisassembler::Fail; 5435 Inst.addOperand(MCOperand::createImm(index)); 5436 5437 return S; 5438 } 5439 5440 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5441 uint64_t Address, const void *Decoder) { 5442 DecodeStatus S = MCDisassembler::Success; 5443 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5444 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5445 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5446 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5447 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5448 5449 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5450 S = MCDisassembler::SoftFail; 5451 5452 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5453 return MCDisassembler::Fail; 5454 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5455 return MCDisassembler::Fail; 5456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5457 return MCDisassembler::Fail; 5458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5459 return MCDisassembler::Fail; 5460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5461 return MCDisassembler::Fail; 5462 5463 return S; 5464 } 5465 5466 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5467 uint64_t Address, const void *Decoder) { 5468 DecodeStatus S = MCDisassembler::Success; 5469 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5470 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5471 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5472 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5473 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5474 5475 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5476 S = MCDisassembler::SoftFail; 5477 5478 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5479 return MCDisassembler::Fail; 5480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5481 return MCDisassembler::Fail; 5482 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5483 return MCDisassembler::Fail; 5484 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5485 return MCDisassembler::Fail; 5486 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5487 return MCDisassembler::Fail; 5488 5489 return S; 5490 } 5491 5492 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5493 uint64_t Address, const void *Decoder) { 5494 DecodeStatus S = MCDisassembler::Success; 5495 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5496 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5497 5498 if (pred == 0xF) { 5499 pred = 0xE; 5500 S = MCDisassembler::SoftFail; 5501 } 5502 5503 if (mask == 0x0) 5504 return MCDisassembler::Fail; 5505 5506 // IT masks are encoded as a sequence of replacement low-order bits 5507 // for the condition code. So if the low bit of the starting 5508 // condition code is 1, then we have to flip all the bits above the 5509 // terminating bit (which is the lowest 1 bit). 5510 if (pred & 1) { 5511 unsigned LowBit = mask & -mask; 5512 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5513 mask ^= BitsAboveLowBit; 5514 } 5515 5516 Inst.addOperand(MCOperand::createImm(pred)); 5517 Inst.addOperand(MCOperand::createImm(mask)); 5518 return S; 5519 } 5520 5521 static DecodeStatus 5522 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5523 uint64_t Address, const void *Decoder) { 5524 DecodeStatus S = MCDisassembler::Success; 5525 5526 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5527 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5528 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5529 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5530 unsigned W = fieldFromInstruction(Insn, 21, 1); 5531 unsigned U = fieldFromInstruction(Insn, 23, 1); 5532 unsigned P = fieldFromInstruction(Insn, 24, 1); 5533 bool writeback = (W == 1) | (P == 0); 5534 5535 addr |= (U << 8) | (Rn << 9); 5536 5537 if (writeback && (Rn == Rt || Rn == Rt2)) 5538 Check(S, MCDisassembler::SoftFail); 5539 if (Rt == Rt2) 5540 Check(S, MCDisassembler::SoftFail); 5541 5542 // Rt 5543 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5544 return MCDisassembler::Fail; 5545 // Rt2 5546 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5547 return MCDisassembler::Fail; 5548 // Writeback operand 5549 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5550 return MCDisassembler::Fail; 5551 // addr 5552 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5553 return MCDisassembler::Fail; 5554 5555 return S; 5556 } 5557 5558 static DecodeStatus 5559 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5560 uint64_t Address, const void *Decoder) { 5561 DecodeStatus S = MCDisassembler::Success; 5562 5563 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5564 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5565 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5566 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5567 unsigned W = fieldFromInstruction(Insn, 21, 1); 5568 unsigned U = fieldFromInstruction(Insn, 23, 1); 5569 unsigned P = fieldFromInstruction(Insn, 24, 1); 5570 bool writeback = (W == 1) | (P == 0); 5571 5572 addr |= (U << 8) | (Rn << 9); 5573 5574 if (writeback && (Rn == Rt || Rn == Rt2)) 5575 Check(S, MCDisassembler::SoftFail); 5576 5577 // Writeback operand 5578 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5579 return MCDisassembler::Fail; 5580 // Rt 5581 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5582 return MCDisassembler::Fail; 5583 // Rt2 5584 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5585 return MCDisassembler::Fail; 5586 // addr 5587 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5588 return MCDisassembler::Fail; 5589 5590 return S; 5591 } 5592 5593 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5594 uint64_t Address, const void *Decoder) { 5595 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5596 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5597 if (sign1 != sign2) return MCDisassembler::Fail; 5598 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5599 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5600 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5601 5602 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5603 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5604 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5605 // If sign, then it is decreasing the address. 5606 if (sign1) { 5607 // Following ARMv7 Architecture Manual, when the offset 5608 // is zero, it is decoded as a subw, not as a adr.w 5609 if (!Val) { 5610 Inst.setOpcode(ARM::t2SUBri12); 5611 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5612 } else 5613 Val = -Val; 5614 } 5615 Inst.addOperand(MCOperand::createImm(Val)); 5616 return S; 5617 } 5618 5619 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5620 uint64_t Address, 5621 const void *Decoder) { 5622 DecodeStatus S = MCDisassembler::Success; 5623 5624 // Shift of "asr #32" is not allowed in Thumb2 mode. 5625 if (Val == 0x20) S = MCDisassembler::Fail; 5626 Inst.addOperand(MCOperand::createImm(Val)); 5627 return S; 5628 } 5629 5630 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5631 uint64_t Address, const void *Decoder) { 5632 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5633 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5634 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5635 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5636 5637 if (pred == 0xF) 5638 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5639 5640 DecodeStatus S = MCDisassembler::Success; 5641 5642 if (Rt == Rn || Rn == Rt2) 5643 S = MCDisassembler::SoftFail; 5644 5645 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5646 return MCDisassembler::Fail; 5647 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5648 return MCDisassembler::Fail; 5649 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5650 return MCDisassembler::Fail; 5651 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5652 return MCDisassembler::Fail; 5653 5654 return S; 5655 } 5656 5657 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5658 uint64_t Address, const void *Decoder) { 5659 const FeatureBitset &featureBits = 5660 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5661 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5662 5663 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5664 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5665 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5666 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5667 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5668 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5669 unsigned op = fieldFromInstruction(Insn, 5, 1); 5670 5671 DecodeStatus S = MCDisassembler::Success; 5672 5673 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5674 if (!(imm & 0x38)) { 5675 if (cmode == 0xF) { 5676 if (op == 1) return MCDisassembler::Fail; 5677 Inst.setOpcode(ARM::VMOVv2f32); 5678 } 5679 if (hasFullFP16) { 5680 if (cmode == 0xE) { 5681 if (op == 1) { 5682 Inst.setOpcode(ARM::VMOVv1i64); 5683 } else { 5684 Inst.setOpcode(ARM::VMOVv8i8); 5685 } 5686 } 5687 if (cmode == 0xD) { 5688 if (op == 1) { 5689 Inst.setOpcode(ARM::VMVNv2i32); 5690 } else { 5691 Inst.setOpcode(ARM::VMOVv2i32); 5692 } 5693 } 5694 if (cmode == 0xC) { 5695 if (op == 1) { 5696 Inst.setOpcode(ARM::VMVNv2i32); 5697 } else { 5698 Inst.setOpcode(ARM::VMOVv2i32); 5699 } 5700 } 5701 } 5702 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5703 } 5704 5705 if (!(imm & 0x20)) return MCDisassembler::Fail; 5706 5707 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5708 return MCDisassembler::Fail; 5709 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5710 return MCDisassembler::Fail; 5711 Inst.addOperand(MCOperand::createImm(64 - imm)); 5712 5713 return S; 5714 } 5715 5716 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5717 uint64_t Address, const void *Decoder) { 5718 const FeatureBitset &featureBits = 5719 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5720 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5721 5722 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5723 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5724 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5725 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5726 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5727 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5728 unsigned op = fieldFromInstruction(Insn, 5, 1); 5729 5730 DecodeStatus S = MCDisassembler::Success; 5731 5732 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5733 if (!(imm & 0x38)) { 5734 if (cmode == 0xF) { 5735 if (op == 1) return MCDisassembler::Fail; 5736 Inst.setOpcode(ARM::VMOVv4f32); 5737 } 5738 if (hasFullFP16) { 5739 if (cmode == 0xE) { 5740 if (op == 1) { 5741 Inst.setOpcode(ARM::VMOVv2i64); 5742 } else { 5743 Inst.setOpcode(ARM::VMOVv16i8); 5744 } 5745 } 5746 if (cmode == 0xD) { 5747 if (op == 1) { 5748 Inst.setOpcode(ARM::VMVNv4i32); 5749 } else { 5750 Inst.setOpcode(ARM::VMOVv4i32); 5751 } 5752 } 5753 if (cmode == 0xC) { 5754 if (op == 1) { 5755 Inst.setOpcode(ARM::VMVNv4i32); 5756 } else { 5757 Inst.setOpcode(ARM::VMOVv4i32); 5758 } 5759 } 5760 } 5761 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5762 } 5763 5764 if (!(imm & 0x20)) return MCDisassembler::Fail; 5765 5766 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5767 return MCDisassembler::Fail; 5768 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5769 return MCDisassembler::Fail; 5770 Inst.addOperand(MCOperand::createImm(64 - imm)); 5771 5772 return S; 5773 } 5774 5775 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5776 unsigned Insn, 5777 uint64_t Address, 5778 const void *Decoder) { 5779 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5780 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5781 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5782 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5783 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5784 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5785 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5786 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5787 5788 DecodeStatus S = MCDisassembler::Success; 5789 5790 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5791 5792 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5793 return MCDisassembler::Fail; 5794 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5795 return MCDisassembler::Fail; 5796 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5797 return MCDisassembler::Fail; 5798 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5799 return MCDisassembler::Fail; 5800 // The lane index does not have any bits in the encoding, because it can only 5801 // be 0. 5802 Inst.addOperand(MCOperand::createImm(0)); 5803 Inst.addOperand(MCOperand::createImm(rotate)); 5804 5805 return S; 5806 } 5807 5808 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5809 uint64_t Address, const void *Decoder) { 5810 DecodeStatus S = MCDisassembler::Success; 5811 5812 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5813 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5814 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5815 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5816 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5817 5818 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5819 S = MCDisassembler::SoftFail; 5820 5821 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5822 return MCDisassembler::Fail; 5823 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5824 return MCDisassembler::Fail; 5825 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5826 return MCDisassembler::Fail; 5827 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5828 return MCDisassembler::Fail; 5829 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5830 return MCDisassembler::Fail; 5831 5832 return S; 5833 } 5834 5835 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5836 uint64_t Address, const void *Decoder) { 5837 DecodeStatus S = MCDisassembler::Success; 5838 5839 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5840 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5841 unsigned cop = fieldFromInstruction(Val, 8, 4); 5842 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5843 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5844 5845 if ((cop & ~0x1) == 0xa) 5846 return MCDisassembler::Fail; 5847 5848 if (Rt == Rt2) 5849 S = MCDisassembler::SoftFail; 5850 5851 // We have to check if the instruction is MRRC2 5852 // or MCRR2 when constructing the operands for 5853 // Inst. Reason is because MRRC2 stores to two 5854 // registers so it's tablegen desc has has two 5855 // outputs whereas MCRR doesn't store to any 5856 // registers so all of it's operands are listed 5857 // as inputs, therefore the operand order for 5858 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5859 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5860 5861 if (Inst.getOpcode() == ARM::MRRC2) { 5862 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5863 return MCDisassembler::Fail; 5864 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5865 return MCDisassembler::Fail; 5866 } 5867 Inst.addOperand(MCOperand::createImm(cop)); 5868 Inst.addOperand(MCOperand::createImm(opc1)); 5869 if (Inst.getOpcode() == ARM::MCRR2) { 5870 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5871 return MCDisassembler::Fail; 5872 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5873 return MCDisassembler::Fail; 5874 } 5875 Inst.addOperand(MCOperand::createImm(CRm)); 5876 5877 return S; 5878 } 5879 5880 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5881 uint64_t Address, 5882 const void *Decoder) { 5883 const FeatureBitset &featureBits = 5884 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5885 DecodeStatus S = MCDisassembler::Success; 5886 5887 // Add explicit operand for the destination sysreg, for cases where 5888 // we have to model it for code generation purposes. 5889 switch (Inst.getOpcode()) { 5890 case ARM::VMSR_FPSCR_NZCVQC: 5891 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5892 break; 5893 case ARM::VMSR_P0: 5894 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5895 break; 5896 } 5897 5898 if (Inst.getOpcode() != ARM::FMSTAT) { 5899 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5900 5901 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5902 if (Rt == 13 || Rt == 15) 5903 S = MCDisassembler::SoftFail; 5904 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5905 } else 5906 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5907 } 5908 5909 // Add explicit operand for the source sysreg, similarly to above. 5910 switch (Inst.getOpcode()) { 5911 case ARM::VMRS_FPSCR_NZCVQC: 5912 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5913 break; 5914 case ARM::VMRS_P0: 5915 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5916 break; 5917 } 5918 5919 if (featureBits[ARM::ModeThumb]) { 5920 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5921 Inst.addOperand(MCOperand::createReg(0)); 5922 } else { 5923 unsigned pred = fieldFromInstruction(Val, 28, 4); 5924 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5925 return MCDisassembler::Fail; 5926 } 5927 5928 return S; 5929 } 5930 5931 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5932 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5933 uint64_t Address, 5934 const void *Decoder) { 5935 DecodeStatus S = MCDisassembler::Success; 5936 if (Val == 0 && !zeroPermitted) 5937 S = MCDisassembler::Fail; 5938 5939 uint64_t DecVal; 5940 if (isSigned) 5941 DecVal = SignExtend32<size + 1>(Val << 1); 5942 else 5943 DecVal = (Val << 1); 5944 5945 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5946 Decoder)) 5947 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5948 return S; 5949 } 5950 5951 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5952 uint64_t Address, 5953 const void *Decoder) { 5954 5955 uint64_t LocImm = Inst.getOperand(0).getImm(); 5956 Val = LocImm + (2 << Val); 5957 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5958 Decoder)) 5959 Inst.addOperand(MCOperand::createImm(Val)); 5960 return MCDisassembler::Success; 5961 } 5962 5963 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5964 uint64_t Address, 5965 const void *Decoder) { 5966 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5967 return MCDisassembler::Fail; 5968 Inst.addOperand(MCOperand::createImm(Val)); 5969 return MCDisassembler::Success; 5970 } 5971 5972 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5973 const void *Decoder) { 5974 DecodeStatus S = MCDisassembler::Success; 5975 5976 if (Inst.getOpcode() == ARM::MVE_LCTP) 5977 return S; 5978 5979 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5980 fieldFromInstruction(Insn, 1, 10) << 1; 5981 switch (Inst.getOpcode()) { 5982 case ARM::t2LEUpdate: 5983 case ARM::MVE_LETP: 5984 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5985 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5986 LLVM_FALLTHROUGH; 5987 case ARM::t2LE: 5988 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 5989 Inst, Imm, Address, Decoder))) 5990 return MCDisassembler::Fail; 5991 break; 5992 case ARM::t2WLS: 5993 case ARM::MVE_WLSTP_8: 5994 case ARM::MVE_WLSTP_16: 5995 case ARM::MVE_WLSTP_32: 5996 case ARM::MVE_WLSTP_64: 5997 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5998 if (!Check(S, 5999 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6000 Address, Decoder)) || 6001 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6002 Inst, Imm, Address, Decoder))) 6003 return MCDisassembler::Fail; 6004 break; 6005 case ARM::t2DLS: 6006 case ARM::MVE_DLSTP_8: 6007 case ARM::MVE_DLSTP_16: 6008 case ARM::MVE_DLSTP_32: 6009 case ARM::MVE_DLSTP_64: 6010 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6011 if (Rn == 0xF) { 6012 // Enforce all the rest of the instruction bits in LCTP, which 6013 // won't have been reliably checked based on LCTP's own tablegen 6014 // record, because we came to this decode by a roundabout route. 6015 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6016 if ((Insn & ~SBZMask) != CanonicalLCTP) 6017 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6018 if (Insn != CanonicalLCTP) 6019 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6020 6021 Inst.setOpcode(ARM::MVE_LCTP); 6022 } else { 6023 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6024 if (!Check(S, DecoderGPRRegisterClass(Inst, 6025 fieldFromInstruction(Insn, 16, 4), 6026 Address, Decoder))) 6027 return MCDisassembler::Fail; 6028 } 6029 break; 6030 } 6031 return S; 6032 } 6033 6034 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6035 uint64_t Address, 6036 const void *Decoder) { 6037 DecodeStatus S = MCDisassembler::Success; 6038 6039 if (Val == 0) 6040 Val = 32; 6041 6042 Inst.addOperand(MCOperand::createImm(Val)); 6043 6044 return S; 6045 } 6046 6047 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6048 uint64_t Address, const void *Decoder) { 6049 if ((RegNo) + 1 > 11) 6050 return MCDisassembler::Fail; 6051 6052 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6053 Inst.addOperand(MCOperand::createReg(Register)); 6054 return MCDisassembler::Success; 6055 } 6056 6057 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6058 uint64_t Address, const void *Decoder) { 6059 if ((RegNo) > 14) 6060 return MCDisassembler::Fail; 6061 6062 unsigned Register = GPRDecoderTable[(RegNo)]; 6063 Inst.addOperand(MCOperand::createReg(Register)); 6064 return MCDisassembler::Success; 6065 } 6066 6067 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6068 const void *Decoder) { 6069 DecodeStatus S = MCDisassembler::Success; 6070 6071 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6072 Inst.addOperand(MCOperand::createReg(0)); 6073 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6074 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6075 (fieldFromInstruction(Insn, 12, 4) << 8) | 6076 (fieldFromInstruction(Insn, 22, 1) << 12); 6077 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6078 return MCDisassembler::Fail; 6079 } 6080 } else { 6081 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6082 (fieldFromInstruction(Insn, 22, 1) << 8) | 6083 (fieldFromInstruction(Insn, 12, 4) << 9); 6084 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6085 return MCDisassembler::Fail; 6086 } 6087 } 6088 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6089 6090 return S; 6091 } 6092 6093 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6094 uint64_t Address, 6095 const void *Decoder) { 6096 if (RegNo > 7) 6097 return MCDisassembler::Fail; 6098 6099 unsigned Register = QPRDecoderTable[RegNo]; 6100 Inst.addOperand(MCOperand::createReg(Register)); 6101 return MCDisassembler::Success; 6102 } 6103 6104 static const uint16_t QQPRDecoderTable[] = { 6105 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6106 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6107 }; 6108 6109 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6110 uint64_t Address, 6111 const void *Decoder) { 6112 if (RegNo > 6) 6113 return MCDisassembler::Fail; 6114 6115 unsigned Register = QQPRDecoderTable[RegNo]; 6116 Inst.addOperand(MCOperand::createReg(Register)); 6117 return MCDisassembler::Success; 6118 } 6119 6120 static const uint16_t QQQQPRDecoderTable[] = { 6121 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6122 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6123 }; 6124 6125 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6126 uint64_t Address, 6127 const void *Decoder) { 6128 if (RegNo > 4) 6129 return MCDisassembler::Fail; 6130 6131 unsigned Register = QQQQPRDecoderTable[RegNo]; 6132 Inst.addOperand(MCOperand::createReg(Register)); 6133 return MCDisassembler::Success; 6134 } 6135 6136 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6137 uint64_t Address, 6138 const void *Decoder) { 6139 DecodeStatus S = MCDisassembler::Success; 6140 6141 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6142 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6143 // 't' as 0 and finish with a 1. 6144 unsigned Imm = 0; 6145 // We always start with a 't'. 6146 unsigned CurBit = 0; 6147 for (int i = 3; i >= 0; --i) { 6148 // If the bit we are looking at is not the same as last one, invert the 6149 // CurBit, if it is the same leave it as is. 6150 CurBit ^= (Val >> i) & 1U; 6151 6152 // Encode the CurBit at the right place in the immediate. 6153 Imm |= (CurBit << i); 6154 6155 // If we are done, finish the encoding with a 1. 6156 if ((Val & ~(~0U << i)) == 0) { 6157 Imm |= 1U << i; 6158 break; 6159 } 6160 } 6161 6162 Inst.addOperand(MCOperand::createImm(Imm)); 6163 6164 return S; 6165 } 6166 6167 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6168 uint64_t Address, const void *Decoder) { 6169 // The vpred_r operand type includes an MQPR register field derived 6170 // from the encoding. But we don't actually want to add an operand 6171 // to the MCInst at this stage, because AddThumbPredicate will do it 6172 // later, and will infer the register number from the TIED_TO 6173 // constraint. So this is a deliberately empty decoder method that 6174 // will inhibit the auto-generated disassembly code from adding an 6175 // operand at all. 6176 return MCDisassembler::Success; 6177 } 6178 6179 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6180 unsigned Val, 6181 uint64_t Address, 6182 const void *Decoder) { 6183 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6184 return MCDisassembler::Success; 6185 } 6186 6187 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6188 unsigned Val, 6189 uint64_t Address, 6190 const void *Decoder) { 6191 unsigned Code; 6192 switch (Val & 0x3) { 6193 case 0: 6194 Code = ARMCC::GE; 6195 break; 6196 case 1: 6197 Code = ARMCC::LT; 6198 break; 6199 case 2: 6200 Code = ARMCC::GT; 6201 break; 6202 case 3: 6203 Code = ARMCC::LE; 6204 break; 6205 } 6206 Inst.addOperand(MCOperand::createImm(Code)); 6207 return MCDisassembler::Success; 6208 } 6209 6210 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6211 unsigned Val, 6212 uint64_t Address, 6213 const void *Decoder) { 6214 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6215 return MCDisassembler::Success; 6216 } 6217 6218 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6219 uint64_t Address, 6220 const void *Decoder) { 6221 unsigned Code; 6222 switch (Val) { 6223 default: 6224 return MCDisassembler::Fail; 6225 case 0: 6226 Code = ARMCC::EQ; 6227 break; 6228 case 1: 6229 Code = ARMCC::NE; 6230 break; 6231 case 4: 6232 Code = ARMCC::GE; 6233 break; 6234 case 5: 6235 Code = ARMCC::LT; 6236 break; 6237 case 6: 6238 Code = ARMCC::GT; 6239 break; 6240 case 7: 6241 Code = ARMCC::LE; 6242 break; 6243 } 6244 6245 Inst.addOperand(MCOperand::createImm(Code)); 6246 return MCDisassembler::Success; 6247 } 6248 6249 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6250 uint64_t Address, const void *Decoder) { 6251 DecodeStatus S = MCDisassembler::Success; 6252 6253 unsigned DecodedVal = 64 - Val; 6254 6255 switch (Inst.getOpcode()) { 6256 case ARM::MVE_VCVTf16s16_fix: 6257 case ARM::MVE_VCVTs16f16_fix: 6258 case ARM::MVE_VCVTf16u16_fix: 6259 case ARM::MVE_VCVTu16f16_fix: 6260 if (DecodedVal > 16) 6261 return MCDisassembler::Fail; 6262 break; 6263 case ARM::MVE_VCVTf32s32_fix: 6264 case ARM::MVE_VCVTs32f32_fix: 6265 case ARM::MVE_VCVTf32u32_fix: 6266 case ARM::MVE_VCVTu32f32_fix: 6267 if (DecodedVal > 32) 6268 return MCDisassembler::Fail; 6269 break; 6270 } 6271 6272 Inst.addOperand(MCOperand::createImm(64 - Val)); 6273 6274 return S; 6275 } 6276 6277 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6278 switch (Opcode) { 6279 case ARM::VSTR_P0_off: 6280 case ARM::VSTR_P0_pre: 6281 case ARM::VSTR_P0_post: 6282 case ARM::VLDR_P0_off: 6283 case ARM::VLDR_P0_pre: 6284 case ARM::VLDR_P0_post: 6285 return ARM::P0; 6286 default: 6287 return 0; 6288 } 6289 } 6290 6291 template<bool Writeback> 6292 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6293 uint64_t Address, 6294 const void *Decoder) { 6295 switch (Inst.getOpcode()) { 6296 case ARM::VSTR_FPSCR_pre: 6297 case ARM::VSTR_FPSCR_NZCVQC_pre: 6298 case ARM::VLDR_FPSCR_pre: 6299 case ARM::VLDR_FPSCR_NZCVQC_pre: 6300 case ARM::VSTR_FPSCR_off: 6301 case ARM::VSTR_FPSCR_NZCVQC_off: 6302 case ARM::VLDR_FPSCR_off: 6303 case ARM::VLDR_FPSCR_NZCVQC_off: 6304 case ARM::VSTR_FPSCR_post: 6305 case ARM::VSTR_FPSCR_NZCVQC_post: 6306 case ARM::VLDR_FPSCR_post: 6307 case ARM::VLDR_FPSCR_NZCVQC_post: 6308 const FeatureBitset &featureBits = 6309 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6310 6311 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6312 return MCDisassembler::Fail; 6313 } 6314 6315 DecodeStatus S = MCDisassembler::Success; 6316 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6317 Inst.addOperand(MCOperand::createReg(Sysreg)); 6318 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6319 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6320 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6321 6322 if (Writeback) { 6323 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6324 return MCDisassembler::Fail; 6325 } 6326 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6327 return MCDisassembler::Fail; 6328 6329 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6330 Inst.addOperand(MCOperand::createReg(0)); 6331 6332 return S; 6333 } 6334 6335 static inline DecodeStatus DecodeMVE_MEM_pre( 6336 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6337 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6338 DecodeStatus S = MCDisassembler::Success; 6339 6340 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6341 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6342 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6343 6344 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6345 return MCDisassembler::Fail; 6346 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6347 return MCDisassembler::Fail; 6348 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6349 return MCDisassembler::Fail; 6350 6351 return S; 6352 } 6353 6354 template <int shift> 6355 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6356 uint64_t Address, const void *Decoder) { 6357 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6358 fieldFromInstruction(Val, 16, 3), 6359 DecodetGPRRegisterClass, 6360 DecodeTAddrModeImm7<shift>); 6361 } 6362 6363 template <int shift> 6364 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6365 uint64_t Address, const void *Decoder) { 6366 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6367 fieldFromInstruction(Val, 16, 4), 6368 DecoderGPRRegisterClass, 6369 DecodeT2AddrModeImm7<shift,1>); 6370 } 6371 6372 template <int shift> 6373 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6374 uint64_t Address, const void *Decoder) { 6375 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6376 fieldFromInstruction(Val, 17, 3), 6377 DecodeMQPRRegisterClass, 6378 DecodeMveAddrModeQ<shift>); 6379 } 6380 6381 template<unsigned MinLog, unsigned MaxLog> 6382 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6383 uint64_t Address, 6384 const void *Decoder) { 6385 DecodeStatus S = MCDisassembler::Success; 6386 6387 if (Val < MinLog || Val > MaxLog) 6388 return MCDisassembler::Fail; 6389 6390 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6391 return S; 6392 } 6393 6394 template<unsigned start> 6395 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6396 uint64_t Address, 6397 const void *Decoder) { 6398 DecodeStatus S = MCDisassembler::Success; 6399 6400 Inst.addOperand(MCOperand::createImm(start + Val)); 6401 6402 return S; 6403 } 6404 6405 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6406 uint64_t Address, const void *Decoder) { 6407 DecodeStatus S = MCDisassembler::Success; 6408 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6409 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6410 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6411 fieldFromInstruction(Insn, 13, 3)); 6412 unsigned index = fieldFromInstruction(Insn, 4, 1); 6413 6414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6415 return MCDisassembler::Fail; 6416 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6417 return MCDisassembler::Fail; 6418 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6419 return MCDisassembler::Fail; 6420 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6421 return MCDisassembler::Fail; 6422 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6423 return MCDisassembler::Fail; 6424 6425 return S; 6426 } 6427 6428 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6429 uint64_t Address, const void *Decoder) { 6430 DecodeStatus S = MCDisassembler::Success; 6431 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6432 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6433 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6434 fieldFromInstruction(Insn, 13, 3)); 6435 unsigned index = fieldFromInstruction(Insn, 4, 1); 6436 6437 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6438 return MCDisassembler::Fail; 6439 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6440 return MCDisassembler::Fail; 6441 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6442 return MCDisassembler::Fail; 6443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6444 return MCDisassembler::Fail; 6445 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6446 return MCDisassembler::Fail; 6447 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6448 return MCDisassembler::Fail; 6449 6450 return S; 6451 } 6452 6453 static DecodeStatus DecodeMVEOverlappingLongShift( 6454 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6455 DecodeStatus S = MCDisassembler::Success; 6456 6457 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6458 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6459 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6460 6461 if (RdaHi == 14) { 6462 // This value of RdaHi (really indicating pc, because RdaHi has to 6463 // be an odd-numbered register, so the low bit will be set by the 6464 // decode function below) indicates that we must decode as SQRSHR 6465 // or UQRSHL, which both have a single Rda register field with all 6466 // four bits. 6467 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6468 6469 switch (Inst.getOpcode()) { 6470 case ARM::MVE_ASRLr: 6471 case ARM::MVE_SQRSHRL: 6472 Inst.setOpcode(ARM::MVE_SQRSHR); 6473 break; 6474 case ARM::MVE_LSLLr: 6475 case ARM::MVE_UQRSHLL: 6476 Inst.setOpcode(ARM::MVE_UQRSHL); 6477 break; 6478 default: 6479 llvm_unreachable("Unexpected starting opcode!"); 6480 } 6481 6482 // Rda as output parameter 6483 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6484 return MCDisassembler::Fail; 6485 6486 // Rda again as input parameter 6487 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6488 return MCDisassembler::Fail; 6489 6490 // Rm, the amount to shift by 6491 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6492 return MCDisassembler::Fail; 6493 6494 if (fieldFromInstruction (Insn, 6, 3) != 4) 6495 return MCDisassembler::SoftFail; 6496 6497 if (Rda == Rm) 6498 return MCDisassembler::SoftFail; 6499 6500 return S; 6501 } 6502 6503 // Otherwise, we decode as whichever opcode our caller has already 6504 // put into Inst. Those all look the same: 6505 6506 // RdaLo,RdaHi as output parameters 6507 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6508 return MCDisassembler::Fail; 6509 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6510 return MCDisassembler::Fail; 6511 6512 // RdaLo,RdaHi again as input parameters 6513 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6514 return MCDisassembler::Fail; 6515 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6516 return MCDisassembler::Fail; 6517 6518 // Rm, the amount to shift by 6519 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6520 return MCDisassembler::Fail; 6521 6522 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6523 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6524 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6525 // Saturate, the bit position for saturation 6526 Inst.addOperand(MCOperand::createImm(Saturate)); 6527 } 6528 6529 return S; 6530 } 6531 6532 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6533 const void *Decoder) { 6534 DecodeStatus S = MCDisassembler::Success; 6535 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6536 fieldFromInstruction(Insn, 13, 3)); 6537 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6538 fieldFromInstruction(Insn, 1, 3)); 6539 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6540 6541 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6542 return MCDisassembler::Fail; 6543 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6544 return MCDisassembler::Fail; 6545 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6546 return MCDisassembler::Fail; 6547 6548 return S; 6549 } 6550 6551 template<bool scalar, OperandDecoder predicate_decoder> 6552 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6553 const void *Decoder) { 6554 DecodeStatus S = MCDisassembler::Success; 6555 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6556 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6557 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6558 return MCDisassembler::Fail; 6559 6560 unsigned fc; 6561 6562 if (scalar) { 6563 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6564 fieldFromInstruction(Insn, 7, 1) | 6565 fieldFromInstruction(Insn, 5, 1) << 1; 6566 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6567 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6568 return MCDisassembler::Fail; 6569 } else { 6570 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6571 fieldFromInstruction(Insn, 7, 1) | 6572 fieldFromInstruction(Insn, 0, 1) << 1; 6573 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6574 fieldFromInstruction(Insn, 1, 3); 6575 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6576 return MCDisassembler::Fail; 6577 } 6578 6579 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6580 return MCDisassembler::Fail; 6581 6582 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6583 Inst.addOperand(MCOperand::createReg(0)); 6584 Inst.addOperand(MCOperand::createImm(0)); 6585 6586 return S; 6587 } 6588 6589 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6590 const void *Decoder) { 6591 DecodeStatus S = MCDisassembler::Success; 6592 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6593 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6594 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6595 return MCDisassembler::Fail; 6596 return S; 6597 } 6598 6599 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6600 const void *Decoder) { 6601 DecodeStatus S = MCDisassembler::Success; 6602 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6603 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6604 return S; 6605 } 6606 6607 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6608 uint64_t Address, const void *Decoder) { 6609 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6610 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6611 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6612 fieldFromInstruction(Insn, 12, 3) << 8 | 6613 fieldFromInstruction(Insn, 0, 8); 6614 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6615 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6616 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6617 unsigned S = fieldFromInstruction(Insn, 20, 1); 6618 if (sign1 != sign2) 6619 return MCDisassembler::Fail; 6620 6621 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6622 DecodeStatus DS = MCDisassembler::Success; 6623 if ((!Check(DS, 6624 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6625 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6626 return MCDisassembler::Fail; 6627 if (TypeT3) { 6628 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6629 S = 0; 6630 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6631 } else { 6632 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6633 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6634 return MCDisassembler::Fail; 6635 } 6636 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6637 return MCDisassembler::Fail; 6638 6639 Inst.addOperand(MCOperand::createReg(0)); // pred 6640 6641 return DS; 6642 } 6643