1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 143 private: 144 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 145 ArrayRef<uint8_t> Bytes, uint64_t Address, 146 raw_ostream &VStream, 147 raw_ostream &CStream) const; 148 149 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 150 ArrayRef<uint8_t> Bytes, uint64_t Address, 151 raw_ostream &VStream, 152 raw_ostream &CStream) const; 153 154 mutable ITStatus ITBlock; 155 mutable VPTStatus VPTBlock; 156 157 DecodeStatus AddThumbPredicate(MCInst&) const; 158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 159 }; 160 161 } // end anonymous namespace 162 163 static bool Check(DecodeStatus &Out, DecodeStatus In) { 164 switch (In) { 165 case MCDisassembler::Success: 166 // Out stays the same. 167 return true; 168 case MCDisassembler::SoftFail: 169 Out = In; 170 return true; 171 case MCDisassembler::Fail: 172 Out = In; 173 return false; 174 } 175 llvm_unreachable("Invalid DecodeStatus!"); 176 } 177 178 // Forward declare these because the autogenerated code will reference them. 179 // Definitions are further down. 180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, 209 const void *Decoder); 210 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Address, 223 const void *Decoder); 224 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 235 unsigned RegNo, uint64_t Address, 236 const void *Decoder); 237 238 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 249 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 254 unsigned Insn, 255 uint64_t Address, 256 const void *Decoder); 257 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 266 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 267 unsigned Insn, 268 uint64_t Adddress, 269 const void *Decoder); 270 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 template<int shift> 343 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 396 unsigned Val, 397 uint64_t Address, 398 const void *Decoder); 399 400 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 401 uint64_t Address, const void *Decoder); 402 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 403 uint64_t Address, const void *Decoder); 404 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 417 uint64_t Address, const void *Decoder); 418 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 421 uint64_t Address, const void* Decoder); 422 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 423 uint64_t Address, const void* Decoder); 424 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 425 uint64_t Address, const void* Decoder); 426 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void* Decoder); 428 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 429 uint64_t Address, const void *Decoder); 430 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 431 uint64_t Address, const void *Decoder); 432 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 433 uint64_t Address, const void *Decoder); 434 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 435 uint64_t Address, 436 const void *Decoder); 437 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 438 uint64_t Address, const void *Decoder); 439 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 440 uint64_t Address, const void *Decoder); 441 template<int shift> 442 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 443 uint64_t Address, const void *Decoder); 444 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 template<int shift> 447 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 448 uint64_t Address, const void *Decoder); 449 template<int shift, int WriteBack> 450 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 451 uint64_t Address, const void *Decoder); 452 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 453 uint64_t Address, const void *Decoder); 454 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 457 uint64_t Address, const void *Decoder); 458 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 461 uint64_t Address, const void *Decoder); 462 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 473 uint64_t Address, const void *Decoder); 474 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 475 uint64_t Address, const void *Decoder); 476 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 477 uint64_t Address, const void *Decoder); 478 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 479 uint64_t Address, const void *Decoder); 480 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 481 uint64_t Address, const void *Decoder); 482 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 483 uint64_t Address, const void *Decoder); 484 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 487 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 488 uint64_t Address, const void *Decoder); 489 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 490 uint64_t Address, const void *Decoder); 491 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 492 uint64_t Address, const void *Decoder); 493 494 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 495 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 496 uint64_t Address, const void *Decoder); 497 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 498 uint64_t Address, 499 const void *Decoder); 500 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 501 uint64_t Address, 502 const void *Decoder); 503 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 504 const void *Decoder); 505 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 506 uint64_t Address, 507 const void *Decoder); 508 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 509 const void *Decoder); 510 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 511 uint64_t Address, const void *Decoder); 512 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 513 uint64_t Address, const void *Decoder); 514 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, 516 const void *Decoder); 517 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 518 uint64_t Address, 519 const void *Decoder); 520 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 521 uint64_t Address, 522 const void *Decoder); 523 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 524 unsigned Val, 525 uint64_t Address, 526 const void *Decoder); 527 template<bool Writeback> 528 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 529 uint64_t Address, 530 const void *Decoder); 531 template<int shift> 532 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 533 uint64_t Address, const void *Decoder); 534 template<int shift> 535 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 536 uint64_t Address, const void *Decoder); 537 template<int shift> 538 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 539 uint64_t Address, const void *Decoder); 540 template<unsigned MinLog, unsigned MaxLog> 541 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 542 uint64_t Address, 543 const void *Decoder); 544 template <int shift> 545 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 546 uint64_t Address, 547 const void *Decoder); 548 template<unsigned start> 549 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 550 uint64_t Address, 551 const void *Decoder); 552 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 553 uint64_t Address, 554 const void *Decoder); 555 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 556 uint64_t Address, 557 const void *Decoder); 558 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 559 uint64_t Address, const void *Decoder); 560 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 561 uint64_t Address, const void *Decoder); 562 template<bool scalar, OperandDecoder predicate_decoder> 563 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 564 uint64_t Address, const void *Decoder); 565 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 566 uint64_t Address, const void *Decoder); 567 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 568 uint64_t Address, const void *Decoder); 569 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 570 uint64_t Address, 571 const void *Decoder); 572 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 573 uint64_t Address, const void *Decoder); 574 575 #include "ARMGenDisassemblerTables.inc" 576 577 static MCDisassembler *createARMDisassembler(const Target &T, 578 const MCSubtargetInfo &STI, 579 MCContext &Ctx) { 580 return new ARMDisassembler(STI, Ctx); 581 } 582 583 // Post-decoding checks 584 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 585 uint64_t Address, raw_ostream &OS, 586 raw_ostream &CS, 587 uint32_t Insn, 588 DecodeStatus Result) { 589 switch (MI.getOpcode()) { 590 case ARM::HVC: { 591 // HVC is undefined if condition = 0xf otherwise upredictable 592 // if condition != 0xe 593 uint32_t Cond = (Insn >> 28) & 0xF; 594 if (Cond == 0xF) 595 return MCDisassembler::Fail; 596 if (Cond != 0xE) 597 return MCDisassembler::SoftFail; 598 return Result; 599 } 600 case ARM::t2ADDri: 601 case ARM::t2ADDri12: 602 case ARM::t2ADDrr: 603 case ARM::t2ADDrs: 604 case ARM::t2SUBri: 605 case ARM::t2SUBri12: 606 case ARM::t2SUBrr: 607 case ARM::t2SUBrs: 608 if (MI.getOperand(0).getReg() == ARM::SP && 609 MI.getOperand(1).getReg() != ARM::SP) 610 return MCDisassembler::SoftFail; 611 return Result; 612 default: return Result; 613 } 614 } 615 616 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 617 ArrayRef<uint8_t> Bytes, 618 uint64_t Address, raw_ostream &OS, 619 raw_ostream &CS) const { 620 if (STI.getFeatureBits()[ARM::ModeThumb]) 621 return getThumbInstruction(MI, Size, Bytes, Address, OS, CS); 622 return getARMInstruction(MI, Size, Bytes, Address, OS, CS); 623 } 624 625 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 626 ArrayRef<uint8_t> Bytes, 627 uint64_t Address, 628 raw_ostream &OS, 629 raw_ostream &CS) const { 630 CommentStream = &CS; 631 632 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 633 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 634 "mode!"); 635 636 // We want to read exactly 4 bytes of data. 637 if (Bytes.size() < 4) { 638 Size = 0; 639 return MCDisassembler::Fail; 640 } 641 642 // Encoded as a small-endian 32-bit word in the stream. 643 uint32_t Insn = 644 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 645 646 // Calling the auto-generated decoder function. 647 DecodeStatus Result = 648 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 649 if (Result != MCDisassembler::Fail) { 650 Size = 4; 651 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 652 } 653 654 struct DecodeTable { 655 const uint8_t *P; 656 bool DecodePred; 657 }; 658 659 const DecodeTable Tables[] = { 660 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 661 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 662 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 663 {DecoderTablev8Crypto32, false}, 664 }; 665 666 for (auto Table : Tables) { 667 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 668 if (Result != MCDisassembler::Fail) { 669 Size = 4; 670 // Add a fake predicate operand, because we share these instruction 671 // definitions with Thumb2 where these instructions are predicable. 672 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 673 return MCDisassembler::Fail; 674 return Result; 675 } 676 } 677 678 Result = 679 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 680 if (Result != MCDisassembler::Fail) { 681 Size = 4; 682 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 683 } 684 685 Size = 4; 686 return MCDisassembler::Fail; 687 } 688 689 namespace llvm { 690 691 extern const MCInstrDesc ARMInsts[]; 692 693 } // end namespace llvm 694 695 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 696 /// immediate Value in the MCInst. The immediate Value has had any PC 697 /// adjustment made by the caller. If the instruction is a branch instruction 698 /// then isBranch is true, else false. If the getOpInfo() function was set as 699 /// part of the setupForSymbolicDisassembly() call then that function is called 700 /// to get any symbolic information at the Address for this instruction. If 701 /// that returns non-zero then the symbolic information it returns is used to 702 /// create an MCExpr and that is added as an operand to the MCInst. If 703 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 704 /// Value is done and if a symbol is found an MCExpr is created with that, else 705 /// an MCExpr with Value is created. This function returns true if it adds an 706 /// operand to the MCInst and false otherwise. 707 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 708 bool isBranch, uint64_t InstSize, 709 MCInst &MI, const void *Decoder) { 710 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 711 // FIXME: Does it make sense for value to be negative? 712 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 713 /* Offset */ 0, InstSize); 714 } 715 716 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 717 /// referenced by a load instruction with the base register that is the Pc. 718 /// These can often be values in a literal pool near the Address of the 719 /// instruction. The Address of the instruction and its immediate Value are 720 /// used as a possible literal pool entry. The SymbolLookUp call back will 721 /// return the name of a symbol referenced by the literal pool's entry if 722 /// the referenced address is that of a symbol. Or it will return a pointer to 723 /// a literal 'C' string if the referenced address of the literal pool's entry 724 /// is an address into a section with 'C' string literals. 725 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 726 const void *Decoder) { 727 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 728 Dis->tryAddingPcLoadReferenceComment(Value, Address); 729 } 730 731 // Thumb1 instructions don't have explicit S bits. Rather, they 732 // implicitly set CPSR. Since it's not represented in the encoding, the 733 // auto-generated decoder won't inject the CPSR operand. We need to fix 734 // that as a post-pass. 735 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 736 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 737 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 738 MCInst::iterator I = MI.begin(); 739 for (unsigned i = 0; i < NumOps; ++i, ++I) { 740 if (I == MI.end()) break; 741 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 742 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 743 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 744 return; 745 } 746 } 747 748 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 749 } 750 751 static bool isVectorPredicable(unsigned Opcode) { 752 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 753 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 754 for (unsigned i = 0; i < NumOps; ++i) { 755 if (ARM::isVpred(OpInfo[i].OperandType)) 756 return true; 757 } 758 return false; 759 } 760 761 // Most Thumb instructions don't have explicit predicates in the 762 // encoding, but rather get their predicates from IT context. We need 763 // to fix up the predicate operands using this context information as a 764 // post-pass. 765 MCDisassembler::DecodeStatus 766 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 767 MCDisassembler::DecodeStatus S = Success; 768 769 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 770 771 // A few instructions actually have predicates encoded in them. Don't 772 // try to overwrite it if we're seeing one of those. 773 switch (MI.getOpcode()) { 774 case ARM::tBcc: 775 case ARM::t2Bcc: 776 case ARM::tCBZ: 777 case ARM::tCBNZ: 778 case ARM::tCPS: 779 case ARM::t2CPS3p: 780 case ARM::t2CPS2p: 781 case ARM::t2CPS1p: 782 case ARM::t2CSEL: 783 case ARM::t2CSINC: 784 case ARM::t2CSINV: 785 case ARM::t2CSNEG: 786 case ARM::tMOVSr: 787 case ARM::tSETEND: 788 // Some instructions (mostly conditional branches) are not 789 // allowed in IT blocks. 790 if (ITBlock.instrInITBlock()) 791 S = SoftFail; 792 else 793 return Success; 794 break; 795 case ARM::t2HINT: 796 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 797 S = SoftFail; 798 break; 799 case ARM::tB: 800 case ARM::t2B: 801 case ARM::t2TBB: 802 case ARM::t2TBH: 803 // Some instructions (mostly unconditional branches) can 804 // only appears at the end of, or outside of, an IT. 805 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 806 S = SoftFail; 807 break; 808 default: 809 break; 810 } 811 812 // Warn on non-VPT predicable instruction in a VPT block and a VPT 813 // predicable instruction in an IT block 814 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 815 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 816 S = SoftFail; 817 818 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 819 // assume a predicate of AL. 820 unsigned CC = ARMCC::AL; 821 unsigned VCC = ARMVCC::None; 822 if (ITBlock.instrInITBlock()) { 823 CC = ITBlock.getITCC(); 824 ITBlock.advanceITState(); 825 } else if (VPTBlock.instrInVPTBlock()) { 826 VCC = VPTBlock.getVPTPred(); 827 VPTBlock.advanceVPTState(); 828 } 829 830 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 831 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 832 833 MCInst::iterator CCI = MI.begin(); 834 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 835 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 836 } 837 838 if (ARMInsts[MI.getOpcode()].isPredicable()) { 839 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 840 ++CCI; 841 if (CC == ARMCC::AL) 842 MI.insert(CCI, MCOperand::createReg(0)); 843 else 844 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 845 } else if (CC != ARMCC::AL) { 846 Check(S, SoftFail); 847 } 848 849 MCInst::iterator VCCI = MI.begin(); 850 unsigned VCCPos; 851 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 852 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 853 } 854 855 if (isVectorPredicable(MI.getOpcode())) { 856 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 857 ++VCCI; 858 if (VCC == ARMVCC::None) 859 MI.insert(VCCI, MCOperand::createReg(0)); 860 else 861 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 862 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 863 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 864 VCCPos + 2, MCOI::TIED_TO); 865 assert(TiedOp >= 0 && 866 "Inactive register in vpred_r is not tied to an output!"); 867 MI.insert(VCCI, MI.getOperand(TiedOp)); 868 } 869 } else if (VCC != ARMVCC::None) { 870 Check(S, SoftFail); 871 } 872 873 return S; 874 } 875 876 // Thumb VFP instructions are a special case. Because we share their 877 // encodings between ARM and Thumb modes, and they are predicable in ARM 878 // mode, the auto-generated decoder will give them an (incorrect) 879 // predicate operand. We need to rewrite these operands based on the IT 880 // context as a post-pass. 881 void ARMDisassembler::UpdateThumbVFPPredicate( 882 DecodeStatus &S, MCInst &MI) const { 883 unsigned CC; 884 CC = ITBlock.getITCC(); 885 if (CC == 0xF) 886 CC = ARMCC::AL; 887 if (ITBlock.instrInITBlock()) 888 ITBlock.advanceITState(); 889 else if (VPTBlock.instrInVPTBlock()) { 890 CC = VPTBlock.getVPTPred(); 891 VPTBlock.advanceVPTState(); 892 } 893 894 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 895 MCInst::iterator I = MI.begin(); 896 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 897 for (unsigned i = 0; i < NumOps; ++i, ++I) { 898 if (OpInfo[i].isPredicate() ) { 899 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 900 Check(S, SoftFail); 901 I->setImm(CC); 902 ++I; 903 if (CC == ARMCC::AL) 904 I->setReg(0); 905 else 906 I->setReg(ARM::CPSR); 907 return; 908 } 909 } 910 } 911 912 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 913 ArrayRef<uint8_t> Bytes, 914 uint64_t Address, 915 raw_ostream &OS, 916 raw_ostream &CS) const { 917 CommentStream = &CS; 918 919 assert(STI.getFeatureBits()[ARM::ModeThumb] && 920 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 921 922 // We want to read exactly 2 bytes of data. 923 if (Bytes.size() < 2) { 924 Size = 0; 925 return MCDisassembler::Fail; 926 } 927 928 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 929 DecodeStatus Result = 930 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 931 if (Result != MCDisassembler::Fail) { 932 Size = 2; 933 Check(Result, AddThumbPredicate(MI)); 934 return Result; 935 } 936 937 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 938 STI); 939 if (Result) { 940 Size = 2; 941 bool InITBlock = ITBlock.instrInITBlock(); 942 Check(Result, AddThumbPredicate(MI)); 943 AddThumb1SBit(MI, InITBlock); 944 return Result; 945 } 946 947 Result = 948 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 949 if (Result != MCDisassembler::Fail) { 950 Size = 2; 951 952 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 953 // the Thumb predicate. 954 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 955 Result = MCDisassembler::SoftFail; 956 957 Check(Result, AddThumbPredicate(MI)); 958 959 // If we find an IT instruction, we need to parse its condition 960 // code and mask operands so that we can apply them correctly 961 // to the subsequent instructions. 962 if (MI.getOpcode() == ARM::t2IT) { 963 unsigned Firstcond = MI.getOperand(0).getImm(); 964 unsigned Mask = MI.getOperand(1).getImm(); 965 ITBlock.setITState(Firstcond, Mask); 966 967 // An IT instruction that would give a 'NV' predicate is unpredictable. 968 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 969 CS << "unpredictable IT predicate sequence"; 970 } 971 972 return Result; 973 } 974 975 // We want to read exactly 4 bytes of data. 976 if (Bytes.size() < 4) { 977 Size = 0; 978 return MCDisassembler::Fail; 979 } 980 981 uint32_t Insn32 = 982 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 983 984 Result = 985 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 986 if (Result != MCDisassembler::Fail) { 987 Size = 4; 988 989 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 990 // the VPT predicate. 991 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 992 Result = MCDisassembler::SoftFail; 993 994 Check(Result, AddThumbPredicate(MI)); 995 996 if (isVPTOpcode(MI.getOpcode())) { 997 unsigned Mask = MI.getOperand(0).getImm(); 998 VPTBlock.setVPTState(Mask); 999 } 1000 1001 return Result; 1002 } 1003 1004 Result = 1005 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1006 if (Result != MCDisassembler::Fail) { 1007 Size = 4; 1008 bool InITBlock = ITBlock.instrInITBlock(); 1009 Check(Result, AddThumbPredicate(MI)); 1010 AddThumb1SBit(MI, InITBlock); 1011 return Result; 1012 } 1013 1014 Result = 1015 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1016 if (Result != MCDisassembler::Fail) { 1017 Size = 4; 1018 Check(Result, AddThumbPredicate(MI)); 1019 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 1020 } 1021 1022 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1023 Result = 1024 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1025 if (Result != MCDisassembler::Fail) { 1026 Size = 4; 1027 UpdateThumbVFPPredicate(Result, MI); 1028 return Result; 1029 } 1030 } 1031 1032 Result = 1033 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1034 if (Result != MCDisassembler::Fail) { 1035 Size = 4; 1036 return Result; 1037 } 1038 1039 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1040 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1041 STI); 1042 if (Result != MCDisassembler::Fail) { 1043 Size = 4; 1044 Check(Result, AddThumbPredicate(MI)); 1045 return Result; 1046 } 1047 } 1048 1049 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1050 uint32_t NEONLdStInsn = Insn32; 1051 NEONLdStInsn &= 0xF0FFFFFF; 1052 NEONLdStInsn |= 0x04000000; 1053 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1054 Address, this, STI); 1055 if (Result != MCDisassembler::Fail) { 1056 Size = 4; 1057 Check(Result, AddThumbPredicate(MI)); 1058 return Result; 1059 } 1060 } 1061 1062 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1063 uint32_t NEONDataInsn = Insn32; 1064 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1065 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1066 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1067 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1068 Address, this, STI); 1069 if (Result != MCDisassembler::Fail) { 1070 Size = 4; 1071 Check(Result, AddThumbPredicate(MI)); 1072 return Result; 1073 } 1074 1075 uint32_t NEONCryptoInsn = Insn32; 1076 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1077 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1078 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1079 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1080 Address, this, STI); 1081 if (Result != MCDisassembler::Fail) { 1082 Size = 4; 1083 return Result; 1084 } 1085 1086 uint32_t NEONv8Insn = Insn32; 1087 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1088 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1089 this, STI); 1090 if (Result != MCDisassembler::Fail) { 1091 Size = 4; 1092 return Result; 1093 } 1094 } 1095 1096 Result = 1097 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1098 if (Result != MCDisassembler::Fail) { 1099 Size = 4; 1100 Check(Result, AddThumbPredicate(MI)); 1101 return Result; 1102 } 1103 1104 Size = 0; 1105 return MCDisassembler::Fail; 1106 } 1107 1108 extern "C" void LLVMInitializeARMDisassembler() { 1109 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1110 createARMDisassembler); 1111 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1112 createARMDisassembler); 1113 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1114 createARMDisassembler); 1115 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1116 createARMDisassembler); 1117 } 1118 1119 static const uint16_t GPRDecoderTable[] = { 1120 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1121 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1122 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1123 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1124 }; 1125 1126 static const uint16_t CLRMGPRDecoderTable[] = { 1127 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1128 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1129 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1130 ARM::R12, 0, ARM::LR, ARM::APSR 1131 }; 1132 1133 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1134 uint64_t Address, const void *Decoder) { 1135 if (RegNo > 15) 1136 return MCDisassembler::Fail; 1137 1138 unsigned Register = GPRDecoderTable[RegNo]; 1139 Inst.addOperand(MCOperand::createReg(Register)); 1140 return MCDisassembler::Success; 1141 } 1142 1143 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1144 uint64_t Address, 1145 const void *Decoder) { 1146 if (RegNo > 15) 1147 return MCDisassembler::Fail; 1148 1149 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1150 if (Register == 0) 1151 return MCDisassembler::Fail; 1152 1153 Inst.addOperand(MCOperand::createReg(Register)); 1154 return MCDisassembler::Success; 1155 } 1156 1157 static DecodeStatus 1158 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1159 uint64_t Address, const void *Decoder) { 1160 DecodeStatus S = MCDisassembler::Success; 1161 1162 if (RegNo == 15) 1163 S = MCDisassembler::SoftFail; 1164 1165 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1166 1167 return S; 1168 } 1169 1170 static DecodeStatus 1171 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1172 uint64_t Address, const void *Decoder) { 1173 DecodeStatus S = MCDisassembler::Success; 1174 1175 if (RegNo == 15) 1176 { 1177 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1178 return MCDisassembler::Success; 1179 } 1180 1181 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1182 return S; 1183 } 1184 1185 static DecodeStatus 1186 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1187 uint64_t Address, const void *Decoder) { 1188 DecodeStatus S = MCDisassembler::Success; 1189 1190 if (RegNo == 15) 1191 { 1192 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1193 return MCDisassembler::Success; 1194 } 1195 1196 if (RegNo == 13) 1197 Check(S, MCDisassembler::SoftFail); 1198 1199 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1200 return S; 1201 } 1202 1203 static DecodeStatus 1204 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1205 uint64_t Address, const void *Decoder) { 1206 DecodeStatus S = MCDisassembler::Success; 1207 if (RegNo == 13) 1208 return MCDisassembler::Fail; 1209 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1210 return S; 1211 } 1212 1213 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1214 uint64_t Address, const void *Decoder) { 1215 if (RegNo > 7) 1216 return MCDisassembler::Fail; 1217 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1218 } 1219 1220 static const uint16_t GPRPairDecoderTable[] = { 1221 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1222 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1223 }; 1224 1225 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1226 uint64_t Address, const void *Decoder) { 1227 DecodeStatus S = MCDisassembler::Success; 1228 1229 if (RegNo > 13) 1230 return MCDisassembler::Fail; 1231 1232 if ((RegNo & 1) || RegNo == 0xe) 1233 S = MCDisassembler::SoftFail; 1234 1235 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1236 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1237 return S; 1238 } 1239 1240 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1241 uint64_t Address, 1242 const void *Decoder) { 1243 if (RegNo != 13) 1244 return MCDisassembler::Fail; 1245 1246 unsigned Register = GPRDecoderTable[RegNo]; 1247 Inst.addOperand(MCOperand::createReg(Register)); 1248 return MCDisassembler::Success; 1249 } 1250 1251 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1252 uint64_t Address, const void *Decoder) { 1253 unsigned Register = 0; 1254 switch (RegNo) { 1255 case 0: 1256 Register = ARM::R0; 1257 break; 1258 case 1: 1259 Register = ARM::R1; 1260 break; 1261 case 2: 1262 Register = ARM::R2; 1263 break; 1264 case 3: 1265 Register = ARM::R3; 1266 break; 1267 case 9: 1268 Register = ARM::R9; 1269 break; 1270 case 12: 1271 Register = ARM::R12; 1272 break; 1273 default: 1274 return MCDisassembler::Fail; 1275 } 1276 1277 Inst.addOperand(MCOperand::createReg(Register)); 1278 return MCDisassembler::Success; 1279 } 1280 1281 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1282 uint64_t Address, const void *Decoder) { 1283 DecodeStatus S = MCDisassembler::Success; 1284 1285 const FeatureBitset &featureBits = 1286 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1287 1288 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1289 S = MCDisassembler::SoftFail; 1290 1291 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1292 return S; 1293 } 1294 1295 static const uint16_t SPRDecoderTable[] = { 1296 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1297 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1298 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1299 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1300 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1301 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1302 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1303 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1304 }; 1305 1306 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1307 uint64_t Address, const void *Decoder) { 1308 if (RegNo > 31) 1309 return MCDisassembler::Fail; 1310 1311 unsigned Register = SPRDecoderTable[RegNo]; 1312 Inst.addOperand(MCOperand::createReg(Register)); 1313 return MCDisassembler::Success; 1314 } 1315 1316 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1317 uint64_t Address, const void *Decoder) { 1318 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1319 } 1320 1321 static const uint16_t DPRDecoderTable[] = { 1322 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1323 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1324 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1325 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1326 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1327 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1328 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1329 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1330 }; 1331 1332 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1333 uint64_t Address, const void *Decoder) { 1334 const FeatureBitset &featureBits = 1335 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1336 1337 bool hasD32 = featureBits[ARM::FeatureD32]; 1338 1339 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1340 return MCDisassembler::Fail; 1341 1342 unsigned Register = DPRDecoderTable[RegNo]; 1343 Inst.addOperand(MCOperand::createReg(Register)); 1344 return MCDisassembler::Success; 1345 } 1346 1347 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1348 uint64_t Address, const void *Decoder) { 1349 if (RegNo > 7) 1350 return MCDisassembler::Fail; 1351 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1352 } 1353 1354 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1355 uint64_t Address, const void *Decoder) { 1356 if (RegNo > 15) 1357 return MCDisassembler::Fail; 1358 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1359 } 1360 1361 static DecodeStatus 1362 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1363 uint64_t Address, const void *Decoder) { 1364 if (RegNo > 15) 1365 return MCDisassembler::Fail; 1366 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1367 } 1368 1369 static const uint16_t QPRDecoderTable[] = { 1370 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1371 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1372 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1373 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1374 }; 1375 1376 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1377 uint64_t Address, const void *Decoder) { 1378 if (RegNo > 31 || (RegNo & 1) != 0) 1379 return MCDisassembler::Fail; 1380 RegNo >>= 1; 1381 1382 unsigned Register = QPRDecoderTable[RegNo]; 1383 Inst.addOperand(MCOperand::createReg(Register)); 1384 return MCDisassembler::Success; 1385 } 1386 1387 static const uint16_t DPairDecoderTable[] = { 1388 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1389 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1390 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1391 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1392 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1393 ARM::Q15 1394 }; 1395 1396 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1397 uint64_t Address, const void *Decoder) { 1398 if (RegNo > 30) 1399 return MCDisassembler::Fail; 1400 1401 unsigned Register = DPairDecoderTable[RegNo]; 1402 Inst.addOperand(MCOperand::createReg(Register)); 1403 return MCDisassembler::Success; 1404 } 1405 1406 static const uint16_t DPairSpacedDecoderTable[] = { 1407 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1408 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1409 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1410 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1411 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1412 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1413 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1414 ARM::D28_D30, ARM::D29_D31 1415 }; 1416 1417 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1418 unsigned RegNo, 1419 uint64_t Address, 1420 const void *Decoder) { 1421 if (RegNo > 29) 1422 return MCDisassembler::Fail; 1423 1424 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1425 Inst.addOperand(MCOperand::createReg(Register)); 1426 return MCDisassembler::Success; 1427 } 1428 1429 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1430 uint64_t Address, const void *Decoder) { 1431 DecodeStatus S = MCDisassembler::Success; 1432 if (Val == 0xF) return MCDisassembler::Fail; 1433 // AL predicate is not allowed on Thumb1 branches. 1434 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1435 return MCDisassembler::Fail; 1436 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1437 Check(S, MCDisassembler::SoftFail); 1438 Inst.addOperand(MCOperand::createImm(Val)); 1439 if (Val == ARMCC::AL) { 1440 Inst.addOperand(MCOperand::createReg(0)); 1441 } else 1442 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1443 return S; 1444 } 1445 1446 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1447 uint64_t Address, const void *Decoder) { 1448 if (Val) 1449 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1450 else 1451 Inst.addOperand(MCOperand::createReg(0)); 1452 return MCDisassembler::Success; 1453 } 1454 1455 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1456 uint64_t Address, const void *Decoder) { 1457 DecodeStatus S = MCDisassembler::Success; 1458 1459 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1460 unsigned type = fieldFromInstruction(Val, 5, 2); 1461 unsigned imm = fieldFromInstruction(Val, 7, 5); 1462 1463 // Register-immediate 1464 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1465 return MCDisassembler::Fail; 1466 1467 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1468 switch (type) { 1469 case 0: 1470 Shift = ARM_AM::lsl; 1471 break; 1472 case 1: 1473 Shift = ARM_AM::lsr; 1474 break; 1475 case 2: 1476 Shift = ARM_AM::asr; 1477 break; 1478 case 3: 1479 Shift = ARM_AM::ror; 1480 break; 1481 } 1482 1483 if (Shift == ARM_AM::ror && imm == 0) 1484 Shift = ARM_AM::rrx; 1485 1486 unsigned Op = Shift | (imm << 3); 1487 Inst.addOperand(MCOperand::createImm(Op)); 1488 1489 return S; 1490 } 1491 1492 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1493 uint64_t Address, const void *Decoder) { 1494 DecodeStatus S = MCDisassembler::Success; 1495 1496 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1497 unsigned type = fieldFromInstruction(Val, 5, 2); 1498 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1499 1500 // Register-register 1501 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1502 return MCDisassembler::Fail; 1503 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1504 return MCDisassembler::Fail; 1505 1506 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1507 switch (type) { 1508 case 0: 1509 Shift = ARM_AM::lsl; 1510 break; 1511 case 1: 1512 Shift = ARM_AM::lsr; 1513 break; 1514 case 2: 1515 Shift = ARM_AM::asr; 1516 break; 1517 case 3: 1518 Shift = ARM_AM::ror; 1519 break; 1520 } 1521 1522 Inst.addOperand(MCOperand::createImm(Shift)); 1523 1524 return S; 1525 } 1526 1527 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1528 uint64_t Address, const void *Decoder) { 1529 DecodeStatus S = MCDisassembler::Success; 1530 1531 bool NeedDisjointWriteback = false; 1532 unsigned WritebackReg = 0; 1533 bool CLRM = false; 1534 switch (Inst.getOpcode()) { 1535 default: 1536 break; 1537 case ARM::LDMIA_UPD: 1538 case ARM::LDMDB_UPD: 1539 case ARM::LDMIB_UPD: 1540 case ARM::LDMDA_UPD: 1541 case ARM::t2LDMIA_UPD: 1542 case ARM::t2LDMDB_UPD: 1543 case ARM::t2STMIA_UPD: 1544 case ARM::t2STMDB_UPD: 1545 NeedDisjointWriteback = true; 1546 WritebackReg = Inst.getOperand(0).getReg(); 1547 break; 1548 case ARM::t2CLRM: 1549 CLRM = true; 1550 break; 1551 } 1552 1553 // Empty register lists are not allowed. 1554 if (Val == 0) return MCDisassembler::Fail; 1555 for (unsigned i = 0; i < 16; ++i) { 1556 if (Val & (1 << i)) { 1557 if (CLRM) { 1558 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1559 return MCDisassembler::Fail; 1560 } 1561 } else { 1562 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1563 return MCDisassembler::Fail; 1564 // Writeback not allowed if Rn is in the target list. 1565 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1566 Check(S, MCDisassembler::SoftFail); 1567 } 1568 } 1569 } 1570 1571 return S; 1572 } 1573 1574 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1575 uint64_t Address, const void *Decoder) { 1576 DecodeStatus S = MCDisassembler::Success; 1577 1578 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1579 unsigned regs = fieldFromInstruction(Val, 0, 8); 1580 1581 // In case of unpredictable encoding, tweak the operands. 1582 if (regs == 0 || (Vd + regs) > 32) { 1583 regs = Vd + regs > 32 ? 32 - Vd : regs; 1584 regs = std::max( 1u, regs); 1585 S = MCDisassembler::SoftFail; 1586 } 1587 1588 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1589 return MCDisassembler::Fail; 1590 for (unsigned i = 0; i < (regs - 1); ++i) { 1591 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1592 return MCDisassembler::Fail; 1593 } 1594 1595 return S; 1596 } 1597 1598 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1599 uint64_t Address, const void *Decoder) { 1600 DecodeStatus S = MCDisassembler::Success; 1601 1602 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1603 unsigned regs = fieldFromInstruction(Val, 1, 7); 1604 1605 // In case of unpredictable encoding, tweak the operands. 1606 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1607 regs = Vd + regs > 32 ? 32 - Vd : regs; 1608 regs = std::max( 1u, regs); 1609 regs = std::min(16u, regs); 1610 S = MCDisassembler::SoftFail; 1611 } 1612 1613 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1614 return MCDisassembler::Fail; 1615 for (unsigned i = 0; i < (regs - 1); ++i) { 1616 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1617 return MCDisassembler::Fail; 1618 } 1619 1620 return S; 1621 } 1622 1623 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1624 uint64_t Address, const void *Decoder) { 1625 // This operand encodes a mask of contiguous zeros between a specified MSB 1626 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1627 // the mask of all bits LSB-and-lower, and then xor them to create 1628 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1629 // create the final mask. 1630 unsigned msb = fieldFromInstruction(Val, 5, 5); 1631 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1632 1633 DecodeStatus S = MCDisassembler::Success; 1634 if (lsb > msb) { 1635 Check(S, MCDisassembler::SoftFail); 1636 // The check above will cause the warning for the "potentially undefined 1637 // instruction encoding" but we can't build a bad MCOperand value here 1638 // with a lsb > msb or else printing the MCInst will cause a crash. 1639 lsb = msb; 1640 } 1641 1642 uint32_t msb_mask = 0xFFFFFFFF; 1643 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1644 uint32_t lsb_mask = (1U << lsb) - 1; 1645 1646 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1647 return S; 1648 } 1649 1650 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1651 uint64_t Address, const void *Decoder) { 1652 DecodeStatus S = MCDisassembler::Success; 1653 1654 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1655 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1656 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1657 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1658 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1659 unsigned U = fieldFromInstruction(Insn, 23, 1); 1660 const FeatureBitset &featureBits = 1661 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1662 1663 switch (Inst.getOpcode()) { 1664 case ARM::LDC_OFFSET: 1665 case ARM::LDC_PRE: 1666 case ARM::LDC_POST: 1667 case ARM::LDC_OPTION: 1668 case ARM::LDCL_OFFSET: 1669 case ARM::LDCL_PRE: 1670 case ARM::LDCL_POST: 1671 case ARM::LDCL_OPTION: 1672 case ARM::STC_OFFSET: 1673 case ARM::STC_PRE: 1674 case ARM::STC_POST: 1675 case ARM::STC_OPTION: 1676 case ARM::STCL_OFFSET: 1677 case ARM::STCL_PRE: 1678 case ARM::STCL_POST: 1679 case ARM::STCL_OPTION: 1680 case ARM::t2LDC_OFFSET: 1681 case ARM::t2LDC_PRE: 1682 case ARM::t2LDC_POST: 1683 case ARM::t2LDC_OPTION: 1684 case ARM::t2LDCL_OFFSET: 1685 case ARM::t2LDCL_PRE: 1686 case ARM::t2LDCL_POST: 1687 case ARM::t2LDCL_OPTION: 1688 case ARM::t2STC_OFFSET: 1689 case ARM::t2STC_PRE: 1690 case ARM::t2STC_POST: 1691 case ARM::t2STC_OPTION: 1692 case ARM::t2STCL_OFFSET: 1693 case ARM::t2STCL_PRE: 1694 case ARM::t2STCL_POST: 1695 case ARM::t2STCL_OPTION: 1696 case ARM::t2LDC2_OFFSET: 1697 case ARM::t2LDC2L_OFFSET: 1698 case ARM::t2LDC2_PRE: 1699 case ARM::t2LDC2L_PRE: 1700 case ARM::t2STC2_OFFSET: 1701 case ARM::t2STC2L_OFFSET: 1702 case ARM::t2STC2_PRE: 1703 case ARM::t2STC2L_PRE: 1704 case ARM::LDC2_OFFSET: 1705 case ARM::LDC2L_OFFSET: 1706 case ARM::LDC2_PRE: 1707 case ARM::LDC2L_PRE: 1708 case ARM::STC2_OFFSET: 1709 case ARM::STC2L_OFFSET: 1710 case ARM::STC2_PRE: 1711 case ARM::STC2L_PRE: 1712 case ARM::t2LDC2_OPTION: 1713 case ARM::t2STC2_OPTION: 1714 case ARM::t2LDC2_POST: 1715 case ARM::t2LDC2L_POST: 1716 case ARM::t2STC2_POST: 1717 case ARM::t2STC2L_POST: 1718 case ARM::LDC2_POST: 1719 case ARM::LDC2L_POST: 1720 case ARM::STC2_POST: 1721 case ARM::STC2L_POST: 1722 if (coproc == 0xA || coproc == 0xB || 1723 (featureBits[ARM::HasV8_1MMainlineOps] && 1724 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1725 coproc == 0xE || coproc == 0xF))) 1726 return MCDisassembler::Fail; 1727 break; 1728 default: 1729 break; 1730 } 1731 1732 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1733 return MCDisassembler::Fail; 1734 1735 Inst.addOperand(MCOperand::createImm(coproc)); 1736 Inst.addOperand(MCOperand::createImm(CRd)); 1737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1738 return MCDisassembler::Fail; 1739 1740 switch (Inst.getOpcode()) { 1741 case ARM::t2LDC2_OFFSET: 1742 case ARM::t2LDC2L_OFFSET: 1743 case ARM::t2LDC2_PRE: 1744 case ARM::t2LDC2L_PRE: 1745 case ARM::t2STC2_OFFSET: 1746 case ARM::t2STC2L_OFFSET: 1747 case ARM::t2STC2_PRE: 1748 case ARM::t2STC2L_PRE: 1749 case ARM::LDC2_OFFSET: 1750 case ARM::LDC2L_OFFSET: 1751 case ARM::LDC2_PRE: 1752 case ARM::LDC2L_PRE: 1753 case ARM::STC2_OFFSET: 1754 case ARM::STC2L_OFFSET: 1755 case ARM::STC2_PRE: 1756 case ARM::STC2L_PRE: 1757 case ARM::t2LDC_OFFSET: 1758 case ARM::t2LDCL_OFFSET: 1759 case ARM::t2LDC_PRE: 1760 case ARM::t2LDCL_PRE: 1761 case ARM::t2STC_OFFSET: 1762 case ARM::t2STCL_OFFSET: 1763 case ARM::t2STC_PRE: 1764 case ARM::t2STCL_PRE: 1765 case ARM::LDC_OFFSET: 1766 case ARM::LDCL_OFFSET: 1767 case ARM::LDC_PRE: 1768 case ARM::LDCL_PRE: 1769 case ARM::STC_OFFSET: 1770 case ARM::STCL_OFFSET: 1771 case ARM::STC_PRE: 1772 case ARM::STCL_PRE: 1773 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1774 Inst.addOperand(MCOperand::createImm(imm)); 1775 break; 1776 case ARM::t2LDC2_POST: 1777 case ARM::t2LDC2L_POST: 1778 case ARM::t2STC2_POST: 1779 case ARM::t2STC2L_POST: 1780 case ARM::LDC2_POST: 1781 case ARM::LDC2L_POST: 1782 case ARM::STC2_POST: 1783 case ARM::STC2L_POST: 1784 case ARM::t2LDC_POST: 1785 case ARM::t2LDCL_POST: 1786 case ARM::t2STC_POST: 1787 case ARM::t2STCL_POST: 1788 case ARM::LDC_POST: 1789 case ARM::LDCL_POST: 1790 case ARM::STC_POST: 1791 case ARM::STCL_POST: 1792 imm |= U << 8; 1793 LLVM_FALLTHROUGH; 1794 default: 1795 // The 'option' variant doesn't encode 'U' in the immediate since 1796 // the immediate is unsigned [0,255]. 1797 Inst.addOperand(MCOperand::createImm(imm)); 1798 break; 1799 } 1800 1801 switch (Inst.getOpcode()) { 1802 case ARM::LDC_OFFSET: 1803 case ARM::LDC_PRE: 1804 case ARM::LDC_POST: 1805 case ARM::LDC_OPTION: 1806 case ARM::LDCL_OFFSET: 1807 case ARM::LDCL_PRE: 1808 case ARM::LDCL_POST: 1809 case ARM::LDCL_OPTION: 1810 case ARM::STC_OFFSET: 1811 case ARM::STC_PRE: 1812 case ARM::STC_POST: 1813 case ARM::STC_OPTION: 1814 case ARM::STCL_OFFSET: 1815 case ARM::STCL_PRE: 1816 case ARM::STCL_POST: 1817 case ARM::STCL_OPTION: 1818 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1819 return MCDisassembler::Fail; 1820 break; 1821 default: 1822 break; 1823 } 1824 1825 return S; 1826 } 1827 1828 static DecodeStatus 1829 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1830 uint64_t Address, const void *Decoder) { 1831 DecodeStatus S = MCDisassembler::Success; 1832 1833 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1834 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1835 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1836 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1837 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1838 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1839 unsigned P = fieldFromInstruction(Insn, 24, 1); 1840 unsigned W = fieldFromInstruction(Insn, 21, 1); 1841 1842 // On stores, the writeback operand precedes Rt. 1843 switch (Inst.getOpcode()) { 1844 case ARM::STR_POST_IMM: 1845 case ARM::STR_POST_REG: 1846 case ARM::STRB_POST_IMM: 1847 case ARM::STRB_POST_REG: 1848 case ARM::STRT_POST_REG: 1849 case ARM::STRT_POST_IMM: 1850 case ARM::STRBT_POST_REG: 1851 case ARM::STRBT_POST_IMM: 1852 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1853 return MCDisassembler::Fail; 1854 break; 1855 default: 1856 break; 1857 } 1858 1859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1860 return MCDisassembler::Fail; 1861 1862 // On loads, the writeback operand comes after Rt. 1863 switch (Inst.getOpcode()) { 1864 case ARM::LDR_POST_IMM: 1865 case ARM::LDR_POST_REG: 1866 case ARM::LDRB_POST_IMM: 1867 case ARM::LDRB_POST_REG: 1868 case ARM::LDRBT_POST_REG: 1869 case ARM::LDRBT_POST_IMM: 1870 case ARM::LDRT_POST_REG: 1871 case ARM::LDRT_POST_IMM: 1872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1873 return MCDisassembler::Fail; 1874 break; 1875 default: 1876 break; 1877 } 1878 1879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 1882 ARM_AM::AddrOpc Op = ARM_AM::add; 1883 if (!fieldFromInstruction(Insn, 23, 1)) 1884 Op = ARM_AM::sub; 1885 1886 bool writeback = (P == 0) || (W == 1); 1887 unsigned idx_mode = 0; 1888 if (P && writeback) 1889 idx_mode = ARMII::IndexModePre; 1890 else if (!P && writeback) 1891 idx_mode = ARMII::IndexModePost; 1892 1893 if (writeback && (Rn == 15 || Rn == Rt)) 1894 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1895 1896 if (reg) { 1897 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1898 return MCDisassembler::Fail; 1899 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1900 switch( fieldFromInstruction(Insn, 5, 2)) { 1901 case 0: 1902 Opc = ARM_AM::lsl; 1903 break; 1904 case 1: 1905 Opc = ARM_AM::lsr; 1906 break; 1907 case 2: 1908 Opc = ARM_AM::asr; 1909 break; 1910 case 3: 1911 Opc = ARM_AM::ror; 1912 break; 1913 default: 1914 return MCDisassembler::Fail; 1915 } 1916 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1917 if (Opc == ARM_AM::ror && amt == 0) 1918 Opc = ARM_AM::rrx; 1919 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1920 1921 Inst.addOperand(MCOperand::createImm(imm)); 1922 } else { 1923 Inst.addOperand(MCOperand::createReg(0)); 1924 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1925 Inst.addOperand(MCOperand::createImm(tmp)); 1926 } 1927 1928 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1929 return MCDisassembler::Fail; 1930 1931 return S; 1932 } 1933 1934 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1935 uint64_t Address, const void *Decoder) { 1936 DecodeStatus S = MCDisassembler::Success; 1937 1938 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1939 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1940 unsigned type = fieldFromInstruction(Val, 5, 2); 1941 unsigned imm = fieldFromInstruction(Val, 7, 5); 1942 unsigned U = fieldFromInstruction(Val, 12, 1); 1943 1944 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1945 switch (type) { 1946 case 0: 1947 ShOp = ARM_AM::lsl; 1948 break; 1949 case 1: 1950 ShOp = ARM_AM::lsr; 1951 break; 1952 case 2: 1953 ShOp = ARM_AM::asr; 1954 break; 1955 case 3: 1956 ShOp = ARM_AM::ror; 1957 break; 1958 } 1959 1960 if (ShOp == ARM_AM::ror && imm == 0) 1961 ShOp = ARM_AM::rrx; 1962 1963 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1964 return MCDisassembler::Fail; 1965 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1966 return MCDisassembler::Fail; 1967 unsigned shift; 1968 if (U) 1969 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1970 else 1971 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1972 Inst.addOperand(MCOperand::createImm(shift)); 1973 1974 return S; 1975 } 1976 1977 static DecodeStatus 1978 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1979 uint64_t Address, const void *Decoder) { 1980 DecodeStatus S = MCDisassembler::Success; 1981 1982 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1983 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1984 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1985 unsigned type = fieldFromInstruction(Insn, 22, 1); 1986 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1987 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1988 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1989 unsigned W = fieldFromInstruction(Insn, 21, 1); 1990 unsigned P = fieldFromInstruction(Insn, 24, 1); 1991 unsigned Rt2 = Rt + 1; 1992 1993 bool writeback = (W == 1) | (P == 0); 1994 1995 // For {LD,ST}RD, Rt must be even, else undefined. 1996 switch (Inst.getOpcode()) { 1997 case ARM::STRD: 1998 case ARM::STRD_PRE: 1999 case ARM::STRD_POST: 2000 case ARM::LDRD: 2001 case ARM::LDRD_PRE: 2002 case ARM::LDRD_POST: 2003 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2004 break; 2005 default: 2006 break; 2007 } 2008 switch (Inst.getOpcode()) { 2009 case ARM::STRD: 2010 case ARM::STRD_PRE: 2011 case ARM::STRD_POST: 2012 if (P == 0 && W == 1) 2013 S = MCDisassembler::SoftFail; 2014 2015 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2016 S = MCDisassembler::SoftFail; 2017 if (type && Rm == 15) 2018 S = MCDisassembler::SoftFail; 2019 if (Rt2 == 15) 2020 S = MCDisassembler::SoftFail; 2021 if (!type && fieldFromInstruction(Insn, 8, 4)) 2022 S = MCDisassembler::SoftFail; 2023 break; 2024 case ARM::STRH: 2025 case ARM::STRH_PRE: 2026 case ARM::STRH_POST: 2027 if (Rt == 15) 2028 S = MCDisassembler::SoftFail; 2029 if (writeback && (Rn == 15 || Rn == Rt)) 2030 S = MCDisassembler::SoftFail; 2031 if (!type && Rm == 15) 2032 S = MCDisassembler::SoftFail; 2033 break; 2034 case ARM::LDRD: 2035 case ARM::LDRD_PRE: 2036 case ARM::LDRD_POST: 2037 if (type && Rn == 15) { 2038 if (Rt2 == 15) 2039 S = MCDisassembler::SoftFail; 2040 break; 2041 } 2042 if (P == 0 && W == 1) 2043 S = MCDisassembler::SoftFail; 2044 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2045 S = MCDisassembler::SoftFail; 2046 if (!type && writeback && Rn == 15) 2047 S = MCDisassembler::SoftFail; 2048 if (writeback && (Rn == Rt || Rn == Rt2)) 2049 S = MCDisassembler::SoftFail; 2050 break; 2051 case ARM::LDRH: 2052 case ARM::LDRH_PRE: 2053 case ARM::LDRH_POST: 2054 if (type && Rn == 15) { 2055 if (Rt == 15) 2056 S = MCDisassembler::SoftFail; 2057 break; 2058 } 2059 if (Rt == 15) 2060 S = MCDisassembler::SoftFail; 2061 if (!type && Rm == 15) 2062 S = MCDisassembler::SoftFail; 2063 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2064 S = MCDisassembler::SoftFail; 2065 break; 2066 case ARM::LDRSH: 2067 case ARM::LDRSH_PRE: 2068 case ARM::LDRSH_POST: 2069 case ARM::LDRSB: 2070 case ARM::LDRSB_PRE: 2071 case ARM::LDRSB_POST: 2072 if (type && Rn == 15) { 2073 if (Rt == 15) 2074 S = MCDisassembler::SoftFail; 2075 break; 2076 } 2077 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2078 S = MCDisassembler::SoftFail; 2079 if (!type && (Rt == 15 || Rm == 15)) 2080 S = MCDisassembler::SoftFail; 2081 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2082 S = MCDisassembler::SoftFail; 2083 break; 2084 default: 2085 break; 2086 } 2087 2088 if (writeback) { // Writeback 2089 if (P) 2090 U |= ARMII::IndexModePre << 9; 2091 else 2092 U |= ARMII::IndexModePost << 9; 2093 2094 // On stores, the writeback operand precedes Rt. 2095 switch (Inst.getOpcode()) { 2096 case ARM::STRD: 2097 case ARM::STRD_PRE: 2098 case ARM::STRD_POST: 2099 case ARM::STRH: 2100 case ARM::STRH_PRE: 2101 case ARM::STRH_POST: 2102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2103 return MCDisassembler::Fail; 2104 break; 2105 default: 2106 break; 2107 } 2108 } 2109 2110 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2111 return MCDisassembler::Fail; 2112 switch (Inst.getOpcode()) { 2113 case ARM::STRD: 2114 case ARM::STRD_PRE: 2115 case ARM::STRD_POST: 2116 case ARM::LDRD: 2117 case ARM::LDRD_PRE: 2118 case ARM::LDRD_POST: 2119 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2120 return MCDisassembler::Fail; 2121 break; 2122 default: 2123 break; 2124 } 2125 2126 if (writeback) { 2127 // On loads, the writeback operand comes after Rt. 2128 switch (Inst.getOpcode()) { 2129 case ARM::LDRD: 2130 case ARM::LDRD_PRE: 2131 case ARM::LDRD_POST: 2132 case ARM::LDRH: 2133 case ARM::LDRH_PRE: 2134 case ARM::LDRH_POST: 2135 case ARM::LDRSH: 2136 case ARM::LDRSH_PRE: 2137 case ARM::LDRSH_POST: 2138 case ARM::LDRSB: 2139 case ARM::LDRSB_PRE: 2140 case ARM::LDRSB_POST: 2141 case ARM::LDRHTr: 2142 case ARM::LDRSBTr: 2143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2144 return MCDisassembler::Fail; 2145 break; 2146 default: 2147 break; 2148 } 2149 } 2150 2151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2152 return MCDisassembler::Fail; 2153 2154 if (type) { 2155 Inst.addOperand(MCOperand::createReg(0)); 2156 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2157 } else { 2158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2159 return MCDisassembler::Fail; 2160 Inst.addOperand(MCOperand::createImm(U)); 2161 } 2162 2163 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2164 return MCDisassembler::Fail; 2165 2166 return S; 2167 } 2168 2169 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2170 uint64_t Address, const void *Decoder) { 2171 DecodeStatus S = MCDisassembler::Success; 2172 2173 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2174 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2175 2176 switch (mode) { 2177 case 0: 2178 mode = ARM_AM::da; 2179 break; 2180 case 1: 2181 mode = ARM_AM::ia; 2182 break; 2183 case 2: 2184 mode = ARM_AM::db; 2185 break; 2186 case 3: 2187 mode = ARM_AM::ib; 2188 break; 2189 } 2190 2191 Inst.addOperand(MCOperand::createImm(mode)); 2192 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2193 return MCDisassembler::Fail; 2194 2195 return S; 2196 } 2197 2198 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2199 uint64_t Address, const void *Decoder) { 2200 DecodeStatus S = MCDisassembler::Success; 2201 2202 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2203 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2204 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2205 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2206 2207 if (pred == 0xF) 2208 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2209 2210 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2211 return MCDisassembler::Fail; 2212 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2213 return MCDisassembler::Fail; 2214 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2215 return MCDisassembler::Fail; 2216 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2217 return MCDisassembler::Fail; 2218 return S; 2219 } 2220 2221 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2222 unsigned Insn, 2223 uint64_t Address, const void *Decoder) { 2224 DecodeStatus S = MCDisassembler::Success; 2225 2226 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2227 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2228 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2229 2230 if (pred == 0xF) { 2231 // Ambiguous with RFE and SRS 2232 switch (Inst.getOpcode()) { 2233 case ARM::LDMDA: 2234 Inst.setOpcode(ARM::RFEDA); 2235 break; 2236 case ARM::LDMDA_UPD: 2237 Inst.setOpcode(ARM::RFEDA_UPD); 2238 break; 2239 case ARM::LDMDB: 2240 Inst.setOpcode(ARM::RFEDB); 2241 break; 2242 case ARM::LDMDB_UPD: 2243 Inst.setOpcode(ARM::RFEDB_UPD); 2244 break; 2245 case ARM::LDMIA: 2246 Inst.setOpcode(ARM::RFEIA); 2247 break; 2248 case ARM::LDMIA_UPD: 2249 Inst.setOpcode(ARM::RFEIA_UPD); 2250 break; 2251 case ARM::LDMIB: 2252 Inst.setOpcode(ARM::RFEIB); 2253 break; 2254 case ARM::LDMIB_UPD: 2255 Inst.setOpcode(ARM::RFEIB_UPD); 2256 break; 2257 case ARM::STMDA: 2258 Inst.setOpcode(ARM::SRSDA); 2259 break; 2260 case ARM::STMDA_UPD: 2261 Inst.setOpcode(ARM::SRSDA_UPD); 2262 break; 2263 case ARM::STMDB: 2264 Inst.setOpcode(ARM::SRSDB); 2265 break; 2266 case ARM::STMDB_UPD: 2267 Inst.setOpcode(ARM::SRSDB_UPD); 2268 break; 2269 case ARM::STMIA: 2270 Inst.setOpcode(ARM::SRSIA); 2271 break; 2272 case ARM::STMIA_UPD: 2273 Inst.setOpcode(ARM::SRSIA_UPD); 2274 break; 2275 case ARM::STMIB: 2276 Inst.setOpcode(ARM::SRSIB); 2277 break; 2278 case ARM::STMIB_UPD: 2279 Inst.setOpcode(ARM::SRSIB_UPD); 2280 break; 2281 default: 2282 return MCDisassembler::Fail; 2283 } 2284 2285 // For stores (which become SRS's, the only operand is the mode. 2286 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2287 // Check SRS encoding constraints 2288 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2289 fieldFromInstruction(Insn, 20, 1) == 0)) 2290 return MCDisassembler::Fail; 2291 2292 Inst.addOperand( 2293 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2294 return S; 2295 } 2296 2297 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2298 } 2299 2300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2301 return MCDisassembler::Fail; 2302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2303 return MCDisassembler::Fail; // Tied 2304 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2305 return MCDisassembler::Fail; 2306 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2307 return MCDisassembler::Fail; 2308 2309 return S; 2310 } 2311 2312 // Check for UNPREDICTABLE predicated ESB instruction 2313 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2314 uint64_t Address, const void *Decoder) { 2315 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2316 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2317 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2318 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2319 2320 DecodeStatus S = MCDisassembler::Success; 2321 2322 Inst.addOperand(MCOperand::createImm(imm8)); 2323 2324 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2325 return MCDisassembler::Fail; 2326 2327 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2328 // so all predicates should be allowed. 2329 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2330 S = MCDisassembler::SoftFail; 2331 2332 return S; 2333 } 2334 2335 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2336 uint64_t Address, const void *Decoder) { 2337 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2338 unsigned M = fieldFromInstruction(Insn, 17, 1); 2339 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2340 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2341 2342 DecodeStatus S = MCDisassembler::Success; 2343 2344 // This decoder is called from multiple location that do not check 2345 // the full encoding is valid before they do. 2346 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2347 fieldFromInstruction(Insn, 16, 1) != 0 || 2348 fieldFromInstruction(Insn, 20, 8) != 0x10) 2349 return MCDisassembler::Fail; 2350 2351 // imod == '01' --> UNPREDICTABLE 2352 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2353 // return failure here. The '01' imod value is unprintable, so there's 2354 // nothing useful we could do even if we returned UNPREDICTABLE. 2355 2356 if (imod == 1) return MCDisassembler::Fail; 2357 2358 if (imod && M) { 2359 Inst.setOpcode(ARM::CPS3p); 2360 Inst.addOperand(MCOperand::createImm(imod)); 2361 Inst.addOperand(MCOperand::createImm(iflags)); 2362 Inst.addOperand(MCOperand::createImm(mode)); 2363 } else if (imod && !M) { 2364 Inst.setOpcode(ARM::CPS2p); 2365 Inst.addOperand(MCOperand::createImm(imod)); 2366 Inst.addOperand(MCOperand::createImm(iflags)); 2367 if (mode) S = MCDisassembler::SoftFail; 2368 } else if (!imod && M) { 2369 Inst.setOpcode(ARM::CPS1p); 2370 Inst.addOperand(MCOperand::createImm(mode)); 2371 if (iflags) S = MCDisassembler::SoftFail; 2372 } else { 2373 // imod == '00' && M == '0' --> UNPREDICTABLE 2374 Inst.setOpcode(ARM::CPS1p); 2375 Inst.addOperand(MCOperand::createImm(mode)); 2376 S = MCDisassembler::SoftFail; 2377 } 2378 2379 return S; 2380 } 2381 2382 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2383 uint64_t Address, const void *Decoder) { 2384 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2385 unsigned M = fieldFromInstruction(Insn, 8, 1); 2386 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2387 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2388 2389 DecodeStatus S = MCDisassembler::Success; 2390 2391 // imod == '01' --> UNPREDICTABLE 2392 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2393 // return failure here. The '01' imod value is unprintable, so there's 2394 // nothing useful we could do even if we returned UNPREDICTABLE. 2395 2396 if (imod == 1) return MCDisassembler::Fail; 2397 2398 if (imod && M) { 2399 Inst.setOpcode(ARM::t2CPS3p); 2400 Inst.addOperand(MCOperand::createImm(imod)); 2401 Inst.addOperand(MCOperand::createImm(iflags)); 2402 Inst.addOperand(MCOperand::createImm(mode)); 2403 } else if (imod && !M) { 2404 Inst.setOpcode(ARM::t2CPS2p); 2405 Inst.addOperand(MCOperand::createImm(imod)); 2406 Inst.addOperand(MCOperand::createImm(iflags)); 2407 if (mode) S = MCDisassembler::SoftFail; 2408 } else if (!imod && M) { 2409 Inst.setOpcode(ARM::t2CPS1p); 2410 Inst.addOperand(MCOperand::createImm(mode)); 2411 if (iflags) S = MCDisassembler::SoftFail; 2412 } else { 2413 // imod == '00' && M == '0' --> this is a HINT instruction 2414 int imm = fieldFromInstruction(Insn, 0, 8); 2415 // HINT are defined only for immediate in [0..4] 2416 if(imm > 4) return MCDisassembler::Fail; 2417 Inst.setOpcode(ARM::t2HINT); 2418 Inst.addOperand(MCOperand::createImm(imm)); 2419 } 2420 2421 return S; 2422 } 2423 2424 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2425 uint64_t Address, const void *Decoder) { 2426 DecodeStatus S = MCDisassembler::Success; 2427 2428 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2429 unsigned imm = 0; 2430 2431 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2432 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2433 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2434 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2435 2436 if (Inst.getOpcode() == ARM::t2MOVTi16) 2437 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2438 return MCDisassembler::Fail; 2439 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2440 return MCDisassembler::Fail; 2441 2442 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2443 Inst.addOperand(MCOperand::createImm(imm)); 2444 2445 return S; 2446 } 2447 2448 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2449 uint64_t Address, const void *Decoder) { 2450 DecodeStatus S = MCDisassembler::Success; 2451 2452 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2453 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2454 unsigned imm = 0; 2455 2456 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2457 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2458 2459 if (Inst.getOpcode() == ARM::MOVTi16) 2460 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2461 return MCDisassembler::Fail; 2462 2463 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2464 return MCDisassembler::Fail; 2465 2466 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2467 Inst.addOperand(MCOperand::createImm(imm)); 2468 2469 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2470 return MCDisassembler::Fail; 2471 2472 return S; 2473 } 2474 2475 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2476 uint64_t Address, const void *Decoder) { 2477 DecodeStatus S = MCDisassembler::Success; 2478 2479 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2480 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2481 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2482 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2483 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2484 2485 if (pred == 0xF) 2486 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2487 2488 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2489 return MCDisassembler::Fail; 2490 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2491 return MCDisassembler::Fail; 2492 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2493 return MCDisassembler::Fail; 2494 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2495 return MCDisassembler::Fail; 2496 2497 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2498 return MCDisassembler::Fail; 2499 2500 return S; 2501 } 2502 2503 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2504 uint64_t Address, const void *Decoder) { 2505 DecodeStatus S = MCDisassembler::Success; 2506 2507 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2508 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2509 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2510 2511 if (Pred == 0xF) 2512 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2513 2514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2515 return MCDisassembler::Fail; 2516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2517 return MCDisassembler::Fail; 2518 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2519 return MCDisassembler::Fail; 2520 2521 return S; 2522 } 2523 2524 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2525 uint64_t Address, const void *Decoder) { 2526 DecodeStatus S = MCDisassembler::Success; 2527 2528 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2529 2530 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2531 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2532 2533 if (!FeatureBits[ARM::HasV8_1aOps] || 2534 !FeatureBits[ARM::HasV8Ops]) 2535 return MCDisassembler::Fail; 2536 2537 // Decoder can be called from DecodeTST, which does not check the full 2538 // encoding is valid. 2539 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2540 fieldFromInstruction(Insn, 4,4) != 0) 2541 return MCDisassembler::Fail; 2542 if (fieldFromInstruction(Insn, 10,10) != 0 || 2543 fieldFromInstruction(Insn, 0,4) != 0) 2544 S = MCDisassembler::SoftFail; 2545 2546 Inst.setOpcode(ARM::SETPAN); 2547 Inst.addOperand(MCOperand::createImm(Imm)); 2548 2549 return S; 2550 } 2551 2552 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2553 uint64_t Address, const void *Decoder) { 2554 DecodeStatus S = MCDisassembler::Success; 2555 2556 unsigned add = fieldFromInstruction(Val, 12, 1); 2557 unsigned imm = fieldFromInstruction(Val, 0, 12); 2558 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2559 2560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2561 return MCDisassembler::Fail; 2562 2563 if (!add) imm *= -1; 2564 if (imm == 0 && !add) imm = INT32_MIN; 2565 Inst.addOperand(MCOperand::createImm(imm)); 2566 if (Rn == 15) 2567 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2568 2569 return S; 2570 } 2571 2572 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2573 uint64_t Address, const void *Decoder) { 2574 DecodeStatus S = MCDisassembler::Success; 2575 2576 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2577 // U == 1 to add imm, 0 to subtract it. 2578 unsigned U = fieldFromInstruction(Val, 8, 1); 2579 unsigned imm = fieldFromInstruction(Val, 0, 8); 2580 2581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2582 return MCDisassembler::Fail; 2583 2584 if (U) 2585 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2586 else 2587 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2588 2589 return S; 2590 } 2591 2592 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2593 uint64_t Address, const void *Decoder) { 2594 DecodeStatus S = MCDisassembler::Success; 2595 2596 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2597 // U == 1 to add imm, 0 to subtract it. 2598 unsigned U = fieldFromInstruction(Val, 8, 1); 2599 unsigned imm = fieldFromInstruction(Val, 0, 8); 2600 2601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2602 return MCDisassembler::Fail; 2603 2604 if (U) 2605 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2606 else 2607 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2608 2609 return S; 2610 } 2611 2612 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2613 uint64_t Address, const void *Decoder) { 2614 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2615 } 2616 2617 static DecodeStatus 2618 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2619 uint64_t Address, const void *Decoder) { 2620 DecodeStatus Status = MCDisassembler::Success; 2621 2622 // Note the J1 and J2 values are from the encoded instruction. So here 2623 // change them to I1 and I2 values via as documented: 2624 // I1 = NOT(J1 EOR S); 2625 // I2 = NOT(J2 EOR S); 2626 // and build the imm32 with one trailing zero as documented: 2627 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2628 unsigned S = fieldFromInstruction(Insn, 26, 1); 2629 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2630 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2631 unsigned I1 = !(J1 ^ S); 2632 unsigned I2 = !(J2 ^ S); 2633 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2634 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2635 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2636 int imm32 = SignExtend32<25>(tmp << 1); 2637 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2638 true, 4, Inst, Decoder)) 2639 Inst.addOperand(MCOperand::createImm(imm32)); 2640 2641 return Status; 2642 } 2643 2644 static DecodeStatus 2645 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2646 uint64_t Address, const void *Decoder) { 2647 DecodeStatus S = MCDisassembler::Success; 2648 2649 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2650 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2651 2652 if (pred == 0xF) { 2653 Inst.setOpcode(ARM::BLXi); 2654 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2655 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2656 true, 4, Inst, Decoder)) 2657 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2658 return S; 2659 } 2660 2661 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2662 true, 4, Inst, Decoder)) 2663 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2664 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2665 return MCDisassembler::Fail; 2666 2667 return S; 2668 } 2669 2670 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2671 uint64_t Address, const void *Decoder) { 2672 DecodeStatus S = MCDisassembler::Success; 2673 2674 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2675 unsigned align = fieldFromInstruction(Val, 4, 2); 2676 2677 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2678 return MCDisassembler::Fail; 2679 if (!align) 2680 Inst.addOperand(MCOperand::createImm(0)); 2681 else 2682 Inst.addOperand(MCOperand::createImm(4 << align)); 2683 2684 return S; 2685 } 2686 2687 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2688 uint64_t Address, const void *Decoder) { 2689 DecodeStatus S = MCDisassembler::Success; 2690 2691 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2692 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2693 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2694 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2695 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2696 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2697 2698 // First output register 2699 switch (Inst.getOpcode()) { 2700 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2701 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2702 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2703 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2704 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2705 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2706 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2707 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2708 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2709 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2710 return MCDisassembler::Fail; 2711 break; 2712 case ARM::VLD2b16: 2713 case ARM::VLD2b32: 2714 case ARM::VLD2b8: 2715 case ARM::VLD2b16wb_fixed: 2716 case ARM::VLD2b16wb_register: 2717 case ARM::VLD2b32wb_fixed: 2718 case ARM::VLD2b32wb_register: 2719 case ARM::VLD2b8wb_fixed: 2720 case ARM::VLD2b8wb_register: 2721 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 break; 2724 default: 2725 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2726 return MCDisassembler::Fail; 2727 } 2728 2729 // Second output register 2730 switch (Inst.getOpcode()) { 2731 case ARM::VLD3d8: 2732 case ARM::VLD3d16: 2733 case ARM::VLD3d32: 2734 case ARM::VLD3d8_UPD: 2735 case ARM::VLD3d16_UPD: 2736 case ARM::VLD3d32_UPD: 2737 case ARM::VLD4d8: 2738 case ARM::VLD4d16: 2739 case ARM::VLD4d32: 2740 case ARM::VLD4d8_UPD: 2741 case ARM::VLD4d16_UPD: 2742 case ARM::VLD4d32_UPD: 2743 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2744 return MCDisassembler::Fail; 2745 break; 2746 case ARM::VLD3q8: 2747 case ARM::VLD3q16: 2748 case ARM::VLD3q32: 2749 case ARM::VLD3q8_UPD: 2750 case ARM::VLD3q16_UPD: 2751 case ARM::VLD3q32_UPD: 2752 case ARM::VLD4q8: 2753 case ARM::VLD4q16: 2754 case ARM::VLD4q32: 2755 case ARM::VLD4q8_UPD: 2756 case ARM::VLD4q16_UPD: 2757 case ARM::VLD4q32_UPD: 2758 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2759 return MCDisassembler::Fail; 2760 break; 2761 default: 2762 break; 2763 } 2764 2765 // Third output register 2766 switch(Inst.getOpcode()) { 2767 case ARM::VLD3d8: 2768 case ARM::VLD3d16: 2769 case ARM::VLD3d32: 2770 case ARM::VLD3d8_UPD: 2771 case ARM::VLD3d16_UPD: 2772 case ARM::VLD3d32_UPD: 2773 case ARM::VLD4d8: 2774 case ARM::VLD4d16: 2775 case ARM::VLD4d32: 2776 case ARM::VLD4d8_UPD: 2777 case ARM::VLD4d16_UPD: 2778 case ARM::VLD4d32_UPD: 2779 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 break; 2782 case ARM::VLD3q8: 2783 case ARM::VLD3q16: 2784 case ARM::VLD3q32: 2785 case ARM::VLD3q8_UPD: 2786 case ARM::VLD3q16_UPD: 2787 case ARM::VLD3q32_UPD: 2788 case ARM::VLD4q8: 2789 case ARM::VLD4q16: 2790 case ARM::VLD4q32: 2791 case ARM::VLD4q8_UPD: 2792 case ARM::VLD4q16_UPD: 2793 case ARM::VLD4q32_UPD: 2794 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2795 return MCDisassembler::Fail; 2796 break; 2797 default: 2798 break; 2799 } 2800 2801 // Fourth output register 2802 switch (Inst.getOpcode()) { 2803 case ARM::VLD4d8: 2804 case ARM::VLD4d16: 2805 case ARM::VLD4d32: 2806 case ARM::VLD4d8_UPD: 2807 case ARM::VLD4d16_UPD: 2808 case ARM::VLD4d32_UPD: 2809 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2810 return MCDisassembler::Fail; 2811 break; 2812 case ARM::VLD4q8: 2813 case ARM::VLD4q16: 2814 case ARM::VLD4q32: 2815 case ARM::VLD4q8_UPD: 2816 case ARM::VLD4q16_UPD: 2817 case ARM::VLD4q32_UPD: 2818 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2819 return MCDisassembler::Fail; 2820 break; 2821 default: 2822 break; 2823 } 2824 2825 // Writeback operand 2826 switch (Inst.getOpcode()) { 2827 case ARM::VLD1d8wb_fixed: 2828 case ARM::VLD1d16wb_fixed: 2829 case ARM::VLD1d32wb_fixed: 2830 case ARM::VLD1d64wb_fixed: 2831 case ARM::VLD1d8wb_register: 2832 case ARM::VLD1d16wb_register: 2833 case ARM::VLD1d32wb_register: 2834 case ARM::VLD1d64wb_register: 2835 case ARM::VLD1q8wb_fixed: 2836 case ARM::VLD1q16wb_fixed: 2837 case ARM::VLD1q32wb_fixed: 2838 case ARM::VLD1q64wb_fixed: 2839 case ARM::VLD1q8wb_register: 2840 case ARM::VLD1q16wb_register: 2841 case ARM::VLD1q32wb_register: 2842 case ARM::VLD1q64wb_register: 2843 case ARM::VLD1d8Twb_fixed: 2844 case ARM::VLD1d8Twb_register: 2845 case ARM::VLD1d16Twb_fixed: 2846 case ARM::VLD1d16Twb_register: 2847 case ARM::VLD1d32Twb_fixed: 2848 case ARM::VLD1d32Twb_register: 2849 case ARM::VLD1d64Twb_fixed: 2850 case ARM::VLD1d64Twb_register: 2851 case ARM::VLD1d8Qwb_fixed: 2852 case ARM::VLD1d8Qwb_register: 2853 case ARM::VLD1d16Qwb_fixed: 2854 case ARM::VLD1d16Qwb_register: 2855 case ARM::VLD1d32Qwb_fixed: 2856 case ARM::VLD1d32Qwb_register: 2857 case ARM::VLD1d64Qwb_fixed: 2858 case ARM::VLD1d64Qwb_register: 2859 case ARM::VLD2d8wb_fixed: 2860 case ARM::VLD2d16wb_fixed: 2861 case ARM::VLD2d32wb_fixed: 2862 case ARM::VLD2q8wb_fixed: 2863 case ARM::VLD2q16wb_fixed: 2864 case ARM::VLD2q32wb_fixed: 2865 case ARM::VLD2d8wb_register: 2866 case ARM::VLD2d16wb_register: 2867 case ARM::VLD2d32wb_register: 2868 case ARM::VLD2q8wb_register: 2869 case ARM::VLD2q16wb_register: 2870 case ARM::VLD2q32wb_register: 2871 case ARM::VLD2b8wb_fixed: 2872 case ARM::VLD2b16wb_fixed: 2873 case ARM::VLD2b32wb_fixed: 2874 case ARM::VLD2b8wb_register: 2875 case ARM::VLD2b16wb_register: 2876 case ARM::VLD2b32wb_register: 2877 Inst.addOperand(MCOperand::createImm(0)); 2878 break; 2879 case ARM::VLD3d8_UPD: 2880 case ARM::VLD3d16_UPD: 2881 case ARM::VLD3d32_UPD: 2882 case ARM::VLD3q8_UPD: 2883 case ARM::VLD3q16_UPD: 2884 case ARM::VLD3q32_UPD: 2885 case ARM::VLD4d8_UPD: 2886 case ARM::VLD4d16_UPD: 2887 case ARM::VLD4d32_UPD: 2888 case ARM::VLD4q8_UPD: 2889 case ARM::VLD4q16_UPD: 2890 case ARM::VLD4q32_UPD: 2891 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2892 return MCDisassembler::Fail; 2893 break; 2894 default: 2895 break; 2896 } 2897 2898 // AddrMode6 Base (register+alignment) 2899 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2900 return MCDisassembler::Fail; 2901 2902 // AddrMode6 Offset (register) 2903 switch (Inst.getOpcode()) { 2904 default: 2905 // The below have been updated to have explicit am6offset split 2906 // between fixed and register offset. For those instructions not 2907 // yet updated, we need to add an additional reg0 operand for the 2908 // fixed variant. 2909 // 2910 // The fixed offset encodes as Rm == 0xd, so we check for that. 2911 if (Rm == 0xd) { 2912 Inst.addOperand(MCOperand::createReg(0)); 2913 break; 2914 } 2915 // Fall through to handle the register offset variant. 2916 LLVM_FALLTHROUGH; 2917 case ARM::VLD1d8wb_fixed: 2918 case ARM::VLD1d16wb_fixed: 2919 case ARM::VLD1d32wb_fixed: 2920 case ARM::VLD1d64wb_fixed: 2921 case ARM::VLD1d8Twb_fixed: 2922 case ARM::VLD1d16Twb_fixed: 2923 case ARM::VLD1d32Twb_fixed: 2924 case ARM::VLD1d64Twb_fixed: 2925 case ARM::VLD1d8Qwb_fixed: 2926 case ARM::VLD1d16Qwb_fixed: 2927 case ARM::VLD1d32Qwb_fixed: 2928 case ARM::VLD1d64Qwb_fixed: 2929 case ARM::VLD1d8wb_register: 2930 case ARM::VLD1d16wb_register: 2931 case ARM::VLD1d32wb_register: 2932 case ARM::VLD1d64wb_register: 2933 case ARM::VLD1q8wb_fixed: 2934 case ARM::VLD1q16wb_fixed: 2935 case ARM::VLD1q32wb_fixed: 2936 case ARM::VLD1q64wb_fixed: 2937 case ARM::VLD1q8wb_register: 2938 case ARM::VLD1q16wb_register: 2939 case ARM::VLD1q32wb_register: 2940 case ARM::VLD1q64wb_register: 2941 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2942 // variant encodes Rm == 0xf. Anything else is a register offset post- 2943 // increment and we need to add the register operand to the instruction. 2944 if (Rm != 0xD && Rm != 0xF && 2945 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2946 return MCDisassembler::Fail; 2947 break; 2948 case ARM::VLD2d8wb_fixed: 2949 case ARM::VLD2d16wb_fixed: 2950 case ARM::VLD2d32wb_fixed: 2951 case ARM::VLD2b8wb_fixed: 2952 case ARM::VLD2b16wb_fixed: 2953 case ARM::VLD2b32wb_fixed: 2954 case ARM::VLD2q8wb_fixed: 2955 case ARM::VLD2q16wb_fixed: 2956 case ARM::VLD2q32wb_fixed: 2957 break; 2958 } 2959 2960 return S; 2961 } 2962 2963 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2964 uint64_t Address, const void *Decoder) { 2965 unsigned type = fieldFromInstruction(Insn, 8, 4); 2966 unsigned align = fieldFromInstruction(Insn, 4, 2); 2967 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2968 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2969 if (type == 10 && align == 3) return MCDisassembler::Fail; 2970 2971 unsigned load = fieldFromInstruction(Insn, 21, 1); 2972 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2973 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2974 } 2975 2976 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2977 uint64_t Address, const void *Decoder) { 2978 unsigned size = fieldFromInstruction(Insn, 6, 2); 2979 if (size == 3) return MCDisassembler::Fail; 2980 2981 unsigned type = fieldFromInstruction(Insn, 8, 4); 2982 unsigned align = fieldFromInstruction(Insn, 4, 2); 2983 if (type == 8 && align == 3) return MCDisassembler::Fail; 2984 if (type == 9 && align == 3) return MCDisassembler::Fail; 2985 2986 unsigned load = fieldFromInstruction(Insn, 21, 1); 2987 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2988 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2989 } 2990 2991 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2992 uint64_t Address, const void *Decoder) { 2993 unsigned size = fieldFromInstruction(Insn, 6, 2); 2994 if (size == 3) return MCDisassembler::Fail; 2995 2996 unsigned align = fieldFromInstruction(Insn, 4, 2); 2997 if (align & 2) return MCDisassembler::Fail; 2998 2999 unsigned load = fieldFromInstruction(Insn, 21, 1); 3000 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3001 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3002 } 3003 3004 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3005 uint64_t Address, const void *Decoder) { 3006 unsigned size = fieldFromInstruction(Insn, 6, 2); 3007 if (size == 3) return MCDisassembler::Fail; 3008 3009 unsigned load = fieldFromInstruction(Insn, 21, 1); 3010 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3011 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3012 } 3013 3014 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3015 uint64_t Address, const void *Decoder) { 3016 DecodeStatus S = MCDisassembler::Success; 3017 3018 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3019 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3020 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3021 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3022 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3023 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3024 3025 // Writeback Operand 3026 switch (Inst.getOpcode()) { 3027 case ARM::VST1d8wb_fixed: 3028 case ARM::VST1d16wb_fixed: 3029 case ARM::VST1d32wb_fixed: 3030 case ARM::VST1d64wb_fixed: 3031 case ARM::VST1d8wb_register: 3032 case ARM::VST1d16wb_register: 3033 case ARM::VST1d32wb_register: 3034 case ARM::VST1d64wb_register: 3035 case ARM::VST1q8wb_fixed: 3036 case ARM::VST1q16wb_fixed: 3037 case ARM::VST1q32wb_fixed: 3038 case ARM::VST1q64wb_fixed: 3039 case ARM::VST1q8wb_register: 3040 case ARM::VST1q16wb_register: 3041 case ARM::VST1q32wb_register: 3042 case ARM::VST1q64wb_register: 3043 case ARM::VST1d8Twb_fixed: 3044 case ARM::VST1d16Twb_fixed: 3045 case ARM::VST1d32Twb_fixed: 3046 case ARM::VST1d64Twb_fixed: 3047 case ARM::VST1d8Twb_register: 3048 case ARM::VST1d16Twb_register: 3049 case ARM::VST1d32Twb_register: 3050 case ARM::VST1d64Twb_register: 3051 case ARM::VST1d8Qwb_fixed: 3052 case ARM::VST1d16Qwb_fixed: 3053 case ARM::VST1d32Qwb_fixed: 3054 case ARM::VST1d64Qwb_fixed: 3055 case ARM::VST1d8Qwb_register: 3056 case ARM::VST1d16Qwb_register: 3057 case ARM::VST1d32Qwb_register: 3058 case ARM::VST1d64Qwb_register: 3059 case ARM::VST2d8wb_fixed: 3060 case ARM::VST2d16wb_fixed: 3061 case ARM::VST2d32wb_fixed: 3062 case ARM::VST2d8wb_register: 3063 case ARM::VST2d16wb_register: 3064 case ARM::VST2d32wb_register: 3065 case ARM::VST2q8wb_fixed: 3066 case ARM::VST2q16wb_fixed: 3067 case ARM::VST2q32wb_fixed: 3068 case ARM::VST2q8wb_register: 3069 case ARM::VST2q16wb_register: 3070 case ARM::VST2q32wb_register: 3071 case ARM::VST2b8wb_fixed: 3072 case ARM::VST2b16wb_fixed: 3073 case ARM::VST2b32wb_fixed: 3074 case ARM::VST2b8wb_register: 3075 case ARM::VST2b16wb_register: 3076 case ARM::VST2b32wb_register: 3077 if (Rm == 0xF) 3078 return MCDisassembler::Fail; 3079 Inst.addOperand(MCOperand::createImm(0)); 3080 break; 3081 case ARM::VST3d8_UPD: 3082 case ARM::VST3d16_UPD: 3083 case ARM::VST3d32_UPD: 3084 case ARM::VST3q8_UPD: 3085 case ARM::VST3q16_UPD: 3086 case ARM::VST3q32_UPD: 3087 case ARM::VST4d8_UPD: 3088 case ARM::VST4d16_UPD: 3089 case ARM::VST4d32_UPD: 3090 case ARM::VST4q8_UPD: 3091 case ARM::VST4q16_UPD: 3092 case ARM::VST4q32_UPD: 3093 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3094 return MCDisassembler::Fail; 3095 break; 3096 default: 3097 break; 3098 } 3099 3100 // AddrMode6 Base (register+alignment) 3101 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3102 return MCDisassembler::Fail; 3103 3104 // AddrMode6 Offset (register) 3105 switch (Inst.getOpcode()) { 3106 default: 3107 if (Rm == 0xD) 3108 Inst.addOperand(MCOperand::createReg(0)); 3109 else if (Rm != 0xF) { 3110 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3111 return MCDisassembler::Fail; 3112 } 3113 break; 3114 case ARM::VST1d8wb_fixed: 3115 case ARM::VST1d16wb_fixed: 3116 case ARM::VST1d32wb_fixed: 3117 case ARM::VST1d64wb_fixed: 3118 case ARM::VST1q8wb_fixed: 3119 case ARM::VST1q16wb_fixed: 3120 case ARM::VST1q32wb_fixed: 3121 case ARM::VST1q64wb_fixed: 3122 case ARM::VST1d8Twb_fixed: 3123 case ARM::VST1d16Twb_fixed: 3124 case ARM::VST1d32Twb_fixed: 3125 case ARM::VST1d64Twb_fixed: 3126 case ARM::VST1d8Qwb_fixed: 3127 case ARM::VST1d16Qwb_fixed: 3128 case ARM::VST1d32Qwb_fixed: 3129 case ARM::VST1d64Qwb_fixed: 3130 case ARM::VST2d8wb_fixed: 3131 case ARM::VST2d16wb_fixed: 3132 case ARM::VST2d32wb_fixed: 3133 case ARM::VST2q8wb_fixed: 3134 case ARM::VST2q16wb_fixed: 3135 case ARM::VST2q32wb_fixed: 3136 case ARM::VST2b8wb_fixed: 3137 case ARM::VST2b16wb_fixed: 3138 case ARM::VST2b32wb_fixed: 3139 break; 3140 } 3141 3142 // First input register 3143 switch (Inst.getOpcode()) { 3144 case ARM::VST1q16: 3145 case ARM::VST1q32: 3146 case ARM::VST1q64: 3147 case ARM::VST1q8: 3148 case ARM::VST1q16wb_fixed: 3149 case ARM::VST1q16wb_register: 3150 case ARM::VST1q32wb_fixed: 3151 case ARM::VST1q32wb_register: 3152 case ARM::VST1q64wb_fixed: 3153 case ARM::VST1q64wb_register: 3154 case ARM::VST1q8wb_fixed: 3155 case ARM::VST1q8wb_register: 3156 case ARM::VST2d16: 3157 case ARM::VST2d32: 3158 case ARM::VST2d8: 3159 case ARM::VST2d16wb_fixed: 3160 case ARM::VST2d16wb_register: 3161 case ARM::VST2d32wb_fixed: 3162 case ARM::VST2d32wb_register: 3163 case ARM::VST2d8wb_fixed: 3164 case ARM::VST2d8wb_register: 3165 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3166 return MCDisassembler::Fail; 3167 break; 3168 case ARM::VST2b16: 3169 case ARM::VST2b32: 3170 case ARM::VST2b8: 3171 case ARM::VST2b16wb_fixed: 3172 case ARM::VST2b16wb_register: 3173 case ARM::VST2b32wb_fixed: 3174 case ARM::VST2b32wb_register: 3175 case ARM::VST2b8wb_fixed: 3176 case ARM::VST2b8wb_register: 3177 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3178 return MCDisassembler::Fail; 3179 break; 3180 default: 3181 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3182 return MCDisassembler::Fail; 3183 } 3184 3185 // Second input register 3186 switch (Inst.getOpcode()) { 3187 case ARM::VST3d8: 3188 case ARM::VST3d16: 3189 case ARM::VST3d32: 3190 case ARM::VST3d8_UPD: 3191 case ARM::VST3d16_UPD: 3192 case ARM::VST3d32_UPD: 3193 case ARM::VST4d8: 3194 case ARM::VST4d16: 3195 case ARM::VST4d32: 3196 case ARM::VST4d8_UPD: 3197 case ARM::VST4d16_UPD: 3198 case ARM::VST4d32_UPD: 3199 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3200 return MCDisassembler::Fail; 3201 break; 3202 case ARM::VST3q8: 3203 case ARM::VST3q16: 3204 case ARM::VST3q32: 3205 case ARM::VST3q8_UPD: 3206 case ARM::VST3q16_UPD: 3207 case ARM::VST3q32_UPD: 3208 case ARM::VST4q8: 3209 case ARM::VST4q16: 3210 case ARM::VST4q32: 3211 case ARM::VST4q8_UPD: 3212 case ARM::VST4q16_UPD: 3213 case ARM::VST4q32_UPD: 3214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3215 return MCDisassembler::Fail; 3216 break; 3217 default: 3218 break; 3219 } 3220 3221 // Third input register 3222 switch (Inst.getOpcode()) { 3223 case ARM::VST3d8: 3224 case ARM::VST3d16: 3225 case ARM::VST3d32: 3226 case ARM::VST3d8_UPD: 3227 case ARM::VST3d16_UPD: 3228 case ARM::VST3d32_UPD: 3229 case ARM::VST4d8: 3230 case ARM::VST4d16: 3231 case ARM::VST4d32: 3232 case ARM::VST4d8_UPD: 3233 case ARM::VST4d16_UPD: 3234 case ARM::VST4d32_UPD: 3235 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3236 return MCDisassembler::Fail; 3237 break; 3238 case ARM::VST3q8: 3239 case ARM::VST3q16: 3240 case ARM::VST3q32: 3241 case ARM::VST3q8_UPD: 3242 case ARM::VST3q16_UPD: 3243 case ARM::VST3q32_UPD: 3244 case ARM::VST4q8: 3245 case ARM::VST4q16: 3246 case ARM::VST4q32: 3247 case ARM::VST4q8_UPD: 3248 case ARM::VST4q16_UPD: 3249 case ARM::VST4q32_UPD: 3250 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3251 return MCDisassembler::Fail; 3252 break; 3253 default: 3254 break; 3255 } 3256 3257 // Fourth input register 3258 switch (Inst.getOpcode()) { 3259 case ARM::VST4d8: 3260 case ARM::VST4d16: 3261 case ARM::VST4d32: 3262 case ARM::VST4d8_UPD: 3263 case ARM::VST4d16_UPD: 3264 case ARM::VST4d32_UPD: 3265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3266 return MCDisassembler::Fail; 3267 break; 3268 case ARM::VST4q8: 3269 case ARM::VST4q16: 3270 case ARM::VST4q32: 3271 case ARM::VST4q8_UPD: 3272 case ARM::VST4q16_UPD: 3273 case ARM::VST4q32_UPD: 3274 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3275 return MCDisassembler::Fail; 3276 break; 3277 default: 3278 break; 3279 } 3280 3281 return S; 3282 } 3283 3284 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3285 uint64_t Address, const void *Decoder) { 3286 DecodeStatus S = MCDisassembler::Success; 3287 3288 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3289 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3290 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3291 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3292 unsigned align = fieldFromInstruction(Insn, 4, 1); 3293 unsigned size = fieldFromInstruction(Insn, 6, 2); 3294 3295 if (size == 0 && align == 1) 3296 return MCDisassembler::Fail; 3297 align *= (1 << size); 3298 3299 switch (Inst.getOpcode()) { 3300 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3301 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3302 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3303 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3304 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3305 return MCDisassembler::Fail; 3306 break; 3307 default: 3308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3309 return MCDisassembler::Fail; 3310 break; 3311 } 3312 if (Rm != 0xF) { 3313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3314 return MCDisassembler::Fail; 3315 } 3316 3317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3318 return MCDisassembler::Fail; 3319 Inst.addOperand(MCOperand::createImm(align)); 3320 3321 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3322 // variant encodes Rm == 0xf. Anything else is a register offset post- 3323 // increment and we need to add the register operand to the instruction. 3324 if (Rm != 0xD && Rm != 0xF && 3325 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 3328 return S; 3329 } 3330 3331 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3332 uint64_t Address, const void *Decoder) { 3333 DecodeStatus S = MCDisassembler::Success; 3334 3335 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3336 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3337 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3338 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3339 unsigned align = fieldFromInstruction(Insn, 4, 1); 3340 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3341 align *= 2*size; 3342 3343 switch (Inst.getOpcode()) { 3344 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3345 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3346 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3347 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3348 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3349 return MCDisassembler::Fail; 3350 break; 3351 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3352 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3353 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3354 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3355 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3356 return MCDisassembler::Fail; 3357 break; 3358 default: 3359 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3360 return MCDisassembler::Fail; 3361 break; 3362 } 3363 3364 if (Rm != 0xF) 3365 Inst.addOperand(MCOperand::createImm(0)); 3366 3367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3368 return MCDisassembler::Fail; 3369 Inst.addOperand(MCOperand::createImm(align)); 3370 3371 if (Rm != 0xD && Rm != 0xF) { 3372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 } 3375 3376 return S; 3377 } 3378 3379 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3380 uint64_t Address, const void *Decoder) { 3381 DecodeStatus S = MCDisassembler::Success; 3382 3383 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3384 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3385 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3386 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3387 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3388 3389 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3390 return MCDisassembler::Fail; 3391 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3392 return MCDisassembler::Fail; 3393 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3394 return MCDisassembler::Fail; 3395 if (Rm != 0xF) { 3396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3397 return MCDisassembler::Fail; 3398 } 3399 3400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3401 return MCDisassembler::Fail; 3402 Inst.addOperand(MCOperand::createImm(0)); 3403 3404 if (Rm == 0xD) 3405 Inst.addOperand(MCOperand::createReg(0)); 3406 else if (Rm != 0xF) { 3407 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3408 return MCDisassembler::Fail; 3409 } 3410 3411 return S; 3412 } 3413 3414 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3415 uint64_t Address, const void *Decoder) { 3416 DecodeStatus S = MCDisassembler::Success; 3417 3418 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3419 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3420 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3421 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3422 unsigned size = fieldFromInstruction(Insn, 6, 2); 3423 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3424 unsigned align = fieldFromInstruction(Insn, 4, 1); 3425 3426 if (size == 0x3) { 3427 if (align == 0) 3428 return MCDisassembler::Fail; 3429 align = 16; 3430 } else { 3431 if (size == 2) { 3432 align *= 8; 3433 } else { 3434 size = 1 << size; 3435 align *= 4*size; 3436 } 3437 } 3438 3439 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3440 return MCDisassembler::Fail; 3441 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3444 return MCDisassembler::Fail; 3445 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3446 return MCDisassembler::Fail; 3447 if (Rm != 0xF) { 3448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3449 return MCDisassembler::Fail; 3450 } 3451 3452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3453 return MCDisassembler::Fail; 3454 Inst.addOperand(MCOperand::createImm(align)); 3455 3456 if (Rm == 0xD) 3457 Inst.addOperand(MCOperand::createReg(0)); 3458 else if (Rm != 0xF) { 3459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3460 return MCDisassembler::Fail; 3461 } 3462 3463 return S; 3464 } 3465 3466 static DecodeStatus 3467 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3468 uint64_t Address, const void *Decoder) { 3469 DecodeStatus S = MCDisassembler::Success; 3470 3471 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3472 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3473 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3474 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3475 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3476 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3477 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3478 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3479 3480 if (Q) { 3481 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3482 return MCDisassembler::Fail; 3483 } else { 3484 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3485 return MCDisassembler::Fail; 3486 } 3487 3488 Inst.addOperand(MCOperand::createImm(imm)); 3489 3490 switch (Inst.getOpcode()) { 3491 case ARM::VORRiv4i16: 3492 case ARM::VORRiv2i32: 3493 case ARM::VBICiv4i16: 3494 case ARM::VBICiv2i32: 3495 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3496 return MCDisassembler::Fail; 3497 break; 3498 case ARM::VORRiv8i16: 3499 case ARM::VORRiv4i32: 3500 case ARM::VBICiv8i16: 3501 case ARM::VBICiv4i32: 3502 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3503 return MCDisassembler::Fail; 3504 break; 3505 default: 3506 break; 3507 } 3508 3509 return S; 3510 } 3511 3512 static DecodeStatus 3513 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3514 uint64_t Address, const void *Decoder) { 3515 DecodeStatus S = MCDisassembler::Success; 3516 3517 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3518 fieldFromInstruction(Insn, 13, 3)); 3519 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3520 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3521 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3522 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3523 imm |= cmode << 8; 3524 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3525 3526 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3527 return MCDisassembler::Fail; 3528 3529 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3530 return MCDisassembler::Fail; 3531 3532 Inst.addOperand(MCOperand::createImm(imm)); 3533 3534 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3535 Inst.addOperand(MCOperand::createReg(0)); 3536 Inst.addOperand(MCOperand::createImm(0)); 3537 3538 return S; 3539 } 3540 3541 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3542 uint64_t Address, const void *Decoder) { 3543 DecodeStatus S = MCDisassembler::Success; 3544 3545 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3546 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3547 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3548 return MCDisassembler::Fail; 3549 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3550 3551 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3552 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3553 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3554 return MCDisassembler::Fail; 3555 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3556 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3557 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3558 return MCDisassembler::Fail; 3559 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3560 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3561 Inst.addOperand(MCOperand::createImm(Qd)); 3562 3563 return S; 3564 } 3565 3566 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3567 uint64_t Address, const void *Decoder) { 3568 DecodeStatus S = MCDisassembler::Success; 3569 3570 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3571 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3572 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3573 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3574 unsigned size = fieldFromInstruction(Insn, 18, 2); 3575 3576 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3577 return MCDisassembler::Fail; 3578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3579 return MCDisassembler::Fail; 3580 Inst.addOperand(MCOperand::createImm(8 << size)); 3581 3582 return S; 3583 } 3584 3585 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3586 uint64_t Address, const void *Decoder) { 3587 Inst.addOperand(MCOperand::createImm(8 - Val)); 3588 return MCDisassembler::Success; 3589 } 3590 3591 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3592 uint64_t Address, const void *Decoder) { 3593 Inst.addOperand(MCOperand::createImm(16 - Val)); 3594 return MCDisassembler::Success; 3595 } 3596 3597 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3598 uint64_t Address, const void *Decoder) { 3599 Inst.addOperand(MCOperand::createImm(32 - Val)); 3600 return MCDisassembler::Success; 3601 } 3602 3603 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3604 uint64_t Address, const void *Decoder) { 3605 Inst.addOperand(MCOperand::createImm(64 - Val)); 3606 return MCDisassembler::Success; 3607 } 3608 3609 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3610 uint64_t Address, const void *Decoder) { 3611 DecodeStatus S = MCDisassembler::Success; 3612 3613 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3614 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3615 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3616 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3617 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3618 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3619 unsigned op = fieldFromInstruction(Insn, 6, 1); 3620 3621 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3622 return MCDisassembler::Fail; 3623 if (op) { 3624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3625 return MCDisassembler::Fail; // Writeback 3626 } 3627 3628 switch (Inst.getOpcode()) { 3629 case ARM::VTBL2: 3630 case ARM::VTBX2: 3631 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 break; 3634 default: 3635 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 } 3638 3639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3640 return MCDisassembler::Fail; 3641 3642 return S; 3643 } 3644 3645 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3646 uint64_t Address, const void *Decoder) { 3647 DecodeStatus S = MCDisassembler::Success; 3648 3649 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3650 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3651 3652 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3653 return MCDisassembler::Fail; 3654 3655 switch(Inst.getOpcode()) { 3656 default: 3657 return MCDisassembler::Fail; 3658 case ARM::tADR: 3659 break; // tADR does not explicitly represent the PC as an operand. 3660 case ARM::tADDrSPi: 3661 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3662 break; 3663 } 3664 3665 Inst.addOperand(MCOperand::createImm(imm)); 3666 return S; 3667 } 3668 3669 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3670 uint64_t Address, const void *Decoder) { 3671 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3672 true, 2, Inst, Decoder)) 3673 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3674 return MCDisassembler::Success; 3675 } 3676 3677 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3678 uint64_t Address, const void *Decoder) { 3679 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3680 true, 4, Inst, Decoder)) 3681 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3682 return MCDisassembler::Success; 3683 } 3684 3685 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3686 uint64_t Address, const void *Decoder) { 3687 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3688 true, 2, Inst, Decoder)) 3689 Inst.addOperand(MCOperand::createImm(Val << 1)); 3690 return MCDisassembler::Success; 3691 } 3692 3693 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3694 uint64_t Address, const void *Decoder) { 3695 DecodeStatus S = MCDisassembler::Success; 3696 3697 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3698 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3699 3700 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3701 return MCDisassembler::Fail; 3702 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3703 return MCDisassembler::Fail; 3704 3705 return S; 3706 } 3707 3708 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3709 uint64_t Address, const void *Decoder) { 3710 DecodeStatus S = MCDisassembler::Success; 3711 3712 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3713 unsigned imm = fieldFromInstruction(Val, 3, 5); 3714 3715 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3716 return MCDisassembler::Fail; 3717 Inst.addOperand(MCOperand::createImm(imm)); 3718 3719 return S; 3720 } 3721 3722 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3723 uint64_t Address, const void *Decoder) { 3724 unsigned imm = Val << 2; 3725 3726 Inst.addOperand(MCOperand::createImm(imm)); 3727 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3728 3729 return MCDisassembler::Success; 3730 } 3731 3732 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3733 uint64_t Address, const void *Decoder) { 3734 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3735 Inst.addOperand(MCOperand::createImm(Val)); 3736 3737 return MCDisassembler::Success; 3738 } 3739 3740 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3741 uint64_t Address, const void *Decoder) { 3742 DecodeStatus S = MCDisassembler::Success; 3743 3744 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3745 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3746 unsigned imm = fieldFromInstruction(Val, 0, 2); 3747 3748 // Thumb stores cannot use PC as dest register. 3749 switch (Inst.getOpcode()) { 3750 case ARM::t2STRHs: 3751 case ARM::t2STRBs: 3752 case ARM::t2STRs: 3753 if (Rn == 15) 3754 return MCDisassembler::Fail; 3755 break; 3756 default: 3757 break; 3758 } 3759 3760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3761 return MCDisassembler::Fail; 3762 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3763 return MCDisassembler::Fail; 3764 Inst.addOperand(MCOperand::createImm(imm)); 3765 3766 return S; 3767 } 3768 3769 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3770 uint64_t Address, const void *Decoder) { 3771 DecodeStatus S = MCDisassembler::Success; 3772 3773 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3774 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3775 3776 const FeatureBitset &featureBits = 3777 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3778 3779 bool hasMP = featureBits[ARM::FeatureMP]; 3780 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3781 3782 if (Rn == 15) { 3783 switch (Inst.getOpcode()) { 3784 case ARM::t2LDRBs: 3785 Inst.setOpcode(ARM::t2LDRBpci); 3786 break; 3787 case ARM::t2LDRHs: 3788 Inst.setOpcode(ARM::t2LDRHpci); 3789 break; 3790 case ARM::t2LDRSHs: 3791 Inst.setOpcode(ARM::t2LDRSHpci); 3792 break; 3793 case ARM::t2LDRSBs: 3794 Inst.setOpcode(ARM::t2LDRSBpci); 3795 break; 3796 case ARM::t2LDRs: 3797 Inst.setOpcode(ARM::t2LDRpci); 3798 break; 3799 case ARM::t2PLDs: 3800 Inst.setOpcode(ARM::t2PLDpci); 3801 break; 3802 case ARM::t2PLIs: 3803 Inst.setOpcode(ARM::t2PLIpci); 3804 break; 3805 default: 3806 return MCDisassembler::Fail; 3807 } 3808 3809 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3810 } 3811 3812 if (Rt == 15) { 3813 switch (Inst.getOpcode()) { 3814 case ARM::t2LDRSHs: 3815 return MCDisassembler::Fail; 3816 case ARM::t2LDRHs: 3817 Inst.setOpcode(ARM::t2PLDWs); 3818 break; 3819 case ARM::t2LDRSBs: 3820 Inst.setOpcode(ARM::t2PLIs); 3821 break; 3822 default: 3823 break; 3824 } 3825 } 3826 3827 switch (Inst.getOpcode()) { 3828 case ARM::t2PLDs: 3829 break; 3830 case ARM::t2PLIs: 3831 if (!hasV7Ops) 3832 return MCDisassembler::Fail; 3833 break; 3834 case ARM::t2PLDWs: 3835 if (!hasV7Ops || !hasMP) 3836 return MCDisassembler::Fail; 3837 break; 3838 default: 3839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3840 return MCDisassembler::Fail; 3841 } 3842 3843 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3844 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3845 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3846 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3847 return MCDisassembler::Fail; 3848 3849 return S; 3850 } 3851 3852 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3853 uint64_t Address, const void* Decoder) { 3854 DecodeStatus S = MCDisassembler::Success; 3855 3856 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3857 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3858 unsigned U = fieldFromInstruction(Insn, 9, 1); 3859 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3860 imm |= (U << 8); 3861 imm |= (Rn << 9); 3862 unsigned add = fieldFromInstruction(Insn, 9, 1); 3863 3864 const FeatureBitset &featureBits = 3865 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3866 3867 bool hasMP = featureBits[ARM::FeatureMP]; 3868 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3869 3870 if (Rn == 15) { 3871 switch (Inst.getOpcode()) { 3872 case ARM::t2LDRi8: 3873 Inst.setOpcode(ARM::t2LDRpci); 3874 break; 3875 case ARM::t2LDRBi8: 3876 Inst.setOpcode(ARM::t2LDRBpci); 3877 break; 3878 case ARM::t2LDRSBi8: 3879 Inst.setOpcode(ARM::t2LDRSBpci); 3880 break; 3881 case ARM::t2LDRHi8: 3882 Inst.setOpcode(ARM::t2LDRHpci); 3883 break; 3884 case ARM::t2LDRSHi8: 3885 Inst.setOpcode(ARM::t2LDRSHpci); 3886 break; 3887 case ARM::t2PLDi8: 3888 Inst.setOpcode(ARM::t2PLDpci); 3889 break; 3890 case ARM::t2PLIi8: 3891 Inst.setOpcode(ARM::t2PLIpci); 3892 break; 3893 default: 3894 return MCDisassembler::Fail; 3895 } 3896 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3897 } 3898 3899 if (Rt == 15) { 3900 switch (Inst.getOpcode()) { 3901 case ARM::t2LDRSHi8: 3902 return MCDisassembler::Fail; 3903 case ARM::t2LDRHi8: 3904 if (!add) 3905 Inst.setOpcode(ARM::t2PLDWi8); 3906 break; 3907 case ARM::t2LDRSBi8: 3908 Inst.setOpcode(ARM::t2PLIi8); 3909 break; 3910 default: 3911 break; 3912 } 3913 } 3914 3915 switch (Inst.getOpcode()) { 3916 case ARM::t2PLDi8: 3917 break; 3918 case ARM::t2PLIi8: 3919 if (!hasV7Ops) 3920 return MCDisassembler::Fail; 3921 break; 3922 case ARM::t2PLDWi8: 3923 if (!hasV7Ops || !hasMP) 3924 return MCDisassembler::Fail; 3925 break; 3926 default: 3927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3928 return MCDisassembler::Fail; 3929 } 3930 3931 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3932 return MCDisassembler::Fail; 3933 return S; 3934 } 3935 3936 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3937 uint64_t Address, const void* Decoder) { 3938 DecodeStatus S = MCDisassembler::Success; 3939 3940 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3941 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3942 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3943 imm |= (Rn << 13); 3944 3945 const FeatureBitset &featureBits = 3946 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3947 3948 bool hasMP = featureBits[ARM::FeatureMP]; 3949 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3950 3951 if (Rn == 15) { 3952 switch (Inst.getOpcode()) { 3953 case ARM::t2LDRi12: 3954 Inst.setOpcode(ARM::t2LDRpci); 3955 break; 3956 case ARM::t2LDRHi12: 3957 Inst.setOpcode(ARM::t2LDRHpci); 3958 break; 3959 case ARM::t2LDRSHi12: 3960 Inst.setOpcode(ARM::t2LDRSHpci); 3961 break; 3962 case ARM::t2LDRBi12: 3963 Inst.setOpcode(ARM::t2LDRBpci); 3964 break; 3965 case ARM::t2LDRSBi12: 3966 Inst.setOpcode(ARM::t2LDRSBpci); 3967 break; 3968 case ARM::t2PLDi12: 3969 Inst.setOpcode(ARM::t2PLDpci); 3970 break; 3971 case ARM::t2PLIi12: 3972 Inst.setOpcode(ARM::t2PLIpci); 3973 break; 3974 default: 3975 return MCDisassembler::Fail; 3976 } 3977 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3978 } 3979 3980 if (Rt == 15) { 3981 switch (Inst.getOpcode()) { 3982 case ARM::t2LDRSHi12: 3983 return MCDisassembler::Fail; 3984 case ARM::t2LDRHi12: 3985 Inst.setOpcode(ARM::t2PLDWi12); 3986 break; 3987 case ARM::t2LDRSBi12: 3988 Inst.setOpcode(ARM::t2PLIi12); 3989 break; 3990 default: 3991 break; 3992 } 3993 } 3994 3995 switch (Inst.getOpcode()) { 3996 case ARM::t2PLDi12: 3997 break; 3998 case ARM::t2PLIi12: 3999 if (!hasV7Ops) 4000 return MCDisassembler::Fail; 4001 break; 4002 case ARM::t2PLDWi12: 4003 if (!hasV7Ops || !hasMP) 4004 return MCDisassembler::Fail; 4005 break; 4006 default: 4007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4008 return MCDisassembler::Fail; 4009 } 4010 4011 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 return S; 4014 } 4015 4016 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4017 uint64_t Address, const void* Decoder) { 4018 DecodeStatus S = MCDisassembler::Success; 4019 4020 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4021 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4022 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4023 imm |= (Rn << 9); 4024 4025 if (Rn == 15) { 4026 switch (Inst.getOpcode()) { 4027 case ARM::t2LDRT: 4028 Inst.setOpcode(ARM::t2LDRpci); 4029 break; 4030 case ARM::t2LDRBT: 4031 Inst.setOpcode(ARM::t2LDRBpci); 4032 break; 4033 case ARM::t2LDRHT: 4034 Inst.setOpcode(ARM::t2LDRHpci); 4035 break; 4036 case ARM::t2LDRSBT: 4037 Inst.setOpcode(ARM::t2LDRSBpci); 4038 break; 4039 case ARM::t2LDRSHT: 4040 Inst.setOpcode(ARM::t2LDRSHpci); 4041 break; 4042 default: 4043 return MCDisassembler::Fail; 4044 } 4045 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4046 } 4047 4048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4049 return MCDisassembler::Fail; 4050 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4051 return MCDisassembler::Fail; 4052 return S; 4053 } 4054 4055 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4056 uint64_t Address, const void* Decoder) { 4057 DecodeStatus S = MCDisassembler::Success; 4058 4059 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4060 unsigned U = fieldFromInstruction(Insn, 23, 1); 4061 int imm = fieldFromInstruction(Insn, 0, 12); 4062 4063 const FeatureBitset &featureBits = 4064 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4065 4066 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4067 4068 if (Rt == 15) { 4069 switch (Inst.getOpcode()) { 4070 case ARM::t2LDRBpci: 4071 case ARM::t2LDRHpci: 4072 Inst.setOpcode(ARM::t2PLDpci); 4073 break; 4074 case ARM::t2LDRSBpci: 4075 Inst.setOpcode(ARM::t2PLIpci); 4076 break; 4077 case ARM::t2LDRSHpci: 4078 return MCDisassembler::Fail; 4079 default: 4080 break; 4081 } 4082 } 4083 4084 switch(Inst.getOpcode()) { 4085 case ARM::t2PLDpci: 4086 break; 4087 case ARM::t2PLIpci: 4088 if (!hasV7Ops) 4089 return MCDisassembler::Fail; 4090 break; 4091 default: 4092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 } 4095 4096 if (!U) { 4097 // Special case for #-0. 4098 if (imm == 0) 4099 imm = INT32_MIN; 4100 else 4101 imm = -imm; 4102 } 4103 Inst.addOperand(MCOperand::createImm(imm)); 4104 4105 return S; 4106 } 4107 4108 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4109 uint64_t Address, const void *Decoder) { 4110 if (Val == 0) 4111 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4112 else { 4113 int imm = Val & 0xFF; 4114 4115 if (!(Val & 0x100)) imm *= -1; 4116 Inst.addOperand(MCOperand::createImm(imm * 4)); 4117 } 4118 4119 return MCDisassembler::Success; 4120 } 4121 4122 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4123 const void *Decoder) { 4124 if (Val == 0) 4125 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4126 else { 4127 int imm = Val & 0x7F; 4128 4129 if (!(Val & 0x80)) 4130 imm *= -1; 4131 Inst.addOperand(MCOperand::createImm(imm * 4)); 4132 } 4133 4134 return MCDisassembler::Success; 4135 } 4136 4137 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4138 uint64_t Address, const void *Decoder) { 4139 DecodeStatus S = MCDisassembler::Success; 4140 4141 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4142 unsigned imm = fieldFromInstruction(Val, 0, 9); 4143 4144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4145 return MCDisassembler::Fail; 4146 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4147 return MCDisassembler::Fail; 4148 4149 return S; 4150 } 4151 4152 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4153 uint64_t Address, 4154 const void *Decoder) { 4155 DecodeStatus S = MCDisassembler::Success; 4156 4157 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4158 unsigned imm = fieldFromInstruction(Val, 0, 8); 4159 4160 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4161 return MCDisassembler::Fail; 4162 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4163 return MCDisassembler::Fail; 4164 4165 return S; 4166 } 4167 4168 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4169 uint64_t Address, const void *Decoder) { 4170 DecodeStatus S = MCDisassembler::Success; 4171 4172 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4173 unsigned imm = fieldFromInstruction(Val, 0, 8); 4174 4175 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 4178 Inst.addOperand(MCOperand::createImm(imm)); 4179 4180 return S; 4181 } 4182 4183 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4184 uint64_t Address, const void *Decoder) { 4185 int imm = Val & 0xFF; 4186 if (Val == 0) 4187 imm = INT32_MIN; 4188 else if (!(Val & 0x100)) 4189 imm *= -1; 4190 Inst.addOperand(MCOperand::createImm(imm)); 4191 4192 return MCDisassembler::Success; 4193 } 4194 4195 template<int shift> 4196 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4197 uint64_t Address, const void *Decoder) { 4198 int imm = Val & 0x7F; 4199 if (Val == 0) 4200 imm = INT32_MIN; 4201 else if (!(Val & 0x80)) 4202 imm *= -1; 4203 if (imm != INT32_MIN) 4204 imm *= (1U << shift); 4205 Inst.addOperand(MCOperand::createImm(imm)); 4206 4207 return MCDisassembler::Success; 4208 } 4209 4210 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4211 uint64_t Address, const void *Decoder) { 4212 DecodeStatus S = MCDisassembler::Success; 4213 4214 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4215 unsigned imm = fieldFromInstruction(Val, 0, 9); 4216 4217 // Thumb stores cannot use PC as dest register. 4218 switch (Inst.getOpcode()) { 4219 case ARM::t2STRT: 4220 case ARM::t2STRBT: 4221 case ARM::t2STRHT: 4222 case ARM::t2STRi8: 4223 case ARM::t2STRHi8: 4224 case ARM::t2STRBi8: 4225 if (Rn == 15) 4226 return MCDisassembler::Fail; 4227 break; 4228 default: 4229 break; 4230 } 4231 4232 // Some instructions always use an additive offset. 4233 switch (Inst.getOpcode()) { 4234 case ARM::t2LDRT: 4235 case ARM::t2LDRBT: 4236 case ARM::t2LDRHT: 4237 case ARM::t2LDRSBT: 4238 case ARM::t2LDRSHT: 4239 case ARM::t2STRT: 4240 case ARM::t2STRBT: 4241 case ARM::t2STRHT: 4242 imm |= 0x100; 4243 break; 4244 default: 4245 break; 4246 } 4247 4248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4249 return MCDisassembler::Fail; 4250 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4251 return MCDisassembler::Fail; 4252 4253 return S; 4254 } 4255 4256 template<int shift> 4257 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4258 uint64_t Address, 4259 const void *Decoder) { 4260 DecodeStatus S = MCDisassembler::Success; 4261 4262 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4263 unsigned imm = fieldFromInstruction(Val, 0, 8); 4264 4265 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4266 return MCDisassembler::Fail; 4267 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 4270 return S; 4271 } 4272 4273 template<int shift, int WriteBack> 4274 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4275 uint64_t Address, 4276 const void *Decoder) { 4277 DecodeStatus S = MCDisassembler::Success; 4278 4279 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4280 unsigned imm = fieldFromInstruction(Val, 0, 8); 4281 if (WriteBack) { 4282 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4283 return MCDisassembler::Fail; 4284 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4285 return MCDisassembler::Fail; 4286 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4287 return MCDisassembler::Fail; 4288 4289 return S; 4290 } 4291 4292 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4293 uint64_t Address, const void *Decoder) { 4294 DecodeStatus S = MCDisassembler::Success; 4295 4296 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4297 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4298 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4299 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4300 addr |= Rn << 9; 4301 unsigned load = fieldFromInstruction(Insn, 20, 1); 4302 4303 if (Rn == 15) { 4304 switch (Inst.getOpcode()) { 4305 case ARM::t2LDR_PRE: 4306 case ARM::t2LDR_POST: 4307 Inst.setOpcode(ARM::t2LDRpci); 4308 break; 4309 case ARM::t2LDRB_PRE: 4310 case ARM::t2LDRB_POST: 4311 Inst.setOpcode(ARM::t2LDRBpci); 4312 break; 4313 case ARM::t2LDRH_PRE: 4314 case ARM::t2LDRH_POST: 4315 Inst.setOpcode(ARM::t2LDRHpci); 4316 break; 4317 case ARM::t2LDRSB_PRE: 4318 case ARM::t2LDRSB_POST: 4319 if (Rt == 15) 4320 Inst.setOpcode(ARM::t2PLIpci); 4321 else 4322 Inst.setOpcode(ARM::t2LDRSBpci); 4323 break; 4324 case ARM::t2LDRSH_PRE: 4325 case ARM::t2LDRSH_POST: 4326 Inst.setOpcode(ARM::t2LDRSHpci); 4327 break; 4328 default: 4329 return MCDisassembler::Fail; 4330 } 4331 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4332 } 4333 4334 if (!load) { 4335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4336 return MCDisassembler::Fail; 4337 } 4338 4339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4340 return MCDisassembler::Fail; 4341 4342 if (load) { 4343 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4344 return MCDisassembler::Fail; 4345 } 4346 4347 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4348 return MCDisassembler::Fail; 4349 4350 return S; 4351 } 4352 4353 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4354 uint64_t Address, const void *Decoder) { 4355 DecodeStatus S = MCDisassembler::Success; 4356 4357 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4358 unsigned imm = fieldFromInstruction(Val, 0, 12); 4359 4360 // Thumb stores cannot use PC as dest register. 4361 switch (Inst.getOpcode()) { 4362 case ARM::t2STRi12: 4363 case ARM::t2STRBi12: 4364 case ARM::t2STRHi12: 4365 if (Rn == 15) 4366 return MCDisassembler::Fail; 4367 break; 4368 default: 4369 break; 4370 } 4371 4372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4373 return MCDisassembler::Fail; 4374 Inst.addOperand(MCOperand::createImm(imm)); 4375 4376 return S; 4377 } 4378 4379 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4380 uint64_t Address, const void *Decoder) { 4381 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4382 4383 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4384 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4385 Inst.addOperand(MCOperand::createImm(imm)); 4386 4387 return MCDisassembler::Success; 4388 } 4389 4390 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4391 uint64_t Address, const void *Decoder) { 4392 DecodeStatus S = MCDisassembler::Success; 4393 4394 if (Inst.getOpcode() == ARM::tADDrSP) { 4395 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4396 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4397 4398 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4399 return MCDisassembler::Fail; 4400 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4402 return MCDisassembler::Fail; 4403 } else if (Inst.getOpcode() == ARM::tADDspr) { 4404 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4405 4406 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4407 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4408 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4409 return MCDisassembler::Fail; 4410 } 4411 4412 return S; 4413 } 4414 4415 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4416 uint64_t Address, const void *Decoder) { 4417 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4418 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4419 4420 Inst.addOperand(MCOperand::createImm(imod)); 4421 Inst.addOperand(MCOperand::createImm(flags)); 4422 4423 return MCDisassembler::Success; 4424 } 4425 4426 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4427 uint64_t Address, const void *Decoder) { 4428 DecodeStatus S = MCDisassembler::Success; 4429 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4430 unsigned add = fieldFromInstruction(Insn, 4, 1); 4431 4432 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4433 return MCDisassembler::Fail; 4434 Inst.addOperand(MCOperand::createImm(add)); 4435 4436 return S; 4437 } 4438 4439 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4440 uint64_t Address, const void *Decoder) { 4441 DecodeStatus S = MCDisassembler::Success; 4442 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4443 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4444 4445 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4446 return MCDisassembler::Fail; 4447 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 4450 return S; 4451 } 4452 4453 template<int shift> 4454 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4455 uint64_t Address, const void *Decoder) { 4456 DecodeStatus S = MCDisassembler::Success; 4457 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4458 int imm = fieldFromInstruction(Insn, 0, 7); 4459 4460 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4461 return MCDisassembler::Fail; 4462 4463 if(!fieldFromInstruction(Insn, 7, 1)) { 4464 if (imm == 0) 4465 imm = INT32_MIN; // indicate -0 4466 else 4467 imm *= -1; 4468 } 4469 if (imm != INT32_MIN) 4470 imm *= (1U << shift); 4471 Inst.addOperand(MCOperand::createImm(imm)); 4472 4473 return S; 4474 } 4475 4476 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4477 uint64_t Address, const void *Decoder) { 4478 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4479 // Note only one trailing zero not two. Also the J1 and J2 values are from 4480 // the encoded instruction. So here change to I1 and I2 values via: 4481 // I1 = NOT(J1 EOR S); 4482 // I2 = NOT(J2 EOR S); 4483 // and build the imm32 with two trailing zeros as documented: 4484 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4485 unsigned S = (Val >> 23) & 1; 4486 unsigned J1 = (Val >> 22) & 1; 4487 unsigned J2 = (Val >> 21) & 1; 4488 unsigned I1 = !(J1 ^ S); 4489 unsigned I2 = !(J2 ^ S); 4490 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4491 int imm32 = SignExtend32<25>(tmp << 1); 4492 4493 if (!tryAddingSymbolicOperand(Address, 4494 (Address & ~2u) + imm32 + 4, 4495 true, 4, Inst, Decoder)) 4496 Inst.addOperand(MCOperand::createImm(imm32)); 4497 return MCDisassembler::Success; 4498 } 4499 4500 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4501 uint64_t Address, const void *Decoder) { 4502 if (Val == 0xA || Val == 0xB) 4503 return MCDisassembler::Fail; 4504 4505 const FeatureBitset &featureBits = 4506 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4507 4508 if (!isValidCoprocessorNumber(Val, featureBits)) 4509 return MCDisassembler::Fail; 4510 4511 Inst.addOperand(MCOperand::createImm(Val)); 4512 return MCDisassembler::Success; 4513 } 4514 4515 static DecodeStatus 4516 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4517 uint64_t Address, const void *Decoder) { 4518 DecodeStatus S = MCDisassembler::Success; 4519 4520 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4521 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4522 4523 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4525 return MCDisassembler::Fail; 4526 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4527 return MCDisassembler::Fail; 4528 return S; 4529 } 4530 4531 static DecodeStatus 4532 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4533 uint64_t Address, const void *Decoder) { 4534 DecodeStatus S = MCDisassembler::Success; 4535 4536 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4537 if (pred == 0xE || pred == 0xF) { 4538 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4539 switch (opc) { 4540 default: 4541 return MCDisassembler::Fail; 4542 case 0xf3bf8f4: 4543 Inst.setOpcode(ARM::t2DSB); 4544 break; 4545 case 0xf3bf8f5: 4546 Inst.setOpcode(ARM::t2DMB); 4547 break; 4548 case 0xf3bf8f6: 4549 Inst.setOpcode(ARM::t2ISB); 4550 break; 4551 } 4552 4553 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4554 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4555 } 4556 4557 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4558 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4559 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4560 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4561 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4562 4563 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4564 return MCDisassembler::Fail; 4565 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4566 return MCDisassembler::Fail; 4567 4568 return S; 4569 } 4570 4571 // Decode a shifted immediate operand. These basically consist 4572 // of an 8-bit value, and a 4-bit directive that specifies either 4573 // a splat operation or a rotation. 4574 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4575 uint64_t Address, const void *Decoder) { 4576 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4577 if (ctrl == 0) { 4578 unsigned byte = fieldFromInstruction(Val, 8, 2); 4579 unsigned imm = fieldFromInstruction(Val, 0, 8); 4580 switch (byte) { 4581 case 0: 4582 Inst.addOperand(MCOperand::createImm(imm)); 4583 break; 4584 case 1: 4585 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4586 break; 4587 case 2: 4588 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4589 break; 4590 case 3: 4591 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4592 (imm << 8) | imm)); 4593 break; 4594 } 4595 } else { 4596 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4597 unsigned rot = fieldFromInstruction(Val, 7, 5); 4598 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4599 Inst.addOperand(MCOperand::createImm(imm)); 4600 } 4601 4602 return MCDisassembler::Success; 4603 } 4604 4605 static DecodeStatus 4606 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4607 uint64_t Address, const void *Decoder) { 4608 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4609 true, 2, Inst, Decoder)) 4610 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4611 return MCDisassembler::Success; 4612 } 4613 4614 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4615 uint64_t Address, 4616 const void *Decoder) { 4617 // Val is passed in as S:J1:J2:imm10:imm11 4618 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4619 // the encoded instruction. So here change to I1 and I2 values via: 4620 // I1 = NOT(J1 EOR S); 4621 // I2 = NOT(J2 EOR S); 4622 // and build the imm32 with one trailing zero as documented: 4623 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4624 unsigned S = (Val >> 23) & 1; 4625 unsigned J1 = (Val >> 22) & 1; 4626 unsigned J2 = (Val >> 21) & 1; 4627 unsigned I1 = !(J1 ^ S); 4628 unsigned I2 = !(J2 ^ S); 4629 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4630 int imm32 = SignExtend32<25>(tmp << 1); 4631 4632 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4633 true, 4, Inst, Decoder)) 4634 Inst.addOperand(MCOperand::createImm(imm32)); 4635 return MCDisassembler::Success; 4636 } 4637 4638 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4639 uint64_t Address, const void *Decoder) { 4640 if (Val & ~0xf) 4641 return MCDisassembler::Fail; 4642 4643 Inst.addOperand(MCOperand::createImm(Val)); 4644 return MCDisassembler::Success; 4645 } 4646 4647 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4648 uint64_t Address, const void *Decoder) { 4649 if (Val & ~0xf) 4650 return MCDisassembler::Fail; 4651 4652 Inst.addOperand(MCOperand::createImm(Val)); 4653 return MCDisassembler::Success; 4654 } 4655 4656 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4657 uint64_t Address, const void *Decoder) { 4658 DecodeStatus S = MCDisassembler::Success; 4659 const FeatureBitset &FeatureBits = 4660 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4661 4662 if (FeatureBits[ARM::FeatureMClass]) { 4663 unsigned ValLow = Val & 0xff; 4664 4665 // Validate the SYSm value first. 4666 switch (ValLow) { 4667 case 0: // apsr 4668 case 1: // iapsr 4669 case 2: // eapsr 4670 case 3: // xpsr 4671 case 5: // ipsr 4672 case 6: // epsr 4673 case 7: // iepsr 4674 case 8: // msp 4675 case 9: // psp 4676 case 16: // primask 4677 case 20: // control 4678 break; 4679 case 17: // basepri 4680 case 18: // basepri_max 4681 case 19: // faultmask 4682 if (!(FeatureBits[ARM::HasV7Ops])) 4683 // Values basepri, basepri_max and faultmask are only valid for v7m. 4684 return MCDisassembler::Fail; 4685 break; 4686 case 0x8a: // msplim_ns 4687 case 0x8b: // psplim_ns 4688 case 0x91: // basepri_ns 4689 case 0x93: // faultmask_ns 4690 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4691 return MCDisassembler::Fail; 4692 LLVM_FALLTHROUGH; 4693 case 10: // msplim 4694 case 11: // psplim 4695 case 0x88: // msp_ns 4696 case 0x89: // psp_ns 4697 case 0x90: // primask_ns 4698 case 0x94: // control_ns 4699 case 0x98: // sp_ns 4700 if (!(FeatureBits[ARM::Feature8MSecExt])) 4701 return MCDisassembler::Fail; 4702 break; 4703 default: 4704 // Architecturally defined as unpredictable 4705 S = MCDisassembler::SoftFail; 4706 break; 4707 } 4708 4709 if (Inst.getOpcode() == ARM::t2MSR_M) { 4710 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4711 if (!(FeatureBits[ARM::HasV7Ops])) { 4712 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4713 // unpredictable. 4714 if (Mask != 2) 4715 S = MCDisassembler::SoftFail; 4716 } 4717 else { 4718 // The ARMv7-M architecture stores an additional 2-bit mask value in 4719 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4720 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4721 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4722 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4723 // only if the processor includes the DSP extension. 4724 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4725 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4726 S = MCDisassembler::SoftFail; 4727 } 4728 } 4729 } else { 4730 // A/R class 4731 if (Val == 0) 4732 return MCDisassembler::Fail; 4733 } 4734 Inst.addOperand(MCOperand::createImm(Val)); 4735 return S; 4736 } 4737 4738 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4739 uint64_t Address, const void *Decoder) { 4740 unsigned R = fieldFromInstruction(Val, 5, 1); 4741 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4742 4743 // The table of encodings for these banked registers comes from B9.2.3 of the 4744 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4745 // neater. So by fiat, these values are UNPREDICTABLE: 4746 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4747 return MCDisassembler::Fail; 4748 4749 Inst.addOperand(MCOperand::createImm(Val)); 4750 return MCDisassembler::Success; 4751 } 4752 4753 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4754 uint64_t Address, const void *Decoder) { 4755 DecodeStatus S = MCDisassembler::Success; 4756 4757 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4758 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4759 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4760 4761 if (Rn == 0xF) 4762 S = MCDisassembler::SoftFail; 4763 4764 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4765 return MCDisassembler::Fail; 4766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4767 return MCDisassembler::Fail; 4768 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4769 return MCDisassembler::Fail; 4770 4771 return S; 4772 } 4773 4774 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4775 uint64_t Address, 4776 const void *Decoder) { 4777 DecodeStatus S = MCDisassembler::Success; 4778 4779 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4780 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4781 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4782 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4783 4784 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4785 return MCDisassembler::Fail; 4786 4787 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4788 S = MCDisassembler::SoftFail; 4789 4790 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4791 return MCDisassembler::Fail; 4792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4793 return MCDisassembler::Fail; 4794 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4795 return MCDisassembler::Fail; 4796 4797 return S; 4798 } 4799 4800 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4801 uint64_t Address, const void *Decoder) { 4802 DecodeStatus S = MCDisassembler::Success; 4803 4804 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4805 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4806 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4807 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4808 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4809 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4810 4811 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4812 4813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4814 return MCDisassembler::Fail; 4815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4816 return MCDisassembler::Fail; 4817 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4818 return MCDisassembler::Fail; 4819 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4820 return MCDisassembler::Fail; 4821 4822 return S; 4823 } 4824 4825 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4826 uint64_t Address, const void *Decoder) { 4827 DecodeStatus S = MCDisassembler::Success; 4828 4829 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4830 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4831 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4832 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4833 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4834 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4835 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4836 4837 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4838 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4839 4840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4841 return MCDisassembler::Fail; 4842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4843 return MCDisassembler::Fail; 4844 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4845 return MCDisassembler::Fail; 4846 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4847 return MCDisassembler::Fail; 4848 4849 return S; 4850 } 4851 4852 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4853 uint64_t Address, const void *Decoder) { 4854 DecodeStatus S = MCDisassembler::Success; 4855 4856 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4857 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4858 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4859 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4860 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4861 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4862 4863 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4864 4865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4866 return MCDisassembler::Fail; 4867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4868 return MCDisassembler::Fail; 4869 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4870 return MCDisassembler::Fail; 4871 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4872 return MCDisassembler::Fail; 4873 4874 return S; 4875 } 4876 4877 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4878 uint64_t Address, const void *Decoder) { 4879 DecodeStatus S = MCDisassembler::Success; 4880 4881 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4882 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4883 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4884 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4885 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4886 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4887 4888 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4889 4890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4891 return MCDisassembler::Fail; 4892 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4893 return MCDisassembler::Fail; 4894 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4895 return MCDisassembler::Fail; 4896 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4897 return MCDisassembler::Fail; 4898 4899 return S; 4900 } 4901 4902 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4903 uint64_t Address, const void *Decoder) { 4904 DecodeStatus S = MCDisassembler::Success; 4905 4906 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4907 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4908 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4909 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4910 unsigned size = fieldFromInstruction(Insn, 10, 2); 4911 4912 unsigned align = 0; 4913 unsigned index = 0; 4914 switch (size) { 4915 default: 4916 return MCDisassembler::Fail; 4917 case 0: 4918 if (fieldFromInstruction(Insn, 4, 1)) 4919 return MCDisassembler::Fail; // UNDEFINED 4920 index = fieldFromInstruction(Insn, 5, 3); 4921 break; 4922 case 1: 4923 if (fieldFromInstruction(Insn, 5, 1)) 4924 return MCDisassembler::Fail; // UNDEFINED 4925 index = fieldFromInstruction(Insn, 6, 2); 4926 if (fieldFromInstruction(Insn, 4, 1)) 4927 align = 2; 4928 break; 4929 case 2: 4930 if (fieldFromInstruction(Insn, 6, 1)) 4931 return MCDisassembler::Fail; // UNDEFINED 4932 index = fieldFromInstruction(Insn, 7, 1); 4933 4934 switch (fieldFromInstruction(Insn, 4, 2)) { 4935 case 0 : 4936 align = 0; break; 4937 case 3: 4938 align = 4; break; 4939 default: 4940 return MCDisassembler::Fail; 4941 } 4942 break; 4943 } 4944 4945 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4946 return MCDisassembler::Fail; 4947 if (Rm != 0xF) { // Writeback 4948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4949 return MCDisassembler::Fail; 4950 } 4951 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4952 return MCDisassembler::Fail; 4953 Inst.addOperand(MCOperand::createImm(align)); 4954 if (Rm != 0xF) { 4955 if (Rm != 0xD) { 4956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4957 return MCDisassembler::Fail; 4958 } else 4959 Inst.addOperand(MCOperand::createReg(0)); 4960 } 4961 4962 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4963 return MCDisassembler::Fail; 4964 Inst.addOperand(MCOperand::createImm(index)); 4965 4966 return S; 4967 } 4968 4969 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4970 uint64_t Address, const void *Decoder) { 4971 DecodeStatus S = MCDisassembler::Success; 4972 4973 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4974 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4975 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4976 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4977 unsigned size = fieldFromInstruction(Insn, 10, 2); 4978 4979 unsigned align = 0; 4980 unsigned index = 0; 4981 switch (size) { 4982 default: 4983 return MCDisassembler::Fail; 4984 case 0: 4985 if (fieldFromInstruction(Insn, 4, 1)) 4986 return MCDisassembler::Fail; // UNDEFINED 4987 index = fieldFromInstruction(Insn, 5, 3); 4988 break; 4989 case 1: 4990 if (fieldFromInstruction(Insn, 5, 1)) 4991 return MCDisassembler::Fail; // UNDEFINED 4992 index = fieldFromInstruction(Insn, 6, 2); 4993 if (fieldFromInstruction(Insn, 4, 1)) 4994 align = 2; 4995 break; 4996 case 2: 4997 if (fieldFromInstruction(Insn, 6, 1)) 4998 return MCDisassembler::Fail; // UNDEFINED 4999 index = fieldFromInstruction(Insn, 7, 1); 5000 5001 switch (fieldFromInstruction(Insn, 4, 2)) { 5002 case 0: 5003 align = 0; break; 5004 case 3: 5005 align = 4; break; 5006 default: 5007 return MCDisassembler::Fail; 5008 } 5009 break; 5010 } 5011 5012 if (Rm != 0xF) { // Writeback 5013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5014 return MCDisassembler::Fail; 5015 } 5016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5017 return MCDisassembler::Fail; 5018 Inst.addOperand(MCOperand::createImm(align)); 5019 if (Rm != 0xF) { 5020 if (Rm != 0xD) { 5021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5022 return MCDisassembler::Fail; 5023 } else 5024 Inst.addOperand(MCOperand::createReg(0)); 5025 } 5026 5027 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5028 return MCDisassembler::Fail; 5029 Inst.addOperand(MCOperand::createImm(index)); 5030 5031 return S; 5032 } 5033 5034 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5035 uint64_t Address, const void *Decoder) { 5036 DecodeStatus S = MCDisassembler::Success; 5037 5038 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5039 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5040 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5041 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5042 unsigned size = fieldFromInstruction(Insn, 10, 2); 5043 5044 unsigned align = 0; 5045 unsigned index = 0; 5046 unsigned inc = 1; 5047 switch (size) { 5048 default: 5049 return MCDisassembler::Fail; 5050 case 0: 5051 index = fieldFromInstruction(Insn, 5, 3); 5052 if (fieldFromInstruction(Insn, 4, 1)) 5053 align = 2; 5054 break; 5055 case 1: 5056 index = fieldFromInstruction(Insn, 6, 2); 5057 if (fieldFromInstruction(Insn, 4, 1)) 5058 align = 4; 5059 if (fieldFromInstruction(Insn, 5, 1)) 5060 inc = 2; 5061 break; 5062 case 2: 5063 if (fieldFromInstruction(Insn, 5, 1)) 5064 return MCDisassembler::Fail; // UNDEFINED 5065 index = fieldFromInstruction(Insn, 7, 1); 5066 if (fieldFromInstruction(Insn, 4, 1) != 0) 5067 align = 8; 5068 if (fieldFromInstruction(Insn, 6, 1)) 5069 inc = 2; 5070 break; 5071 } 5072 5073 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5074 return MCDisassembler::Fail; 5075 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5076 return MCDisassembler::Fail; 5077 if (Rm != 0xF) { // Writeback 5078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5079 return MCDisassembler::Fail; 5080 } 5081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5082 return MCDisassembler::Fail; 5083 Inst.addOperand(MCOperand::createImm(align)); 5084 if (Rm != 0xF) { 5085 if (Rm != 0xD) { 5086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5087 return MCDisassembler::Fail; 5088 } else 5089 Inst.addOperand(MCOperand::createReg(0)); 5090 } 5091 5092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5093 return MCDisassembler::Fail; 5094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5095 return MCDisassembler::Fail; 5096 Inst.addOperand(MCOperand::createImm(index)); 5097 5098 return S; 5099 } 5100 5101 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5102 uint64_t Address, const void *Decoder) { 5103 DecodeStatus S = MCDisassembler::Success; 5104 5105 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5106 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5107 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5108 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5109 unsigned size = fieldFromInstruction(Insn, 10, 2); 5110 5111 unsigned align = 0; 5112 unsigned index = 0; 5113 unsigned inc = 1; 5114 switch (size) { 5115 default: 5116 return MCDisassembler::Fail; 5117 case 0: 5118 index = fieldFromInstruction(Insn, 5, 3); 5119 if (fieldFromInstruction(Insn, 4, 1)) 5120 align = 2; 5121 break; 5122 case 1: 5123 index = fieldFromInstruction(Insn, 6, 2); 5124 if (fieldFromInstruction(Insn, 4, 1)) 5125 align = 4; 5126 if (fieldFromInstruction(Insn, 5, 1)) 5127 inc = 2; 5128 break; 5129 case 2: 5130 if (fieldFromInstruction(Insn, 5, 1)) 5131 return MCDisassembler::Fail; // UNDEFINED 5132 index = fieldFromInstruction(Insn, 7, 1); 5133 if (fieldFromInstruction(Insn, 4, 1) != 0) 5134 align = 8; 5135 if (fieldFromInstruction(Insn, 6, 1)) 5136 inc = 2; 5137 break; 5138 } 5139 5140 if (Rm != 0xF) { // Writeback 5141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5142 return MCDisassembler::Fail; 5143 } 5144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5145 return MCDisassembler::Fail; 5146 Inst.addOperand(MCOperand::createImm(align)); 5147 if (Rm != 0xF) { 5148 if (Rm != 0xD) { 5149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5150 return MCDisassembler::Fail; 5151 } else 5152 Inst.addOperand(MCOperand::createReg(0)); 5153 } 5154 5155 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5156 return MCDisassembler::Fail; 5157 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5158 return MCDisassembler::Fail; 5159 Inst.addOperand(MCOperand::createImm(index)); 5160 5161 return S; 5162 } 5163 5164 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5165 uint64_t Address, const void *Decoder) { 5166 DecodeStatus S = MCDisassembler::Success; 5167 5168 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5169 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5170 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5171 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5172 unsigned size = fieldFromInstruction(Insn, 10, 2); 5173 5174 unsigned align = 0; 5175 unsigned index = 0; 5176 unsigned inc = 1; 5177 switch (size) { 5178 default: 5179 return MCDisassembler::Fail; 5180 case 0: 5181 if (fieldFromInstruction(Insn, 4, 1)) 5182 return MCDisassembler::Fail; // UNDEFINED 5183 index = fieldFromInstruction(Insn, 5, 3); 5184 break; 5185 case 1: 5186 if (fieldFromInstruction(Insn, 4, 1)) 5187 return MCDisassembler::Fail; // UNDEFINED 5188 index = fieldFromInstruction(Insn, 6, 2); 5189 if (fieldFromInstruction(Insn, 5, 1)) 5190 inc = 2; 5191 break; 5192 case 2: 5193 if (fieldFromInstruction(Insn, 4, 2)) 5194 return MCDisassembler::Fail; // UNDEFINED 5195 index = fieldFromInstruction(Insn, 7, 1); 5196 if (fieldFromInstruction(Insn, 6, 1)) 5197 inc = 2; 5198 break; 5199 } 5200 5201 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5202 return MCDisassembler::Fail; 5203 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5204 return MCDisassembler::Fail; 5205 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5206 return MCDisassembler::Fail; 5207 5208 if (Rm != 0xF) { // Writeback 5209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5210 return MCDisassembler::Fail; 5211 } 5212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5213 return MCDisassembler::Fail; 5214 Inst.addOperand(MCOperand::createImm(align)); 5215 if (Rm != 0xF) { 5216 if (Rm != 0xD) { 5217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5218 return MCDisassembler::Fail; 5219 } else 5220 Inst.addOperand(MCOperand::createReg(0)); 5221 } 5222 5223 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5224 return MCDisassembler::Fail; 5225 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5226 return MCDisassembler::Fail; 5227 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5228 return MCDisassembler::Fail; 5229 Inst.addOperand(MCOperand::createImm(index)); 5230 5231 return S; 5232 } 5233 5234 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5235 uint64_t Address, const void *Decoder) { 5236 DecodeStatus S = MCDisassembler::Success; 5237 5238 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5239 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5240 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5241 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5242 unsigned size = fieldFromInstruction(Insn, 10, 2); 5243 5244 unsigned align = 0; 5245 unsigned index = 0; 5246 unsigned inc = 1; 5247 switch (size) { 5248 default: 5249 return MCDisassembler::Fail; 5250 case 0: 5251 if (fieldFromInstruction(Insn, 4, 1)) 5252 return MCDisassembler::Fail; // UNDEFINED 5253 index = fieldFromInstruction(Insn, 5, 3); 5254 break; 5255 case 1: 5256 if (fieldFromInstruction(Insn, 4, 1)) 5257 return MCDisassembler::Fail; // UNDEFINED 5258 index = fieldFromInstruction(Insn, 6, 2); 5259 if (fieldFromInstruction(Insn, 5, 1)) 5260 inc = 2; 5261 break; 5262 case 2: 5263 if (fieldFromInstruction(Insn, 4, 2)) 5264 return MCDisassembler::Fail; // UNDEFINED 5265 index = fieldFromInstruction(Insn, 7, 1); 5266 if (fieldFromInstruction(Insn, 6, 1)) 5267 inc = 2; 5268 break; 5269 } 5270 5271 if (Rm != 0xF) { // Writeback 5272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5273 return MCDisassembler::Fail; 5274 } 5275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5276 return MCDisassembler::Fail; 5277 Inst.addOperand(MCOperand::createImm(align)); 5278 if (Rm != 0xF) { 5279 if (Rm != 0xD) { 5280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5281 return MCDisassembler::Fail; 5282 } else 5283 Inst.addOperand(MCOperand::createReg(0)); 5284 } 5285 5286 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5287 return MCDisassembler::Fail; 5288 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5289 return MCDisassembler::Fail; 5290 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5291 return MCDisassembler::Fail; 5292 Inst.addOperand(MCOperand::createImm(index)); 5293 5294 return S; 5295 } 5296 5297 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5298 uint64_t Address, const void *Decoder) { 5299 DecodeStatus S = MCDisassembler::Success; 5300 5301 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5302 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5303 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5304 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5305 unsigned size = fieldFromInstruction(Insn, 10, 2); 5306 5307 unsigned align = 0; 5308 unsigned index = 0; 5309 unsigned inc = 1; 5310 switch (size) { 5311 default: 5312 return MCDisassembler::Fail; 5313 case 0: 5314 if (fieldFromInstruction(Insn, 4, 1)) 5315 align = 4; 5316 index = fieldFromInstruction(Insn, 5, 3); 5317 break; 5318 case 1: 5319 if (fieldFromInstruction(Insn, 4, 1)) 5320 align = 8; 5321 index = fieldFromInstruction(Insn, 6, 2); 5322 if (fieldFromInstruction(Insn, 5, 1)) 5323 inc = 2; 5324 break; 5325 case 2: 5326 switch (fieldFromInstruction(Insn, 4, 2)) { 5327 case 0: 5328 align = 0; break; 5329 case 3: 5330 return MCDisassembler::Fail; 5331 default: 5332 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5333 } 5334 5335 index = fieldFromInstruction(Insn, 7, 1); 5336 if (fieldFromInstruction(Insn, 6, 1)) 5337 inc = 2; 5338 break; 5339 } 5340 5341 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5342 return MCDisassembler::Fail; 5343 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5344 return MCDisassembler::Fail; 5345 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5346 return MCDisassembler::Fail; 5347 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5348 return MCDisassembler::Fail; 5349 5350 if (Rm != 0xF) { // Writeback 5351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5352 return MCDisassembler::Fail; 5353 } 5354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5355 return MCDisassembler::Fail; 5356 Inst.addOperand(MCOperand::createImm(align)); 5357 if (Rm != 0xF) { 5358 if (Rm != 0xD) { 5359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5360 return MCDisassembler::Fail; 5361 } else 5362 Inst.addOperand(MCOperand::createReg(0)); 5363 } 5364 5365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5366 return MCDisassembler::Fail; 5367 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5368 return MCDisassembler::Fail; 5369 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5370 return MCDisassembler::Fail; 5371 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5372 return MCDisassembler::Fail; 5373 Inst.addOperand(MCOperand::createImm(index)); 5374 5375 return S; 5376 } 5377 5378 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5379 uint64_t Address, const void *Decoder) { 5380 DecodeStatus S = MCDisassembler::Success; 5381 5382 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5383 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5384 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5385 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5386 unsigned size = fieldFromInstruction(Insn, 10, 2); 5387 5388 unsigned align = 0; 5389 unsigned index = 0; 5390 unsigned inc = 1; 5391 switch (size) { 5392 default: 5393 return MCDisassembler::Fail; 5394 case 0: 5395 if (fieldFromInstruction(Insn, 4, 1)) 5396 align = 4; 5397 index = fieldFromInstruction(Insn, 5, 3); 5398 break; 5399 case 1: 5400 if (fieldFromInstruction(Insn, 4, 1)) 5401 align = 8; 5402 index = fieldFromInstruction(Insn, 6, 2); 5403 if (fieldFromInstruction(Insn, 5, 1)) 5404 inc = 2; 5405 break; 5406 case 2: 5407 switch (fieldFromInstruction(Insn, 4, 2)) { 5408 case 0: 5409 align = 0; break; 5410 case 3: 5411 return MCDisassembler::Fail; 5412 default: 5413 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5414 } 5415 5416 index = fieldFromInstruction(Insn, 7, 1); 5417 if (fieldFromInstruction(Insn, 6, 1)) 5418 inc = 2; 5419 break; 5420 } 5421 5422 if (Rm != 0xF) { // Writeback 5423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5424 return MCDisassembler::Fail; 5425 } 5426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5427 return MCDisassembler::Fail; 5428 Inst.addOperand(MCOperand::createImm(align)); 5429 if (Rm != 0xF) { 5430 if (Rm != 0xD) { 5431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5432 return MCDisassembler::Fail; 5433 } else 5434 Inst.addOperand(MCOperand::createReg(0)); 5435 } 5436 5437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5438 return MCDisassembler::Fail; 5439 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5440 return MCDisassembler::Fail; 5441 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5442 return MCDisassembler::Fail; 5443 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5444 return MCDisassembler::Fail; 5445 Inst.addOperand(MCOperand::createImm(index)); 5446 5447 return S; 5448 } 5449 5450 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5451 uint64_t Address, const void *Decoder) { 5452 DecodeStatus S = MCDisassembler::Success; 5453 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5454 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5455 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5456 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5457 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5458 5459 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5460 S = MCDisassembler::SoftFail; 5461 5462 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5463 return MCDisassembler::Fail; 5464 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5465 return MCDisassembler::Fail; 5466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5467 return MCDisassembler::Fail; 5468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5469 return MCDisassembler::Fail; 5470 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5471 return MCDisassembler::Fail; 5472 5473 return S; 5474 } 5475 5476 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5477 uint64_t Address, const void *Decoder) { 5478 DecodeStatus S = MCDisassembler::Success; 5479 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5480 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5481 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5482 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5483 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5484 5485 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5486 S = MCDisassembler::SoftFail; 5487 5488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5489 return MCDisassembler::Fail; 5490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5491 return MCDisassembler::Fail; 5492 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5493 return MCDisassembler::Fail; 5494 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5495 return MCDisassembler::Fail; 5496 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5497 return MCDisassembler::Fail; 5498 5499 return S; 5500 } 5501 5502 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5503 uint64_t Address, const void *Decoder) { 5504 DecodeStatus S = MCDisassembler::Success; 5505 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5506 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5507 5508 if (pred == 0xF) { 5509 pred = 0xE; 5510 S = MCDisassembler::SoftFail; 5511 } 5512 5513 if (mask == 0x0) 5514 return MCDisassembler::Fail; 5515 5516 // IT masks are encoded as a sequence of replacement low-order bits 5517 // for the condition code. So if the low bit of the starting 5518 // condition code is 1, then we have to flip all the bits above the 5519 // terminating bit (which is the lowest 1 bit). 5520 if (pred & 1) { 5521 unsigned LowBit = mask & -mask; 5522 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5523 mask ^= BitsAboveLowBit; 5524 } 5525 5526 Inst.addOperand(MCOperand::createImm(pred)); 5527 Inst.addOperand(MCOperand::createImm(mask)); 5528 return S; 5529 } 5530 5531 static DecodeStatus 5532 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5533 uint64_t Address, const void *Decoder) { 5534 DecodeStatus S = MCDisassembler::Success; 5535 5536 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5537 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5538 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5539 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5540 unsigned W = fieldFromInstruction(Insn, 21, 1); 5541 unsigned U = fieldFromInstruction(Insn, 23, 1); 5542 unsigned P = fieldFromInstruction(Insn, 24, 1); 5543 bool writeback = (W == 1) | (P == 0); 5544 5545 addr |= (U << 8) | (Rn << 9); 5546 5547 if (writeback && (Rn == Rt || Rn == Rt2)) 5548 Check(S, MCDisassembler::SoftFail); 5549 if (Rt == Rt2) 5550 Check(S, MCDisassembler::SoftFail); 5551 5552 // Rt 5553 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5554 return MCDisassembler::Fail; 5555 // Rt2 5556 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5557 return MCDisassembler::Fail; 5558 // Writeback operand 5559 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5560 return MCDisassembler::Fail; 5561 // addr 5562 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5563 return MCDisassembler::Fail; 5564 5565 return S; 5566 } 5567 5568 static DecodeStatus 5569 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5570 uint64_t Address, const void *Decoder) { 5571 DecodeStatus S = MCDisassembler::Success; 5572 5573 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5574 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5575 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5576 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5577 unsigned W = fieldFromInstruction(Insn, 21, 1); 5578 unsigned U = fieldFromInstruction(Insn, 23, 1); 5579 unsigned P = fieldFromInstruction(Insn, 24, 1); 5580 bool writeback = (W == 1) | (P == 0); 5581 5582 addr |= (U << 8) | (Rn << 9); 5583 5584 if (writeback && (Rn == Rt || Rn == Rt2)) 5585 Check(S, MCDisassembler::SoftFail); 5586 5587 // Writeback operand 5588 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5589 return MCDisassembler::Fail; 5590 // Rt 5591 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5592 return MCDisassembler::Fail; 5593 // Rt2 5594 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5595 return MCDisassembler::Fail; 5596 // addr 5597 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5598 return MCDisassembler::Fail; 5599 5600 return S; 5601 } 5602 5603 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5604 uint64_t Address, const void *Decoder) { 5605 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5606 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5607 if (sign1 != sign2) return MCDisassembler::Fail; 5608 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5609 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5610 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5611 5612 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5613 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5614 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5615 // If sign, then it is decreasing the address. 5616 if (sign1) { 5617 // Following ARMv7 Architecture Manual, when the offset 5618 // is zero, it is decoded as a subw, not as a adr.w 5619 if (!Val) { 5620 Inst.setOpcode(ARM::t2SUBri12); 5621 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5622 } else 5623 Val = -Val; 5624 } 5625 Inst.addOperand(MCOperand::createImm(Val)); 5626 return S; 5627 } 5628 5629 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5630 uint64_t Address, 5631 const void *Decoder) { 5632 DecodeStatus S = MCDisassembler::Success; 5633 5634 // Shift of "asr #32" is not allowed in Thumb2 mode. 5635 if (Val == 0x20) S = MCDisassembler::Fail; 5636 Inst.addOperand(MCOperand::createImm(Val)); 5637 return S; 5638 } 5639 5640 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5641 uint64_t Address, const void *Decoder) { 5642 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5643 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5644 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5645 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5646 5647 if (pred == 0xF) 5648 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5649 5650 DecodeStatus S = MCDisassembler::Success; 5651 5652 if (Rt == Rn || Rn == Rt2) 5653 S = MCDisassembler::SoftFail; 5654 5655 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5656 return MCDisassembler::Fail; 5657 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5658 return MCDisassembler::Fail; 5659 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5660 return MCDisassembler::Fail; 5661 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5662 return MCDisassembler::Fail; 5663 5664 return S; 5665 } 5666 5667 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5668 uint64_t Address, const void *Decoder) { 5669 const FeatureBitset &featureBits = 5670 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5671 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5672 5673 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5674 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5675 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5676 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5677 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5678 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5679 unsigned op = fieldFromInstruction(Insn, 5, 1); 5680 5681 DecodeStatus S = MCDisassembler::Success; 5682 5683 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5684 if (!(imm & 0x38)) { 5685 if (cmode == 0xF) { 5686 if (op == 1) return MCDisassembler::Fail; 5687 Inst.setOpcode(ARM::VMOVv2f32); 5688 } 5689 if (hasFullFP16) { 5690 if (cmode == 0xE) { 5691 if (op == 1) { 5692 Inst.setOpcode(ARM::VMOVv1i64); 5693 } else { 5694 Inst.setOpcode(ARM::VMOVv8i8); 5695 } 5696 } 5697 if (cmode == 0xD) { 5698 if (op == 1) { 5699 Inst.setOpcode(ARM::VMVNv2i32); 5700 } else { 5701 Inst.setOpcode(ARM::VMOVv2i32); 5702 } 5703 } 5704 if (cmode == 0xC) { 5705 if (op == 1) { 5706 Inst.setOpcode(ARM::VMVNv2i32); 5707 } else { 5708 Inst.setOpcode(ARM::VMOVv2i32); 5709 } 5710 } 5711 } 5712 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5713 } 5714 5715 if (!(imm & 0x20)) return MCDisassembler::Fail; 5716 5717 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5718 return MCDisassembler::Fail; 5719 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5720 return MCDisassembler::Fail; 5721 Inst.addOperand(MCOperand::createImm(64 - imm)); 5722 5723 return S; 5724 } 5725 5726 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5727 uint64_t Address, const void *Decoder) { 5728 const FeatureBitset &featureBits = 5729 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5730 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5731 5732 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5733 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5734 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5735 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5736 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5737 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5738 unsigned op = fieldFromInstruction(Insn, 5, 1); 5739 5740 DecodeStatus S = MCDisassembler::Success; 5741 5742 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5743 if (!(imm & 0x38)) { 5744 if (cmode == 0xF) { 5745 if (op == 1) return MCDisassembler::Fail; 5746 Inst.setOpcode(ARM::VMOVv4f32); 5747 } 5748 if (hasFullFP16) { 5749 if (cmode == 0xE) { 5750 if (op == 1) { 5751 Inst.setOpcode(ARM::VMOVv2i64); 5752 } else { 5753 Inst.setOpcode(ARM::VMOVv16i8); 5754 } 5755 } 5756 if (cmode == 0xD) { 5757 if (op == 1) { 5758 Inst.setOpcode(ARM::VMVNv4i32); 5759 } else { 5760 Inst.setOpcode(ARM::VMOVv4i32); 5761 } 5762 } 5763 if (cmode == 0xC) { 5764 if (op == 1) { 5765 Inst.setOpcode(ARM::VMVNv4i32); 5766 } else { 5767 Inst.setOpcode(ARM::VMOVv4i32); 5768 } 5769 } 5770 } 5771 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5772 } 5773 5774 if (!(imm & 0x20)) return MCDisassembler::Fail; 5775 5776 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5777 return MCDisassembler::Fail; 5778 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5779 return MCDisassembler::Fail; 5780 Inst.addOperand(MCOperand::createImm(64 - imm)); 5781 5782 return S; 5783 } 5784 5785 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5786 unsigned Insn, 5787 uint64_t Address, 5788 const void *Decoder) { 5789 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5790 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5791 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5792 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5793 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5794 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5795 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5796 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5797 5798 DecodeStatus S = MCDisassembler::Success; 5799 5800 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5801 5802 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5803 return MCDisassembler::Fail; 5804 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5805 return MCDisassembler::Fail; 5806 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5807 return MCDisassembler::Fail; 5808 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5809 return MCDisassembler::Fail; 5810 // The lane index does not have any bits in the encoding, because it can only 5811 // be 0. 5812 Inst.addOperand(MCOperand::createImm(0)); 5813 Inst.addOperand(MCOperand::createImm(rotate)); 5814 5815 return S; 5816 } 5817 5818 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5819 uint64_t Address, const void *Decoder) { 5820 DecodeStatus S = MCDisassembler::Success; 5821 5822 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5823 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5824 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5825 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5826 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5827 5828 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5829 S = MCDisassembler::SoftFail; 5830 5831 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5832 return MCDisassembler::Fail; 5833 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5834 return MCDisassembler::Fail; 5835 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5836 return MCDisassembler::Fail; 5837 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5838 return MCDisassembler::Fail; 5839 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5840 return MCDisassembler::Fail; 5841 5842 return S; 5843 } 5844 5845 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5846 uint64_t Address, const void *Decoder) { 5847 DecodeStatus S = MCDisassembler::Success; 5848 5849 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5850 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5851 unsigned cop = fieldFromInstruction(Val, 8, 4); 5852 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5853 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5854 5855 if ((cop & ~0x1) == 0xa) 5856 return MCDisassembler::Fail; 5857 5858 if (Rt == Rt2) 5859 S = MCDisassembler::SoftFail; 5860 5861 // We have to check if the instruction is MRRC2 5862 // or MCRR2 when constructing the operands for 5863 // Inst. Reason is because MRRC2 stores to two 5864 // registers so it's tablegen desc has has two 5865 // outputs whereas MCRR doesn't store to any 5866 // registers so all of it's operands are listed 5867 // as inputs, therefore the operand order for 5868 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5869 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5870 5871 if (Inst.getOpcode() == ARM::MRRC2) { 5872 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5873 return MCDisassembler::Fail; 5874 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5875 return MCDisassembler::Fail; 5876 } 5877 Inst.addOperand(MCOperand::createImm(cop)); 5878 Inst.addOperand(MCOperand::createImm(opc1)); 5879 if (Inst.getOpcode() == ARM::MCRR2) { 5880 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5881 return MCDisassembler::Fail; 5882 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5883 return MCDisassembler::Fail; 5884 } 5885 Inst.addOperand(MCOperand::createImm(CRm)); 5886 5887 return S; 5888 } 5889 5890 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5891 uint64_t Address, 5892 const void *Decoder) { 5893 const FeatureBitset &featureBits = 5894 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5895 DecodeStatus S = MCDisassembler::Success; 5896 5897 // Add explicit operand for the destination sysreg, for cases where 5898 // we have to model it for code generation purposes. 5899 switch (Inst.getOpcode()) { 5900 case ARM::VMSR_FPSCR_NZCVQC: 5901 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5902 break; 5903 case ARM::VMSR_P0: 5904 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5905 break; 5906 } 5907 5908 if (Inst.getOpcode() != ARM::FMSTAT) { 5909 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5910 5911 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5912 if (Rt == 13 || Rt == 15) 5913 S = MCDisassembler::SoftFail; 5914 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5915 } else 5916 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5917 } 5918 5919 // Add explicit operand for the source sysreg, similarly to above. 5920 switch (Inst.getOpcode()) { 5921 case ARM::VMRS_FPSCR_NZCVQC: 5922 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5923 break; 5924 case ARM::VMRS_P0: 5925 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5926 break; 5927 } 5928 5929 if (featureBits[ARM::ModeThumb]) { 5930 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5931 Inst.addOperand(MCOperand::createReg(0)); 5932 } else { 5933 unsigned pred = fieldFromInstruction(Val, 28, 4); 5934 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5935 return MCDisassembler::Fail; 5936 } 5937 5938 return S; 5939 } 5940 5941 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5942 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5943 uint64_t Address, 5944 const void *Decoder) { 5945 DecodeStatus S = MCDisassembler::Success; 5946 if (Val == 0 && !zeroPermitted) 5947 S = MCDisassembler::Fail; 5948 5949 uint64_t DecVal; 5950 if (isSigned) 5951 DecVal = SignExtend32<size + 1>(Val << 1); 5952 else 5953 DecVal = (Val << 1); 5954 5955 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5956 Decoder)) 5957 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5958 return S; 5959 } 5960 5961 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5962 uint64_t Address, 5963 const void *Decoder) { 5964 5965 uint64_t LocImm = Inst.getOperand(0).getImm(); 5966 Val = LocImm + (2 << Val); 5967 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5968 Decoder)) 5969 Inst.addOperand(MCOperand::createImm(Val)); 5970 return MCDisassembler::Success; 5971 } 5972 5973 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5974 uint64_t Address, 5975 const void *Decoder) { 5976 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5977 return MCDisassembler::Fail; 5978 Inst.addOperand(MCOperand::createImm(Val)); 5979 return MCDisassembler::Success; 5980 } 5981 5982 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5983 const void *Decoder) { 5984 DecodeStatus S = MCDisassembler::Success; 5985 5986 if (Inst.getOpcode() == ARM::MVE_LCTP) 5987 return S; 5988 5989 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5990 fieldFromInstruction(Insn, 1, 10) << 1; 5991 switch (Inst.getOpcode()) { 5992 case ARM::t2LEUpdate: 5993 case ARM::MVE_LETP: 5994 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5995 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5996 LLVM_FALLTHROUGH; 5997 case ARM::t2LE: 5998 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 5999 Inst, Imm, Address, Decoder))) 6000 return MCDisassembler::Fail; 6001 break; 6002 case ARM::t2WLS: 6003 case ARM::MVE_WLSTP_8: 6004 case ARM::MVE_WLSTP_16: 6005 case ARM::MVE_WLSTP_32: 6006 case ARM::MVE_WLSTP_64: 6007 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6008 if (!Check(S, 6009 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6010 Address, Decoder)) || 6011 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6012 Inst, Imm, Address, Decoder))) 6013 return MCDisassembler::Fail; 6014 break; 6015 case ARM::t2DLS: 6016 case ARM::MVE_DLSTP_8: 6017 case ARM::MVE_DLSTP_16: 6018 case ARM::MVE_DLSTP_32: 6019 case ARM::MVE_DLSTP_64: 6020 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6021 if (Rn == 0xF) { 6022 // Enforce all the rest of the instruction bits in LCTP, which 6023 // won't have been reliably checked based on LCTP's own tablegen 6024 // record, because we came to this decode by a roundabout route. 6025 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6026 if ((Insn & ~SBZMask) != CanonicalLCTP) 6027 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6028 if (Insn != CanonicalLCTP) 6029 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6030 6031 Inst.setOpcode(ARM::MVE_LCTP); 6032 } else { 6033 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6034 if (!Check(S, DecoderGPRRegisterClass(Inst, 6035 fieldFromInstruction(Insn, 16, 4), 6036 Address, Decoder))) 6037 return MCDisassembler::Fail; 6038 } 6039 break; 6040 } 6041 return S; 6042 } 6043 6044 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6045 uint64_t Address, 6046 const void *Decoder) { 6047 DecodeStatus S = MCDisassembler::Success; 6048 6049 if (Val == 0) 6050 Val = 32; 6051 6052 Inst.addOperand(MCOperand::createImm(Val)); 6053 6054 return S; 6055 } 6056 6057 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6058 uint64_t Address, const void *Decoder) { 6059 if ((RegNo) + 1 > 11) 6060 return MCDisassembler::Fail; 6061 6062 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6063 Inst.addOperand(MCOperand::createReg(Register)); 6064 return MCDisassembler::Success; 6065 } 6066 6067 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6068 uint64_t Address, const void *Decoder) { 6069 if ((RegNo) > 14) 6070 return MCDisassembler::Fail; 6071 6072 unsigned Register = GPRDecoderTable[(RegNo)]; 6073 Inst.addOperand(MCOperand::createReg(Register)); 6074 return MCDisassembler::Success; 6075 } 6076 6077 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6078 const void *Decoder) { 6079 DecodeStatus S = MCDisassembler::Success; 6080 6081 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6082 Inst.addOperand(MCOperand::createReg(0)); 6083 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6084 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6085 (fieldFromInstruction(Insn, 12, 4) << 8) | 6086 (fieldFromInstruction(Insn, 22, 1) << 12); 6087 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6088 return MCDisassembler::Fail; 6089 } 6090 } else { 6091 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6092 (fieldFromInstruction(Insn, 22, 1) << 8) | 6093 (fieldFromInstruction(Insn, 12, 4) << 9); 6094 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6095 return MCDisassembler::Fail; 6096 } 6097 } 6098 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6099 6100 return S; 6101 } 6102 6103 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6104 uint64_t Address, 6105 const void *Decoder) { 6106 if (RegNo > 7) 6107 return MCDisassembler::Fail; 6108 6109 unsigned Register = QPRDecoderTable[RegNo]; 6110 Inst.addOperand(MCOperand::createReg(Register)); 6111 return MCDisassembler::Success; 6112 } 6113 6114 static const uint16_t QQPRDecoderTable[] = { 6115 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6116 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6117 }; 6118 6119 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6120 uint64_t Address, 6121 const void *Decoder) { 6122 if (RegNo > 6) 6123 return MCDisassembler::Fail; 6124 6125 unsigned Register = QQPRDecoderTable[RegNo]; 6126 Inst.addOperand(MCOperand::createReg(Register)); 6127 return MCDisassembler::Success; 6128 } 6129 6130 static const uint16_t QQQQPRDecoderTable[] = { 6131 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6132 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6133 }; 6134 6135 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6136 uint64_t Address, 6137 const void *Decoder) { 6138 if (RegNo > 4) 6139 return MCDisassembler::Fail; 6140 6141 unsigned Register = QQQQPRDecoderTable[RegNo]; 6142 Inst.addOperand(MCOperand::createReg(Register)); 6143 return MCDisassembler::Success; 6144 } 6145 6146 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6147 uint64_t Address, 6148 const void *Decoder) { 6149 DecodeStatus S = MCDisassembler::Success; 6150 6151 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6152 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6153 // 't' as 0 and finish with a 1. 6154 unsigned Imm = 0; 6155 // We always start with a 't'. 6156 unsigned CurBit = 0; 6157 for (int i = 3; i >= 0; --i) { 6158 // If the bit we are looking at is not the same as last one, invert the 6159 // CurBit, if it is the same leave it as is. 6160 CurBit ^= (Val >> i) & 1U; 6161 6162 // Encode the CurBit at the right place in the immediate. 6163 Imm |= (CurBit << i); 6164 6165 // If we are done, finish the encoding with a 1. 6166 if ((Val & ~(~0U << i)) == 0) { 6167 Imm |= 1U << i; 6168 break; 6169 } 6170 } 6171 6172 Inst.addOperand(MCOperand::createImm(Imm)); 6173 6174 return S; 6175 } 6176 6177 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6178 uint64_t Address, const void *Decoder) { 6179 // The vpred_r operand type includes an MQPR register field derived 6180 // from the encoding. But we don't actually want to add an operand 6181 // to the MCInst at this stage, because AddThumbPredicate will do it 6182 // later, and will infer the register number from the TIED_TO 6183 // constraint. So this is a deliberately empty decoder method that 6184 // will inhibit the auto-generated disassembly code from adding an 6185 // operand at all. 6186 return MCDisassembler::Success; 6187 } 6188 6189 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6190 unsigned Val, 6191 uint64_t Address, 6192 const void *Decoder) { 6193 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6194 return MCDisassembler::Success; 6195 } 6196 6197 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6198 unsigned Val, 6199 uint64_t Address, 6200 const void *Decoder) { 6201 unsigned Code; 6202 switch (Val & 0x3) { 6203 case 0: 6204 Code = ARMCC::GE; 6205 break; 6206 case 1: 6207 Code = ARMCC::LT; 6208 break; 6209 case 2: 6210 Code = ARMCC::GT; 6211 break; 6212 case 3: 6213 Code = ARMCC::LE; 6214 break; 6215 } 6216 Inst.addOperand(MCOperand::createImm(Code)); 6217 return MCDisassembler::Success; 6218 } 6219 6220 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6221 unsigned Val, 6222 uint64_t Address, 6223 const void *Decoder) { 6224 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6225 return MCDisassembler::Success; 6226 } 6227 6228 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6229 uint64_t Address, 6230 const void *Decoder) { 6231 unsigned Code; 6232 switch (Val) { 6233 default: 6234 return MCDisassembler::Fail; 6235 case 0: 6236 Code = ARMCC::EQ; 6237 break; 6238 case 1: 6239 Code = ARMCC::NE; 6240 break; 6241 case 4: 6242 Code = ARMCC::GE; 6243 break; 6244 case 5: 6245 Code = ARMCC::LT; 6246 break; 6247 case 6: 6248 Code = ARMCC::GT; 6249 break; 6250 case 7: 6251 Code = ARMCC::LE; 6252 break; 6253 } 6254 6255 Inst.addOperand(MCOperand::createImm(Code)); 6256 return MCDisassembler::Success; 6257 } 6258 6259 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6260 uint64_t Address, const void *Decoder) { 6261 DecodeStatus S = MCDisassembler::Success; 6262 6263 unsigned DecodedVal = 64 - Val; 6264 6265 switch (Inst.getOpcode()) { 6266 case ARM::MVE_VCVTf16s16_fix: 6267 case ARM::MVE_VCVTs16f16_fix: 6268 case ARM::MVE_VCVTf16u16_fix: 6269 case ARM::MVE_VCVTu16f16_fix: 6270 if (DecodedVal > 16) 6271 return MCDisassembler::Fail; 6272 break; 6273 case ARM::MVE_VCVTf32s32_fix: 6274 case ARM::MVE_VCVTs32f32_fix: 6275 case ARM::MVE_VCVTf32u32_fix: 6276 case ARM::MVE_VCVTu32f32_fix: 6277 if (DecodedVal > 32) 6278 return MCDisassembler::Fail; 6279 break; 6280 } 6281 6282 Inst.addOperand(MCOperand::createImm(64 - Val)); 6283 6284 return S; 6285 } 6286 6287 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6288 switch (Opcode) { 6289 case ARM::VSTR_P0_off: 6290 case ARM::VSTR_P0_pre: 6291 case ARM::VSTR_P0_post: 6292 case ARM::VLDR_P0_off: 6293 case ARM::VLDR_P0_pre: 6294 case ARM::VLDR_P0_post: 6295 return ARM::P0; 6296 default: 6297 return 0; 6298 } 6299 } 6300 6301 template<bool Writeback> 6302 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6303 uint64_t Address, 6304 const void *Decoder) { 6305 switch (Inst.getOpcode()) { 6306 case ARM::VSTR_FPSCR_pre: 6307 case ARM::VSTR_FPSCR_NZCVQC_pre: 6308 case ARM::VLDR_FPSCR_pre: 6309 case ARM::VLDR_FPSCR_NZCVQC_pre: 6310 case ARM::VSTR_FPSCR_off: 6311 case ARM::VSTR_FPSCR_NZCVQC_off: 6312 case ARM::VLDR_FPSCR_off: 6313 case ARM::VLDR_FPSCR_NZCVQC_off: 6314 case ARM::VSTR_FPSCR_post: 6315 case ARM::VSTR_FPSCR_NZCVQC_post: 6316 case ARM::VLDR_FPSCR_post: 6317 case ARM::VLDR_FPSCR_NZCVQC_post: 6318 const FeatureBitset &featureBits = 6319 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6320 6321 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6322 return MCDisassembler::Fail; 6323 } 6324 6325 DecodeStatus S = MCDisassembler::Success; 6326 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6327 Inst.addOperand(MCOperand::createReg(Sysreg)); 6328 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6329 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6330 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6331 6332 if (Writeback) { 6333 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6334 return MCDisassembler::Fail; 6335 } 6336 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6337 return MCDisassembler::Fail; 6338 6339 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6340 Inst.addOperand(MCOperand::createReg(0)); 6341 6342 return S; 6343 } 6344 6345 static inline DecodeStatus DecodeMVE_MEM_pre( 6346 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6347 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6348 DecodeStatus S = MCDisassembler::Success; 6349 6350 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6351 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6352 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6353 6354 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6355 return MCDisassembler::Fail; 6356 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6357 return MCDisassembler::Fail; 6358 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6359 return MCDisassembler::Fail; 6360 6361 return S; 6362 } 6363 6364 template <int shift> 6365 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6366 uint64_t Address, const void *Decoder) { 6367 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6368 fieldFromInstruction(Val, 16, 3), 6369 DecodetGPRRegisterClass, 6370 DecodeTAddrModeImm7<shift>); 6371 } 6372 6373 template <int shift> 6374 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6375 uint64_t Address, const void *Decoder) { 6376 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6377 fieldFromInstruction(Val, 16, 4), 6378 DecoderGPRRegisterClass, 6379 DecodeT2AddrModeImm7<shift,1>); 6380 } 6381 6382 template <int shift> 6383 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6384 uint64_t Address, const void *Decoder) { 6385 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6386 fieldFromInstruction(Val, 17, 3), 6387 DecodeMQPRRegisterClass, 6388 DecodeMveAddrModeQ<shift>); 6389 } 6390 6391 template<unsigned MinLog, unsigned MaxLog> 6392 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6393 uint64_t Address, 6394 const void *Decoder) { 6395 DecodeStatus S = MCDisassembler::Success; 6396 6397 if (Val < MinLog || Val > MaxLog) 6398 return MCDisassembler::Fail; 6399 6400 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6401 return S; 6402 } 6403 6404 template <int shift> 6405 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6406 uint64_t Address, 6407 const void *Decoder) { 6408 Val <<= shift; 6409 6410 Inst.addOperand(MCOperand::createImm(Val)); 6411 return MCDisassembler::Success; 6412 } 6413 6414 template<unsigned start> 6415 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6416 uint64_t Address, 6417 const void *Decoder) { 6418 DecodeStatus S = MCDisassembler::Success; 6419 6420 Inst.addOperand(MCOperand::createImm(start + Val)); 6421 6422 return S; 6423 } 6424 6425 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6426 uint64_t Address, const void *Decoder) { 6427 DecodeStatus S = MCDisassembler::Success; 6428 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6429 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6430 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6431 fieldFromInstruction(Insn, 13, 3)); 6432 unsigned index = fieldFromInstruction(Insn, 4, 1); 6433 6434 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6435 return MCDisassembler::Fail; 6436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6437 return MCDisassembler::Fail; 6438 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6439 return MCDisassembler::Fail; 6440 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6441 return MCDisassembler::Fail; 6442 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6443 return MCDisassembler::Fail; 6444 6445 return S; 6446 } 6447 6448 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6449 uint64_t Address, const void *Decoder) { 6450 DecodeStatus S = MCDisassembler::Success; 6451 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6452 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6453 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6454 fieldFromInstruction(Insn, 13, 3)); 6455 unsigned index = fieldFromInstruction(Insn, 4, 1); 6456 6457 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6458 return MCDisassembler::Fail; 6459 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6460 return MCDisassembler::Fail; 6461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6462 return MCDisassembler::Fail; 6463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6464 return MCDisassembler::Fail; 6465 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6466 return MCDisassembler::Fail; 6467 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6468 return MCDisassembler::Fail; 6469 6470 return S; 6471 } 6472 6473 static DecodeStatus DecodeMVEOverlappingLongShift( 6474 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6475 DecodeStatus S = MCDisassembler::Success; 6476 6477 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6478 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6479 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6480 6481 if (RdaHi == 14) { 6482 // This value of RdaHi (really indicating pc, because RdaHi has to 6483 // be an odd-numbered register, so the low bit will be set by the 6484 // decode function below) indicates that we must decode as SQRSHR 6485 // or UQRSHL, which both have a single Rda register field with all 6486 // four bits. 6487 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6488 6489 switch (Inst.getOpcode()) { 6490 case ARM::MVE_ASRLr: 6491 case ARM::MVE_SQRSHRL: 6492 Inst.setOpcode(ARM::MVE_SQRSHR); 6493 break; 6494 case ARM::MVE_LSLLr: 6495 case ARM::MVE_UQRSHLL: 6496 Inst.setOpcode(ARM::MVE_UQRSHL); 6497 break; 6498 default: 6499 llvm_unreachable("Unexpected starting opcode!"); 6500 } 6501 6502 // Rda as output parameter 6503 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6504 return MCDisassembler::Fail; 6505 6506 // Rda again as input parameter 6507 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6508 return MCDisassembler::Fail; 6509 6510 // Rm, the amount to shift by 6511 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6512 return MCDisassembler::Fail; 6513 6514 if (fieldFromInstruction (Insn, 6, 3) != 4) 6515 return MCDisassembler::SoftFail; 6516 6517 if (Rda == Rm) 6518 return MCDisassembler::SoftFail; 6519 6520 return S; 6521 } 6522 6523 // Otherwise, we decode as whichever opcode our caller has already 6524 // put into Inst. Those all look the same: 6525 6526 // RdaLo,RdaHi as output parameters 6527 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6528 return MCDisassembler::Fail; 6529 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6530 return MCDisassembler::Fail; 6531 6532 // RdaLo,RdaHi again as input parameters 6533 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6534 return MCDisassembler::Fail; 6535 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6536 return MCDisassembler::Fail; 6537 6538 // Rm, the amount to shift by 6539 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6540 return MCDisassembler::Fail; 6541 6542 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6543 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6544 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6545 // Saturate, the bit position for saturation 6546 Inst.addOperand(MCOperand::createImm(Saturate)); 6547 } 6548 6549 return S; 6550 } 6551 6552 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6553 const void *Decoder) { 6554 DecodeStatus S = MCDisassembler::Success; 6555 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6556 fieldFromInstruction(Insn, 13, 3)); 6557 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6558 fieldFromInstruction(Insn, 1, 3)); 6559 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6560 6561 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6562 return MCDisassembler::Fail; 6563 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6564 return MCDisassembler::Fail; 6565 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6566 return MCDisassembler::Fail; 6567 6568 return S; 6569 } 6570 6571 template<bool scalar, OperandDecoder predicate_decoder> 6572 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6573 const void *Decoder) { 6574 DecodeStatus S = MCDisassembler::Success; 6575 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6576 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6577 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6578 return MCDisassembler::Fail; 6579 6580 unsigned fc; 6581 6582 if (scalar) { 6583 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6584 fieldFromInstruction(Insn, 7, 1) | 6585 fieldFromInstruction(Insn, 5, 1) << 1; 6586 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6587 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6588 return MCDisassembler::Fail; 6589 } else { 6590 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6591 fieldFromInstruction(Insn, 7, 1) | 6592 fieldFromInstruction(Insn, 0, 1) << 1; 6593 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6594 fieldFromInstruction(Insn, 1, 3); 6595 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6596 return MCDisassembler::Fail; 6597 } 6598 6599 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6600 return MCDisassembler::Fail; 6601 6602 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6603 Inst.addOperand(MCOperand::createReg(0)); 6604 Inst.addOperand(MCOperand::createImm(0)); 6605 6606 return S; 6607 } 6608 6609 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6610 const void *Decoder) { 6611 DecodeStatus S = MCDisassembler::Success; 6612 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6613 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6614 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6615 return MCDisassembler::Fail; 6616 return S; 6617 } 6618 6619 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6620 const void *Decoder) { 6621 DecodeStatus S = MCDisassembler::Success; 6622 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6623 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6624 return S; 6625 } 6626 6627 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6628 uint64_t Address, const void *Decoder) { 6629 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6630 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6631 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6632 fieldFromInstruction(Insn, 12, 3) << 8 | 6633 fieldFromInstruction(Insn, 0, 8); 6634 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6635 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6636 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6637 unsigned S = fieldFromInstruction(Insn, 20, 1); 6638 if (sign1 != sign2) 6639 return MCDisassembler::Fail; 6640 6641 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6642 DecodeStatus DS = MCDisassembler::Success; 6643 if ((!Check(DS, 6644 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6645 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6646 return MCDisassembler::Fail; 6647 if (TypeT3) { 6648 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6649 S = 0; 6650 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6651 } else { 6652 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6653 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6654 return MCDisassembler::Fail; 6655 } 6656 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6657 return MCDisassembler::Fail; 6658 6659 Inst.addOperand(MCOperand::createReg(0)); // pred 6660 6661 return DS; 6662 } 6663