1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, 102 uint64_t &size, 103 const MemoryObject ®ion, 104 uint64_t address, 105 raw_ostream &vStream, 106 raw_ostream &cStream) const; 107 }; 108 109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 110 class ThumbDisassembler : public MCDisassembler { 111 public: 112 /// Constructor - Initializes the disassembler. 113 /// 114 ThumbDisassembler(const MCSubtargetInfo &STI) : 115 MCDisassembler(STI) { 116 } 117 118 ~ThumbDisassembler() { 119 } 120 121 /// getInstruction - See MCDisassembler. 122 DecodeStatus getInstruction(MCInst &instr, 123 uint64_t &size, 124 const MemoryObject ®ion, 125 uint64_t address, 126 raw_ostream &vStream, 127 raw_ostream &cStream) const; 128 129 private: 130 mutable ITStatus ITBlock; 131 DecodeStatus AddThumbPredicate(MCInst&) const; 132 void UpdateThumbVFPPredicate(MCInst&) const; 133 }; 134 } 135 136 static bool Check(DecodeStatus &Out, DecodeStatus In) { 137 switch (In) { 138 case MCDisassembler::Success: 139 // Out stays the same. 140 return true; 141 case MCDisassembler::SoftFail: 142 Out = In; 143 return true; 144 case MCDisassembler::Fail: 145 Out = In; 146 return false; 147 } 148 llvm_unreachable("Invalid DecodeStatus!"); 149 } 150 151 152 // Forward declare these because the autogenerated code will reference them. 153 // Definitions are further down. 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 160 unsigned RegNo, uint64_t Address, 161 const void *Decoder); 162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 206 unsigned Insn, 207 uint64_t Address, 208 const void *Decoder); 209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 219 unsigned Insn, 220 uint64_t Adddress, 221 const void *Decoder); 222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 327 328 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void* Decoder); 350 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void* Decoder); 356 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 401 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 #include "ARMGenDisassemblerTables.inc" 406 407 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 408 return new ARMDisassembler(STI); 409 } 410 411 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 412 return new ThumbDisassembler(STI); 413 } 414 415 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 416 const MemoryObject &Region, 417 uint64_t Address, 418 raw_ostream &os, 419 raw_ostream &cs) const { 420 CommentStream = &cs; 421 422 uint8_t bytes[4]; 423 424 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 425 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 426 427 // We want to read exactly 4 bytes of data. 428 if (Region.readBytes(Address, 4, bytes) == -1) { 429 Size = 0; 430 return MCDisassembler::Fail; 431 } 432 433 // Encoded as a small-endian 32-bit word in the stream. 434 uint32_t insn = (bytes[3] << 24) | 435 (bytes[2] << 16) | 436 (bytes[1] << 8) | 437 (bytes[0] << 0); 438 439 // Calling the auto-generated decoder function. 440 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 441 Address, this, STI); 442 if (result != MCDisassembler::Fail) { 443 Size = 4; 444 return result; 445 } 446 447 // VFP and NEON instructions, similarly, are shared between ARM 448 // and Thumb modes. 449 MI.clear(); 450 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 451 if (result != MCDisassembler::Fail) { 452 Size = 4; 453 return result; 454 } 455 456 MI.clear(); 457 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI); 458 if (result != MCDisassembler::Fail) { 459 Size = 4; 460 return result; 461 } 462 463 MI.clear(); 464 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 465 this, STI); 466 if (result != MCDisassembler::Fail) { 467 Size = 4; 468 // Add a fake predicate operand, because we share these instruction 469 // definitions with Thumb2 where these instructions are predicable. 470 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 471 return MCDisassembler::Fail; 472 return result; 473 } 474 475 MI.clear(); 476 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 477 this, STI); 478 if (result != MCDisassembler::Fail) { 479 Size = 4; 480 // Add a fake predicate operand, because we share these instruction 481 // definitions with Thumb2 where these instructions are predicable. 482 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 483 return MCDisassembler::Fail; 484 return result; 485 } 486 487 MI.clear(); 488 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 489 this, STI); 490 if (result != MCDisassembler::Fail) { 491 Size = 4; 492 // Add a fake predicate operand, because we share these instruction 493 // definitions with Thumb2 where these instructions are predicable. 494 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 495 return MCDisassembler::Fail; 496 return result; 497 } 498 499 MI.clear(); 500 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address, 501 this, STI); 502 if (result != MCDisassembler::Fail) { 503 Size = 4; 504 return result; 505 } 506 507 MI.clear(); 508 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address, 509 this, STI); 510 if (result != MCDisassembler::Fail) { 511 Size = 4; 512 return result; 513 } 514 515 MI.clear(); 516 Size = 0; 517 return MCDisassembler::Fail; 518 } 519 520 namespace llvm { 521 extern const MCInstrDesc ARMInsts[]; 522 } 523 524 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 525 /// immediate Value in the MCInst. The immediate Value has had any PC 526 /// adjustment made by the caller. If the instruction is a branch instruction 527 /// then isBranch is true, else false. If the getOpInfo() function was set as 528 /// part of the setupForSymbolicDisassembly() call then that function is called 529 /// to get any symbolic information at the Address for this instruction. If 530 /// that returns non-zero then the symbolic information it returns is used to 531 /// create an MCExpr and that is added as an operand to the MCInst. If 532 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 533 /// Value is done and if a symbol is found an MCExpr is created with that, else 534 /// an MCExpr with Value is created. This function returns true if it adds an 535 /// operand to the MCInst and false otherwise. 536 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 537 bool isBranch, uint64_t InstSize, 538 MCInst &MI, const void *Decoder) { 539 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 540 // FIXME: Does it make sense for value to be negative? 541 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 542 /* Offset */ 0, InstSize); 543 } 544 545 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 546 /// referenced by a load instruction with the base register that is the Pc. 547 /// These can often be values in a literal pool near the Address of the 548 /// instruction. The Address of the instruction and its immediate Value are 549 /// used as a possible literal pool entry. The SymbolLookUp call back will 550 /// return the name of a symbol referenced by the literal pool's entry if 551 /// the referenced address is that of a symbol. Or it will return a pointer to 552 /// a literal 'C' string if the referenced address of the literal pool's entry 553 /// is an address into a section with 'C' string literals. 554 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 555 const void *Decoder) { 556 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 557 Dis->tryAddingPcLoadReferenceComment(Value, Address); 558 } 559 560 // Thumb1 instructions don't have explicit S bits. Rather, they 561 // implicitly set CPSR. Since it's not represented in the encoding, the 562 // auto-generated decoder won't inject the CPSR operand. We need to fix 563 // that as a post-pass. 564 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 565 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 566 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 567 MCInst::iterator I = MI.begin(); 568 for (unsigned i = 0; i < NumOps; ++i, ++I) { 569 if (I == MI.end()) break; 570 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 571 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 572 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 573 return; 574 } 575 } 576 577 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 578 } 579 580 // Most Thumb instructions don't have explicit predicates in the 581 // encoding, but rather get their predicates from IT context. We need 582 // to fix up the predicate operands using this context information as a 583 // post-pass. 584 MCDisassembler::DecodeStatus 585 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 586 MCDisassembler::DecodeStatus S = Success; 587 588 // A few instructions actually have predicates encoded in them. Don't 589 // try to overwrite it if we're seeing one of those. 590 switch (MI.getOpcode()) { 591 case ARM::tBcc: 592 case ARM::t2Bcc: 593 case ARM::tCBZ: 594 case ARM::tCBNZ: 595 case ARM::tCPS: 596 case ARM::t2CPS3p: 597 case ARM::t2CPS2p: 598 case ARM::t2CPS1p: 599 case ARM::tMOVSr: 600 case ARM::tSETEND: 601 // Some instructions (mostly conditional branches) are not 602 // allowed in IT blocks. 603 if (ITBlock.instrInITBlock()) 604 S = SoftFail; 605 else 606 return Success; 607 break; 608 case ARM::tB: 609 case ARM::t2B: 610 case ARM::t2TBB: 611 case ARM::t2TBH: 612 // Some instructions (mostly unconditional branches) can 613 // only appears at the end of, or outside of, an IT. 614 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 615 S = SoftFail; 616 break; 617 default: 618 break; 619 } 620 621 // If we're in an IT block, base the predicate on that. Otherwise, 622 // assume a predicate of AL. 623 unsigned CC; 624 CC = ITBlock.getITCC(); 625 if (CC == 0xF) 626 CC = ARMCC::AL; 627 if (ITBlock.instrInITBlock()) 628 ITBlock.advanceITState(); 629 630 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 631 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 632 MCInst::iterator I = MI.begin(); 633 for (unsigned i = 0; i < NumOps; ++i, ++I) { 634 if (I == MI.end()) break; 635 if (OpInfo[i].isPredicate()) { 636 I = MI.insert(I, MCOperand::CreateImm(CC)); 637 ++I; 638 if (CC == ARMCC::AL) 639 MI.insert(I, MCOperand::CreateReg(0)); 640 else 641 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 642 return S; 643 } 644 } 645 646 I = MI.insert(I, MCOperand::CreateImm(CC)); 647 ++I; 648 if (CC == ARMCC::AL) 649 MI.insert(I, MCOperand::CreateReg(0)); 650 else 651 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 652 653 return S; 654 } 655 656 // Thumb VFP instructions are a special case. Because we share their 657 // encodings between ARM and Thumb modes, and they are predicable in ARM 658 // mode, the auto-generated decoder will give them an (incorrect) 659 // predicate operand. We need to rewrite these operands based on the IT 660 // context as a post-pass. 661 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 662 unsigned CC; 663 CC = ITBlock.getITCC(); 664 if (ITBlock.instrInITBlock()) 665 ITBlock.advanceITState(); 666 667 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 668 MCInst::iterator I = MI.begin(); 669 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 670 for (unsigned i = 0; i < NumOps; ++i, ++I) { 671 if (OpInfo[i].isPredicate() ) { 672 I->setImm(CC); 673 ++I; 674 if (CC == ARMCC::AL) 675 I->setReg(0); 676 else 677 I->setReg(ARM::CPSR); 678 return; 679 } 680 } 681 } 682 683 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 684 const MemoryObject &Region, 685 uint64_t Address, 686 raw_ostream &os, 687 raw_ostream &cs) const { 688 CommentStream = &cs; 689 690 uint8_t bytes[4]; 691 692 assert((STI.getFeatureBits() & ARM::ModeThumb) && 693 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 694 695 // We want to read exactly 2 bytes of data. 696 if (Region.readBytes(Address, 2, bytes) == -1) { 697 Size = 0; 698 return MCDisassembler::Fail; 699 } 700 701 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 702 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 703 Address, this, STI); 704 if (result != MCDisassembler::Fail) { 705 Size = 2; 706 Check(result, AddThumbPredicate(MI)); 707 return result; 708 } 709 710 MI.clear(); 711 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 712 Address, this, STI); 713 if (result) { 714 Size = 2; 715 bool InITBlock = ITBlock.instrInITBlock(); 716 Check(result, AddThumbPredicate(MI)); 717 AddThumb1SBit(MI, InITBlock); 718 return result; 719 } 720 721 MI.clear(); 722 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 723 Address, this, STI); 724 if (result != MCDisassembler::Fail) { 725 Size = 2; 726 727 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 728 // the Thumb predicate. 729 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 730 result = MCDisassembler::SoftFail; 731 732 Check(result, AddThumbPredicate(MI)); 733 734 // If we find an IT instruction, we need to parse its condition 735 // code and mask operands so that we can apply them correctly 736 // to the subsequent instructions. 737 if (MI.getOpcode() == ARM::t2IT) { 738 739 unsigned Firstcond = MI.getOperand(0).getImm(); 740 unsigned Mask = MI.getOperand(1).getImm(); 741 ITBlock.setITState(Firstcond, Mask); 742 } 743 744 return result; 745 } 746 747 // We want to read exactly 4 bytes of data. 748 if (Region.readBytes(Address, 4, bytes) == -1) { 749 Size = 0; 750 return MCDisassembler::Fail; 751 } 752 753 uint32_t insn32 = (bytes[3] << 8) | 754 (bytes[2] << 0) | 755 (bytes[1] << 24) | 756 (bytes[0] << 16); 757 MI.clear(); 758 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 759 this, STI); 760 if (result != MCDisassembler::Fail) { 761 Size = 4; 762 bool InITBlock = ITBlock.instrInITBlock(); 763 Check(result, AddThumbPredicate(MI)); 764 AddThumb1SBit(MI, InITBlock); 765 return result; 766 } 767 768 MI.clear(); 769 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 770 this, STI); 771 if (result != MCDisassembler::Fail) { 772 Size = 4; 773 Check(result, AddThumbPredicate(MI)); 774 return result; 775 } 776 777 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 778 MI.clear(); 779 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 780 if (result != MCDisassembler::Fail) { 781 Size = 4; 782 UpdateThumbVFPPredicate(MI); 783 return result; 784 } 785 } 786 787 MI.clear(); 788 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI); 789 if (result != MCDisassembler::Fail) { 790 Size = 4; 791 return result; 792 } 793 794 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 795 MI.clear(); 796 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 797 this, STI); 798 if (result != MCDisassembler::Fail) { 799 Size = 4; 800 Check(result, AddThumbPredicate(MI)); 801 return result; 802 } 803 } 804 805 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 806 MI.clear(); 807 uint32_t NEONLdStInsn = insn32; 808 NEONLdStInsn &= 0xF0FFFFFF; 809 NEONLdStInsn |= 0x04000000; 810 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 811 Address, this, STI); 812 if (result != MCDisassembler::Fail) { 813 Size = 4; 814 Check(result, AddThumbPredicate(MI)); 815 return result; 816 } 817 } 818 819 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 820 MI.clear(); 821 uint32_t NEONDataInsn = insn32; 822 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 823 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 824 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 825 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 826 Address, this, STI); 827 if (result != MCDisassembler::Fail) { 828 Size = 4; 829 Check(result, AddThumbPredicate(MI)); 830 return result; 831 } 832 } 833 834 MI.clear(); 835 uint32_t NEONCryptoInsn = insn32; 836 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 837 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 838 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 839 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 840 Address, this, STI); 841 if (result != MCDisassembler::Fail) { 842 Size = 4; 843 return result; 844 } 845 846 MI.clear(); 847 uint32_t NEONv8Insn = insn32; 848 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 849 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 850 this, STI); 851 if (result != MCDisassembler::Fail) { 852 Size = 4; 853 return result; 854 } 855 856 MI.clear(); 857 Size = 0; 858 return MCDisassembler::Fail; 859 } 860 861 862 extern "C" void LLVMInitializeARMDisassembler() { 863 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 864 createARMDisassembler); 865 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 866 createThumbDisassembler); 867 } 868 869 static const uint16_t GPRDecoderTable[] = { 870 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 871 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 872 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 873 ARM::R12, ARM::SP, ARM::LR, ARM::PC 874 }; 875 876 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 877 uint64_t Address, const void *Decoder) { 878 if (RegNo > 15) 879 return MCDisassembler::Fail; 880 881 unsigned Register = GPRDecoderTable[RegNo]; 882 Inst.addOperand(MCOperand::CreateReg(Register)); 883 return MCDisassembler::Success; 884 } 885 886 static DecodeStatus 887 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 888 uint64_t Address, const void *Decoder) { 889 DecodeStatus S = MCDisassembler::Success; 890 891 if (RegNo == 15) 892 S = MCDisassembler::SoftFail; 893 894 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 895 896 return S; 897 } 898 899 static DecodeStatus 900 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 901 uint64_t Address, const void *Decoder) { 902 DecodeStatus S = MCDisassembler::Success; 903 904 if (RegNo == 15) 905 { 906 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 907 return MCDisassembler::Success; 908 } 909 910 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 911 return S; 912 } 913 914 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 915 uint64_t Address, const void *Decoder) { 916 if (RegNo > 7) 917 return MCDisassembler::Fail; 918 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 919 } 920 921 static const uint16_t GPRPairDecoderTable[] = { 922 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 923 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 924 }; 925 926 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 927 uint64_t Address, const void *Decoder) { 928 DecodeStatus S = MCDisassembler::Success; 929 930 if (RegNo > 13) 931 return MCDisassembler::Fail; 932 933 if ((RegNo & 1) || RegNo == 0xe) 934 S = MCDisassembler::SoftFail; 935 936 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 937 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 938 return S; 939 } 940 941 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 942 uint64_t Address, const void *Decoder) { 943 unsigned Register = 0; 944 switch (RegNo) { 945 case 0: 946 Register = ARM::R0; 947 break; 948 case 1: 949 Register = ARM::R1; 950 break; 951 case 2: 952 Register = ARM::R2; 953 break; 954 case 3: 955 Register = ARM::R3; 956 break; 957 case 9: 958 Register = ARM::R9; 959 break; 960 case 12: 961 Register = ARM::R12; 962 break; 963 default: 964 return MCDisassembler::Fail; 965 } 966 967 Inst.addOperand(MCOperand::CreateReg(Register)); 968 return MCDisassembler::Success; 969 } 970 971 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 972 uint64_t Address, const void *Decoder) { 973 DecodeStatus S = MCDisassembler::Success; 974 if (RegNo == 13 || RegNo == 15) 975 S = MCDisassembler::SoftFail; 976 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 977 return S; 978 } 979 980 static const uint16_t SPRDecoderTable[] = { 981 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 982 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 983 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 984 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 985 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 986 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 987 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 988 ARM::S28, ARM::S29, ARM::S30, ARM::S31 989 }; 990 991 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 992 uint64_t Address, const void *Decoder) { 993 if (RegNo > 31) 994 return MCDisassembler::Fail; 995 996 unsigned Register = SPRDecoderTable[RegNo]; 997 Inst.addOperand(MCOperand::CreateReg(Register)); 998 return MCDisassembler::Success; 999 } 1000 1001 static const uint16_t DPRDecoderTable[] = { 1002 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1004 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1006 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1007 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1008 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1009 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1010 }; 1011 1012 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1013 uint64_t Address, const void *Decoder) { 1014 if (RegNo > 31) 1015 return MCDisassembler::Fail; 1016 1017 unsigned Register = DPRDecoderTable[RegNo]; 1018 Inst.addOperand(MCOperand::CreateReg(Register)); 1019 return MCDisassembler::Success; 1020 } 1021 1022 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1023 uint64_t Address, const void *Decoder) { 1024 if (RegNo > 7) 1025 return MCDisassembler::Fail; 1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1027 } 1028 1029 static DecodeStatus 1030 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1031 uint64_t Address, const void *Decoder) { 1032 if (RegNo > 15) 1033 return MCDisassembler::Fail; 1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1035 } 1036 1037 static const uint16_t QPRDecoderTable[] = { 1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1042 }; 1043 1044 1045 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1046 uint64_t Address, const void *Decoder) { 1047 if (RegNo > 31 || (RegNo & 1) != 0) 1048 return MCDisassembler::Fail; 1049 RegNo >>= 1; 1050 1051 unsigned Register = QPRDecoderTable[RegNo]; 1052 Inst.addOperand(MCOperand::CreateReg(Register)); 1053 return MCDisassembler::Success; 1054 } 1055 1056 static const uint16_t DPairDecoderTable[] = { 1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1062 ARM::Q15 1063 }; 1064 1065 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1066 uint64_t Address, const void *Decoder) { 1067 if (RegNo > 30) 1068 return MCDisassembler::Fail; 1069 1070 unsigned Register = DPairDecoderTable[RegNo]; 1071 Inst.addOperand(MCOperand::CreateReg(Register)); 1072 return MCDisassembler::Success; 1073 } 1074 1075 static const uint16_t DPairSpacedDecoderTable[] = { 1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1083 ARM::D28_D30, ARM::D29_D31 1084 }; 1085 1086 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1087 unsigned RegNo, 1088 uint64_t Address, 1089 const void *Decoder) { 1090 if (RegNo > 29) 1091 return MCDisassembler::Fail; 1092 1093 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1094 Inst.addOperand(MCOperand::CreateReg(Register)); 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val == 0xF) return MCDisassembler::Fail; 1101 // AL predicate is not allowed on Thumb1 branches. 1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1103 return MCDisassembler::Fail; 1104 Inst.addOperand(MCOperand::CreateImm(Val)); 1105 if (Val == ARMCC::AL) { 1106 Inst.addOperand(MCOperand::CreateReg(0)); 1107 } else 1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1109 return MCDisassembler::Success; 1110 } 1111 1112 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1113 uint64_t Address, const void *Decoder) { 1114 if (Val) 1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1116 else 1117 Inst.addOperand(MCOperand::CreateReg(0)); 1118 return MCDisassembler::Success; 1119 } 1120 1121 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1122 uint64_t Address, const void *Decoder) { 1123 uint32_t imm = Val & 0xFF; 1124 uint32_t rot = (Val & 0xF00) >> 7; 1125 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1126 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1127 return MCDisassembler::Success; 1128 } 1129 1130 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1131 uint64_t Address, const void *Decoder) { 1132 DecodeStatus S = MCDisassembler::Success; 1133 1134 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1135 unsigned type = fieldFromInstruction(Val, 5, 2); 1136 unsigned imm = fieldFromInstruction(Val, 7, 5); 1137 1138 // Register-immediate 1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1140 return MCDisassembler::Fail; 1141 1142 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1143 switch (type) { 1144 case 0: 1145 Shift = ARM_AM::lsl; 1146 break; 1147 case 1: 1148 Shift = ARM_AM::lsr; 1149 break; 1150 case 2: 1151 Shift = ARM_AM::asr; 1152 break; 1153 case 3: 1154 Shift = ARM_AM::ror; 1155 break; 1156 } 1157 1158 if (Shift == ARM_AM::ror && imm == 0) 1159 Shift = ARM_AM::rrx; 1160 1161 unsigned Op = Shift | (imm << 3); 1162 Inst.addOperand(MCOperand::CreateImm(Op)); 1163 1164 return S; 1165 } 1166 1167 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1168 uint64_t Address, const void *Decoder) { 1169 DecodeStatus S = MCDisassembler::Success; 1170 1171 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1172 unsigned type = fieldFromInstruction(Val, 5, 2); 1173 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1174 1175 // Register-register 1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1177 return MCDisassembler::Fail; 1178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1179 return MCDisassembler::Fail; 1180 1181 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1182 switch (type) { 1183 case 0: 1184 Shift = ARM_AM::lsl; 1185 break; 1186 case 1: 1187 Shift = ARM_AM::lsr; 1188 break; 1189 case 2: 1190 Shift = ARM_AM::asr; 1191 break; 1192 case 3: 1193 Shift = ARM_AM::ror; 1194 break; 1195 } 1196 1197 Inst.addOperand(MCOperand::CreateImm(Shift)); 1198 1199 return S; 1200 } 1201 1202 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1203 uint64_t Address, const void *Decoder) { 1204 DecodeStatus S = MCDisassembler::Success; 1205 1206 bool writebackLoad = false; 1207 unsigned writebackReg = 0; 1208 switch (Inst.getOpcode()) { 1209 default: 1210 break; 1211 case ARM::LDMIA_UPD: 1212 case ARM::LDMDB_UPD: 1213 case ARM::LDMIB_UPD: 1214 case ARM::LDMDA_UPD: 1215 case ARM::t2LDMIA_UPD: 1216 case ARM::t2LDMDB_UPD: 1217 writebackLoad = true; 1218 writebackReg = Inst.getOperand(0).getReg(); 1219 break; 1220 } 1221 1222 // Empty register lists are not allowed. 1223 if (Val == 0) return MCDisassembler::Fail; 1224 for (unsigned i = 0; i < 16; ++i) { 1225 if (Val & (1 << i)) { 1226 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1227 return MCDisassembler::Fail; 1228 // Writeback not allowed if Rn is in the target list. 1229 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1230 Check(S, MCDisassembler::SoftFail); 1231 } 1232 } 1233 1234 return S; 1235 } 1236 1237 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1238 uint64_t Address, const void *Decoder) { 1239 DecodeStatus S = MCDisassembler::Success; 1240 1241 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1242 unsigned regs = fieldFromInstruction(Val, 0, 8); 1243 1244 // In case of unpredictable encoding, tweak the operands. 1245 if (regs == 0 || (Vd + regs) > 32) { 1246 regs = Vd + regs > 32 ? 32 - Vd : regs; 1247 regs = std::max( 1u, regs); 1248 S = MCDisassembler::SoftFail; 1249 } 1250 1251 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1252 return MCDisassembler::Fail; 1253 for (unsigned i = 0; i < (regs - 1); ++i) { 1254 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1255 return MCDisassembler::Fail; 1256 } 1257 1258 return S; 1259 } 1260 1261 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1262 uint64_t Address, const void *Decoder) { 1263 DecodeStatus S = MCDisassembler::Success; 1264 1265 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1266 unsigned regs = fieldFromInstruction(Val, 1, 7); 1267 1268 // In case of unpredictable encoding, tweak the operands. 1269 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1270 regs = Vd + regs > 32 ? 32 - Vd : regs; 1271 regs = std::max( 1u, regs); 1272 regs = std::min(16u, regs); 1273 S = MCDisassembler::SoftFail; 1274 } 1275 1276 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1277 return MCDisassembler::Fail; 1278 for (unsigned i = 0; i < (regs - 1); ++i) { 1279 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1280 return MCDisassembler::Fail; 1281 } 1282 1283 return S; 1284 } 1285 1286 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1287 uint64_t Address, const void *Decoder) { 1288 // This operand encodes a mask of contiguous zeros between a specified MSB 1289 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1290 // the mask of all bits LSB-and-lower, and then xor them to create 1291 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1292 // create the final mask. 1293 unsigned msb = fieldFromInstruction(Val, 5, 5); 1294 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1295 1296 DecodeStatus S = MCDisassembler::Success; 1297 if (lsb > msb) { 1298 Check(S, MCDisassembler::SoftFail); 1299 // The check above will cause the warning for the "potentially undefined 1300 // instruction encoding" but we can't build a bad MCOperand value here 1301 // with a lsb > msb or else printing the MCInst will cause a crash. 1302 lsb = msb; 1303 } 1304 1305 uint32_t msb_mask = 0xFFFFFFFF; 1306 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1307 uint32_t lsb_mask = (1U << lsb) - 1; 1308 1309 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1310 return S; 1311 } 1312 1313 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1314 uint64_t Address, const void *Decoder) { 1315 DecodeStatus S = MCDisassembler::Success; 1316 1317 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1318 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1319 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1320 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1321 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1322 unsigned U = fieldFromInstruction(Insn, 23, 1); 1323 1324 switch (Inst.getOpcode()) { 1325 case ARM::LDC_OFFSET: 1326 case ARM::LDC_PRE: 1327 case ARM::LDC_POST: 1328 case ARM::LDC_OPTION: 1329 case ARM::LDCL_OFFSET: 1330 case ARM::LDCL_PRE: 1331 case ARM::LDCL_POST: 1332 case ARM::LDCL_OPTION: 1333 case ARM::STC_OFFSET: 1334 case ARM::STC_PRE: 1335 case ARM::STC_POST: 1336 case ARM::STC_OPTION: 1337 case ARM::STCL_OFFSET: 1338 case ARM::STCL_PRE: 1339 case ARM::STCL_POST: 1340 case ARM::STCL_OPTION: 1341 case ARM::t2LDC_OFFSET: 1342 case ARM::t2LDC_PRE: 1343 case ARM::t2LDC_POST: 1344 case ARM::t2LDC_OPTION: 1345 case ARM::t2LDCL_OFFSET: 1346 case ARM::t2LDCL_PRE: 1347 case ARM::t2LDCL_POST: 1348 case ARM::t2LDCL_OPTION: 1349 case ARM::t2STC_OFFSET: 1350 case ARM::t2STC_PRE: 1351 case ARM::t2STC_POST: 1352 case ARM::t2STC_OPTION: 1353 case ARM::t2STCL_OFFSET: 1354 case ARM::t2STCL_PRE: 1355 case ARM::t2STCL_POST: 1356 case ARM::t2STCL_OPTION: 1357 if (coproc == 0xA || coproc == 0xB) 1358 return MCDisassembler::Fail; 1359 break; 1360 default: 1361 break; 1362 } 1363 1364 Inst.addOperand(MCOperand::CreateImm(coproc)); 1365 Inst.addOperand(MCOperand::CreateImm(CRd)); 1366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1367 return MCDisassembler::Fail; 1368 1369 switch (Inst.getOpcode()) { 1370 case ARM::t2LDC2_OFFSET: 1371 case ARM::t2LDC2L_OFFSET: 1372 case ARM::t2LDC2_PRE: 1373 case ARM::t2LDC2L_PRE: 1374 case ARM::t2STC2_OFFSET: 1375 case ARM::t2STC2L_OFFSET: 1376 case ARM::t2STC2_PRE: 1377 case ARM::t2STC2L_PRE: 1378 case ARM::LDC2_OFFSET: 1379 case ARM::LDC2L_OFFSET: 1380 case ARM::LDC2_PRE: 1381 case ARM::LDC2L_PRE: 1382 case ARM::STC2_OFFSET: 1383 case ARM::STC2L_OFFSET: 1384 case ARM::STC2_PRE: 1385 case ARM::STC2L_PRE: 1386 case ARM::t2LDC_OFFSET: 1387 case ARM::t2LDCL_OFFSET: 1388 case ARM::t2LDC_PRE: 1389 case ARM::t2LDCL_PRE: 1390 case ARM::t2STC_OFFSET: 1391 case ARM::t2STCL_OFFSET: 1392 case ARM::t2STC_PRE: 1393 case ARM::t2STCL_PRE: 1394 case ARM::LDC_OFFSET: 1395 case ARM::LDCL_OFFSET: 1396 case ARM::LDC_PRE: 1397 case ARM::LDCL_PRE: 1398 case ARM::STC_OFFSET: 1399 case ARM::STCL_OFFSET: 1400 case ARM::STC_PRE: 1401 case ARM::STCL_PRE: 1402 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1403 Inst.addOperand(MCOperand::CreateImm(imm)); 1404 break; 1405 case ARM::t2LDC2_POST: 1406 case ARM::t2LDC2L_POST: 1407 case ARM::t2STC2_POST: 1408 case ARM::t2STC2L_POST: 1409 case ARM::LDC2_POST: 1410 case ARM::LDC2L_POST: 1411 case ARM::STC2_POST: 1412 case ARM::STC2L_POST: 1413 case ARM::t2LDC_POST: 1414 case ARM::t2LDCL_POST: 1415 case ARM::t2STC_POST: 1416 case ARM::t2STCL_POST: 1417 case ARM::LDC_POST: 1418 case ARM::LDCL_POST: 1419 case ARM::STC_POST: 1420 case ARM::STCL_POST: 1421 imm |= U << 8; 1422 // fall through. 1423 default: 1424 // The 'option' variant doesn't encode 'U' in the immediate since 1425 // the immediate is unsigned [0,255]. 1426 Inst.addOperand(MCOperand::CreateImm(imm)); 1427 break; 1428 } 1429 1430 switch (Inst.getOpcode()) { 1431 case ARM::LDC_OFFSET: 1432 case ARM::LDC_PRE: 1433 case ARM::LDC_POST: 1434 case ARM::LDC_OPTION: 1435 case ARM::LDCL_OFFSET: 1436 case ARM::LDCL_PRE: 1437 case ARM::LDCL_POST: 1438 case ARM::LDCL_OPTION: 1439 case ARM::STC_OFFSET: 1440 case ARM::STC_PRE: 1441 case ARM::STC_POST: 1442 case ARM::STC_OPTION: 1443 case ARM::STCL_OFFSET: 1444 case ARM::STCL_PRE: 1445 case ARM::STCL_POST: 1446 case ARM::STCL_OPTION: 1447 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1448 return MCDisassembler::Fail; 1449 break; 1450 default: 1451 break; 1452 } 1453 1454 return S; 1455 } 1456 1457 static DecodeStatus 1458 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1459 uint64_t Address, const void *Decoder) { 1460 DecodeStatus S = MCDisassembler::Success; 1461 1462 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1463 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1464 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1465 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1466 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1467 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1468 unsigned P = fieldFromInstruction(Insn, 24, 1); 1469 unsigned W = fieldFromInstruction(Insn, 21, 1); 1470 1471 // On stores, the writeback operand precedes Rt. 1472 switch (Inst.getOpcode()) { 1473 case ARM::STR_POST_IMM: 1474 case ARM::STR_POST_REG: 1475 case ARM::STRB_POST_IMM: 1476 case ARM::STRB_POST_REG: 1477 case ARM::STRT_POST_REG: 1478 case ARM::STRT_POST_IMM: 1479 case ARM::STRBT_POST_REG: 1480 case ARM::STRBT_POST_IMM: 1481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1482 return MCDisassembler::Fail; 1483 break; 1484 default: 1485 break; 1486 } 1487 1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1489 return MCDisassembler::Fail; 1490 1491 // On loads, the writeback operand comes after Rt. 1492 switch (Inst.getOpcode()) { 1493 case ARM::LDR_POST_IMM: 1494 case ARM::LDR_POST_REG: 1495 case ARM::LDRB_POST_IMM: 1496 case ARM::LDRB_POST_REG: 1497 case ARM::LDRBT_POST_REG: 1498 case ARM::LDRBT_POST_IMM: 1499 case ARM::LDRT_POST_REG: 1500 case ARM::LDRT_POST_IMM: 1501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1502 return MCDisassembler::Fail; 1503 break; 1504 default: 1505 break; 1506 } 1507 1508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1509 return MCDisassembler::Fail; 1510 1511 ARM_AM::AddrOpc Op = ARM_AM::add; 1512 if (!fieldFromInstruction(Insn, 23, 1)) 1513 Op = ARM_AM::sub; 1514 1515 bool writeback = (P == 0) || (W == 1); 1516 unsigned idx_mode = 0; 1517 if (P && writeback) 1518 idx_mode = ARMII::IndexModePre; 1519 else if (!P && writeback) 1520 idx_mode = ARMII::IndexModePost; 1521 1522 if (writeback && (Rn == 15 || Rn == Rt)) 1523 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1524 1525 if (reg) { 1526 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1527 return MCDisassembler::Fail; 1528 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1529 switch( fieldFromInstruction(Insn, 5, 2)) { 1530 case 0: 1531 Opc = ARM_AM::lsl; 1532 break; 1533 case 1: 1534 Opc = ARM_AM::lsr; 1535 break; 1536 case 2: 1537 Opc = ARM_AM::asr; 1538 break; 1539 case 3: 1540 Opc = ARM_AM::ror; 1541 break; 1542 default: 1543 return MCDisassembler::Fail; 1544 } 1545 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1546 if (Opc == ARM_AM::ror && amt == 0) 1547 Opc = ARM_AM::rrx; 1548 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1549 1550 Inst.addOperand(MCOperand::CreateImm(imm)); 1551 } else { 1552 Inst.addOperand(MCOperand::CreateReg(0)); 1553 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1554 Inst.addOperand(MCOperand::CreateImm(tmp)); 1555 } 1556 1557 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1558 return MCDisassembler::Fail; 1559 1560 return S; 1561 } 1562 1563 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1564 uint64_t Address, const void *Decoder) { 1565 DecodeStatus S = MCDisassembler::Success; 1566 1567 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1568 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1569 unsigned type = fieldFromInstruction(Val, 5, 2); 1570 unsigned imm = fieldFromInstruction(Val, 7, 5); 1571 unsigned U = fieldFromInstruction(Val, 12, 1); 1572 1573 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1574 switch (type) { 1575 case 0: 1576 ShOp = ARM_AM::lsl; 1577 break; 1578 case 1: 1579 ShOp = ARM_AM::lsr; 1580 break; 1581 case 2: 1582 ShOp = ARM_AM::asr; 1583 break; 1584 case 3: 1585 ShOp = ARM_AM::ror; 1586 break; 1587 } 1588 1589 if (ShOp == ARM_AM::ror && imm == 0) 1590 ShOp = ARM_AM::rrx; 1591 1592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1593 return MCDisassembler::Fail; 1594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1595 return MCDisassembler::Fail; 1596 unsigned shift; 1597 if (U) 1598 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1599 else 1600 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1601 Inst.addOperand(MCOperand::CreateImm(shift)); 1602 1603 return S; 1604 } 1605 1606 static DecodeStatus 1607 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1608 uint64_t Address, const void *Decoder) { 1609 DecodeStatus S = MCDisassembler::Success; 1610 1611 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1612 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1613 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1614 unsigned type = fieldFromInstruction(Insn, 22, 1); 1615 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1616 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1617 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1618 unsigned W = fieldFromInstruction(Insn, 21, 1); 1619 unsigned P = fieldFromInstruction(Insn, 24, 1); 1620 unsigned Rt2 = Rt + 1; 1621 1622 bool writeback = (W == 1) | (P == 0); 1623 1624 // For {LD,ST}RD, Rt must be even, else undefined. 1625 switch (Inst.getOpcode()) { 1626 case ARM::STRD: 1627 case ARM::STRD_PRE: 1628 case ARM::STRD_POST: 1629 case ARM::LDRD: 1630 case ARM::LDRD_PRE: 1631 case ARM::LDRD_POST: 1632 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1633 break; 1634 default: 1635 break; 1636 } 1637 switch (Inst.getOpcode()) { 1638 case ARM::STRD: 1639 case ARM::STRD_PRE: 1640 case ARM::STRD_POST: 1641 if (P == 0 && W == 1) 1642 S = MCDisassembler::SoftFail; 1643 1644 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1645 S = MCDisassembler::SoftFail; 1646 if (type && Rm == 15) 1647 S = MCDisassembler::SoftFail; 1648 if (Rt2 == 15) 1649 S = MCDisassembler::SoftFail; 1650 if (!type && fieldFromInstruction(Insn, 8, 4)) 1651 S = MCDisassembler::SoftFail; 1652 break; 1653 case ARM::STRH: 1654 case ARM::STRH_PRE: 1655 case ARM::STRH_POST: 1656 if (Rt == 15) 1657 S = MCDisassembler::SoftFail; 1658 if (writeback && (Rn == 15 || Rn == Rt)) 1659 S = MCDisassembler::SoftFail; 1660 if (!type && Rm == 15) 1661 S = MCDisassembler::SoftFail; 1662 break; 1663 case ARM::LDRD: 1664 case ARM::LDRD_PRE: 1665 case ARM::LDRD_POST: 1666 if (type && Rn == 15){ 1667 if (Rt2 == 15) 1668 S = MCDisassembler::SoftFail; 1669 break; 1670 } 1671 if (P == 0 && W == 1) 1672 S = MCDisassembler::SoftFail; 1673 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1674 S = MCDisassembler::SoftFail; 1675 if (!type && writeback && Rn == 15) 1676 S = MCDisassembler::SoftFail; 1677 if (writeback && (Rn == Rt || Rn == Rt2)) 1678 S = MCDisassembler::SoftFail; 1679 break; 1680 case ARM::LDRH: 1681 case ARM::LDRH_PRE: 1682 case ARM::LDRH_POST: 1683 if (type && Rn == 15){ 1684 if (Rt == 15) 1685 S = MCDisassembler::SoftFail; 1686 break; 1687 } 1688 if (Rt == 15) 1689 S = MCDisassembler::SoftFail; 1690 if (!type && Rm == 15) 1691 S = MCDisassembler::SoftFail; 1692 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1693 S = MCDisassembler::SoftFail; 1694 break; 1695 case ARM::LDRSH: 1696 case ARM::LDRSH_PRE: 1697 case ARM::LDRSH_POST: 1698 case ARM::LDRSB: 1699 case ARM::LDRSB_PRE: 1700 case ARM::LDRSB_POST: 1701 if (type && Rn == 15){ 1702 if (Rt == 15) 1703 S = MCDisassembler::SoftFail; 1704 break; 1705 } 1706 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1707 S = MCDisassembler::SoftFail; 1708 if (!type && (Rt == 15 || Rm == 15)) 1709 S = MCDisassembler::SoftFail; 1710 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1711 S = MCDisassembler::SoftFail; 1712 break; 1713 default: 1714 break; 1715 } 1716 1717 if (writeback) { // Writeback 1718 if (P) 1719 U |= ARMII::IndexModePre << 9; 1720 else 1721 U |= ARMII::IndexModePost << 9; 1722 1723 // On stores, the writeback operand precedes Rt. 1724 switch (Inst.getOpcode()) { 1725 case ARM::STRD: 1726 case ARM::STRD_PRE: 1727 case ARM::STRD_POST: 1728 case ARM::STRH: 1729 case ARM::STRH_PRE: 1730 case ARM::STRH_POST: 1731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1732 return MCDisassembler::Fail; 1733 break; 1734 default: 1735 break; 1736 } 1737 } 1738 1739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1740 return MCDisassembler::Fail; 1741 switch (Inst.getOpcode()) { 1742 case ARM::STRD: 1743 case ARM::STRD_PRE: 1744 case ARM::STRD_POST: 1745 case ARM::LDRD: 1746 case ARM::LDRD_PRE: 1747 case ARM::LDRD_POST: 1748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1749 return MCDisassembler::Fail; 1750 break; 1751 default: 1752 break; 1753 } 1754 1755 if (writeback) { 1756 // On loads, the writeback operand comes after Rt. 1757 switch (Inst.getOpcode()) { 1758 case ARM::LDRD: 1759 case ARM::LDRD_PRE: 1760 case ARM::LDRD_POST: 1761 case ARM::LDRH: 1762 case ARM::LDRH_PRE: 1763 case ARM::LDRH_POST: 1764 case ARM::LDRSH: 1765 case ARM::LDRSH_PRE: 1766 case ARM::LDRSH_POST: 1767 case ARM::LDRSB: 1768 case ARM::LDRSB_PRE: 1769 case ARM::LDRSB_POST: 1770 case ARM::LDRHTr: 1771 case ARM::LDRSBTr: 1772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1773 return MCDisassembler::Fail; 1774 break; 1775 default: 1776 break; 1777 } 1778 } 1779 1780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1781 return MCDisassembler::Fail; 1782 1783 if (type) { 1784 Inst.addOperand(MCOperand::CreateReg(0)); 1785 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1786 } else { 1787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1788 return MCDisassembler::Fail; 1789 Inst.addOperand(MCOperand::CreateImm(U)); 1790 } 1791 1792 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1793 return MCDisassembler::Fail; 1794 1795 return S; 1796 } 1797 1798 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1799 uint64_t Address, const void *Decoder) { 1800 DecodeStatus S = MCDisassembler::Success; 1801 1802 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1803 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1804 1805 switch (mode) { 1806 case 0: 1807 mode = ARM_AM::da; 1808 break; 1809 case 1: 1810 mode = ARM_AM::ia; 1811 break; 1812 case 2: 1813 mode = ARM_AM::db; 1814 break; 1815 case 3: 1816 mode = ARM_AM::ib; 1817 break; 1818 } 1819 1820 Inst.addOperand(MCOperand::CreateImm(mode)); 1821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1822 return MCDisassembler::Fail; 1823 1824 return S; 1825 } 1826 1827 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1828 uint64_t Address, const void *Decoder) { 1829 DecodeStatus S = MCDisassembler::Success; 1830 1831 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1832 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1833 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1834 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1835 1836 if (pred == 0xF) 1837 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1838 1839 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1840 return MCDisassembler::Fail; 1841 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1842 return MCDisassembler::Fail; 1843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1844 return MCDisassembler::Fail; 1845 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1846 return MCDisassembler::Fail; 1847 return S; 1848 } 1849 1850 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1851 unsigned Insn, 1852 uint64_t Address, const void *Decoder) { 1853 DecodeStatus S = MCDisassembler::Success; 1854 1855 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1856 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1857 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1858 1859 if (pred == 0xF) { 1860 // Ambiguous with RFE and SRS 1861 switch (Inst.getOpcode()) { 1862 case ARM::LDMDA: 1863 Inst.setOpcode(ARM::RFEDA); 1864 break; 1865 case ARM::LDMDA_UPD: 1866 Inst.setOpcode(ARM::RFEDA_UPD); 1867 break; 1868 case ARM::LDMDB: 1869 Inst.setOpcode(ARM::RFEDB); 1870 break; 1871 case ARM::LDMDB_UPD: 1872 Inst.setOpcode(ARM::RFEDB_UPD); 1873 break; 1874 case ARM::LDMIA: 1875 Inst.setOpcode(ARM::RFEIA); 1876 break; 1877 case ARM::LDMIA_UPD: 1878 Inst.setOpcode(ARM::RFEIA_UPD); 1879 break; 1880 case ARM::LDMIB: 1881 Inst.setOpcode(ARM::RFEIB); 1882 break; 1883 case ARM::LDMIB_UPD: 1884 Inst.setOpcode(ARM::RFEIB_UPD); 1885 break; 1886 case ARM::STMDA: 1887 Inst.setOpcode(ARM::SRSDA); 1888 break; 1889 case ARM::STMDA_UPD: 1890 Inst.setOpcode(ARM::SRSDA_UPD); 1891 break; 1892 case ARM::STMDB: 1893 Inst.setOpcode(ARM::SRSDB); 1894 break; 1895 case ARM::STMDB_UPD: 1896 Inst.setOpcode(ARM::SRSDB_UPD); 1897 break; 1898 case ARM::STMIA: 1899 Inst.setOpcode(ARM::SRSIA); 1900 break; 1901 case ARM::STMIA_UPD: 1902 Inst.setOpcode(ARM::SRSIA_UPD); 1903 break; 1904 case ARM::STMIB: 1905 Inst.setOpcode(ARM::SRSIB); 1906 break; 1907 case ARM::STMIB_UPD: 1908 Inst.setOpcode(ARM::SRSIB_UPD); 1909 break; 1910 default: 1911 return MCDisassembler::Fail; 1912 } 1913 1914 // For stores (which become SRS's, the only operand is the mode. 1915 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1916 // Check SRS encoding constraints 1917 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1918 fieldFromInstruction(Insn, 20, 1) == 0)) 1919 return MCDisassembler::Fail; 1920 1921 Inst.addOperand( 1922 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1923 return S; 1924 } 1925 1926 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1927 } 1928 1929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1930 return MCDisassembler::Fail; 1931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1932 return MCDisassembler::Fail; // Tied 1933 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1934 return MCDisassembler::Fail; 1935 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1936 return MCDisassembler::Fail; 1937 1938 return S; 1939 } 1940 1941 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1942 uint64_t Address, const void *Decoder) { 1943 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1944 unsigned M = fieldFromInstruction(Insn, 17, 1); 1945 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1946 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1947 1948 DecodeStatus S = MCDisassembler::Success; 1949 1950 // This decoder is called from multiple location that do not check 1951 // the full encoding is valid before they do. 1952 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1953 fieldFromInstruction(Insn, 16, 1) != 0 || 1954 fieldFromInstruction(Insn, 20, 8) != 0x10) 1955 return MCDisassembler::Fail; 1956 1957 // imod == '01' --> UNPREDICTABLE 1958 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1959 // return failure here. The '01' imod value is unprintable, so there's 1960 // nothing useful we could do even if we returned UNPREDICTABLE. 1961 1962 if (imod == 1) return MCDisassembler::Fail; 1963 1964 if (imod && M) { 1965 Inst.setOpcode(ARM::CPS3p); 1966 Inst.addOperand(MCOperand::CreateImm(imod)); 1967 Inst.addOperand(MCOperand::CreateImm(iflags)); 1968 Inst.addOperand(MCOperand::CreateImm(mode)); 1969 } else if (imod && !M) { 1970 Inst.setOpcode(ARM::CPS2p); 1971 Inst.addOperand(MCOperand::CreateImm(imod)); 1972 Inst.addOperand(MCOperand::CreateImm(iflags)); 1973 if (mode) S = MCDisassembler::SoftFail; 1974 } else if (!imod && M) { 1975 Inst.setOpcode(ARM::CPS1p); 1976 Inst.addOperand(MCOperand::CreateImm(mode)); 1977 if (iflags) S = MCDisassembler::SoftFail; 1978 } else { 1979 // imod == '00' && M == '0' --> UNPREDICTABLE 1980 Inst.setOpcode(ARM::CPS1p); 1981 Inst.addOperand(MCOperand::CreateImm(mode)); 1982 S = MCDisassembler::SoftFail; 1983 } 1984 1985 return S; 1986 } 1987 1988 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1989 uint64_t Address, const void *Decoder) { 1990 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1991 unsigned M = fieldFromInstruction(Insn, 8, 1); 1992 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1993 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1994 1995 DecodeStatus S = MCDisassembler::Success; 1996 1997 // imod == '01' --> UNPREDICTABLE 1998 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1999 // return failure here. The '01' imod value is unprintable, so there's 2000 // nothing useful we could do even if we returned UNPREDICTABLE. 2001 2002 if (imod == 1) return MCDisassembler::Fail; 2003 2004 if (imod && M) { 2005 Inst.setOpcode(ARM::t2CPS3p); 2006 Inst.addOperand(MCOperand::CreateImm(imod)); 2007 Inst.addOperand(MCOperand::CreateImm(iflags)); 2008 Inst.addOperand(MCOperand::CreateImm(mode)); 2009 } else if (imod && !M) { 2010 Inst.setOpcode(ARM::t2CPS2p); 2011 Inst.addOperand(MCOperand::CreateImm(imod)); 2012 Inst.addOperand(MCOperand::CreateImm(iflags)); 2013 if (mode) S = MCDisassembler::SoftFail; 2014 } else if (!imod && M) { 2015 Inst.setOpcode(ARM::t2CPS1p); 2016 Inst.addOperand(MCOperand::CreateImm(mode)); 2017 if (iflags) S = MCDisassembler::SoftFail; 2018 } else { 2019 // imod == '00' && M == '0' --> this is a HINT instruction 2020 int imm = fieldFromInstruction(Insn, 0, 8); 2021 // HINT are defined only for immediate in [0..4] 2022 if(imm > 4) return MCDisassembler::Fail; 2023 Inst.setOpcode(ARM::t2HINT); 2024 Inst.addOperand(MCOperand::CreateImm(imm)); 2025 } 2026 2027 return S; 2028 } 2029 2030 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2031 uint64_t Address, const void *Decoder) { 2032 DecodeStatus S = MCDisassembler::Success; 2033 2034 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2035 unsigned imm = 0; 2036 2037 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2038 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2039 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2040 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2041 2042 if (Inst.getOpcode() == ARM::t2MOVTi16) 2043 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2044 return MCDisassembler::Fail; 2045 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2046 return MCDisassembler::Fail; 2047 2048 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2049 Inst.addOperand(MCOperand::CreateImm(imm)); 2050 2051 return S; 2052 } 2053 2054 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2055 uint64_t Address, const void *Decoder) { 2056 DecodeStatus S = MCDisassembler::Success; 2057 2058 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2059 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2060 unsigned imm = 0; 2061 2062 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2063 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2064 2065 if (Inst.getOpcode() == ARM::MOVTi16) 2066 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2067 return MCDisassembler::Fail; 2068 2069 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2070 return MCDisassembler::Fail; 2071 2072 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2073 Inst.addOperand(MCOperand::CreateImm(imm)); 2074 2075 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2076 return MCDisassembler::Fail; 2077 2078 return S; 2079 } 2080 2081 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2082 uint64_t Address, const void *Decoder) { 2083 DecodeStatus S = MCDisassembler::Success; 2084 2085 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2086 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2087 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2088 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2089 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2090 2091 if (pred == 0xF) 2092 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2093 2094 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2095 return MCDisassembler::Fail; 2096 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2097 return MCDisassembler::Fail; 2098 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2099 return MCDisassembler::Fail; 2100 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2101 return MCDisassembler::Fail; 2102 2103 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2104 return MCDisassembler::Fail; 2105 2106 return S; 2107 } 2108 2109 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2110 uint64_t Address, const void *Decoder) { 2111 DecodeStatus S = MCDisassembler::Success; 2112 2113 unsigned add = fieldFromInstruction(Val, 12, 1); 2114 unsigned imm = fieldFromInstruction(Val, 0, 12); 2115 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2116 2117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 2120 if (!add) imm *= -1; 2121 if (imm == 0 && !add) imm = INT32_MIN; 2122 Inst.addOperand(MCOperand::CreateImm(imm)); 2123 if (Rn == 15) 2124 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2125 2126 return S; 2127 } 2128 2129 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2130 uint64_t Address, const void *Decoder) { 2131 DecodeStatus S = MCDisassembler::Success; 2132 2133 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2134 unsigned U = fieldFromInstruction(Val, 8, 1); 2135 unsigned imm = fieldFromInstruction(Val, 0, 8); 2136 2137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2138 return MCDisassembler::Fail; 2139 2140 if (U) 2141 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2142 else 2143 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2144 2145 return S; 2146 } 2147 2148 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2149 uint64_t Address, const void *Decoder) { 2150 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2151 } 2152 2153 static DecodeStatus 2154 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2155 uint64_t Address, const void *Decoder) { 2156 DecodeStatus Status = MCDisassembler::Success; 2157 2158 // Note the J1 and J2 values are from the encoded instruction. So here 2159 // change them to I1 and I2 values via as documented: 2160 // I1 = NOT(J1 EOR S); 2161 // I2 = NOT(J2 EOR S); 2162 // and build the imm32 with one trailing zero as documented: 2163 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2164 unsigned S = fieldFromInstruction(Insn, 26, 1); 2165 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2166 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2167 unsigned I1 = !(J1 ^ S); 2168 unsigned I2 = !(J2 ^ S); 2169 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2170 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2171 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2172 int imm32 = SignExtend32<25>(tmp << 1); 2173 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2174 true, 4, Inst, Decoder)) 2175 Inst.addOperand(MCOperand::CreateImm(imm32)); 2176 2177 return Status; 2178 } 2179 2180 static DecodeStatus 2181 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2182 uint64_t Address, const void *Decoder) { 2183 DecodeStatus S = MCDisassembler::Success; 2184 2185 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2186 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2187 2188 if (pred == 0xF) { 2189 Inst.setOpcode(ARM::BLXi); 2190 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2191 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2192 true, 4, Inst, Decoder)) 2193 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2194 return S; 2195 } 2196 2197 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2198 true, 4, Inst, Decoder)) 2199 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2200 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2201 return MCDisassembler::Fail; 2202 2203 return S; 2204 } 2205 2206 2207 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2208 uint64_t Address, const void *Decoder) { 2209 DecodeStatus S = MCDisassembler::Success; 2210 2211 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2212 unsigned align = fieldFromInstruction(Val, 4, 2); 2213 2214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2215 return MCDisassembler::Fail; 2216 if (!align) 2217 Inst.addOperand(MCOperand::CreateImm(0)); 2218 else 2219 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2220 2221 return S; 2222 } 2223 2224 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2225 uint64_t Address, const void *Decoder) { 2226 DecodeStatus S = MCDisassembler::Success; 2227 2228 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2229 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2230 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2231 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2232 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2233 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2234 2235 // First output register 2236 switch (Inst.getOpcode()) { 2237 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2238 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2239 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2240 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2241 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2242 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2243 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2244 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2245 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2246 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2247 return MCDisassembler::Fail; 2248 break; 2249 case ARM::VLD2b16: 2250 case ARM::VLD2b32: 2251 case ARM::VLD2b8: 2252 case ARM::VLD2b16wb_fixed: 2253 case ARM::VLD2b16wb_register: 2254 case ARM::VLD2b32wb_fixed: 2255 case ARM::VLD2b32wb_register: 2256 case ARM::VLD2b8wb_fixed: 2257 case ARM::VLD2b8wb_register: 2258 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2259 return MCDisassembler::Fail; 2260 break; 2261 default: 2262 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2263 return MCDisassembler::Fail; 2264 } 2265 2266 // Second output register 2267 switch (Inst.getOpcode()) { 2268 case ARM::VLD3d8: 2269 case ARM::VLD3d16: 2270 case ARM::VLD3d32: 2271 case ARM::VLD3d8_UPD: 2272 case ARM::VLD3d16_UPD: 2273 case ARM::VLD3d32_UPD: 2274 case ARM::VLD4d8: 2275 case ARM::VLD4d16: 2276 case ARM::VLD4d32: 2277 case ARM::VLD4d8_UPD: 2278 case ARM::VLD4d16_UPD: 2279 case ARM::VLD4d32_UPD: 2280 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2281 return MCDisassembler::Fail; 2282 break; 2283 case ARM::VLD3q8: 2284 case ARM::VLD3q16: 2285 case ARM::VLD3q32: 2286 case ARM::VLD3q8_UPD: 2287 case ARM::VLD3q16_UPD: 2288 case ARM::VLD3q32_UPD: 2289 case ARM::VLD4q8: 2290 case ARM::VLD4q16: 2291 case ARM::VLD4q32: 2292 case ARM::VLD4q8_UPD: 2293 case ARM::VLD4q16_UPD: 2294 case ARM::VLD4q32_UPD: 2295 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2296 return MCDisassembler::Fail; 2297 default: 2298 break; 2299 } 2300 2301 // Third output register 2302 switch(Inst.getOpcode()) { 2303 case ARM::VLD3d8: 2304 case ARM::VLD3d16: 2305 case ARM::VLD3d32: 2306 case ARM::VLD3d8_UPD: 2307 case ARM::VLD3d16_UPD: 2308 case ARM::VLD3d32_UPD: 2309 case ARM::VLD4d8: 2310 case ARM::VLD4d16: 2311 case ARM::VLD4d32: 2312 case ARM::VLD4d8_UPD: 2313 case ARM::VLD4d16_UPD: 2314 case ARM::VLD4d32_UPD: 2315 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2316 return MCDisassembler::Fail; 2317 break; 2318 case ARM::VLD3q8: 2319 case ARM::VLD3q16: 2320 case ARM::VLD3q32: 2321 case ARM::VLD3q8_UPD: 2322 case ARM::VLD3q16_UPD: 2323 case ARM::VLD3q32_UPD: 2324 case ARM::VLD4q8: 2325 case ARM::VLD4q16: 2326 case ARM::VLD4q32: 2327 case ARM::VLD4q8_UPD: 2328 case ARM::VLD4q16_UPD: 2329 case ARM::VLD4q32_UPD: 2330 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2331 return MCDisassembler::Fail; 2332 break; 2333 default: 2334 break; 2335 } 2336 2337 // Fourth output register 2338 switch (Inst.getOpcode()) { 2339 case ARM::VLD4d8: 2340 case ARM::VLD4d16: 2341 case ARM::VLD4d32: 2342 case ARM::VLD4d8_UPD: 2343 case ARM::VLD4d16_UPD: 2344 case ARM::VLD4d32_UPD: 2345 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2346 return MCDisassembler::Fail; 2347 break; 2348 case ARM::VLD4q8: 2349 case ARM::VLD4q16: 2350 case ARM::VLD4q32: 2351 case ARM::VLD4q8_UPD: 2352 case ARM::VLD4q16_UPD: 2353 case ARM::VLD4q32_UPD: 2354 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2355 return MCDisassembler::Fail; 2356 break; 2357 default: 2358 break; 2359 } 2360 2361 // Writeback operand 2362 switch (Inst.getOpcode()) { 2363 case ARM::VLD1d8wb_fixed: 2364 case ARM::VLD1d16wb_fixed: 2365 case ARM::VLD1d32wb_fixed: 2366 case ARM::VLD1d64wb_fixed: 2367 case ARM::VLD1d8wb_register: 2368 case ARM::VLD1d16wb_register: 2369 case ARM::VLD1d32wb_register: 2370 case ARM::VLD1d64wb_register: 2371 case ARM::VLD1q8wb_fixed: 2372 case ARM::VLD1q16wb_fixed: 2373 case ARM::VLD1q32wb_fixed: 2374 case ARM::VLD1q64wb_fixed: 2375 case ARM::VLD1q8wb_register: 2376 case ARM::VLD1q16wb_register: 2377 case ARM::VLD1q32wb_register: 2378 case ARM::VLD1q64wb_register: 2379 case ARM::VLD1d8Twb_fixed: 2380 case ARM::VLD1d8Twb_register: 2381 case ARM::VLD1d16Twb_fixed: 2382 case ARM::VLD1d16Twb_register: 2383 case ARM::VLD1d32Twb_fixed: 2384 case ARM::VLD1d32Twb_register: 2385 case ARM::VLD1d64Twb_fixed: 2386 case ARM::VLD1d64Twb_register: 2387 case ARM::VLD1d8Qwb_fixed: 2388 case ARM::VLD1d8Qwb_register: 2389 case ARM::VLD1d16Qwb_fixed: 2390 case ARM::VLD1d16Qwb_register: 2391 case ARM::VLD1d32Qwb_fixed: 2392 case ARM::VLD1d32Qwb_register: 2393 case ARM::VLD1d64Qwb_fixed: 2394 case ARM::VLD1d64Qwb_register: 2395 case ARM::VLD2d8wb_fixed: 2396 case ARM::VLD2d16wb_fixed: 2397 case ARM::VLD2d32wb_fixed: 2398 case ARM::VLD2q8wb_fixed: 2399 case ARM::VLD2q16wb_fixed: 2400 case ARM::VLD2q32wb_fixed: 2401 case ARM::VLD2d8wb_register: 2402 case ARM::VLD2d16wb_register: 2403 case ARM::VLD2d32wb_register: 2404 case ARM::VLD2q8wb_register: 2405 case ARM::VLD2q16wb_register: 2406 case ARM::VLD2q32wb_register: 2407 case ARM::VLD2b8wb_fixed: 2408 case ARM::VLD2b16wb_fixed: 2409 case ARM::VLD2b32wb_fixed: 2410 case ARM::VLD2b8wb_register: 2411 case ARM::VLD2b16wb_register: 2412 case ARM::VLD2b32wb_register: 2413 Inst.addOperand(MCOperand::CreateImm(0)); 2414 break; 2415 case ARM::VLD3d8_UPD: 2416 case ARM::VLD3d16_UPD: 2417 case ARM::VLD3d32_UPD: 2418 case ARM::VLD3q8_UPD: 2419 case ARM::VLD3q16_UPD: 2420 case ARM::VLD3q32_UPD: 2421 case ARM::VLD4d8_UPD: 2422 case ARM::VLD4d16_UPD: 2423 case ARM::VLD4d32_UPD: 2424 case ARM::VLD4q8_UPD: 2425 case ARM::VLD4q16_UPD: 2426 case ARM::VLD4q32_UPD: 2427 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 break; 2430 default: 2431 break; 2432 } 2433 2434 // AddrMode6 Base (register+alignment) 2435 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2436 return MCDisassembler::Fail; 2437 2438 // AddrMode6 Offset (register) 2439 switch (Inst.getOpcode()) { 2440 default: 2441 // The below have been updated to have explicit am6offset split 2442 // between fixed and register offset. For those instructions not 2443 // yet updated, we need to add an additional reg0 operand for the 2444 // fixed variant. 2445 // 2446 // The fixed offset encodes as Rm == 0xd, so we check for that. 2447 if (Rm == 0xd) { 2448 Inst.addOperand(MCOperand::CreateReg(0)); 2449 break; 2450 } 2451 // Fall through to handle the register offset variant. 2452 case ARM::VLD1d8wb_fixed: 2453 case ARM::VLD1d16wb_fixed: 2454 case ARM::VLD1d32wb_fixed: 2455 case ARM::VLD1d64wb_fixed: 2456 case ARM::VLD1d8Twb_fixed: 2457 case ARM::VLD1d16Twb_fixed: 2458 case ARM::VLD1d32Twb_fixed: 2459 case ARM::VLD1d64Twb_fixed: 2460 case ARM::VLD1d8Qwb_fixed: 2461 case ARM::VLD1d16Qwb_fixed: 2462 case ARM::VLD1d32Qwb_fixed: 2463 case ARM::VLD1d64Qwb_fixed: 2464 case ARM::VLD1d8wb_register: 2465 case ARM::VLD1d16wb_register: 2466 case ARM::VLD1d32wb_register: 2467 case ARM::VLD1d64wb_register: 2468 case ARM::VLD1q8wb_fixed: 2469 case ARM::VLD1q16wb_fixed: 2470 case ARM::VLD1q32wb_fixed: 2471 case ARM::VLD1q64wb_fixed: 2472 case ARM::VLD1q8wb_register: 2473 case ARM::VLD1q16wb_register: 2474 case ARM::VLD1q32wb_register: 2475 case ARM::VLD1q64wb_register: 2476 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2477 // variant encodes Rm == 0xf. Anything else is a register offset post- 2478 // increment and we need to add the register operand to the instruction. 2479 if (Rm != 0xD && Rm != 0xF && 2480 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2481 return MCDisassembler::Fail; 2482 break; 2483 case ARM::VLD2d8wb_fixed: 2484 case ARM::VLD2d16wb_fixed: 2485 case ARM::VLD2d32wb_fixed: 2486 case ARM::VLD2b8wb_fixed: 2487 case ARM::VLD2b16wb_fixed: 2488 case ARM::VLD2b32wb_fixed: 2489 case ARM::VLD2q8wb_fixed: 2490 case ARM::VLD2q16wb_fixed: 2491 case ARM::VLD2q32wb_fixed: 2492 break; 2493 } 2494 2495 return S; 2496 } 2497 2498 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2499 uint64_t Address, const void *Decoder) { 2500 unsigned type = fieldFromInstruction(Insn, 8, 4); 2501 unsigned align = fieldFromInstruction(Insn, 4, 2); 2502 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2503 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2504 if (type == 10 && align == 3) return MCDisassembler::Fail; 2505 2506 unsigned load = fieldFromInstruction(Insn, 21, 1); 2507 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2508 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2509 } 2510 2511 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2512 uint64_t Address, const void *Decoder) { 2513 unsigned size = fieldFromInstruction(Insn, 6, 2); 2514 if (size == 3) return MCDisassembler::Fail; 2515 2516 unsigned type = fieldFromInstruction(Insn, 8, 4); 2517 unsigned align = fieldFromInstruction(Insn, 4, 2); 2518 if (type == 8 && align == 3) return MCDisassembler::Fail; 2519 if (type == 9 && align == 3) return MCDisassembler::Fail; 2520 2521 unsigned load = fieldFromInstruction(Insn, 21, 1); 2522 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2523 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2524 } 2525 2526 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2527 uint64_t Address, const void *Decoder) { 2528 unsigned size = fieldFromInstruction(Insn, 6, 2); 2529 if (size == 3) return MCDisassembler::Fail; 2530 2531 unsigned align = fieldFromInstruction(Insn, 4, 2); 2532 if (align & 2) return MCDisassembler::Fail; 2533 2534 unsigned load = fieldFromInstruction(Insn, 21, 1); 2535 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2536 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2537 } 2538 2539 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2540 uint64_t Address, const void *Decoder) { 2541 unsigned size = fieldFromInstruction(Insn, 6, 2); 2542 if (size == 3) return MCDisassembler::Fail; 2543 2544 unsigned load = fieldFromInstruction(Insn, 21, 1); 2545 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2546 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2547 } 2548 2549 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2550 uint64_t Address, const void *Decoder) { 2551 DecodeStatus S = MCDisassembler::Success; 2552 2553 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2554 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2555 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2556 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2557 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2558 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2559 2560 // Writeback Operand 2561 switch (Inst.getOpcode()) { 2562 case ARM::VST1d8wb_fixed: 2563 case ARM::VST1d16wb_fixed: 2564 case ARM::VST1d32wb_fixed: 2565 case ARM::VST1d64wb_fixed: 2566 case ARM::VST1d8wb_register: 2567 case ARM::VST1d16wb_register: 2568 case ARM::VST1d32wb_register: 2569 case ARM::VST1d64wb_register: 2570 case ARM::VST1q8wb_fixed: 2571 case ARM::VST1q16wb_fixed: 2572 case ARM::VST1q32wb_fixed: 2573 case ARM::VST1q64wb_fixed: 2574 case ARM::VST1q8wb_register: 2575 case ARM::VST1q16wb_register: 2576 case ARM::VST1q32wb_register: 2577 case ARM::VST1q64wb_register: 2578 case ARM::VST1d8Twb_fixed: 2579 case ARM::VST1d16Twb_fixed: 2580 case ARM::VST1d32Twb_fixed: 2581 case ARM::VST1d64Twb_fixed: 2582 case ARM::VST1d8Twb_register: 2583 case ARM::VST1d16Twb_register: 2584 case ARM::VST1d32Twb_register: 2585 case ARM::VST1d64Twb_register: 2586 case ARM::VST1d8Qwb_fixed: 2587 case ARM::VST1d16Qwb_fixed: 2588 case ARM::VST1d32Qwb_fixed: 2589 case ARM::VST1d64Qwb_fixed: 2590 case ARM::VST1d8Qwb_register: 2591 case ARM::VST1d16Qwb_register: 2592 case ARM::VST1d32Qwb_register: 2593 case ARM::VST1d64Qwb_register: 2594 case ARM::VST2d8wb_fixed: 2595 case ARM::VST2d16wb_fixed: 2596 case ARM::VST2d32wb_fixed: 2597 case ARM::VST2d8wb_register: 2598 case ARM::VST2d16wb_register: 2599 case ARM::VST2d32wb_register: 2600 case ARM::VST2q8wb_fixed: 2601 case ARM::VST2q16wb_fixed: 2602 case ARM::VST2q32wb_fixed: 2603 case ARM::VST2q8wb_register: 2604 case ARM::VST2q16wb_register: 2605 case ARM::VST2q32wb_register: 2606 case ARM::VST2b8wb_fixed: 2607 case ARM::VST2b16wb_fixed: 2608 case ARM::VST2b32wb_fixed: 2609 case ARM::VST2b8wb_register: 2610 case ARM::VST2b16wb_register: 2611 case ARM::VST2b32wb_register: 2612 if (Rm == 0xF) 2613 return MCDisassembler::Fail; 2614 Inst.addOperand(MCOperand::CreateImm(0)); 2615 break; 2616 case ARM::VST3d8_UPD: 2617 case ARM::VST3d16_UPD: 2618 case ARM::VST3d32_UPD: 2619 case ARM::VST3q8_UPD: 2620 case ARM::VST3q16_UPD: 2621 case ARM::VST3q32_UPD: 2622 case ARM::VST4d8_UPD: 2623 case ARM::VST4d16_UPD: 2624 case ARM::VST4d32_UPD: 2625 case ARM::VST4q8_UPD: 2626 case ARM::VST4q16_UPD: 2627 case ARM::VST4q32_UPD: 2628 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2629 return MCDisassembler::Fail; 2630 break; 2631 default: 2632 break; 2633 } 2634 2635 // AddrMode6 Base (register+alignment) 2636 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2637 return MCDisassembler::Fail; 2638 2639 // AddrMode6 Offset (register) 2640 switch (Inst.getOpcode()) { 2641 default: 2642 if (Rm == 0xD) 2643 Inst.addOperand(MCOperand::CreateReg(0)); 2644 else if (Rm != 0xF) { 2645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2646 return MCDisassembler::Fail; 2647 } 2648 break; 2649 case ARM::VST1d8wb_fixed: 2650 case ARM::VST1d16wb_fixed: 2651 case ARM::VST1d32wb_fixed: 2652 case ARM::VST1d64wb_fixed: 2653 case ARM::VST1q8wb_fixed: 2654 case ARM::VST1q16wb_fixed: 2655 case ARM::VST1q32wb_fixed: 2656 case ARM::VST1q64wb_fixed: 2657 case ARM::VST1d8Twb_fixed: 2658 case ARM::VST1d16Twb_fixed: 2659 case ARM::VST1d32Twb_fixed: 2660 case ARM::VST1d64Twb_fixed: 2661 case ARM::VST1d8Qwb_fixed: 2662 case ARM::VST1d16Qwb_fixed: 2663 case ARM::VST1d32Qwb_fixed: 2664 case ARM::VST1d64Qwb_fixed: 2665 case ARM::VST2d8wb_fixed: 2666 case ARM::VST2d16wb_fixed: 2667 case ARM::VST2d32wb_fixed: 2668 case ARM::VST2q8wb_fixed: 2669 case ARM::VST2q16wb_fixed: 2670 case ARM::VST2q32wb_fixed: 2671 case ARM::VST2b8wb_fixed: 2672 case ARM::VST2b16wb_fixed: 2673 case ARM::VST2b32wb_fixed: 2674 break; 2675 } 2676 2677 2678 // First input register 2679 switch (Inst.getOpcode()) { 2680 case ARM::VST1q16: 2681 case ARM::VST1q32: 2682 case ARM::VST1q64: 2683 case ARM::VST1q8: 2684 case ARM::VST1q16wb_fixed: 2685 case ARM::VST1q16wb_register: 2686 case ARM::VST1q32wb_fixed: 2687 case ARM::VST1q32wb_register: 2688 case ARM::VST1q64wb_fixed: 2689 case ARM::VST1q64wb_register: 2690 case ARM::VST1q8wb_fixed: 2691 case ARM::VST1q8wb_register: 2692 case ARM::VST2d16: 2693 case ARM::VST2d32: 2694 case ARM::VST2d8: 2695 case ARM::VST2d16wb_fixed: 2696 case ARM::VST2d16wb_register: 2697 case ARM::VST2d32wb_fixed: 2698 case ARM::VST2d32wb_register: 2699 case ARM::VST2d8wb_fixed: 2700 case ARM::VST2d8wb_register: 2701 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2702 return MCDisassembler::Fail; 2703 break; 2704 case ARM::VST2b16: 2705 case ARM::VST2b32: 2706 case ARM::VST2b8: 2707 case ARM::VST2b16wb_fixed: 2708 case ARM::VST2b16wb_register: 2709 case ARM::VST2b32wb_fixed: 2710 case ARM::VST2b32wb_register: 2711 case ARM::VST2b8wb_fixed: 2712 case ARM::VST2b8wb_register: 2713 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 break; 2716 default: 2717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2718 return MCDisassembler::Fail; 2719 } 2720 2721 // Second input register 2722 switch (Inst.getOpcode()) { 2723 case ARM::VST3d8: 2724 case ARM::VST3d16: 2725 case ARM::VST3d32: 2726 case ARM::VST3d8_UPD: 2727 case ARM::VST3d16_UPD: 2728 case ARM::VST3d32_UPD: 2729 case ARM::VST4d8: 2730 case ARM::VST4d16: 2731 case ARM::VST4d32: 2732 case ARM::VST4d8_UPD: 2733 case ARM::VST4d16_UPD: 2734 case ARM::VST4d32_UPD: 2735 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 break; 2738 case ARM::VST3q8: 2739 case ARM::VST3q16: 2740 case ARM::VST3q32: 2741 case ARM::VST3q8_UPD: 2742 case ARM::VST3q16_UPD: 2743 case ARM::VST3q32_UPD: 2744 case ARM::VST4q8: 2745 case ARM::VST4q16: 2746 case ARM::VST4q32: 2747 case ARM::VST4q8_UPD: 2748 case ARM::VST4q16_UPD: 2749 case ARM::VST4q32_UPD: 2750 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 break; 2753 default: 2754 break; 2755 } 2756 2757 // Third input register 2758 switch (Inst.getOpcode()) { 2759 case ARM::VST3d8: 2760 case ARM::VST3d16: 2761 case ARM::VST3d32: 2762 case ARM::VST3d8_UPD: 2763 case ARM::VST3d16_UPD: 2764 case ARM::VST3d32_UPD: 2765 case ARM::VST4d8: 2766 case ARM::VST4d16: 2767 case ARM::VST4d32: 2768 case ARM::VST4d8_UPD: 2769 case ARM::VST4d16_UPD: 2770 case ARM::VST4d32_UPD: 2771 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2772 return MCDisassembler::Fail; 2773 break; 2774 case ARM::VST3q8: 2775 case ARM::VST3q16: 2776 case ARM::VST3q32: 2777 case ARM::VST3q8_UPD: 2778 case ARM::VST3q16_UPD: 2779 case ARM::VST3q32_UPD: 2780 case ARM::VST4q8: 2781 case ARM::VST4q16: 2782 case ARM::VST4q32: 2783 case ARM::VST4q8_UPD: 2784 case ARM::VST4q16_UPD: 2785 case ARM::VST4q32_UPD: 2786 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2787 return MCDisassembler::Fail; 2788 break; 2789 default: 2790 break; 2791 } 2792 2793 // Fourth input register 2794 switch (Inst.getOpcode()) { 2795 case ARM::VST4d8: 2796 case ARM::VST4d16: 2797 case ARM::VST4d32: 2798 case ARM::VST4d8_UPD: 2799 case ARM::VST4d16_UPD: 2800 case ARM::VST4d32_UPD: 2801 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2802 return MCDisassembler::Fail; 2803 break; 2804 case ARM::VST4q8: 2805 case ARM::VST4q16: 2806 case ARM::VST4q32: 2807 case ARM::VST4q8_UPD: 2808 case ARM::VST4q16_UPD: 2809 case ARM::VST4q32_UPD: 2810 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2811 return MCDisassembler::Fail; 2812 break; 2813 default: 2814 break; 2815 } 2816 2817 return S; 2818 } 2819 2820 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2821 uint64_t Address, const void *Decoder) { 2822 DecodeStatus S = MCDisassembler::Success; 2823 2824 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2825 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2826 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2827 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2828 unsigned align = fieldFromInstruction(Insn, 4, 1); 2829 unsigned size = fieldFromInstruction(Insn, 6, 2); 2830 2831 if (size == 0 && align == 1) 2832 return MCDisassembler::Fail; 2833 align *= (1 << size); 2834 2835 switch (Inst.getOpcode()) { 2836 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2837 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2838 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2839 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2840 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2841 return MCDisassembler::Fail; 2842 break; 2843 default: 2844 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2845 return MCDisassembler::Fail; 2846 break; 2847 } 2848 if (Rm != 0xF) { 2849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2850 return MCDisassembler::Fail; 2851 } 2852 2853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2854 return MCDisassembler::Fail; 2855 Inst.addOperand(MCOperand::CreateImm(align)); 2856 2857 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2858 // variant encodes Rm == 0xf. Anything else is a register offset post- 2859 // increment and we need to add the register operand to the instruction. 2860 if (Rm != 0xD && Rm != 0xF && 2861 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2862 return MCDisassembler::Fail; 2863 2864 return S; 2865 } 2866 2867 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2868 uint64_t Address, const void *Decoder) { 2869 DecodeStatus S = MCDisassembler::Success; 2870 2871 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2872 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2873 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2874 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2875 unsigned align = fieldFromInstruction(Insn, 4, 1); 2876 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2877 align *= 2*size; 2878 2879 switch (Inst.getOpcode()) { 2880 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2881 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2882 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2883 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2884 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2885 return MCDisassembler::Fail; 2886 break; 2887 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2888 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2889 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2890 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2891 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2892 return MCDisassembler::Fail; 2893 break; 2894 default: 2895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2896 return MCDisassembler::Fail; 2897 break; 2898 } 2899 2900 if (Rm != 0xF) 2901 Inst.addOperand(MCOperand::CreateImm(0)); 2902 2903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2904 return MCDisassembler::Fail; 2905 Inst.addOperand(MCOperand::CreateImm(align)); 2906 2907 if (Rm != 0xD && Rm != 0xF) { 2908 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 } 2911 2912 return S; 2913 } 2914 2915 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2916 uint64_t Address, const void *Decoder) { 2917 DecodeStatus S = MCDisassembler::Success; 2918 2919 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2920 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2921 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2922 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2923 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2924 2925 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2926 return MCDisassembler::Fail; 2927 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2928 return MCDisassembler::Fail; 2929 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2930 return MCDisassembler::Fail; 2931 if (Rm != 0xF) { 2932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2933 return MCDisassembler::Fail; 2934 } 2935 2936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2937 return MCDisassembler::Fail; 2938 Inst.addOperand(MCOperand::CreateImm(0)); 2939 2940 if (Rm == 0xD) 2941 Inst.addOperand(MCOperand::CreateReg(0)); 2942 else if (Rm != 0xF) { 2943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2944 return MCDisassembler::Fail; 2945 } 2946 2947 return S; 2948 } 2949 2950 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2951 uint64_t Address, const void *Decoder) { 2952 DecodeStatus S = MCDisassembler::Success; 2953 2954 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2955 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2956 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2957 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2958 unsigned size = fieldFromInstruction(Insn, 6, 2); 2959 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2960 unsigned align = fieldFromInstruction(Insn, 4, 1); 2961 2962 if (size == 0x3) { 2963 if (align == 0) 2964 return MCDisassembler::Fail; 2965 size = 4; 2966 align = 16; 2967 } else { 2968 if (size == 2) { 2969 size = 1 << size; 2970 align *= 8; 2971 } else { 2972 size = 1 << size; 2973 align *= 4*size; 2974 } 2975 } 2976 2977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2978 return MCDisassembler::Fail; 2979 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2982 return MCDisassembler::Fail; 2983 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 if (Rm != 0xF) { 2986 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2987 return MCDisassembler::Fail; 2988 } 2989 2990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2991 return MCDisassembler::Fail; 2992 Inst.addOperand(MCOperand::CreateImm(align)); 2993 2994 if (Rm == 0xD) 2995 Inst.addOperand(MCOperand::CreateReg(0)); 2996 else if (Rm != 0xF) { 2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2998 return MCDisassembler::Fail; 2999 } 3000 3001 return S; 3002 } 3003 3004 static DecodeStatus 3005 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3006 uint64_t Address, const void *Decoder) { 3007 DecodeStatus S = MCDisassembler::Success; 3008 3009 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3010 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3011 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3012 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3013 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3014 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3015 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3016 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3017 3018 if (Q) { 3019 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3020 return MCDisassembler::Fail; 3021 } else { 3022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3023 return MCDisassembler::Fail; 3024 } 3025 3026 Inst.addOperand(MCOperand::CreateImm(imm)); 3027 3028 switch (Inst.getOpcode()) { 3029 case ARM::VORRiv4i16: 3030 case ARM::VORRiv2i32: 3031 case ARM::VBICiv4i16: 3032 case ARM::VBICiv2i32: 3033 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3034 return MCDisassembler::Fail; 3035 break; 3036 case ARM::VORRiv8i16: 3037 case ARM::VORRiv4i32: 3038 case ARM::VBICiv8i16: 3039 case ARM::VBICiv4i32: 3040 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3041 return MCDisassembler::Fail; 3042 break; 3043 default: 3044 break; 3045 } 3046 3047 return S; 3048 } 3049 3050 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3051 uint64_t Address, const void *Decoder) { 3052 DecodeStatus S = MCDisassembler::Success; 3053 3054 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3055 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3056 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3057 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3058 unsigned size = fieldFromInstruction(Insn, 18, 2); 3059 3060 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3061 return MCDisassembler::Fail; 3062 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3065 3066 return S; 3067 } 3068 3069 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3070 uint64_t Address, const void *Decoder) { 3071 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3072 return MCDisassembler::Success; 3073 } 3074 3075 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3076 uint64_t Address, const void *Decoder) { 3077 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3078 return MCDisassembler::Success; 3079 } 3080 3081 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3082 uint64_t Address, const void *Decoder) { 3083 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3084 return MCDisassembler::Success; 3085 } 3086 3087 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3088 uint64_t Address, const void *Decoder) { 3089 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3090 return MCDisassembler::Success; 3091 } 3092 3093 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3094 uint64_t Address, const void *Decoder) { 3095 DecodeStatus S = MCDisassembler::Success; 3096 3097 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3098 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3099 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3100 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3101 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3102 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3103 unsigned op = fieldFromInstruction(Insn, 6, 1); 3104 3105 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 if (op) { 3108 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3109 return MCDisassembler::Fail; // Writeback 3110 } 3111 3112 switch (Inst.getOpcode()) { 3113 case ARM::VTBL2: 3114 case ARM::VTBX2: 3115 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3116 return MCDisassembler::Fail; 3117 break; 3118 default: 3119 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3120 return MCDisassembler::Fail; 3121 } 3122 3123 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 3126 return S; 3127 } 3128 3129 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3130 uint64_t Address, const void *Decoder) { 3131 DecodeStatus S = MCDisassembler::Success; 3132 3133 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3134 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3135 3136 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3137 return MCDisassembler::Fail; 3138 3139 switch(Inst.getOpcode()) { 3140 default: 3141 return MCDisassembler::Fail; 3142 case ARM::tADR: 3143 break; // tADR does not explicitly represent the PC as an operand. 3144 case ARM::tADDrSPi: 3145 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3146 break; 3147 } 3148 3149 Inst.addOperand(MCOperand::CreateImm(imm)); 3150 return S; 3151 } 3152 3153 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3154 uint64_t Address, const void *Decoder) { 3155 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3156 true, 2, Inst, Decoder)) 3157 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3158 return MCDisassembler::Success; 3159 } 3160 3161 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3162 uint64_t Address, const void *Decoder) { 3163 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3164 true, 4, Inst, Decoder)) 3165 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3166 return MCDisassembler::Success; 3167 } 3168 3169 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3170 uint64_t Address, const void *Decoder) { 3171 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3172 true, 2, Inst, Decoder)) 3173 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3174 return MCDisassembler::Success; 3175 } 3176 3177 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3178 uint64_t Address, const void *Decoder) { 3179 DecodeStatus S = MCDisassembler::Success; 3180 3181 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3182 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3183 3184 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3185 return MCDisassembler::Fail; 3186 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 3189 return S; 3190 } 3191 3192 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3193 uint64_t Address, const void *Decoder) { 3194 DecodeStatus S = MCDisassembler::Success; 3195 3196 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3197 unsigned imm = fieldFromInstruction(Val, 3, 5); 3198 3199 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3200 return MCDisassembler::Fail; 3201 Inst.addOperand(MCOperand::CreateImm(imm)); 3202 3203 return S; 3204 } 3205 3206 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3207 uint64_t Address, const void *Decoder) { 3208 unsigned imm = Val << 2; 3209 3210 Inst.addOperand(MCOperand::CreateImm(imm)); 3211 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3212 3213 return MCDisassembler::Success; 3214 } 3215 3216 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3217 uint64_t Address, const void *Decoder) { 3218 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3219 Inst.addOperand(MCOperand::CreateImm(Val)); 3220 3221 return MCDisassembler::Success; 3222 } 3223 3224 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3225 uint64_t Address, const void *Decoder) { 3226 DecodeStatus S = MCDisassembler::Success; 3227 3228 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3229 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3230 unsigned imm = fieldFromInstruction(Val, 0, 2); 3231 3232 // Thumb stores cannot use PC as dest register. 3233 switch (Inst.getOpcode()) { 3234 case ARM::t2STRHs: 3235 case ARM::t2STRBs: 3236 case ARM::t2STRs: 3237 if (Rn == 15) 3238 return MCDisassembler::Fail; 3239 default: 3240 break; 3241 } 3242 3243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3244 return MCDisassembler::Fail; 3245 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3246 return MCDisassembler::Fail; 3247 Inst.addOperand(MCOperand::CreateImm(imm)); 3248 3249 return S; 3250 } 3251 3252 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3253 uint64_t Address, const void *Decoder) { 3254 DecodeStatus S = MCDisassembler::Success; 3255 3256 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3257 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3258 3259 if (Rn == 15) { 3260 switch (Inst.getOpcode()) { 3261 case ARM::t2LDRBs: 3262 Inst.setOpcode(ARM::t2LDRBpci); 3263 break; 3264 case ARM::t2LDRHs: 3265 Inst.setOpcode(ARM::t2LDRHpci); 3266 break; 3267 case ARM::t2LDRSHs: 3268 Inst.setOpcode(ARM::t2LDRSHpci); 3269 break; 3270 case ARM::t2LDRSBs: 3271 Inst.setOpcode(ARM::t2LDRSBpci); 3272 break; 3273 case ARM::t2LDRs: 3274 Inst.setOpcode(ARM::t2LDRpci); 3275 break; 3276 case ARM::t2PLDs: 3277 Inst.setOpcode(ARM::t2PLDpci); 3278 break; 3279 case ARM::t2PLIs: 3280 Inst.setOpcode(ARM::t2PLIpci); 3281 break; 3282 default: 3283 return MCDisassembler::Fail; 3284 } 3285 3286 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3287 } 3288 3289 if (Rt == 15) { 3290 switch (Inst.getOpcode()) { 3291 case ARM::t2LDRSHs: 3292 return MCDisassembler::Fail; 3293 case ARM::t2LDRHs: 3294 // FIXME: this instruction is only available with MP extensions, 3295 // this should be checked first but we don't have access to the 3296 // feature bits here. 3297 Inst.setOpcode(ARM::t2PLDWs); 3298 break; 3299 default: 3300 break; 3301 } 3302 } 3303 3304 switch (Inst.getOpcode()) { 3305 case ARM::t2PLDs: 3306 case ARM::t2PLDWs: 3307 case ARM::t2PLIs: 3308 break; 3309 default: 3310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3311 return MCDisassembler::Fail; 3312 } 3313 3314 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3315 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3316 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3317 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3318 return MCDisassembler::Fail; 3319 3320 return S; 3321 } 3322 3323 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3324 uint64_t Address, const void* Decoder) { 3325 DecodeStatus S = MCDisassembler::Success; 3326 3327 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3328 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3329 unsigned U = fieldFromInstruction(Insn, 9, 1); 3330 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3331 imm |= (U << 8); 3332 imm |= (Rn << 9); 3333 3334 if (Rn == 15) { 3335 switch (Inst.getOpcode()) { 3336 case ARM::t2LDRi8: 3337 Inst.setOpcode(ARM::t2LDRpci); 3338 break; 3339 case ARM::t2LDRBi8: 3340 Inst.setOpcode(ARM::t2LDRBpci); 3341 break; 3342 case ARM::t2LDRSBi8: 3343 Inst.setOpcode(ARM::t2LDRSBpci); 3344 break; 3345 case ARM::t2LDRHi8: 3346 Inst.setOpcode(ARM::t2LDRHpci); 3347 break; 3348 case ARM::t2LDRSHi8: 3349 Inst.setOpcode(ARM::t2LDRSHpci); 3350 break; 3351 case ARM::t2PLDi8: 3352 Inst.setOpcode(ARM::t2PLDpci); 3353 break; 3354 case ARM::t2PLIi8: 3355 Inst.setOpcode(ARM::t2PLIpci); 3356 break; 3357 default: 3358 return MCDisassembler::Fail; 3359 } 3360 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3361 } 3362 3363 if (Rt == 15) { 3364 switch (Inst.getOpcode()) { 3365 case ARM::t2LDRSHi8: 3366 return MCDisassembler::Fail; 3367 default: 3368 break; 3369 } 3370 } 3371 3372 switch (Inst.getOpcode()) { 3373 case ARM::t2PLDi8: 3374 case ARM::t2PLIi8: 3375 case ARM::t2PLDWi8: 3376 break; 3377 default: 3378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3379 return MCDisassembler::Fail; 3380 } 3381 3382 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3383 return MCDisassembler::Fail; 3384 return S; 3385 } 3386 3387 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3388 uint64_t Address, const void* Decoder) { 3389 DecodeStatus S = MCDisassembler::Success; 3390 3391 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3392 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3393 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3394 imm |= (Rn << 13); 3395 3396 if (Rn == 15) { 3397 switch (Inst.getOpcode()) { 3398 case ARM::t2LDRi12: 3399 Inst.setOpcode(ARM::t2LDRpci); 3400 break; 3401 case ARM::t2LDRHi12: 3402 Inst.setOpcode(ARM::t2LDRHpci); 3403 break; 3404 case ARM::t2LDRSHi12: 3405 Inst.setOpcode(ARM::t2LDRSHpci); 3406 break; 3407 case ARM::t2LDRBi12: 3408 Inst.setOpcode(ARM::t2LDRBpci); 3409 break; 3410 case ARM::t2LDRSBi12: 3411 Inst.setOpcode(ARM::t2LDRSBpci); 3412 break; 3413 case ARM::t2PLDi12: 3414 Inst.setOpcode(ARM::t2PLDpci); 3415 break; 3416 case ARM::t2PLIi12: 3417 Inst.setOpcode(ARM::t2PLIpci); 3418 break; 3419 default: 3420 return MCDisassembler::Fail; 3421 } 3422 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3423 } 3424 3425 if (Rt == 15) { 3426 switch (Inst.getOpcode()) { 3427 case ARM::t2LDRSHi12: 3428 return MCDisassembler::Fail; 3429 case ARM::t2LDRHi12: 3430 Inst.setOpcode(ARM::t2PLDi12); 3431 break; 3432 default: 3433 break; 3434 } 3435 } 3436 3437 switch (Inst.getOpcode()) { 3438 case ARM::t2PLDi12: 3439 case ARM::t2PLDWi12: 3440 case ARM::t2PLIi12: 3441 break; 3442 default: 3443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3444 return MCDisassembler::Fail; 3445 } 3446 3447 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3448 return MCDisassembler::Fail; 3449 return S; 3450 } 3451 3452 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3453 uint64_t Address, const void* Decoder) { 3454 DecodeStatus S = MCDisassembler::Success; 3455 3456 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3457 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3458 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3459 imm |= (Rn << 9); 3460 3461 if (Rn == 15) { 3462 switch (Inst.getOpcode()) { 3463 case ARM::t2LDRT: 3464 Inst.setOpcode(ARM::t2LDRpci); 3465 break; 3466 case ARM::t2LDRBT: 3467 Inst.setOpcode(ARM::t2LDRBpci); 3468 break; 3469 case ARM::t2LDRHT: 3470 Inst.setOpcode(ARM::t2LDRHpci); 3471 break; 3472 case ARM::t2LDRSBT: 3473 Inst.setOpcode(ARM::t2LDRSBpci); 3474 break; 3475 case ARM::t2LDRSHT: 3476 Inst.setOpcode(ARM::t2LDRSHpci); 3477 break; 3478 default: 3479 return MCDisassembler::Fail; 3480 } 3481 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3482 } 3483 3484 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3485 return MCDisassembler::Fail; 3486 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3487 return MCDisassembler::Fail; 3488 return S; 3489 } 3490 3491 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3492 uint64_t Address, const void* Decoder) { 3493 DecodeStatus S = MCDisassembler::Success; 3494 3495 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3496 unsigned U = fieldFromInstruction(Insn, 23, 1); 3497 int imm = fieldFromInstruction(Insn, 0, 12); 3498 3499 if (Rt == 15) { 3500 switch (Inst.getOpcode()) { 3501 case ARM::t2LDRBpci: 3502 case ARM::t2LDRHpci: 3503 Inst.setOpcode(ARM::t2PLDpci); 3504 break; 3505 case ARM::t2LDRSBpci: 3506 Inst.setOpcode(ARM::t2PLIpci); 3507 break; 3508 case ARM::t2LDRSHpci: 3509 return MCDisassembler::Fail; 3510 default: 3511 break; 3512 } 3513 } 3514 3515 switch(Inst.getOpcode()) { 3516 case ARM::t2PLDpci: 3517 case ARM::t2PLIpci: 3518 break; 3519 default: 3520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3521 return MCDisassembler::Fail; 3522 } 3523 3524 if (!U) { 3525 // Special case for #-0. 3526 if (imm == 0) 3527 imm = INT32_MIN; 3528 else 3529 imm = -imm; 3530 } 3531 Inst.addOperand(MCOperand::CreateImm(imm)); 3532 3533 return S; 3534 } 3535 3536 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3537 uint64_t Address, const void *Decoder) { 3538 if (Val == 0) 3539 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3540 else { 3541 int imm = Val & 0xFF; 3542 3543 if (!(Val & 0x100)) imm *= -1; 3544 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3545 } 3546 3547 return MCDisassembler::Success; 3548 } 3549 3550 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3551 uint64_t Address, const void *Decoder) { 3552 DecodeStatus S = MCDisassembler::Success; 3553 3554 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3555 unsigned imm = fieldFromInstruction(Val, 0, 9); 3556 3557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3558 return MCDisassembler::Fail; 3559 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 3562 return S; 3563 } 3564 3565 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3566 uint64_t Address, const void *Decoder) { 3567 DecodeStatus S = MCDisassembler::Success; 3568 3569 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3570 unsigned imm = fieldFromInstruction(Val, 0, 8); 3571 3572 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 3575 Inst.addOperand(MCOperand::CreateImm(imm)); 3576 3577 return S; 3578 } 3579 3580 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3581 uint64_t Address, const void *Decoder) { 3582 int imm = Val & 0xFF; 3583 if (Val == 0) 3584 imm = INT32_MIN; 3585 else if (!(Val & 0x100)) 3586 imm *= -1; 3587 Inst.addOperand(MCOperand::CreateImm(imm)); 3588 3589 return MCDisassembler::Success; 3590 } 3591 3592 3593 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3594 uint64_t Address, const void *Decoder) { 3595 DecodeStatus S = MCDisassembler::Success; 3596 3597 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3598 unsigned imm = fieldFromInstruction(Val, 0, 9); 3599 3600 // Thumb stores cannot use PC as dest register. 3601 switch (Inst.getOpcode()) { 3602 case ARM::t2STRT: 3603 case ARM::t2STRBT: 3604 case ARM::t2STRHT: 3605 case ARM::t2STRi8: 3606 case ARM::t2STRHi8: 3607 case ARM::t2STRBi8: 3608 if (Rn == 15) 3609 return MCDisassembler::Fail; 3610 break; 3611 default: 3612 break; 3613 } 3614 3615 // Some instructions always use an additive offset. 3616 switch (Inst.getOpcode()) { 3617 case ARM::t2LDRT: 3618 case ARM::t2LDRBT: 3619 case ARM::t2LDRHT: 3620 case ARM::t2LDRSBT: 3621 case ARM::t2LDRSHT: 3622 case ARM::t2STRT: 3623 case ARM::t2STRBT: 3624 case ARM::t2STRHT: 3625 imm |= 0x100; 3626 break; 3627 default: 3628 break; 3629 } 3630 3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 3636 return S; 3637 } 3638 3639 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3640 uint64_t Address, const void *Decoder) { 3641 DecodeStatus S = MCDisassembler::Success; 3642 3643 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3644 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3645 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3646 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3647 addr |= Rn << 9; 3648 unsigned load = fieldFromInstruction(Insn, 20, 1); 3649 3650 if (Rn == 15) { 3651 switch (Inst.getOpcode()) { 3652 case ARM::t2LDR_PRE: 3653 case ARM::t2LDR_POST: 3654 Inst.setOpcode(ARM::t2LDRpci); 3655 break; 3656 case ARM::t2LDRB_PRE: 3657 case ARM::t2LDRB_POST: 3658 Inst.setOpcode(ARM::t2LDRBpci); 3659 break; 3660 case ARM::t2LDRH_PRE: 3661 case ARM::t2LDRH_POST: 3662 Inst.setOpcode(ARM::t2LDRHpci); 3663 break; 3664 case ARM::t2LDRSB_PRE: 3665 case ARM::t2LDRSB_POST: 3666 if (Rt == 15) 3667 Inst.setOpcode(ARM::t2PLIpci); 3668 else 3669 Inst.setOpcode(ARM::t2LDRSBpci); 3670 break; 3671 case ARM::t2LDRSH_PRE: 3672 case ARM::t2LDRSH_POST: 3673 Inst.setOpcode(ARM::t2LDRSHpci); 3674 break; 3675 default: 3676 return MCDisassembler::Fail; 3677 } 3678 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3679 } 3680 3681 if (!load) { 3682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3683 return MCDisassembler::Fail; 3684 } 3685 3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 3689 if (load) { 3690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3691 return MCDisassembler::Fail; 3692 } 3693 3694 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3695 return MCDisassembler::Fail; 3696 3697 return S; 3698 } 3699 3700 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3701 uint64_t Address, const void *Decoder) { 3702 DecodeStatus S = MCDisassembler::Success; 3703 3704 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3705 unsigned imm = fieldFromInstruction(Val, 0, 12); 3706 3707 // Thumb stores cannot use PC as dest register. 3708 switch (Inst.getOpcode()) { 3709 case ARM::t2STRi12: 3710 case ARM::t2STRBi12: 3711 case ARM::t2STRHi12: 3712 if (Rn == 15) 3713 return MCDisassembler::Fail; 3714 default: 3715 break; 3716 } 3717 3718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3719 return MCDisassembler::Fail; 3720 Inst.addOperand(MCOperand::CreateImm(imm)); 3721 3722 return S; 3723 } 3724 3725 3726 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3727 uint64_t Address, const void *Decoder) { 3728 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3729 3730 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3731 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3732 Inst.addOperand(MCOperand::CreateImm(imm)); 3733 3734 return MCDisassembler::Success; 3735 } 3736 3737 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3738 uint64_t Address, const void *Decoder) { 3739 DecodeStatus S = MCDisassembler::Success; 3740 3741 if (Inst.getOpcode() == ARM::tADDrSP) { 3742 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3743 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3744 3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3749 return MCDisassembler::Fail; 3750 } else if (Inst.getOpcode() == ARM::tADDspr) { 3751 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3752 3753 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3754 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3756 return MCDisassembler::Fail; 3757 } 3758 3759 return S; 3760 } 3761 3762 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3763 uint64_t Address, const void *Decoder) { 3764 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3765 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3766 3767 Inst.addOperand(MCOperand::CreateImm(imod)); 3768 Inst.addOperand(MCOperand::CreateImm(flags)); 3769 3770 return MCDisassembler::Success; 3771 } 3772 3773 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3774 uint64_t Address, const void *Decoder) { 3775 DecodeStatus S = MCDisassembler::Success; 3776 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3777 unsigned add = fieldFromInstruction(Insn, 4, 1); 3778 3779 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3780 return MCDisassembler::Fail; 3781 Inst.addOperand(MCOperand::CreateImm(add)); 3782 3783 return S; 3784 } 3785 3786 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3787 uint64_t Address, const void *Decoder) { 3788 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3789 // Note only one trailing zero not two. Also the J1 and J2 values are from 3790 // the encoded instruction. So here change to I1 and I2 values via: 3791 // I1 = NOT(J1 EOR S); 3792 // I2 = NOT(J2 EOR S); 3793 // and build the imm32 with two trailing zeros as documented: 3794 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3795 unsigned S = (Val >> 23) & 1; 3796 unsigned J1 = (Val >> 22) & 1; 3797 unsigned J2 = (Val >> 21) & 1; 3798 unsigned I1 = !(J1 ^ S); 3799 unsigned I2 = !(J2 ^ S); 3800 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3801 int imm32 = SignExtend32<25>(tmp << 1); 3802 3803 if (!tryAddingSymbolicOperand(Address, 3804 (Address & ~2u) + imm32 + 4, 3805 true, 4, Inst, Decoder)) 3806 Inst.addOperand(MCOperand::CreateImm(imm32)); 3807 return MCDisassembler::Success; 3808 } 3809 3810 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3811 uint64_t Address, const void *Decoder) { 3812 if (Val == 0xA || Val == 0xB) 3813 return MCDisassembler::Fail; 3814 3815 Inst.addOperand(MCOperand::CreateImm(Val)); 3816 return MCDisassembler::Success; 3817 } 3818 3819 static DecodeStatus 3820 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3821 uint64_t Address, const void *Decoder) { 3822 DecodeStatus S = MCDisassembler::Success; 3823 3824 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3825 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3826 3827 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3829 return MCDisassembler::Fail; 3830 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3831 return MCDisassembler::Fail; 3832 return S; 3833 } 3834 3835 static DecodeStatus 3836 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3837 uint64_t Address, const void *Decoder) { 3838 DecodeStatus S = MCDisassembler::Success; 3839 3840 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3841 if (pred == 0xE || pred == 0xF) { 3842 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3843 switch (opc) { 3844 default: 3845 return MCDisassembler::Fail; 3846 case 0xf3bf8f4: 3847 Inst.setOpcode(ARM::t2DSB); 3848 break; 3849 case 0xf3bf8f5: 3850 Inst.setOpcode(ARM::t2DMB); 3851 break; 3852 case 0xf3bf8f6: 3853 Inst.setOpcode(ARM::t2ISB); 3854 break; 3855 } 3856 3857 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3858 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3859 } 3860 3861 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3862 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3863 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3864 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3865 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3866 3867 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3868 return MCDisassembler::Fail; 3869 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 3872 return S; 3873 } 3874 3875 // Decode a shifted immediate operand. These basically consist 3876 // of an 8-bit value, and a 4-bit directive that specifies either 3877 // a splat operation or a rotation. 3878 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3879 uint64_t Address, const void *Decoder) { 3880 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3881 if (ctrl == 0) { 3882 unsigned byte = fieldFromInstruction(Val, 8, 2); 3883 unsigned imm = fieldFromInstruction(Val, 0, 8); 3884 switch (byte) { 3885 case 0: 3886 Inst.addOperand(MCOperand::CreateImm(imm)); 3887 break; 3888 case 1: 3889 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3890 break; 3891 case 2: 3892 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3893 break; 3894 case 3: 3895 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3896 (imm << 8) | imm)); 3897 break; 3898 } 3899 } else { 3900 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3901 unsigned rot = fieldFromInstruction(Val, 7, 5); 3902 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3903 Inst.addOperand(MCOperand::CreateImm(imm)); 3904 } 3905 3906 return MCDisassembler::Success; 3907 } 3908 3909 static DecodeStatus 3910 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3911 uint64_t Address, const void *Decoder){ 3912 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3913 true, 2, Inst, Decoder)) 3914 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3915 return MCDisassembler::Success; 3916 } 3917 3918 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3919 uint64_t Address, const void *Decoder){ 3920 // Val is passed in as S:J1:J2:imm10:imm11 3921 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3922 // the encoded instruction. So here change to I1 and I2 values via: 3923 // I1 = NOT(J1 EOR S); 3924 // I2 = NOT(J2 EOR S); 3925 // and build the imm32 with one trailing zero as documented: 3926 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3927 unsigned S = (Val >> 23) & 1; 3928 unsigned J1 = (Val >> 22) & 1; 3929 unsigned J2 = (Val >> 21) & 1; 3930 unsigned I1 = !(J1 ^ S); 3931 unsigned I2 = !(J2 ^ S); 3932 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3933 int imm32 = SignExtend32<25>(tmp << 1); 3934 3935 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3936 true, 4, Inst, Decoder)) 3937 Inst.addOperand(MCOperand::CreateImm(imm32)); 3938 return MCDisassembler::Success; 3939 } 3940 3941 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3942 uint64_t Address, const void *Decoder) { 3943 if (Val & ~0xf) 3944 return MCDisassembler::Fail; 3945 3946 Inst.addOperand(MCOperand::CreateImm(Val)); 3947 return MCDisassembler::Success; 3948 } 3949 3950 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 3951 uint64_t Address, const void *Decoder) { 3952 if (Val & ~0xf) 3953 return MCDisassembler::Fail; 3954 3955 Inst.addOperand(MCOperand::CreateImm(Val)); 3956 return MCDisassembler::Success; 3957 } 3958 3959 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3960 uint64_t Address, const void *Decoder) { 3961 if (!Val) return MCDisassembler::Fail; 3962 Inst.addOperand(MCOperand::CreateImm(Val)); 3963 return MCDisassembler::Success; 3964 } 3965 3966 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3967 uint64_t Address, const void *Decoder) { 3968 DecodeStatus S = MCDisassembler::Success; 3969 3970 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3971 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3972 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3973 3974 if (Rn == 0xF) 3975 S = MCDisassembler::SoftFail; 3976 3977 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3978 return MCDisassembler::Fail; 3979 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3980 return MCDisassembler::Fail; 3981 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3982 return MCDisassembler::Fail; 3983 3984 return S; 3985 } 3986 3987 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3988 uint64_t Address, const void *Decoder){ 3989 DecodeStatus S = MCDisassembler::Success; 3990 3991 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3992 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 3993 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3994 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3995 3996 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 3997 return MCDisassembler::Fail; 3998 3999 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4000 S = MCDisassembler::SoftFail; 4001 4002 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4005 return MCDisassembler::Fail; 4006 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4007 return MCDisassembler::Fail; 4008 4009 return S; 4010 } 4011 4012 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4013 uint64_t Address, const void *Decoder) { 4014 DecodeStatus S = MCDisassembler::Success; 4015 4016 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4017 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4018 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4019 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4020 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4021 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4022 4023 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4024 4025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4026 return MCDisassembler::Fail; 4027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4028 return MCDisassembler::Fail; 4029 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4030 return MCDisassembler::Fail; 4031 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 4034 return S; 4035 } 4036 4037 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4038 uint64_t Address, const void *Decoder) { 4039 DecodeStatus S = MCDisassembler::Success; 4040 4041 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4042 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4043 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4044 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4045 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4046 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4047 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4048 4049 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4050 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4051 4052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4053 return MCDisassembler::Fail; 4054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4055 return MCDisassembler::Fail; 4056 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4057 return MCDisassembler::Fail; 4058 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4059 return MCDisassembler::Fail; 4060 4061 return S; 4062 } 4063 4064 4065 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4066 uint64_t Address, const void *Decoder) { 4067 DecodeStatus S = MCDisassembler::Success; 4068 4069 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4070 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4071 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4072 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4073 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4074 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4075 4076 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4077 4078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4079 return MCDisassembler::Fail; 4080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4081 return MCDisassembler::Fail; 4082 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4083 return MCDisassembler::Fail; 4084 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4085 return MCDisassembler::Fail; 4086 4087 return S; 4088 } 4089 4090 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4091 uint64_t Address, const void *Decoder) { 4092 DecodeStatus S = MCDisassembler::Success; 4093 4094 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4095 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4096 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4097 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4098 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4099 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4100 4101 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4102 4103 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4104 return MCDisassembler::Fail; 4105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4106 return MCDisassembler::Fail; 4107 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4108 return MCDisassembler::Fail; 4109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4110 return MCDisassembler::Fail; 4111 4112 return S; 4113 } 4114 4115 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4116 uint64_t Address, const void *Decoder) { 4117 DecodeStatus S = MCDisassembler::Success; 4118 4119 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4120 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4121 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4122 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4123 unsigned size = fieldFromInstruction(Insn, 10, 2); 4124 4125 unsigned align = 0; 4126 unsigned index = 0; 4127 switch (size) { 4128 default: 4129 return MCDisassembler::Fail; 4130 case 0: 4131 if (fieldFromInstruction(Insn, 4, 1)) 4132 return MCDisassembler::Fail; // UNDEFINED 4133 index = fieldFromInstruction(Insn, 5, 3); 4134 break; 4135 case 1: 4136 if (fieldFromInstruction(Insn, 5, 1)) 4137 return MCDisassembler::Fail; // UNDEFINED 4138 index = fieldFromInstruction(Insn, 6, 2); 4139 if (fieldFromInstruction(Insn, 4, 1)) 4140 align = 2; 4141 break; 4142 case 2: 4143 if (fieldFromInstruction(Insn, 6, 1)) 4144 return MCDisassembler::Fail; // UNDEFINED 4145 index = fieldFromInstruction(Insn, 7, 1); 4146 4147 switch (fieldFromInstruction(Insn, 4, 2)) { 4148 case 0 : 4149 align = 0; break; 4150 case 3: 4151 align = 4; break; 4152 default: 4153 return MCDisassembler::Fail; 4154 } 4155 break; 4156 } 4157 4158 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4159 return MCDisassembler::Fail; 4160 if (Rm != 0xF) { // Writeback 4161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4162 return MCDisassembler::Fail; 4163 } 4164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4165 return MCDisassembler::Fail; 4166 Inst.addOperand(MCOperand::CreateImm(align)); 4167 if (Rm != 0xF) { 4168 if (Rm != 0xD) { 4169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4170 return MCDisassembler::Fail; 4171 } else 4172 Inst.addOperand(MCOperand::CreateReg(0)); 4173 } 4174 4175 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 Inst.addOperand(MCOperand::CreateImm(index)); 4178 4179 return S; 4180 } 4181 4182 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4183 uint64_t Address, const void *Decoder) { 4184 DecodeStatus S = MCDisassembler::Success; 4185 4186 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4187 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4188 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4189 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4190 unsigned size = fieldFromInstruction(Insn, 10, 2); 4191 4192 unsigned align = 0; 4193 unsigned index = 0; 4194 switch (size) { 4195 default: 4196 return MCDisassembler::Fail; 4197 case 0: 4198 if (fieldFromInstruction(Insn, 4, 1)) 4199 return MCDisassembler::Fail; // UNDEFINED 4200 index = fieldFromInstruction(Insn, 5, 3); 4201 break; 4202 case 1: 4203 if (fieldFromInstruction(Insn, 5, 1)) 4204 return MCDisassembler::Fail; // UNDEFINED 4205 index = fieldFromInstruction(Insn, 6, 2); 4206 if (fieldFromInstruction(Insn, 4, 1)) 4207 align = 2; 4208 break; 4209 case 2: 4210 if (fieldFromInstruction(Insn, 6, 1)) 4211 return MCDisassembler::Fail; // UNDEFINED 4212 index = fieldFromInstruction(Insn, 7, 1); 4213 4214 switch (fieldFromInstruction(Insn, 4, 2)) { 4215 case 0: 4216 align = 0; break; 4217 case 3: 4218 align = 4; break; 4219 default: 4220 return MCDisassembler::Fail; 4221 } 4222 break; 4223 } 4224 4225 if (Rm != 0xF) { // Writeback 4226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 } 4229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4230 return MCDisassembler::Fail; 4231 Inst.addOperand(MCOperand::CreateImm(align)); 4232 if (Rm != 0xF) { 4233 if (Rm != 0xD) { 4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 } else 4237 Inst.addOperand(MCOperand::CreateReg(0)); 4238 } 4239 4240 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4241 return MCDisassembler::Fail; 4242 Inst.addOperand(MCOperand::CreateImm(index)); 4243 4244 return S; 4245 } 4246 4247 4248 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4249 uint64_t Address, const void *Decoder) { 4250 DecodeStatus S = MCDisassembler::Success; 4251 4252 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4253 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4254 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4255 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4256 unsigned size = fieldFromInstruction(Insn, 10, 2); 4257 4258 unsigned align = 0; 4259 unsigned index = 0; 4260 unsigned inc = 1; 4261 switch (size) { 4262 default: 4263 return MCDisassembler::Fail; 4264 case 0: 4265 index = fieldFromInstruction(Insn, 5, 3); 4266 if (fieldFromInstruction(Insn, 4, 1)) 4267 align = 2; 4268 break; 4269 case 1: 4270 index = fieldFromInstruction(Insn, 6, 2); 4271 if (fieldFromInstruction(Insn, 4, 1)) 4272 align = 4; 4273 if (fieldFromInstruction(Insn, 5, 1)) 4274 inc = 2; 4275 break; 4276 case 2: 4277 if (fieldFromInstruction(Insn, 5, 1)) 4278 return MCDisassembler::Fail; // UNDEFINED 4279 index = fieldFromInstruction(Insn, 7, 1); 4280 if (fieldFromInstruction(Insn, 4, 1) != 0) 4281 align = 8; 4282 if (fieldFromInstruction(Insn, 6, 1)) 4283 inc = 2; 4284 break; 4285 } 4286 4287 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4288 return MCDisassembler::Fail; 4289 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4290 return MCDisassembler::Fail; 4291 if (Rm != 0xF) { // Writeback 4292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4293 return MCDisassembler::Fail; 4294 } 4295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4296 return MCDisassembler::Fail; 4297 Inst.addOperand(MCOperand::CreateImm(align)); 4298 if (Rm != 0xF) { 4299 if (Rm != 0xD) { 4300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4301 return MCDisassembler::Fail; 4302 } else 4303 Inst.addOperand(MCOperand::CreateReg(0)); 4304 } 4305 4306 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4307 return MCDisassembler::Fail; 4308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 Inst.addOperand(MCOperand::CreateImm(index)); 4311 4312 return S; 4313 } 4314 4315 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4316 uint64_t Address, const void *Decoder) { 4317 DecodeStatus S = MCDisassembler::Success; 4318 4319 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4320 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4321 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4322 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4323 unsigned size = fieldFromInstruction(Insn, 10, 2); 4324 4325 unsigned align = 0; 4326 unsigned index = 0; 4327 unsigned inc = 1; 4328 switch (size) { 4329 default: 4330 return MCDisassembler::Fail; 4331 case 0: 4332 index = fieldFromInstruction(Insn, 5, 3); 4333 if (fieldFromInstruction(Insn, 4, 1)) 4334 align = 2; 4335 break; 4336 case 1: 4337 index = fieldFromInstruction(Insn, 6, 2); 4338 if (fieldFromInstruction(Insn, 4, 1)) 4339 align = 4; 4340 if (fieldFromInstruction(Insn, 5, 1)) 4341 inc = 2; 4342 break; 4343 case 2: 4344 if (fieldFromInstruction(Insn, 5, 1)) 4345 return MCDisassembler::Fail; // UNDEFINED 4346 index = fieldFromInstruction(Insn, 7, 1); 4347 if (fieldFromInstruction(Insn, 4, 1) != 0) 4348 align = 8; 4349 if (fieldFromInstruction(Insn, 6, 1)) 4350 inc = 2; 4351 break; 4352 } 4353 4354 if (Rm != 0xF) { // Writeback 4355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4356 return MCDisassembler::Fail; 4357 } 4358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4359 return MCDisassembler::Fail; 4360 Inst.addOperand(MCOperand::CreateImm(align)); 4361 if (Rm != 0xF) { 4362 if (Rm != 0xD) { 4363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4364 return MCDisassembler::Fail; 4365 } else 4366 Inst.addOperand(MCOperand::CreateReg(0)); 4367 } 4368 4369 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4370 return MCDisassembler::Fail; 4371 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 Inst.addOperand(MCOperand::CreateImm(index)); 4374 4375 return S; 4376 } 4377 4378 4379 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4380 uint64_t Address, const void *Decoder) { 4381 DecodeStatus S = MCDisassembler::Success; 4382 4383 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4384 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4385 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4386 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4387 unsigned size = fieldFromInstruction(Insn, 10, 2); 4388 4389 unsigned align = 0; 4390 unsigned index = 0; 4391 unsigned inc = 1; 4392 switch (size) { 4393 default: 4394 return MCDisassembler::Fail; 4395 case 0: 4396 if (fieldFromInstruction(Insn, 4, 1)) 4397 return MCDisassembler::Fail; // UNDEFINED 4398 index = fieldFromInstruction(Insn, 5, 3); 4399 break; 4400 case 1: 4401 if (fieldFromInstruction(Insn, 4, 1)) 4402 return MCDisassembler::Fail; // UNDEFINED 4403 index = fieldFromInstruction(Insn, 6, 2); 4404 if (fieldFromInstruction(Insn, 5, 1)) 4405 inc = 2; 4406 break; 4407 case 2: 4408 if (fieldFromInstruction(Insn, 4, 2)) 4409 return MCDisassembler::Fail; // UNDEFINED 4410 index = fieldFromInstruction(Insn, 7, 1); 4411 if (fieldFromInstruction(Insn, 6, 1)) 4412 inc = 2; 4413 break; 4414 } 4415 4416 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4417 return MCDisassembler::Fail; 4418 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4419 return MCDisassembler::Fail; 4420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4421 return MCDisassembler::Fail; 4422 4423 if (Rm != 0xF) { // Writeback 4424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4425 return MCDisassembler::Fail; 4426 } 4427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4428 return MCDisassembler::Fail; 4429 Inst.addOperand(MCOperand::CreateImm(align)); 4430 if (Rm != 0xF) { 4431 if (Rm != 0xD) { 4432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4433 return MCDisassembler::Fail; 4434 } else 4435 Inst.addOperand(MCOperand::CreateReg(0)); 4436 } 4437 4438 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4439 return MCDisassembler::Fail; 4440 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4441 return MCDisassembler::Fail; 4442 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4443 return MCDisassembler::Fail; 4444 Inst.addOperand(MCOperand::CreateImm(index)); 4445 4446 return S; 4447 } 4448 4449 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4450 uint64_t Address, const void *Decoder) { 4451 DecodeStatus S = MCDisassembler::Success; 4452 4453 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4454 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4455 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4456 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4457 unsigned size = fieldFromInstruction(Insn, 10, 2); 4458 4459 unsigned align = 0; 4460 unsigned index = 0; 4461 unsigned inc = 1; 4462 switch (size) { 4463 default: 4464 return MCDisassembler::Fail; 4465 case 0: 4466 if (fieldFromInstruction(Insn, 4, 1)) 4467 return MCDisassembler::Fail; // UNDEFINED 4468 index = fieldFromInstruction(Insn, 5, 3); 4469 break; 4470 case 1: 4471 if (fieldFromInstruction(Insn, 4, 1)) 4472 return MCDisassembler::Fail; // UNDEFINED 4473 index = fieldFromInstruction(Insn, 6, 2); 4474 if (fieldFromInstruction(Insn, 5, 1)) 4475 inc = 2; 4476 break; 4477 case 2: 4478 if (fieldFromInstruction(Insn, 4, 2)) 4479 return MCDisassembler::Fail; // UNDEFINED 4480 index = fieldFromInstruction(Insn, 7, 1); 4481 if (fieldFromInstruction(Insn, 6, 1)) 4482 inc = 2; 4483 break; 4484 } 4485 4486 if (Rm != 0xF) { // Writeback 4487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4488 return MCDisassembler::Fail; 4489 } 4490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4491 return MCDisassembler::Fail; 4492 Inst.addOperand(MCOperand::CreateImm(align)); 4493 if (Rm != 0xF) { 4494 if (Rm != 0xD) { 4495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4496 return MCDisassembler::Fail; 4497 } else 4498 Inst.addOperand(MCOperand::CreateReg(0)); 4499 } 4500 4501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4502 return MCDisassembler::Fail; 4503 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4504 return MCDisassembler::Fail; 4505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4506 return MCDisassembler::Fail; 4507 Inst.addOperand(MCOperand::CreateImm(index)); 4508 4509 return S; 4510 } 4511 4512 4513 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4514 uint64_t Address, const void *Decoder) { 4515 DecodeStatus S = MCDisassembler::Success; 4516 4517 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4518 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4519 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4520 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4521 unsigned size = fieldFromInstruction(Insn, 10, 2); 4522 4523 unsigned align = 0; 4524 unsigned index = 0; 4525 unsigned inc = 1; 4526 switch (size) { 4527 default: 4528 return MCDisassembler::Fail; 4529 case 0: 4530 if (fieldFromInstruction(Insn, 4, 1)) 4531 align = 4; 4532 index = fieldFromInstruction(Insn, 5, 3); 4533 break; 4534 case 1: 4535 if (fieldFromInstruction(Insn, 4, 1)) 4536 align = 8; 4537 index = fieldFromInstruction(Insn, 6, 2); 4538 if (fieldFromInstruction(Insn, 5, 1)) 4539 inc = 2; 4540 break; 4541 case 2: 4542 switch (fieldFromInstruction(Insn, 4, 2)) { 4543 case 0: 4544 align = 0; break; 4545 case 3: 4546 return MCDisassembler::Fail; 4547 default: 4548 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4549 } 4550 4551 index = fieldFromInstruction(Insn, 7, 1); 4552 if (fieldFromInstruction(Insn, 6, 1)) 4553 inc = 2; 4554 break; 4555 } 4556 4557 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4558 return MCDisassembler::Fail; 4559 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4560 return MCDisassembler::Fail; 4561 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4562 return MCDisassembler::Fail; 4563 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4564 return MCDisassembler::Fail; 4565 4566 if (Rm != 0xF) { // Writeback 4567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4568 return MCDisassembler::Fail; 4569 } 4570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4571 return MCDisassembler::Fail; 4572 Inst.addOperand(MCOperand::CreateImm(align)); 4573 if (Rm != 0xF) { 4574 if (Rm != 0xD) { 4575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4576 return MCDisassembler::Fail; 4577 } else 4578 Inst.addOperand(MCOperand::CreateReg(0)); 4579 } 4580 4581 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4582 return MCDisassembler::Fail; 4583 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4584 return MCDisassembler::Fail; 4585 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4586 return MCDisassembler::Fail; 4587 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4588 return MCDisassembler::Fail; 4589 Inst.addOperand(MCOperand::CreateImm(index)); 4590 4591 return S; 4592 } 4593 4594 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4595 uint64_t Address, const void *Decoder) { 4596 DecodeStatus S = MCDisassembler::Success; 4597 4598 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4599 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4600 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4601 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4602 unsigned size = fieldFromInstruction(Insn, 10, 2); 4603 4604 unsigned align = 0; 4605 unsigned index = 0; 4606 unsigned inc = 1; 4607 switch (size) { 4608 default: 4609 return MCDisassembler::Fail; 4610 case 0: 4611 if (fieldFromInstruction(Insn, 4, 1)) 4612 align = 4; 4613 index = fieldFromInstruction(Insn, 5, 3); 4614 break; 4615 case 1: 4616 if (fieldFromInstruction(Insn, 4, 1)) 4617 align = 8; 4618 index = fieldFromInstruction(Insn, 6, 2); 4619 if (fieldFromInstruction(Insn, 5, 1)) 4620 inc = 2; 4621 break; 4622 case 2: 4623 switch (fieldFromInstruction(Insn, 4, 2)) { 4624 case 0: 4625 align = 0; break; 4626 case 3: 4627 return MCDisassembler::Fail; 4628 default: 4629 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4630 } 4631 4632 index = fieldFromInstruction(Insn, 7, 1); 4633 if (fieldFromInstruction(Insn, 6, 1)) 4634 inc = 2; 4635 break; 4636 } 4637 4638 if (Rm != 0xF) { // Writeback 4639 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4640 return MCDisassembler::Fail; 4641 } 4642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4643 return MCDisassembler::Fail; 4644 Inst.addOperand(MCOperand::CreateImm(align)); 4645 if (Rm != 0xF) { 4646 if (Rm != 0xD) { 4647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4648 return MCDisassembler::Fail; 4649 } else 4650 Inst.addOperand(MCOperand::CreateReg(0)); 4651 } 4652 4653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4654 return MCDisassembler::Fail; 4655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4656 return MCDisassembler::Fail; 4657 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4658 return MCDisassembler::Fail; 4659 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4660 return MCDisassembler::Fail; 4661 Inst.addOperand(MCOperand::CreateImm(index)); 4662 4663 return S; 4664 } 4665 4666 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4667 uint64_t Address, const void *Decoder) { 4668 DecodeStatus S = MCDisassembler::Success; 4669 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4670 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4671 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4672 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4673 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4674 4675 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4676 S = MCDisassembler::SoftFail; 4677 4678 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4683 return MCDisassembler::Fail; 4684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4685 return MCDisassembler::Fail; 4686 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4687 return MCDisassembler::Fail; 4688 4689 return S; 4690 } 4691 4692 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4693 uint64_t Address, const void *Decoder) { 4694 DecodeStatus S = MCDisassembler::Success; 4695 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4696 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4697 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4698 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4699 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4700 4701 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4702 S = MCDisassembler::SoftFail; 4703 4704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4705 return MCDisassembler::Fail; 4706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4707 return MCDisassembler::Fail; 4708 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4709 return MCDisassembler::Fail; 4710 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4711 return MCDisassembler::Fail; 4712 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4713 return MCDisassembler::Fail; 4714 4715 return S; 4716 } 4717 4718 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4719 uint64_t Address, const void *Decoder) { 4720 DecodeStatus S = MCDisassembler::Success; 4721 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4722 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4723 4724 if (pred == 0xF) { 4725 pred = 0xE; 4726 S = MCDisassembler::SoftFail; 4727 } 4728 4729 if (mask == 0x0) 4730 return MCDisassembler::Fail; 4731 4732 Inst.addOperand(MCOperand::CreateImm(pred)); 4733 Inst.addOperand(MCOperand::CreateImm(mask)); 4734 return S; 4735 } 4736 4737 static DecodeStatus 4738 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4739 uint64_t Address, const void *Decoder) { 4740 DecodeStatus S = MCDisassembler::Success; 4741 4742 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4743 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4744 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4745 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4746 unsigned W = fieldFromInstruction(Insn, 21, 1); 4747 unsigned U = fieldFromInstruction(Insn, 23, 1); 4748 unsigned P = fieldFromInstruction(Insn, 24, 1); 4749 bool writeback = (W == 1) | (P == 0); 4750 4751 addr |= (U << 8) | (Rn << 9); 4752 4753 if (writeback && (Rn == Rt || Rn == Rt2)) 4754 Check(S, MCDisassembler::SoftFail); 4755 if (Rt == Rt2) 4756 Check(S, MCDisassembler::SoftFail); 4757 4758 // Rt 4759 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4760 return MCDisassembler::Fail; 4761 // Rt2 4762 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4763 return MCDisassembler::Fail; 4764 // Writeback operand 4765 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4766 return MCDisassembler::Fail; 4767 // addr 4768 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4769 return MCDisassembler::Fail; 4770 4771 return S; 4772 } 4773 4774 static DecodeStatus 4775 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4776 uint64_t Address, const void *Decoder) { 4777 DecodeStatus S = MCDisassembler::Success; 4778 4779 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4780 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4781 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4782 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4783 unsigned W = fieldFromInstruction(Insn, 21, 1); 4784 unsigned U = fieldFromInstruction(Insn, 23, 1); 4785 unsigned P = fieldFromInstruction(Insn, 24, 1); 4786 bool writeback = (W == 1) | (P == 0); 4787 4788 addr |= (U << 8) | (Rn << 9); 4789 4790 if (writeback && (Rn == Rt || Rn == Rt2)) 4791 Check(S, MCDisassembler::SoftFail); 4792 4793 // Writeback operand 4794 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4795 return MCDisassembler::Fail; 4796 // Rt 4797 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4798 return MCDisassembler::Fail; 4799 // Rt2 4800 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4801 return MCDisassembler::Fail; 4802 // addr 4803 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4804 return MCDisassembler::Fail; 4805 4806 return S; 4807 } 4808 4809 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4810 uint64_t Address, const void *Decoder) { 4811 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4812 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4813 if (sign1 != sign2) return MCDisassembler::Fail; 4814 4815 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4816 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4817 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4818 Val |= sign1 << 12; 4819 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4820 4821 return MCDisassembler::Success; 4822 } 4823 4824 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4825 uint64_t Address, 4826 const void *Decoder) { 4827 DecodeStatus S = MCDisassembler::Success; 4828 4829 // Shift of "asr #32" is not allowed in Thumb2 mode. 4830 if (Val == 0x20) S = MCDisassembler::SoftFail; 4831 Inst.addOperand(MCOperand::CreateImm(Val)); 4832 return S; 4833 } 4834 4835 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4836 uint64_t Address, const void *Decoder) { 4837 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4838 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4840 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4841 4842 if (pred == 0xF) 4843 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4844 4845 DecodeStatus S = MCDisassembler::Success; 4846 4847 if (Rt == Rn || Rn == Rt2) 4848 S = MCDisassembler::SoftFail; 4849 4850 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4851 return MCDisassembler::Fail; 4852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4853 return MCDisassembler::Fail; 4854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4855 return MCDisassembler::Fail; 4856 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4857 return MCDisassembler::Fail; 4858 4859 return S; 4860 } 4861 4862 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4863 uint64_t Address, const void *Decoder) { 4864 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4865 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4866 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4867 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4868 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4869 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4870 unsigned op = fieldFromInstruction(Insn, 5, 1); 4871 4872 DecodeStatus S = MCDisassembler::Success; 4873 4874 // VMOVv2f32 is ambiguous with these decodings. 4875 if (!(imm & 0x38) && cmode == 0xF) { 4876 if (op == 1) return MCDisassembler::Fail; 4877 Inst.setOpcode(ARM::VMOVv2f32); 4878 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4879 } 4880 4881 if (!(imm & 0x20)) return MCDisassembler::Fail; 4882 4883 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4884 return MCDisassembler::Fail; 4885 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4886 return MCDisassembler::Fail; 4887 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4888 4889 return S; 4890 } 4891 4892 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4893 uint64_t Address, const void *Decoder) { 4894 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4895 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4896 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4897 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4898 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4899 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4900 unsigned op = fieldFromInstruction(Insn, 5, 1); 4901 4902 DecodeStatus S = MCDisassembler::Success; 4903 4904 // VMOVv4f32 is ambiguous with these decodings. 4905 if (!(imm & 0x38) && cmode == 0xF) { 4906 if (op == 1) return MCDisassembler::Fail; 4907 Inst.setOpcode(ARM::VMOVv4f32); 4908 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4909 } 4910 4911 if (!(imm & 0x20)) return MCDisassembler::Fail; 4912 4913 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4914 return MCDisassembler::Fail; 4915 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4916 return MCDisassembler::Fail; 4917 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4918 4919 return S; 4920 } 4921 4922 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4923 uint64_t Address, const void *Decoder) { 4924 DecodeStatus S = MCDisassembler::Success; 4925 4926 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4927 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4928 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4929 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4930 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4931 4932 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4933 S = MCDisassembler::SoftFail; 4934 4935 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4936 return MCDisassembler::Fail; 4937 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4938 return MCDisassembler::Fail; 4939 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4942 return MCDisassembler::Fail; 4943 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4944 return MCDisassembler::Fail; 4945 4946 return S; 4947 } 4948 4949 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4950 uint64_t Address, const void *Decoder) { 4951 4952 DecodeStatus S = MCDisassembler::Success; 4953 4954 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4955 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4956 unsigned cop = fieldFromInstruction(Val, 8, 4); 4957 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4958 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4959 4960 if ((cop & ~0x1) == 0xa) 4961 return MCDisassembler::Fail; 4962 4963 if (Rt == Rt2) 4964 S = MCDisassembler::SoftFail; 4965 4966 Inst.addOperand(MCOperand::CreateImm(cop)); 4967 Inst.addOperand(MCOperand::CreateImm(opc1)); 4968 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4969 return MCDisassembler::Fail; 4970 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4971 return MCDisassembler::Fail; 4972 Inst.addOperand(MCOperand::CreateImm(CRm)); 4973 4974 return S; 4975 } 4976 4977