1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 143 private: 144 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 145 ArrayRef<uint8_t> Bytes, uint64_t Address, 146 raw_ostream &VStream, 147 raw_ostream &CStream) const; 148 149 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 150 ArrayRef<uint8_t> Bytes, uint64_t Address, 151 raw_ostream &VStream, 152 raw_ostream &CStream) const; 153 154 mutable ITStatus ITBlock; 155 mutable VPTStatus VPTBlock; 156 157 DecodeStatus AddThumbPredicate(MCInst&) const; 158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 159 }; 160 161 } // end anonymous namespace 162 163 static bool Check(DecodeStatus &Out, DecodeStatus In) { 164 switch (In) { 165 case MCDisassembler::Success: 166 // Out stays the same. 167 return true; 168 case MCDisassembler::SoftFail: 169 Out = In; 170 return true; 171 case MCDisassembler::Fail: 172 Out = In; 173 return false; 174 } 175 llvm_unreachable("Invalid DecodeStatus!"); 176 } 177 178 // Forward declare these because the autogenerated code will reference them. 179 // Definitions are further down. 180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 216 unsigned RegNo, 217 uint64_t Address, 218 const void *Decoder); 219 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 226 unsigned RegNo, uint64_t Address, 227 const void *Decoder); 228 229 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 240 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 257 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 258 unsigned Insn, 259 uint64_t Adddress, 260 const void *Decoder); 261 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 378 unsigned Val, 379 uint64_t Address, 380 const void *Decoder); 381 382 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 403 uint64_t Address, const void* Decoder); 404 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 405 uint64_t Address, const void* Decoder); 406 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 407 uint64_t Address, const void* Decoder); 408 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 409 uint64_t Address, const void* Decoder); 410 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 417 uint64_t Address, 418 const void *Decoder); 419 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 420 uint64_t Address, const void *Decoder); 421 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 422 uint64_t Address, const void *Decoder); 423 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 424 uint64_t Address, const void *Decoder); 425 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 426 uint64_t Address, const void *Decoder); 427 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 428 uint64_t Address, const void *Decoder); 429 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 430 uint64_t Address, const void *Decoder); 431 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 432 uint64_t Address, const void *Decoder); 433 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 434 uint64_t Address, const void *Decoder); 435 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 436 uint64_t Address, const void *Decoder); 437 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 438 uint64_t Address, const void *Decoder); 439 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 444 uint64_t Address, const void *Decoder); 445 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 446 uint64_t Address, const void *Decoder); 447 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 448 uint64_t Address, const void *Decoder); 449 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 450 uint64_t Address, const void *Decoder); 451 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 452 uint64_t Address, const void *Decoder); 453 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 454 uint64_t Address, const void *Decoder); 455 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 456 uint64_t Address, const void *Decoder); 457 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 458 uint64_t Address, const void *Decoder); 459 460 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 461 uint64_t Address, const void *Decoder); 462 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 465 uint64_t Address, const void *Decoder); 466 467 template <bool isSigned, bool isNeg, int size> 468 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 471 uint64_t Address, 472 const void *Decoder); 473 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 474 uint64_t Address, 475 const void *Decoder); 476 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 477 const void *Decoder); 478 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 479 uint64_t Address, 480 const void *Decoder); 481 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 482 const void *Decoder); 483 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 484 uint64_t Address, const void *Decoder); 485 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 486 uint64_t Address, const void *Decoder); 487 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 488 uint64_t Address, 489 const void *Decoder); 490 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 491 uint64_t Address, 492 const void *Decoder); 493 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 494 uint64_t Address, 495 const void *Decoder); 496 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 497 unsigned Val, 498 uint64_t Address, 499 const void *Decoder); 500 template<bool Writeback> 501 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 502 uint64_t Address, 503 const void *Decoder); 504 template <int shift> 505 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 506 uint64_t Address, 507 const void *Decoder); 508 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 509 uint64_t Address, 510 const void *Decoder); 511 #include "ARMGenDisassemblerTables.inc" 512 513 static MCDisassembler *createARMDisassembler(const Target &T, 514 const MCSubtargetInfo &STI, 515 MCContext &Ctx) { 516 return new ARMDisassembler(STI, Ctx); 517 } 518 519 // Post-decoding checks 520 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 521 uint64_t Address, raw_ostream &OS, 522 raw_ostream &CS, 523 uint32_t Insn, 524 DecodeStatus Result) { 525 switch (MI.getOpcode()) { 526 case ARM::HVC: { 527 // HVC is undefined if condition = 0xf otherwise upredictable 528 // if condition != 0xe 529 uint32_t Cond = (Insn >> 28) & 0xF; 530 if (Cond == 0xF) 531 return MCDisassembler::Fail; 532 if (Cond != 0xE) 533 return MCDisassembler::SoftFail; 534 return Result; 535 } 536 case ARM::t2ADDri: 537 case ARM::t2ADDri12: 538 case ARM::t2ADDrr: 539 case ARM::t2ADDrs: 540 case ARM::t2SUBri: 541 case ARM::t2SUBri12: 542 case ARM::t2SUBrr: 543 case ARM::t2SUBrs: 544 if (MI.getOperand(0).getReg() == ARM::SP && 545 MI.getOperand(1).getReg() != ARM::SP) 546 return MCDisassembler::SoftFail; 547 return Result; 548 default: return Result; 549 } 550 } 551 552 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 553 ArrayRef<uint8_t> Bytes, 554 uint64_t Address, raw_ostream &OS, 555 raw_ostream &CS) const { 556 if (STI.getFeatureBits()[ARM::ModeThumb]) 557 return getThumbInstruction(MI, Size, Bytes, Address, OS, CS); 558 return getARMInstruction(MI, Size, Bytes, Address, OS, CS); 559 } 560 561 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 562 ArrayRef<uint8_t> Bytes, 563 uint64_t Address, 564 raw_ostream &OS, 565 raw_ostream &CS) const { 566 CommentStream = &CS; 567 568 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 569 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 570 "mode!"); 571 572 // We want to read exactly 4 bytes of data. 573 if (Bytes.size() < 4) { 574 Size = 0; 575 return MCDisassembler::Fail; 576 } 577 578 // Encoded as a small-endian 32-bit word in the stream. 579 uint32_t Insn = 580 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 581 582 // Calling the auto-generated decoder function. 583 DecodeStatus Result = 584 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 585 if (Result != MCDisassembler::Fail) { 586 Size = 4; 587 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 588 } 589 590 struct DecodeTable { 591 const uint8_t *P; 592 bool DecodePred; 593 }; 594 595 const DecodeTable Tables[] = { 596 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 597 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 598 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 599 {DecoderTablev8Crypto32, false}, 600 }; 601 602 for (auto Table : Tables) { 603 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 604 if (Result != MCDisassembler::Fail) { 605 Size = 4; 606 // Add a fake predicate operand, because we share these instruction 607 // definitions with Thumb2 where these instructions are predicable. 608 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 609 return MCDisassembler::Fail; 610 return Result; 611 } 612 } 613 614 Result = 615 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 616 if (Result != MCDisassembler::Fail) { 617 Size = 4; 618 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 619 } 620 621 Size = 4; 622 return MCDisassembler::Fail; 623 } 624 625 namespace llvm { 626 627 extern const MCInstrDesc ARMInsts[]; 628 629 } // end namespace llvm 630 631 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 632 /// immediate Value in the MCInst. The immediate Value has had any PC 633 /// adjustment made by the caller. If the instruction is a branch instruction 634 /// then isBranch is true, else false. If the getOpInfo() function was set as 635 /// part of the setupForSymbolicDisassembly() call then that function is called 636 /// to get any symbolic information at the Address for this instruction. If 637 /// that returns non-zero then the symbolic information it returns is used to 638 /// create an MCExpr and that is added as an operand to the MCInst. If 639 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 640 /// Value is done and if a symbol is found an MCExpr is created with that, else 641 /// an MCExpr with Value is created. This function returns true if it adds an 642 /// operand to the MCInst and false otherwise. 643 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 644 bool isBranch, uint64_t InstSize, 645 MCInst &MI, const void *Decoder) { 646 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 647 // FIXME: Does it make sense for value to be negative? 648 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 649 /* Offset */ 0, InstSize); 650 } 651 652 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 653 /// referenced by a load instruction with the base register that is the Pc. 654 /// These can often be values in a literal pool near the Address of the 655 /// instruction. The Address of the instruction and its immediate Value are 656 /// used as a possible literal pool entry. The SymbolLookUp call back will 657 /// return the name of a symbol referenced by the literal pool's entry if 658 /// the referenced address is that of a symbol. Or it will return a pointer to 659 /// a literal 'C' string if the referenced address of the literal pool's entry 660 /// is an address into a section with 'C' string literals. 661 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 662 const void *Decoder) { 663 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 664 Dis->tryAddingPcLoadReferenceComment(Value, Address); 665 } 666 667 // Thumb1 instructions don't have explicit S bits. Rather, they 668 // implicitly set CPSR. Since it's not represented in the encoding, the 669 // auto-generated decoder won't inject the CPSR operand. We need to fix 670 // that as a post-pass. 671 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 672 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 673 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 674 MCInst::iterator I = MI.begin(); 675 for (unsigned i = 0; i < NumOps; ++i, ++I) { 676 if (I == MI.end()) break; 677 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 678 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 679 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 680 return; 681 } 682 } 683 684 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 685 } 686 687 static bool isVectorPredicable(unsigned Opcode) { 688 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 689 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 690 for (unsigned i = 0; i < NumOps; ++i) { 691 if (ARM::isVpred(OpInfo[i].OperandType)) 692 return true; 693 } 694 return false; 695 } 696 697 // Most Thumb instructions don't have explicit predicates in the 698 // encoding, but rather get their predicates from IT context. We need 699 // to fix up the predicate operands using this context information as a 700 // post-pass. 701 MCDisassembler::DecodeStatus 702 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 703 MCDisassembler::DecodeStatus S = Success; 704 705 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 706 707 // A few instructions actually have predicates encoded in them. Don't 708 // try to overwrite it if we're seeing one of those. 709 switch (MI.getOpcode()) { 710 case ARM::tBcc: 711 case ARM::t2Bcc: 712 case ARM::tCBZ: 713 case ARM::tCBNZ: 714 case ARM::tCPS: 715 case ARM::t2CPS3p: 716 case ARM::t2CPS2p: 717 case ARM::t2CPS1p: 718 case ARM::t2CSEL: 719 case ARM::t2CSINC: 720 case ARM::t2CSINV: 721 case ARM::t2CSNEG: 722 case ARM::tMOVSr: 723 case ARM::tSETEND: 724 // Some instructions (mostly conditional branches) are not 725 // allowed in IT blocks. 726 if (ITBlock.instrInITBlock()) 727 S = SoftFail; 728 else 729 return Success; 730 break; 731 case ARM::t2HINT: 732 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 733 S = SoftFail; 734 break; 735 case ARM::tB: 736 case ARM::t2B: 737 case ARM::t2TBB: 738 case ARM::t2TBH: 739 // Some instructions (mostly unconditional branches) can 740 // only appears at the end of, or outside of, an IT. 741 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 742 S = SoftFail; 743 break; 744 default: 745 break; 746 } 747 748 // Warn on non-VPT predicable instruction in a VPT block and a VPT 749 // predicable instruction in an IT block 750 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 751 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 752 S = SoftFail; 753 754 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 755 // assume a predicate of AL. 756 unsigned CC = ARMCC::AL; 757 unsigned VCC = ARMVCC::None; 758 if (ITBlock.instrInITBlock()) { 759 CC = ITBlock.getITCC(); 760 ITBlock.advanceITState(); 761 } else if (VPTBlock.instrInVPTBlock()) { 762 VCC = VPTBlock.getVPTPred(); 763 VPTBlock.advanceVPTState(); 764 } 765 766 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 767 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 768 769 MCInst::iterator CCI = MI.begin(); 770 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 771 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 772 } 773 774 if (ARMInsts[MI.getOpcode()].isPredicable()) { 775 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 776 ++CCI; 777 if (CC == ARMCC::AL) 778 MI.insert(CCI, MCOperand::createReg(0)); 779 else 780 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 781 } else if (CC != ARMCC::AL) { 782 Check(S, SoftFail); 783 } 784 785 MCInst::iterator VCCI = MI.begin(); 786 unsigned VCCPos; 787 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 788 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 789 } 790 791 if (isVectorPredicable(MI.getOpcode())) { 792 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 793 ++VCCI; 794 if (VCC == ARMVCC::None) 795 MI.insert(VCCI, MCOperand::createReg(0)); 796 else 797 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 798 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 799 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 800 VCCPos + 2, MCOI::TIED_TO); 801 assert(TiedOp >= 0 && 802 "Inactive register in vpred_r is not tied to an output!"); 803 MI.insert(VCCI, MI.getOperand(TiedOp)); 804 } 805 } else if (VCC != ARMVCC::None) { 806 Check(S, SoftFail); 807 } 808 809 return S; 810 } 811 812 // Thumb VFP instructions are a special case. Because we share their 813 // encodings between ARM and Thumb modes, and they are predicable in ARM 814 // mode, the auto-generated decoder will give them an (incorrect) 815 // predicate operand. We need to rewrite these operands based on the IT 816 // context as a post-pass. 817 void ARMDisassembler::UpdateThumbVFPPredicate( 818 DecodeStatus &S, MCInst &MI) const { 819 unsigned CC; 820 CC = ITBlock.getITCC(); 821 if (CC == 0xF) 822 CC = ARMCC::AL; 823 if (ITBlock.instrInITBlock()) 824 ITBlock.advanceITState(); 825 else if (VPTBlock.instrInVPTBlock()) { 826 CC = VPTBlock.getVPTPred(); 827 VPTBlock.advanceVPTState(); 828 } 829 830 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 831 MCInst::iterator I = MI.begin(); 832 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 833 for (unsigned i = 0; i < NumOps; ++i, ++I) { 834 if (OpInfo[i].isPredicate() ) { 835 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 836 Check(S, SoftFail); 837 I->setImm(CC); 838 ++I; 839 if (CC == ARMCC::AL) 840 I->setReg(0); 841 else 842 I->setReg(ARM::CPSR); 843 return; 844 } 845 } 846 } 847 848 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 849 ArrayRef<uint8_t> Bytes, 850 uint64_t Address, 851 raw_ostream &OS, 852 raw_ostream &CS) const { 853 CommentStream = &CS; 854 855 assert(STI.getFeatureBits()[ARM::ModeThumb] && 856 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 857 858 // We want to read exactly 2 bytes of data. 859 if (Bytes.size() < 2) { 860 Size = 0; 861 return MCDisassembler::Fail; 862 } 863 864 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 865 DecodeStatus Result = 866 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 867 if (Result != MCDisassembler::Fail) { 868 Size = 2; 869 Check(Result, AddThumbPredicate(MI)); 870 return Result; 871 } 872 873 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 874 STI); 875 if (Result) { 876 Size = 2; 877 bool InITBlock = ITBlock.instrInITBlock(); 878 Check(Result, AddThumbPredicate(MI)); 879 AddThumb1SBit(MI, InITBlock); 880 return Result; 881 } 882 883 Result = 884 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 885 if (Result != MCDisassembler::Fail) { 886 Size = 2; 887 888 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 889 // the Thumb predicate. 890 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 891 Result = MCDisassembler::SoftFail; 892 893 Check(Result, AddThumbPredicate(MI)); 894 895 // If we find an IT instruction, we need to parse its condition 896 // code and mask operands so that we can apply them correctly 897 // to the subsequent instructions. 898 if (MI.getOpcode() == ARM::t2IT) { 899 unsigned Firstcond = MI.getOperand(0).getImm(); 900 unsigned Mask = MI.getOperand(1).getImm(); 901 ITBlock.setITState(Firstcond, Mask); 902 903 // An IT instruction that would give a 'NV' predicate is unpredictable. 904 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 905 CS << "unpredictable IT predicate sequence"; 906 } 907 908 return Result; 909 } 910 911 // We want to read exactly 4 bytes of data. 912 if (Bytes.size() < 4) { 913 Size = 0; 914 return MCDisassembler::Fail; 915 } 916 917 uint32_t Insn32 = 918 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 919 920 Result = 921 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 922 if (Result != MCDisassembler::Fail) { 923 Size = 4; 924 925 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 926 // the VPT predicate. 927 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 928 Result = MCDisassembler::SoftFail; 929 930 Check(Result, AddThumbPredicate(MI)); 931 932 if (isVPTOpcode(MI.getOpcode())) { 933 unsigned Mask = MI.getOperand(0).getImm(); 934 VPTBlock.setVPTState(Mask); 935 } 936 937 return Result; 938 } 939 940 Result = 941 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 942 if (Result != MCDisassembler::Fail) { 943 Size = 4; 944 bool InITBlock = ITBlock.instrInITBlock(); 945 Check(Result, AddThumbPredicate(MI)); 946 AddThumb1SBit(MI, InITBlock); 947 return Result; 948 } 949 950 Result = 951 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 952 if (Result != MCDisassembler::Fail) { 953 Size = 4; 954 Check(Result, AddThumbPredicate(MI)); 955 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 956 } 957 958 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 959 Result = 960 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 961 if (Result != MCDisassembler::Fail) { 962 Size = 4; 963 UpdateThumbVFPPredicate(Result, MI); 964 return Result; 965 } 966 } 967 968 Result = 969 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 970 if (Result != MCDisassembler::Fail) { 971 Size = 4; 972 return Result; 973 } 974 975 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 976 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 977 STI); 978 if (Result != MCDisassembler::Fail) { 979 Size = 4; 980 Check(Result, AddThumbPredicate(MI)); 981 return Result; 982 } 983 } 984 985 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 986 uint32_t NEONLdStInsn = Insn32; 987 NEONLdStInsn &= 0xF0FFFFFF; 988 NEONLdStInsn |= 0x04000000; 989 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 990 Address, this, STI); 991 if (Result != MCDisassembler::Fail) { 992 Size = 4; 993 Check(Result, AddThumbPredicate(MI)); 994 return Result; 995 } 996 } 997 998 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 999 uint32_t NEONDataInsn = Insn32; 1000 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1001 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1002 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1003 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1004 Address, this, STI); 1005 if (Result != MCDisassembler::Fail) { 1006 Size = 4; 1007 Check(Result, AddThumbPredicate(MI)); 1008 return Result; 1009 } 1010 1011 uint32_t NEONCryptoInsn = Insn32; 1012 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1013 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1014 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1015 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1016 Address, this, STI); 1017 if (Result != MCDisassembler::Fail) { 1018 Size = 4; 1019 return Result; 1020 } 1021 1022 uint32_t NEONv8Insn = Insn32; 1023 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1024 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1025 this, STI); 1026 if (Result != MCDisassembler::Fail) { 1027 Size = 4; 1028 return Result; 1029 } 1030 } 1031 1032 Result = 1033 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1034 if (Result != MCDisassembler::Fail) { 1035 Size = 4; 1036 Check(Result, AddThumbPredicate(MI)); 1037 return Result; 1038 } 1039 1040 Size = 0; 1041 return MCDisassembler::Fail; 1042 } 1043 1044 extern "C" void LLVMInitializeARMDisassembler() { 1045 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1046 createARMDisassembler); 1047 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1048 createARMDisassembler); 1049 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1050 createARMDisassembler); 1051 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1052 createARMDisassembler); 1053 } 1054 1055 static const uint16_t GPRDecoderTable[] = { 1056 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1057 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1058 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1059 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1060 }; 1061 1062 static const uint16_t CLRMGPRDecoderTable[] = { 1063 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1064 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1065 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1066 ARM::R12, 0, ARM::LR, ARM::APSR 1067 }; 1068 1069 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1070 uint64_t Address, const void *Decoder) { 1071 if (RegNo > 15) 1072 return MCDisassembler::Fail; 1073 1074 unsigned Register = GPRDecoderTable[RegNo]; 1075 Inst.addOperand(MCOperand::createReg(Register)); 1076 return MCDisassembler::Success; 1077 } 1078 1079 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1080 uint64_t Address, 1081 const void *Decoder) { 1082 if (RegNo > 15) 1083 return MCDisassembler::Fail; 1084 1085 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1086 if (Register == 0) 1087 return MCDisassembler::Fail; 1088 1089 Inst.addOperand(MCOperand::createReg(Register)); 1090 return MCDisassembler::Success; 1091 } 1092 1093 static DecodeStatus 1094 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1095 uint64_t Address, const void *Decoder) { 1096 DecodeStatus S = MCDisassembler::Success; 1097 1098 if (RegNo == 15) 1099 S = MCDisassembler::SoftFail; 1100 1101 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1102 1103 return S; 1104 } 1105 1106 static DecodeStatus 1107 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1108 uint64_t Address, const void *Decoder) { 1109 DecodeStatus S = MCDisassembler::Success; 1110 1111 if (RegNo == 15) 1112 { 1113 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1114 return MCDisassembler::Success; 1115 } 1116 1117 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1118 return S; 1119 } 1120 1121 static DecodeStatus 1122 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1123 uint64_t Address, const void *Decoder) { 1124 DecodeStatus S = MCDisassembler::Success; 1125 1126 if (RegNo == 15) 1127 { 1128 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1129 return MCDisassembler::Success; 1130 } 1131 1132 if (RegNo == 13) 1133 S = MCDisassembler::SoftFail; 1134 1135 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1136 return S; 1137 } 1138 1139 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1140 uint64_t Address, const void *Decoder) { 1141 if (RegNo > 7) 1142 return MCDisassembler::Fail; 1143 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1144 } 1145 1146 static const uint16_t GPRPairDecoderTable[] = { 1147 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1148 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1149 }; 1150 1151 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1152 uint64_t Address, const void *Decoder) { 1153 DecodeStatus S = MCDisassembler::Success; 1154 1155 if (RegNo > 13) 1156 return MCDisassembler::Fail; 1157 1158 if ((RegNo & 1) || RegNo == 0xe) 1159 S = MCDisassembler::SoftFail; 1160 1161 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1162 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1163 return S; 1164 } 1165 1166 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1167 uint64_t Address, const void *Decoder) { 1168 unsigned Register = 0; 1169 switch (RegNo) { 1170 case 0: 1171 Register = ARM::R0; 1172 break; 1173 case 1: 1174 Register = ARM::R1; 1175 break; 1176 case 2: 1177 Register = ARM::R2; 1178 break; 1179 case 3: 1180 Register = ARM::R3; 1181 break; 1182 case 9: 1183 Register = ARM::R9; 1184 break; 1185 case 12: 1186 Register = ARM::R12; 1187 break; 1188 default: 1189 return MCDisassembler::Fail; 1190 } 1191 1192 Inst.addOperand(MCOperand::createReg(Register)); 1193 return MCDisassembler::Success; 1194 } 1195 1196 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1197 uint64_t Address, const void *Decoder) { 1198 DecodeStatus S = MCDisassembler::Success; 1199 1200 const FeatureBitset &featureBits = 1201 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1202 1203 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1204 S = MCDisassembler::SoftFail; 1205 1206 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1207 return S; 1208 } 1209 1210 static const uint16_t SPRDecoderTable[] = { 1211 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1212 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1213 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1214 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1215 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1216 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1217 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1218 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1219 }; 1220 1221 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1222 uint64_t Address, const void *Decoder) { 1223 if (RegNo > 31) 1224 return MCDisassembler::Fail; 1225 1226 unsigned Register = SPRDecoderTable[RegNo]; 1227 Inst.addOperand(MCOperand::createReg(Register)); 1228 return MCDisassembler::Success; 1229 } 1230 1231 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1232 uint64_t Address, const void *Decoder) { 1233 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1234 } 1235 1236 static const uint16_t DPRDecoderTable[] = { 1237 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1238 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1239 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1240 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1241 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1242 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1243 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1244 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1245 }; 1246 1247 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1248 uint64_t Address, const void *Decoder) { 1249 const FeatureBitset &featureBits = 1250 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1251 1252 bool hasD32 = featureBits[ARM::FeatureD32]; 1253 1254 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1255 return MCDisassembler::Fail; 1256 1257 unsigned Register = DPRDecoderTable[RegNo]; 1258 Inst.addOperand(MCOperand::createReg(Register)); 1259 return MCDisassembler::Success; 1260 } 1261 1262 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1263 uint64_t Address, const void *Decoder) { 1264 if (RegNo > 7) 1265 return MCDisassembler::Fail; 1266 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1267 } 1268 1269 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1270 uint64_t Address, const void *Decoder) { 1271 if (RegNo > 15) 1272 return MCDisassembler::Fail; 1273 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1274 } 1275 1276 static DecodeStatus 1277 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1278 uint64_t Address, const void *Decoder) { 1279 if (RegNo > 15) 1280 return MCDisassembler::Fail; 1281 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1282 } 1283 1284 static const uint16_t QPRDecoderTable[] = { 1285 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1286 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1287 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1288 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1289 }; 1290 1291 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1292 uint64_t Address, const void *Decoder) { 1293 if (RegNo > 31 || (RegNo & 1) != 0) 1294 return MCDisassembler::Fail; 1295 RegNo >>= 1; 1296 1297 unsigned Register = QPRDecoderTable[RegNo]; 1298 Inst.addOperand(MCOperand::createReg(Register)); 1299 return MCDisassembler::Success; 1300 } 1301 1302 static const uint16_t DPairDecoderTable[] = { 1303 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1304 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1305 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1306 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1307 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1308 ARM::Q15 1309 }; 1310 1311 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1312 uint64_t Address, const void *Decoder) { 1313 if (RegNo > 30) 1314 return MCDisassembler::Fail; 1315 1316 unsigned Register = DPairDecoderTable[RegNo]; 1317 Inst.addOperand(MCOperand::createReg(Register)); 1318 return MCDisassembler::Success; 1319 } 1320 1321 static const uint16_t DPairSpacedDecoderTable[] = { 1322 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1323 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1324 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1325 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1326 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1327 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1328 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1329 ARM::D28_D30, ARM::D29_D31 1330 }; 1331 1332 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1333 unsigned RegNo, 1334 uint64_t Address, 1335 const void *Decoder) { 1336 if (RegNo > 29) 1337 return MCDisassembler::Fail; 1338 1339 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1340 Inst.addOperand(MCOperand::createReg(Register)); 1341 return MCDisassembler::Success; 1342 } 1343 1344 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1345 uint64_t Address, const void *Decoder) { 1346 DecodeStatus S = MCDisassembler::Success; 1347 if (Val == 0xF) return MCDisassembler::Fail; 1348 // AL predicate is not allowed on Thumb1 branches. 1349 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1350 return MCDisassembler::Fail; 1351 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1352 Check(S, MCDisassembler::SoftFail); 1353 Inst.addOperand(MCOperand::createImm(Val)); 1354 if (Val == ARMCC::AL) { 1355 Inst.addOperand(MCOperand::createReg(0)); 1356 } else 1357 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1358 return S; 1359 } 1360 1361 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1362 uint64_t Address, const void *Decoder) { 1363 if (Val) 1364 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1365 else 1366 Inst.addOperand(MCOperand::createReg(0)); 1367 return MCDisassembler::Success; 1368 } 1369 1370 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1371 uint64_t Address, const void *Decoder) { 1372 DecodeStatus S = MCDisassembler::Success; 1373 1374 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1375 unsigned type = fieldFromInstruction(Val, 5, 2); 1376 unsigned imm = fieldFromInstruction(Val, 7, 5); 1377 1378 // Register-immediate 1379 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1380 return MCDisassembler::Fail; 1381 1382 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1383 switch (type) { 1384 case 0: 1385 Shift = ARM_AM::lsl; 1386 break; 1387 case 1: 1388 Shift = ARM_AM::lsr; 1389 break; 1390 case 2: 1391 Shift = ARM_AM::asr; 1392 break; 1393 case 3: 1394 Shift = ARM_AM::ror; 1395 break; 1396 } 1397 1398 if (Shift == ARM_AM::ror && imm == 0) 1399 Shift = ARM_AM::rrx; 1400 1401 unsigned Op = Shift | (imm << 3); 1402 Inst.addOperand(MCOperand::createImm(Op)); 1403 1404 return S; 1405 } 1406 1407 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1408 uint64_t Address, const void *Decoder) { 1409 DecodeStatus S = MCDisassembler::Success; 1410 1411 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1412 unsigned type = fieldFromInstruction(Val, 5, 2); 1413 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1414 1415 // Register-register 1416 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1417 return MCDisassembler::Fail; 1418 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1419 return MCDisassembler::Fail; 1420 1421 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1422 switch (type) { 1423 case 0: 1424 Shift = ARM_AM::lsl; 1425 break; 1426 case 1: 1427 Shift = ARM_AM::lsr; 1428 break; 1429 case 2: 1430 Shift = ARM_AM::asr; 1431 break; 1432 case 3: 1433 Shift = ARM_AM::ror; 1434 break; 1435 } 1436 1437 Inst.addOperand(MCOperand::createImm(Shift)); 1438 1439 return S; 1440 } 1441 1442 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1443 uint64_t Address, const void *Decoder) { 1444 DecodeStatus S = MCDisassembler::Success; 1445 1446 bool NeedDisjointWriteback = false; 1447 unsigned WritebackReg = 0; 1448 bool CLRM = false; 1449 switch (Inst.getOpcode()) { 1450 default: 1451 break; 1452 case ARM::LDMIA_UPD: 1453 case ARM::LDMDB_UPD: 1454 case ARM::LDMIB_UPD: 1455 case ARM::LDMDA_UPD: 1456 case ARM::t2LDMIA_UPD: 1457 case ARM::t2LDMDB_UPD: 1458 case ARM::t2STMIA_UPD: 1459 case ARM::t2STMDB_UPD: 1460 NeedDisjointWriteback = true; 1461 WritebackReg = Inst.getOperand(0).getReg(); 1462 break; 1463 case ARM::t2CLRM: 1464 CLRM = true; 1465 break; 1466 } 1467 1468 // Empty register lists are not allowed. 1469 if (Val == 0) return MCDisassembler::Fail; 1470 for (unsigned i = 0; i < 16; ++i) { 1471 if (Val & (1 << i)) { 1472 if (CLRM) { 1473 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1474 return MCDisassembler::Fail; 1475 } 1476 } else { 1477 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1478 return MCDisassembler::Fail; 1479 // Writeback not allowed if Rn is in the target list. 1480 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1481 Check(S, MCDisassembler::SoftFail); 1482 } 1483 } 1484 } 1485 1486 return S; 1487 } 1488 1489 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1490 uint64_t Address, const void *Decoder) { 1491 DecodeStatus S = MCDisassembler::Success; 1492 1493 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1494 unsigned regs = fieldFromInstruction(Val, 0, 8); 1495 1496 // In case of unpredictable encoding, tweak the operands. 1497 if (regs == 0 || (Vd + regs) > 32) { 1498 regs = Vd + regs > 32 ? 32 - Vd : regs; 1499 regs = std::max( 1u, regs); 1500 S = MCDisassembler::SoftFail; 1501 } 1502 1503 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1504 return MCDisassembler::Fail; 1505 for (unsigned i = 0; i < (regs - 1); ++i) { 1506 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1507 return MCDisassembler::Fail; 1508 } 1509 1510 return S; 1511 } 1512 1513 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1514 uint64_t Address, const void *Decoder) { 1515 DecodeStatus S = MCDisassembler::Success; 1516 1517 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1518 unsigned regs = fieldFromInstruction(Val, 1, 7); 1519 1520 // In case of unpredictable encoding, tweak the operands. 1521 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1522 regs = Vd + regs > 32 ? 32 - Vd : regs; 1523 regs = std::max( 1u, regs); 1524 regs = std::min(16u, regs); 1525 S = MCDisassembler::SoftFail; 1526 } 1527 1528 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1529 return MCDisassembler::Fail; 1530 for (unsigned i = 0; i < (regs - 1); ++i) { 1531 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1532 return MCDisassembler::Fail; 1533 } 1534 1535 return S; 1536 } 1537 1538 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1539 uint64_t Address, const void *Decoder) { 1540 // This operand encodes a mask of contiguous zeros between a specified MSB 1541 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1542 // the mask of all bits LSB-and-lower, and then xor them to create 1543 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1544 // create the final mask. 1545 unsigned msb = fieldFromInstruction(Val, 5, 5); 1546 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1547 1548 DecodeStatus S = MCDisassembler::Success; 1549 if (lsb > msb) { 1550 Check(S, MCDisassembler::SoftFail); 1551 // The check above will cause the warning for the "potentially undefined 1552 // instruction encoding" but we can't build a bad MCOperand value here 1553 // with a lsb > msb or else printing the MCInst will cause a crash. 1554 lsb = msb; 1555 } 1556 1557 uint32_t msb_mask = 0xFFFFFFFF; 1558 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1559 uint32_t lsb_mask = (1U << lsb) - 1; 1560 1561 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1562 return S; 1563 } 1564 1565 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1566 uint64_t Address, const void *Decoder) { 1567 DecodeStatus S = MCDisassembler::Success; 1568 1569 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1570 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1571 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1572 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1573 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1574 unsigned U = fieldFromInstruction(Insn, 23, 1); 1575 const FeatureBitset &featureBits = 1576 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1577 1578 switch (Inst.getOpcode()) { 1579 case ARM::LDC_OFFSET: 1580 case ARM::LDC_PRE: 1581 case ARM::LDC_POST: 1582 case ARM::LDC_OPTION: 1583 case ARM::LDCL_OFFSET: 1584 case ARM::LDCL_PRE: 1585 case ARM::LDCL_POST: 1586 case ARM::LDCL_OPTION: 1587 case ARM::STC_OFFSET: 1588 case ARM::STC_PRE: 1589 case ARM::STC_POST: 1590 case ARM::STC_OPTION: 1591 case ARM::STCL_OFFSET: 1592 case ARM::STCL_PRE: 1593 case ARM::STCL_POST: 1594 case ARM::STCL_OPTION: 1595 case ARM::t2LDC_OFFSET: 1596 case ARM::t2LDC_PRE: 1597 case ARM::t2LDC_POST: 1598 case ARM::t2LDC_OPTION: 1599 case ARM::t2LDCL_OFFSET: 1600 case ARM::t2LDCL_PRE: 1601 case ARM::t2LDCL_POST: 1602 case ARM::t2LDCL_OPTION: 1603 case ARM::t2STC_OFFSET: 1604 case ARM::t2STC_PRE: 1605 case ARM::t2STC_POST: 1606 case ARM::t2STC_OPTION: 1607 case ARM::t2STCL_OFFSET: 1608 case ARM::t2STCL_PRE: 1609 case ARM::t2STCL_POST: 1610 case ARM::t2STCL_OPTION: 1611 case ARM::t2LDC2_OFFSET: 1612 case ARM::t2LDC2L_OFFSET: 1613 case ARM::t2LDC2_PRE: 1614 case ARM::t2LDC2L_PRE: 1615 case ARM::t2STC2_OFFSET: 1616 case ARM::t2STC2L_OFFSET: 1617 case ARM::t2STC2_PRE: 1618 case ARM::t2STC2L_PRE: 1619 case ARM::LDC2_OFFSET: 1620 case ARM::LDC2L_OFFSET: 1621 case ARM::LDC2_PRE: 1622 case ARM::LDC2L_PRE: 1623 case ARM::STC2_OFFSET: 1624 case ARM::STC2L_OFFSET: 1625 case ARM::STC2_PRE: 1626 case ARM::STC2L_PRE: 1627 case ARM::t2LDC2_OPTION: 1628 case ARM::t2STC2_OPTION: 1629 case ARM::t2LDC2_POST: 1630 case ARM::t2LDC2L_POST: 1631 case ARM::t2STC2_POST: 1632 case ARM::t2STC2L_POST: 1633 case ARM::LDC2_POST: 1634 case ARM::LDC2L_POST: 1635 case ARM::STC2_POST: 1636 case ARM::STC2L_POST: 1637 if (coproc == 0xA || coproc == 0xB || 1638 (featureBits[ARM::HasV8_1MMainlineOps] && 1639 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1640 coproc == 0xE || coproc == 0xF))) 1641 return MCDisassembler::Fail; 1642 break; 1643 default: 1644 break; 1645 } 1646 1647 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1648 return MCDisassembler::Fail; 1649 1650 Inst.addOperand(MCOperand::createImm(coproc)); 1651 Inst.addOperand(MCOperand::createImm(CRd)); 1652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1653 return MCDisassembler::Fail; 1654 1655 switch (Inst.getOpcode()) { 1656 case ARM::t2LDC2_OFFSET: 1657 case ARM::t2LDC2L_OFFSET: 1658 case ARM::t2LDC2_PRE: 1659 case ARM::t2LDC2L_PRE: 1660 case ARM::t2STC2_OFFSET: 1661 case ARM::t2STC2L_OFFSET: 1662 case ARM::t2STC2_PRE: 1663 case ARM::t2STC2L_PRE: 1664 case ARM::LDC2_OFFSET: 1665 case ARM::LDC2L_OFFSET: 1666 case ARM::LDC2_PRE: 1667 case ARM::LDC2L_PRE: 1668 case ARM::STC2_OFFSET: 1669 case ARM::STC2L_OFFSET: 1670 case ARM::STC2_PRE: 1671 case ARM::STC2L_PRE: 1672 case ARM::t2LDC_OFFSET: 1673 case ARM::t2LDCL_OFFSET: 1674 case ARM::t2LDC_PRE: 1675 case ARM::t2LDCL_PRE: 1676 case ARM::t2STC_OFFSET: 1677 case ARM::t2STCL_OFFSET: 1678 case ARM::t2STC_PRE: 1679 case ARM::t2STCL_PRE: 1680 case ARM::LDC_OFFSET: 1681 case ARM::LDCL_OFFSET: 1682 case ARM::LDC_PRE: 1683 case ARM::LDCL_PRE: 1684 case ARM::STC_OFFSET: 1685 case ARM::STCL_OFFSET: 1686 case ARM::STC_PRE: 1687 case ARM::STCL_PRE: 1688 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1689 Inst.addOperand(MCOperand::createImm(imm)); 1690 break; 1691 case ARM::t2LDC2_POST: 1692 case ARM::t2LDC2L_POST: 1693 case ARM::t2STC2_POST: 1694 case ARM::t2STC2L_POST: 1695 case ARM::LDC2_POST: 1696 case ARM::LDC2L_POST: 1697 case ARM::STC2_POST: 1698 case ARM::STC2L_POST: 1699 case ARM::t2LDC_POST: 1700 case ARM::t2LDCL_POST: 1701 case ARM::t2STC_POST: 1702 case ARM::t2STCL_POST: 1703 case ARM::LDC_POST: 1704 case ARM::LDCL_POST: 1705 case ARM::STC_POST: 1706 case ARM::STCL_POST: 1707 imm |= U << 8; 1708 LLVM_FALLTHROUGH; 1709 default: 1710 // The 'option' variant doesn't encode 'U' in the immediate since 1711 // the immediate is unsigned [0,255]. 1712 Inst.addOperand(MCOperand::createImm(imm)); 1713 break; 1714 } 1715 1716 switch (Inst.getOpcode()) { 1717 case ARM::LDC_OFFSET: 1718 case ARM::LDC_PRE: 1719 case ARM::LDC_POST: 1720 case ARM::LDC_OPTION: 1721 case ARM::LDCL_OFFSET: 1722 case ARM::LDCL_PRE: 1723 case ARM::LDCL_POST: 1724 case ARM::LDCL_OPTION: 1725 case ARM::STC_OFFSET: 1726 case ARM::STC_PRE: 1727 case ARM::STC_POST: 1728 case ARM::STC_OPTION: 1729 case ARM::STCL_OFFSET: 1730 case ARM::STCL_PRE: 1731 case ARM::STCL_POST: 1732 case ARM::STCL_OPTION: 1733 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1734 return MCDisassembler::Fail; 1735 break; 1736 default: 1737 break; 1738 } 1739 1740 return S; 1741 } 1742 1743 static DecodeStatus 1744 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1745 uint64_t Address, const void *Decoder) { 1746 DecodeStatus S = MCDisassembler::Success; 1747 1748 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1749 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1750 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1751 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1752 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1753 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1754 unsigned P = fieldFromInstruction(Insn, 24, 1); 1755 unsigned W = fieldFromInstruction(Insn, 21, 1); 1756 1757 // On stores, the writeback operand precedes Rt. 1758 switch (Inst.getOpcode()) { 1759 case ARM::STR_POST_IMM: 1760 case ARM::STR_POST_REG: 1761 case ARM::STRB_POST_IMM: 1762 case ARM::STRB_POST_REG: 1763 case ARM::STRT_POST_REG: 1764 case ARM::STRT_POST_IMM: 1765 case ARM::STRBT_POST_REG: 1766 case ARM::STRBT_POST_IMM: 1767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1768 return MCDisassembler::Fail; 1769 break; 1770 default: 1771 break; 1772 } 1773 1774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1775 return MCDisassembler::Fail; 1776 1777 // On loads, the writeback operand comes after Rt. 1778 switch (Inst.getOpcode()) { 1779 case ARM::LDR_POST_IMM: 1780 case ARM::LDR_POST_REG: 1781 case ARM::LDRB_POST_IMM: 1782 case ARM::LDRB_POST_REG: 1783 case ARM::LDRBT_POST_REG: 1784 case ARM::LDRBT_POST_IMM: 1785 case ARM::LDRT_POST_REG: 1786 case ARM::LDRT_POST_IMM: 1787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1788 return MCDisassembler::Fail; 1789 break; 1790 default: 1791 break; 1792 } 1793 1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1795 return MCDisassembler::Fail; 1796 1797 ARM_AM::AddrOpc Op = ARM_AM::add; 1798 if (!fieldFromInstruction(Insn, 23, 1)) 1799 Op = ARM_AM::sub; 1800 1801 bool writeback = (P == 0) || (W == 1); 1802 unsigned idx_mode = 0; 1803 if (P && writeback) 1804 idx_mode = ARMII::IndexModePre; 1805 else if (!P && writeback) 1806 idx_mode = ARMII::IndexModePost; 1807 1808 if (writeback && (Rn == 15 || Rn == Rt)) 1809 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1810 1811 if (reg) { 1812 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1813 return MCDisassembler::Fail; 1814 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1815 switch( fieldFromInstruction(Insn, 5, 2)) { 1816 case 0: 1817 Opc = ARM_AM::lsl; 1818 break; 1819 case 1: 1820 Opc = ARM_AM::lsr; 1821 break; 1822 case 2: 1823 Opc = ARM_AM::asr; 1824 break; 1825 case 3: 1826 Opc = ARM_AM::ror; 1827 break; 1828 default: 1829 return MCDisassembler::Fail; 1830 } 1831 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1832 if (Opc == ARM_AM::ror && amt == 0) 1833 Opc = ARM_AM::rrx; 1834 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1835 1836 Inst.addOperand(MCOperand::createImm(imm)); 1837 } else { 1838 Inst.addOperand(MCOperand::createReg(0)); 1839 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1840 Inst.addOperand(MCOperand::createImm(tmp)); 1841 } 1842 1843 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1844 return MCDisassembler::Fail; 1845 1846 return S; 1847 } 1848 1849 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1850 uint64_t Address, const void *Decoder) { 1851 DecodeStatus S = MCDisassembler::Success; 1852 1853 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1854 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1855 unsigned type = fieldFromInstruction(Val, 5, 2); 1856 unsigned imm = fieldFromInstruction(Val, 7, 5); 1857 unsigned U = fieldFromInstruction(Val, 12, 1); 1858 1859 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1860 switch (type) { 1861 case 0: 1862 ShOp = ARM_AM::lsl; 1863 break; 1864 case 1: 1865 ShOp = ARM_AM::lsr; 1866 break; 1867 case 2: 1868 ShOp = ARM_AM::asr; 1869 break; 1870 case 3: 1871 ShOp = ARM_AM::ror; 1872 break; 1873 } 1874 1875 if (ShOp == ARM_AM::ror && imm == 0) 1876 ShOp = ARM_AM::rrx; 1877 1878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1879 return MCDisassembler::Fail; 1880 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1881 return MCDisassembler::Fail; 1882 unsigned shift; 1883 if (U) 1884 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1885 else 1886 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1887 Inst.addOperand(MCOperand::createImm(shift)); 1888 1889 return S; 1890 } 1891 1892 static DecodeStatus 1893 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1894 uint64_t Address, const void *Decoder) { 1895 DecodeStatus S = MCDisassembler::Success; 1896 1897 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1898 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1899 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1900 unsigned type = fieldFromInstruction(Insn, 22, 1); 1901 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1902 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1903 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1904 unsigned W = fieldFromInstruction(Insn, 21, 1); 1905 unsigned P = fieldFromInstruction(Insn, 24, 1); 1906 unsigned Rt2 = Rt + 1; 1907 1908 bool writeback = (W == 1) | (P == 0); 1909 1910 // For {LD,ST}RD, Rt must be even, else undefined. 1911 switch (Inst.getOpcode()) { 1912 case ARM::STRD: 1913 case ARM::STRD_PRE: 1914 case ARM::STRD_POST: 1915 case ARM::LDRD: 1916 case ARM::LDRD_PRE: 1917 case ARM::LDRD_POST: 1918 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1919 break; 1920 default: 1921 break; 1922 } 1923 switch (Inst.getOpcode()) { 1924 case ARM::STRD: 1925 case ARM::STRD_PRE: 1926 case ARM::STRD_POST: 1927 if (P == 0 && W == 1) 1928 S = MCDisassembler::SoftFail; 1929 1930 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1931 S = MCDisassembler::SoftFail; 1932 if (type && Rm == 15) 1933 S = MCDisassembler::SoftFail; 1934 if (Rt2 == 15) 1935 S = MCDisassembler::SoftFail; 1936 if (!type && fieldFromInstruction(Insn, 8, 4)) 1937 S = MCDisassembler::SoftFail; 1938 break; 1939 case ARM::STRH: 1940 case ARM::STRH_PRE: 1941 case ARM::STRH_POST: 1942 if (Rt == 15) 1943 S = MCDisassembler::SoftFail; 1944 if (writeback && (Rn == 15 || Rn == Rt)) 1945 S = MCDisassembler::SoftFail; 1946 if (!type && Rm == 15) 1947 S = MCDisassembler::SoftFail; 1948 break; 1949 case ARM::LDRD: 1950 case ARM::LDRD_PRE: 1951 case ARM::LDRD_POST: 1952 if (type && Rn == 15) { 1953 if (Rt2 == 15) 1954 S = MCDisassembler::SoftFail; 1955 break; 1956 } 1957 if (P == 0 && W == 1) 1958 S = MCDisassembler::SoftFail; 1959 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1960 S = MCDisassembler::SoftFail; 1961 if (!type && writeback && Rn == 15) 1962 S = MCDisassembler::SoftFail; 1963 if (writeback && (Rn == Rt || Rn == Rt2)) 1964 S = MCDisassembler::SoftFail; 1965 break; 1966 case ARM::LDRH: 1967 case ARM::LDRH_PRE: 1968 case ARM::LDRH_POST: 1969 if (type && Rn == 15) { 1970 if (Rt == 15) 1971 S = MCDisassembler::SoftFail; 1972 break; 1973 } 1974 if (Rt == 15) 1975 S = MCDisassembler::SoftFail; 1976 if (!type && Rm == 15) 1977 S = MCDisassembler::SoftFail; 1978 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1979 S = MCDisassembler::SoftFail; 1980 break; 1981 case ARM::LDRSH: 1982 case ARM::LDRSH_PRE: 1983 case ARM::LDRSH_POST: 1984 case ARM::LDRSB: 1985 case ARM::LDRSB_PRE: 1986 case ARM::LDRSB_POST: 1987 if (type && Rn == 15) { 1988 if (Rt == 15) 1989 S = MCDisassembler::SoftFail; 1990 break; 1991 } 1992 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1993 S = MCDisassembler::SoftFail; 1994 if (!type && (Rt == 15 || Rm == 15)) 1995 S = MCDisassembler::SoftFail; 1996 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1997 S = MCDisassembler::SoftFail; 1998 break; 1999 default: 2000 break; 2001 } 2002 2003 if (writeback) { // Writeback 2004 if (P) 2005 U |= ARMII::IndexModePre << 9; 2006 else 2007 U |= ARMII::IndexModePost << 9; 2008 2009 // On stores, the writeback operand precedes Rt. 2010 switch (Inst.getOpcode()) { 2011 case ARM::STRD: 2012 case ARM::STRD_PRE: 2013 case ARM::STRD_POST: 2014 case ARM::STRH: 2015 case ARM::STRH_PRE: 2016 case ARM::STRH_POST: 2017 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2018 return MCDisassembler::Fail; 2019 break; 2020 default: 2021 break; 2022 } 2023 } 2024 2025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2026 return MCDisassembler::Fail; 2027 switch (Inst.getOpcode()) { 2028 case ARM::STRD: 2029 case ARM::STRD_PRE: 2030 case ARM::STRD_POST: 2031 case ARM::LDRD: 2032 case ARM::LDRD_PRE: 2033 case ARM::LDRD_POST: 2034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2035 return MCDisassembler::Fail; 2036 break; 2037 default: 2038 break; 2039 } 2040 2041 if (writeback) { 2042 // On loads, the writeback operand comes after Rt. 2043 switch (Inst.getOpcode()) { 2044 case ARM::LDRD: 2045 case ARM::LDRD_PRE: 2046 case ARM::LDRD_POST: 2047 case ARM::LDRH: 2048 case ARM::LDRH_PRE: 2049 case ARM::LDRH_POST: 2050 case ARM::LDRSH: 2051 case ARM::LDRSH_PRE: 2052 case ARM::LDRSH_POST: 2053 case ARM::LDRSB: 2054 case ARM::LDRSB_PRE: 2055 case ARM::LDRSB_POST: 2056 case ARM::LDRHTr: 2057 case ARM::LDRSBTr: 2058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2059 return MCDisassembler::Fail; 2060 break; 2061 default: 2062 break; 2063 } 2064 } 2065 2066 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2067 return MCDisassembler::Fail; 2068 2069 if (type) { 2070 Inst.addOperand(MCOperand::createReg(0)); 2071 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2072 } else { 2073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2074 return MCDisassembler::Fail; 2075 Inst.addOperand(MCOperand::createImm(U)); 2076 } 2077 2078 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2079 return MCDisassembler::Fail; 2080 2081 return S; 2082 } 2083 2084 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2085 uint64_t Address, const void *Decoder) { 2086 DecodeStatus S = MCDisassembler::Success; 2087 2088 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2089 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2090 2091 switch (mode) { 2092 case 0: 2093 mode = ARM_AM::da; 2094 break; 2095 case 1: 2096 mode = ARM_AM::ia; 2097 break; 2098 case 2: 2099 mode = ARM_AM::db; 2100 break; 2101 case 3: 2102 mode = ARM_AM::ib; 2103 break; 2104 } 2105 2106 Inst.addOperand(MCOperand::createImm(mode)); 2107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2108 return MCDisassembler::Fail; 2109 2110 return S; 2111 } 2112 2113 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2114 uint64_t Address, const void *Decoder) { 2115 DecodeStatus S = MCDisassembler::Success; 2116 2117 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2118 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2119 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2120 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2121 2122 if (pred == 0xF) 2123 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2124 2125 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2126 return MCDisassembler::Fail; 2127 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2130 return MCDisassembler::Fail; 2131 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2132 return MCDisassembler::Fail; 2133 return S; 2134 } 2135 2136 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2137 unsigned Insn, 2138 uint64_t Address, const void *Decoder) { 2139 DecodeStatus S = MCDisassembler::Success; 2140 2141 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2142 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2143 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2144 2145 if (pred == 0xF) { 2146 // Ambiguous with RFE and SRS 2147 switch (Inst.getOpcode()) { 2148 case ARM::LDMDA: 2149 Inst.setOpcode(ARM::RFEDA); 2150 break; 2151 case ARM::LDMDA_UPD: 2152 Inst.setOpcode(ARM::RFEDA_UPD); 2153 break; 2154 case ARM::LDMDB: 2155 Inst.setOpcode(ARM::RFEDB); 2156 break; 2157 case ARM::LDMDB_UPD: 2158 Inst.setOpcode(ARM::RFEDB_UPD); 2159 break; 2160 case ARM::LDMIA: 2161 Inst.setOpcode(ARM::RFEIA); 2162 break; 2163 case ARM::LDMIA_UPD: 2164 Inst.setOpcode(ARM::RFEIA_UPD); 2165 break; 2166 case ARM::LDMIB: 2167 Inst.setOpcode(ARM::RFEIB); 2168 break; 2169 case ARM::LDMIB_UPD: 2170 Inst.setOpcode(ARM::RFEIB_UPD); 2171 break; 2172 case ARM::STMDA: 2173 Inst.setOpcode(ARM::SRSDA); 2174 break; 2175 case ARM::STMDA_UPD: 2176 Inst.setOpcode(ARM::SRSDA_UPD); 2177 break; 2178 case ARM::STMDB: 2179 Inst.setOpcode(ARM::SRSDB); 2180 break; 2181 case ARM::STMDB_UPD: 2182 Inst.setOpcode(ARM::SRSDB_UPD); 2183 break; 2184 case ARM::STMIA: 2185 Inst.setOpcode(ARM::SRSIA); 2186 break; 2187 case ARM::STMIA_UPD: 2188 Inst.setOpcode(ARM::SRSIA_UPD); 2189 break; 2190 case ARM::STMIB: 2191 Inst.setOpcode(ARM::SRSIB); 2192 break; 2193 case ARM::STMIB_UPD: 2194 Inst.setOpcode(ARM::SRSIB_UPD); 2195 break; 2196 default: 2197 return MCDisassembler::Fail; 2198 } 2199 2200 // For stores (which become SRS's, the only operand is the mode. 2201 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2202 // Check SRS encoding constraints 2203 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2204 fieldFromInstruction(Insn, 20, 1) == 0)) 2205 return MCDisassembler::Fail; 2206 2207 Inst.addOperand( 2208 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2209 return S; 2210 } 2211 2212 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2213 } 2214 2215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2216 return MCDisassembler::Fail; 2217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2218 return MCDisassembler::Fail; // Tied 2219 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2220 return MCDisassembler::Fail; 2221 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2222 return MCDisassembler::Fail; 2223 2224 return S; 2225 } 2226 2227 // Check for UNPREDICTABLE predicated ESB instruction 2228 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2229 uint64_t Address, const void *Decoder) { 2230 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2231 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2232 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2233 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2234 2235 DecodeStatus S = MCDisassembler::Success; 2236 2237 Inst.addOperand(MCOperand::createImm(imm8)); 2238 2239 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2240 return MCDisassembler::Fail; 2241 2242 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2243 // so all predicates should be allowed. 2244 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2245 S = MCDisassembler::SoftFail; 2246 2247 return S; 2248 } 2249 2250 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2251 uint64_t Address, const void *Decoder) { 2252 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2253 unsigned M = fieldFromInstruction(Insn, 17, 1); 2254 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2255 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2256 2257 DecodeStatus S = MCDisassembler::Success; 2258 2259 // This decoder is called from multiple location that do not check 2260 // the full encoding is valid before they do. 2261 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2262 fieldFromInstruction(Insn, 16, 1) != 0 || 2263 fieldFromInstruction(Insn, 20, 8) != 0x10) 2264 return MCDisassembler::Fail; 2265 2266 // imod == '01' --> UNPREDICTABLE 2267 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2268 // return failure here. The '01' imod value is unprintable, so there's 2269 // nothing useful we could do even if we returned UNPREDICTABLE. 2270 2271 if (imod == 1) return MCDisassembler::Fail; 2272 2273 if (imod && M) { 2274 Inst.setOpcode(ARM::CPS3p); 2275 Inst.addOperand(MCOperand::createImm(imod)); 2276 Inst.addOperand(MCOperand::createImm(iflags)); 2277 Inst.addOperand(MCOperand::createImm(mode)); 2278 } else if (imod && !M) { 2279 Inst.setOpcode(ARM::CPS2p); 2280 Inst.addOperand(MCOperand::createImm(imod)); 2281 Inst.addOperand(MCOperand::createImm(iflags)); 2282 if (mode) S = MCDisassembler::SoftFail; 2283 } else if (!imod && M) { 2284 Inst.setOpcode(ARM::CPS1p); 2285 Inst.addOperand(MCOperand::createImm(mode)); 2286 if (iflags) S = MCDisassembler::SoftFail; 2287 } else { 2288 // imod == '00' && M == '0' --> UNPREDICTABLE 2289 Inst.setOpcode(ARM::CPS1p); 2290 Inst.addOperand(MCOperand::createImm(mode)); 2291 S = MCDisassembler::SoftFail; 2292 } 2293 2294 return S; 2295 } 2296 2297 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2298 uint64_t Address, const void *Decoder) { 2299 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2300 unsigned M = fieldFromInstruction(Insn, 8, 1); 2301 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2302 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2303 2304 DecodeStatus S = MCDisassembler::Success; 2305 2306 // imod == '01' --> UNPREDICTABLE 2307 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2308 // return failure here. The '01' imod value is unprintable, so there's 2309 // nothing useful we could do even if we returned UNPREDICTABLE. 2310 2311 if (imod == 1) return MCDisassembler::Fail; 2312 2313 if (imod && M) { 2314 Inst.setOpcode(ARM::t2CPS3p); 2315 Inst.addOperand(MCOperand::createImm(imod)); 2316 Inst.addOperand(MCOperand::createImm(iflags)); 2317 Inst.addOperand(MCOperand::createImm(mode)); 2318 } else if (imod && !M) { 2319 Inst.setOpcode(ARM::t2CPS2p); 2320 Inst.addOperand(MCOperand::createImm(imod)); 2321 Inst.addOperand(MCOperand::createImm(iflags)); 2322 if (mode) S = MCDisassembler::SoftFail; 2323 } else if (!imod && M) { 2324 Inst.setOpcode(ARM::t2CPS1p); 2325 Inst.addOperand(MCOperand::createImm(mode)); 2326 if (iflags) S = MCDisassembler::SoftFail; 2327 } else { 2328 // imod == '00' && M == '0' --> this is a HINT instruction 2329 int imm = fieldFromInstruction(Insn, 0, 8); 2330 // HINT are defined only for immediate in [0..4] 2331 if(imm > 4) return MCDisassembler::Fail; 2332 Inst.setOpcode(ARM::t2HINT); 2333 Inst.addOperand(MCOperand::createImm(imm)); 2334 } 2335 2336 return S; 2337 } 2338 2339 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2340 uint64_t Address, const void *Decoder) { 2341 DecodeStatus S = MCDisassembler::Success; 2342 2343 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2344 unsigned imm = 0; 2345 2346 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2347 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2348 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2349 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2350 2351 if (Inst.getOpcode() == ARM::t2MOVTi16) 2352 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2353 return MCDisassembler::Fail; 2354 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2355 return MCDisassembler::Fail; 2356 2357 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2358 Inst.addOperand(MCOperand::createImm(imm)); 2359 2360 return S; 2361 } 2362 2363 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2364 uint64_t Address, const void *Decoder) { 2365 DecodeStatus S = MCDisassembler::Success; 2366 2367 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2368 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2369 unsigned imm = 0; 2370 2371 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2372 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2373 2374 if (Inst.getOpcode() == ARM::MOVTi16) 2375 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2376 return MCDisassembler::Fail; 2377 2378 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2379 return MCDisassembler::Fail; 2380 2381 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2382 Inst.addOperand(MCOperand::createImm(imm)); 2383 2384 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2385 return MCDisassembler::Fail; 2386 2387 return S; 2388 } 2389 2390 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2391 uint64_t Address, const void *Decoder) { 2392 DecodeStatus S = MCDisassembler::Success; 2393 2394 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2395 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2396 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2397 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2398 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2399 2400 if (pred == 0xF) 2401 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2402 2403 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2404 return MCDisassembler::Fail; 2405 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2406 return MCDisassembler::Fail; 2407 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2408 return MCDisassembler::Fail; 2409 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2410 return MCDisassembler::Fail; 2411 2412 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2413 return MCDisassembler::Fail; 2414 2415 return S; 2416 } 2417 2418 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2419 uint64_t Address, const void *Decoder) { 2420 DecodeStatus S = MCDisassembler::Success; 2421 2422 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2423 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2424 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2425 2426 if (Pred == 0xF) 2427 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2428 2429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2430 return MCDisassembler::Fail; 2431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2432 return MCDisassembler::Fail; 2433 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2434 return MCDisassembler::Fail; 2435 2436 return S; 2437 } 2438 2439 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2440 uint64_t Address, const void *Decoder) { 2441 DecodeStatus S = MCDisassembler::Success; 2442 2443 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2444 2445 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2446 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2447 2448 if (!FeatureBits[ARM::HasV8_1aOps] || 2449 !FeatureBits[ARM::HasV8Ops]) 2450 return MCDisassembler::Fail; 2451 2452 // Decoder can be called from DecodeTST, which does not check the full 2453 // encoding is valid. 2454 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2455 fieldFromInstruction(Insn, 4,4) != 0) 2456 return MCDisassembler::Fail; 2457 if (fieldFromInstruction(Insn, 10,10) != 0 || 2458 fieldFromInstruction(Insn, 0,4) != 0) 2459 S = MCDisassembler::SoftFail; 2460 2461 Inst.setOpcode(ARM::SETPAN); 2462 Inst.addOperand(MCOperand::createImm(Imm)); 2463 2464 return S; 2465 } 2466 2467 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2468 uint64_t Address, const void *Decoder) { 2469 DecodeStatus S = MCDisassembler::Success; 2470 2471 unsigned add = fieldFromInstruction(Val, 12, 1); 2472 unsigned imm = fieldFromInstruction(Val, 0, 12); 2473 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2474 2475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2476 return MCDisassembler::Fail; 2477 2478 if (!add) imm *= -1; 2479 if (imm == 0 && !add) imm = INT32_MIN; 2480 Inst.addOperand(MCOperand::createImm(imm)); 2481 if (Rn == 15) 2482 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2483 2484 return S; 2485 } 2486 2487 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2488 uint64_t Address, const void *Decoder) { 2489 DecodeStatus S = MCDisassembler::Success; 2490 2491 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2492 // U == 1 to add imm, 0 to subtract it. 2493 unsigned U = fieldFromInstruction(Val, 8, 1); 2494 unsigned imm = fieldFromInstruction(Val, 0, 8); 2495 2496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2497 return MCDisassembler::Fail; 2498 2499 if (U) 2500 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2501 else 2502 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2503 2504 return S; 2505 } 2506 2507 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2508 uint64_t Address, const void *Decoder) { 2509 DecodeStatus S = MCDisassembler::Success; 2510 2511 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2512 // U == 1 to add imm, 0 to subtract it. 2513 unsigned U = fieldFromInstruction(Val, 8, 1); 2514 unsigned imm = fieldFromInstruction(Val, 0, 8); 2515 2516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2517 return MCDisassembler::Fail; 2518 2519 if (U) 2520 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2521 else 2522 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2523 2524 return S; 2525 } 2526 2527 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2528 uint64_t Address, const void *Decoder) { 2529 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2530 } 2531 2532 static DecodeStatus 2533 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2534 uint64_t Address, const void *Decoder) { 2535 DecodeStatus Status = MCDisassembler::Success; 2536 2537 // Note the J1 and J2 values are from the encoded instruction. So here 2538 // change them to I1 and I2 values via as documented: 2539 // I1 = NOT(J1 EOR S); 2540 // I2 = NOT(J2 EOR S); 2541 // and build the imm32 with one trailing zero as documented: 2542 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2543 unsigned S = fieldFromInstruction(Insn, 26, 1); 2544 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2545 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2546 unsigned I1 = !(J1 ^ S); 2547 unsigned I2 = !(J2 ^ S); 2548 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2549 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2550 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2551 int imm32 = SignExtend32<25>(tmp << 1); 2552 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2553 true, 4, Inst, Decoder)) 2554 Inst.addOperand(MCOperand::createImm(imm32)); 2555 2556 return Status; 2557 } 2558 2559 static DecodeStatus 2560 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2561 uint64_t Address, const void *Decoder) { 2562 DecodeStatus S = MCDisassembler::Success; 2563 2564 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2565 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2566 2567 if (pred == 0xF) { 2568 Inst.setOpcode(ARM::BLXi); 2569 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2570 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2571 true, 4, Inst, Decoder)) 2572 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2573 return S; 2574 } 2575 2576 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2577 true, 4, Inst, Decoder)) 2578 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2579 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2580 return MCDisassembler::Fail; 2581 2582 return S; 2583 } 2584 2585 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2586 uint64_t Address, const void *Decoder) { 2587 DecodeStatus S = MCDisassembler::Success; 2588 2589 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2590 unsigned align = fieldFromInstruction(Val, 4, 2); 2591 2592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2593 return MCDisassembler::Fail; 2594 if (!align) 2595 Inst.addOperand(MCOperand::createImm(0)); 2596 else 2597 Inst.addOperand(MCOperand::createImm(4 << align)); 2598 2599 return S; 2600 } 2601 2602 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2603 uint64_t Address, const void *Decoder) { 2604 DecodeStatus S = MCDisassembler::Success; 2605 2606 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2607 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2608 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2609 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2610 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2611 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2612 2613 // First output register 2614 switch (Inst.getOpcode()) { 2615 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2616 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2617 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2618 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2619 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2620 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2621 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2622 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2623 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2624 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2625 return MCDisassembler::Fail; 2626 break; 2627 case ARM::VLD2b16: 2628 case ARM::VLD2b32: 2629 case ARM::VLD2b8: 2630 case ARM::VLD2b16wb_fixed: 2631 case ARM::VLD2b16wb_register: 2632 case ARM::VLD2b32wb_fixed: 2633 case ARM::VLD2b32wb_register: 2634 case ARM::VLD2b8wb_fixed: 2635 case ARM::VLD2b8wb_register: 2636 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2637 return MCDisassembler::Fail; 2638 break; 2639 default: 2640 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2641 return MCDisassembler::Fail; 2642 } 2643 2644 // Second output register 2645 switch (Inst.getOpcode()) { 2646 case ARM::VLD3d8: 2647 case ARM::VLD3d16: 2648 case ARM::VLD3d32: 2649 case ARM::VLD3d8_UPD: 2650 case ARM::VLD3d16_UPD: 2651 case ARM::VLD3d32_UPD: 2652 case ARM::VLD4d8: 2653 case ARM::VLD4d16: 2654 case ARM::VLD4d32: 2655 case ARM::VLD4d8_UPD: 2656 case ARM::VLD4d16_UPD: 2657 case ARM::VLD4d32_UPD: 2658 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2659 return MCDisassembler::Fail; 2660 break; 2661 case ARM::VLD3q8: 2662 case ARM::VLD3q16: 2663 case ARM::VLD3q32: 2664 case ARM::VLD3q8_UPD: 2665 case ARM::VLD3q16_UPD: 2666 case ARM::VLD3q32_UPD: 2667 case ARM::VLD4q8: 2668 case ARM::VLD4q16: 2669 case ARM::VLD4q32: 2670 case ARM::VLD4q8_UPD: 2671 case ARM::VLD4q16_UPD: 2672 case ARM::VLD4q32_UPD: 2673 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2674 return MCDisassembler::Fail; 2675 break; 2676 default: 2677 break; 2678 } 2679 2680 // Third output register 2681 switch(Inst.getOpcode()) { 2682 case ARM::VLD3d8: 2683 case ARM::VLD3d16: 2684 case ARM::VLD3d32: 2685 case ARM::VLD3d8_UPD: 2686 case ARM::VLD3d16_UPD: 2687 case ARM::VLD3d32_UPD: 2688 case ARM::VLD4d8: 2689 case ARM::VLD4d16: 2690 case ARM::VLD4d32: 2691 case ARM::VLD4d8_UPD: 2692 case ARM::VLD4d16_UPD: 2693 case ARM::VLD4d32_UPD: 2694 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2695 return MCDisassembler::Fail; 2696 break; 2697 case ARM::VLD3q8: 2698 case ARM::VLD3q16: 2699 case ARM::VLD3q32: 2700 case ARM::VLD3q8_UPD: 2701 case ARM::VLD3q16_UPD: 2702 case ARM::VLD3q32_UPD: 2703 case ARM::VLD4q8: 2704 case ARM::VLD4q16: 2705 case ARM::VLD4q32: 2706 case ARM::VLD4q8_UPD: 2707 case ARM::VLD4q16_UPD: 2708 case ARM::VLD4q32_UPD: 2709 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2710 return MCDisassembler::Fail; 2711 break; 2712 default: 2713 break; 2714 } 2715 2716 // Fourth output register 2717 switch (Inst.getOpcode()) { 2718 case ARM::VLD4d8: 2719 case ARM::VLD4d16: 2720 case ARM::VLD4d32: 2721 case ARM::VLD4d8_UPD: 2722 case ARM::VLD4d16_UPD: 2723 case ARM::VLD4d32_UPD: 2724 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 break; 2727 case ARM::VLD4q8: 2728 case ARM::VLD4q16: 2729 case ARM::VLD4q32: 2730 case ARM::VLD4q8_UPD: 2731 case ARM::VLD4q16_UPD: 2732 case ARM::VLD4q32_UPD: 2733 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2734 return MCDisassembler::Fail; 2735 break; 2736 default: 2737 break; 2738 } 2739 2740 // Writeback operand 2741 switch (Inst.getOpcode()) { 2742 case ARM::VLD1d8wb_fixed: 2743 case ARM::VLD1d16wb_fixed: 2744 case ARM::VLD1d32wb_fixed: 2745 case ARM::VLD1d64wb_fixed: 2746 case ARM::VLD1d8wb_register: 2747 case ARM::VLD1d16wb_register: 2748 case ARM::VLD1d32wb_register: 2749 case ARM::VLD1d64wb_register: 2750 case ARM::VLD1q8wb_fixed: 2751 case ARM::VLD1q16wb_fixed: 2752 case ARM::VLD1q32wb_fixed: 2753 case ARM::VLD1q64wb_fixed: 2754 case ARM::VLD1q8wb_register: 2755 case ARM::VLD1q16wb_register: 2756 case ARM::VLD1q32wb_register: 2757 case ARM::VLD1q64wb_register: 2758 case ARM::VLD1d8Twb_fixed: 2759 case ARM::VLD1d8Twb_register: 2760 case ARM::VLD1d16Twb_fixed: 2761 case ARM::VLD1d16Twb_register: 2762 case ARM::VLD1d32Twb_fixed: 2763 case ARM::VLD1d32Twb_register: 2764 case ARM::VLD1d64Twb_fixed: 2765 case ARM::VLD1d64Twb_register: 2766 case ARM::VLD1d8Qwb_fixed: 2767 case ARM::VLD1d8Qwb_register: 2768 case ARM::VLD1d16Qwb_fixed: 2769 case ARM::VLD1d16Qwb_register: 2770 case ARM::VLD1d32Qwb_fixed: 2771 case ARM::VLD1d32Qwb_register: 2772 case ARM::VLD1d64Qwb_fixed: 2773 case ARM::VLD1d64Qwb_register: 2774 case ARM::VLD2d8wb_fixed: 2775 case ARM::VLD2d16wb_fixed: 2776 case ARM::VLD2d32wb_fixed: 2777 case ARM::VLD2q8wb_fixed: 2778 case ARM::VLD2q16wb_fixed: 2779 case ARM::VLD2q32wb_fixed: 2780 case ARM::VLD2d8wb_register: 2781 case ARM::VLD2d16wb_register: 2782 case ARM::VLD2d32wb_register: 2783 case ARM::VLD2q8wb_register: 2784 case ARM::VLD2q16wb_register: 2785 case ARM::VLD2q32wb_register: 2786 case ARM::VLD2b8wb_fixed: 2787 case ARM::VLD2b16wb_fixed: 2788 case ARM::VLD2b32wb_fixed: 2789 case ARM::VLD2b8wb_register: 2790 case ARM::VLD2b16wb_register: 2791 case ARM::VLD2b32wb_register: 2792 Inst.addOperand(MCOperand::createImm(0)); 2793 break; 2794 case ARM::VLD3d8_UPD: 2795 case ARM::VLD3d16_UPD: 2796 case ARM::VLD3d32_UPD: 2797 case ARM::VLD3q8_UPD: 2798 case ARM::VLD3q16_UPD: 2799 case ARM::VLD3q32_UPD: 2800 case ARM::VLD4d8_UPD: 2801 case ARM::VLD4d16_UPD: 2802 case ARM::VLD4d32_UPD: 2803 case ARM::VLD4q8_UPD: 2804 case ARM::VLD4q16_UPD: 2805 case ARM::VLD4q32_UPD: 2806 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2807 return MCDisassembler::Fail; 2808 break; 2809 default: 2810 break; 2811 } 2812 2813 // AddrMode6 Base (register+alignment) 2814 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2815 return MCDisassembler::Fail; 2816 2817 // AddrMode6 Offset (register) 2818 switch (Inst.getOpcode()) { 2819 default: 2820 // The below have been updated to have explicit am6offset split 2821 // between fixed and register offset. For those instructions not 2822 // yet updated, we need to add an additional reg0 operand for the 2823 // fixed variant. 2824 // 2825 // The fixed offset encodes as Rm == 0xd, so we check for that. 2826 if (Rm == 0xd) { 2827 Inst.addOperand(MCOperand::createReg(0)); 2828 break; 2829 } 2830 // Fall through to handle the register offset variant. 2831 LLVM_FALLTHROUGH; 2832 case ARM::VLD1d8wb_fixed: 2833 case ARM::VLD1d16wb_fixed: 2834 case ARM::VLD1d32wb_fixed: 2835 case ARM::VLD1d64wb_fixed: 2836 case ARM::VLD1d8Twb_fixed: 2837 case ARM::VLD1d16Twb_fixed: 2838 case ARM::VLD1d32Twb_fixed: 2839 case ARM::VLD1d64Twb_fixed: 2840 case ARM::VLD1d8Qwb_fixed: 2841 case ARM::VLD1d16Qwb_fixed: 2842 case ARM::VLD1d32Qwb_fixed: 2843 case ARM::VLD1d64Qwb_fixed: 2844 case ARM::VLD1d8wb_register: 2845 case ARM::VLD1d16wb_register: 2846 case ARM::VLD1d32wb_register: 2847 case ARM::VLD1d64wb_register: 2848 case ARM::VLD1q8wb_fixed: 2849 case ARM::VLD1q16wb_fixed: 2850 case ARM::VLD1q32wb_fixed: 2851 case ARM::VLD1q64wb_fixed: 2852 case ARM::VLD1q8wb_register: 2853 case ARM::VLD1q16wb_register: 2854 case ARM::VLD1q32wb_register: 2855 case ARM::VLD1q64wb_register: 2856 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2857 // variant encodes Rm == 0xf. Anything else is a register offset post- 2858 // increment and we need to add the register operand to the instruction. 2859 if (Rm != 0xD && Rm != 0xF && 2860 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2861 return MCDisassembler::Fail; 2862 break; 2863 case ARM::VLD2d8wb_fixed: 2864 case ARM::VLD2d16wb_fixed: 2865 case ARM::VLD2d32wb_fixed: 2866 case ARM::VLD2b8wb_fixed: 2867 case ARM::VLD2b16wb_fixed: 2868 case ARM::VLD2b32wb_fixed: 2869 case ARM::VLD2q8wb_fixed: 2870 case ARM::VLD2q16wb_fixed: 2871 case ARM::VLD2q32wb_fixed: 2872 break; 2873 } 2874 2875 return S; 2876 } 2877 2878 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2879 uint64_t Address, const void *Decoder) { 2880 unsigned type = fieldFromInstruction(Insn, 8, 4); 2881 unsigned align = fieldFromInstruction(Insn, 4, 2); 2882 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2883 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2884 if (type == 10 && align == 3) return MCDisassembler::Fail; 2885 2886 unsigned load = fieldFromInstruction(Insn, 21, 1); 2887 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2888 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2889 } 2890 2891 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2892 uint64_t Address, const void *Decoder) { 2893 unsigned size = fieldFromInstruction(Insn, 6, 2); 2894 if (size == 3) return MCDisassembler::Fail; 2895 2896 unsigned type = fieldFromInstruction(Insn, 8, 4); 2897 unsigned align = fieldFromInstruction(Insn, 4, 2); 2898 if (type == 8 && align == 3) return MCDisassembler::Fail; 2899 if (type == 9 && align == 3) return MCDisassembler::Fail; 2900 2901 unsigned load = fieldFromInstruction(Insn, 21, 1); 2902 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2903 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2904 } 2905 2906 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2907 uint64_t Address, const void *Decoder) { 2908 unsigned size = fieldFromInstruction(Insn, 6, 2); 2909 if (size == 3) return MCDisassembler::Fail; 2910 2911 unsigned align = fieldFromInstruction(Insn, 4, 2); 2912 if (align & 2) return MCDisassembler::Fail; 2913 2914 unsigned load = fieldFromInstruction(Insn, 21, 1); 2915 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2916 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2917 } 2918 2919 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2920 uint64_t Address, const void *Decoder) { 2921 unsigned size = fieldFromInstruction(Insn, 6, 2); 2922 if (size == 3) return MCDisassembler::Fail; 2923 2924 unsigned load = fieldFromInstruction(Insn, 21, 1); 2925 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2926 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2927 } 2928 2929 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2930 uint64_t Address, const void *Decoder) { 2931 DecodeStatus S = MCDisassembler::Success; 2932 2933 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2934 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2935 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2936 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2937 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2938 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2939 2940 // Writeback Operand 2941 switch (Inst.getOpcode()) { 2942 case ARM::VST1d8wb_fixed: 2943 case ARM::VST1d16wb_fixed: 2944 case ARM::VST1d32wb_fixed: 2945 case ARM::VST1d64wb_fixed: 2946 case ARM::VST1d8wb_register: 2947 case ARM::VST1d16wb_register: 2948 case ARM::VST1d32wb_register: 2949 case ARM::VST1d64wb_register: 2950 case ARM::VST1q8wb_fixed: 2951 case ARM::VST1q16wb_fixed: 2952 case ARM::VST1q32wb_fixed: 2953 case ARM::VST1q64wb_fixed: 2954 case ARM::VST1q8wb_register: 2955 case ARM::VST1q16wb_register: 2956 case ARM::VST1q32wb_register: 2957 case ARM::VST1q64wb_register: 2958 case ARM::VST1d8Twb_fixed: 2959 case ARM::VST1d16Twb_fixed: 2960 case ARM::VST1d32Twb_fixed: 2961 case ARM::VST1d64Twb_fixed: 2962 case ARM::VST1d8Twb_register: 2963 case ARM::VST1d16Twb_register: 2964 case ARM::VST1d32Twb_register: 2965 case ARM::VST1d64Twb_register: 2966 case ARM::VST1d8Qwb_fixed: 2967 case ARM::VST1d16Qwb_fixed: 2968 case ARM::VST1d32Qwb_fixed: 2969 case ARM::VST1d64Qwb_fixed: 2970 case ARM::VST1d8Qwb_register: 2971 case ARM::VST1d16Qwb_register: 2972 case ARM::VST1d32Qwb_register: 2973 case ARM::VST1d64Qwb_register: 2974 case ARM::VST2d8wb_fixed: 2975 case ARM::VST2d16wb_fixed: 2976 case ARM::VST2d32wb_fixed: 2977 case ARM::VST2d8wb_register: 2978 case ARM::VST2d16wb_register: 2979 case ARM::VST2d32wb_register: 2980 case ARM::VST2q8wb_fixed: 2981 case ARM::VST2q16wb_fixed: 2982 case ARM::VST2q32wb_fixed: 2983 case ARM::VST2q8wb_register: 2984 case ARM::VST2q16wb_register: 2985 case ARM::VST2q32wb_register: 2986 case ARM::VST2b8wb_fixed: 2987 case ARM::VST2b16wb_fixed: 2988 case ARM::VST2b32wb_fixed: 2989 case ARM::VST2b8wb_register: 2990 case ARM::VST2b16wb_register: 2991 case ARM::VST2b32wb_register: 2992 if (Rm == 0xF) 2993 return MCDisassembler::Fail; 2994 Inst.addOperand(MCOperand::createImm(0)); 2995 break; 2996 case ARM::VST3d8_UPD: 2997 case ARM::VST3d16_UPD: 2998 case ARM::VST3d32_UPD: 2999 case ARM::VST3q8_UPD: 3000 case ARM::VST3q16_UPD: 3001 case ARM::VST3q32_UPD: 3002 case ARM::VST4d8_UPD: 3003 case ARM::VST4d16_UPD: 3004 case ARM::VST4d32_UPD: 3005 case ARM::VST4q8_UPD: 3006 case ARM::VST4q16_UPD: 3007 case ARM::VST4q32_UPD: 3008 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3009 return MCDisassembler::Fail; 3010 break; 3011 default: 3012 break; 3013 } 3014 3015 // AddrMode6 Base (register+alignment) 3016 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3017 return MCDisassembler::Fail; 3018 3019 // AddrMode6 Offset (register) 3020 switch (Inst.getOpcode()) { 3021 default: 3022 if (Rm == 0xD) 3023 Inst.addOperand(MCOperand::createReg(0)); 3024 else if (Rm != 0xF) { 3025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3026 return MCDisassembler::Fail; 3027 } 3028 break; 3029 case ARM::VST1d8wb_fixed: 3030 case ARM::VST1d16wb_fixed: 3031 case ARM::VST1d32wb_fixed: 3032 case ARM::VST1d64wb_fixed: 3033 case ARM::VST1q8wb_fixed: 3034 case ARM::VST1q16wb_fixed: 3035 case ARM::VST1q32wb_fixed: 3036 case ARM::VST1q64wb_fixed: 3037 case ARM::VST1d8Twb_fixed: 3038 case ARM::VST1d16Twb_fixed: 3039 case ARM::VST1d32Twb_fixed: 3040 case ARM::VST1d64Twb_fixed: 3041 case ARM::VST1d8Qwb_fixed: 3042 case ARM::VST1d16Qwb_fixed: 3043 case ARM::VST1d32Qwb_fixed: 3044 case ARM::VST1d64Qwb_fixed: 3045 case ARM::VST2d8wb_fixed: 3046 case ARM::VST2d16wb_fixed: 3047 case ARM::VST2d32wb_fixed: 3048 case ARM::VST2q8wb_fixed: 3049 case ARM::VST2q16wb_fixed: 3050 case ARM::VST2q32wb_fixed: 3051 case ARM::VST2b8wb_fixed: 3052 case ARM::VST2b16wb_fixed: 3053 case ARM::VST2b32wb_fixed: 3054 break; 3055 } 3056 3057 // First input register 3058 switch (Inst.getOpcode()) { 3059 case ARM::VST1q16: 3060 case ARM::VST1q32: 3061 case ARM::VST1q64: 3062 case ARM::VST1q8: 3063 case ARM::VST1q16wb_fixed: 3064 case ARM::VST1q16wb_register: 3065 case ARM::VST1q32wb_fixed: 3066 case ARM::VST1q32wb_register: 3067 case ARM::VST1q64wb_fixed: 3068 case ARM::VST1q64wb_register: 3069 case ARM::VST1q8wb_fixed: 3070 case ARM::VST1q8wb_register: 3071 case ARM::VST2d16: 3072 case ARM::VST2d32: 3073 case ARM::VST2d8: 3074 case ARM::VST2d16wb_fixed: 3075 case ARM::VST2d16wb_register: 3076 case ARM::VST2d32wb_fixed: 3077 case ARM::VST2d32wb_register: 3078 case ARM::VST2d8wb_fixed: 3079 case ARM::VST2d8wb_register: 3080 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3081 return MCDisassembler::Fail; 3082 break; 3083 case ARM::VST2b16: 3084 case ARM::VST2b32: 3085 case ARM::VST2b8: 3086 case ARM::VST2b16wb_fixed: 3087 case ARM::VST2b16wb_register: 3088 case ARM::VST2b32wb_fixed: 3089 case ARM::VST2b32wb_register: 3090 case ARM::VST2b8wb_fixed: 3091 case ARM::VST2b8wb_register: 3092 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3093 return MCDisassembler::Fail; 3094 break; 3095 default: 3096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3097 return MCDisassembler::Fail; 3098 } 3099 3100 // Second input register 3101 switch (Inst.getOpcode()) { 3102 case ARM::VST3d8: 3103 case ARM::VST3d16: 3104 case ARM::VST3d32: 3105 case ARM::VST3d8_UPD: 3106 case ARM::VST3d16_UPD: 3107 case ARM::VST3d32_UPD: 3108 case ARM::VST4d8: 3109 case ARM::VST4d16: 3110 case ARM::VST4d32: 3111 case ARM::VST4d8_UPD: 3112 case ARM::VST4d16_UPD: 3113 case ARM::VST4d32_UPD: 3114 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3115 return MCDisassembler::Fail; 3116 break; 3117 case ARM::VST3q8: 3118 case ARM::VST3q16: 3119 case ARM::VST3q32: 3120 case ARM::VST3q8_UPD: 3121 case ARM::VST3q16_UPD: 3122 case ARM::VST3q32_UPD: 3123 case ARM::VST4q8: 3124 case ARM::VST4q16: 3125 case ARM::VST4q32: 3126 case ARM::VST4q8_UPD: 3127 case ARM::VST4q16_UPD: 3128 case ARM::VST4q32_UPD: 3129 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3130 return MCDisassembler::Fail; 3131 break; 3132 default: 3133 break; 3134 } 3135 3136 // Third input register 3137 switch (Inst.getOpcode()) { 3138 case ARM::VST3d8: 3139 case ARM::VST3d16: 3140 case ARM::VST3d32: 3141 case ARM::VST3d8_UPD: 3142 case ARM::VST3d16_UPD: 3143 case ARM::VST3d32_UPD: 3144 case ARM::VST4d8: 3145 case ARM::VST4d16: 3146 case ARM::VST4d32: 3147 case ARM::VST4d8_UPD: 3148 case ARM::VST4d16_UPD: 3149 case ARM::VST4d32_UPD: 3150 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3151 return MCDisassembler::Fail; 3152 break; 3153 case ARM::VST3q8: 3154 case ARM::VST3q16: 3155 case ARM::VST3q32: 3156 case ARM::VST3q8_UPD: 3157 case ARM::VST3q16_UPD: 3158 case ARM::VST3q32_UPD: 3159 case ARM::VST4q8: 3160 case ARM::VST4q16: 3161 case ARM::VST4q32: 3162 case ARM::VST4q8_UPD: 3163 case ARM::VST4q16_UPD: 3164 case ARM::VST4q32_UPD: 3165 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3166 return MCDisassembler::Fail; 3167 break; 3168 default: 3169 break; 3170 } 3171 3172 // Fourth input register 3173 switch (Inst.getOpcode()) { 3174 case ARM::VST4d8: 3175 case ARM::VST4d16: 3176 case ARM::VST4d32: 3177 case ARM::VST4d8_UPD: 3178 case ARM::VST4d16_UPD: 3179 case ARM::VST4d32_UPD: 3180 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3181 return MCDisassembler::Fail; 3182 break; 3183 case ARM::VST4q8: 3184 case ARM::VST4q16: 3185 case ARM::VST4q32: 3186 case ARM::VST4q8_UPD: 3187 case ARM::VST4q16_UPD: 3188 case ARM::VST4q32_UPD: 3189 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 break; 3192 default: 3193 break; 3194 } 3195 3196 return S; 3197 } 3198 3199 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3200 uint64_t Address, const void *Decoder) { 3201 DecodeStatus S = MCDisassembler::Success; 3202 3203 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3204 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3205 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3206 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3207 unsigned align = fieldFromInstruction(Insn, 4, 1); 3208 unsigned size = fieldFromInstruction(Insn, 6, 2); 3209 3210 if (size == 0 && align == 1) 3211 return MCDisassembler::Fail; 3212 align *= (1 << size); 3213 3214 switch (Inst.getOpcode()) { 3215 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3216 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3217 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3218 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3219 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3220 return MCDisassembler::Fail; 3221 break; 3222 default: 3223 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3224 return MCDisassembler::Fail; 3225 break; 3226 } 3227 if (Rm != 0xF) { 3228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 } 3231 3232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3233 return MCDisassembler::Fail; 3234 Inst.addOperand(MCOperand::createImm(align)); 3235 3236 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3237 // variant encodes Rm == 0xf. Anything else is a register offset post- 3238 // increment and we need to add the register operand to the instruction. 3239 if (Rm != 0xD && Rm != 0xF && 3240 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3241 return MCDisassembler::Fail; 3242 3243 return S; 3244 } 3245 3246 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3247 uint64_t Address, const void *Decoder) { 3248 DecodeStatus S = MCDisassembler::Success; 3249 3250 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3251 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3252 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3253 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3254 unsigned align = fieldFromInstruction(Insn, 4, 1); 3255 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3256 align *= 2*size; 3257 3258 switch (Inst.getOpcode()) { 3259 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3260 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3261 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3262 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3263 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3264 return MCDisassembler::Fail; 3265 break; 3266 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3267 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3268 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3269 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3270 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3271 return MCDisassembler::Fail; 3272 break; 3273 default: 3274 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3275 return MCDisassembler::Fail; 3276 break; 3277 } 3278 3279 if (Rm != 0xF) 3280 Inst.addOperand(MCOperand::createImm(0)); 3281 3282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 Inst.addOperand(MCOperand::createImm(align)); 3285 3286 if (Rm != 0xD && Rm != 0xF) { 3287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3288 return MCDisassembler::Fail; 3289 } 3290 3291 return S; 3292 } 3293 3294 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3295 uint64_t Address, const void *Decoder) { 3296 DecodeStatus S = MCDisassembler::Success; 3297 3298 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3299 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3300 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3301 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3302 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3303 3304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3305 return MCDisassembler::Fail; 3306 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3307 return MCDisassembler::Fail; 3308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3309 return MCDisassembler::Fail; 3310 if (Rm != 0xF) { 3311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3312 return MCDisassembler::Fail; 3313 } 3314 3315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3316 return MCDisassembler::Fail; 3317 Inst.addOperand(MCOperand::createImm(0)); 3318 3319 if (Rm == 0xD) 3320 Inst.addOperand(MCOperand::createReg(0)); 3321 else if (Rm != 0xF) { 3322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3323 return MCDisassembler::Fail; 3324 } 3325 3326 return S; 3327 } 3328 3329 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3330 uint64_t Address, const void *Decoder) { 3331 DecodeStatus S = MCDisassembler::Success; 3332 3333 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3334 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3335 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3336 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3337 unsigned size = fieldFromInstruction(Insn, 6, 2); 3338 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3339 unsigned align = fieldFromInstruction(Insn, 4, 1); 3340 3341 if (size == 0x3) { 3342 if (align == 0) 3343 return MCDisassembler::Fail; 3344 align = 16; 3345 } else { 3346 if (size == 2) { 3347 align *= 8; 3348 } else { 3349 size = 1 << size; 3350 align *= 4*size; 3351 } 3352 } 3353 3354 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3357 return MCDisassembler::Fail; 3358 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3359 return MCDisassembler::Fail; 3360 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3361 return MCDisassembler::Fail; 3362 if (Rm != 0xF) { 3363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3364 return MCDisassembler::Fail; 3365 } 3366 3367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3368 return MCDisassembler::Fail; 3369 Inst.addOperand(MCOperand::createImm(align)); 3370 3371 if (Rm == 0xD) 3372 Inst.addOperand(MCOperand::createReg(0)); 3373 else if (Rm != 0xF) { 3374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3375 return MCDisassembler::Fail; 3376 } 3377 3378 return S; 3379 } 3380 3381 static DecodeStatus 3382 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3383 uint64_t Address, const void *Decoder) { 3384 DecodeStatus S = MCDisassembler::Success; 3385 3386 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3387 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3388 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3389 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3390 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3391 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3392 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3393 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3394 3395 if (Q) { 3396 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3397 return MCDisassembler::Fail; 3398 } else { 3399 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3400 return MCDisassembler::Fail; 3401 } 3402 3403 Inst.addOperand(MCOperand::createImm(imm)); 3404 3405 switch (Inst.getOpcode()) { 3406 case ARM::VORRiv4i16: 3407 case ARM::VORRiv2i32: 3408 case ARM::VBICiv4i16: 3409 case ARM::VBICiv2i32: 3410 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3411 return MCDisassembler::Fail; 3412 break; 3413 case ARM::VORRiv8i16: 3414 case ARM::VORRiv4i32: 3415 case ARM::VBICiv8i16: 3416 case ARM::VBICiv4i32: 3417 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3418 return MCDisassembler::Fail; 3419 break; 3420 default: 3421 break; 3422 } 3423 3424 return S; 3425 } 3426 3427 static DecodeStatus 3428 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3429 uint64_t Address, const void *Decoder) { 3430 DecodeStatus S = MCDisassembler::Success; 3431 3432 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3433 fieldFromInstruction(Insn, 13, 3)); 3434 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3435 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3436 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3437 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3438 imm |= cmode << 8; 3439 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3440 3441 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3442 return MCDisassembler::Fail; 3443 3444 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3445 return MCDisassembler::Fail; 3446 3447 Inst.addOperand(MCOperand::createImm(imm)); 3448 3449 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3450 Inst.addOperand(MCOperand::createReg(0)); 3451 Inst.addOperand(MCOperand::createImm(0)); 3452 3453 return S; 3454 } 3455 3456 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3457 uint64_t Address, const void *Decoder) { 3458 DecodeStatus S = MCDisassembler::Success; 3459 3460 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3461 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3462 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3463 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3464 unsigned size = fieldFromInstruction(Insn, 18, 2); 3465 3466 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3467 return MCDisassembler::Fail; 3468 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3469 return MCDisassembler::Fail; 3470 Inst.addOperand(MCOperand::createImm(8 << size)); 3471 3472 return S; 3473 } 3474 3475 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3476 uint64_t Address, const void *Decoder) { 3477 Inst.addOperand(MCOperand::createImm(8 - Val)); 3478 return MCDisassembler::Success; 3479 } 3480 3481 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3482 uint64_t Address, const void *Decoder) { 3483 Inst.addOperand(MCOperand::createImm(16 - Val)); 3484 return MCDisassembler::Success; 3485 } 3486 3487 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3488 uint64_t Address, const void *Decoder) { 3489 Inst.addOperand(MCOperand::createImm(32 - Val)); 3490 return MCDisassembler::Success; 3491 } 3492 3493 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3494 uint64_t Address, const void *Decoder) { 3495 Inst.addOperand(MCOperand::createImm(64 - Val)); 3496 return MCDisassembler::Success; 3497 } 3498 3499 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3500 uint64_t Address, const void *Decoder) { 3501 DecodeStatus S = MCDisassembler::Success; 3502 3503 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3504 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3505 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3506 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3507 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3508 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3509 unsigned op = fieldFromInstruction(Insn, 6, 1); 3510 3511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3512 return MCDisassembler::Fail; 3513 if (op) { 3514 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3515 return MCDisassembler::Fail; // Writeback 3516 } 3517 3518 switch (Inst.getOpcode()) { 3519 case ARM::VTBL2: 3520 case ARM::VTBX2: 3521 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3522 return MCDisassembler::Fail; 3523 break; 3524 default: 3525 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3526 return MCDisassembler::Fail; 3527 } 3528 3529 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3530 return MCDisassembler::Fail; 3531 3532 return S; 3533 } 3534 3535 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3536 uint64_t Address, const void *Decoder) { 3537 DecodeStatus S = MCDisassembler::Success; 3538 3539 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3540 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3541 3542 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3543 return MCDisassembler::Fail; 3544 3545 switch(Inst.getOpcode()) { 3546 default: 3547 return MCDisassembler::Fail; 3548 case ARM::tADR: 3549 break; // tADR does not explicitly represent the PC as an operand. 3550 case ARM::tADDrSPi: 3551 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3552 break; 3553 } 3554 3555 Inst.addOperand(MCOperand::createImm(imm)); 3556 return S; 3557 } 3558 3559 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3560 uint64_t Address, const void *Decoder) { 3561 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3562 true, 2, Inst, Decoder)) 3563 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3564 return MCDisassembler::Success; 3565 } 3566 3567 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3568 uint64_t Address, const void *Decoder) { 3569 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3570 true, 4, Inst, Decoder)) 3571 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3572 return MCDisassembler::Success; 3573 } 3574 3575 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3576 uint64_t Address, const void *Decoder) { 3577 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3578 true, 2, Inst, Decoder)) 3579 Inst.addOperand(MCOperand::createImm(Val << 1)); 3580 return MCDisassembler::Success; 3581 } 3582 3583 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3584 uint64_t Address, const void *Decoder) { 3585 DecodeStatus S = MCDisassembler::Success; 3586 3587 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3588 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3589 3590 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3591 return MCDisassembler::Fail; 3592 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3593 return MCDisassembler::Fail; 3594 3595 return S; 3596 } 3597 3598 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3599 uint64_t Address, const void *Decoder) { 3600 DecodeStatus S = MCDisassembler::Success; 3601 3602 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3603 unsigned imm = fieldFromInstruction(Val, 3, 5); 3604 3605 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 Inst.addOperand(MCOperand::createImm(imm)); 3608 3609 return S; 3610 } 3611 3612 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3613 uint64_t Address, const void *Decoder) { 3614 unsigned imm = Val << 2; 3615 3616 Inst.addOperand(MCOperand::createImm(imm)); 3617 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3618 3619 return MCDisassembler::Success; 3620 } 3621 3622 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3623 uint64_t Address, const void *Decoder) { 3624 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3625 Inst.addOperand(MCOperand::createImm(Val)); 3626 3627 return MCDisassembler::Success; 3628 } 3629 3630 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3631 uint64_t Address, const void *Decoder) { 3632 DecodeStatus S = MCDisassembler::Success; 3633 3634 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3635 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3636 unsigned imm = fieldFromInstruction(Val, 0, 2); 3637 3638 // Thumb stores cannot use PC as dest register. 3639 switch (Inst.getOpcode()) { 3640 case ARM::t2STRHs: 3641 case ARM::t2STRBs: 3642 case ARM::t2STRs: 3643 if (Rn == 15) 3644 return MCDisassembler::Fail; 3645 break; 3646 default: 3647 break; 3648 } 3649 3650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3651 return MCDisassembler::Fail; 3652 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3653 return MCDisassembler::Fail; 3654 Inst.addOperand(MCOperand::createImm(imm)); 3655 3656 return S; 3657 } 3658 3659 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3660 uint64_t Address, const void *Decoder) { 3661 DecodeStatus S = MCDisassembler::Success; 3662 3663 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3664 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3665 3666 const FeatureBitset &featureBits = 3667 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3668 3669 bool hasMP = featureBits[ARM::FeatureMP]; 3670 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3671 3672 if (Rn == 15) { 3673 switch (Inst.getOpcode()) { 3674 case ARM::t2LDRBs: 3675 Inst.setOpcode(ARM::t2LDRBpci); 3676 break; 3677 case ARM::t2LDRHs: 3678 Inst.setOpcode(ARM::t2LDRHpci); 3679 break; 3680 case ARM::t2LDRSHs: 3681 Inst.setOpcode(ARM::t2LDRSHpci); 3682 break; 3683 case ARM::t2LDRSBs: 3684 Inst.setOpcode(ARM::t2LDRSBpci); 3685 break; 3686 case ARM::t2LDRs: 3687 Inst.setOpcode(ARM::t2LDRpci); 3688 break; 3689 case ARM::t2PLDs: 3690 Inst.setOpcode(ARM::t2PLDpci); 3691 break; 3692 case ARM::t2PLIs: 3693 Inst.setOpcode(ARM::t2PLIpci); 3694 break; 3695 default: 3696 return MCDisassembler::Fail; 3697 } 3698 3699 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3700 } 3701 3702 if (Rt == 15) { 3703 switch (Inst.getOpcode()) { 3704 case ARM::t2LDRSHs: 3705 return MCDisassembler::Fail; 3706 case ARM::t2LDRHs: 3707 Inst.setOpcode(ARM::t2PLDWs); 3708 break; 3709 case ARM::t2LDRSBs: 3710 Inst.setOpcode(ARM::t2PLIs); 3711 break; 3712 default: 3713 break; 3714 } 3715 } 3716 3717 switch (Inst.getOpcode()) { 3718 case ARM::t2PLDs: 3719 break; 3720 case ARM::t2PLIs: 3721 if (!hasV7Ops) 3722 return MCDisassembler::Fail; 3723 break; 3724 case ARM::t2PLDWs: 3725 if (!hasV7Ops || !hasMP) 3726 return MCDisassembler::Fail; 3727 break; 3728 default: 3729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 } 3732 3733 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3734 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3735 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3736 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3737 return MCDisassembler::Fail; 3738 3739 return S; 3740 } 3741 3742 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3743 uint64_t Address, const void* Decoder) { 3744 DecodeStatus S = MCDisassembler::Success; 3745 3746 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3747 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3748 unsigned U = fieldFromInstruction(Insn, 9, 1); 3749 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3750 imm |= (U << 8); 3751 imm |= (Rn << 9); 3752 unsigned add = fieldFromInstruction(Insn, 9, 1); 3753 3754 const FeatureBitset &featureBits = 3755 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3756 3757 bool hasMP = featureBits[ARM::FeatureMP]; 3758 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3759 3760 if (Rn == 15) { 3761 switch (Inst.getOpcode()) { 3762 case ARM::t2LDRi8: 3763 Inst.setOpcode(ARM::t2LDRpci); 3764 break; 3765 case ARM::t2LDRBi8: 3766 Inst.setOpcode(ARM::t2LDRBpci); 3767 break; 3768 case ARM::t2LDRSBi8: 3769 Inst.setOpcode(ARM::t2LDRSBpci); 3770 break; 3771 case ARM::t2LDRHi8: 3772 Inst.setOpcode(ARM::t2LDRHpci); 3773 break; 3774 case ARM::t2LDRSHi8: 3775 Inst.setOpcode(ARM::t2LDRSHpci); 3776 break; 3777 case ARM::t2PLDi8: 3778 Inst.setOpcode(ARM::t2PLDpci); 3779 break; 3780 case ARM::t2PLIi8: 3781 Inst.setOpcode(ARM::t2PLIpci); 3782 break; 3783 default: 3784 return MCDisassembler::Fail; 3785 } 3786 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3787 } 3788 3789 if (Rt == 15) { 3790 switch (Inst.getOpcode()) { 3791 case ARM::t2LDRSHi8: 3792 return MCDisassembler::Fail; 3793 case ARM::t2LDRHi8: 3794 if (!add) 3795 Inst.setOpcode(ARM::t2PLDWi8); 3796 break; 3797 case ARM::t2LDRSBi8: 3798 Inst.setOpcode(ARM::t2PLIi8); 3799 break; 3800 default: 3801 break; 3802 } 3803 } 3804 3805 switch (Inst.getOpcode()) { 3806 case ARM::t2PLDi8: 3807 break; 3808 case ARM::t2PLIi8: 3809 if (!hasV7Ops) 3810 return MCDisassembler::Fail; 3811 break; 3812 case ARM::t2PLDWi8: 3813 if (!hasV7Ops || !hasMP) 3814 return MCDisassembler::Fail; 3815 break; 3816 default: 3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 } 3820 3821 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3822 return MCDisassembler::Fail; 3823 return S; 3824 } 3825 3826 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3827 uint64_t Address, const void* Decoder) { 3828 DecodeStatus S = MCDisassembler::Success; 3829 3830 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3831 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3832 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3833 imm |= (Rn << 13); 3834 3835 const FeatureBitset &featureBits = 3836 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3837 3838 bool hasMP = featureBits[ARM::FeatureMP]; 3839 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3840 3841 if (Rn == 15) { 3842 switch (Inst.getOpcode()) { 3843 case ARM::t2LDRi12: 3844 Inst.setOpcode(ARM::t2LDRpci); 3845 break; 3846 case ARM::t2LDRHi12: 3847 Inst.setOpcode(ARM::t2LDRHpci); 3848 break; 3849 case ARM::t2LDRSHi12: 3850 Inst.setOpcode(ARM::t2LDRSHpci); 3851 break; 3852 case ARM::t2LDRBi12: 3853 Inst.setOpcode(ARM::t2LDRBpci); 3854 break; 3855 case ARM::t2LDRSBi12: 3856 Inst.setOpcode(ARM::t2LDRSBpci); 3857 break; 3858 case ARM::t2PLDi12: 3859 Inst.setOpcode(ARM::t2PLDpci); 3860 break; 3861 case ARM::t2PLIi12: 3862 Inst.setOpcode(ARM::t2PLIpci); 3863 break; 3864 default: 3865 return MCDisassembler::Fail; 3866 } 3867 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3868 } 3869 3870 if (Rt == 15) { 3871 switch (Inst.getOpcode()) { 3872 case ARM::t2LDRSHi12: 3873 return MCDisassembler::Fail; 3874 case ARM::t2LDRHi12: 3875 Inst.setOpcode(ARM::t2PLDWi12); 3876 break; 3877 case ARM::t2LDRSBi12: 3878 Inst.setOpcode(ARM::t2PLIi12); 3879 break; 3880 default: 3881 break; 3882 } 3883 } 3884 3885 switch (Inst.getOpcode()) { 3886 case ARM::t2PLDi12: 3887 break; 3888 case ARM::t2PLIi12: 3889 if (!hasV7Ops) 3890 return MCDisassembler::Fail; 3891 break; 3892 case ARM::t2PLDWi12: 3893 if (!hasV7Ops || !hasMP) 3894 return MCDisassembler::Fail; 3895 break; 3896 default: 3897 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3898 return MCDisassembler::Fail; 3899 } 3900 3901 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 return S; 3904 } 3905 3906 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3907 uint64_t Address, const void* Decoder) { 3908 DecodeStatus S = MCDisassembler::Success; 3909 3910 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3911 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3912 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3913 imm |= (Rn << 9); 3914 3915 if (Rn == 15) { 3916 switch (Inst.getOpcode()) { 3917 case ARM::t2LDRT: 3918 Inst.setOpcode(ARM::t2LDRpci); 3919 break; 3920 case ARM::t2LDRBT: 3921 Inst.setOpcode(ARM::t2LDRBpci); 3922 break; 3923 case ARM::t2LDRHT: 3924 Inst.setOpcode(ARM::t2LDRHpci); 3925 break; 3926 case ARM::t2LDRSBT: 3927 Inst.setOpcode(ARM::t2LDRSBpci); 3928 break; 3929 case ARM::t2LDRSHT: 3930 Inst.setOpcode(ARM::t2LDRSHpci); 3931 break; 3932 default: 3933 return MCDisassembler::Fail; 3934 } 3935 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3936 } 3937 3938 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3939 return MCDisassembler::Fail; 3940 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3941 return MCDisassembler::Fail; 3942 return S; 3943 } 3944 3945 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3946 uint64_t Address, const void* Decoder) { 3947 DecodeStatus S = MCDisassembler::Success; 3948 3949 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3950 unsigned U = fieldFromInstruction(Insn, 23, 1); 3951 int imm = fieldFromInstruction(Insn, 0, 12); 3952 3953 const FeatureBitset &featureBits = 3954 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3955 3956 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3957 3958 if (Rt == 15) { 3959 switch (Inst.getOpcode()) { 3960 case ARM::t2LDRBpci: 3961 case ARM::t2LDRHpci: 3962 Inst.setOpcode(ARM::t2PLDpci); 3963 break; 3964 case ARM::t2LDRSBpci: 3965 Inst.setOpcode(ARM::t2PLIpci); 3966 break; 3967 case ARM::t2LDRSHpci: 3968 return MCDisassembler::Fail; 3969 default: 3970 break; 3971 } 3972 } 3973 3974 switch(Inst.getOpcode()) { 3975 case ARM::t2PLDpci: 3976 break; 3977 case ARM::t2PLIpci: 3978 if (!hasV7Ops) 3979 return MCDisassembler::Fail; 3980 break; 3981 default: 3982 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3983 return MCDisassembler::Fail; 3984 } 3985 3986 if (!U) { 3987 // Special case for #-0. 3988 if (imm == 0) 3989 imm = INT32_MIN; 3990 else 3991 imm = -imm; 3992 } 3993 Inst.addOperand(MCOperand::createImm(imm)); 3994 3995 return S; 3996 } 3997 3998 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3999 uint64_t Address, const void *Decoder) { 4000 if (Val == 0) 4001 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4002 else { 4003 int imm = Val & 0xFF; 4004 4005 if (!(Val & 0x100)) imm *= -1; 4006 Inst.addOperand(MCOperand::createImm(imm * 4)); 4007 } 4008 4009 return MCDisassembler::Success; 4010 } 4011 4012 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4013 const void *Decoder) { 4014 if (Val == 0) 4015 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4016 else { 4017 int imm = Val & 0x7F; 4018 4019 if (!(Val & 0x80)) 4020 imm *= -1; 4021 Inst.addOperand(MCOperand::createImm(imm * 4)); 4022 } 4023 4024 return MCDisassembler::Success; 4025 } 4026 4027 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4028 uint64_t Address, const void *Decoder) { 4029 DecodeStatus S = MCDisassembler::Success; 4030 4031 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4032 unsigned imm = fieldFromInstruction(Val, 0, 9); 4033 4034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4035 return MCDisassembler::Fail; 4036 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4037 return MCDisassembler::Fail; 4038 4039 return S; 4040 } 4041 4042 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4043 uint64_t Address, 4044 const void *Decoder) { 4045 DecodeStatus S = MCDisassembler::Success; 4046 4047 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4048 unsigned imm = fieldFromInstruction(Val, 0, 8); 4049 4050 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4051 return MCDisassembler::Fail; 4052 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4053 return MCDisassembler::Fail; 4054 4055 return S; 4056 } 4057 4058 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4059 uint64_t Address, const void *Decoder) { 4060 DecodeStatus S = MCDisassembler::Success; 4061 4062 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4063 unsigned imm = fieldFromInstruction(Val, 0, 8); 4064 4065 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4066 return MCDisassembler::Fail; 4067 4068 Inst.addOperand(MCOperand::createImm(imm)); 4069 4070 return S; 4071 } 4072 4073 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4074 uint64_t Address, const void *Decoder) { 4075 int imm = Val & 0xFF; 4076 if (Val == 0) 4077 imm = INT32_MIN; 4078 else if (!(Val & 0x100)) 4079 imm *= -1; 4080 Inst.addOperand(MCOperand::createImm(imm)); 4081 4082 return MCDisassembler::Success; 4083 } 4084 4085 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4086 uint64_t Address, const void *Decoder) { 4087 DecodeStatus S = MCDisassembler::Success; 4088 4089 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4090 unsigned imm = fieldFromInstruction(Val, 0, 9); 4091 4092 // Thumb stores cannot use PC as dest register. 4093 switch (Inst.getOpcode()) { 4094 case ARM::t2STRT: 4095 case ARM::t2STRBT: 4096 case ARM::t2STRHT: 4097 case ARM::t2STRi8: 4098 case ARM::t2STRHi8: 4099 case ARM::t2STRBi8: 4100 if (Rn == 15) 4101 return MCDisassembler::Fail; 4102 break; 4103 default: 4104 break; 4105 } 4106 4107 // Some instructions always use an additive offset. 4108 switch (Inst.getOpcode()) { 4109 case ARM::t2LDRT: 4110 case ARM::t2LDRBT: 4111 case ARM::t2LDRHT: 4112 case ARM::t2LDRSBT: 4113 case ARM::t2LDRSHT: 4114 case ARM::t2STRT: 4115 case ARM::t2STRBT: 4116 case ARM::t2STRHT: 4117 imm |= 0x100; 4118 break; 4119 default: 4120 break; 4121 } 4122 4123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4124 return MCDisassembler::Fail; 4125 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4126 return MCDisassembler::Fail; 4127 4128 return S; 4129 } 4130 4131 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4132 uint64_t Address, const void *Decoder) { 4133 DecodeStatus S = MCDisassembler::Success; 4134 4135 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4136 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4137 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4138 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4139 addr |= Rn << 9; 4140 unsigned load = fieldFromInstruction(Insn, 20, 1); 4141 4142 if (Rn == 15) { 4143 switch (Inst.getOpcode()) { 4144 case ARM::t2LDR_PRE: 4145 case ARM::t2LDR_POST: 4146 Inst.setOpcode(ARM::t2LDRpci); 4147 break; 4148 case ARM::t2LDRB_PRE: 4149 case ARM::t2LDRB_POST: 4150 Inst.setOpcode(ARM::t2LDRBpci); 4151 break; 4152 case ARM::t2LDRH_PRE: 4153 case ARM::t2LDRH_POST: 4154 Inst.setOpcode(ARM::t2LDRHpci); 4155 break; 4156 case ARM::t2LDRSB_PRE: 4157 case ARM::t2LDRSB_POST: 4158 if (Rt == 15) 4159 Inst.setOpcode(ARM::t2PLIpci); 4160 else 4161 Inst.setOpcode(ARM::t2LDRSBpci); 4162 break; 4163 case ARM::t2LDRSH_PRE: 4164 case ARM::t2LDRSH_POST: 4165 Inst.setOpcode(ARM::t2LDRSHpci); 4166 break; 4167 default: 4168 return MCDisassembler::Fail; 4169 } 4170 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4171 } 4172 4173 if (!load) { 4174 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4175 return MCDisassembler::Fail; 4176 } 4177 4178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4179 return MCDisassembler::Fail; 4180 4181 if (load) { 4182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4183 return MCDisassembler::Fail; 4184 } 4185 4186 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4187 return MCDisassembler::Fail; 4188 4189 return S; 4190 } 4191 4192 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4193 uint64_t Address, const void *Decoder) { 4194 DecodeStatus S = MCDisassembler::Success; 4195 4196 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4197 unsigned imm = fieldFromInstruction(Val, 0, 12); 4198 4199 // Thumb stores cannot use PC as dest register. 4200 switch (Inst.getOpcode()) { 4201 case ARM::t2STRi12: 4202 case ARM::t2STRBi12: 4203 case ARM::t2STRHi12: 4204 if (Rn == 15) 4205 return MCDisassembler::Fail; 4206 break; 4207 default: 4208 break; 4209 } 4210 4211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4212 return MCDisassembler::Fail; 4213 Inst.addOperand(MCOperand::createImm(imm)); 4214 4215 return S; 4216 } 4217 4218 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4219 uint64_t Address, const void *Decoder) { 4220 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4221 4222 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4223 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4224 Inst.addOperand(MCOperand::createImm(imm)); 4225 4226 return MCDisassembler::Success; 4227 } 4228 4229 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4230 uint64_t Address, const void *Decoder) { 4231 DecodeStatus S = MCDisassembler::Success; 4232 4233 if (Inst.getOpcode() == ARM::tADDrSP) { 4234 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4235 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4236 4237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4241 return MCDisassembler::Fail; 4242 } else if (Inst.getOpcode() == ARM::tADDspr) { 4243 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4244 4245 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4246 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4248 return MCDisassembler::Fail; 4249 } 4250 4251 return S; 4252 } 4253 4254 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4255 uint64_t Address, const void *Decoder) { 4256 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4257 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4258 4259 Inst.addOperand(MCOperand::createImm(imod)); 4260 Inst.addOperand(MCOperand::createImm(flags)); 4261 4262 return MCDisassembler::Success; 4263 } 4264 4265 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4266 uint64_t Address, const void *Decoder) { 4267 DecodeStatus S = MCDisassembler::Success; 4268 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4269 unsigned add = fieldFromInstruction(Insn, 4, 1); 4270 4271 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4272 return MCDisassembler::Fail; 4273 Inst.addOperand(MCOperand::createImm(add)); 4274 4275 return S; 4276 } 4277 4278 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4279 uint64_t Address, const void *Decoder) { 4280 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4281 // Note only one trailing zero not two. Also the J1 and J2 values are from 4282 // the encoded instruction. So here change to I1 and I2 values via: 4283 // I1 = NOT(J1 EOR S); 4284 // I2 = NOT(J2 EOR S); 4285 // and build the imm32 with two trailing zeros as documented: 4286 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4287 unsigned S = (Val >> 23) & 1; 4288 unsigned J1 = (Val >> 22) & 1; 4289 unsigned J2 = (Val >> 21) & 1; 4290 unsigned I1 = !(J1 ^ S); 4291 unsigned I2 = !(J2 ^ S); 4292 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4293 int imm32 = SignExtend32<25>(tmp << 1); 4294 4295 if (!tryAddingSymbolicOperand(Address, 4296 (Address & ~2u) + imm32 + 4, 4297 true, 4, Inst, Decoder)) 4298 Inst.addOperand(MCOperand::createImm(imm32)); 4299 return MCDisassembler::Success; 4300 } 4301 4302 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4303 uint64_t Address, const void *Decoder) { 4304 if (Val == 0xA || Val == 0xB) 4305 return MCDisassembler::Fail; 4306 4307 const FeatureBitset &featureBits = 4308 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4309 4310 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4311 return MCDisassembler::Fail; 4312 4313 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4314 // decode as VFP/MVE instructions. 4315 if (featureBits[ARM::HasV8_1MMainlineOps] && 4316 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4317 (Val & 0xE) == 0xE)) 4318 return MCDisassembler::Fail; 4319 4320 Inst.addOperand(MCOperand::createImm(Val)); 4321 return MCDisassembler::Success; 4322 } 4323 4324 static DecodeStatus 4325 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4326 uint64_t Address, const void *Decoder) { 4327 DecodeStatus S = MCDisassembler::Success; 4328 4329 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4330 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4331 4332 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4334 return MCDisassembler::Fail; 4335 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4336 return MCDisassembler::Fail; 4337 return S; 4338 } 4339 4340 static DecodeStatus 4341 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4342 uint64_t Address, const void *Decoder) { 4343 DecodeStatus S = MCDisassembler::Success; 4344 4345 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4346 if (pred == 0xE || pred == 0xF) { 4347 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4348 switch (opc) { 4349 default: 4350 return MCDisassembler::Fail; 4351 case 0xf3bf8f4: 4352 Inst.setOpcode(ARM::t2DSB); 4353 break; 4354 case 0xf3bf8f5: 4355 Inst.setOpcode(ARM::t2DMB); 4356 break; 4357 case 0xf3bf8f6: 4358 Inst.setOpcode(ARM::t2ISB); 4359 break; 4360 } 4361 4362 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4363 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4364 } 4365 4366 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4367 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4368 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4369 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4370 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4371 4372 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4373 return MCDisassembler::Fail; 4374 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4375 return MCDisassembler::Fail; 4376 4377 return S; 4378 } 4379 4380 // Decode a shifted immediate operand. These basically consist 4381 // of an 8-bit value, and a 4-bit directive that specifies either 4382 // a splat operation or a rotation. 4383 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4384 uint64_t Address, const void *Decoder) { 4385 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4386 if (ctrl == 0) { 4387 unsigned byte = fieldFromInstruction(Val, 8, 2); 4388 unsigned imm = fieldFromInstruction(Val, 0, 8); 4389 switch (byte) { 4390 case 0: 4391 Inst.addOperand(MCOperand::createImm(imm)); 4392 break; 4393 case 1: 4394 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4395 break; 4396 case 2: 4397 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4398 break; 4399 case 3: 4400 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4401 (imm << 8) | imm)); 4402 break; 4403 } 4404 } else { 4405 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4406 unsigned rot = fieldFromInstruction(Val, 7, 5); 4407 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4408 Inst.addOperand(MCOperand::createImm(imm)); 4409 } 4410 4411 return MCDisassembler::Success; 4412 } 4413 4414 static DecodeStatus 4415 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4416 uint64_t Address, const void *Decoder) { 4417 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4418 true, 2, Inst, Decoder)) 4419 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4420 return MCDisassembler::Success; 4421 } 4422 4423 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4424 uint64_t Address, 4425 const void *Decoder) { 4426 // Val is passed in as S:J1:J2:imm10:imm11 4427 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4428 // the encoded instruction. So here change to I1 and I2 values via: 4429 // I1 = NOT(J1 EOR S); 4430 // I2 = NOT(J2 EOR S); 4431 // and build the imm32 with one trailing zero as documented: 4432 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4433 unsigned S = (Val >> 23) & 1; 4434 unsigned J1 = (Val >> 22) & 1; 4435 unsigned J2 = (Val >> 21) & 1; 4436 unsigned I1 = !(J1 ^ S); 4437 unsigned I2 = !(J2 ^ S); 4438 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4439 int imm32 = SignExtend32<25>(tmp << 1); 4440 4441 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4442 true, 4, Inst, Decoder)) 4443 Inst.addOperand(MCOperand::createImm(imm32)); 4444 return MCDisassembler::Success; 4445 } 4446 4447 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4448 uint64_t Address, const void *Decoder) { 4449 if (Val & ~0xf) 4450 return MCDisassembler::Fail; 4451 4452 Inst.addOperand(MCOperand::createImm(Val)); 4453 return MCDisassembler::Success; 4454 } 4455 4456 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4457 uint64_t Address, const void *Decoder) { 4458 if (Val & ~0xf) 4459 return MCDisassembler::Fail; 4460 4461 Inst.addOperand(MCOperand::createImm(Val)); 4462 return MCDisassembler::Success; 4463 } 4464 4465 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4466 uint64_t Address, const void *Decoder) { 4467 DecodeStatus S = MCDisassembler::Success; 4468 const FeatureBitset &FeatureBits = 4469 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4470 4471 if (FeatureBits[ARM::FeatureMClass]) { 4472 unsigned ValLow = Val & 0xff; 4473 4474 // Validate the SYSm value first. 4475 switch (ValLow) { 4476 case 0: // apsr 4477 case 1: // iapsr 4478 case 2: // eapsr 4479 case 3: // xpsr 4480 case 5: // ipsr 4481 case 6: // epsr 4482 case 7: // iepsr 4483 case 8: // msp 4484 case 9: // psp 4485 case 16: // primask 4486 case 20: // control 4487 break; 4488 case 17: // basepri 4489 case 18: // basepri_max 4490 case 19: // faultmask 4491 if (!(FeatureBits[ARM::HasV7Ops])) 4492 // Values basepri, basepri_max and faultmask are only valid for v7m. 4493 return MCDisassembler::Fail; 4494 break; 4495 case 0x8a: // msplim_ns 4496 case 0x8b: // psplim_ns 4497 case 0x91: // basepri_ns 4498 case 0x93: // faultmask_ns 4499 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4500 return MCDisassembler::Fail; 4501 LLVM_FALLTHROUGH; 4502 case 10: // msplim 4503 case 11: // psplim 4504 case 0x88: // msp_ns 4505 case 0x89: // psp_ns 4506 case 0x90: // primask_ns 4507 case 0x94: // control_ns 4508 case 0x98: // sp_ns 4509 if (!(FeatureBits[ARM::Feature8MSecExt])) 4510 return MCDisassembler::Fail; 4511 break; 4512 default: 4513 // Architecturally defined as unpredictable 4514 S = MCDisassembler::SoftFail; 4515 break; 4516 } 4517 4518 if (Inst.getOpcode() == ARM::t2MSR_M) { 4519 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4520 if (!(FeatureBits[ARM::HasV7Ops])) { 4521 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4522 // unpredictable. 4523 if (Mask != 2) 4524 S = MCDisassembler::SoftFail; 4525 } 4526 else { 4527 // The ARMv7-M architecture stores an additional 2-bit mask value in 4528 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4529 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4530 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4531 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4532 // only if the processor includes the DSP extension. 4533 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4534 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4535 S = MCDisassembler::SoftFail; 4536 } 4537 } 4538 } else { 4539 // A/R class 4540 if (Val == 0) 4541 return MCDisassembler::Fail; 4542 } 4543 Inst.addOperand(MCOperand::createImm(Val)); 4544 return S; 4545 } 4546 4547 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4548 uint64_t Address, const void *Decoder) { 4549 unsigned R = fieldFromInstruction(Val, 5, 1); 4550 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4551 4552 // The table of encodings for these banked registers comes from B9.2.3 of the 4553 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4554 // neater. So by fiat, these values are UNPREDICTABLE: 4555 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4556 return MCDisassembler::Fail; 4557 4558 Inst.addOperand(MCOperand::createImm(Val)); 4559 return MCDisassembler::Success; 4560 } 4561 4562 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4563 uint64_t Address, const void *Decoder) { 4564 DecodeStatus S = MCDisassembler::Success; 4565 4566 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4567 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4568 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4569 4570 if (Rn == 0xF) 4571 S = MCDisassembler::SoftFail; 4572 4573 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4574 return MCDisassembler::Fail; 4575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4576 return MCDisassembler::Fail; 4577 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4578 return MCDisassembler::Fail; 4579 4580 return S; 4581 } 4582 4583 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4584 uint64_t Address, 4585 const void *Decoder) { 4586 DecodeStatus S = MCDisassembler::Success; 4587 4588 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4589 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4590 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4591 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4592 4593 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4594 return MCDisassembler::Fail; 4595 4596 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4597 S = MCDisassembler::SoftFail; 4598 4599 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4600 return MCDisassembler::Fail; 4601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4602 return MCDisassembler::Fail; 4603 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4604 return MCDisassembler::Fail; 4605 4606 return S; 4607 } 4608 4609 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4610 uint64_t Address, const void *Decoder) { 4611 DecodeStatus S = MCDisassembler::Success; 4612 4613 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4614 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4615 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4616 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4617 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4618 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4619 4620 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4621 4622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4623 return MCDisassembler::Fail; 4624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4625 return MCDisassembler::Fail; 4626 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4627 return MCDisassembler::Fail; 4628 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4629 return MCDisassembler::Fail; 4630 4631 return S; 4632 } 4633 4634 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4635 uint64_t Address, const void *Decoder) { 4636 DecodeStatus S = MCDisassembler::Success; 4637 4638 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4639 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4640 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4641 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4642 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4643 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4644 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4645 4646 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4647 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4648 4649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4650 return MCDisassembler::Fail; 4651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4652 return MCDisassembler::Fail; 4653 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4654 return MCDisassembler::Fail; 4655 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4656 return MCDisassembler::Fail; 4657 4658 return S; 4659 } 4660 4661 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4662 uint64_t Address, const void *Decoder) { 4663 DecodeStatus S = MCDisassembler::Success; 4664 4665 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4666 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4667 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4668 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4669 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4670 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4671 4672 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4673 4674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4675 return MCDisassembler::Fail; 4676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4677 return MCDisassembler::Fail; 4678 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 4683 return S; 4684 } 4685 4686 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4687 uint64_t Address, const void *Decoder) { 4688 DecodeStatus S = MCDisassembler::Success; 4689 4690 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4691 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4692 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4693 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4694 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4695 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4696 4697 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4698 4699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4700 return MCDisassembler::Fail; 4701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4702 return MCDisassembler::Fail; 4703 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4704 return MCDisassembler::Fail; 4705 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4706 return MCDisassembler::Fail; 4707 4708 return S; 4709 } 4710 4711 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4712 uint64_t Address, const void *Decoder) { 4713 DecodeStatus S = MCDisassembler::Success; 4714 4715 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4716 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4717 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4718 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4719 unsigned size = fieldFromInstruction(Insn, 10, 2); 4720 4721 unsigned align = 0; 4722 unsigned index = 0; 4723 switch (size) { 4724 default: 4725 return MCDisassembler::Fail; 4726 case 0: 4727 if (fieldFromInstruction(Insn, 4, 1)) 4728 return MCDisassembler::Fail; // UNDEFINED 4729 index = fieldFromInstruction(Insn, 5, 3); 4730 break; 4731 case 1: 4732 if (fieldFromInstruction(Insn, 5, 1)) 4733 return MCDisassembler::Fail; // UNDEFINED 4734 index = fieldFromInstruction(Insn, 6, 2); 4735 if (fieldFromInstruction(Insn, 4, 1)) 4736 align = 2; 4737 break; 4738 case 2: 4739 if (fieldFromInstruction(Insn, 6, 1)) 4740 return MCDisassembler::Fail; // UNDEFINED 4741 index = fieldFromInstruction(Insn, 7, 1); 4742 4743 switch (fieldFromInstruction(Insn, 4, 2)) { 4744 case 0 : 4745 align = 0; break; 4746 case 3: 4747 align = 4; break; 4748 default: 4749 return MCDisassembler::Fail; 4750 } 4751 break; 4752 } 4753 4754 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4755 return MCDisassembler::Fail; 4756 if (Rm != 0xF) { // Writeback 4757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4758 return MCDisassembler::Fail; 4759 } 4760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4761 return MCDisassembler::Fail; 4762 Inst.addOperand(MCOperand::createImm(align)); 4763 if (Rm != 0xF) { 4764 if (Rm != 0xD) { 4765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4766 return MCDisassembler::Fail; 4767 } else 4768 Inst.addOperand(MCOperand::createReg(0)); 4769 } 4770 4771 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4772 return MCDisassembler::Fail; 4773 Inst.addOperand(MCOperand::createImm(index)); 4774 4775 return S; 4776 } 4777 4778 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4779 uint64_t Address, const void *Decoder) { 4780 DecodeStatus S = MCDisassembler::Success; 4781 4782 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4783 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4784 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4785 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4786 unsigned size = fieldFromInstruction(Insn, 10, 2); 4787 4788 unsigned align = 0; 4789 unsigned index = 0; 4790 switch (size) { 4791 default: 4792 return MCDisassembler::Fail; 4793 case 0: 4794 if (fieldFromInstruction(Insn, 4, 1)) 4795 return MCDisassembler::Fail; // UNDEFINED 4796 index = fieldFromInstruction(Insn, 5, 3); 4797 break; 4798 case 1: 4799 if (fieldFromInstruction(Insn, 5, 1)) 4800 return MCDisassembler::Fail; // UNDEFINED 4801 index = fieldFromInstruction(Insn, 6, 2); 4802 if (fieldFromInstruction(Insn, 4, 1)) 4803 align = 2; 4804 break; 4805 case 2: 4806 if (fieldFromInstruction(Insn, 6, 1)) 4807 return MCDisassembler::Fail; // UNDEFINED 4808 index = fieldFromInstruction(Insn, 7, 1); 4809 4810 switch (fieldFromInstruction(Insn, 4, 2)) { 4811 case 0: 4812 align = 0; break; 4813 case 3: 4814 align = 4; break; 4815 default: 4816 return MCDisassembler::Fail; 4817 } 4818 break; 4819 } 4820 4821 if (Rm != 0xF) { // Writeback 4822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4823 return MCDisassembler::Fail; 4824 } 4825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4826 return MCDisassembler::Fail; 4827 Inst.addOperand(MCOperand::createImm(align)); 4828 if (Rm != 0xF) { 4829 if (Rm != 0xD) { 4830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4831 return MCDisassembler::Fail; 4832 } else 4833 Inst.addOperand(MCOperand::createReg(0)); 4834 } 4835 4836 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4837 return MCDisassembler::Fail; 4838 Inst.addOperand(MCOperand::createImm(index)); 4839 4840 return S; 4841 } 4842 4843 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4844 uint64_t Address, const void *Decoder) { 4845 DecodeStatus S = MCDisassembler::Success; 4846 4847 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4848 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4849 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4850 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4851 unsigned size = fieldFromInstruction(Insn, 10, 2); 4852 4853 unsigned align = 0; 4854 unsigned index = 0; 4855 unsigned inc = 1; 4856 switch (size) { 4857 default: 4858 return MCDisassembler::Fail; 4859 case 0: 4860 index = fieldFromInstruction(Insn, 5, 3); 4861 if (fieldFromInstruction(Insn, 4, 1)) 4862 align = 2; 4863 break; 4864 case 1: 4865 index = fieldFromInstruction(Insn, 6, 2); 4866 if (fieldFromInstruction(Insn, 4, 1)) 4867 align = 4; 4868 if (fieldFromInstruction(Insn, 5, 1)) 4869 inc = 2; 4870 break; 4871 case 2: 4872 if (fieldFromInstruction(Insn, 5, 1)) 4873 return MCDisassembler::Fail; // UNDEFINED 4874 index = fieldFromInstruction(Insn, 7, 1); 4875 if (fieldFromInstruction(Insn, 4, 1) != 0) 4876 align = 8; 4877 if (fieldFromInstruction(Insn, 6, 1)) 4878 inc = 2; 4879 break; 4880 } 4881 4882 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4883 return MCDisassembler::Fail; 4884 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4885 return MCDisassembler::Fail; 4886 if (Rm != 0xF) { // Writeback 4887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4888 return MCDisassembler::Fail; 4889 } 4890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4891 return MCDisassembler::Fail; 4892 Inst.addOperand(MCOperand::createImm(align)); 4893 if (Rm != 0xF) { 4894 if (Rm != 0xD) { 4895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4896 return MCDisassembler::Fail; 4897 } else 4898 Inst.addOperand(MCOperand::createReg(0)); 4899 } 4900 4901 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4902 return MCDisassembler::Fail; 4903 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4904 return MCDisassembler::Fail; 4905 Inst.addOperand(MCOperand::createImm(index)); 4906 4907 return S; 4908 } 4909 4910 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4911 uint64_t Address, const void *Decoder) { 4912 DecodeStatus S = MCDisassembler::Success; 4913 4914 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4915 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4916 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4917 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4918 unsigned size = fieldFromInstruction(Insn, 10, 2); 4919 4920 unsigned align = 0; 4921 unsigned index = 0; 4922 unsigned inc = 1; 4923 switch (size) { 4924 default: 4925 return MCDisassembler::Fail; 4926 case 0: 4927 index = fieldFromInstruction(Insn, 5, 3); 4928 if (fieldFromInstruction(Insn, 4, 1)) 4929 align = 2; 4930 break; 4931 case 1: 4932 index = fieldFromInstruction(Insn, 6, 2); 4933 if (fieldFromInstruction(Insn, 4, 1)) 4934 align = 4; 4935 if (fieldFromInstruction(Insn, 5, 1)) 4936 inc = 2; 4937 break; 4938 case 2: 4939 if (fieldFromInstruction(Insn, 5, 1)) 4940 return MCDisassembler::Fail; // UNDEFINED 4941 index = fieldFromInstruction(Insn, 7, 1); 4942 if (fieldFromInstruction(Insn, 4, 1) != 0) 4943 align = 8; 4944 if (fieldFromInstruction(Insn, 6, 1)) 4945 inc = 2; 4946 break; 4947 } 4948 4949 if (Rm != 0xF) { // Writeback 4950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4951 return MCDisassembler::Fail; 4952 } 4953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4954 return MCDisassembler::Fail; 4955 Inst.addOperand(MCOperand::createImm(align)); 4956 if (Rm != 0xF) { 4957 if (Rm != 0xD) { 4958 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4959 return MCDisassembler::Fail; 4960 } else 4961 Inst.addOperand(MCOperand::createReg(0)); 4962 } 4963 4964 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4965 return MCDisassembler::Fail; 4966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4967 return MCDisassembler::Fail; 4968 Inst.addOperand(MCOperand::createImm(index)); 4969 4970 return S; 4971 } 4972 4973 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4974 uint64_t Address, const void *Decoder) { 4975 DecodeStatus S = MCDisassembler::Success; 4976 4977 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4978 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4979 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4980 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4981 unsigned size = fieldFromInstruction(Insn, 10, 2); 4982 4983 unsigned align = 0; 4984 unsigned index = 0; 4985 unsigned inc = 1; 4986 switch (size) { 4987 default: 4988 return MCDisassembler::Fail; 4989 case 0: 4990 if (fieldFromInstruction(Insn, 4, 1)) 4991 return MCDisassembler::Fail; // UNDEFINED 4992 index = fieldFromInstruction(Insn, 5, 3); 4993 break; 4994 case 1: 4995 if (fieldFromInstruction(Insn, 4, 1)) 4996 return MCDisassembler::Fail; // UNDEFINED 4997 index = fieldFromInstruction(Insn, 6, 2); 4998 if (fieldFromInstruction(Insn, 5, 1)) 4999 inc = 2; 5000 break; 5001 case 2: 5002 if (fieldFromInstruction(Insn, 4, 2)) 5003 return MCDisassembler::Fail; // UNDEFINED 5004 index = fieldFromInstruction(Insn, 7, 1); 5005 if (fieldFromInstruction(Insn, 6, 1)) 5006 inc = 2; 5007 break; 5008 } 5009 5010 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5011 return MCDisassembler::Fail; 5012 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5013 return MCDisassembler::Fail; 5014 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5015 return MCDisassembler::Fail; 5016 5017 if (Rm != 0xF) { // Writeback 5018 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5019 return MCDisassembler::Fail; 5020 } 5021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5022 return MCDisassembler::Fail; 5023 Inst.addOperand(MCOperand::createImm(align)); 5024 if (Rm != 0xF) { 5025 if (Rm != 0xD) { 5026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5027 return MCDisassembler::Fail; 5028 } else 5029 Inst.addOperand(MCOperand::createReg(0)); 5030 } 5031 5032 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5033 return MCDisassembler::Fail; 5034 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5035 return MCDisassembler::Fail; 5036 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5037 return MCDisassembler::Fail; 5038 Inst.addOperand(MCOperand::createImm(index)); 5039 5040 return S; 5041 } 5042 5043 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5044 uint64_t Address, const void *Decoder) { 5045 DecodeStatus S = MCDisassembler::Success; 5046 5047 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5048 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5049 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5050 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5051 unsigned size = fieldFromInstruction(Insn, 10, 2); 5052 5053 unsigned align = 0; 5054 unsigned index = 0; 5055 unsigned inc = 1; 5056 switch (size) { 5057 default: 5058 return MCDisassembler::Fail; 5059 case 0: 5060 if (fieldFromInstruction(Insn, 4, 1)) 5061 return MCDisassembler::Fail; // UNDEFINED 5062 index = fieldFromInstruction(Insn, 5, 3); 5063 break; 5064 case 1: 5065 if (fieldFromInstruction(Insn, 4, 1)) 5066 return MCDisassembler::Fail; // UNDEFINED 5067 index = fieldFromInstruction(Insn, 6, 2); 5068 if (fieldFromInstruction(Insn, 5, 1)) 5069 inc = 2; 5070 break; 5071 case 2: 5072 if (fieldFromInstruction(Insn, 4, 2)) 5073 return MCDisassembler::Fail; // UNDEFINED 5074 index = fieldFromInstruction(Insn, 7, 1); 5075 if (fieldFromInstruction(Insn, 6, 1)) 5076 inc = 2; 5077 break; 5078 } 5079 5080 if (Rm != 0xF) { // Writeback 5081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5082 return MCDisassembler::Fail; 5083 } 5084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5085 return MCDisassembler::Fail; 5086 Inst.addOperand(MCOperand::createImm(align)); 5087 if (Rm != 0xF) { 5088 if (Rm != 0xD) { 5089 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5090 return MCDisassembler::Fail; 5091 } else 5092 Inst.addOperand(MCOperand::createReg(0)); 5093 } 5094 5095 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5096 return MCDisassembler::Fail; 5097 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5098 return MCDisassembler::Fail; 5099 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5100 return MCDisassembler::Fail; 5101 Inst.addOperand(MCOperand::createImm(index)); 5102 5103 return S; 5104 } 5105 5106 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5107 uint64_t Address, const void *Decoder) { 5108 DecodeStatus S = MCDisassembler::Success; 5109 5110 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5111 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5112 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5113 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5114 unsigned size = fieldFromInstruction(Insn, 10, 2); 5115 5116 unsigned align = 0; 5117 unsigned index = 0; 5118 unsigned inc = 1; 5119 switch (size) { 5120 default: 5121 return MCDisassembler::Fail; 5122 case 0: 5123 if (fieldFromInstruction(Insn, 4, 1)) 5124 align = 4; 5125 index = fieldFromInstruction(Insn, 5, 3); 5126 break; 5127 case 1: 5128 if (fieldFromInstruction(Insn, 4, 1)) 5129 align = 8; 5130 index = fieldFromInstruction(Insn, 6, 2); 5131 if (fieldFromInstruction(Insn, 5, 1)) 5132 inc = 2; 5133 break; 5134 case 2: 5135 switch (fieldFromInstruction(Insn, 4, 2)) { 5136 case 0: 5137 align = 0; break; 5138 case 3: 5139 return MCDisassembler::Fail; 5140 default: 5141 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5142 } 5143 5144 index = fieldFromInstruction(Insn, 7, 1); 5145 if (fieldFromInstruction(Insn, 6, 1)) 5146 inc = 2; 5147 break; 5148 } 5149 5150 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5151 return MCDisassembler::Fail; 5152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5153 return MCDisassembler::Fail; 5154 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5155 return MCDisassembler::Fail; 5156 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5157 return MCDisassembler::Fail; 5158 5159 if (Rm != 0xF) { // Writeback 5160 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5161 return MCDisassembler::Fail; 5162 } 5163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5164 return MCDisassembler::Fail; 5165 Inst.addOperand(MCOperand::createImm(align)); 5166 if (Rm != 0xF) { 5167 if (Rm != 0xD) { 5168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5169 return MCDisassembler::Fail; 5170 } else 5171 Inst.addOperand(MCOperand::createReg(0)); 5172 } 5173 5174 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5175 return MCDisassembler::Fail; 5176 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5177 return MCDisassembler::Fail; 5178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5179 return MCDisassembler::Fail; 5180 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5181 return MCDisassembler::Fail; 5182 Inst.addOperand(MCOperand::createImm(index)); 5183 5184 return S; 5185 } 5186 5187 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5188 uint64_t Address, const void *Decoder) { 5189 DecodeStatus S = MCDisassembler::Success; 5190 5191 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5192 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5193 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5194 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5195 unsigned size = fieldFromInstruction(Insn, 10, 2); 5196 5197 unsigned align = 0; 5198 unsigned index = 0; 5199 unsigned inc = 1; 5200 switch (size) { 5201 default: 5202 return MCDisassembler::Fail; 5203 case 0: 5204 if (fieldFromInstruction(Insn, 4, 1)) 5205 align = 4; 5206 index = fieldFromInstruction(Insn, 5, 3); 5207 break; 5208 case 1: 5209 if (fieldFromInstruction(Insn, 4, 1)) 5210 align = 8; 5211 index = fieldFromInstruction(Insn, 6, 2); 5212 if (fieldFromInstruction(Insn, 5, 1)) 5213 inc = 2; 5214 break; 5215 case 2: 5216 switch (fieldFromInstruction(Insn, 4, 2)) { 5217 case 0: 5218 align = 0; break; 5219 case 3: 5220 return MCDisassembler::Fail; 5221 default: 5222 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5223 } 5224 5225 index = fieldFromInstruction(Insn, 7, 1); 5226 if (fieldFromInstruction(Insn, 6, 1)) 5227 inc = 2; 5228 break; 5229 } 5230 5231 if (Rm != 0xF) { // Writeback 5232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5233 return MCDisassembler::Fail; 5234 } 5235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5236 return MCDisassembler::Fail; 5237 Inst.addOperand(MCOperand::createImm(align)); 5238 if (Rm != 0xF) { 5239 if (Rm != 0xD) { 5240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5241 return MCDisassembler::Fail; 5242 } else 5243 Inst.addOperand(MCOperand::createReg(0)); 5244 } 5245 5246 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5247 return MCDisassembler::Fail; 5248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5249 return MCDisassembler::Fail; 5250 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5251 return MCDisassembler::Fail; 5252 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5253 return MCDisassembler::Fail; 5254 Inst.addOperand(MCOperand::createImm(index)); 5255 5256 return S; 5257 } 5258 5259 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5260 uint64_t Address, const void *Decoder) { 5261 DecodeStatus S = MCDisassembler::Success; 5262 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5263 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5264 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5265 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5266 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5267 5268 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5269 S = MCDisassembler::SoftFail; 5270 5271 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5272 return MCDisassembler::Fail; 5273 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5274 return MCDisassembler::Fail; 5275 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5276 return MCDisassembler::Fail; 5277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5278 return MCDisassembler::Fail; 5279 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5280 return MCDisassembler::Fail; 5281 5282 return S; 5283 } 5284 5285 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5286 uint64_t Address, const void *Decoder) { 5287 DecodeStatus S = MCDisassembler::Success; 5288 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5289 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5290 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5291 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5292 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5293 5294 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5295 S = MCDisassembler::SoftFail; 5296 5297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5298 return MCDisassembler::Fail; 5299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5300 return MCDisassembler::Fail; 5301 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5302 return MCDisassembler::Fail; 5303 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5304 return MCDisassembler::Fail; 5305 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5306 return MCDisassembler::Fail; 5307 5308 return S; 5309 } 5310 5311 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5312 uint64_t Address, const void *Decoder) { 5313 DecodeStatus S = MCDisassembler::Success; 5314 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5315 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5316 5317 if (pred == 0xF) { 5318 pred = 0xE; 5319 S = MCDisassembler::SoftFail; 5320 } 5321 5322 if (mask == 0x0) 5323 return MCDisassembler::Fail; 5324 5325 // IT masks are encoded as a sequence of replacement low-order bits 5326 // for the condition code. So if the low bit of the starting 5327 // condition code is 1, then we have to flip all the bits above the 5328 // terminating bit (which is the lowest 1 bit). 5329 if (pred & 1) { 5330 unsigned LowBit = mask & -mask; 5331 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5332 mask ^= BitsAboveLowBit; 5333 } 5334 5335 Inst.addOperand(MCOperand::createImm(pred)); 5336 Inst.addOperand(MCOperand::createImm(mask)); 5337 return S; 5338 } 5339 5340 static DecodeStatus 5341 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5342 uint64_t Address, const void *Decoder) { 5343 DecodeStatus S = MCDisassembler::Success; 5344 5345 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5346 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5347 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5348 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5349 unsigned W = fieldFromInstruction(Insn, 21, 1); 5350 unsigned U = fieldFromInstruction(Insn, 23, 1); 5351 unsigned P = fieldFromInstruction(Insn, 24, 1); 5352 bool writeback = (W == 1) | (P == 0); 5353 5354 addr |= (U << 8) | (Rn << 9); 5355 5356 if (writeback && (Rn == Rt || Rn == Rt2)) 5357 Check(S, MCDisassembler::SoftFail); 5358 if (Rt == Rt2) 5359 Check(S, MCDisassembler::SoftFail); 5360 5361 // Rt 5362 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5363 return MCDisassembler::Fail; 5364 // Rt2 5365 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5366 return MCDisassembler::Fail; 5367 // Writeback operand 5368 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5369 return MCDisassembler::Fail; 5370 // addr 5371 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5372 return MCDisassembler::Fail; 5373 5374 return S; 5375 } 5376 5377 static DecodeStatus 5378 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5379 uint64_t Address, const void *Decoder) { 5380 DecodeStatus S = MCDisassembler::Success; 5381 5382 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5383 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5384 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5385 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5386 unsigned W = fieldFromInstruction(Insn, 21, 1); 5387 unsigned U = fieldFromInstruction(Insn, 23, 1); 5388 unsigned P = fieldFromInstruction(Insn, 24, 1); 5389 bool writeback = (W == 1) | (P == 0); 5390 5391 addr |= (U << 8) | (Rn << 9); 5392 5393 if (writeback && (Rn == Rt || Rn == Rt2)) 5394 Check(S, MCDisassembler::SoftFail); 5395 5396 // Writeback operand 5397 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5398 return MCDisassembler::Fail; 5399 // Rt 5400 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5401 return MCDisassembler::Fail; 5402 // Rt2 5403 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5404 return MCDisassembler::Fail; 5405 // addr 5406 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5407 return MCDisassembler::Fail; 5408 5409 return S; 5410 } 5411 5412 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5413 uint64_t Address, const void *Decoder) { 5414 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5415 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5416 if (sign1 != sign2) return MCDisassembler::Fail; 5417 5418 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5419 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5420 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5421 Val |= sign1 << 12; 5422 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5423 5424 return MCDisassembler::Success; 5425 } 5426 5427 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5428 uint64_t Address, 5429 const void *Decoder) { 5430 DecodeStatus S = MCDisassembler::Success; 5431 5432 // Shift of "asr #32" is not allowed in Thumb2 mode. 5433 if (Val == 0x20) S = MCDisassembler::Fail; 5434 Inst.addOperand(MCOperand::createImm(Val)); 5435 return S; 5436 } 5437 5438 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5439 uint64_t Address, const void *Decoder) { 5440 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5441 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5442 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5443 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5444 5445 if (pred == 0xF) 5446 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5447 5448 DecodeStatus S = MCDisassembler::Success; 5449 5450 if (Rt == Rn || Rn == Rt2) 5451 S = MCDisassembler::SoftFail; 5452 5453 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5454 return MCDisassembler::Fail; 5455 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5456 return MCDisassembler::Fail; 5457 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5458 return MCDisassembler::Fail; 5459 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5460 return MCDisassembler::Fail; 5461 5462 return S; 5463 } 5464 5465 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5466 uint64_t Address, const void *Decoder) { 5467 const FeatureBitset &featureBits = 5468 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5469 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5470 5471 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5472 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5473 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5474 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5475 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5476 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5477 unsigned op = fieldFromInstruction(Insn, 5, 1); 5478 5479 DecodeStatus S = MCDisassembler::Success; 5480 5481 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5482 if (!(imm & 0x38)) { 5483 if (cmode == 0xF) { 5484 if (op == 1) return MCDisassembler::Fail; 5485 Inst.setOpcode(ARM::VMOVv2f32); 5486 } 5487 if (hasFullFP16) { 5488 if (cmode == 0xE) { 5489 if (op == 1) { 5490 Inst.setOpcode(ARM::VMOVv1i64); 5491 } else { 5492 Inst.setOpcode(ARM::VMOVv8i8); 5493 } 5494 } 5495 if (cmode == 0xD) { 5496 if (op == 1) { 5497 Inst.setOpcode(ARM::VMVNv2i32); 5498 } else { 5499 Inst.setOpcode(ARM::VMOVv2i32); 5500 } 5501 } 5502 if (cmode == 0xC) { 5503 if (op == 1) { 5504 Inst.setOpcode(ARM::VMVNv2i32); 5505 } else { 5506 Inst.setOpcode(ARM::VMOVv2i32); 5507 } 5508 } 5509 } 5510 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5511 } 5512 5513 if (!(imm & 0x20)) return MCDisassembler::Fail; 5514 5515 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5516 return MCDisassembler::Fail; 5517 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5518 return MCDisassembler::Fail; 5519 Inst.addOperand(MCOperand::createImm(64 - imm)); 5520 5521 return S; 5522 } 5523 5524 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5525 uint64_t Address, const void *Decoder) { 5526 const FeatureBitset &featureBits = 5527 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5528 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5529 5530 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5531 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5532 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5533 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5534 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5535 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5536 unsigned op = fieldFromInstruction(Insn, 5, 1); 5537 5538 DecodeStatus S = MCDisassembler::Success; 5539 5540 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5541 if (!(imm & 0x38)) { 5542 if (cmode == 0xF) { 5543 if (op == 1) return MCDisassembler::Fail; 5544 Inst.setOpcode(ARM::VMOVv4f32); 5545 } 5546 if (hasFullFP16) { 5547 if (cmode == 0xE) { 5548 if (op == 1) { 5549 Inst.setOpcode(ARM::VMOVv2i64); 5550 } else { 5551 Inst.setOpcode(ARM::VMOVv16i8); 5552 } 5553 } 5554 if (cmode == 0xD) { 5555 if (op == 1) { 5556 Inst.setOpcode(ARM::VMVNv4i32); 5557 } else { 5558 Inst.setOpcode(ARM::VMOVv4i32); 5559 } 5560 } 5561 if (cmode == 0xC) { 5562 if (op == 1) { 5563 Inst.setOpcode(ARM::VMVNv4i32); 5564 } else { 5565 Inst.setOpcode(ARM::VMOVv4i32); 5566 } 5567 } 5568 } 5569 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5570 } 5571 5572 if (!(imm & 0x20)) return MCDisassembler::Fail; 5573 5574 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5575 return MCDisassembler::Fail; 5576 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5577 return MCDisassembler::Fail; 5578 Inst.addOperand(MCOperand::createImm(64 - imm)); 5579 5580 return S; 5581 } 5582 5583 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5584 unsigned Insn, 5585 uint64_t Address, 5586 const void *Decoder) { 5587 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5588 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5589 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5590 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5591 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5592 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5593 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5594 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5595 5596 DecodeStatus S = MCDisassembler::Success; 5597 5598 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5599 5600 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5601 return MCDisassembler::Fail; 5602 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5603 return MCDisassembler::Fail; 5604 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5605 return MCDisassembler::Fail; 5606 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5607 return MCDisassembler::Fail; 5608 // The lane index does not have any bits in the encoding, because it can only 5609 // be 0. 5610 Inst.addOperand(MCOperand::createImm(0)); 5611 Inst.addOperand(MCOperand::createImm(rotate)); 5612 5613 return S; 5614 } 5615 5616 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5617 uint64_t Address, const void *Decoder) { 5618 DecodeStatus S = MCDisassembler::Success; 5619 5620 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5621 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5622 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5623 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5624 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5625 5626 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5627 S = MCDisassembler::SoftFail; 5628 5629 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5630 return MCDisassembler::Fail; 5631 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5632 return MCDisassembler::Fail; 5633 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5634 return MCDisassembler::Fail; 5635 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5636 return MCDisassembler::Fail; 5637 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5638 return MCDisassembler::Fail; 5639 5640 return S; 5641 } 5642 5643 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5644 uint64_t Address, const void *Decoder) { 5645 DecodeStatus S = MCDisassembler::Success; 5646 5647 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5648 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5649 unsigned cop = fieldFromInstruction(Val, 8, 4); 5650 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5651 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5652 5653 if ((cop & ~0x1) == 0xa) 5654 return MCDisassembler::Fail; 5655 5656 if (Rt == Rt2) 5657 S = MCDisassembler::SoftFail; 5658 5659 // We have to check if the instruction is MRRC2 5660 // or MCRR2 when constructing the operands for 5661 // Inst. Reason is because MRRC2 stores to two 5662 // registers so it's tablegen desc has has two 5663 // outputs whereas MCRR doesn't store to any 5664 // registers so all of it's operands are listed 5665 // as inputs, therefore the operand order for 5666 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5667 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5668 5669 if (Inst.getOpcode() == ARM::MRRC2) { 5670 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5671 return MCDisassembler::Fail; 5672 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5673 return MCDisassembler::Fail; 5674 } 5675 Inst.addOperand(MCOperand::createImm(cop)); 5676 Inst.addOperand(MCOperand::createImm(opc1)); 5677 if (Inst.getOpcode() == ARM::MCRR2) { 5678 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5679 return MCDisassembler::Fail; 5680 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5681 return MCDisassembler::Fail; 5682 } 5683 Inst.addOperand(MCOperand::createImm(CRm)); 5684 5685 return S; 5686 } 5687 5688 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5689 uint64_t Address, 5690 const void *Decoder) { 5691 const FeatureBitset &featureBits = 5692 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5693 DecodeStatus S = MCDisassembler::Success; 5694 5695 // Add explicit operand for the destination sysreg, for cases where 5696 // we have to model it for code generation purposes. 5697 switch (Inst.getOpcode()) { 5698 case ARM::VMSR_FPSCR_NZCVQC: 5699 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5700 break; 5701 case ARM::VMSR_P0: 5702 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5703 break; 5704 } 5705 5706 if (Inst.getOpcode() != ARM::FMSTAT) { 5707 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5708 5709 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5710 if (Rt == 13 || Rt == 15) 5711 S = MCDisassembler::SoftFail; 5712 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5713 } else 5714 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5715 } 5716 5717 // Add explicit operand for the source sysreg, similarly to above. 5718 switch (Inst.getOpcode()) { 5719 case ARM::VMRS_FPSCR_NZCVQC: 5720 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5721 break; 5722 case ARM::VMRS_P0: 5723 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5724 break; 5725 } 5726 5727 if (featureBits[ARM::ModeThumb]) { 5728 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5729 Inst.addOperand(MCOperand::createReg(0)); 5730 } else { 5731 unsigned pred = fieldFromInstruction(Val, 28, 4); 5732 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5733 return MCDisassembler::Fail; 5734 } 5735 5736 return S; 5737 } 5738 5739 template <bool isSigned, bool isNeg, int size> 5740 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5741 uint64_t Address, 5742 const void *Decoder) { 5743 DecodeStatus S = MCDisassembler::Success; 5744 if (Val == 0) 5745 S = MCDisassembler::SoftFail; 5746 5747 uint64_t DecVal; 5748 if (isSigned) 5749 DecVal = SignExtend32<size + 1>(Val << 1); 5750 else 5751 DecVal = (Val << 1); 5752 5753 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5754 Decoder)) 5755 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5756 return S; 5757 } 5758 5759 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5760 uint64_t Address, 5761 const void *Decoder) { 5762 5763 uint64_t LocImm = Inst.getOperand(0).getImm(); 5764 Val = LocImm + (2 << Val); 5765 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5766 Decoder)) 5767 Inst.addOperand(MCOperand::createImm(Val)); 5768 return MCDisassembler::Success; 5769 } 5770 5771 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5772 uint64_t Address, 5773 const void *Decoder) { 5774 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5775 return MCDisassembler::Fail; 5776 Inst.addOperand(MCOperand::createImm(Val)); 5777 return MCDisassembler::Success; 5778 } 5779 5780 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5781 const void *Decoder) { 5782 DecodeStatus S = MCDisassembler::Success; 5783 5784 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5785 fieldFromInstruction(Insn, 1, 10) << 1; 5786 switch (Inst.getOpcode()) { 5787 case ARM::t2LEUpdate: 5788 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5789 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5790 LLVM_FALLTHROUGH; 5791 case ARM::t2LE: 5792 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5793 Decoder))) 5794 return MCDisassembler::Fail; 5795 break; 5796 case ARM::t2WLS: 5797 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5798 if (!Check(S, 5799 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5800 Address, Decoder)) || 5801 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5802 Decoder))) 5803 return MCDisassembler::Fail; 5804 break; 5805 case ARM::t2DLS: 5806 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5807 if (Rn == 0xF) { 5808 return MCDisassembler::Fail; 5809 } else { 5810 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5811 if (!Check(S, DecoderGPRRegisterClass(Inst, 5812 fieldFromInstruction(Insn, 16, 4), 5813 Address, Decoder))) 5814 return MCDisassembler::Fail; 5815 } 5816 break; 5817 } 5818 return S; 5819 } 5820 5821 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 5822 uint64_t Address, 5823 const void *Decoder) { 5824 DecodeStatus S = MCDisassembler::Success; 5825 5826 if (Val == 0) 5827 Val = 32; 5828 5829 Inst.addOperand(MCOperand::createImm(Val)); 5830 5831 return S; 5832 } 5833 5834 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 5835 uint64_t Address, const void *Decoder) { 5836 if ((RegNo) + 1 > 11) 5837 return MCDisassembler::Fail; 5838 5839 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 5840 Inst.addOperand(MCOperand::createReg(Register)); 5841 return MCDisassembler::Success; 5842 } 5843 5844 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 5845 uint64_t Address, const void *Decoder) { 5846 if ((RegNo) > 14) 5847 return MCDisassembler::Fail; 5848 5849 unsigned Register = GPRDecoderTable[(RegNo)]; 5850 Inst.addOperand(MCOperand::createReg(Register)); 5851 return MCDisassembler::Success; 5852 } 5853 5854 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 5855 const void *Decoder) { 5856 DecodeStatus S = MCDisassembler::Success; 5857 5858 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5859 Inst.addOperand(MCOperand::createReg(0)); 5860 if (Inst.getOpcode() == ARM::VSCCLRMD) { 5861 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 5862 (fieldFromInstruction(Insn, 12, 4) << 8) | 5863 (fieldFromInstruction(Insn, 22, 1) << 12); 5864 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 5865 return MCDisassembler::Fail; 5866 } 5867 } else { 5868 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 5869 (fieldFromInstruction(Insn, 22, 1) << 8) | 5870 (fieldFromInstruction(Insn, 12, 4) << 9); 5871 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 5872 return MCDisassembler::Fail; 5873 } 5874 } 5875 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5876 5877 return S; 5878 } 5879 5880 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 5881 uint64_t Address, 5882 const void *Decoder) { 5883 if (RegNo > 7) 5884 return MCDisassembler::Fail; 5885 5886 unsigned Register = QPRDecoderTable[RegNo]; 5887 Inst.addOperand(MCOperand::createReg(Register)); 5888 return MCDisassembler::Success; 5889 } 5890 5891 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 5892 uint64_t Address, 5893 const void *Decoder) { 5894 DecodeStatus S = MCDisassembler::Success; 5895 5896 // Parse VPT mask and encode it in the MCInst as an immediate with the same 5897 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 5898 // 't' as 0 and finish with a 1. 5899 unsigned Imm = 0; 5900 // We always start with a 't'. 5901 unsigned CurBit = 0; 5902 for (int i = 3; i >= 0; --i) { 5903 // If the bit we are looking at is not the same as last one, invert the 5904 // CurBit, if it is the same leave it as is. 5905 CurBit ^= (Val >> i) & 1U; 5906 5907 // Encode the CurBit at the right place in the immediate. 5908 Imm |= (CurBit << i); 5909 5910 // If we are done, finish the encoding with a 1. 5911 if ((Val & ~(~0U << i)) == 0) { 5912 Imm |= 1U << i; 5913 break; 5914 } 5915 } 5916 5917 Inst.addOperand(MCOperand::createImm(Imm)); 5918 5919 return S; 5920 } 5921 5922 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 5923 uint64_t Address, const void *Decoder) { 5924 // The vpred_r operand type includes an MQPR register field derived 5925 // from the encoding. But we don't actually want to add an operand 5926 // to the MCInst at this stage, because AddThumbPredicate will do it 5927 // later, and will infer the register number from the TIED_TO 5928 // constraint. So this is a deliberately empty decoder method that 5929 // will inhibit the auto-generated disassembly code from adding an 5930 // operand at all. 5931 return MCDisassembler::Success; 5932 } 5933 5934 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 5935 unsigned Val, 5936 uint64_t Address, 5937 const void *Decoder) { 5938 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 5939 return MCDisassembler::Success; 5940 } 5941 5942 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 5943 unsigned Val, 5944 uint64_t Address, 5945 const void *Decoder) { 5946 unsigned Code; 5947 switch (Val & 0x3) { 5948 case 0: 5949 Code = ARMCC::GE; 5950 break; 5951 case 1: 5952 Code = ARMCC::LT; 5953 break; 5954 case 2: 5955 Code = ARMCC::GT; 5956 break; 5957 case 3: 5958 Code = ARMCC::LE; 5959 break; 5960 } 5961 Inst.addOperand(MCOperand::createImm(Code)); 5962 return MCDisassembler::Success; 5963 } 5964 5965 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 5966 unsigned Val, 5967 uint64_t Address, 5968 const void *Decoder) { 5969 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 5970 return MCDisassembler::Success; 5971 } 5972 5973 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 5974 uint64_t Address, 5975 const void *Decoder) { 5976 unsigned Code; 5977 switch (Val) { 5978 default: 5979 return MCDisassembler::Fail; 5980 case 0: 5981 Code = ARMCC::EQ; 5982 break; 5983 case 1: 5984 Code = ARMCC::NE; 5985 break; 5986 case 4: 5987 Code = ARMCC::GE; 5988 break; 5989 case 5: 5990 Code = ARMCC::LT; 5991 break; 5992 case 6: 5993 Code = ARMCC::GT; 5994 break; 5995 case 7: 5996 Code = ARMCC::LE; 5997 break; 5998 } 5999 6000 Inst.addOperand(MCOperand::createImm(Code)); 6001 return MCDisassembler::Success; 6002 } 6003 6004 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6005 switch (Opcode) { 6006 case ARM::VSTR_P0_off: 6007 case ARM::VSTR_P0_pre: 6008 case ARM::VSTR_P0_post: 6009 case ARM::VLDR_P0_off: 6010 case ARM::VLDR_P0_pre: 6011 case ARM::VLDR_P0_post: 6012 return ARM::P0; 6013 default: 6014 return 0; 6015 } 6016 } 6017 6018 template<bool Writeback> 6019 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6020 uint64_t Address, 6021 const void *Decoder) { 6022 switch (Inst.getOpcode()) { 6023 case ARM::VSTR_FPSCR_pre: 6024 case ARM::VSTR_FPSCR_NZCVQC_pre: 6025 case ARM::VLDR_FPSCR_pre: 6026 case ARM::VLDR_FPSCR_NZCVQC_pre: 6027 case ARM::VSTR_FPSCR_off: 6028 case ARM::VSTR_FPSCR_NZCVQC_off: 6029 case ARM::VLDR_FPSCR_off: 6030 case ARM::VLDR_FPSCR_NZCVQC_off: 6031 case ARM::VSTR_FPSCR_post: 6032 case ARM::VSTR_FPSCR_NZCVQC_post: 6033 case ARM::VLDR_FPSCR_post: 6034 case ARM::VLDR_FPSCR_NZCVQC_post: 6035 const FeatureBitset &featureBits = 6036 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6037 6038 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6039 return MCDisassembler::Fail; 6040 } 6041 6042 DecodeStatus S = MCDisassembler::Success; 6043 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6044 Inst.addOperand(MCOperand::createReg(Sysreg)); 6045 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6046 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6047 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6048 6049 if (Writeback) { 6050 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6051 return MCDisassembler::Fail; 6052 } 6053 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6054 return MCDisassembler::Fail; 6055 6056 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6057 Inst.addOperand(MCOperand::createReg(0)); 6058 6059 return S; 6060 } 6061 6062 template <int shift> 6063 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6064 uint64_t Address, 6065 const void *Decoder) { 6066 Val <<= shift; 6067 6068 Inst.addOperand(MCOperand::createImm(Val)); 6069 return MCDisassembler::Success; 6070 } 6071 6072 static DecodeStatus DecodeMVEOverlappingLongShift( 6073 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6074 DecodeStatus S = MCDisassembler::Success; 6075 6076 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6077 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6078 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6079 6080 if (RdaHi == 14) { 6081 // This value of RdaHi (really indicating pc, because RdaHi has to 6082 // be an odd-numbered register, so the low bit will be set by the 6083 // decode function below) indicates that we must decode as SQRSHR 6084 // or UQRSHL, which both have a single Rda register field with all 6085 // four bits. 6086 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6087 6088 switch (Inst.getOpcode()) { 6089 case ARM::MVE_ASRLr: 6090 case ARM::MVE_SQRSHRL: 6091 Inst.setOpcode(ARM::MVE_SQRSHR); 6092 break; 6093 case ARM::MVE_LSLLr: 6094 case ARM::MVE_UQRSHLL: 6095 Inst.setOpcode(ARM::MVE_UQRSHL); 6096 break; 6097 default: 6098 llvm_unreachable("Unexpected starting opcode!"); 6099 } 6100 6101 // Rda as output parameter 6102 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6103 return MCDisassembler::Fail; 6104 6105 // Rda again as input parameter 6106 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6107 return MCDisassembler::Fail; 6108 6109 // Rm, the amount to shift by 6110 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6111 return MCDisassembler::Fail; 6112 6113 return S; 6114 } 6115 6116 // Otherwise, we decode as whichever opcode our caller has already 6117 // put into Inst. Those all look the same: 6118 6119 // RdaLo,RdaHi as output parameters 6120 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6121 return MCDisassembler::Fail; 6122 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6123 return MCDisassembler::Fail; 6124 6125 // RdaLo,RdaHi again as input parameters 6126 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6127 return MCDisassembler::Fail; 6128 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6129 return MCDisassembler::Fail; 6130 6131 // Rm, the amount to shift by 6132 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6133 return MCDisassembler::Fail; 6134 6135 return S; 6136 } 6137