1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "llvm/MC/MCContext.h" 14 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 15 #include "llvm/MC/MCFixedLenDisassembler.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCSubtargetInfo.h" 19 #include "llvm/MC/SubtargetFeature.h" 20 #include "llvm/Support/Compiler.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/raw_ostream.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include <algorithm> 26 #include <cassert> 27 #include <cstdint> 28 #include <vector> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "arm-disassembler" 33 34 typedef MCDisassembler::DecodeStatus DecodeStatus; 35 36 namespace { 37 38 // Handles the condition code status of instructions in IT blocks 39 class ITStatus 40 { 41 public: 42 // Returns the condition code for instruction in IT block 43 unsigned getITCC() { 44 unsigned CC = ARMCC::AL; 45 if (instrInITBlock()) 46 CC = ITStates.back(); 47 return CC; 48 } 49 50 // Advances the IT block state to the next T or E 51 void advanceITState() { 52 ITStates.pop_back(); 53 } 54 55 // Returns true if the current instruction is in an IT block 56 bool instrInITBlock() { 57 return !ITStates.empty(); 58 } 59 60 // Returns true if current instruction is the last instruction in an IT block 61 bool instrLastInITBlock() { 62 return ITStates.size() == 1; 63 } 64 65 // Called when decoding an IT instruction. Sets the IT state for the following 66 // instructions that for the IT block. Firstcond and Mask correspond to the 67 // fields in the IT instruction encoding. 68 void setITState(char Firstcond, char Mask) { 69 // (3 - the number of trailing zeros) is the number of then / else. 70 unsigned CondBit0 = Firstcond & 1; 71 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 72 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 73 assert(NumTZ <= 3 && "Invalid IT mask!"); 74 // push condition codes onto the stack the correct order for the pops 75 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 76 bool T = ((Mask >> Pos) & 1) == CondBit0; 77 if (T) 78 ITStates.push_back(CCBits); 79 else 80 ITStates.push_back(CCBits ^ 1); 81 } 82 ITStates.push_back(CCBits); 83 } 84 85 private: 86 std::vector<unsigned char> ITStates; 87 }; 88 89 /// ARM disassembler for all ARM platforms. 90 class ARMDisassembler : public MCDisassembler { 91 public: 92 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 93 MCDisassembler(STI, Ctx) { 94 } 95 96 ~ARMDisassembler() override = default; 97 98 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 99 ArrayRef<uint8_t> Bytes, uint64_t Address, 100 raw_ostream &VStream, 101 raw_ostream &CStream) const override; 102 }; 103 104 /// Thumb disassembler for all Thumb platforms. 105 class ThumbDisassembler : public MCDisassembler { 106 public: 107 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 108 MCDisassembler(STI, Ctx) { 109 } 110 111 ~ThumbDisassembler() override = default; 112 113 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 114 ArrayRef<uint8_t> Bytes, uint64_t Address, 115 raw_ostream &VStream, 116 raw_ostream &CStream) const override; 117 118 private: 119 mutable ITStatus ITBlock; 120 DecodeStatus AddThumbPredicate(MCInst&) const; 121 void UpdateThumbVFPPredicate(MCInst&) const; 122 }; 123 124 } // end anonymous namespace 125 126 static bool Check(DecodeStatus &Out, DecodeStatus In) { 127 switch (In) { 128 case MCDisassembler::Success: 129 // Out stays the same. 130 return true; 131 case MCDisassembler::SoftFail: 132 Out = In; 133 return true; 134 case MCDisassembler::Fail: 135 Out = In; 136 return false; 137 } 138 llvm_unreachable("Invalid DecodeStatus!"); 139 } 140 141 // Forward declare these because the autogenerated code will reference them. 142 // Definitions are further down. 143 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 146 unsigned RegNo, uint64_t Address, 147 const void *Decoder); 148 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 149 unsigned RegNo, uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 166 unsigned RegNo, 167 uint64_t Address, 168 const void *Decoder); 169 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 174 unsigned RegNo, uint64_t Address, 175 const void *Decoder); 176 177 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 188 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 193 unsigned Insn, 194 uint64_t Address, 195 const void *Decoder); 196 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 203 uint64_t Address, const void *Decoder); 204 205 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 206 unsigned Insn, 207 uint64_t Adddress, 208 const void *Decoder); 209 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 322 uint64_t Address, const void *Decoder); 323 324 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void* Decoder); 346 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void* Decoder); 348 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void* Decoder); 350 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 397 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 402 #include "ARMGenDisassemblerTables.inc" 403 404 static MCDisassembler *createARMDisassembler(const Target &T, 405 const MCSubtargetInfo &STI, 406 MCContext &Ctx) { 407 return new ARMDisassembler(STI, Ctx); 408 } 409 410 static MCDisassembler *createThumbDisassembler(const Target &T, 411 const MCSubtargetInfo &STI, 412 MCContext &Ctx) { 413 return new ThumbDisassembler(STI, Ctx); 414 } 415 416 // Post-decoding checks 417 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 418 uint64_t Address, raw_ostream &OS, 419 raw_ostream &CS, 420 uint32_t Insn, 421 DecodeStatus Result) { 422 switch (MI.getOpcode()) { 423 case ARM::HVC: { 424 // HVC is undefined if condition = 0xf otherwise upredictable 425 // if condition != 0xe 426 uint32_t Cond = (Insn >> 28) & 0xF; 427 if (Cond == 0xF) 428 return MCDisassembler::Fail; 429 if (Cond != 0xE) 430 return MCDisassembler::SoftFail; 431 return Result; 432 } 433 default: return Result; 434 } 435 } 436 437 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 438 ArrayRef<uint8_t> Bytes, 439 uint64_t Address, raw_ostream &OS, 440 raw_ostream &CS) const { 441 CommentStream = &CS; 442 443 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 444 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 445 "mode!"); 446 447 // We want to read exactly 4 bytes of data. 448 if (Bytes.size() < 4) { 449 Size = 0; 450 return MCDisassembler::Fail; 451 } 452 453 // Encoded as a small-endian 32-bit word in the stream. 454 uint32_t Insn = 455 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 456 457 // Calling the auto-generated decoder function. 458 DecodeStatus Result = 459 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 460 if (Result != MCDisassembler::Fail) { 461 Size = 4; 462 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 463 } 464 465 // VFP and NEON instructions, similarly, are shared between ARM 466 // and Thumb modes. 467 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI); 468 if (Result != MCDisassembler::Fail) { 469 Size = 4; 470 return Result; 471 } 472 473 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI); 474 if (Result != MCDisassembler::Fail) { 475 Size = 4; 476 return Result; 477 } 478 479 Result = 480 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI); 481 if (Result != MCDisassembler::Fail) { 482 Size = 4; 483 // Add a fake predicate operand, because we share these instruction 484 // definitions with Thumb2 where these instructions are predicable. 485 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 486 return MCDisassembler::Fail; 487 return Result; 488 } 489 490 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address, 491 this, STI); 492 if (Result != MCDisassembler::Fail) { 493 Size = 4; 494 // Add a fake predicate operand, because we share these instruction 495 // definitions with Thumb2 where these instructions are predicable. 496 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 497 return MCDisassembler::Fail; 498 return Result; 499 } 500 501 Result = 502 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI); 503 if (Result != MCDisassembler::Fail) { 504 Size = 4; 505 // Add a fake predicate operand, because we share these instruction 506 // definitions with Thumb2 where these instructions are predicable. 507 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 508 return MCDisassembler::Fail; 509 return Result; 510 } 511 512 Result = 513 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI); 514 if (Result != MCDisassembler::Fail) { 515 Size = 4; 516 return Result; 517 } 518 519 Result = 520 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI); 521 if (Result != MCDisassembler::Fail) { 522 Size = 4; 523 return Result; 524 } 525 526 Size = 0; 527 return MCDisassembler::Fail; 528 } 529 530 namespace llvm { 531 532 extern const MCInstrDesc ARMInsts[]; 533 534 } // end namespace llvm 535 536 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 537 /// immediate Value in the MCInst. The immediate Value has had any PC 538 /// adjustment made by the caller. If the instruction is a branch instruction 539 /// then isBranch is true, else false. If the getOpInfo() function was set as 540 /// part of the setupForSymbolicDisassembly() call then that function is called 541 /// to get any symbolic information at the Address for this instruction. If 542 /// that returns non-zero then the symbolic information it returns is used to 543 /// create an MCExpr and that is added as an operand to the MCInst. If 544 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 545 /// Value is done and if a symbol is found an MCExpr is created with that, else 546 /// an MCExpr with Value is created. This function returns true if it adds an 547 /// operand to the MCInst and false otherwise. 548 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 549 bool isBranch, uint64_t InstSize, 550 MCInst &MI, const void *Decoder) { 551 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 552 // FIXME: Does it make sense for value to be negative? 553 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 554 /* Offset */ 0, InstSize); 555 } 556 557 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 558 /// referenced by a load instruction with the base register that is the Pc. 559 /// These can often be values in a literal pool near the Address of the 560 /// instruction. The Address of the instruction and its immediate Value are 561 /// used as a possible literal pool entry. The SymbolLookUp call back will 562 /// return the name of a symbol referenced by the literal pool's entry if 563 /// the referenced address is that of a symbol. Or it will return a pointer to 564 /// a literal 'C' string if the referenced address of the literal pool's entry 565 /// is an address into a section with 'C' string literals. 566 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 567 const void *Decoder) { 568 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 569 Dis->tryAddingPcLoadReferenceComment(Value, Address); 570 } 571 572 // Thumb1 instructions don't have explicit S bits. Rather, they 573 // implicitly set CPSR. Since it's not represented in the encoding, the 574 // auto-generated decoder won't inject the CPSR operand. We need to fix 575 // that as a post-pass. 576 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 577 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 578 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 579 MCInst::iterator I = MI.begin(); 580 for (unsigned i = 0; i < NumOps; ++i, ++I) { 581 if (I == MI.end()) break; 582 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 583 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 584 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 585 return; 586 } 587 } 588 589 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 590 } 591 592 // Most Thumb instructions don't have explicit predicates in the 593 // encoding, but rather get their predicates from IT context. We need 594 // to fix up the predicate operands using this context information as a 595 // post-pass. 596 MCDisassembler::DecodeStatus 597 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 598 MCDisassembler::DecodeStatus S = Success; 599 600 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 601 602 // A few instructions actually have predicates encoded in them. Don't 603 // try to overwrite it if we're seeing one of those. 604 switch (MI.getOpcode()) { 605 case ARM::tBcc: 606 case ARM::t2Bcc: 607 case ARM::tCBZ: 608 case ARM::tCBNZ: 609 case ARM::tCPS: 610 case ARM::t2CPS3p: 611 case ARM::t2CPS2p: 612 case ARM::t2CPS1p: 613 case ARM::tMOVSr: 614 case ARM::tSETEND: 615 // Some instructions (mostly conditional branches) are not 616 // allowed in IT blocks. 617 if (ITBlock.instrInITBlock()) 618 S = SoftFail; 619 else 620 return Success; 621 break; 622 case ARM::t2HINT: 623 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 624 S = SoftFail; 625 break; 626 case ARM::tB: 627 case ARM::t2B: 628 case ARM::t2TBB: 629 case ARM::t2TBH: 630 // Some instructions (mostly unconditional branches) can 631 // only appears at the end of, or outside of, an IT. 632 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 633 S = SoftFail; 634 break; 635 default: 636 break; 637 } 638 639 // If we're in an IT block, base the predicate on that. Otherwise, 640 // assume a predicate of AL. 641 unsigned CC; 642 CC = ITBlock.getITCC(); 643 if (CC == 0xF) 644 CC = ARMCC::AL; 645 if (ITBlock.instrInITBlock()) 646 ITBlock.advanceITState(); 647 648 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 649 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 650 MCInst::iterator I = MI.begin(); 651 for (unsigned i = 0; i < NumOps; ++i, ++I) { 652 if (I == MI.end()) break; 653 if (OpInfo[i].isPredicate()) { 654 I = MI.insert(I, MCOperand::createImm(CC)); 655 ++I; 656 if (CC == ARMCC::AL) 657 MI.insert(I, MCOperand::createReg(0)); 658 else 659 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 660 return S; 661 } 662 } 663 664 I = MI.insert(I, MCOperand::createImm(CC)); 665 ++I; 666 if (CC == ARMCC::AL) 667 MI.insert(I, MCOperand::createReg(0)); 668 else 669 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 670 671 return S; 672 } 673 674 // Thumb VFP instructions are a special case. Because we share their 675 // encodings between ARM and Thumb modes, and they are predicable in ARM 676 // mode, the auto-generated decoder will give them an (incorrect) 677 // predicate operand. We need to rewrite these operands based on the IT 678 // context as a post-pass. 679 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 680 unsigned CC; 681 CC = ITBlock.getITCC(); 682 if (ITBlock.instrInITBlock()) 683 ITBlock.advanceITState(); 684 685 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 686 MCInst::iterator I = MI.begin(); 687 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 688 for (unsigned i = 0; i < NumOps; ++i, ++I) { 689 if (OpInfo[i].isPredicate() ) { 690 I->setImm(CC); 691 ++I; 692 if (CC == ARMCC::AL) 693 I->setReg(0); 694 else 695 I->setReg(ARM::CPSR); 696 return; 697 } 698 } 699 } 700 701 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 702 ArrayRef<uint8_t> Bytes, 703 uint64_t Address, 704 raw_ostream &OS, 705 raw_ostream &CS) const { 706 CommentStream = &CS; 707 708 assert(STI.getFeatureBits()[ARM::ModeThumb] && 709 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 710 711 // We want to read exactly 2 bytes of data. 712 if (Bytes.size() < 2) { 713 Size = 0; 714 return MCDisassembler::Fail; 715 } 716 717 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 718 DecodeStatus Result = 719 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 720 if (Result != MCDisassembler::Fail) { 721 Size = 2; 722 Check(Result, AddThumbPredicate(MI)); 723 return Result; 724 } 725 726 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 727 STI); 728 if (Result) { 729 Size = 2; 730 bool InITBlock = ITBlock.instrInITBlock(); 731 Check(Result, AddThumbPredicate(MI)); 732 AddThumb1SBit(MI, InITBlock); 733 return Result; 734 } 735 736 Result = 737 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 738 if (Result != MCDisassembler::Fail) { 739 Size = 2; 740 741 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 742 // the Thumb predicate. 743 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 744 Result = MCDisassembler::SoftFail; 745 746 Check(Result, AddThumbPredicate(MI)); 747 748 // If we find an IT instruction, we need to parse its condition 749 // code and mask operands so that we can apply them correctly 750 // to the subsequent instructions. 751 if (MI.getOpcode() == ARM::t2IT) { 752 753 unsigned Firstcond = MI.getOperand(0).getImm(); 754 unsigned Mask = MI.getOperand(1).getImm(); 755 ITBlock.setITState(Firstcond, Mask); 756 } 757 758 return Result; 759 } 760 761 // We want to read exactly 4 bytes of data. 762 if (Bytes.size() < 4) { 763 Size = 0; 764 return MCDisassembler::Fail; 765 } 766 767 uint32_t Insn32 = 768 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 769 Result = 770 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 771 if (Result != MCDisassembler::Fail) { 772 Size = 4; 773 bool InITBlock = ITBlock.instrInITBlock(); 774 Check(Result, AddThumbPredicate(MI)); 775 AddThumb1SBit(MI, InITBlock); 776 return Result; 777 } 778 779 Result = 780 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 781 if (Result != MCDisassembler::Fail) { 782 Size = 4; 783 Check(Result, AddThumbPredicate(MI)); 784 return Result; 785 } 786 787 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 788 Result = 789 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 790 if (Result != MCDisassembler::Fail) { 791 Size = 4; 792 UpdateThumbVFPPredicate(MI); 793 return Result; 794 } 795 } 796 797 Result = 798 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 799 if (Result != MCDisassembler::Fail) { 800 Size = 4; 801 return Result; 802 } 803 804 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 805 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 806 STI); 807 if (Result != MCDisassembler::Fail) { 808 Size = 4; 809 Check(Result, AddThumbPredicate(MI)); 810 return Result; 811 } 812 } 813 814 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 815 uint32_t NEONLdStInsn = Insn32; 816 NEONLdStInsn &= 0xF0FFFFFF; 817 NEONLdStInsn |= 0x04000000; 818 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 819 Address, this, STI); 820 if (Result != MCDisassembler::Fail) { 821 Size = 4; 822 Check(Result, AddThumbPredicate(MI)); 823 return Result; 824 } 825 } 826 827 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 828 uint32_t NEONDataInsn = Insn32; 829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 832 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 833 Address, this, STI); 834 if (Result != MCDisassembler::Fail) { 835 Size = 4; 836 Check(Result, AddThumbPredicate(MI)); 837 return Result; 838 } 839 840 uint32_t NEONCryptoInsn = Insn32; 841 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 842 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 843 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 844 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 845 Address, this, STI); 846 if (Result != MCDisassembler::Fail) { 847 Size = 4; 848 return Result; 849 } 850 851 uint32_t NEONv8Insn = Insn32; 852 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 853 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 854 this, STI); 855 if (Result != MCDisassembler::Fail) { 856 Size = 4; 857 return Result; 858 } 859 } 860 861 Size = 0; 862 return MCDisassembler::Fail; 863 } 864 865 extern "C" void LLVMInitializeARMDisassembler() { 866 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 867 createARMDisassembler); 868 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 869 createARMDisassembler); 870 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 871 createThumbDisassembler); 872 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 873 createThumbDisassembler); 874 } 875 876 static const uint16_t GPRDecoderTable[] = { 877 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 878 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 879 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 880 ARM::R12, ARM::SP, ARM::LR, ARM::PC 881 }; 882 883 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 884 uint64_t Address, const void *Decoder) { 885 if (RegNo > 15) 886 return MCDisassembler::Fail; 887 888 unsigned Register = GPRDecoderTable[RegNo]; 889 Inst.addOperand(MCOperand::createReg(Register)); 890 return MCDisassembler::Success; 891 } 892 893 static DecodeStatus 894 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 895 uint64_t Address, const void *Decoder) { 896 DecodeStatus S = MCDisassembler::Success; 897 898 if (RegNo == 15) 899 S = MCDisassembler::SoftFail; 900 901 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 902 903 return S; 904 } 905 906 static DecodeStatus 907 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 908 uint64_t Address, const void *Decoder) { 909 DecodeStatus S = MCDisassembler::Success; 910 911 if (RegNo == 15) 912 { 913 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 914 return MCDisassembler::Success; 915 } 916 917 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 918 return S; 919 } 920 921 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 922 uint64_t Address, const void *Decoder) { 923 if (RegNo > 7) 924 return MCDisassembler::Fail; 925 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 926 } 927 928 static const uint16_t GPRPairDecoderTable[] = { 929 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 930 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 931 }; 932 933 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 934 uint64_t Address, const void *Decoder) { 935 DecodeStatus S = MCDisassembler::Success; 936 937 if (RegNo > 13) 938 return MCDisassembler::Fail; 939 940 if ((RegNo & 1) || RegNo == 0xe) 941 S = MCDisassembler::SoftFail; 942 943 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 944 Inst.addOperand(MCOperand::createReg(RegisterPair)); 945 return S; 946 } 947 948 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 949 uint64_t Address, const void *Decoder) { 950 unsigned Register = 0; 951 switch (RegNo) { 952 case 0: 953 Register = ARM::R0; 954 break; 955 case 1: 956 Register = ARM::R1; 957 break; 958 case 2: 959 Register = ARM::R2; 960 break; 961 case 3: 962 Register = ARM::R3; 963 break; 964 case 9: 965 Register = ARM::R9; 966 break; 967 case 12: 968 Register = ARM::R12; 969 break; 970 default: 971 return MCDisassembler::Fail; 972 } 973 974 Inst.addOperand(MCOperand::createReg(Register)); 975 return MCDisassembler::Success; 976 } 977 978 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 979 uint64_t Address, const void *Decoder) { 980 DecodeStatus S = MCDisassembler::Success; 981 982 const FeatureBitset &featureBits = 983 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 984 985 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 986 S = MCDisassembler::SoftFail; 987 988 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 989 return S; 990 } 991 992 static const uint16_t SPRDecoderTable[] = { 993 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 994 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 995 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 996 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 997 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 998 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 999 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1000 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1001 }; 1002 1003 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1004 uint64_t Address, const void *Decoder) { 1005 if (RegNo > 31) 1006 return MCDisassembler::Fail; 1007 1008 unsigned Register = SPRDecoderTable[RegNo]; 1009 Inst.addOperand(MCOperand::createReg(Register)); 1010 return MCDisassembler::Success; 1011 } 1012 1013 static const uint16_t DPRDecoderTable[] = { 1014 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1015 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1016 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1017 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1018 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1019 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1020 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1021 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1022 }; 1023 1024 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1025 uint64_t Address, const void *Decoder) { 1026 const FeatureBitset &featureBits = 1027 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1028 1029 bool hasD16 = featureBits[ARM::FeatureD16]; 1030 1031 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1032 return MCDisassembler::Fail; 1033 1034 unsigned Register = DPRDecoderTable[RegNo]; 1035 Inst.addOperand(MCOperand::createReg(Register)); 1036 return MCDisassembler::Success; 1037 } 1038 1039 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1040 uint64_t Address, const void *Decoder) { 1041 if (RegNo > 7) 1042 return MCDisassembler::Fail; 1043 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1044 } 1045 1046 static DecodeStatus 1047 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1048 uint64_t Address, const void *Decoder) { 1049 if (RegNo > 15) 1050 return MCDisassembler::Fail; 1051 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1052 } 1053 1054 static const uint16_t QPRDecoderTable[] = { 1055 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1056 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1057 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1058 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1059 }; 1060 1061 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1062 uint64_t Address, const void *Decoder) { 1063 if (RegNo > 31 || (RegNo & 1) != 0) 1064 return MCDisassembler::Fail; 1065 RegNo >>= 1; 1066 1067 unsigned Register = QPRDecoderTable[RegNo]; 1068 Inst.addOperand(MCOperand::createReg(Register)); 1069 return MCDisassembler::Success; 1070 } 1071 1072 static const uint16_t DPairDecoderTable[] = { 1073 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1074 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1075 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1076 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1077 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1078 ARM::Q15 1079 }; 1080 1081 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1082 uint64_t Address, const void *Decoder) { 1083 if (RegNo > 30) 1084 return MCDisassembler::Fail; 1085 1086 unsigned Register = DPairDecoderTable[RegNo]; 1087 Inst.addOperand(MCOperand::createReg(Register)); 1088 return MCDisassembler::Success; 1089 } 1090 1091 static const uint16_t DPairSpacedDecoderTable[] = { 1092 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1093 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1094 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1095 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1096 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1097 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1098 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1099 ARM::D28_D30, ARM::D29_D31 1100 }; 1101 1102 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1103 unsigned RegNo, 1104 uint64_t Address, 1105 const void *Decoder) { 1106 if (RegNo > 29) 1107 return MCDisassembler::Fail; 1108 1109 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1110 Inst.addOperand(MCOperand::createReg(Register)); 1111 return MCDisassembler::Success; 1112 } 1113 1114 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1115 uint64_t Address, const void *Decoder) { 1116 if (Val == 0xF) return MCDisassembler::Fail; 1117 // AL predicate is not allowed on Thumb1 branches. 1118 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1119 return MCDisassembler::Fail; 1120 Inst.addOperand(MCOperand::createImm(Val)); 1121 if (Val == ARMCC::AL) { 1122 Inst.addOperand(MCOperand::createReg(0)); 1123 } else 1124 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1125 return MCDisassembler::Success; 1126 } 1127 1128 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1129 uint64_t Address, const void *Decoder) { 1130 if (Val) 1131 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1132 else 1133 Inst.addOperand(MCOperand::createReg(0)); 1134 return MCDisassembler::Success; 1135 } 1136 1137 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1138 uint64_t Address, const void *Decoder) { 1139 DecodeStatus S = MCDisassembler::Success; 1140 1141 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1142 unsigned type = fieldFromInstruction(Val, 5, 2); 1143 unsigned imm = fieldFromInstruction(Val, 7, 5); 1144 1145 // Register-immediate 1146 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1147 return MCDisassembler::Fail; 1148 1149 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1150 switch (type) { 1151 case 0: 1152 Shift = ARM_AM::lsl; 1153 break; 1154 case 1: 1155 Shift = ARM_AM::lsr; 1156 break; 1157 case 2: 1158 Shift = ARM_AM::asr; 1159 break; 1160 case 3: 1161 Shift = ARM_AM::ror; 1162 break; 1163 } 1164 1165 if (Shift == ARM_AM::ror && imm == 0) 1166 Shift = ARM_AM::rrx; 1167 1168 unsigned Op = Shift | (imm << 3); 1169 Inst.addOperand(MCOperand::createImm(Op)); 1170 1171 return S; 1172 } 1173 1174 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1175 uint64_t Address, const void *Decoder) { 1176 DecodeStatus S = MCDisassembler::Success; 1177 1178 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1179 unsigned type = fieldFromInstruction(Val, 5, 2); 1180 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1181 1182 // Register-register 1183 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1184 return MCDisassembler::Fail; 1185 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1186 return MCDisassembler::Fail; 1187 1188 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1189 switch (type) { 1190 case 0: 1191 Shift = ARM_AM::lsl; 1192 break; 1193 case 1: 1194 Shift = ARM_AM::lsr; 1195 break; 1196 case 2: 1197 Shift = ARM_AM::asr; 1198 break; 1199 case 3: 1200 Shift = ARM_AM::ror; 1201 break; 1202 } 1203 1204 Inst.addOperand(MCOperand::createImm(Shift)); 1205 1206 return S; 1207 } 1208 1209 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1210 uint64_t Address, const void *Decoder) { 1211 DecodeStatus S = MCDisassembler::Success; 1212 1213 bool NeedDisjointWriteback = false; 1214 unsigned WritebackReg = 0; 1215 switch (Inst.getOpcode()) { 1216 default: 1217 break; 1218 case ARM::LDMIA_UPD: 1219 case ARM::LDMDB_UPD: 1220 case ARM::LDMIB_UPD: 1221 case ARM::LDMDA_UPD: 1222 case ARM::t2LDMIA_UPD: 1223 case ARM::t2LDMDB_UPD: 1224 case ARM::t2STMIA_UPD: 1225 case ARM::t2STMDB_UPD: 1226 NeedDisjointWriteback = true; 1227 WritebackReg = Inst.getOperand(0).getReg(); 1228 break; 1229 } 1230 1231 // Empty register lists are not allowed. 1232 if (Val == 0) return MCDisassembler::Fail; 1233 for (unsigned i = 0; i < 16; ++i) { 1234 if (Val & (1 << i)) { 1235 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1236 return MCDisassembler::Fail; 1237 // Writeback not allowed if Rn is in the target list. 1238 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1239 Check(S, MCDisassembler::SoftFail); 1240 } 1241 } 1242 1243 return S; 1244 } 1245 1246 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1247 uint64_t Address, const void *Decoder) { 1248 DecodeStatus S = MCDisassembler::Success; 1249 1250 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1251 unsigned regs = fieldFromInstruction(Val, 0, 8); 1252 1253 // In case of unpredictable encoding, tweak the operands. 1254 if (regs == 0 || (Vd + regs) > 32) { 1255 regs = Vd + regs > 32 ? 32 - Vd : regs; 1256 regs = std::max( 1u, regs); 1257 S = MCDisassembler::SoftFail; 1258 } 1259 1260 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1261 return MCDisassembler::Fail; 1262 for (unsigned i = 0; i < (regs - 1); ++i) { 1263 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1264 return MCDisassembler::Fail; 1265 } 1266 1267 return S; 1268 } 1269 1270 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1271 uint64_t Address, const void *Decoder) { 1272 DecodeStatus S = MCDisassembler::Success; 1273 1274 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1275 unsigned regs = fieldFromInstruction(Val, 1, 7); 1276 1277 // In case of unpredictable encoding, tweak the operands. 1278 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1279 regs = Vd + regs > 32 ? 32 - Vd : regs; 1280 regs = std::max( 1u, regs); 1281 regs = std::min(16u, regs); 1282 S = MCDisassembler::SoftFail; 1283 } 1284 1285 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1286 return MCDisassembler::Fail; 1287 for (unsigned i = 0; i < (regs - 1); ++i) { 1288 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1289 return MCDisassembler::Fail; 1290 } 1291 1292 return S; 1293 } 1294 1295 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1296 uint64_t Address, const void *Decoder) { 1297 // This operand encodes a mask of contiguous zeros between a specified MSB 1298 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1299 // the mask of all bits LSB-and-lower, and then xor them to create 1300 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1301 // create the final mask. 1302 unsigned msb = fieldFromInstruction(Val, 5, 5); 1303 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1304 1305 DecodeStatus S = MCDisassembler::Success; 1306 if (lsb > msb) { 1307 Check(S, MCDisassembler::SoftFail); 1308 // The check above will cause the warning for the "potentially undefined 1309 // instruction encoding" but we can't build a bad MCOperand value here 1310 // with a lsb > msb or else printing the MCInst will cause a crash. 1311 lsb = msb; 1312 } 1313 1314 uint32_t msb_mask = 0xFFFFFFFF; 1315 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1316 uint32_t lsb_mask = (1U << lsb) - 1; 1317 1318 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1319 return S; 1320 } 1321 1322 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1323 uint64_t Address, const void *Decoder) { 1324 DecodeStatus S = MCDisassembler::Success; 1325 1326 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1327 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1328 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1329 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1330 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1331 unsigned U = fieldFromInstruction(Insn, 23, 1); 1332 1333 switch (Inst.getOpcode()) { 1334 case ARM::LDC_OFFSET: 1335 case ARM::LDC_PRE: 1336 case ARM::LDC_POST: 1337 case ARM::LDC_OPTION: 1338 case ARM::LDCL_OFFSET: 1339 case ARM::LDCL_PRE: 1340 case ARM::LDCL_POST: 1341 case ARM::LDCL_OPTION: 1342 case ARM::STC_OFFSET: 1343 case ARM::STC_PRE: 1344 case ARM::STC_POST: 1345 case ARM::STC_OPTION: 1346 case ARM::STCL_OFFSET: 1347 case ARM::STCL_PRE: 1348 case ARM::STCL_POST: 1349 case ARM::STCL_OPTION: 1350 case ARM::t2LDC_OFFSET: 1351 case ARM::t2LDC_PRE: 1352 case ARM::t2LDC_POST: 1353 case ARM::t2LDC_OPTION: 1354 case ARM::t2LDCL_OFFSET: 1355 case ARM::t2LDCL_PRE: 1356 case ARM::t2LDCL_POST: 1357 case ARM::t2LDCL_OPTION: 1358 case ARM::t2STC_OFFSET: 1359 case ARM::t2STC_PRE: 1360 case ARM::t2STC_POST: 1361 case ARM::t2STC_OPTION: 1362 case ARM::t2STCL_OFFSET: 1363 case ARM::t2STCL_PRE: 1364 case ARM::t2STCL_POST: 1365 case ARM::t2STCL_OPTION: 1366 if (coproc == 0xA || coproc == 0xB) 1367 return MCDisassembler::Fail; 1368 break; 1369 default: 1370 break; 1371 } 1372 1373 const FeatureBitset &featureBits = 1374 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1375 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1376 return MCDisassembler::Fail; 1377 1378 Inst.addOperand(MCOperand::createImm(coproc)); 1379 Inst.addOperand(MCOperand::createImm(CRd)); 1380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1381 return MCDisassembler::Fail; 1382 1383 switch (Inst.getOpcode()) { 1384 case ARM::t2LDC2_OFFSET: 1385 case ARM::t2LDC2L_OFFSET: 1386 case ARM::t2LDC2_PRE: 1387 case ARM::t2LDC2L_PRE: 1388 case ARM::t2STC2_OFFSET: 1389 case ARM::t2STC2L_OFFSET: 1390 case ARM::t2STC2_PRE: 1391 case ARM::t2STC2L_PRE: 1392 case ARM::LDC2_OFFSET: 1393 case ARM::LDC2L_OFFSET: 1394 case ARM::LDC2_PRE: 1395 case ARM::LDC2L_PRE: 1396 case ARM::STC2_OFFSET: 1397 case ARM::STC2L_OFFSET: 1398 case ARM::STC2_PRE: 1399 case ARM::STC2L_PRE: 1400 case ARM::t2LDC_OFFSET: 1401 case ARM::t2LDCL_OFFSET: 1402 case ARM::t2LDC_PRE: 1403 case ARM::t2LDCL_PRE: 1404 case ARM::t2STC_OFFSET: 1405 case ARM::t2STCL_OFFSET: 1406 case ARM::t2STC_PRE: 1407 case ARM::t2STCL_PRE: 1408 case ARM::LDC_OFFSET: 1409 case ARM::LDCL_OFFSET: 1410 case ARM::LDC_PRE: 1411 case ARM::LDCL_PRE: 1412 case ARM::STC_OFFSET: 1413 case ARM::STCL_OFFSET: 1414 case ARM::STC_PRE: 1415 case ARM::STCL_PRE: 1416 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1417 Inst.addOperand(MCOperand::createImm(imm)); 1418 break; 1419 case ARM::t2LDC2_POST: 1420 case ARM::t2LDC2L_POST: 1421 case ARM::t2STC2_POST: 1422 case ARM::t2STC2L_POST: 1423 case ARM::LDC2_POST: 1424 case ARM::LDC2L_POST: 1425 case ARM::STC2_POST: 1426 case ARM::STC2L_POST: 1427 case ARM::t2LDC_POST: 1428 case ARM::t2LDCL_POST: 1429 case ARM::t2STC_POST: 1430 case ARM::t2STCL_POST: 1431 case ARM::LDC_POST: 1432 case ARM::LDCL_POST: 1433 case ARM::STC_POST: 1434 case ARM::STCL_POST: 1435 imm |= U << 8; 1436 LLVM_FALLTHROUGH; 1437 default: 1438 // The 'option' variant doesn't encode 'U' in the immediate since 1439 // the immediate is unsigned [0,255]. 1440 Inst.addOperand(MCOperand::createImm(imm)); 1441 break; 1442 } 1443 1444 switch (Inst.getOpcode()) { 1445 case ARM::LDC_OFFSET: 1446 case ARM::LDC_PRE: 1447 case ARM::LDC_POST: 1448 case ARM::LDC_OPTION: 1449 case ARM::LDCL_OFFSET: 1450 case ARM::LDCL_PRE: 1451 case ARM::LDCL_POST: 1452 case ARM::LDCL_OPTION: 1453 case ARM::STC_OFFSET: 1454 case ARM::STC_PRE: 1455 case ARM::STC_POST: 1456 case ARM::STC_OPTION: 1457 case ARM::STCL_OFFSET: 1458 case ARM::STCL_PRE: 1459 case ARM::STCL_POST: 1460 case ARM::STCL_OPTION: 1461 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1462 return MCDisassembler::Fail; 1463 break; 1464 default: 1465 break; 1466 } 1467 1468 return S; 1469 } 1470 1471 static DecodeStatus 1472 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1473 uint64_t Address, const void *Decoder) { 1474 DecodeStatus S = MCDisassembler::Success; 1475 1476 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1477 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1478 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1479 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1480 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1481 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1482 unsigned P = fieldFromInstruction(Insn, 24, 1); 1483 unsigned W = fieldFromInstruction(Insn, 21, 1); 1484 1485 // On stores, the writeback operand precedes Rt. 1486 switch (Inst.getOpcode()) { 1487 case ARM::STR_POST_IMM: 1488 case ARM::STR_POST_REG: 1489 case ARM::STRB_POST_IMM: 1490 case ARM::STRB_POST_REG: 1491 case ARM::STRT_POST_REG: 1492 case ARM::STRT_POST_IMM: 1493 case ARM::STRBT_POST_REG: 1494 case ARM::STRBT_POST_IMM: 1495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1496 return MCDisassembler::Fail; 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1503 return MCDisassembler::Fail; 1504 1505 // On loads, the writeback operand comes after Rt. 1506 switch (Inst.getOpcode()) { 1507 case ARM::LDR_POST_IMM: 1508 case ARM::LDR_POST_REG: 1509 case ARM::LDRB_POST_IMM: 1510 case ARM::LDRB_POST_REG: 1511 case ARM::LDRBT_POST_REG: 1512 case ARM::LDRBT_POST_IMM: 1513 case ARM::LDRT_POST_REG: 1514 case ARM::LDRT_POST_IMM: 1515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1516 return MCDisassembler::Fail; 1517 break; 1518 default: 1519 break; 1520 } 1521 1522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1523 return MCDisassembler::Fail; 1524 1525 ARM_AM::AddrOpc Op = ARM_AM::add; 1526 if (!fieldFromInstruction(Insn, 23, 1)) 1527 Op = ARM_AM::sub; 1528 1529 bool writeback = (P == 0) || (W == 1); 1530 unsigned idx_mode = 0; 1531 if (P && writeback) 1532 idx_mode = ARMII::IndexModePre; 1533 else if (!P && writeback) 1534 idx_mode = ARMII::IndexModePost; 1535 1536 if (writeback && (Rn == 15 || Rn == Rt)) 1537 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1538 1539 if (reg) { 1540 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1541 return MCDisassembler::Fail; 1542 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1543 switch( fieldFromInstruction(Insn, 5, 2)) { 1544 case 0: 1545 Opc = ARM_AM::lsl; 1546 break; 1547 case 1: 1548 Opc = ARM_AM::lsr; 1549 break; 1550 case 2: 1551 Opc = ARM_AM::asr; 1552 break; 1553 case 3: 1554 Opc = ARM_AM::ror; 1555 break; 1556 default: 1557 return MCDisassembler::Fail; 1558 } 1559 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1560 if (Opc == ARM_AM::ror && amt == 0) 1561 Opc = ARM_AM::rrx; 1562 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1563 1564 Inst.addOperand(MCOperand::createImm(imm)); 1565 } else { 1566 Inst.addOperand(MCOperand::createReg(0)); 1567 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1568 Inst.addOperand(MCOperand::createImm(tmp)); 1569 } 1570 1571 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1572 return MCDisassembler::Fail; 1573 1574 return S; 1575 } 1576 1577 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1578 uint64_t Address, const void *Decoder) { 1579 DecodeStatus S = MCDisassembler::Success; 1580 1581 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1582 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1583 unsigned type = fieldFromInstruction(Val, 5, 2); 1584 unsigned imm = fieldFromInstruction(Val, 7, 5); 1585 unsigned U = fieldFromInstruction(Val, 12, 1); 1586 1587 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1588 switch (type) { 1589 case 0: 1590 ShOp = ARM_AM::lsl; 1591 break; 1592 case 1: 1593 ShOp = ARM_AM::lsr; 1594 break; 1595 case 2: 1596 ShOp = ARM_AM::asr; 1597 break; 1598 case 3: 1599 ShOp = ARM_AM::ror; 1600 break; 1601 } 1602 1603 if (ShOp == ARM_AM::ror && imm == 0) 1604 ShOp = ARM_AM::rrx; 1605 1606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1607 return MCDisassembler::Fail; 1608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1609 return MCDisassembler::Fail; 1610 unsigned shift; 1611 if (U) 1612 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1613 else 1614 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1615 Inst.addOperand(MCOperand::createImm(shift)); 1616 1617 return S; 1618 } 1619 1620 static DecodeStatus 1621 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1622 uint64_t Address, const void *Decoder) { 1623 DecodeStatus S = MCDisassembler::Success; 1624 1625 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1626 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1627 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1628 unsigned type = fieldFromInstruction(Insn, 22, 1); 1629 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1630 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1631 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1632 unsigned W = fieldFromInstruction(Insn, 21, 1); 1633 unsigned P = fieldFromInstruction(Insn, 24, 1); 1634 unsigned Rt2 = Rt + 1; 1635 1636 bool writeback = (W == 1) | (P == 0); 1637 1638 // For {LD,ST}RD, Rt must be even, else undefined. 1639 switch (Inst.getOpcode()) { 1640 case ARM::STRD: 1641 case ARM::STRD_PRE: 1642 case ARM::STRD_POST: 1643 case ARM::LDRD: 1644 case ARM::LDRD_PRE: 1645 case ARM::LDRD_POST: 1646 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1647 break; 1648 default: 1649 break; 1650 } 1651 switch (Inst.getOpcode()) { 1652 case ARM::STRD: 1653 case ARM::STRD_PRE: 1654 case ARM::STRD_POST: 1655 if (P == 0 && W == 1) 1656 S = MCDisassembler::SoftFail; 1657 1658 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1659 S = MCDisassembler::SoftFail; 1660 if (type && Rm == 15) 1661 S = MCDisassembler::SoftFail; 1662 if (Rt2 == 15) 1663 S = MCDisassembler::SoftFail; 1664 if (!type && fieldFromInstruction(Insn, 8, 4)) 1665 S = MCDisassembler::SoftFail; 1666 break; 1667 case ARM::STRH: 1668 case ARM::STRH_PRE: 1669 case ARM::STRH_POST: 1670 if (Rt == 15) 1671 S = MCDisassembler::SoftFail; 1672 if (writeback && (Rn == 15 || Rn == Rt)) 1673 S = MCDisassembler::SoftFail; 1674 if (!type && Rm == 15) 1675 S = MCDisassembler::SoftFail; 1676 break; 1677 case ARM::LDRD: 1678 case ARM::LDRD_PRE: 1679 case ARM::LDRD_POST: 1680 if (type && Rn == 15) { 1681 if (Rt2 == 15) 1682 S = MCDisassembler::SoftFail; 1683 break; 1684 } 1685 if (P == 0 && W == 1) 1686 S = MCDisassembler::SoftFail; 1687 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1688 S = MCDisassembler::SoftFail; 1689 if (!type && writeback && Rn == 15) 1690 S = MCDisassembler::SoftFail; 1691 if (writeback && (Rn == Rt || Rn == Rt2)) 1692 S = MCDisassembler::SoftFail; 1693 break; 1694 case ARM::LDRH: 1695 case ARM::LDRH_PRE: 1696 case ARM::LDRH_POST: 1697 if (type && Rn == 15) { 1698 if (Rt == 15) 1699 S = MCDisassembler::SoftFail; 1700 break; 1701 } 1702 if (Rt == 15) 1703 S = MCDisassembler::SoftFail; 1704 if (!type && Rm == 15) 1705 S = MCDisassembler::SoftFail; 1706 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1707 S = MCDisassembler::SoftFail; 1708 break; 1709 case ARM::LDRSH: 1710 case ARM::LDRSH_PRE: 1711 case ARM::LDRSH_POST: 1712 case ARM::LDRSB: 1713 case ARM::LDRSB_PRE: 1714 case ARM::LDRSB_POST: 1715 if (type && Rn == 15) { 1716 if (Rt == 15) 1717 S = MCDisassembler::SoftFail; 1718 break; 1719 } 1720 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1721 S = MCDisassembler::SoftFail; 1722 if (!type && (Rt == 15 || Rm == 15)) 1723 S = MCDisassembler::SoftFail; 1724 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1725 S = MCDisassembler::SoftFail; 1726 break; 1727 default: 1728 break; 1729 } 1730 1731 if (writeback) { // Writeback 1732 if (P) 1733 U |= ARMII::IndexModePre << 9; 1734 else 1735 U |= ARMII::IndexModePost << 9; 1736 1737 // On stores, the writeback operand precedes Rt. 1738 switch (Inst.getOpcode()) { 1739 case ARM::STRD: 1740 case ARM::STRD_PRE: 1741 case ARM::STRD_POST: 1742 case ARM::STRH: 1743 case ARM::STRH_PRE: 1744 case ARM::STRH_POST: 1745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1746 return MCDisassembler::Fail; 1747 break; 1748 default: 1749 break; 1750 } 1751 } 1752 1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1754 return MCDisassembler::Fail; 1755 switch (Inst.getOpcode()) { 1756 case ARM::STRD: 1757 case ARM::STRD_PRE: 1758 case ARM::STRD_POST: 1759 case ARM::LDRD: 1760 case ARM::LDRD_PRE: 1761 case ARM::LDRD_POST: 1762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1763 return MCDisassembler::Fail; 1764 break; 1765 default: 1766 break; 1767 } 1768 1769 if (writeback) { 1770 // On loads, the writeback operand comes after Rt. 1771 switch (Inst.getOpcode()) { 1772 case ARM::LDRD: 1773 case ARM::LDRD_PRE: 1774 case ARM::LDRD_POST: 1775 case ARM::LDRH: 1776 case ARM::LDRH_PRE: 1777 case ARM::LDRH_POST: 1778 case ARM::LDRSH: 1779 case ARM::LDRSH_PRE: 1780 case ARM::LDRSH_POST: 1781 case ARM::LDRSB: 1782 case ARM::LDRSB_PRE: 1783 case ARM::LDRSB_POST: 1784 case ARM::LDRHTr: 1785 case ARM::LDRSBTr: 1786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1787 return MCDisassembler::Fail; 1788 break; 1789 default: 1790 break; 1791 } 1792 } 1793 1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1795 return MCDisassembler::Fail; 1796 1797 if (type) { 1798 Inst.addOperand(MCOperand::createReg(0)); 1799 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1800 } else { 1801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1802 return MCDisassembler::Fail; 1803 Inst.addOperand(MCOperand::createImm(U)); 1804 } 1805 1806 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1807 return MCDisassembler::Fail; 1808 1809 return S; 1810 } 1811 1812 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1813 uint64_t Address, const void *Decoder) { 1814 DecodeStatus S = MCDisassembler::Success; 1815 1816 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1817 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1818 1819 switch (mode) { 1820 case 0: 1821 mode = ARM_AM::da; 1822 break; 1823 case 1: 1824 mode = ARM_AM::ia; 1825 break; 1826 case 2: 1827 mode = ARM_AM::db; 1828 break; 1829 case 3: 1830 mode = ARM_AM::ib; 1831 break; 1832 } 1833 1834 Inst.addOperand(MCOperand::createImm(mode)); 1835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1836 return MCDisassembler::Fail; 1837 1838 return S; 1839 } 1840 1841 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1842 uint64_t Address, const void *Decoder) { 1843 DecodeStatus S = MCDisassembler::Success; 1844 1845 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1846 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1847 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1848 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1849 1850 if (pred == 0xF) 1851 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1852 1853 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1854 return MCDisassembler::Fail; 1855 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1856 return MCDisassembler::Fail; 1857 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1858 return MCDisassembler::Fail; 1859 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1860 return MCDisassembler::Fail; 1861 return S; 1862 } 1863 1864 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1865 unsigned Insn, 1866 uint64_t Address, const void *Decoder) { 1867 DecodeStatus S = MCDisassembler::Success; 1868 1869 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1870 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1871 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1872 1873 if (pred == 0xF) { 1874 // Ambiguous with RFE and SRS 1875 switch (Inst.getOpcode()) { 1876 case ARM::LDMDA: 1877 Inst.setOpcode(ARM::RFEDA); 1878 break; 1879 case ARM::LDMDA_UPD: 1880 Inst.setOpcode(ARM::RFEDA_UPD); 1881 break; 1882 case ARM::LDMDB: 1883 Inst.setOpcode(ARM::RFEDB); 1884 break; 1885 case ARM::LDMDB_UPD: 1886 Inst.setOpcode(ARM::RFEDB_UPD); 1887 break; 1888 case ARM::LDMIA: 1889 Inst.setOpcode(ARM::RFEIA); 1890 break; 1891 case ARM::LDMIA_UPD: 1892 Inst.setOpcode(ARM::RFEIA_UPD); 1893 break; 1894 case ARM::LDMIB: 1895 Inst.setOpcode(ARM::RFEIB); 1896 break; 1897 case ARM::LDMIB_UPD: 1898 Inst.setOpcode(ARM::RFEIB_UPD); 1899 break; 1900 case ARM::STMDA: 1901 Inst.setOpcode(ARM::SRSDA); 1902 break; 1903 case ARM::STMDA_UPD: 1904 Inst.setOpcode(ARM::SRSDA_UPD); 1905 break; 1906 case ARM::STMDB: 1907 Inst.setOpcode(ARM::SRSDB); 1908 break; 1909 case ARM::STMDB_UPD: 1910 Inst.setOpcode(ARM::SRSDB_UPD); 1911 break; 1912 case ARM::STMIA: 1913 Inst.setOpcode(ARM::SRSIA); 1914 break; 1915 case ARM::STMIA_UPD: 1916 Inst.setOpcode(ARM::SRSIA_UPD); 1917 break; 1918 case ARM::STMIB: 1919 Inst.setOpcode(ARM::SRSIB); 1920 break; 1921 case ARM::STMIB_UPD: 1922 Inst.setOpcode(ARM::SRSIB_UPD); 1923 break; 1924 default: 1925 return MCDisassembler::Fail; 1926 } 1927 1928 // For stores (which become SRS's, the only operand is the mode. 1929 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1930 // Check SRS encoding constraints 1931 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1932 fieldFromInstruction(Insn, 20, 1) == 0)) 1933 return MCDisassembler::Fail; 1934 1935 Inst.addOperand( 1936 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1937 return S; 1938 } 1939 1940 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1941 } 1942 1943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1944 return MCDisassembler::Fail; 1945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1946 return MCDisassembler::Fail; // Tied 1947 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1948 return MCDisassembler::Fail; 1949 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1950 return MCDisassembler::Fail; 1951 1952 return S; 1953 } 1954 1955 // Check for UNPREDICTABLE predicated ESB instruction 1956 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 1957 uint64_t Address, const void *Decoder) { 1958 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1959 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 1960 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 1961 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 1962 1963 DecodeStatus S = MCDisassembler::Success; 1964 1965 Inst.addOperand(MCOperand::createImm(imm8)); 1966 1967 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1968 return MCDisassembler::Fail; 1969 1970 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 1971 // so all predicates should be allowed. 1972 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 1973 S = MCDisassembler::SoftFail; 1974 1975 return S; 1976 } 1977 1978 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1979 uint64_t Address, const void *Decoder) { 1980 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1981 unsigned M = fieldFromInstruction(Insn, 17, 1); 1982 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1983 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1984 1985 DecodeStatus S = MCDisassembler::Success; 1986 1987 // This decoder is called from multiple location that do not check 1988 // the full encoding is valid before they do. 1989 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1990 fieldFromInstruction(Insn, 16, 1) != 0 || 1991 fieldFromInstruction(Insn, 20, 8) != 0x10) 1992 return MCDisassembler::Fail; 1993 1994 // imod == '01' --> UNPREDICTABLE 1995 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1996 // return failure here. The '01' imod value is unprintable, so there's 1997 // nothing useful we could do even if we returned UNPREDICTABLE. 1998 1999 if (imod == 1) return MCDisassembler::Fail; 2000 2001 if (imod && M) { 2002 Inst.setOpcode(ARM::CPS3p); 2003 Inst.addOperand(MCOperand::createImm(imod)); 2004 Inst.addOperand(MCOperand::createImm(iflags)); 2005 Inst.addOperand(MCOperand::createImm(mode)); 2006 } else if (imod && !M) { 2007 Inst.setOpcode(ARM::CPS2p); 2008 Inst.addOperand(MCOperand::createImm(imod)); 2009 Inst.addOperand(MCOperand::createImm(iflags)); 2010 if (mode) S = MCDisassembler::SoftFail; 2011 } else if (!imod && M) { 2012 Inst.setOpcode(ARM::CPS1p); 2013 Inst.addOperand(MCOperand::createImm(mode)); 2014 if (iflags) S = MCDisassembler::SoftFail; 2015 } else { 2016 // imod == '00' && M == '0' --> UNPREDICTABLE 2017 Inst.setOpcode(ARM::CPS1p); 2018 Inst.addOperand(MCOperand::createImm(mode)); 2019 S = MCDisassembler::SoftFail; 2020 } 2021 2022 return S; 2023 } 2024 2025 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2026 uint64_t Address, const void *Decoder) { 2027 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2028 unsigned M = fieldFromInstruction(Insn, 8, 1); 2029 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2030 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2031 2032 DecodeStatus S = MCDisassembler::Success; 2033 2034 // imod == '01' --> UNPREDICTABLE 2035 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2036 // return failure here. The '01' imod value is unprintable, so there's 2037 // nothing useful we could do even if we returned UNPREDICTABLE. 2038 2039 if (imod == 1) return MCDisassembler::Fail; 2040 2041 if (imod && M) { 2042 Inst.setOpcode(ARM::t2CPS3p); 2043 Inst.addOperand(MCOperand::createImm(imod)); 2044 Inst.addOperand(MCOperand::createImm(iflags)); 2045 Inst.addOperand(MCOperand::createImm(mode)); 2046 } else if (imod && !M) { 2047 Inst.setOpcode(ARM::t2CPS2p); 2048 Inst.addOperand(MCOperand::createImm(imod)); 2049 Inst.addOperand(MCOperand::createImm(iflags)); 2050 if (mode) S = MCDisassembler::SoftFail; 2051 } else if (!imod && M) { 2052 Inst.setOpcode(ARM::t2CPS1p); 2053 Inst.addOperand(MCOperand::createImm(mode)); 2054 if (iflags) S = MCDisassembler::SoftFail; 2055 } else { 2056 // imod == '00' && M == '0' --> this is a HINT instruction 2057 int imm = fieldFromInstruction(Insn, 0, 8); 2058 // HINT are defined only for immediate in [0..4] 2059 if(imm > 4) return MCDisassembler::Fail; 2060 Inst.setOpcode(ARM::t2HINT); 2061 Inst.addOperand(MCOperand::createImm(imm)); 2062 } 2063 2064 return S; 2065 } 2066 2067 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2068 uint64_t Address, const void *Decoder) { 2069 DecodeStatus S = MCDisassembler::Success; 2070 2071 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2072 unsigned imm = 0; 2073 2074 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2075 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2076 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2077 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2078 2079 if (Inst.getOpcode() == ARM::t2MOVTi16) 2080 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2081 return MCDisassembler::Fail; 2082 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2083 return MCDisassembler::Fail; 2084 2085 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2086 Inst.addOperand(MCOperand::createImm(imm)); 2087 2088 return S; 2089 } 2090 2091 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2092 uint64_t Address, const void *Decoder) { 2093 DecodeStatus S = MCDisassembler::Success; 2094 2095 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2096 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2097 unsigned imm = 0; 2098 2099 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2100 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2101 2102 if (Inst.getOpcode() == ARM::MOVTi16) 2103 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2104 return MCDisassembler::Fail; 2105 2106 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2107 return MCDisassembler::Fail; 2108 2109 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2110 Inst.addOperand(MCOperand::createImm(imm)); 2111 2112 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2113 return MCDisassembler::Fail; 2114 2115 return S; 2116 } 2117 2118 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2119 uint64_t Address, const void *Decoder) { 2120 DecodeStatus S = MCDisassembler::Success; 2121 2122 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2123 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2124 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2125 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2126 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2127 2128 if (pred == 0xF) 2129 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2130 2131 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2132 return MCDisassembler::Fail; 2133 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2134 return MCDisassembler::Fail; 2135 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2136 return MCDisassembler::Fail; 2137 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2138 return MCDisassembler::Fail; 2139 2140 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2141 return MCDisassembler::Fail; 2142 2143 return S; 2144 } 2145 2146 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2147 uint64_t Address, const void *Decoder) { 2148 DecodeStatus S = MCDisassembler::Success; 2149 2150 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2151 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2152 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2153 2154 if (Pred == 0xF) 2155 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2156 2157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2158 return MCDisassembler::Fail; 2159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2160 return MCDisassembler::Fail; 2161 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2162 return MCDisassembler::Fail; 2163 2164 return S; 2165 } 2166 2167 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2168 uint64_t Address, const void *Decoder) { 2169 DecodeStatus S = MCDisassembler::Success; 2170 2171 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2172 2173 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2174 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2175 2176 if (!FeatureBits[ARM::HasV8_1aOps] || 2177 !FeatureBits[ARM::HasV8Ops]) 2178 return MCDisassembler::Fail; 2179 2180 // Decoder can be called from DecodeTST, which does not check the full 2181 // encoding is valid. 2182 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2183 fieldFromInstruction(Insn, 4,4) != 0) 2184 return MCDisassembler::Fail; 2185 if (fieldFromInstruction(Insn, 10,10) != 0 || 2186 fieldFromInstruction(Insn, 0,4) != 0) 2187 S = MCDisassembler::SoftFail; 2188 2189 Inst.setOpcode(ARM::SETPAN); 2190 Inst.addOperand(MCOperand::createImm(Imm)); 2191 2192 return S; 2193 } 2194 2195 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2196 uint64_t Address, const void *Decoder) { 2197 DecodeStatus S = MCDisassembler::Success; 2198 2199 unsigned add = fieldFromInstruction(Val, 12, 1); 2200 unsigned imm = fieldFromInstruction(Val, 0, 12); 2201 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2202 2203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2204 return MCDisassembler::Fail; 2205 2206 if (!add) imm *= -1; 2207 if (imm == 0 && !add) imm = INT32_MIN; 2208 Inst.addOperand(MCOperand::createImm(imm)); 2209 if (Rn == 15) 2210 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2211 2212 return S; 2213 } 2214 2215 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2216 uint64_t Address, const void *Decoder) { 2217 DecodeStatus S = MCDisassembler::Success; 2218 2219 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2220 // U == 1 to add imm, 0 to subtract it. 2221 unsigned U = fieldFromInstruction(Val, 8, 1); 2222 unsigned imm = fieldFromInstruction(Val, 0, 8); 2223 2224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2225 return MCDisassembler::Fail; 2226 2227 if (U) 2228 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2229 else 2230 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2231 2232 return S; 2233 } 2234 2235 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2236 uint64_t Address, const void *Decoder) { 2237 DecodeStatus S = MCDisassembler::Success; 2238 2239 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2240 // U == 1 to add imm, 0 to subtract it. 2241 unsigned U = fieldFromInstruction(Val, 8, 1); 2242 unsigned imm = fieldFromInstruction(Val, 0, 8); 2243 2244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2245 return MCDisassembler::Fail; 2246 2247 if (U) 2248 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2249 else 2250 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2251 2252 return S; 2253 } 2254 2255 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2256 uint64_t Address, const void *Decoder) { 2257 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2258 } 2259 2260 static DecodeStatus 2261 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2262 uint64_t Address, const void *Decoder) { 2263 DecodeStatus Status = MCDisassembler::Success; 2264 2265 // Note the J1 and J2 values are from the encoded instruction. So here 2266 // change them to I1 and I2 values via as documented: 2267 // I1 = NOT(J1 EOR S); 2268 // I2 = NOT(J2 EOR S); 2269 // and build the imm32 with one trailing zero as documented: 2270 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2271 unsigned S = fieldFromInstruction(Insn, 26, 1); 2272 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2273 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2274 unsigned I1 = !(J1 ^ S); 2275 unsigned I2 = !(J2 ^ S); 2276 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2277 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2278 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2279 int imm32 = SignExtend32<25>(tmp << 1); 2280 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2281 true, 4, Inst, Decoder)) 2282 Inst.addOperand(MCOperand::createImm(imm32)); 2283 2284 return Status; 2285 } 2286 2287 static DecodeStatus 2288 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2289 uint64_t Address, const void *Decoder) { 2290 DecodeStatus S = MCDisassembler::Success; 2291 2292 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2293 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2294 2295 if (pred == 0xF) { 2296 Inst.setOpcode(ARM::BLXi); 2297 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2298 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2299 true, 4, Inst, Decoder)) 2300 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2301 return S; 2302 } 2303 2304 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2305 true, 4, Inst, Decoder)) 2306 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2307 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2308 return MCDisassembler::Fail; 2309 2310 return S; 2311 } 2312 2313 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2314 uint64_t Address, const void *Decoder) { 2315 DecodeStatus S = MCDisassembler::Success; 2316 2317 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2318 unsigned align = fieldFromInstruction(Val, 4, 2); 2319 2320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2321 return MCDisassembler::Fail; 2322 if (!align) 2323 Inst.addOperand(MCOperand::createImm(0)); 2324 else 2325 Inst.addOperand(MCOperand::createImm(4 << align)); 2326 2327 return S; 2328 } 2329 2330 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2331 uint64_t Address, const void *Decoder) { 2332 DecodeStatus S = MCDisassembler::Success; 2333 2334 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2335 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2336 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2337 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2338 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2339 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2340 2341 // First output register 2342 switch (Inst.getOpcode()) { 2343 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2344 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2345 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2346 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2347 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2348 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2349 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2350 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2351 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2352 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2353 return MCDisassembler::Fail; 2354 break; 2355 case ARM::VLD2b16: 2356 case ARM::VLD2b32: 2357 case ARM::VLD2b8: 2358 case ARM::VLD2b16wb_fixed: 2359 case ARM::VLD2b16wb_register: 2360 case ARM::VLD2b32wb_fixed: 2361 case ARM::VLD2b32wb_register: 2362 case ARM::VLD2b8wb_fixed: 2363 case ARM::VLD2b8wb_register: 2364 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2365 return MCDisassembler::Fail; 2366 break; 2367 default: 2368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2369 return MCDisassembler::Fail; 2370 } 2371 2372 // Second output register 2373 switch (Inst.getOpcode()) { 2374 case ARM::VLD3d8: 2375 case ARM::VLD3d16: 2376 case ARM::VLD3d32: 2377 case ARM::VLD3d8_UPD: 2378 case ARM::VLD3d16_UPD: 2379 case ARM::VLD3d32_UPD: 2380 case ARM::VLD4d8: 2381 case ARM::VLD4d16: 2382 case ARM::VLD4d32: 2383 case ARM::VLD4d8_UPD: 2384 case ARM::VLD4d16_UPD: 2385 case ARM::VLD4d32_UPD: 2386 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2387 return MCDisassembler::Fail; 2388 break; 2389 case ARM::VLD3q8: 2390 case ARM::VLD3q16: 2391 case ARM::VLD3q32: 2392 case ARM::VLD3q8_UPD: 2393 case ARM::VLD3q16_UPD: 2394 case ARM::VLD3q32_UPD: 2395 case ARM::VLD4q8: 2396 case ARM::VLD4q16: 2397 case ARM::VLD4q32: 2398 case ARM::VLD4q8_UPD: 2399 case ARM::VLD4q16_UPD: 2400 case ARM::VLD4q32_UPD: 2401 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2402 return MCDisassembler::Fail; 2403 default: 2404 break; 2405 } 2406 2407 // Third output register 2408 switch(Inst.getOpcode()) { 2409 case ARM::VLD3d8: 2410 case ARM::VLD3d16: 2411 case ARM::VLD3d32: 2412 case ARM::VLD3d8_UPD: 2413 case ARM::VLD3d16_UPD: 2414 case ARM::VLD3d32_UPD: 2415 case ARM::VLD4d8: 2416 case ARM::VLD4d16: 2417 case ARM::VLD4d32: 2418 case ARM::VLD4d8_UPD: 2419 case ARM::VLD4d16_UPD: 2420 case ARM::VLD4d32_UPD: 2421 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2422 return MCDisassembler::Fail; 2423 break; 2424 case ARM::VLD3q8: 2425 case ARM::VLD3q16: 2426 case ARM::VLD3q32: 2427 case ARM::VLD3q8_UPD: 2428 case ARM::VLD3q16_UPD: 2429 case ARM::VLD3q32_UPD: 2430 case ARM::VLD4q8: 2431 case ARM::VLD4q16: 2432 case ARM::VLD4q32: 2433 case ARM::VLD4q8_UPD: 2434 case ARM::VLD4q16_UPD: 2435 case ARM::VLD4q32_UPD: 2436 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2437 return MCDisassembler::Fail; 2438 break; 2439 default: 2440 break; 2441 } 2442 2443 // Fourth output register 2444 switch (Inst.getOpcode()) { 2445 case ARM::VLD4d8: 2446 case ARM::VLD4d16: 2447 case ARM::VLD4d32: 2448 case ARM::VLD4d8_UPD: 2449 case ARM::VLD4d16_UPD: 2450 case ARM::VLD4d32_UPD: 2451 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2452 return MCDisassembler::Fail; 2453 break; 2454 case ARM::VLD4q8: 2455 case ARM::VLD4q16: 2456 case ARM::VLD4q32: 2457 case ARM::VLD4q8_UPD: 2458 case ARM::VLD4q16_UPD: 2459 case ARM::VLD4q32_UPD: 2460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2461 return MCDisassembler::Fail; 2462 break; 2463 default: 2464 break; 2465 } 2466 2467 // Writeback operand 2468 switch (Inst.getOpcode()) { 2469 case ARM::VLD1d8wb_fixed: 2470 case ARM::VLD1d16wb_fixed: 2471 case ARM::VLD1d32wb_fixed: 2472 case ARM::VLD1d64wb_fixed: 2473 case ARM::VLD1d8wb_register: 2474 case ARM::VLD1d16wb_register: 2475 case ARM::VLD1d32wb_register: 2476 case ARM::VLD1d64wb_register: 2477 case ARM::VLD1q8wb_fixed: 2478 case ARM::VLD1q16wb_fixed: 2479 case ARM::VLD1q32wb_fixed: 2480 case ARM::VLD1q64wb_fixed: 2481 case ARM::VLD1q8wb_register: 2482 case ARM::VLD1q16wb_register: 2483 case ARM::VLD1q32wb_register: 2484 case ARM::VLD1q64wb_register: 2485 case ARM::VLD1d8Twb_fixed: 2486 case ARM::VLD1d8Twb_register: 2487 case ARM::VLD1d16Twb_fixed: 2488 case ARM::VLD1d16Twb_register: 2489 case ARM::VLD1d32Twb_fixed: 2490 case ARM::VLD1d32Twb_register: 2491 case ARM::VLD1d64Twb_fixed: 2492 case ARM::VLD1d64Twb_register: 2493 case ARM::VLD1d8Qwb_fixed: 2494 case ARM::VLD1d8Qwb_register: 2495 case ARM::VLD1d16Qwb_fixed: 2496 case ARM::VLD1d16Qwb_register: 2497 case ARM::VLD1d32Qwb_fixed: 2498 case ARM::VLD1d32Qwb_register: 2499 case ARM::VLD1d64Qwb_fixed: 2500 case ARM::VLD1d64Qwb_register: 2501 case ARM::VLD2d8wb_fixed: 2502 case ARM::VLD2d16wb_fixed: 2503 case ARM::VLD2d32wb_fixed: 2504 case ARM::VLD2q8wb_fixed: 2505 case ARM::VLD2q16wb_fixed: 2506 case ARM::VLD2q32wb_fixed: 2507 case ARM::VLD2d8wb_register: 2508 case ARM::VLD2d16wb_register: 2509 case ARM::VLD2d32wb_register: 2510 case ARM::VLD2q8wb_register: 2511 case ARM::VLD2q16wb_register: 2512 case ARM::VLD2q32wb_register: 2513 case ARM::VLD2b8wb_fixed: 2514 case ARM::VLD2b16wb_fixed: 2515 case ARM::VLD2b32wb_fixed: 2516 case ARM::VLD2b8wb_register: 2517 case ARM::VLD2b16wb_register: 2518 case ARM::VLD2b32wb_register: 2519 Inst.addOperand(MCOperand::createImm(0)); 2520 break; 2521 case ARM::VLD3d8_UPD: 2522 case ARM::VLD3d16_UPD: 2523 case ARM::VLD3d32_UPD: 2524 case ARM::VLD3q8_UPD: 2525 case ARM::VLD3q16_UPD: 2526 case ARM::VLD3q32_UPD: 2527 case ARM::VLD4d8_UPD: 2528 case ARM::VLD4d16_UPD: 2529 case ARM::VLD4d32_UPD: 2530 case ARM::VLD4q8_UPD: 2531 case ARM::VLD4q16_UPD: 2532 case ARM::VLD4q32_UPD: 2533 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 break; 2536 default: 2537 break; 2538 } 2539 2540 // AddrMode6 Base (register+alignment) 2541 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2542 return MCDisassembler::Fail; 2543 2544 // AddrMode6 Offset (register) 2545 switch (Inst.getOpcode()) { 2546 default: 2547 // The below have been updated to have explicit am6offset split 2548 // between fixed and register offset. For those instructions not 2549 // yet updated, we need to add an additional reg0 operand for the 2550 // fixed variant. 2551 // 2552 // The fixed offset encodes as Rm == 0xd, so we check for that. 2553 if (Rm == 0xd) { 2554 Inst.addOperand(MCOperand::createReg(0)); 2555 break; 2556 } 2557 // Fall through to handle the register offset variant. 2558 LLVM_FALLTHROUGH; 2559 case ARM::VLD1d8wb_fixed: 2560 case ARM::VLD1d16wb_fixed: 2561 case ARM::VLD1d32wb_fixed: 2562 case ARM::VLD1d64wb_fixed: 2563 case ARM::VLD1d8Twb_fixed: 2564 case ARM::VLD1d16Twb_fixed: 2565 case ARM::VLD1d32Twb_fixed: 2566 case ARM::VLD1d64Twb_fixed: 2567 case ARM::VLD1d8Qwb_fixed: 2568 case ARM::VLD1d16Qwb_fixed: 2569 case ARM::VLD1d32Qwb_fixed: 2570 case ARM::VLD1d64Qwb_fixed: 2571 case ARM::VLD1d8wb_register: 2572 case ARM::VLD1d16wb_register: 2573 case ARM::VLD1d32wb_register: 2574 case ARM::VLD1d64wb_register: 2575 case ARM::VLD1q8wb_fixed: 2576 case ARM::VLD1q16wb_fixed: 2577 case ARM::VLD1q32wb_fixed: 2578 case ARM::VLD1q64wb_fixed: 2579 case ARM::VLD1q8wb_register: 2580 case ARM::VLD1q16wb_register: 2581 case ARM::VLD1q32wb_register: 2582 case ARM::VLD1q64wb_register: 2583 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2584 // variant encodes Rm == 0xf. Anything else is a register offset post- 2585 // increment and we need to add the register operand to the instruction. 2586 if (Rm != 0xD && Rm != 0xF && 2587 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2588 return MCDisassembler::Fail; 2589 break; 2590 case ARM::VLD2d8wb_fixed: 2591 case ARM::VLD2d16wb_fixed: 2592 case ARM::VLD2d32wb_fixed: 2593 case ARM::VLD2b8wb_fixed: 2594 case ARM::VLD2b16wb_fixed: 2595 case ARM::VLD2b32wb_fixed: 2596 case ARM::VLD2q8wb_fixed: 2597 case ARM::VLD2q16wb_fixed: 2598 case ARM::VLD2q32wb_fixed: 2599 break; 2600 } 2601 2602 return S; 2603 } 2604 2605 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2606 uint64_t Address, const void *Decoder) { 2607 unsigned type = fieldFromInstruction(Insn, 8, 4); 2608 unsigned align = fieldFromInstruction(Insn, 4, 2); 2609 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2610 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2611 if (type == 10 && align == 3) return MCDisassembler::Fail; 2612 2613 unsigned load = fieldFromInstruction(Insn, 21, 1); 2614 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2615 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2616 } 2617 2618 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2619 uint64_t Address, const void *Decoder) { 2620 unsigned size = fieldFromInstruction(Insn, 6, 2); 2621 if (size == 3) return MCDisassembler::Fail; 2622 2623 unsigned type = fieldFromInstruction(Insn, 8, 4); 2624 unsigned align = fieldFromInstruction(Insn, 4, 2); 2625 if (type == 8 && align == 3) return MCDisassembler::Fail; 2626 if (type == 9 && align == 3) return MCDisassembler::Fail; 2627 2628 unsigned load = fieldFromInstruction(Insn, 21, 1); 2629 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2630 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2631 } 2632 2633 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2634 uint64_t Address, const void *Decoder) { 2635 unsigned size = fieldFromInstruction(Insn, 6, 2); 2636 if (size == 3) return MCDisassembler::Fail; 2637 2638 unsigned align = fieldFromInstruction(Insn, 4, 2); 2639 if (align & 2) return MCDisassembler::Fail; 2640 2641 unsigned load = fieldFromInstruction(Insn, 21, 1); 2642 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2643 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2644 } 2645 2646 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2647 uint64_t Address, const void *Decoder) { 2648 unsigned size = fieldFromInstruction(Insn, 6, 2); 2649 if (size == 3) return MCDisassembler::Fail; 2650 2651 unsigned load = fieldFromInstruction(Insn, 21, 1); 2652 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2653 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2654 } 2655 2656 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2657 uint64_t Address, const void *Decoder) { 2658 DecodeStatus S = MCDisassembler::Success; 2659 2660 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2661 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2662 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2663 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2664 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2665 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2666 2667 // Writeback Operand 2668 switch (Inst.getOpcode()) { 2669 case ARM::VST1d8wb_fixed: 2670 case ARM::VST1d16wb_fixed: 2671 case ARM::VST1d32wb_fixed: 2672 case ARM::VST1d64wb_fixed: 2673 case ARM::VST1d8wb_register: 2674 case ARM::VST1d16wb_register: 2675 case ARM::VST1d32wb_register: 2676 case ARM::VST1d64wb_register: 2677 case ARM::VST1q8wb_fixed: 2678 case ARM::VST1q16wb_fixed: 2679 case ARM::VST1q32wb_fixed: 2680 case ARM::VST1q64wb_fixed: 2681 case ARM::VST1q8wb_register: 2682 case ARM::VST1q16wb_register: 2683 case ARM::VST1q32wb_register: 2684 case ARM::VST1q64wb_register: 2685 case ARM::VST1d8Twb_fixed: 2686 case ARM::VST1d16Twb_fixed: 2687 case ARM::VST1d32Twb_fixed: 2688 case ARM::VST1d64Twb_fixed: 2689 case ARM::VST1d8Twb_register: 2690 case ARM::VST1d16Twb_register: 2691 case ARM::VST1d32Twb_register: 2692 case ARM::VST1d64Twb_register: 2693 case ARM::VST1d8Qwb_fixed: 2694 case ARM::VST1d16Qwb_fixed: 2695 case ARM::VST1d32Qwb_fixed: 2696 case ARM::VST1d64Qwb_fixed: 2697 case ARM::VST1d8Qwb_register: 2698 case ARM::VST1d16Qwb_register: 2699 case ARM::VST1d32Qwb_register: 2700 case ARM::VST1d64Qwb_register: 2701 case ARM::VST2d8wb_fixed: 2702 case ARM::VST2d16wb_fixed: 2703 case ARM::VST2d32wb_fixed: 2704 case ARM::VST2d8wb_register: 2705 case ARM::VST2d16wb_register: 2706 case ARM::VST2d32wb_register: 2707 case ARM::VST2q8wb_fixed: 2708 case ARM::VST2q16wb_fixed: 2709 case ARM::VST2q32wb_fixed: 2710 case ARM::VST2q8wb_register: 2711 case ARM::VST2q16wb_register: 2712 case ARM::VST2q32wb_register: 2713 case ARM::VST2b8wb_fixed: 2714 case ARM::VST2b16wb_fixed: 2715 case ARM::VST2b32wb_fixed: 2716 case ARM::VST2b8wb_register: 2717 case ARM::VST2b16wb_register: 2718 case ARM::VST2b32wb_register: 2719 if (Rm == 0xF) 2720 return MCDisassembler::Fail; 2721 Inst.addOperand(MCOperand::createImm(0)); 2722 break; 2723 case ARM::VST3d8_UPD: 2724 case ARM::VST3d16_UPD: 2725 case ARM::VST3d32_UPD: 2726 case ARM::VST3q8_UPD: 2727 case ARM::VST3q16_UPD: 2728 case ARM::VST3q32_UPD: 2729 case ARM::VST4d8_UPD: 2730 case ARM::VST4d16_UPD: 2731 case ARM::VST4d32_UPD: 2732 case ARM::VST4q8_UPD: 2733 case ARM::VST4q16_UPD: 2734 case ARM::VST4q32_UPD: 2735 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 break; 2738 default: 2739 break; 2740 } 2741 2742 // AddrMode6 Base (register+alignment) 2743 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2744 return MCDisassembler::Fail; 2745 2746 // AddrMode6 Offset (register) 2747 switch (Inst.getOpcode()) { 2748 default: 2749 if (Rm == 0xD) 2750 Inst.addOperand(MCOperand::createReg(0)); 2751 else if (Rm != 0xF) { 2752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 } 2755 break; 2756 case ARM::VST1d8wb_fixed: 2757 case ARM::VST1d16wb_fixed: 2758 case ARM::VST1d32wb_fixed: 2759 case ARM::VST1d64wb_fixed: 2760 case ARM::VST1q8wb_fixed: 2761 case ARM::VST1q16wb_fixed: 2762 case ARM::VST1q32wb_fixed: 2763 case ARM::VST1q64wb_fixed: 2764 case ARM::VST1d8Twb_fixed: 2765 case ARM::VST1d16Twb_fixed: 2766 case ARM::VST1d32Twb_fixed: 2767 case ARM::VST1d64Twb_fixed: 2768 case ARM::VST1d8Qwb_fixed: 2769 case ARM::VST1d16Qwb_fixed: 2770 case ARM::VST1d32Qwb_fixed: 2771 case ARM::VST1d64Qwb_fixed: 2772 case ARM::VST2d8wb_fixed: 2773 case ARM::VST2d16wb_fixed: 2774 case ARM::VST2d32wb_fixed: 2775 case ARM::VST2q8wb_fixed: 2776 case ARM::VST2q16wb_fixed: 2777 case ARM::VST2q32wb_fixed: 2778 case ARM::VST2b8wb_fixed: 2779 case ARM::VST2b16wb_fixed: 2780 case ARM::VST2b32wb_fixed: 2781 break; 2782 } 2783 2784 2785 // First input register 2786 switch (Inst.getOpcode()) { 2787 case ARM::VST1q16: 2788 case ARM::VST1q32: 2789 case ARM::VST1q64: 2790 case ARM::VST1q8: 2791 case ARM::VST1q16wb_fixed: 2792 case ARM::VST1q16wb_register: 2793 case ARM::VST1q32wb_fixed: 2794 case ARM::VST1q32wb_register: 2795 case ARM::VST1q64wb_fixed: 2796 case ARM::VST1q64wb_register: 2797 case ARM::VST1q8wb_fixed: 2798 case ARM::VST1q8wb_register: 2799 case ARM::VST2d16: 2800 case ARM::VST2d32: 2801 case ARM::VST2d8: 2802 case ARM::VST2d16wb_fixed: 2803 case ARM::VST2d16wb_register: 2804 case ARM::VST2d32wb_fixed: 2805 case ARM::VST2d32wb_register: 2806 case ARM::VST2d8wb_fixed: 2807 case ARM::VST2d8wb_register: 2808 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2809 return MCDisassembler::Fail; 2810 break; 2811 case ARM::VST2b16: 2812 case ARM::VST2b32: 2813 case ARM::VST2b8: 2814 case ARM::VST2b16wb_fixed: 2815 case ARM::VST2b16wb_register: 2816 case ARM::VST2b32wb_fixed: 2817 case ARM::VST2b32wb_register: 2818 case ARM::VST2b8wb_fixed: 2819 case ARM::VST2b8wb_register: 2820 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2821 return MCDisassembler::Fail; 2822 break; 2823 default: 2824 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2825 return MCDisassembler::Fail; 2826 } 2827 2828 // Second input register 2829 switch (Inst.getOpcode()) { 2830 case ARM::VST3d8: 2831 case ARM::VST3d16: 2832 case ARM::VST3d32: 2833 case ARM::VST3d8_UPD: 2834 case ARM::VST3d16_UPD: 2835 case ARM::VST3d32_UPD: 2836 case ARM::VST4d8: 2837 case ARM::VST4d16: 2838 case ARM::VST4d32: 2839 case ARM::VST4d8_UPD: 2840 case ARM::VST4d16_UPD: 2841 case ARM::VST4d32_UPD: 2842 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2843 return MCDisassembler::Fail; 2844 break; 2845 case ARM::VST3q8: 2846 case ARM::VST3q16: 2847 case ARM::VST3q32: 2848 case ARM::VST3q8_UPD: 2849 case ARM::VST3q16_UPD: 2850 case ARM::VST3q32_UPD: 2851 case ARM::VST4q8: 2852 case ARM::VST4q16: 2853 case ARM::VST4q32: 2854 case ARM::VST4q8_UPD: 2855 case ARM::VST4q16_UPD: 2856 case ARM::VST4q32_UPD: 2857 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2858 return MCDisassembler::Fail; 2859 break; 2860 default: 2861 break; 2862 } 2863 2864 // Third input register 2865 switch (Inst.getOpcode()) { 2866 case ARM::VST3d8: 2867 case ARM::VST3d16: 2868 case ARM::VST3d32: 2869 case ARM::VST3d8_UPD: 2870 case ARM::VST3d16_UPD: 2871 case ARM::VST3d32_UPD: 2872 case ARM::VST4d8: 2873 case ARM::VST4d16: 2874 case ARM::VST4d32: 2875 case ARM::VST4d8_UPD: 2876 case ARM::VST4d16_UPD: 2877 case ARM::VST4d32_UPD: 2878 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2879 return MCDisassembler::Fail; 2880 break; 2881 case ARM::VST3q8: 2882 case ARM::VST3q16: 2883 case ARM::VST3q32: 2884 case ARM::VST3q8_UPD: 2885 case ARM::VST3q16_UPD: 2886 case ARM::VST3q32_UPD: 2887 case ARM::VST4q8: 2888 case ARM::VST4q16: 2889 case ARM::VST4q32: 2890 case ARM::VST4q8_UPD: 2891 case ARM::VST4q16_UPD: 2892 case ARM::VST4q32_UPD: 2893 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2894 return MCDisassembler::Fail; 2895 break; 2896 default: 2897 break; 2898 } 2899 2900 // Fourth input register 2901 switch (Inst.getOpcode()) { 2902 case ARM::VST4d8: 2903 case ARM::VST4d16: 2904 case ARM::VST4d32: 2905 case ARM::VST4d8_UPD: 2906 case ARM::VST4d16_UPD: 2907 case ARM::VST4d32_UPD: 2908 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 break; 2911 case ARM::VST4q8: 2912 case ARM::VST4q16: 2913 case ARM::VST4q32: 2914 case ARM::VST4q8_UPD: 2915 case ARM::VST4q16_UPD: 2916 case ARM::VST4q32_UPD: 2917 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2918 return MCDisassembler::Fail; 2919 break; 2920 default: 2921 break; 2922 } 2923 2924 return S; 2925 } 2926 2927 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2928 uint64_t Address, const void *Decoder) { 2929 DecodeStatus S = MCDisassembler::Success; 2930 2931 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2932 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2933 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2934 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2935 unsigned align = fieldFromInstruction(Insn, 4, 1); 2936 unsigned size = fieldFromInstruction(Insn, 6, 2); 2937 2938 if (size == 0 && align == 1) 2939 return MCDisassembler::Fail; 2940 align *= (1 << size); 2941 2942 switch (Inst.getOpcode()) { 2943 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2944 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2945 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2946 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2947 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2948 return MCDisassembler::Fail; 2949 break; 2950 default: 2951 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2952 return MCDisassembler::Fail; 2953 break; 2954 } 2955 if (Rm != 0xF) { 2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 } 2959 2960 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2961 return MCDisassembler::Fail; 2962 Inst.addOperand(MCOperand::createImm(align)); 2963 2964 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2965 // variant encodes Rm == 0xf. Anything else is a register offset post- 2966 // increment and we need to add the register operand to the instruction. 2967 if (Rm != 0xD && Rm != 0xF && 2968 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2969 return MCDisassembler::Fail; 2970 2971 return S; 2972 } 2973 2974 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2975 uint64_t Address, const void *Decoder) { 2976 DecodeStatus S = MCDisassembler::Success; 2977 2978 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2979 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2980 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2981 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2982 unsigned align = fieldFromInstruction(Insn, 4, 1); 2983 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2984 align *= 2*size; 2985 2986 switch (Inst.getOpcode()) { 2987 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2988 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2989 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2990 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2991 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2992 return MCDisassembler::Fail; 2993 break; 2994 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2995 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2996 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2997 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2998 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2999 return MCDisassembler::Fail; 3000 break; 3001 default: 3002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3003 return MCDisassembler::Fail; 3004 break; 3005 } 3006 3007 if (Rm != 0xF) 3008 Inst.addOperand(MCOperand::createImm(0)); 3009 3010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3011 return MCDisassembler::Fail; 3012 Inst.addOperand(MCOperand::createImm(align)); 3013 3014 if (Rm != 0xD && Rm != 0xF) { 3015 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3016 return MCDisassembler::Fail; 3017 } 3018 3019 return S; 3020 } 3021 3022 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3023 uint64_t Address, const void *Decoder) { 3024 DecodeStatus S = MCDisassembler::Success; 3025 3026 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3027 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3028 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3029 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3030 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3031 3032 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3033 return MCDisassembler::Fail; 3034 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3035 return MCDisassembler::Fail; 3036 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3037 return MCDisassembler::Fail; 3038 if (Rm != 0xF) { 3039 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3040 return MCDisassembler::Fail; 3041 } 3042 3043 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3044 return MCDisassembler::Fail; 3045 Inst.addOperand(MCOperand::createImm(0)); 3046 3047 if (Rm == 0xD) 3048 Inst.addOperand(MCOperand::createReg(0)); 3049 else if (Rm != 0xF) { 3050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 } 3053 3054 return S; 3055 } 3056 3057 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3058 uint64_t Address, const void *Decoder) { 3059 DecodeStatus S = MCDisassembler::Success; 3060 3061 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3062 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3063 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3064 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3065 unsigned size = fieldFromInstruction(Insn, 6, 2); 3066 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3067 unsigned align = fieldFromInstruction(Insn, 4, 1); 3068 3069 if (size == 0x3) { 3070 if (align == 0) 3071 return MCDisassembler::Fail; 3072 align = 16; 3073 } else { 3074 if (size == 2) { 3075 align *= 8; 3076 } else { 3077 size = 1 << size; 3078 align *= 4*size; 3079 } 3080 } 3081 3082 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3085 return MCDisassembler::Fail; 3086 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3087 return MCDisassembler::Fail; 3088 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3089 return MCDisassembler::Fail; 3090 if (Rm != 0xF) { 3091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3092 return MCDisassembler::Fail; 3093 } 3094 3095 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3096 return MCDisassembler::Fail; 3097 Inst.addOperand(MCOperand::createImm(align)); 3098 3099 if (Rm == 0xD) 3100 Inst.addOperand(MCOperand::createReg(0)); 3101 else if (Rm != 0xF) { 3102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3103 return MCDisassembler::Fail; 3104 } 3105 3106 return S; 3107 } 3108 3109 static DecodeStatus 3110 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3111 uint64_t Address, const void *Decoder) { 3112 DecodeStatus S = MCDisassembler::Success; 3113 3114 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3115 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3116 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3117 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3118 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3119 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3120 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3121 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3122 3123 if (Q) { 3124 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3125 return MCDisassembler::Fail; 3126 } else { 3127 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3128 return MCDisassembler::Fail; 3129 } 3130 3131 Inst.addOperand(MCOperand::createImm(imm)); 3132 3133 switch (Inst.getOpcode()) { 3134 case ARM::VORRiv4i16: 3135 case ARM::VORRiv2i32: 3136 case ARM::VBICiv4i16: 3137 case ARM::VBICiv2i32: 3138 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 break; 3141 case ARM::VORRiv8i16: 3142 case ARM::VORRiv4i32: 3143 case ARM::VBICiv8i16: 3144 case ARM::VBICiv4i32: 3145 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3146 return MCDisassembler::Fail; 3147 break; 3148 default: 3149 break; 3150 } 3151 3152 return S; 3153 } 3154 3155 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3156 uint64_t Address, const void *Decoder) { 3157 DecodeStatus S = MCDisassembler::Success; 3158 3159 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3160 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3161 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3162 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3163 unsigned size = fieldFromInstruction(Insn, 18, 2); 3164 3165 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3166 return MCDisassembler::Fail; 3167 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3168 return MCDisassembler::Fail; 3169 Inst.addOperand(MCOperand::createImm(8 << size)); 3170 3171 return S; 3172 } 3173 3174 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3175 uint64_t Address, const void *Decoder) { 3176 Inst.addOperand(MCOperand::createImm(8 - Val)); 3177 return MCDisassembler::Success; 3178 } 3179 3180 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3181 uint64_t Address, const void *Decoder) { 3182 Inst.addOperand(MCOperand::createImm(16 - Val)); 3183 return MCDisassembler::Success; 3184 } 3185 3186 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3187 uint64_t Address, const void *Decoder) { 3188 Inst.addOperand(MCOperand::createImm(32 - Val)); 3189 return MCDisassembler::Success; 3190 } 3191 3192 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3193 uint64_t Address, const void *Decoder) { 3194 Inst.addOperand(MCOperand::createImm(64 - Val)); 3195 return MCDisassembler::Success; 3196 } 3197 3198 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3199 uint64_t Address, const void *Decoder) { 3200 DecodeStatus S = MCDisassembler::Success; 3201 3202 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3203 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3204 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3205 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3206 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3207 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3208 unsigned op = fieldFromInstruction(Insn, 6, 1); 3209 3210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3211 return MCDisassembler::Fail; 3212 if (op) { 3213 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3214 return MCDisassembler::Fail; // Writeback 3215 } 3216 3217 switch (Inst.getOpcode()) { 3218 case ARM::VTBL2: 3219 case ARM::VTBX2: 3220 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3221 return MCDisassembler::Fail; 3222 break; 3223 default: 3224 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3225 return MCDisassembler::Fail; 3226 } 3227 3228 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 3231 return S; 3232 } 3233 3234 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3235 uint64_t Address, const void *Decoder) { 3236 DecodeStatus S = MCDisassembler::Success; 3237 3238 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3239 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3240 3241 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3242 return MCDisassembler::Fail; 3243 3244 switch(Inst.getOpcode()) { 3245 default: 3246 return MCDisassembler::Fail; 3247 case ARM::tADR: 3248 break; // tADR does not explicitly represent the PC as an operand. 3249 case ARM::tADDrSPi: 3250 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3251 break; 3252 } 3253 3254 Inst.addOperand(MCOperand::createImm(imm)); 3255 return S; 3256 } 3257 3258 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3259 uint64_t Address, const void *Decoder) { 3260 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3261 true, 2, Inst, Decoder)) 3262 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3263 return MCDisassembler::Success; 3264 } 3265 3266 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3267 uint64_t Address, const void *Decoder) { 3268 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3269 true, 4, Inst, Decoder)) 3270 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3271 return MCDisassembler::Success; 3272 } 3273 3274 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3275 uint64_t Address, const void *Decoder) { 3276 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3277 true, 2, Inst, Decoder)) 3278 Inst.addOperand(MCOperand::createImm(Val << 1)); 3279 return MCDisassembler::Success; 3280 } 3281 3282 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3283 uint64_t Address, const void *Decoder) { 3284 DecodeStatus S = MCDisassembler::Success; 3285 3286 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3287 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3288 3289 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3290 return MCDisassembler::Fail; 3291 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 3294 return S; 3295 } 3296 3297 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3298 uint64_t Address, const void *Decoder) { 3299 DecodeStatus S = MCDisassembler::Success; 3300 3301 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3302 unsigned imm = fieldFromInstruction(Val, 3, 5); 3303 3304 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3305 return MCDisassembler::Fail; 3306 Inst.addOperand(MCOperand::createImm(imm)); 3307 3308 return S; 3309 } 3310 3311 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3312 uint64_t Address, const void *Decoder) { 3313 unsigned imm = Val << 2; 3314 3315 Inst.addOperand(MCOperand::createImm(imm)); 3316 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3317 3318 return MCDisassembler::Success; 3319 } 3320 3321 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3322 uint64_t Address, const void *Decoder) { 3323 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3324 Inst.addOperand(MCOperand::createImm(Val)); 3325 3326 return MCDisassembler::Success; 3327 } 3328 3329 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3330 uint64_t Address, const void *Decoder) { 3331 DecodeStatus S = MCDisassembler::Success; 3332 3333 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3334 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3335 unsigned imm = fieldFromInstruction(Val, 0, 2); 3336 3337 // Thumb stores cannot use PC as dest register. 3338 switch (Inst.getOpcode()) { 3339 case ARM::t2STRHs: 3340 case ARM::t2STRBs: 3341 case ARM::t2STRs: 3342 if (Rn == 15) 3343 return MCDisassembler::Fail; 3344 default: 3345 break; 3346 } 3347 3348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3349 return MCDisassembler::Fail; 3350 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3351 return MCDisassembler::Fail; 3352 Inst.addOperand(MCOperand::createImm(imm)); 3353 3354 return S; 3355 } 3356 3357 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3358 uint64_t Address, const void *Decoder) { 3359 DecodeStatus S = MCDisassembler::Success; 3360 3361 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3362 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3363 3364 const FeatureBitset &featureBits = 3365 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3366 3367 bool hasMP = featureBits[ARM::FeatureMP]; 3368 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3369 3370 if (Rn == 15) { 3371 switch (Inst.getOpcode()) { 3372 case ARM::t2LDRBs: 3373 Inst.setOpcode(ARM::t2LDRBpci); 3374 break; 3375 case ARM::t2LDRHs: 3376 Inst.setOpcode(ARM::t2LDRHpci); 3377 break; 3378 case ARM::t2LDRSHs: 3379 Inst.setOpcode(ARM::t2LDRSHpci); 3380 break; 3381 case ARM::t2LDRSBs: 3382 Inst.setOpcode(ARM::t2LDRSBpci); 3383 break; 3384 case ARM::t2LDRs: 3385 Inst.setOpcode(ARM::t2LDRpci); 3386 break; 3387 case ARM::t2PLDs: 3388 Inst.setOpcode(ARM::t2PLDpci); 3389 break; 3390 case ARM::t2PLIs: 3391 Inst.setOpcode(ARM::t2PLIpci); 3392 break; 3393 default: 3394 return MCDisassembler::Fail; 3395 } 3396 3397 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3398 } 3399 3400 if (Rt == 15) { 3401 switch (Inst.getOpcode()) { 3402 case ARM::t2LDRSHs: 3403 return MCDisassembler::Fail; 3404 case ARM::t2LDRHs: 3405 Inst.setOpcode(ARM::t2PLDWs); 3406 break; 3407 case ARM::t2LDRSBs: 3408 Inst.setOpcode(ARM::t2PLIs); 3409 default: 3410 break; 3411 } 3412 } 3413 3414 switch (Inst.getOpcode()) { 3415 case ARM::t2PLDs: 3416 break; 3417 case ARM::t2PLIs: 3418 if (!hasV7Ops) 3419 return MCDisassembler::Fail; 3420 break; 3421 case ARM::t2PLDWs: 3422 if (!hasV7Ops || !hasMP) 3423 return MCDisassembler::Fail; 3424 break; 3425 default: 3426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3427 return MCDisassembler::Fail; 3428 } 3429 3430 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3431 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3432 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3433 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 3436 return S; 3437 } 3438 3439 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3440 uint64_t Address, const void* Decoder) { 3441 DecodeStatus S = MCDisassembler::Success; 3442 3443 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3444 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3445 unsigned U = fieldFromInstruction(Insn, 9, 1); 3446 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3447 imm |= (U << 8); 3448 imm |= (Rn << 9); 3449 unsigned add = fieldFromInstruction(Insn, 9, 1); 3450 3451 const FeatureBitset &featureBits = 3452 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3453 3454 bool hasMP = featureBits[ARM::FeatureMP]; 3455 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3456 3457 if (Rn == 15) { 3458 switch (Inst.getOpcode()) { 3459 case ARM::t2LDRi8: 3460 Inst.setOpcode(ARM::t2LDRpci); 3461 break; 3462 case ARM::t2LDRBi8: 3463 Inst.setOpcode(ARM::t2LDRBpci); 3464 break; 3465 case ARM::t2LDRSBi8: 3466 Inst.setOpcode(ARM::t2LDRSBpci); 3467 break; 3468 case ARM::t2LDRHi8: 3469 Inst.setOpcode(ARM::t2LDRHpci); 3470 break; 3471 case ARM::t2LDRSHi8: 3472 Inst.setOpcode(ARM::t2LDRSHpci); 3473 break; 3474 case ARM::t2PLDi8: 3475 Inst.setOpcode(ARM::t2PLDpci); 3476 break; 3477 case ARM::t2PLIi8: 3478 Inst.setOpcode(ARM::t2PLIpci); 3479 break; 3480 default: 3481 return MCDisassembler::Fail; 3482 } 3483 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3484 } 3485 3486 if (Rt == 15) { 3487 switch (Inst.getOpcode()) { 3488 case ARM::t2LDRSHi8: 3489 return MCDisassembler::Fail; 3490 case ARM::t2LDRHi8: 3491 if (!add) 3492 Inst.setOpcode(ARM::t2PLDWi8); 3493 break; 3494 case ARM::t2LDRSBi8: 3495 Inst.setOpcode(ARM::t2PLIi8); 3496 break; 3497 default: 3498 break; 3499 } 3500 } 3501 3502 switch (Inst.getOpcode()) { 3503 case ARM::t2PLDi8: 3504 break; 3505 case ARM::t2PLIi8: 3506 if (!hasV7Ops) 3507 return MCDisassembler::Fail; 3508 break; 3509 case ARM::t2PLDWi8: 3510 if (!hasV7Ops || !hasMP) 3511 return MCDisassembler::Fail; 3512 break; 3513 default: 3514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3515 return MCDisassembler::Fail; 3516 } 3517 3518 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3519 return MCDisassembler::Fail; 3520 return S; 3521 } 3522 3523 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3524 uint64_t Address, const void* Decoder) { 3525 DecodeStatus S = MCDisassembler::Success; 3526 3527 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3528 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3529 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3530 imm |= (Rn << 13); 3531 3532 const FeatureBitset &featureBits = 3533 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3534 3535 bool hasMP = featureBits[ARM::FeatureMP]; 3536 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3537 3538 if (Rn == 15) { 3539 switch (Inst.getOpcode()) { 3540 case ARM::t2LDRi12: 3541 Inst.setOpcode(ARM::t2LDRpci); 3542 break; 3543 case ARM::t2LDRHi12: 3544 Inst.setOpcode(ARM::t2LDRHpci); 3545 break; 3546 case ARM::t2LDRSHi12: 3547 Inst.setOpcode(ARM::t2LDRSHpci); 3548 break; 3549 case ARM::t2LDRBi12: 3550 Inst.setOpcode(ARM::t2LDRBpci); 3551 break; 3552 case ARM::t2LDRSBi12: 3553 Inst.setOpcode(ARM::t2LDRSBpci); 3554 break; 3555 case ARM::t2PLDi12: 3556 Inst.setOpcode(ARM::t2PLDpci); 3557 break; 3558 case ARM::t2PLIi12: 3559 Inst.setOpcode(ARM::t2PLIpci); 3560 break; 3561 default: 3562 return MCDisassembler::Fail; 3563 } 3564 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3565 } 3566 3567 if (Rt == 15) { 3568 switch (Inst.getOpcode()) { 3569 case ARM::t2LDRSHi12: 3570 return MCDisassembler::Fail; 3571 case ARM::t2LDRHi12: 3572 Inst.setOpcode(ARM::t2PLDWi12); 3573 break; 3574 case ARM::t2LDRSBi12: 3575 Inst.setOpcode(ARM::t2PLIi12); 3576 break; 3577 default: 3578 break; 3579 } 3580 } 3581 3582 switch (Inst.getOpcode()) { 3583 case ARM::t2PLDi12: 3584 break; 3585 case ARM::t2PLIi12: 3586 if (!hasV7Ops) 3587 return MCDisassembler::Fail; 3588 break; 3589 case ARM::t2PLDWi12: 3590 if (!hasV7Ops || !hasMP) 3591 return MCDisassembler::Fail; 3592 break; 3593 default: 3594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3595 return MCDisassembler::Fail; 3596 } 3597 3598 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3599 return MCDisassembler::Fail; 3600 return S; 3601 } 3602 3603 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3604 uint64_t Address, const void* Decoder) { 3605 DecodeStatus S = MCDisassembler::Success; 3606 3607 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3608 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3609 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3610 imm |= (Rn << 9); 3611 3612 if (Rn == 15) { 3613 switch (Inst.getOpcode()) { 3614 case ARM::t2LDRT: 3615 Inst.setOpcode(ARM::t2LDRpci); 3616 break; 3617 case ARM::t2LDRBT: 3618 Inst.setOpcode(ARM::t2LDRBpci); 3619 break; 3620 case ARM::t2LDRHT: 3621 Inst.setOpcode(ARM::t2LDRHpci); 3622 break; 3623 case ARM::t2LDRSBT: 3624 Inst.setOpcode(ARM::t2LDRSBpci); 3625 break; 3626 case ARM::t2LDRSHT: 3627 Inst.setOpcode(ARM::t2LDRSHpci); 3628 break; 3629 default: 3630 return MCDisassembler::Fail; 3631 } 3632 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3633 } 3634 3635 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3638 return MCDisassembler::Fail; 3639 return S; 3640 } 3641 3642 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3643 uint64_t Address, const void* Decoder) { 3644 DecodeStatus S = MCDisassembler::Success; 3645 3646 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3647 unsigned U = fieldFromInstruction(Insn, 23, 1); 3648 int imm = fieldFromInstruction(Insn, 0, 12); 3649 3650 const FeatureBitset &featureBits = 3651 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3652 3653 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3654 3655 if (Rt == 15) { 3656 switch (Inst.getOpcode()) { 3657 case ARM::t2LDRBpci: 3658 case ARM::t2LDRHpci: 3659 Inst.setOpcode(ARM::t2PLDpci); 3660 break; 3661 case ARM::t2LDRSBpci: 3662 Inst.setOpcode(ARM::t2PLIpci); 3663 break; 3664 case ARM::t2LDRSHpci: 3665 return MCDisassembler::Fail; 3666 default: 3667 break; 3668 } 3669 } 3670 3671 switch(Inst.getOpcode()) { 3672 case ARM::t2PLDpci: 3673 break; 3674 case ARM::t2PLIpci: 3675 if (!hasV7Ops) 3676 return MCDisassembler::Fail; 3677 break; 3678 default: 3679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 } 3682 3683 if (!U) { 3684 // Special case for #-0. 3685 if (imm == 0) 3686 imm = INT32_MIN; 3687 else 3688 imm = -imm; 3689 } 3690 Inst.addOperand(MCOperand::createImm(imm)); 3691 3692 return S; 3693 } 3694 3695 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3696 uint64_t Address, const void *Decoder) { 3697 if (Val == 0) 3698 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3699 else { 3700 int imm = Val & 0xFF; 3701 3702 if (!(Val & 0x100)) imm *= -1; 3703 Inst.addOperand(MCOperand::createImm(imm * 4)); 3704 } 3705 3706 return MCDisassembler::Success; 3707 } 3708 3709 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3710 uint64_t Address, const void *Decoder) { 3711 DecodeStatus S = MCDisassembler::Success; 3712 3713 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3714 unsigned imm = fieldFromInstruction(Val, 0, 9); 3715 3716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3717 return MCDisassembler::Fail; 3718 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3719 return MCDisassembler::Fail; 3720 3721 return S; 3722 } 3723 3724 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3725 uint64_t Address, const void *Decoder) { 3726 DecodeStatus S = MCDisassembler::Success; 3727 3728 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3729 unsigned imm = fieldFromInstruction(Val, 0, 8); 3730 3731 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3732 return MCDisassembler::Fail; 3733 3734 Inst.addOperand(MCOperand::createImm(imm)); 3735 3736 return S; 3737 } 3738 3739 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3740 uint64_t Address, const void *Decoder) { 3741 int imm = Val & 0xFF; 3742 if (Val == 0) 3743 imm = INT32_MIN; 3744 else if (!(Val & 0x100)) 3745 imm *= -1; 3746 Inst.addOperand(MCOperand::createImm(imm)); 3747 3748 return MCDisassembler::Success; 3749 } 3750 3751 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3752 uint64_t Address, const void *Decoder) { 3753 DecodeStatus S = MCDisassembler::Success; 3754 3755 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3756 unsigned imm = fieldFromInstruction(Val, 0, 9); 3757 3758 // Thumb stores cannot use PC as dest register. 3759 switch (Inst.getOpcode()) { 3760 case ARM::t2STRT: 3761 case ARM::t2STRBT: 3762 case ARM::t2STRHT: 3763 case ARM::t2STRi8: 3764 case ARM::t2STRHi8: 3765 case ARM::t2STRBi8: 3766 if (Rn == 15) 3767 return MCDisassembler::Fail; 3768 break; 3769 default: 3770 break; 3771 } 3772 3773 // Some instructions always use an additive offset. 3774 switch (Inst.getOpcode()) { 3775 case ARM::t2LDRT: 3776 case ARM::t2LDRBT: 3777 case ARM::t2LDRHT: 3778 case ARM::t2LDRSBT: 3779 case ARM::t2LDRSHT: 3780 case ARM::t2STRT: 3781 case ARM::t2STRBT: 3782 case ARM::t2STRHT: 3783 imm |= 0x100; 3784 break; 3785 default: 3786 break; 3787 } 3788 3789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3790 return MCDisassembler::Fail; 3791 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3792 return MCDisassembler::Fail; 3793 3794 return S; 3795 } 3796 3797 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3798 uint64_t Address, const void *Decoder) { 3799 DecodeStatus S = MCDisassembler::Success; 3800 3801 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3802 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3803 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3804 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3805 addr |= Rn << 9; 3806 unsigned load = fieldFromInstruction(Insn, 20, 1); 3807 3808 if (Rn == 15) { 3809 switch (Inst.getOpcode()) { 3810 case ARM::t2LDR_PRE: 3811 case ARM::t2LDR_POST: 3812 Inst.setOpcode(ARM::t2LDRpci); 3813 break; 3814 case ARM::t2LDRB_PRE: 3815 case ARM::t2LDRB_POST: 3816 Inst.setOpcode(ARM::t2LDRBpci); 3817 break; 3818 case ARM::t2LDRH_PRE: 3819 case ARM::t2LDRH_POST: 3820 Inst.setOpcode(ARM::t2LDRHpci); 3821 break; 3822 case ARM::t2LDRSB_PRE: 3823 case ARM::t2LDRSB_POST: 3824 if (Rt == 15) 3825 Inst.setOpcode(ARM::t2PLIpci); 3826 else 3827 Inst.setOpcode(ARM::t2LDRSBpci); 3828 break; 3829 case ARM::t2LDRSH_PRE: 3830 case ARM::t2LDRSH_POST: 3831 Inst.setOpcode(ARM::t2LDRSHpci); 3832 break; 3833 default: 3834 return MCDisassembler::Fail; 3835 } 3836 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3837 } 3838 3839 if (!load) { 3840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3841 return MCDisassembler::Fail; 3842 } 3843 3844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3845 return MCDisassembler::Fail; 3846 3847 if (load) { 3848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3849 return MCDisassembler::Fail; 3850 } 3851 3852 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3853 return MCDisassembler::Fail; 3854 3855 return S; 3856 } 3857 3858 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3859 uint64_t Address, const void *Decoder) { 3860 DecodeStatus S = MCDisassembler::Success; 3861 3862 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3863 unsigned imm = fieldFromInstruction(Val, 0, 12); 3864 3865 // Thumb stores cannot use PC as dest register. 3866 switch (Inst.getOpcode()) { 3867 case ARM::t2STRi12: 3868 case ARM::t2STRBi12: 3869 case ARM::t2STRHi12: 3870 if (Rn == 15) 3871 return MCDisassembler::Fail; 3872 default: 3873 break; 3874 } 3875 3876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3877 return MCDisassembler::Fail; 3878 Inst.addOperand(MCOperand::createImm(imm)); 3879 3880 return S; 3881 } 3882 3883 3884 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3885 uint64_t Address, const void *Decoder) { 3886 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3887 3888 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3889 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3890 Inst.addOperand(MCOperand::createImm(imm)); 3891 3892 return MCDisassembler::Success; 3893 } 3894 3895 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3896 uint64_t Address, const void *Decoder) { 3897 DecodeStatus S = MCDisassembler::Success; 3898 3899 if (Inst.getOpcode() == ARM::tADDrSP) { 3900 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3901 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3902 3903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3904 return MCDisassembler::Fail; 3905 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3907 return MCDisassembler::Fail; 3908 } else if (Inst.getOpcode() == ARM::tADDspr) { 3909 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3910 3911 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3912 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3914 return MCDisassembler::Fail; 3915 } 3916 3917 return S; 3918 } 3919 3920 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3921 uint64_t Address, const void *Decoder) { 3922 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3923 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3924 3925 Inst.addOperand(MCOperand::createImm(imod)); 3926 Inst.addOperand(MCOperand::createImm(flags)); 3927 3928 return MCDisassembler::Success; 3929 } 3930 3931 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3932 uint64_t Address, const void *Decoder) { 3933 DecodeStatus S = MCDisassembler::Success; 3934 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3935 unsigned add = fieldFromInstruction(Insn, 4, 1); 3936 3937 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3938 return MCDisassembler::Fail; 3939 Inst.addOperand(MCOperand::createImm(add)); 3940 3941 return S; 3942 } 3943 3944 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3945 uint64_t Address, const void *Decoder) { 3946 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3947 // Note only one trailing zero not two. Also the J1 and J2 values are from 3948 // the encoded instruction. So here change to I1 and I2 values via: 3949 // I1 = NOT(J1 EOR S); 3950 // I2 = NOT(J2 EOR S); 3951 // and build the imm32 with two trailing zeros as documented: 3952 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3953 unsigned S = (Val >> 23) & 1; 3954 unsigned J1 = (Val >> 22) & 1; 3955 unsigned J2 = (Val >> 21) & 1; 3956 unsigned I1 = !(J1 ^ S); 3957 unsigned I2 = !(J2 ^ S); 3958 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3959 int imm32 = SignExtend32<25>(tmp << 1); 3960 3961 if (!tryAddingSymbolicOperand(Address, 3962 (Address & ~2u) + imm32 + 4, 3963 true, 4, Inst, Decoder)) 3964 Inst.addOperand(MCOperand::createImm(imm32)); 3965 return MCDisassembler::Success; 3966 } 3967 3968 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3969 uint64_t Address, const void *Decoder) { 3970 if (Val == 0xA || Val == 0xB) 3971 return MCDisassembler::Fail; 3972 3973 const FeatureBitset &featureBits = 3974 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3975 3976 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 3977 return MCDisassembler::Fail; 3978 3979 Inst.addOperand(MCOperand::createImm(Val)); 3980 return MCDisassembler::Success; 3981 } 3982 3983 static DecodeStatus 3984 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3985 uint64_t Address, const void *Decoder) { 3986 DecodeStatus S = MCDisassembler::Success; 3987 3988 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3989 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3990 3991 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3992 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3993 return MCDisassembler::Fail; 3994 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3995 return MCDisassembler::Fail; 3996 return S; 3997 } 3998 3999 static DecodeStatus 4000 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4001 uint64_t Address, const void *Decoder) { 4002 DecodeStatus S = MCDisassembler::Success; 4003 4004 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4005 if (pred == 0xE || pred == 0xF) { 4006 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4007 switch (opc) { 4008 default: 4009 return MCDisassembler::Fail; 4010 case 0xf3bf8f4: 4011 Inst.setOpcode(ARM::t2DSB); 4012 break; 4013 case 0xf3bf8f5: 4014 Inst.setOpcode(ARM::t2DMB); 4015 break; 4016 case 0xf3bf8f6: 4017 Inst.setOpcode(ARM::t2ISB); 4018 break; 4019 } 4020 4021 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4022 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4023 } 4024 4025 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4026 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4027 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4028 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4029 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4030 4031 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4034 return MCDisassembler::Fail; 4035 4036 return S; 4037 } 4038 4039 // Decode a shifted immediate operand. These basically consist 4040 // of an 8-bit value, and a 4-bit directive that specifies either 4041 // a splat operation or a rotation. 4042 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4043 uint64_t Address, const void *Decoder) { 4044 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4045 if (ctrl == 0) { 4046 unsigned byte = fieldFromInstruction(Val, 8, 2); 4047 unsigned imm = fieldFromInstruction(Val, 0, 8); 4048 switch (byte) { 4049 case 0: 4050 Inst.addOperand(MCOperand::createImm(imm)); 4051 break; 4052 case 1: 4053 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4054 break; 4055 case 2: 4056 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4057 break; 4058 case 3: 4059 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4060 (imm << 8) | imm)); 4061 break; 4062 } 4063 } else { 4064 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4065 unsigned rot = fieldFromInstruction(Val, 7, 5); 4066 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4067 Inst.addOperand(MCOperand::createImm(imm)); 4068 } 4069 4070 return MCDisassembler::Success; 4071 } 4072 4073 static DecodeStatus 4074 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4075 uint64_t Address, const void *Decoder) { 4076 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4077 true, 2, Inst, Decoder)) 4078 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4079 return MCDisassembler::Success; 4080 } 4081 4082 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4083 uint64_t Address, 4084 const void *Decoder) { 4085 // Val is passed in as S:J1:J2:imm10:imm11 4086 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4087 // the encoded instruction. So here change to I1 and I2 values via: 4088 // I1 = NOT(J1 EOR S); 4089 // I2 = NOT(J2 EOR S); 4090 // and build the imm32 with one trailing zero as documented: 4091 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4092 unsigned S = (Val >> 23) & 1; 4093 unsigned J1 = (Val >> 22) & 1; 4094 unsigned J2 = (Val >> 21) & 1; 4095 unsigned I1 = !(J1 ^ S); 4096 unsigned I2 = !(J2 ^ S); 4097 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4098 int imm32 = SignExtend32<25>(tmp << 1); 4099 4100 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4101 true, 4, Inst, Decoder)) 4102 Inst.addOperand(MCOperand::createImm(imm32)); 4103 return MCDisassembler::Success; 4104 } 4105 4106 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4107 uint64_t Address, const void *Decoder) { 4108 if (Val & ~0xf) 4109 return MCDisassembler::Fail; 4110 4111 Inst.addOperand(MCOperand::createImm(Val)); 4112 return MCDisassembler::Success; 4113 } 4114 4115 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4116 uint64_t Address, const void *Decoder) { 4117 if (Val & ~0xf) 4118 return MCDisassembler::Fail; 4119 4120 Inst.addOperand(MCOperand::createImm(Val)); 4121 return MCDisassembler::Success; 4122 } 4123 4124 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4125 uint64_t Address, const void *Decoder) { 4126 DecodeStatus S = MCDisassembler::Success; 4127 const FeatureBitset &FeatureBits = 4128 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4129 4130 if (FeatureBits[ARM::FeatureMClass]) { 4131 unsigned ValLow = Val & 0xff; 4132 4133 // Validate the SYSm value first. 4134 switch (ValLow) { 4135 case 0: // apsr 4136 case 1: // iapsr 4137 case 2: // eapsr 4138 case 3: // xpsr 4139 case 5: // ipsr 4140 case 6: // epsr 4141 case 7: // iepsr 4142 case 8: // msp 4143 case 9: // psp 4144 case 16: // primask 4145 case 20: // control 4146 break; 4147 case 17: // basepri 4148 case 18: // basepri_max 4149 case 19: // faultmask 4150 if (!(FeatureBits[ARM::HasV7Ops])) 4151 // Values basepri, basepri_max and faultmask are only valid for v7m. 4152 return MCDisassembler::Fail; 4153 break; 4154 case 0x8a: // msplim_ns 4155 case 0x8b: // psplim_ns 4156 case 0x91: // basepri_ns 4157 case 0x92: // basepri_max_ns 4158 case 0x93: // faultmask_ns 4159 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4160 return MCDisassembler::Fail; 4161 LLVM_FALLTHROUGH; 4162 case 10: // msplim 4163 case 11: // psplim 4164 case 0x88: // msp_ns 4165 case 0x89: // psp_ns 4166 case 0x90: // primask_ns 4167 case 0x94: // control_ns 4168 case 0x98: // sp_ns 4169 if (!(FeatureBits[ARM::Feature8MSecExt])) 4170 return MCDisassembler::Fail; 4171 break; 4172 default: 4173 return MCDisassembler::Fail; 4174 } 4175 4176 if (Inst.getOpcode() == ARM::t2MSR_M) { 4177 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4178 if (!(FeatureBits[ARM::HasV7Ops])) { 4179 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4180 // unpredictable. 4181 if (Mask != 2) 4182 S = MCDisassembler::SoftFail; 4183 } 4184 else { 4185 // The ARMv7-M architecture stores an additional 2-bit mask value in 4186 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4187 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4188 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4189 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4190 // only if the processor includes the DSP extension. 4191 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4192 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4193 S = MCDisassembler::SoftFail; 4194 } 4195 } 4196 } else { 4197 // A/R class 4198 if (Val == 0) 4199 return MCDisassembler::Fail; 4200 } 4201 Inst.addOperand(MCOperand::createImm(Val)); 4202 return S; 4203 } 4204 4205 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4206 uint64_t Address, const void *Decoder) { 4207 4208 unsigned R = fieldFromInstruction(Val, 5, 1); 4209 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4210 4211 // The table of encodings for these banked registers comes from B9.2.3 of the 4212 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4213 // neater. So by fiat, these values are UNPREDICTABLE: 4214 if (!R) { 4215 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 4216 SysM == 0x1a || SysM == 0x1b) 4217 return MCDisassembler::SoftFail; 4218 } else { 4219 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 4220 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 4221 return MCDisassembler::SoftFail; 4222 } 4223 4224 Inst.addOperand(MCOperand::createImm(Val)); 4225 return MCDisassembler::Success; 4226 } 4227 4228 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4229 uint64_t Address, const void *Decoder) { 4230 DecodeStatus S = MCDisassembler::Success; 4231 4232 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4233 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4234 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4235 4236 if (Rn == 0xF) 4237 S = MCDisassembler::SoftFail; 4238 4239 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4240 return MCDisassembler::Fail; 4241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 4246 return S; 4247 } 4248 4249 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4250 uint64_t Address, 4251 const void *Decoder) { 4252 DecodeStatus S = MCDisassembler::Success; 4253 4254 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4255 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4256 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4257 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4258 4259 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4260 return MCDisassembler::Fail; 4261 4262 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4263 S = MCDisassembler::SoftFail; 4264 4265 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4266 return MCDisassembler::Fail; 4267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 4272 return S; 4273 } 4274 4275 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4276 uint64_t Address, const void *Decoder) { 4277 DecodeStatus S = MCDisassembler::Success; 4278 4279 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4280 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4281 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4282 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4283 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4284 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4285 4286 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4287 4288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4289 return MCDisassembler::Fail; 4290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4291 return MCDisassembler::Fail; 4292 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4293 return MCDisassembler::Fail; 4294 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 4297 return S; 4298 } 4299 4300 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4301 uint64_t Address, const void *Decoder) { 4302 DecodeStatus S = MCDisassembler::Success; 4303 4304 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4305 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4306 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4307 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4308 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4309 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4310 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4311 4312 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4313 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4314 4315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4316 return MCDisassembler::Fail; 4317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4318 return MCDisassembler::Fail; 4319 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4320 return MCDisassembler::Fail; 4321 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4322 return MCDisassembler::Fail; 4323 4324 return S; 4325 } 4326 4327 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4328 uint64_t Address, const void *Decoder) { 4329 DecodeStatus S = MCDisassembler::Success; 4330 4331 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4332 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4333 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4334 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4335 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4336 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4337 4338 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4339 4340 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4341 return MCDisassembler::Fail; 4342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4345 return MCDisassembler::Fail; 4346 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4347 return MCDisassembler::Fail; 4348 4349 return S; 4350 } 4351 4352 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4353 uint64_t Address, const void *Decoder) { 4354 DecodeStatus S = MCDisassembler::Success; 4355 4356 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4357 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4358 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4359 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4360 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4361 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4362 4363 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4364 4365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4368 return MCDisassembler::Fail; 4369 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4370 return MCDisassembler::Fail; 4371 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 4374 return S; 4375 } 4376 4377 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4378 uint64_t Address, const void *Decoder) { 4379 DecodeStatus S = MCDisassembler::Success; 4380 4381 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4382 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4383 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4384 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4385 unsigned size = fieldFromInstruction(Insn, 10, 2); 4386 4387 unsigned align = 0; 4388 unsigned index = 0; 4389 switch (size) { 4390 default: 4391 return MCDisassembler::Fail; 4392 case 0: 4393 if (fieldFromInstruction(Insn, 4, 1)) 4394 return MCDisassembler::Fail; // UNDEFINED 4395 index = fieldFromInstruction(Insn, 5, 3); 4396 break; 4397 case 1: 4398 if (fieldFromInstruction(Insn, 5, 1)) 4399 return MCDisassembler::Fail; // UNDEFINED 4400 index = fieldFromInstruction(Insn, 6, 2); 4401 if (fieldFromInstruction(Insn, 4, 1)) 4402 align = 2; 4403 break; 4404 case 2: 4405 if (fieldFromInstruction(Insn, 6, 1)) 4406 return MCDisassembler::Fail; // UNDEFINED 4407 index = fieldFromInstruction(Insn, 7, 1); 4408 4409 switch (fieldFromInstruction(Insn, 4, 2)) { 4410 case 0 : 4411 align = 0; break; 4412 case 3: 4413 align = 4; break; 4414 default: 4415 return MCDisassembler::Fail; 4416 } 4417 break; 4418 } 4419 4420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4421 return MCDisassembler::Fail; 4422 if (Rm != 0xF) { // Writeback 4423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4424 return MCDisassembler::Fail; 4425 } 4426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 Inst.addOperand(MCOperand::createImm(align)); 4429 if (Rm != 0xF) { 4430 if (Rm != 0xD) { 4431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4432 return MCDisassembler::Fail; 4433 } else 4434 Inst.addOperand(MCOperand::createReg(0)); 4435 } 4436 4437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4438 return MCDisassembler::Fail; 4439 Inst.addOperand(MCOperand::createImm(index)); 4440 4441 return S; 4442 } 4443 4444 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4445 uint64_t Address, const void *Decoder) { 4446 DecodeStatus S = MCDisassembler::Success; 4447 4448 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4449 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4450 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4451 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4452 unsigned size = fieldFromInstruction(Insn, 10, 2); 4453 4454 unsigned align = 0; 4455 unsigned index = 0; 4456 switch (size) { 4457 default: 4458 return MCDisassembler::Fail; 4459 case 0: 4460 if (fieldFromInstruction(Insn, 4, 1)) 4461 return MCDisassembler::Fail; // UNDEFINED 4462 index = fieldFromInstruction(Insn, 5, 3); 4463 break; 4464 case 1: 4465 if (fieldFromInstruction(Insn, 5, 1)) 4466 return MCDisassembler::Fail; // UNDEFINED 4467 index = fieldFromInstruction(Insn, 6, 2); 4468 if (fieldFromInstruction(Insn, 4, 1)) 4469 align = 2; 4470 break; 4471 case 2: 4472 if (fieldFromInstruction(Insn, 6, 1)) 4473 return MCDisassembler::Fail; // UNDEFINED 4474 index = fieldFromInstruction(Insn, 7, 1); 4475 4476 switch (fieldFromInstruction(Insn, 4, 2)) { 4477 case 0: 4478 align = 0; break; 4479 case 3: 4480 align = 4; break; 4481 default: 4482 return MCDisassembler::Fail; 4483 } 4484 break; 4485 } 4486 4487 if (Rm != 0xF) { // Writeback 4488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4489 return MCDisassembler::Fail; 4490 } 4491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4492 return MCDisassembler::Fail; 4493 Inst.addOperand(MCOperand::createImm(align)); 4494 if (Rm != 0xF) { 4495 if (Rm != 0xD) { 4496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4497 return MCDisassembler::Fail; 4498 } else 4499 Inst.addOperand(MCOperand::createReg(0)); 4500 } 4501 4502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4503 return MCDisassembler::Fail; 4504 Inst.addOperand(MCOperand::createImm(index)); 4505 4506 return S; 4507 } 4508 4509 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4510 uint64_t Address, const void *Decoder) { 4511 DecodeStatus S = MCDisassembler::Success; 4512 4513 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4514 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4515 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4516 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4517 unsigned size = fieldFromInstruction(Insn, 10, 2); 4518 4519 unsigned align = 0; 4520 unsigned index = 0; 4521 unsigned inc = 1; 4522 switch (size) { 4523 default: 4524 return MCDisassembler::Fail; 4525 case 0: 4526 index = fieldFromInstruction(Insn, 5, 3); 4527 if (fieldFromInstruction(Insn, 4, 1)) 4528 align = 2; 4529 break; 4530 case 1: 4531 index = fieldFromInstruction(Insn, 6, 2); 4532 if (fieldFromInstruction(Insn, 4, 1)) 4533 align = 4; 4534 if (fieldFromInstruction(Insn, 5, 1)) 4535 inc = 2; 4536 break; 4537 case 2: 4538 if (fieldFromInstruction(Insn, 5, 1)) 4539 return MCDisassembler::Fail; // UNDEFINED 4540 index = fieldFromInstruction(Insn, 7, 1); 4541 if (fieldFromInstruction(Insn, 4, 1) != 0) 4542 align = 8; 4543 if (fieldFromInstruction(Insn, 6, 1)) 4544 inc = 2; 4545 break; 4546 } 4547 4548 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4549 return MCDisassembler::Fail; 4550 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4551 return MCDisassembler::Fail; 4552 if (Rm != 0xF) { // Writeback 4553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4554 return MCDisassembler::Fail; 4555 } 4556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4557 return MCDisassembler::Fail; 4558 Inst.addOperand(MCOperand::createImm(align)); 4559 if (Rm != 0xF) { 4560 if (Rm != 0xD) { 4561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4562 return MCDisassembler::Fail; 4563 } else 4564 Inst.addOperand(MCOperand::createReg(0)); 4565 } 4566 4567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4568 return MCDisassembler::Fail; 4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4570 return MCDisassembler::Fail; 4571 Inst.addOperand(MCOperand::createImm(index)); 4572 4573 return S; 4574 } 4575 4576 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4577 uint64_t Address, const void *Decoder) { 4578 DecodeStatus S = MCDisassembler::Success; 4579 4580 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4581 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4583 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4584 unsigned size = fieldFromInstruction(Insn, 10, 2); 4585 4586 unsigned align = 0; 4587 unsigned index = 0; 4588 unsigned inc = 1; 4589 switch (size) { 4590 default: 4591 return MCDisassembler::Fail; 4592 case 0: 4593 index = fieldFromInstruction(Insn, 5, 3); 4594 if (fieldFromInstruction(Insn, 4, 1)) 4595 align = 2; 4596 break; 4597 case 1: 4598 index = fieldFromInstruction(Insn, 6, 2); 4599 if (fieldFromInstruction(Insn, 4, 1)) 4600 align = 4; 4601 if (fieldFromInstruction(Insn, 5, 1)) 4602 inc = 2; 4603 break; 4604 case 2: 4605 if (fieldFromInstruction(Insn, 5, 1)) 4606 return MCDisassembler::Fail; // UNDEFINED 4607 index = fieldFromInstruction(Insn, 7, 1); 4608 if (fieldFromInstruction(Insn, 4, 1) != 0) 4609 align = 8; 4610 if (fieldFromInstruction(Insn, 6, 1)) 4611 inc = 2; 4612 break; 4613 } 4614 4615 if (Rm != 0xF) { // Writeback 4616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4617 return MCDisassembler::Fail; 4618 } 4619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4620 return MCDisassembler::Fail; 4621 Inst.addOperand(MCOperand::createImm(align)); 4622 if (Rm != 0xF) { 4623 if (Rm != 0xD) { 4624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4625 return MCDisassembler::Fail; 4626 } else 4627 Inst.addOperand(MCOperand::createReg(0)); 4628 } 4629 4630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4631 return MCDisassembler::Fail; 4632 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4633 return MCDisassembler::Fail; 4634 Inst.addOperand(MCOperand::createImm(index)); 4635 4636 return S; 4637 } 4638 4639 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4640 uint64_t Address, const void *Decoder) { 4641 DecodeStatus S = MCDisassembler::Success; 4642 4643 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4644 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4645 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4646 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4647 unsigned size = fieldFromInstruction(Insn, 10, 2); 4648 4649 unsigned align = 0; 4650 unsigned index = 0; 4651 unsigned inc = 1; 4652 switch (size) { 4653 default: 4654 return MCDisassembler::Fail; 4655 case 0: 4656 if (fieldFromInstruction(Insn, 4, 1)) 4657 return MCDisassembler::Fail; // UNDEFINED 4658 index = fieldFromInstruction(Insn, 5, 3); 4659 break; 4660 case 1: 4661 if (fieldFromInstruction(Insn, 4, 1)) 4662 return MCDisassembler::Fail; // UNDEFINED 4663 index = fieldFromInstruction(Insn, 6, 2); 4664 if (fieldFromInstruction(Insn, 5, 1)) 4665 inc = 2; 4666 break; 4667 case 2: 4668 if (fieldFromInstruction(Insn, 4, 2)) 4669 return MCDisassembler::Fail; // UNDEFINED 4670 index = fieldFromInstruction(Insn, 7, 1); 4671 if (fieldFromInstruction(Insn, 6, 1)) 4672 inc = 2; 4673 break; 4674 } 4675 4676 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4677 return MCDisassembler::Fail; 4678 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 4683 if (Rm != 0xF) { // Writeback 4684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4685 return MCDisassembler::Fail; 4686 } 4687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4688 return MCDisassembler::Fail; 4689 Inst.addOperand(MCOperand::createImm(align)); 4690 if (Rm != 0xF) { 4691 if (Rm != 0xD) { 4692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4693 return MCDisassembler::Fail; 4694 } else 4695 Inst.addOperand(MCOperand::createReg(0)); 4696 } 4697 4698 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4699 return MCDisassembler::Fail; 4700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4701 return MCDisassembler::Fail; 4702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4703 return MCDisassembler::Fail; 4704 Inst.addOperand(MCOperand::createImm(index)); 4705 4706 return S; 4707 } 4708 4709 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4710 uint64_t Address, const void *Decoder) { 4711 DecodeStatus S = MCDisassembler::Success; 4712 4713 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4714 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4715 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4716 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4717 unsigned size = fieldFromInstruction(Insn, 10, 2); 4718 4719 unsigned align = 0; 4720 unsigned index = 0; 4721 unsigned inc = 1; 4722 switch (size) { 4723 default: 4724 return MCDisassembler::Fail; 4725 case 0: 4726 if (fieldFromInstruction(Insn, 4, 1)) 4727 return MCDisassembler::Fail; // UNDEFINED 4728 index = fieldFromInstruction(Insn, 5, 3); 4729 break; 4730 case 1: 4731 if (fieldFromInstruction(Insn, 4, 1)) 4732 return MCDisassembler::Fail; // UNDEFINED 4733 index = fieldFromInstruction(Insn, 6, 2); 4734 if (fieldFromInstruction(Insn, 5, 1)) 4735 inc = 2; 4736 break; 4737 case 2: 4738 if (fieldFromInstruction(Insn, 4, 2)) 4739 return MCDisassembler::Fail; // UNDEFINED 4740 index = fieldFromInstruction(Insn, 7, 1); 4741 if (fieldFromInstruction(Insn, 6, 1)) 4742 inc = 2; 4743 break; 4744 } 4745 4746 if (Rm != 0xF) { // Writeback 4747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4748 return MCDisassembler::Fail; 4749 } 4750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4751 return MCDisassembler::Fail; 4752 Inst.addOperand(MCOperand::createImm(align)); 4753 if (Rm != 0xF) { 4754 if (Rm != 0xD) { 4755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4756 return MCDisassembler::Fail; 4757 } else 4758 Inst.addOperand(MCOperand::createReg(0)); 4759 } 4760 4761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4762 return MCDisassembler::Fail; 4763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4764 return MCDisassembler::Fail; 4765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4766 return MCDisassembler::Fail; 4767 Inst.addOperand(MCOperand::createImm(index)); 4768 4769 return S; 4770 } 4771 4772 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4773 uint64_t Address, const void *Decoder) { 4774 DecodeStatus S = MCDisassembler::Success; 4775 4776 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4777 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4778 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4779 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4780 unsigned size = fieldFromInstruction(Insn, 10, 2); 4781 4782 unsigned align = 0; 4783 unsigned index = 0; 4784 unsigned inc = 1; 4785 switch (size) { 4786 default: 4787 return MCDisassembler::Fail; 4788 case 0: 4789 if (fieldFromInstruction(Insn, 4, 1)) 4790 align = 4; 4791 index = fieldFromInstruction(Insn, 5, 3); 4792 break; 4793 case 1: 4794 if (fieldFromInstruction(Insn, 4, 1)) 4795 align = 8; 4796 index = fieldFromInstruction(Insn, 6, 2); 4797 if (fieldFromInstruction(Insn, 5, 1)) 4798 inc = 2; 4799 break; 4800 case 2: 4801 switch (fieldFromInstruction(Insn, 4, 2)) { 4802 case 0: 4803 align = 0; break; 4804 case 3: 4805 return MCDisassembler::Fail; 4806 default: 4807 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4808 } 4809 4810 index = fieldFromInstruction(Insn, 7, 1); 4811 if (fieldFromInstruction(Insn, 6, 1)) 4812 inc = 2; 4813 break; 4814 } 4815 4816 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4817 return MCDisassembler::Fail; 4818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4819 return MCDisassembler::Fail; 4820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4821 return MCDisassembler::Fail; 4822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4823 return MCDisassembler::Fail; 4824 4825 if (Rm != 0xF) { // Writeback 4826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4827 return MCDisassembler::Fail; 4828 } 4829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4830 return MCDisassembler::Fail; 4831 Inst.addOperand(MCOperand::createImm(align)); 4832 if (Rm != 0xF) { 4833 if (Rm != 0xD) { 4834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4835 return MCDisassembler::Fail; 4836 } else 4837 Inst.addOperand(MCOperand::createReg(0)); 4838 } 4839 4840 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4841 return MCDisassembler::Fail; 4842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4843 return MCDisassembler::Fail; 4844 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4845 return MCDisassembler::Fail; 4846 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4847 return MCDisassembler::Fail; 4848 Inst.addOperand(MCOperand::createImm(index)); 4849 4850 return S; 4851 } 4852 4853 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4854 uint64_t Address, const void *Decoder) { 4855 DecodeStatus S = MCDisassembler::Success; 4856 4857 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4858 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4859 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4860 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4861 unsigned size = fieldFromInstruction(Insn, 10, 2); 4862 4863 unsigned align = 0; 4864 unsigned index = 0; 4865 unsigned inc = 1; 4866 switch (size) { 4867 default: 4868 return MCDisassembler::Fail; 4869 case 0: 4870 if (fieldFromInstruction(Insn, 4, 1)) 4871 align = 4; 4872 index = fieldFromInstruction(Insn, 5, 3); 4873 break; 4874 case 1: 4875 if (fieldFromInstruction(Insn, 4, 1)) 4876 align = 8; 4877 index = fieldFromInstruction(Insn, 6, 2); 4878 if (fieldFromInstruction(Insn, 5, 1)) 4879 inc = 2; 4880 break; 4881 case 2: 4882 switch (fieldFromInstruction(Insn, 4, 2)) { 4883 case 0: 4884 align = 0; break; 4885 case 3: 4886 return MCDisassembler::Fail; 4887 default: 4888 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4889 } 4890 4891 index = fieldFromInstruction(Insn, 7, 1); 4892 if (fieldFromInstruction(Insn, 6, 1)) 4893 inc = 2; 4894 break; 4895 } 4896 4897 if (Rm != 0xF) { // Writeback 4898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4899 return MCDisassembler::Fail; 4900 } 4901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4902 return MCDisassembler::Fail; 4903 Inst.addOperand(MCOperand::createImm(align)); 4904 if (Rm != 0xF) { 4905 if (Rm != 0xD) { 4906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4907 return MCDisassembler::Fail; 4908 } else 4909 Inst.addOperand(MCOperand::createReg(0)); 4910 } 4911 4912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4913 return MCDisassembler::Fail; 4914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4915 return MCDisassembler::Fail; 4916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4917 return MCDisassembler::Fail; 4918 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4919 return MCDisassembler::Fail; 4920 Inst.addOperand(MCOperand::createImm(index)); 4921 4922 return S; 4923 } 4924 4925 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4926 uint64_t Address, const void *Decoder) { 4927 DecodeStatus S = MCDisassembler::Success; 4928 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4929 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4930 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4931 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4932 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4933 4934 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4935 S = MCDisassembler::SoftFail; 4936 4937 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4938 return MCDisassembler::Fail; 4939 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4942 return MCDisassembler::Fail; 4943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4944 return MCDisassembler::Fail; 4945 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4946 return MCDisassembler::Fail; 4947 4948 return S; 4949 } 4950 4951 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4952 uint64_t Address, const void *Decoder) { 4953 DecodeStatus S = MCDisassembler::Success; 4954 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4955 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4956 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4957 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4958 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4959 4960 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4961 S = MCDisassembler::SoftFail; 4962 4963 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4964 return MCDisassembler::Fail; 4965 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4966 return MCDisassembler::Fail; 4967 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4968 return MCDisassembler::Fail; 4969 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4970 return MCDisassembler::Fail; 4971 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4972 return MCDisassembler::Fail; 4973 4974 return S; 4975 } 4976 4977 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4978 uint64_t Address, const void *Decoder) { 4979 DecodeStatus S = MCDisassembler::Success; 4980 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4981 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4982 4983 if (pred == 0xF) { 4984 pred = 0xE; 4985 S = MCDisassembler::SoftFail; 4986 } 4987 4988 if (mask == 0x0) 4989 return MCDisassembler::Fail; 4990 4991 Inst.addOperand(MCOperand::createImm(pred)); 4992 Inst.addOperand(MCOperand::createImm(mask)); 4993 return S; 4994 } 4995 4996 static DecodeStatus 4997 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4998 uint64_t Address, const void *Decoder) { 4999 DecodeStatus S = MCDisassembler::Success; 5000 5001 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5002 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5003 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5004 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5005 unsigned W = fieldFromInstruction(Insn, 21, 1); 5006 unsigned U = fieldFromInstruction(Insn, 23, 1); 5007 unsigned P = fieldFromInstruction(Insn, 24, 1); 5008 bool writeback = (W == 1) | (P == 0); 5009 5010 addr |= (U << 8) | (Rn << 9); 5011 5012 if (writeback && (Rn == Rt || Rn == Rt2)) 5013 Check(S, MCDisassembler::SoftFail); 5014 if (Rt == Rt2) 5015 Check(S, MCDisassembler::SoftFail); 5016 5017 // Rt 5018 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5019 return MCDisassembler::Fail; 5020 // Rt2 5021 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5022 return MCDisassembler::Fail; 5023 // Writeback operand 5024 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5025 return MCDisassembler::Fail; 5026 // addr 5027 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5028 return MCDisassembler::Fail; 5029 5030 return S; 5031 } 5032 5033 static DecodeStatus 5034 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5035 uint64_t Address, const void *Decoder) { 5036 DecodeStatus S = MCDisassembler::Success; 5037 5038 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5039 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5040 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5041 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5042 unsigned W = fieldFromInstruction(Insn, 21, 1); 5043 unsigned U = fieldFromInstruction(Insn, 23, 1); 5044 unsigned P = fieldFromInstruction(Insn, 24, 1); 5045 bool writeback = (W == 1) | (P == 0); 5046 5047 addr |= (U << 8) | (Rn << 9); 5048 5049 if (writeback && (Rn == Rt || Rn == Rt2)) 5050 Check(S, MCDisassembler::SoftFail); 5051 5052 // Writeback operand 5053 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5054 return MCDisassembler::Fail; 5055 // Rt 5056 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5057 return MCDisassembler::Fail; 5058 // Rt2 5059 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5060 return MCDisassembler::Fail; 5061 // addr 5062 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5063 return MCDisassembler::Fail; 5064 5065 return S; 5066 } 5067 5068 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5069 uint64_t Address, const void *Decoder) { 5070 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5071 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5072 if (sign1 != sign2) return MCDisassembler::Fail; 5073 5074 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5075 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5076 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5077 Val |= sign1 << 12; 5078 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5079 5080 return MCDisassembler::Success; 5081 } 5082 5083 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5084 uint64_t Address, 5085 const void *Decoder) { 5086 DecodeStatus S = MCDisassembler::Success; 5087 5088 // Shift of "asr #32" is not allowed in Thumb2 mode. 5089 if (Val == 0x20) S = MCDisassembler::Fail; 5090 Inst.addOperand(MCOperand::createImm(Val)); 5091 return S; 5092 } 5093 5094 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5095 uint64_t Address, const void *Decoder) { 5096 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5097 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5098 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5099 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5100 5101 if (pred == 0xF) 5102 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5103 5104 DecodeStatus S = MCDisassembler::Success; 5105 5106 if (Rt == Rn || Rn == Rt2) 5107 S = MCDisassembler::SoftFail; 5108 5109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5110 return MCDisassembler::Fail; 5111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5112 return MCDisassembler::Fail; 5113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5114 return MCDisassembler::Fail; 5115 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5116 return MCDisassembler::Fail; 5117 5118 return S; 5119 } 5120 5121 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5122 uint64_t Address, const void *Decoder) { 5123 const FeatureBitset &featureBits = 5124 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5125 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5126 5127 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5128 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5129 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5130 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5131 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5132 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5133 unsigned op = fieldFromInstruction(Insn, 5, 1); 5134 5135 DecodeStatus S = MCDisassembler::Success; 5136 5137 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5138 if (!(imm & 0x38)) { 5139 if (cmode == 0xF) { 5140 if (op == 1) return MCDisassembler::Fail; 5141 Inst.setOpcode(ARM::VMOVv2f32); 5142 } 5143 if (hasFullFP16) { 5144 if (cmode == 0xE) { 5145 if (op == 1) { 5146 Inst.setOpcode(ARM::VMOVv1i64); 5147 } else { 5148 Inst.setOpcode(ARM::VMOVv8i8); 5149 } 5150 } 5151 if (cmode == 0xD) { 5152 if (op == 1) { 5153 Inst.setOpcode(ARM::VMVNv2i32); 5154 } else { 5155 Inst.setOpcode(ARM::VMOVv2i32); 5156 } 5157 } 5158 if (cmode == 0xC) { 5159 if (op == 1) { 5160 Inst.setOpcode(ARM::VMVNv2i32); 5161 } else { 5162 Inst.setOpcode(ARM::VMOVv2i32); 5163 } 5164 } 5165 } 5166 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5167 } 5168 5169 if (!(imm & 0x20)) return MCDisassembler::Fail; 5170 5171 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5172 return MCDisassembler::Fail; 5173 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5174 return MCDisassembler::Fail; 5175 Inst.addOperand(MCOperand::createImm(64 - imm)); 5176 5177 return S; 5178 } 5179 5180 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5181 uint64_t Address, const void *Decoder) { 5182 const FeatureBitset &featureBits = 5183 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5184 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5185 5186 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5187 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5188 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5189 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5190 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5191 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5192 unsigned op = fieldFromInstruction(Insn, 5, 1); 5193 5194 DecodeStatus S = MCDisassembler::Success; 5195 5196 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5197 if (!(imm & 0x38)) { 5198 if (cmode == 0xF) { 5199 if (op == 1) return MCDisassembler::Fail; 5200 Inst.setOpcode(ARM::VMOVv4f32); 5201 } 5202 if (hasFullFP16) { 5203 if (cmode == 0xE) { 5204 if (op == 1) { 5205 Inst.setOpcode(ARM::VMOVv2i64); 5206 } else { 5207 Inst.setOpcode(ARM::VMOVv16i8); 5208 } 5209 } 5210 if (cmode == 0xD) { 5211 if (op == 1) { 5212 Inst.setOpcode(ARM::VMVNv4i32); 5213 } else { 5214 Inst.setOpcode(ARM::VMOVv4i32); 5215 } 5216 } 5217 if (cmode == 0xC) { 5218 if (op == 1) { 5219 Inst.setOpcode(ARM::VMVNv4i32); 5220 } else { 5221 Inst.setOpcode(ARM::VMOVv4i32); 5222 } 5223 } 5224 } 5225 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5226 } 5227 5228 if (!(imm & 0x20)) return MCDisassembler::Fail; 5229 5230 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5231 return MCDisassembler::Fail; 5232 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5233 return MCDisassembler::Fail; 5234 Inst.addOperand(MCOperand::createImm(64 - imm)); 5235 5236 return S; 5237 } 5238 5239 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5240 uint64_t Address, const void *Decoder) { 5241 DecodeStatus S = MCDisassembler::Success; 5242 5243 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5244 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5245 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5246 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5247 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5248 5249 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5250 S = MCDisassembler::SoftFail; 5251 5252 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5253 return MCDisassembler::Fail; 5254 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5255 return MCDisassembler::Fail; 5256 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5257 return MCDisassembler::Fail; 5258 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5259 return MCDisassembler::Fail; 5260 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5261 return MCDisassembler::Fail; 5262 5263 return S; 5264 } 5265 5266 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5267 uint64_t Address, const void *Decoder) { 5268 DecodeStatus S = MCDisassembler::Success; 5269 5270 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5271 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5272 unsigned cop = fieldFromInstruction(Val, 8, 4); 5273 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5274 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5275 5276 if ((cop & ~0x1) == 0xa) 5277 return MCDisassembler::Fail; 5278 5279 if (Rt == Rt2) 5280 S = MCDisassembler::SoftFail; 5281 5282 // We have to check if the instruction is MRRC2 5283 // or MCRR2 when constructing the operands for 5284 // Inst. Reason is because MRRC2 stores to two 5285 // registers so it's tablegen desc has has two 5286 // outputs whereas MCRR doesn't store to any 5287 // registers so all of it's operands are listed 5288 // as inputs, therefore the operand order for 5289 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5290 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5291 5292 if (Inst.getOpcode() == ARM::MRRC2) { 5293 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5294 return MCDisassembler::Fail; 5295 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5296 return MCDisassembler::Fail; 5297 } 5298 Inst.addOperand(MCOperand::createImm(cop)); 5299 Inst.addOperand(MCOperand::createImm(opc1)); 5300 if (Inst.getOpcode() == ARM::MCRR2) { 5301 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5302 return MCDisassembler::Fail; 5303 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5304 return MCDisassembler::Fail; 5305 } 5306 Inst.addOperand(MCOperand::createImm(CRm)); 5307 5308 return S; 5309 } 5310