1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCTargetAsmParser.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "llvm/ADT/BitVector.h" 15 #include "llvm/ADT/OwningPtr.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Twine.h" 20 #include "llvm/MC/MCAsmInfo.h" 21 #include "llvm/MC/MCAssembler.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCELFStreamer.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCInst.h" 26 #include "llvm/MC/MCInstrDesc.h" 27 #include "llvm/MC/MCParser/MCAsmLexer.h" 28 #include "llvm/MC/MCParser/MCAsmParser.h" 29 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCStreamer.h" 32 #include "llvm/MC/MCSubtargetInfo.h" 33 #include "llvm/Support/ELF.h" 34 #include "llvm/Support/MathExtras.h" 35 #include "llvm/Support/SourceMgr.h" 36 #include "llvm/Support/TargetRegistry.h" 37 #include "llvm/Support/raw_ostream.h" 38 39 using namespace llvm; 40 41 namespace { 42 43 class ARMOperand; 44 45 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 46 47 class ARMAsmParser : public MCTargetAsmParser { 48 MCSubtargetInfo &STI; 49 MCAsmParser &Parser; 50 const MCRegisterInfo *MRI; 51 52 // Unwind directives state 53 SMLoc FnStartLoc; 54 SMLoc CantUnwindLoc; 55 SMLoc PersonalityLoc; 56 SMLoc HandlerDataLoc; 57 int FPReg; 58 void resetUnwindDirectiveParserState() { 59 FnStartLoc = SMLoc(); 60 CantUnwindLoc = SMLoc(); 61 PersonalityLoc = SMLoc(); 62 HandlerDataLoc = SMLoc(); 63 FPReg = -1; 64 } 65 66 // Map of register aliases registers via the .req directive. 67 StringMap<unsigned> RegisterReqs; 68 69 struct { 70 ARMCC::CondCodes Cond; // Condition for IT block. 71 unsigned Mask:4; // Condition mask for instructions. 72 // Starting at first 1 (from lsb). 73 // '1' condition as indicated in IT. 74 // '0' inverse of condition (else). 75 // Count of instructions in IT block is 76 // 4 - trailingzeroes(mask) 77 78 bool FirstCond; // Explicit flag for when we're parsing the 79 // First instruction in the IT block. It's 80 // implied in the mask, so needs special 81 // handling. 82 83 unsigned CurPosition; // Current position in parsing of IT 84 // block. In range [0,3]. Initialized 85 // according to count of instructions in block. 86 // ~0U if no active IT block. 87 } ITState; 88 bool inITBlock() { return ITState.CurPosition != ~0U;} 89 void forwardITPosition() { 90 if (!inITBlock()) return; 91 // Move to the next instruction in the IT block, if there is one. If not, 92 // mark the block as done. 93 unsigned TZ = countTrailingZeros(ITState.Mask); 94 if (++ITState.CurPosition == 5 - TZ) 95 ITState.CurPosition = ~0U; // Done with the IT block after this. 96 } 97 98 99 MCAsmParser &getParser() const { return Parser; } 100 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 101 102 bool Warning(SMLoc L, const Twine &Msg, 103 ArrayRef<SMRange> Ranges = None) { 104 return Parser.Warning(L, Msg, Ranges); 105 } 106 bool Error(SMLoc L, const Twine &Msg, 107 ArrayRef<SMRange> Ranges = None) { 108 return Parser.Error(L, Msg, Ranges); 109 } 110 111 int tryParseRegister(); 112 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 113 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 114 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 115 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 116 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 117 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 118 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 119 unsigned &ShiftAmount); 120 bool parseDirectiveWord(unsigned Size, SMLoc L); 121 bool parseDirectiveThumb(SMLoc L); 122 bool parseDirectiveARM(SMLoc L); 123 bool parseDirectiveThumbFunc(SMLoc L); 124 bool parseDirectiveCode(SMLoc L); 125 bool parseDirectiveSyntax(SMLoc L); 126 bool parseDirectiveReq(StringRef Name, SMLoc L); 127 bool parseDirectiveUnreq(SMLoc L); 128 bool parseDirectiveArch(SMLoc L); 129 bool parseDirectiveEabiAttr(SMLoc L); 130 bool parseDirectiveFnStart(SMLoc L); 131 bool parseDirectiveFnEnd(SMLoc L); 132 bool parseDirectiveCantUnwind(SMLoc L); 133 bool parseDirectivePersonality(SMLoc L); 134 bool parseDirectiveHandlerData(SMLoc L); 135 bool parseDirectiveSetFP(SMLoc L); 136 bool parseDirectivePad(SMLoc L); 137 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 138 139 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 140 bool &CarrySetting, unsigned &ProcessorIMod, 141 StringRef &ITMask); 142 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 143 bool &CanAcceptPredicationCode); 144 145 bool isThumb() const { 146 // FIXME: Can tablegen auto-generate this? 147 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 148 } 149 bool isThumbOne() const { 150 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 151 } 152 bool isThumbTwo() const { 153 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 154 } 155 bool hasThumb() const { 156 return STI.getFeatureBits() & ARM::HasV4TOps; 157 } 158 bool hasV6Ops() const { 159 return STI.getFeatureBits() & ARM::HasV6Ops; 160 } 161 bool hasV7Ops() const { 162 return STI.getFeatureBits() & ARM::HasV7Ops; 163 } 164 bool hasV8Ops() const { 165 return STI.getFeatureBits() & ARM::HasV8Ops; 166 } 167 bool hasARM() const { 168 return !(STI.getFeatureBits() & ARM::FeatureNoARM); 169 } 170 171 void SwitchMode() { 172 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 173 setAvailableFeatures(FB); 174 } 175 bool isMClass() const { 176 return STI.getFeatureBits() & ARM::FeatureMClass; 177 } 178 179 /// @name Auto-generated Match Functions 180 /// { 181 182 #define GET_ASSEMBLER_HEADER 183 #include "ARMGenAsmMatcher.inc" 184 185 /// } 186 187 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 188 OperandMatchResultTy parseCoprocNumOperand( 189 SmallVectorImpl<MCParsedAsmOperand*>&); 190 OperandMatchResultTy parseCoprocRegOperand( 191 SmallVectorImpl<MCParsedAsmOperand*>&); 192 OperandMatchResultTy parseCoprocOptionOperand( 193 SmallVectorImpl<MCParsedAsmOperand*>&); 194 OperandMatchResultTy parseMemBarrierOptOperand( 195 SmallVectorImpl<MCParsedAsmOperand*>&); 196 OperandMatchResultTy parseInstSyncBarrierOptOperand( 197 SmallVectorImpl<MCParsedAsmOperand*>&); 198 OperandMatchResultTy parseProcIFlagsOperand( 199 SmallVectorImpl<MCParsedAsmOperand*>&); 200 OperandMatchResultTy parseMSRMaskOperand( 201 SmallVectorImpl<MCParsedAsmOperand*>&); 202 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 203 StringRef Op, int Low, int High); 204 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 205 return parsePKHImm(O, "lsl", 0, 31); 206 } 207 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 208 return parsePKHImm(O, "asr", 1, 32); 209 } 210 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 211 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 212 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 213 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 214 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 215 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 216 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 217 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 218 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 219 SMLoc &EndLoc); 220 221 // Asm Match Converter Methods 222 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 223 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 224 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 225 const SmallVectorImpl<MCParsedAsmOperand*> &); 226 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 227 const SmallVectorImpl<MCParsedAsmOperand*> &); 228 void cvtLdWriteBackRegAddrMode2(MCInst &Inst, 229 const SmallVectorImpl<MCParsedAsmOperand*> &); 230 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 231 const SmallVectorImpl<MCParsedAsmOperand*> &); 232 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 233 const SmallVectorImpl<MCParsedAsmOperand*> &); 234 void cvtStWriteBackRegAddrMode2(MCInst &Inst, 235 const SmallVectorImpl<MCParsedAsmOperand*> &); 236 void cvtStWriteBackRegAddrMode3(MCInst &Inst, 237 const SmallVectorImpl<MCParsedAsmOperand*> &); 238 void cvtLdExtTWriteBackImm(MCInst &Inst, 239 const SmallVectorImpl<MCParsedAsmOperand*> &); 240 void cvtLdExtTWriteBackReg(MCInst &Inst, 241 const SmallVectorImpl<MCParsedAsmOperand*> &); 242 void cvtStExtTWriteBackImm(MCInst &Inst, 243 const SmallVectorImpl<MCParsedAsmOperand*> &); 244 void cvtStExtTWriteBackReg(MCInst &Inst, 245 const SmallVectorImpl<MCParsedAsmOperand*> &); 246 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 247 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 248 void cvtLdWriteBackRegAddrMode3(MCInst &Inst, 249 const SmallVectorImpl<MCParsedAsmOperand*> &); 250 void cvtThumbMultiply(MCInst &Inst, 251 const SmallVectorImpl<MCParsedAsmOperand*> &); 252 void cvtVLDwbFixed(MCInst &Inst, 253 const SmallVectorImpl<MCParsedAsmOperand*> &); 254 void cvtVLDwbRegister(MCInst &Inst, 255 const SmallVectorImpl<MCParsedAsmOperand*> &); 256 void cvtVSTwbFixed(MCInst &Inst, 257 const SmallVectorImpl<MCParsedAsmOperand*> &); 258 void cvtVSTwbRegister(MCInst &Inst, 259 const SmallVectorImpl<MCParsedAsmOperand*> &); 260 bool validateInstruction(MCInst &Inst, 261 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 262 bool processInstruction(MCInst &Inst, 263 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 264 bool shouldOmitCCOutOperand(StringRef Mnemonic, 265 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 266 267 public: 268 enum ARMMatchResultTy { 269 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 270 Match_RequiresNotITBlock, 271 Match_RequiresV6, 272 Match_RequiresThumb2, 273 #define GET_OPERAND_DIAGNOSTIC_TYPES 274 #include "ARMGenAsmMatcher.inc" 275 276 }; 277 278 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 279 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) { 280 MCAsmParserExtension::Initialize(_Parser); 281 282 // Cache the MCRegisterInfo. 283 MRI = getContext().getRegisterInfo(); 284 285 // Initialize the set of available features. 286 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 287 288 // Not in an ITBlock to start with. 289 ITState.CurPosition = ~0U; 290 291 // Set ELF header flags. 292 // FIXME: This should eventually end up somewhere else where more 293 // intelligent flag decisions can be made. For now we are just maintaining 294 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default. 295 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer())) 296 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5); 297 } 298 299 // Implementation of the MCTargetAsmParser interface: 300 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 301 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 302 SMLoc NameLoc, 303 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 304 bool ParseDirective(AsmToken DirectiveID); 305 306 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); 307 unsigned checkTargetMatchPredicate(MCInst &Inst); 308 309 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 310 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 311 MCStreamer &Out, unsigned &ErrorInfo, 312 bool MatchingInlineAsm); 313 }; 314 } // end anonymous namespace 315 316 namespace { 317 318 /// ARMOperand - Instances of this class represent a parsed ARM machine 319 /// operand. 320 class ARMOperand : public MCParsedAsmOperand { 321 enum KindTy { 322 k_CondCode, 323 k_CCOut, 324 k_ITCondMask, 325 k_CoprocNum, 326 k_CoprocReg, 327 k_CoprocOption, 328 k_Immediate, 329 k_MemBarrierOpt, 330 k_InstSyncBarrierOpt, 331 k_Memory, 332 k_PostIndexRegister, 333 k_MSRMask, 334 k_ProcIFlags, 335 k_VectorIndex, 336 k_Register, 337 k_RegisterList, 338 k_DPRRegisterList, 339 k_SPRRegisterList, 340 k_VectorList, 341 k_VectorListAllLanes, 342 k_VectorListIndexed, 343 k_ShiftedRegister, 344 k_ShiftedImmediate, 345 k_ShifterImmediate, 346 k_RotateImmediate, 347 k_BitfieldDescriptor, 348 k_Token 349 } Kind; 350 351 SMLoc StartLoc, EndLoc; 352 SmallVector<unsigned, 8> Registers; 353 354 struct CCOp { 355 ARMCC::CondCodes Val; 356 }; 357 358 struct CopOp { 359 unsigned Val; 360 }; 361 362 struct CoprocOptionOp { 363 unsigned Val; 364 }; 365 366 struct ITMaskOp { 367 unsigned Mask:4; 368 }; 369 370 struct MBOptOp { 371 ARM_MB::MemBOpt Val; 372 }; 373 374 struct ISBOptOp { 375 ARM_ISB::InstSyncBOpt Val; 376 }; 377 378 struct IFlagsOp { 379 ARM_PROC::IFlags Val; 380 }; 381 382 struct MMaskOp { 383 unsigned Val; 384 }; 385 386 struct TokOp { 387 const char *Data; 388 unsigned Length; 389 }; 390 391 struct RegOp { 392 unsigned RegNum; 393 }; 394 395 // A vector register list is a sequential list of 1 to 4 registers. 396 struct VectorListOp { 397 unsigned RegNum; 398 unsigned Count; 399 unsigned LaneIndex; 400 bool isDoubleSpaced; 401 }; 402 403 struct VectorIndexOp { 404 unsigned Val; 405 }; 406 407 struct ImmOp { 408 const MCExpr *Val; 409 }; 410 411 /// Combined record for all forms of ARM address expressions. 412 struct MemoryOp { 413 unsigned BaseRegNum; 414 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 415 // was specified. 416 const MCConstantExpr *OffsetImm; // Offset immediate value 417 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 418 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 419 unsigned ShiftImm; // shift for OffsetReg. 420 unsigned Alignment; // 0 = no alignment specified 421 // n = alignment in bytes (2, 4, 8, 16, or 32) 422 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 423 }; 424 425 struct PostIdxRegOp { 426 unsigned RegNum; 427 bool isAdd; 428 ARM_AM::ShiftOpc ShiftTy; 429 unsigned ShiftImm; 430 }; 431 432 struct ShifterImmOp { 433 bool isASR; 434 unsigned Imm; 435 }; 436 437 struct RegShiftedRegOp { 438 ARM_AM::ShiftOpc ShiftTy; 439 unsigned SrcReg; 440 unsigned ShiftReg; 441 unsigned ShiftImm; 442 }; 443 444 struct RegShiftedImmOp { 445 ARM_AM::ShiftOpc ShiftTy; 446 unsigned SrcReg; 447 unsigned ShiftImm; 448 }; 449 450 struct RotImmOp { 451 unsigned Imm; 452 }; 453 454 struct BitfieldOp { 455 unsigned LSB; 456 unsigned Width; 457 }; 458 459 union { 460 struct CCOp CC; 461 struct CopOp Cop; 462 struct CoprocOptionOp CoprocOption; 463 struct MBOptOp MBOpt; 464 struct ISBOptOp ISBOpt; 465 struct ITMaskOp ITMask; 466 struct IFlagsOp IFlags; 467 struct MMaskOp MMask; 468 struct TokOp Tok; 469 struct RegOp Reg; 470 struct VectorListOp VectorList; 471 struct VectorIndexOp VectorIndex; 472 struct ImmOp Imm; 473 struct MemoryOp Memory; 474 struct PostIdxRegOp PostIdxReg; 475 struct ShifterImmOp ShifterImm; 476 struct RegShiftedRegOp RegShiftedReg; 477 struct RegShiftedImmOp RegShiftedImm; 478 struct RotImmOp RotImm; 479 struct BitfieldOp Bitfield; 480 }; 481 482 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 483 public: 484 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 485 Kind = o.Kind; 486 StartLoc = o.StartLoc; 487 EndLoc = o.EndLoc; 488 switch (Kind) { 489 case k_CondCode: 490 CC = o.CC; 491 break; 492 case k_ITCondMask: 493 ITMask = o.ITMask; 494 break; 495 case k_Token: 496 Tok = o.Tok; 497 break; 498 case k_CCOut: 499 case k_Register: 500 Reg = o.Reg; 501 break; 502 case k_RegisterList: 503 case k_DPRRegisterList: 504 case k_SPRRegisterList: 505 Registers = o.Registers; 506 break; 507 case k_VectorList: 508 case k_VectorListAllLanes: 509 case k_VectorListIndexed: 510 VectorList = o.VectorList; 511 break; 512 case k_CoprocNum: 513 case k_CoprocReg: 514 Cop = o.Cop; 515 break; 516 case k_CoprocOption: 517 CoprocOption = o.CoprocOption; 518 break; 519 case k_Immediate: 520 Imm = o.Imm; 521 break; 522 case k_MemBarrierOpt: 523 MBOpt = o.MBOpt; 524 break; 525 case k_InstSyncBarrierOpt: 526 ISBOpt = o.ISBOpt; 527 case k_Memory: 528 Memory = o.Memory; 529 break; 530 case k_PostIndexRegister: 531 PostIdxReg = o.PostIdxReg; 532 break; 533 case k_MSRMask: 534 MMask = o.MMask; 535 break; 536 case k_ProcIFlags: 537 IFlags = o.IFlags; 538 break; 539 case k_ShifterImmediate: 540 ShifterImm = o.ShifterImm; 541 break; 542 case k_ShiftedRegister: 543 RegShiftedReg = o.RegShiftedReg; 544 break; 545 case k_ShiftedImmediate: 546 RegShiftedImm = o.RegShiftedImm; 547 break; 548 case k_RotateImmediate: 549 RotImm = o.RotImm; 550 break; 551 case k_BitfieldDescriptor: 552 Bitfield = o.Bitfield; 553 break; 554 case k_VectorIndex: 555 VectorIndex = o.VectorIndex; 556 break; 557 } 558 } 559 560 /// getStartLoc - Get the location of the first token of this operand. 561 SMLoc getStartLoc() const { return StartLoc; } 562 /// getEndLoc - Get the location of the last token of this operand. 563 SMLoc getEndLoc() const { return EndLoc; } 564 /// getLocRange - Get the range between the first and last token of this 565 /// operand. 566 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 567 568 ARMCC::CondCodes getCondCode() const { 569 assert(Kind == k_CondCode && "Invalid access!"); 570 return CC.Val; 571 } 572 573 unsigned getCoproc() const { 574 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 575 return Cop.Val; 576 } 577 578 StringRef getToken() const { 579 assert(Kind == k_Token && "Invalid access!"); 580 return StringRef(Tok.Data, Tok.Length); 581 } 582 583 unsigned getReg() const { 584 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 585 return Reg.RegNum; 586 } 587 588 const SmallVectorImpl<unsigned> &getRegList() const { 589 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 590 Kind == k_SPRRegisterList) && "Invalid access!"); 591 return Registers; 592 } 593 594 const MCExpr *getImm() const { 595 assert(isImm() && "Invalid access!"); 596 return Imm.Val; 597 } 598 599 unsigned getVectorIndex() const { 600 assert(Kind == k_VectorIndex && "Invalid access!"); 601 return VectorIndex.Val; 602 } 603 604 ARM_MB::MemBOpt getMemBarrierOpt() const { 605 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 606 return MBOpt.Val; 607 } 608 609 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 610 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 611 return ISBOpt.Val; 612 } 613 614 ARM_PROC::IFlags getProcIFlags() const { 615 assert(Kind == k_ProcIFlags && "Invalid access!"); 616 return IFlags.Val; 617 } 618 619 unsigned getMSRMask() const { 620 assert(Kind == k_MSRMask && "Invalid access!"); 621 return MMask.Val; 622 } 623 624 bool isCoprocNum() const { return Kind == k_CoprocNum; } 625 bool isCoprocReg() const { return Kind == k_CoprocReg; } 626 bool isCoprocOption() const { return Kind == k_CoprocOption; } 627 bool isCondCode() const { return Kind == k_CondCode; } 628 bool isCCOut() const { return Kind == k_CCOut; } 629 bool isITMask() const { return Kind == k_ITCondMask; } 630 bool isITCondCode() const { return Kind == k_CondCode; } 631 bool isImm() const { return Kind == k_Immediate; } 632 bool isFPImm() const { 633 if (!isImm()) return false; 634 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 635 if (!CE) return false; 636 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 637 return Val != -1; 638 } 639 bool isFBits16() const { 640 if (!isImm()) return false; 641 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 642 if (!CE) return false; 643 int64_t Value = CE->getValue(); 644 return Value >= 0 && Value <= 16; 645 } 646 bool isFBits32() const { 647 if (!isImm()) return false; 648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 649 if (!CE) return false; 650 int64_t Value = CE->getValue(); 651 return Value >= 1 && Value <= 32; 652 } 653 bool isImm8s4() const { 654 if (!isImm()) return false; 655 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 656 if (!CE) return false; 657 int64_t Value = CE->getValue(); 658 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 659 } 660 bool isImm0_4() const { 661 if (!isImm()) return false; 662 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 663 if (!CE) return false; 664 int64_t Value = CE->getValue(); 665 return Value >= 0 && Value < 5; 666 } 667 bool isImm0_1020s4() const { 668 if (!isImm()) return false; 669 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 670 if (!CE) return false; 671 int64_t Value = CE->getValue(); 672 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 673 } 674 bool isImm0_508s4() const { 675 if (!isImm()) return false; 676 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 677 if (!CE) return false; 678 int64_t Value = CE->getValue(); 679 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 680 } 681 bool isImm0_508s4Neg() const { 682 if (!isImm()) return false; 683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 684 if (!CE) return false; 685 int64_t Value = -CE->getValue(); 686 // explicitly exclude zero. we want that to use the normal 0_508 version. 687 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 688 } 689 bool isImm0_255() const { 690 if (!isImm()) return false; 691 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 692 if (!CE) return false; 693 int64_t Value = CE->getValue(); 694 return Value >= 0 && Value < 256; 695 } 696 bool isImm0_4095() const { 697 if (!isImm()) return false; 698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 699 if (!CE) return false; 700 int64_t Value = CE->getValue(); 701 return Value >= 0 && Value < 4096; 702 } 703 bool isImm0_4095Neg() const { 704 if (!isImm()) return false; 705 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 706 if (!CE) return false; 707 int64_t Value = -CE->getValue(); 708 return Value > 0 && Value < 4096; 709 } 710 bool isImm0_1() const { 711 if (!isImm()) return false; 712 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 713 if (!CE) return false; 714 int64_t Value = CE->getValue(); 715 return Value >= 0 && Value < 2; 716 } 717 bool isImm0_3() const { 718 if (!isImm()) return false; 719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 720 if (!CE) return false; 721 int64_t Value = CE->getValue(); 722 return Value >= 0 && Value < 4; 723 } 724 bool isImm0_7() const { 725 if (!isImm()) return false; 726 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 727 if (!CE) return false; 728 int64_t Value = CE->getValue(); 729 return Value >= 0 && Value < 8; 730 } 731 bool isImm0_15() const { 732 if (!isImm()) return false; 733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 734 if (!CE) return false; 735 int64_t Value = CE->getValue(); 736 return Value >= 0 && Value < 16; 737 } 738 bool isImm0_31() const { 739 if (!isImm()) return false; 740 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 741 if (!CE) return false; 742 int64_t Value = CE->getValue(); 743 return Value >= 0 && Value < 32; 744 } 745 bool isImm0_63() const { 746 if (!isImm()) return false; 747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 748 if (!CE) return false; 749 int64_t Value = CE->getValue(); 750 return Value >= 0 && Value < 64; 751 } 752 bool isImm8() const { 753 if (!isImm()) return false; 754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 755 if (!CE) return false; 756 int64_t Value = CE->getValue(); 757 return Value == 8; 758 } 759 bool isImm16() const { 760 if (!isImm()) return false; 761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 762 if (!CE) return false; 763 int64_t Value = CE->getValue(); 764 return Value == 16; 765 } 766 bool isImm32() const { 767 if (!isImm()) return false; 768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 769 if (!CE) return false; 770 int64_t Value = CE->getValue(); 771 return Value == 32; 772 } 773 bool isShrImm8() const { 774 if (!isImm()) return false; 775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 776 if (!CE) return false; 777 int64_t Value = CE->getValue(); 778 return Value > 0 && Value <= 8; 779 } 780 bool isShrImm16() const { 781 if (!isImm()) return false; 782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 783 if (!CE) return false; 784 int64_t Value = CE->getValue(); 785 return Value > 0 && Value <= 16; 786 } 787 bool isShrImm32() const { 788 if (!isImm()) return false; 789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 790 if (!CE) return false; 791 int64_t Value = CE->getValue(); 792 return Value > 0 && Value <= 32; 793 } 794 bool isShrImm64() const { 795 if (!isImm()) return false; 796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 797 if (!CE) return false; 798 int64_t Value = CE->getValue(); 799 return Value > 0 && Value <= 64; 800 } 801 bool isImm1_7() const { 802 if (!isImm()) return false; 803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 804 if (!CE) return false; 805 int64_t Value = CE->getValue(); 806 return Value > 0 && Value < 8; 807 } 808 bool isImm1_15() const { 809 if (!isImm()) return false; 810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 811 if (!CE) return false; 812 int64_t Value = CE->getValue(); 813 return Value > 0 && Value < 16; 814 } 815 bool isImm1_31() const { 816 if (!isImm()) return false; 817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 818 if (!CE) return false; 819 int64_t Value = CE->getValue(); 820 return Value > 0 && Value < 32; 821 } 822 bool isImm1_16() const { 823 if (!isImm()) return false; 824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 825 if (!CE) return false; 826 int64_t Value = CE->getValue(); 827 return Value > 0 && Value < 17; 828 } 829 bool isImm1_32() const { 830 if (!isImm()) return false; 831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 832 if (!CE) return false; 833 int64_t Value = CE->getValue(); 834 return Value > 0 && Value < 33; 835 } 836 bool isImm0_32() const { 837 if (!isImm()) return false; 838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 839 if (!CE) return false; 840 int64_t Value = CE->getValue(); 841 return Value >= 0 && Value < 33; 842 } 843 bool isImm0_65535() const { 844 if (!isImm()) return false; 845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 846 if (!CE) return false; 847 int64_t Value = CE->getValue(); 848 return Value >= 0 && Value < 65536; 849 } 850 bool isImm0_65535Expr() const { 851 if (!isImm()) return false; 852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 853 // If it's not a constant expression, it'll generate a fixup and be 854 // handled later. 855 if (!CE) return true; 856 int64_t Value = CE->getValue(); 857 return Value >= 0 && Value < 65536; 858 } 859 bool isImm24bit() const { 860 if (!isImm()) return false; 861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 862 if (!CE) return false; 863 int64_t Value = CE->getValue(); 864 return Value >= 0 && Value <= 0xffffff; 865 } 866 bool isImmThumbSR() const { 867 if (!isImm()) return false; 868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 869 if (!CE) return false; 870 int64_t Value = CE->getValue(); 871 return Value > 0 && Value < 33; 872 } 873 bool isPKHLSLImm() const { 874 if (!isImm()) return false; 875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 876 if (!CE) return false; 877 int64_t Value = CE->getValue(); 878 return Value >= 0 && Value < 32; 879 } 880 bool isPKHASRImm() const { 881 if (!isImm()) return false; 882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 883 if (!CE) return false; 884 int64_t Value = CE->getValue(); 885 return Value > 0 && Value <= 32; 886 } 887 bool isAdrLabel() const { 888 // If we have an immediate that's not a constant, treat it as a label 889 // reference needing a fixup. If it is a constant, but it can't fit 890 // into shift immediate encoding, we reject it. 891 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 892 else return (isARMSOImm() || isARMSOImmNeg()); 893 } 894 bool isARMSOImm() const { 895 if (!isImm()) return false; 896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 897 if (!CE) return false; 898 int64_t Value = CE->getValue(); 899 return ARM_AM::getSOImmVal(Value) != -1; 900 } 901 bool isARMSOImmNot() const { 902 if (!isImm()) return false; 903 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 904 if (!CE) return false; 905 int64_t Value = CE->getValue(); 906 return ARM_AM::getSOImmVal(~Value) != -1; 907 } 908 bool isARMSOImmNeg() const { 909 if (!isImm()) return false; 910 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 911 if (!CE) return false; 912 int64_t Value = CE->getValue(); 913 // Only use this when not representable as a plain so_imm. 914 return ARM_AM::getSOImmVal(Value) == -1 && 915 ARM_AM::getSOImmVal(-Value) != -1; 916 } 917 bool isT2SOImm() const { 918 if (!isImm()) return false; 919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 920 if (!CE) return false; 921 int64_t Value = CE->getValue(); 922 return ARM_AM::getT2SOImmVal(Value) != -1; 923 } 924 bool isT2SOImmNot() const { 925 if (!isImm()) return false; 926 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 927 if (!CE) return false; 928 int64_t Value = CE->getValue(); 929 return ARM_AM::getT2SOImmVal(~Value) != -1; 930 } 931 bool isT2SOImmNeg() const { 932 if (!isImm()) return false; 933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 934 if (!CE) return false; 935 int64_t Value = CE->getValue(); 936 // Only use this when not representable as a plain so_imm. 937 return ARM_AM::getT2SOImmVal(Value) == -1 && 938 ARM_AM::getT2SOImmVal(-Value) != -1; 939 } 940 bool isSetEndImm() const { 941 if (!isImm()) return false; 942 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 943 if (!CE) return false; 944 int64_t Value = CE->getValue(); 945 return Value == 1 || Value == 0; 946 } 947 bool isReg() const { return Kind == k_Register; } 948 bool isRegList() const { return Kind == k_RegisterList; } 949 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 950 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 951 bool isToken() const { return Kind == k_Token; } 952 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 953 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 954 bool isMem() const { return Kind == k_Memory; } 955 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 956 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 957 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 958 bool isRotImm() const { return Kind == k_RotateImmediate; } 959 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 960 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 961 bool isPostIdxReg() const { 962 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 963 } 964 bool isMemNoOffset(bool alignOK = false) const { 965 if (!isMem()) 966 return false; 967 // No offset of any kind. 968 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 969 (alignOK || Memory.Alignment == 0); 970 } 971 bool isMemPCRelImm12() const { 972 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 973 return false; 974 // Base register must be PC. 975 if (Memory.BaseRegNum != ARM::PC) 976 return false; 977 // Immediate offset in range [-4095, 4095]. 978 if (!Memory.OffsetImm) return true; 979 int64_t Val = Memory.OffsetImm->getValue(); 980 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 981 } 982 bool isAlignedMemory() const { 983 return isMemNoOffset(true); 984 } 985 bool isAddrMode2() const { 986 if (!isMem() || Memory.Alignment != 0) return false; 987 // Check for register offset. 988 if (Memory.OffsetRegNum) return true; 989 // Immediate offset in range [-4095, 4095]. 990 if (!Memory.OffsetImm) return true; 991 int64_t Val = Memory.OffsetImm->getValue(); 992 return Val > -4096 && Val < 4096; 993 } 994 bool isAM2OffsetImm() const { 995 if (!isImm()) return false; 996 // Immediate offset in range [-4095, 4095]. 997 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 998 if (!CE) return false; 999 int64_t Val = CE->getValue(); 1000 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 1001 } 1002 bool isAddrMode3() const { 1003 // If we have an immediate that's not a constant, treat it as a label 1004 // reference needing a fixup. If it is a constant, it's something else 1005 // and we reject it. 1006 if (isImm() && !isa<MCConstantExpr>(getImm())) 1007 return true; 1008 if (!isMem() || Memory.Alignment != 0) return false; 1009 // No shifts are legal for AM3. 1010 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1011 // Check for register offset. 1012 if (Memory.OffsetRegNum) return true; 1013 // Immediate offset in range [-255, 255]. 1014 if (!Memory.OffsetImm) return true; 1015 int64_t Val = Memory.OffsetImm->getValue(); 1016 // The #-0 offset is encoded as INT32_MIN, and we have to check 1017 // for this too. 1018 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1019 } 1020 bool isAM3Offset() const { 1021 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1022 return false; 1023 if (Kind == k_PostIndexRegister) 1024 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1025 // Immediate offset in range [-255, 255]. 1026 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1027 if (!CE) return false; 1028 int64_t Val = CE->getValue(); 1029 // Special case, #-0 is INT32_MIN. 1030 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1031 } 1032 bool isAddrMode5() const { 1033 // If we have an immediate that's not a constant, treat it as a label 1034 // reference needing a fixup. If it is a constant, it's something else 1035 // and we reject it. 1036 if (isImm() && !isa<MCConstantExpr>(getImm())) 1037 return true; 1038 if (!isMem() || Memory.Alignment != 0) return false; 1039 // Check for register offset. 1040 if (Memory.OffsetRegNum) return false; 1041 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1042 if (!Memory.OffsetImm) return true; 1043 int64_t Val = Memory.OffsetImm->getValue(); 1044 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1045 Val == INT32_MIN; 1046 } 1047 bool isMemTBB() const { 1048 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1049 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1050 return false; 1051 return true; 1052 } 1053 bool isMemTBH() const { 1054 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1055 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1056 Memory.Alignment != 0 ) 1057 return false; 1058 return true; 1059 } 1060 bool isMemRegOffset() const { 1061 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1062 return false; 1063 return true; 1064 } 1065 bool isT2MemRegOffset() const { 1066 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1067 Memory.Alignment != 0) 1068 return false; 1069 // Only lsl #{0, 1, 2, 3} allowed. 1070 if (Memory.ShiftType == ARM_AM::no_shift) 1071 return true; 1072 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1073 return false; 1074 return true; 1075 } 1076 bool isMemThumbRR() const { 1077 // Thumb reg+reg addressing is simple. Just two registers, a base and 1078 // an offset. No shifts, negations or any other complicating factors. 1079 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1080 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1081 return false; 1082 return isARMLowRegister(Memory.BaseRegNum) && 1083 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1084 } 1085 bool isMemThumbRIs4() const { 1086 if (!isMem() || Memory.OffsetRegNum != 0 || 1087 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1088 return false; 1089 // Immediate offset, multiple of 4 in range [0, 124]. 1090 if (!Memory.OffsetImm) return true; 1091 int64_t Val = Memory.OffsetImm->getValue(); 1092 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1093 } 1094 bool isMemThumbRIs2() const { 1095 if (!isMem() || Memory.OffsetRegNum != 0 || 1096 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1097 return false; 1098 // Immediate offset, multiple of 4 in range [0, 62]. 1099 if (!Memory.OffsetImm) return true; 1100 int64_t Val = Memory.OffsetImm->getValue(); 1101 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1102 } 1103 bool isMemThumbRIs1() const { 1104 if (!isMem() || Memory.OffsetRegNum != 0 || 1105 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1106 return false; 1107 // Immediate offset in range [0, 31]. 1108 if (!Memory.OffsetImm) return true; 1109 int64_t Val = Memory.OffsetImm->getValue(); 1110 return Val >= 0 && Val <= 31; 1111 } 1112 bool isMemThumbSPI() const { 1113 if (!isMem() || Memory.OffsetRegNum != 0 || 1114 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1115 return false; 1116 // Immediate offset, multiple of 4 in range [0, 1020]. 1117 if (!Memory.OffsetImm) return true; 1118 int64_t Val = Memory.OffsetImm->getValue(); 1119 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1120 } 1121 bool isMemImm8s4Offset() const { 1122 // If we have an immediate that's not a constant, treat it as a label 1123 // reference needing a fixup. If it is a constant, it's something else 1124 // and we reject it. 1125 if (isImm() && !isa<MCConstantExpr>(getImm())) 1126 return true; 1127 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1128 return false; 1129 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1130 if (!Memory.OffsetImm) return true; 1131 int64_t Val = Memory.OffsetImm->getValue(); 1132 // Special case, #-0 is INT32_MIN. 1133 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1134 } 1135 bool isMemImm0_1020s4Offset() const { 1136 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1137 return false; 1138 // Immediate offset a multiple of 4 in range [0, 1020]. 1139 if (!Memory.OffsetImm) return true; 1140 int64_t Val = Memory.OffsetImm->getValue(); 1141 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1142 } 1143 bool isMemImm8Offset() const { 1144 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1145 return false; 1146 // Base reg of PC isn't allowed for these encodings. 1147 if (Memory.BaseRegNum == ARM::PC) return false; 1148 // Immediate offset in range [-255, 255]. 1149 if (!Memory.OffsetImm) return true; 1150 int64_t Val = Memory.OffsetImm->getValue(); 1151 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1152 } 1153 bool isMemPosImm8Offset() const { 1154 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1155 return false; 1156 // Immediate offset in range [0, 255]. 1157 if (!Memory.OffsetImm) return true; 1158 int64_t Val = Memory.OffsetImm->getValue(); 1159 return Val >= 0 && Val < 256; 1160 } 1161 bool isMemNegImm8Offset() const { 1162 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1163 return false; 1164 // Base reg of PC isn't allowed for these encodings. 1165 if (Memory.BaseRegNum == ARM::PC) return false; 1166 // Immediate offset in range [-255, -1]. 1167 if (!Memory.OffsetImm) return false; 1168 int64_t Val = Memory.OffsetImm->getValue(); 1169 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1170 } 1171 bool isMemUImm12Offset() const { 1172 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1173 return false; 1174 // Immediate offset in range [0, 4095]. 1175 if (!Memory.OffsetImm) return true; 1176 int64_t Val = Memory.OffsetImm->getValue(); 1177 return (Val >= 0 && Val < 4096); 1178 } 1179 bool isMemImm12Offset() const { 1180 // If we have an immediate that's not a constant, treat it as a label 1181 // reference needing a fixup. If it is a constant, it's something else 1182 // and we reject it. 1183 if (isImm() && !isa<MCConstantExpr>(getImm())) 1184 return true; 1185 1186 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1187 return false; 1188 // Immediate offset in range [-4095, 4095]. 1189 if (!Memory.OffsetImm) return true; 1190 int64_t Val = Memory.OffsetImm->getValue(); 1191 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1192 } 1193 bool isPostIdxImm8() const { 1194 if (!isImm()) return false; 1195 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1196 if (!CE) return false; 1197 int64_t Val = CE->getValue(); 1198 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1199 } 1200 bool isPostIdxImm8s4() const { 1201 if (!isImm()) return false; 1202 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1203 if (!CE) return false; 1204 int64_t Val = CE->getValue(); 1205 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1206 (Val == INT32_MIN); 1207 } 1208 1209 bool isMSRMask() const { return Kind == k_MSRMask; } 1210 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1211 1212 // NEON operands. 1213 bool isSingleSpacedVectorList() const { 1214 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1215 } 1216 bool isDoubleSpacedVectorList() const { 1217 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1218 } 1219 bool isVecListOneD() const { 1220 if (!isSingleSpacedVectorList()) return false; 1221 return VectorList.Count == 1; 1222 } 1223 1224 bool isVecListDPair() const { 1225 if (!isSingleSpacedVectorList()) return false; 1226 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1227 .contains(VectorList.RegNum)); 1228 } 1229 1230 bool isVecListThreeD() const { 1231 if (!isSingleSpacedVectorList()) return false; 1232 return VectorList.Count == 3; 1233 } 1234 1235 bool isVecListFourD() const { 1236 if (!isSingleSpacedVectorList()) return false; 1237 return VectorList.Count == 4; 1238 } 1239 1240 bool isVecListDPairSpaced() const { 1241 if (isSingleSpacedVectorList()) return false; 1242 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1243 .contains(VectorList.RegNum)); 1244 } 1245 1246 bool isVecListThreeQ() const { 1247 if (!isDoubleSpacedVectorList()) return false; 1248 return VectorList.Count == 3; 1249 } 1250 1251 bool isVecListFourQ() const { 1252 if (!isDoubleSpacedVectorList()) return false; 1253 return VectorList.Count == 4; 1254 } 1255 1256 bool isSingleSpacedVectorAllLanes() const { 1257 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1258 } 1259 bool isDoubleSpacedVectorAllLanes() const { 1260 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1261 } 1262 bool isVecListOneDAllLanes() const { 1263 if (!isSingleSpacedVectorAllLanes()) return false; 1264 return VectorList.Count == 1; 1265 } 1266 1267 bool isVecListDPairAllLanes() const { 1268 if (!isSingleSpacedVectorAllLanes()) return false; 1269 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1270 .contains(VectorList.RegNum)); 1271 } 1272 1273 bool isVecListDPairSpacedAllLanes() const { 1274 if (!isDoubleSpacedVectorAllLanes()) return false; 1275 return VectorList.Count == 2; 1276 } 1277 1278 bool isVecListThreeDAllLanes() const { 1279 if (!isSingleSpacedVectorAllLanes()) return false; 1280 return VectorList.Count == 3; 1281 } 1282 1283 bool isVecListThreeQAllLanes() const { 1284 if (!isDoubleSpacedVectorAllLanes()) return false; 1285 return VectorList.Count == 3; 1286 } 1287 1288 bool isVecListFourDAllLanes() const { 1289 if (!isSingleSpacedVectorAllLanes()) return false; 1290 return VectorList.Count == 4; 1291 } 1292 1293 bool isVecListFourQAllLanes() const { 1294 if (!isDoubleSpacedVectorAllLanes()) return false; 1295 return VectorList.Count == 4; 1296 } 1297 1298 bool isSingleSpacedVectorIndexed() const { 1299 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1300 } 1301 bool isDoubleSpacedVectorIndexed() const { 1302 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1303 } 1304 bool isVecListOneDByteIndexed() const { 1305 if (!isSingleSpacedVectorIndexed()) return false; 1306 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1307 } 1308 1309 bool isVecListOneDHWordIndexed() const { 1310 if (!isSingleSpacedVectorIndexed()) return false; 1311 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1312 } 1313 1314 bool isVecListOneDWordIndexed() const { 1315 if (!isSingleSpacedVectorIndexed()) return false; 1316 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1317 } 1318 1319 bool isVecListTwoDByteIndexed() const { 1320 if (!isSingleSpacedVectorIndexed()) return false; 1321 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1322 } 1323 1324 bool isVecListTwoDHWordIndexed() const { 1325 if (!isSingleSpacedVectorIndexed()) return false; 1326 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1327 } 1328 1329 bool isVecListTwoQWordIndexed() const { 1330 if (!isDoubleSpacedVectorIndexed()) return false; 1331 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1332 } 1333 1334 bool isVecListTwoQHWordIndexed() const { 1335 if (!isDoubleSpacedVectorIndexed()) return false; 1336 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1337 } 1338 1339 bool isVecListTwoDWordIndexed() const { 1340 if (!isSingleSpacedVectorIndexed()) return false; 1341 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1342 } 1343 1344 bool isVecListThreeDByteIndexed() const { 1345 if (!isSingleSpacedVectorIndexed()) return false; 1346 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1347 } 1348 1349 bool isVecListThreeDHWordIndexed() const { 1350 if (!isSingleSpacedVectorIndexed()) return false; 1351 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1352 } 1353 1354 bool isVecListThreeQWordIndexed() const { 1355 if (!isDoubleSpacedVectorIndexed()) return false; 1356 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1357 } 1358 1359 bool isVecListThreeQHWordIndexed() const { 1360 if (!isDoubleSpacedVectorIndexed()) return false; 1361 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1362 } 1363 1364 bool isVecListThreeDWordIndexed() const { 1365 if (!isSingleSpacedVectorIndexed()) return false; 1366 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1367 } 1368 1369 bool isVecListFourDByteIndexed() const { 1370 if (!isSingleSpacedVectorIndexed()) return false; 1371 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1372 } 1373 1374 bool isVecListFourDHWordIndexed() const { 1375 if (!isSingleSpacedVectorIndexed()) return false; 1376 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1377 } 1378 1379 bool isVecListFourQWordIndexed() const { 1380 if (!isDoubleSpacedVectorIndexed()) return false; 1381 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1382 } 1383 1384 bool isVecListFourQHWordIndexed() const { 1385 if (!isDoubleSpacedVectorIndexed()) return false; 1386 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1387 } 1388 1389 bool isVecListFourDWordIndexed() const { 1390 if (!isSingleSpacedVectorIndexed()) return false; 1391 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1392 } 1393 1394 bool isVectorIndex8() const { 1395 if (Kind != k_VectorIndex) return false; 1396 return VectorIndex.Val < 8; 1397 } 1398 bool isVectorIndex16() const { 1399 if (Kind != k_VectorIndex) return false; 1400 return VectorIndex.Val < 4; 1401 } 1402 bool isVectorIndex32() const { 1403 if (Kind != k_VectorIndex) return false; 1404 return VectorIndex.Val < 2; 1405 } 1406 1407 bool isNEONi8splat() const { 1408 if (!isImm()) return false; 1409 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1410 // Must be a constant. 1411 if (!CE) return false; 1412 int64_t Value = CE->getValue(); 1413 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1414 // value. 1415 return Value >= 0 && Value < 256; 1416 } 1417 1418 bool isNEONi16splat() const { 1419 if (!isImm()) return false; 1420 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1421 // Must be a constant. 1422 if (!CE) return false; 1423 int64_t Value = CE->getValue(); 1424 // i16 value in the range [0,255] or [0x0100, 0xff00] 1425 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1426 } 1427 1428 bool isNEONi32splat() const { 1429 if (!isImm()) return false; 1430 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1431 // Must be a constant. 1432 if (!CE) return false; 1433 int64_t Value = CE->getValue(); 1434 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1435 return (Value >= 0 && Value < 256) || 1436 (Value >= 0x0100 && Value <= 0xff00) || 1437 (Value >= 0x010000 && Value <= 0xff0000) || 1438 (Value >= 0x01000000 && Value <= 0xff000000); 1439 } 1440 1441 bool isNEONi32vmov() const { 1442 if (!isImm()) return false; 1443 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1444 // Must be a constant. 1445 if (!CE) return false; 1446 int64_t Value = CE->getValue(); 1447 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1448 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1449 return (Value >= 0 && Value < 256) || 1450 (Value >= 0x0100 && Value <= 0xff00) || 1451 (Value >= 0x010000 && Value <= 0xff0000) || 1452 (Value >= 0x01000000 && Value <= 0xff000000) || 1453 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1454 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1455 } 1456 bool isNEONi32vmovNeg() const { 1457 if (!isImm()) return false; 1458 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1459 // Must be a constant. 1460 if (!CE) return false; 1461 int64_t Value = ~CE->getValue(); 1462 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1463 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1464 return (Value >= 0 && Value < 256) || 1465 (Value >= 0x0100 && Value <= 0xff00) || 1466 (Value >= 0x010000 && Value <= 0xff0000) || 1467 (Value >= 0x01000000 && Value <= 0xff000000) || 1468 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1469 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1470 } 1471 1472 bool isNEONi64splat() const { 1473 if (!isImm()) return false; 1474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1475 // Must be a constant. 1476 if (!CE) return false; 1477 uint64_t Value = CE->getValue(); 1478 // i64 value with each byte being either 0 or 0xff. 1479 for (unsigned i = 0; i < 8; ++i) 1480 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1481 return true; 1482 } 1483 1484 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1485 // Add as immediates when possible. Null MCExpr = 0. 1486 if (Expr == 0) 1487 Inst.addOperand(MCOperand::CreateImm(0)); 1488 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1489 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1490 else 1491 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1492 } 1493 1494 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1495 assert(N == 2 && "Invalid number of operands!"); 1496 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1497 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1498 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1499 } 1500 1501 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1502 assert(N == 1 && "Invalid number of operands!"); 1503 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1504 } 1505 1506 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1507 assert(N == 1 && "Invalid number of operands!"); 1508 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1509 } 1510 1511 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1512 assert(N == 1 && "Invalid number of operands!"); 1513 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1514 } 1515 1516 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1517 assert(N == 1 && "Invalid number of operands!"); 1518 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1519 } 1520 1521 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1522 assert(N == 1 && "Invalid number of operands!"); 1523 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1524 } 1525 1526 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1527 assert(N == 1 && "Invalid number of operands!"); 1528 Inst.addOperand(MCOperand::CreateReg(getReg())); 1529 } 1530 1531 void addRegOperands(MCInst &Inst, unsigned N) const { 1532 assert(N == 1 && "Invalid number of operands!"); 1533 Inst.addOperand(MCOperand::CreateReg(getReg())); 1534 } 1535 1536 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1537 assert(N == 3 && "Invalid number of operands!"); 1538 assert(isRegShiftedReg() && 1539 "addRegShiftedRegOperands() on non RegShiftedReg!"); 1540 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1541 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1542 Inst.addOperand(MCOperand::CreateImm( 1543 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1544 } 1545 1546 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1547 assert(N == 2 && "Invalid number of operands!"); 1548 assert(isRegShiftedImm() && 1549 "addRegShiftedImmOperands() on non RegShiftedImm!"); 1550 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1551 // Shift of #32 is encoded as 0 where permitted 1552 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1553 Inst.addOperand(MCOperand::CreateImm( 1554 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1555 } 1556 1557 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1558 assert(N == 1 && "Invalid number of operands!"); 1559 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1560 ShifterImm.Imm)); 1561 } 1562 1563 void addRegListOperands(MCInst &Inst, unsigned N) const { 1564 assert(N == 1 && "Invalid number of operands!"); 1565 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1566 for (SmallVectorImpl<unsigned>::const_iterator 1567 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1568 Inst.addOperand(MCOperand::CreateReg(*I)); 1569 } 1570 1571 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1572 addRegListOperands(Inst, N); 1573 } 1574 1575 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1576 addRegListOperands(Inst, N); 1577 } 1578 1579 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1580 assert(N == 1 && "Invalid number of operands!"); 1581 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1582 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1583 } 1584 1585 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1586 assert(N == 1 && "Invalid number of operands!"); 1587 // Munge the lsb/width into a bitfield mask. 1588 unsigned lsb = Bitfield.LSB; 1589 unsigned width = Bitfield.Width; 1590 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1591 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1592 (32 - (lsb + width))); 1593 Inst.addOperand(MCOperand::CreateImm(Mask)); 1594 } 1595 1596 void addImmOperands(MCInst &Inst, unsigned N) const { 1597 assert(N == 1 && "Invalid number of operands!"); 1598 addExpr(Inst, getImm()); 1599 } 1600 1601 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1602 assert(N == 1 && "Invalid number of operands!"); 1603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1604 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1605 } 1606 1607 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1608 assert(N == 1 && "Invalid number of operands!"); 1609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1610 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1611 } 1612 1613 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1614 assert(N == 1 && "Invalid number of operands!"); 1615 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1616 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1617 Inst.addOperand(MCOperand::CreateImm(Val)); 1618 } 1619 1620 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1621 assert(N == 1 && "Invalid number of operands!"); 1622 // FIXME: We really want to scale the value here, but the LDRD/STRD 1623 // instruction don't encode operands that way yet. 1624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1625 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1626 } 1627 1628 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1629 assert(N == 1 && "Invalid number of operands!"); 1630 // The immediate is scaled by four in the encoding and is stored 1631 // in the MCInst as such. Lop off the low two bits here. 1632 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1633 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1634 } 1635 1636 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1637 assert(N == 1 && "Invalid number of operands!"); 1638 // The immediate is scaled by four in the encoding and is stored 1639 // in the MCInst as such. Lop off the low two bits here. 1640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1641 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1642 } 1643 1644 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1645 assert(N == 1 && "Invalid number of operands!"); 1646 // The immediate is scaled by four in the encoding and is stored 1647 // in the MCInst as such. Lop off the low two bits here. 1648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1649 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1650 } 1651 1652 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1653 assert(N == 1 && "Invalid number of operands!"); 1654 // The constant encodes as the immediate-1, and we store in the instruction 1655 // the bits as encoded, so subtract off one here. 1656 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1657 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1658 } 1659 1660 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1661 assert(N == 1 && "Invalid number of operands!"); 1662 // The constant encodes as the immediate-1, and we store in the instruction 1663 // the bits as encoded, so subtract off one here. 1664 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1665 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1666 } 1667 1668 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1669 assert(N == 1 && "Invalid number of operands!"); 1670 // The constant encodes as the immediate, except for 32, which encodes as 1671 // zero. 1672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1673 unsigned Imm = CE->getValue(); 1674 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1675 } 1676 1677 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1678 assert(N == 1 && "Invalid number of operands!"); 1679 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1680 // the instruction as well. 1681 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1682 int Val = CE->getValue(); 1683 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1684 } 1685 1686 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1687 assert(N == 1 && "Invalid number of operands!"); 1688 // The operand is actually a t2_so_imm, but we have its bitwise 1689 // negation in the assembly source, so twiddle it here. 1690 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1691 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1692 } 1693 1694 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1695 assert(N == 1 && "Invalid number of operands!"); 1696 // The operand is actually a t2_so_imm, but we have its 1697 // negation in the assembly source, so twiddle it here. 1698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1699 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1700 } 1701 1702 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1703 assert(N == 1 && "Invalid number of operands!"); 1704 // The operand is actually an imm0_4095, but we have its 1705 // negation in the assembly source, so twiddle it here. 1706 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1707 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1708 } 1709 1710 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1711 assert(N == 1 && "Invalid number of operands!"); 1712 // The operand is actually a so_imm, but we have its bitwise 1713 // negation in the assembly source, so twiddle it here. 1714 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1715 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1716 } 1717 1718 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1719 assert(N == 1 && "Invalid number of operands!"); 1720 // The operand is actually a so_imm, but we have its 1721 // negation in the assembly source, so twiddle it here. 1722 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1723 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1724 } 1725 1726 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1727 assert(N == 1 && "Invalid number of operands!"); 1728 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1729 } 1730 1731 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 1732 assert(N == 1 && "Invalid number of operands!"); 1733 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); 1734 } 1735 1736 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1737 assert(N == 1 && "Invalid number of operands!"); 1738 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1739 } 1740 1741 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1742 assert(N == 1 && "Invalid number of operands!"); 1743 int32_t Imm = Memory.OffsetImm->getValue(); 1744 // FIXME: Handle #-0 1745 if (Imm == INT32_MIN) Imm = 0; 1746 Inst.addOperand(MCOperand::CreateImm(Imm)); 1747 } 1748 1749 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1750 assert(N == 1 && "Invalid number of operands!"); 1751 assert(isImm() && "Not an immediate!"); 1752 1753 // If we have an immediate that's not a constant, treat it as a label 1754 // reference needing a fixup. 1755 if (!isa<MCConstantExpr>(getImm())) { 1756 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1757 return; 1758 } 1759 1760 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1761 int Val = CE->getValue(); 1762 Inst.addOperand(MCOperand::CreateImm(Val)); 1763 } 1764 1765 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1766 assert(N == 2 && "Invalid number of operands!"); 1767 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1768 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1769 } 1770 1771 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1772 assert(N == 3 && "Invalid number of operands!"); 1773 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1774 if (!Memory.OffsetRegNum) { 1775 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1776 // Special case for #-0 1777 if (Val == INT32_MIN) Val = 0; 1778 if (Val < 0) Val = -Val; 1779 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1780 } else { 1781 // For register offset, we encode the shift type and negation flag 1782 // here. 1783 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1784 Memory.ShiftImm, Memory.ShiftType); 1785 } 1786 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1787 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1788 Inst.addOperand(MCOperand::CreateImm(Val)); 1789 } 1790 1791 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1792 assert(N == 2 && "Invalid number of operands!"); 1793 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1794 assert(CE && "non-constant AM2OffsetImm operand!"); 1795 int32_t Val = CE->getValue(); 1796 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1797 // Special case for #-0 1798 if (Val == INT32_MIN) Val = 0; 1799 if (Val < 0) Val = -Val; 1800 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1801 Inst.addOperand(MCOperand::CreateReg(0)); 1802 Inst.addOperand(MCOperand::CreateImm(Val)); 1803 } 1804 1805 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1806 assert(N == 3 && "Invalid number of operands!"); 1807 // If we have an immediate that's not a constant, treat it as a label 1808 // reference needing a fixup. If it is a constant, it's something else 1809 // and we reject it. 1810 if (isImm()) { 1811 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1812 Inst.addOperand(MCOperand::CreateReg(0)); 1813 Inst.addOperand(MCOperand::CreateImm(0)); 1814 return; 1815 } 1816 1817 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1818 if (!Memory.OffsetRegNum) { 1819 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1820 // Special case for #-0 1821 if (Val == INT32_MIN) Val = 0; 1822 if (Val < 0) Val = -Val; 1823 Val = ARM_AM::getAM3Opc(AddSub, Val); 1824 } else { 1825 // For register offset, we encode the shift type and negation flag 1826 // here. 1827 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1828 } 1829 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1830 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1831 Inst.addOperand(MCOperand::CreateImm(Val)); 1832 } 1833 1834 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1835 assert(N == 2 && "Invalid number of operands!"); 1836 if (Kind == k_PostIndexRegister) { 1837 int32_t Val = 1838 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1839 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1840 Inst.addOperand(MCOperand::CreateImm(Val)); 1841 return; 1842 } 1843 1844 // Constant offset. 1845 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1846 int32_t Val = CE->getValue(); 1847 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1848 // Special case for #-0 1849 if (Val == INT32_MIN) Val = 0; 1850 if (Val < 0) Val = -Val; 1851 Val = ARM_AM::getAM3Opc(AddSub, Val); 1852 Inst.addOperand(MCOperand::CreateReg(0)); 1853 Inst.addOperand(MCOperand::CreateImm(Val)); 1854 } 1855 1856 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1857 assert(N == 2 && "Invalid number of operands!"); 1858 // If we have an immediate that's not a constant, treat it as a label 1859 // reference needing a fixup. If it is a constant, it's something else 1860 // and we reject it. 1861 if (isImm()) { 1862 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1863 Inst.addOperand(MCOperand::CreateImm(0)); 1864 return; 1865 } 1866 1867 // The lower two bits are always zero and as such are not encoded. 1868 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1869 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1870 // Special case for #-0 1871 if (Val == INT32_MIN) Val = 0; 1872 if (Val < 0) Val = -Val; 1873 Val = ARM_AM::getAM5Opc(AddSub, Val); 1874 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1875 Inst.addOperand(MCOperand::CreateImm(Val)); 1876 } 1877 1878 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1879 assert(N == 2 && "Invalid number of operands!"); 1880 // If we have an immediate that's not a constant, treat it as a label 1881 // reference needing a fixup. If it is a constant, it's something else 1882 // and we reject it. 1883 if (isImm()) { 1884 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1885 Inst.addOperand(MCOperand::CreateImm(0)); 1886 return; 1887 } 1888 1889 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1890 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1891 Inst.addOperand(MCOperand::CreateImm(Val)); 1892 } 1893 1894 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1895 assert(N == 2 && "Invalid number of operands!"); 1896 // The lower two bits are always zero and as such are not encoded. 1897 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1898 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1899 Inst.addOperand(MCOperand::CreateImm(Val)); 1900 } 1901 1902 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1903 assert(N == 2 && "Invalid number of operands!"); 1904 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1905 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1906 Inst.addOperand(MCOperand::CreateImm(Val)); 1907 } 1908 1909 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1910 addMemImm8OffsetOperands(Inst, N); 1911 } 1912 1913 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1914 addMemImm8OffsetOperands(Inst, N); 1915 } 1916 1917 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1918 assert(N == 2 && "Invalid number of operands!"); 1919 // If this is an immediate, it's a label reference. 1920 if (isImm()) { 1921 addExpr(Inst, getImm()); 1922 Inst.addOperand(MCOperand::CreateImm(0)); 1923 return; 1924 } 1925 1926 // Otherwise, it's a normal memory reg+offset. 1927 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1928 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1929 Inst.addOperand(MCOperand::CreateImm(Val)); 1930 } 1931 1932 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1933 assert(N == 2 && "Invalid number of operands!"); 1934 // If this is an immediate, it's a label reference. 1935 if (isImm()) { 1936 addExpr(Inst, getImm()); 1937 Inst.addOperand(MCOperand::CreateImm(0)); 1938 return; 1939 } 1940 1941 // Otherwise, it's a normal memory reg+offset. 1942 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1943 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1944 Inst.addOperand(MCOperand::CreateImm(Val)); 1945 } 1946 1947 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 1948 assert(N == 2 && "Invalid number of operands!"); 1949 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1950 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1951 } 1952 1953 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 1954 assert(N == 2 && "Invalid number of operands!"); 1955 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1956 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1957 } 1958 1959 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1960 assert(N == 3 && "Invalid number of operands!"); 1961 unsigned Val = 1962 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1963 Memory.ShiftImm, Memory.ShiftType); 1964 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1965 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1966 Inst.addOperand(MCOperand::CreateImm(Val)); 1967 } 1968 1969 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1970 assert(N == 3 && "Invalid number of operands!"); 1971 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1972 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1973 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1974 } 1975 1976 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1977 assert(N == 2 && "Invalid number of operands!"); 1978 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1979 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1980 } 1981 1982 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1983 assert(N == 2 && "Invalid number of operands!"); 1984 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1985 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1986 Inst.addOperand(MCOperand::CreateImm(Val)); 1987 } 1988 1989 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1990 assert(N == 2 && "Invalid number of operands!"); 1991 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1992 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1993 Inst.addOperand(MCOperand::CreateImm(Val)); 1994 } 1995 1996 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1997 assert(N == 2 && "Invalid number of operands!"); 1998 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1999 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2000 Inst.addOperand(MCOperand::CreateImm(Val)); 2001 } 2002 2003 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2004 assert(N == 2 && "Invalid number of operands!"); 2005 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2006 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2007 Inst.addOperand(MCOperand::CreateImm(Val)); 2008 } 2009 2010 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2011 assert(N == 1 && "Invalid number of operands!"); 2012 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2013 assert(CE && "non-constant post-idx-imm8 operand!"); 2014 int Imm = CE->getValue(); 2015 bool isAdd = Imm >= 0; 2016 if (Imm == INT32_MIN) Imm = 0; 2017 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2018 Inst.addOperand(MCOperand::CreateImm(Imm)); 2019 } 2020 2021 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2022 assert(N == 1 && "Invalid number of operands!"); 2023 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2024 assert(CE && "non-constant post-idx-imm8s4 operand!"); 2025 int Imm = CE->getValue(); 2026 bool isAdd = Imm >= 0; 2027 if (Imm == INT32_MIN) Imm = 0; 2028 // Immediate is scaled by 4. 2029 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2030 Inst.addOperand(MCOperand::CreateImm(Imm)); 2031 } 2032 2033 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2034 assert(N == 2 && "Invalid number of operands!"); 2035 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2036 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 2037 } 2038 2039 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2040 assert(N == 2 && "Invalid number of operands!"); 2041 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2042 // The sign, shift type, and shift amount are encoded in a single operand 2043 // using the AM2 encoding helpers. 2044 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2045 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2046 PostIdxReg.ShiftTy); 2047 Inst.addOperand(MCOperand::CreateImm(Imm)); 2048 } 2049 2050 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2051 assert(N == 1 && "Invalid number of operands!"); 2052 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 2053 } 2054 2055 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2056 assert(N == 1 && "Invalid number of operands!"); 2057 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 2058 } 2059 2060 void addVecListOperands(MCInst &Inst, unsigned N) const { 2061 assert(N == 1 && "Invalid number of operands!"); 2062 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2063 } 2064 2065 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2066 assert(N == 2 && "Invalid number of operands!"); 2067 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2068 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 2069 } 2070 2071 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2072 assert(N == 1 && "Invalid number of operands!"); 2073 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2074 } 2075 2076 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2077 assert(N == 1 && "Invalid number of operands!"); 2078 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2079 } 2080 2081 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2082 assert(N == 1 && "Invalid number of operands!"); 2083 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2084 } 2085 2086 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2087 assert(N == 1 && "Invalid number of operands!"); 2088 // The immediate encodes the type of constant as well as the value. 2089 // Mask in that this is an i8 splat. 2090 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2091 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 2092 } 2093 2094 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2095 assert(N == 1 && "Invalid number of operands!"); 2096 // The immediate encodes the type of constant as well as the value. 2097 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2098 unsigned Value = CE->getValue(); 2099 if (Value >= 256) 2100 Value = (Value >> 8) | 0xa00; 2101 else 2102 Value |= 0x800; 2103 Inst.addOperand(MCOperand::CreateImm(Value)); 2104 } 2105 2106 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2107 assert(N == 1 && "Invalid number of operands!"); 2108 // The immediate encodes the type of constant as well as the value. 2109 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2110 unsigned Value = CE->getValue(); 2111 if (Value >= 256 && Value <= 0xff00) 2112 Value = (Value >> 8) | 0x200; 2113 else if (Value > 0xffff && Value <= 0xff0000) 2114 Value = (Value >> 16) | 0x400; 2115 else if (Value > 0xffffff) 2116 Value = (Value >> 24) | 0x600; 2117 Inst.addOperand(MCOperand::CreateImm(Value)); 2118 } 2119 2120 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2121 assert(N == 1 && "Invalid number of operands!"); 2122 // The immediate encodes the type of constant as well as the value. 2123 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2124 unsigned Value = CE->getValue(); 2125 if (Value >= 256 && Value <= 0xffff) 2126 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2127 else if (Value > 0xffff && Value <= 0xffffff) 2128 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2129 else if (Value > 0xffffff) 2130 Value = (Value >> 24) | 0x600; 2131 Inst.addOperand(MCOperand::CreateImm(Value)); 2132 } 2133 2134 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2135 assert(N == 1 && "Invalid number of operands!"); 2136 // The immediate encodes the type of constant as well as the value. 2137 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2138 unsigned Value = ~CE->getValue(); 2139 if (Value >= 256 && Value <= 0xffff) 2140 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2141 else if (Value > 0xffff && Value <= 0xffffff) 2142 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2143 else if (Value > 0xffffff) 2144 Value = (Value >> 24) | 0x600; 2145 Inst.addOperand(MCOperand::CreateImm(Value)); 2146 } 2147 2148 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2149 assert(N == 1 && "Invalid number of operands!"); 2150 // The immediate encodes the type of constant as well as the value. 2151 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2152 uint64_t Value = CE->getValue(); 2153 unsigned Imm = 0; 2154 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2155 Imm |= (Value & 1) << i; 2156 } 2157 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2158 } 2159 2160 virtual void print(raw_ostream &OS) const; 2161 2162 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2163 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2164 Op->ITMask.Mask = Mask; 2165 Op->StartLoc = S; 2166 Op->EndLoc = S; 2167 return Op; 2168 } 2169 2170 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2171 ARMOperand *Op = new ARMOperand(k_CondCode); 2172 Op->CC.Val = CC; 2173 Op->StartLoc = S; 2174 Op->EndLoc = S; 2175 return Op; 2176 } 2177 2178 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2179 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2180 Op->Cop.Val = CopVal; 2181 Op->StartLoc = S; 2182 Op->EndLoc = S; 2183 return Op; 2184 } 2185 2186 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2187 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2188 Op->Cop.Val = CopVal; 2189 Op->StartLoc = S; 2190 Op->EndLoc = S; 2191 return Op; 2192 } 2193 2194 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2195 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2196 Op->Cop.Val = Val; 2197 Op->StartLoc = S; 2198 Op->EndLoc = E; 2199 return Op; 2200 } 2201 2202 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2203 ARMOperand *Op = new ARMOperand(k_CCOut); 2204 Op->Reg.RegNum = RegNum; 2205 Op->StartLoc = S; 2206 Op->EndLoc = S; 2207 return Op; 2208 } 2209 2210 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2211 ARMOperand *Op = new ARMOperand(k_Token); 2212 Op->Tok.Data = Str.data(); 2213 Op->Tok.Length = Str.size(); 2214 Op->StartLoc = S; 2215 Op->EndLoc = S; 2216 return Op; 2217 } 2218 2219 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2220 ARMOperand *Op = new ARMOperand(k_Register); 2221 Op->Reg.RegNum = RegNum; 2222 Op->StartLoc = S; 2223 Op->EndLoc = E; 2224 return Op; 2225 } 2226 2227 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2228 unsigned SrcReg, 2229 unsigned ShiftReg, 2230 unsigned ShiftImm, 2231 SMLoc S, SMLoc E) { 2232 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2233 Op->RegShiftedReg.ShiftTy = ShTy; 2234 Op->RegShiftedReg.SrcReg = SrcReg; 2235 Op->RegShiftedReg.ShiftReg = ShiftReg; 2236 Op->RegShiftedReg.ShiftImm = ShiftImm; 2237 Op->StartLoc = S; 2238 Op->EndLoc = E; 2239 return Op; 2240 } 2241 2242 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2243 unsigned SrcReg, 2244 unsigned ShiftImm, 2245 SMLoc S, SMLoc E) { 2246 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2247 Op->RegShiftedImm.ShiftTy = ShTy; 2248 Op->RegShiftedImm.SrcReg = SrcReg; 2249 Op->RegShiftedImm.ShiftImm = ShiftImm; 2250 Op->StartLoc = S; 2251 Op->EndLoc = E; 2252 return Op; 2253 } 2254 2255 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2256 SMLoc S, SMLoc E) { 2257 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2258 Op->ShifterImm.isASR = isASR; 2259 Op->ShifterImm.Imm = Imm; 2260 Op->StartLoc = S; 2261 Op->EndLoc = E; 2262 return Op; 2263 } 2264 2265 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2266 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2267 Op->RotImm.Imm = Imm; 2268 Op->StartLoc = S; 2269 Op->EndLoc = E; 2270 return Op; 2271 } 2272 2273 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2274 SMLoc S, SMLoc E) { 2275 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2276 Op->Bitfield.LSB = LSB; 2277 Op->Bitfield.Width = Width; 2278 Op->StartLoc = S; 2279 Op->EndLoc = E; 2280 return Op; 2281 } 2282 2283 static ARMOperand * 2284 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2285 SMLoc StartLoc, SMLoc EndLoc) { 2286 KindTy Kind = k_RegisterList; 2287 2288 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 2289 Kind = k_DPRRegisterList; 2290 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2291 contains(Regs.front().first)) 2292 Kind = k_SPRRegisterList; 2293 2294 ARMOperand *Op = new ARMOperand(Kind); 2295 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 2296 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2297 Op->Registers.push_back(I->first); 2298 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2299 Op->StartLoc = StartLoc; 2300 Op->EndLoc = EndLoc; 2301 return Op; 2302 } 2303 2304 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2305 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2306 ARMOperand *Op = new ARMOperand(k_VectorList); 2307 Op->VectorList.RegNum = RegNum; 2308 Op->VectorList.Count = Count; 2309 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2310 Op->StartLoc = S; 2311 Op->EndLoc = E; 2312 return Op; 2313 } 2314 2315 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2316 bool isDoubleSpaced, 2317 SMLoc S, SMLoc E) { 2318 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2319 Op->VectorList.RegNum = RegNum; 2320 Op->VectorList.Count = Count; 2321 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2322 Op->StartLoc = S; 2323 Op->EndLoc = E; 2324 return Op; 2325 } 2326 2327 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2328 unsigned Index, 2329 bool isDoubleSpaced, 2330 SMLoc S, SMLoc E) { 2331 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2332 Op->VectorList.RegNum = RegNum; 2333 Op->VectorList.Count = Count; 2334 Op->VectorList.LaneIndex = Index; 2335 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2336 Op->StartLoc = S; 2337 Op->EndLoc = E; 2338 return Op; 2339 } 2340 2341 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2342 MCContext &Ctx) { 2343 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2344 Op->VectorIndex.Val = Idx; 2345 Op->StartLoc = S; 2346 Op->EndLoc = E; 2347 return Op; 2348 } 2349 2350 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2351 ARMOperand *Op = new ARMOperand(k_Immediate); 2352 Op->Imm.Val = Val; 2353 Op->StartLoc = S; 2354 Op->EndLoc = E; 2355 return Op; 2356 } 2357 2358 static ARMOperand *CreateMem(unsigned BaseRegNum, 2359 const MCConstantExpr *OffsetImm, 2360 unsigned OffsetRegNum, 2361 ARM_AM::ShiftOpc ShiftType, 2362 unsigned ShiftImm, 2363 unsigned Alignment, 2364 bool isNegative, 2365 SMLoc S, SMLoc E) { 2366 ARMOperand *Op = new ARMOperand(k_Memory); 2367 Op->Memory.BaseRegNum = BaseRegNum; 2368 Op->Memory.OffsetImm = OffsetImm; 2369 Op->Memory.OffsetRegNum = OffsetRegNum; 2370 Op->Memory.ShiftType = ShiftType; 2371 Op->Memory.ShiftImm = ShiftImm; 2372 Op->Memory.Alignment = Alignment; 2373 Op->Memory.isNegative = isNegative; 2374 Op->StartLoc = S; 2375 Op->EndLoc = E; 2376 return Op; 2377 } 2378 2379 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2380 ARM_AM::ShiftOpc ShiftTy, 2381 unsigned ShiftImm, 2382 SMLoc S, SMLoc E) { 2383 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2384 Op->PostIdxReg.RegNum = RegNum; 2385 Op->PostIdxReg.isAdd = isAdd; 2386 Op->PostIdxReg.ShiftTy = ShiftTy; 2387 Op->PostIdxReg.ShiftImm = ShiftImm; 2388 Op->StartLoc = S; 2389 Op->EndLoc = E; 2390 return Op; 2391 } 2392 2393 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2394 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2395 Op->MBOpt.Val = Opt; 2396 Op->StartLoc = S; 2397 Op->EndLoc = S; 2398 return Op; 2399 } 2400 2401 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, 2402 SMLoc S) { 2403 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt); 2404 Op->ISBOpt.Val = Opt; 2405 Op->StartLoc = S; 2406 Op->EndLoc = S; 2407 return Op; 2408 } 2409 2410 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2411 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2412 Op->IFlags.Val = IFlags; 2413 Op->StartLoc = S; 2414 Op->EndLoc = S; 2415 return Op; 2416 } 2417 2418 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2419 ARMOperand *Op = new ARMOperand(k_MSRMask); 2420 Op->MMask.Val = MMask; 2421 Op->StartLoc = S; 2422 Op->EndLoc = S; 2423 return Op; 2424 } 2425 }; 2426 2427 } // end anonymous namespace. 2428 2429 void ARMOperand::print(raw_ostream &OS) const { 2430 switch (Kind) { 2431 case k_CondCode: 2432 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2433 break; 2434 case k_CCOut: 2435 OS << "<ccout " << getReg() << ">"; 2436 break; 2437 case k_ITCondMask: { 2438 static const char *const MaskStr[] = { 2439 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2440 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2441 }; 2442 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2443 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2444 break; 2445 } 2446 case k_CoprocNum: 2447 OS << "<coprocessor number: " << getCoproc() << ">"; 2448 break; 2449 case k_CoprocReg: 2450 OS << "<coprocessor register: " << getCoproc() << ">"; 2451 break; 2452 case k_CoprocOption: 2453 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2454 break; 2455 case k_MSRMask: 2456 OS << "<mask: " << getMSRMask() << ">"; 2457 break; 2458 case k_Immediate: 2459 getImm()->print(OS); 2460 break; 2461 case k_MemBarrierOpt: 2462 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2463 break; 2464 case k_InstSyncBarrierOpt: 2465 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2466 break; 2467 case k_Memory: 2468 OS << "<memory " 2469 << " base:" << Memory.BaseRegNum; 2470 OS << ">"; 2471 break; 2472 case k_PostIndexRegister: 2473 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2474 << PostIdxReg.RegNum; 2475 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2476 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2477 << PostIdxReg.ShiftImm; 2478 OS << ">"; 2479 break; 2480 case k_ProcIFlags: { 2481 OS << "<ARM_PROC::"; 2482 unsigned IFlags = getProcIFlags(); 2483 for (int i=2; i >= 0; --i) 2484 if (IFlags & (1 << i)) 2485 OS << ARM_PROC::IFlagsToString(1 << i); 2486 OS << ">"; 2487 break; 2488 } 2489 case k_Register: 2490 OS << "<register " << getReg() << ">"; 2491 break; 2492 case k_ShifterImmediate: 2493 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2494 << " #" << ShifterImm.Imm << ">"; 2495 break; 2496 case k_ShiftedRegister: 2497 OS << "<so_reg_reg " 2498 << RegShiftedReg.SrcReg << " " 2499 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2500 << " " << RegShiftedReg.ShiftReg << ">"; 2501 break; 2502 case k_ShiftedImmediate: 2503 OS << "<so_reg_imm " 2504 << RegShiftedImm.SrcReg << " " 2505 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2506 << " #" << RegShiftedImm.ShiftImm << ">"; 2507 break; 2508 case k_RotateImmediate: 2509 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2510 break; 2511 case k_BitfieldDescriptor: 2512 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2513 << ", width: " << Bitfield.Width << ">"; 2514 break; 2515 case k_RegisterList: 2516 case k_DPRRegisterList: 2517 case k_SPRRegisterList: { 2518 OS << "<register_list "; 2519 2520 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2521 for (SmallVectorImpl<unsigned>::const_iterator 2522 I = RegList.begin(), E = RegList.end(); I != E; ) { 2523 OS << *I; 2524 if (++I < E) OS << ", "; 2525 } 2526 2527 OS << ">"; 2528 break; 2529 } 2530 case k_VectorList: 2531 OS << "<vector_list " << VectorList.Count << " * " 2532 << VectorList.RegNum << ">"; 2533 break; 2534 case k_VectorListAllLanes: 2535 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2536 << VectorList.RegNum << ">"; 2537 break; 2538 case k_VectorListIndexed: 2539 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2540 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2541 break; 2542 case k_Token: 2543 OS << "'" << getToken() << "'"; 2544 break; 2545 case k_VectorIndex: 2546 OS << "<vectorindex " << getVectorIndex() << ">"; 2547 break; 2548 } 2549 } 2550 2551 /// @name Auto-generated Match Functions 2552 /// { 2553 2554 static unsigned MatchRegisterName(StringRef Name); 2555 2556 /// } 2557 2558 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2559 SMLoc &StartLoc, SMLoc &EndLoc) { 2560 StartLoc = Parser.getTok().getLoc(); 2561 EndLoc = Parser.getTok().getEndLoc(); 2562 RegNo = tryParseRegister(); 2563 2564 return (RegNo == (unsigned)-1); 2565 } 2566 2567 /// Try to parse a register name. The token must be an Identifier when called, 2568 /// and if it is a register name the token is eaten and the register number is 2569 /// returned. Otherwise return -1. 2570 /// 2571 int ARMAsmParser::tryParseRegister() { 2572 const AsmToken &Tok = Parser.getTok(); 2573 if (Tok.isNot(AsmToken::Identifier)) return -1; 2574 2575 std::string lowerCase = Tok.getString().lower(); 2576 unsigned RegNum = MatchRegisterName(lowerCase); 2577 if (!RegNum) { 2578 RegNum = StringSwitch<unsigned>(lowerCase) 2579 .Case("r13", ARM::SP) 2580 .Case("r14", ARM::LR) 2581 .Case("r15", ARM::PC) 2582 .Case("ip", ARM::R12) 2583 // Additional register name aliases for 'gas' compatibility. 2584 .Case("a1", ARM::R0) 2585 .Case("a2", ARM::R1) 2586 .Case("a3", ARM::R2) 2587 .Case("a4", ARM::R3) 2588 .Case("v1", ARM::R4) 2589 .Case("v2", ARM::R5) 2590 .Case("v3", ARM::R6) 2591 .Case("v4", ARM::R7) 2592 .Case("v5", ARM::R8) 2593 .Case("v6", ARM::R9) 2594 .Case("v7", ARM::R10) 2595 .Case("v8", ARM::R11) 2596 .Case("sb", ARM::R9) 2597 .Case("sl", ARM::R10) 2598 .Case("fp", ARM::R11) 2599 .Default(0); 2600 } 2601 if (!RegNum) { 2602 // Check for aliases registered via .req. Canonicalize to lower case. 2603 // That's more consistent since register names are case insensitive, and 2604 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2605 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2606 // If no match, return failure. 2607 if (Entry == RegisterReqs.end()) 2608 return -1; 2609 Parser.Lex(); // Eat identifier token. 2610 return Entry->getValue(); 2611 } 2612 2613 Parser.Lex(); // Eat identifier token. 2614 2615 return RegNum; 2616 } 2617 2618 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2619 // If a recoverable error occurs, return 1. If an irrecoverable error 2620 // occurs, return -1. An irrecoverable error is one where tokens have been 2621 // consumed in the process of trying to parse the shifter (i.e., when it is 2622 // indeed a shifter operand, but malformed). 2623 int ARMAsmParser::tryParseShiftRegister( 2624 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2625 SMLoc S = Parser.getTok().getLoc(); 2626 const AsmToken &Tok = Parser.getTok(); 2627 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2628 2629 std::string lowerCase = Tok.getString().lower(); 2630 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2631 .Case("asl", ARM_AM::lsl) 2632 .Case("lsl", ARM_AM::lsl) 2633 .Case("lsr", ARM_AM::lsr) 2634 .Case("asr", ARM_AM::asr) 2635 .Case("ror", ARM_AM::ror) 2636 .Case("rrx", ARM_AM::rrx) 2637 .Default(ARM_AM::no_shift); 2638 2639 if (ShiftTy == ARM_AM::no_shift) 2640 return 1; 2641 2642 Parser.Lex(); // Eat the operator. 2643 2644 // The source register for the shift has already been added to the 2645 // operand list, so we need to pop it off and combine it into the shifted 2646 // register operand instead. 2647 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2648 if (!PrevOp->isReg()) 2649 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2650 int SrcReg = PrevOp->getReg(); 2651 2652 SMLoc EndLoc; 2653 int64_t Imm = 0; 2654 int ShiftReg = 0; 2655 if (ShiftTy == ARM_AM::rrx) { 2656 // RRX Doesn't have an explicit shift amount. The encoder expects 2657 // the shift register to be the same as the source register. Seems odd, 2658 // but OK. 2659 ShiftReg = SrcReg; 2660 } else { 2661 // Figure out if this is shifted by a constant or a register (for non-RRX). 2662 if (Parser.getTok().is(AsmToken::Hash) || 2663 Parser.getTok().is(AsmToken::Dollar)) { 2664 Parser.Lex(); // Eat hash. 2665 SMLoc ImmLoc = Parser.getTok().getLoc(); 2666 const MCExpr *ShiftExpr = 0; 2667 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 2668 Error(ImmLoc, "invalid immediate shift value"); 2669 return -1; 2670 } 2671 // The expression must be evaluatable as an immediate. 2672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2673 if (!CE) { 2674 Error(ImmLoc, "invalid immediate shift value"); 2675 return -1; 2676 } 2677 // Range check the immediate. 2678 // lsl, ror: 0 <= imm <= 31 2679 // lsr, asr: 0 <= imm <= 32 2680 Imm = CE->getValue(); 2681 if (Imm < 0 || 2682 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2683 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2684 Error(ImmLoc, "immediate shift value out of range"); 2685 return -1; 2686 } 2687 // shift by zero is a nop. Always send it through as lsl. 2688 // ('as' compatibility) 2689 if (Imm == 0) 2690 ShiftTy = ARM_AM::lsl; 2691 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2692 SMLoc L = Parser.getTok().getLoc(); 2693 EndLoc = Parser.getTok().getEndLoc(); 2694 ShiftReg = tryParseRegister(); 2695 if (ShiftReg == -1) { 2696 Error (L, "expected immediate or register in shift operand"); 2697 return -1; 2698 } 2699 } else { 2700 Error (Parser.getTok().getLoc(), 2701 "expected immediate or register in shift operand"); 2702 return -1; 2703 } 2704 } 2705 2706 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2707 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2708 ShiftReg, Imm, 2709 S, EndLoc)); 2710 else 2711 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2712 S, EndLoc)); 2713 2714 return 0; 2715 } 2716 2717 2718 /// Try to parse a register name. The token must be an Identifier when called. 2719 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 2720 /// if there is a "writeback". 'true' if it's not a register. 2721 /// 2722 /// TODO this is likely to change to allow different register types and or to 2723 /// parse for a specific register type. 2724 bool ARMAsmParser:: 2725 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2726 const AsmToken &RegTok = Parser.getTok(); 2727 int RegNo = tryParseRegister(); 2728 if (RegNo == -1) 2729 return true; 2730 2731 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 2732 RegTok.getEndLoc())); 2733 2734 const AsmToken &ExclaimTok = Parser.getTok(); 2735 if (ExclaimTok.is(AsmToken::Exclaim)) { 2736 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2737 ExclaimTok.getLoc())); 2738 Parser.Lex(); // Eat exclaim token 2739 return false; 2740 } 2741 2742 // Also check for an index operand. This is only legal for vector registers, 2743 // but that'll get caught OK in operand matching, so we don't need to 2744 // explicitly filter everything else out here. 2745 if (Parser.getTok().is(AsmToken::LBrac)) { 2746 SMLoc SIdx = Parser.getTok().getLoc(); 2747 Parser.Lex(); // Eat left bracket token. 2748 2749 const MCExpr *ImmVal; 2750 if (getParser().parseExpression(ImmVal)) 2751 return true; 2752 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2753 if (!MCE) 2754 return TokError("immediate value expected for vector index"); 2755 2756 if (Parser.getTok().isNot(AsmToken::RBrac)) 2757 return Error(Parser.getTok().getLoc(), "']' expected"); 2758 2759 SMLoc E = Parser.getTok().getEndLoc(); 2760 Parser.Lex(); // Eat right bracket token. 2761 2762 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2763 SIdx, E, 2764 getContext())); 2765 } 2766 2767 return false; 2768 } 2769 2770 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 2771 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2772 /// "c5", ... 2773 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2774 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2775 // but efficient. 2776 switch (Name.size()) { 2777 default: return -1; 2778 case 2: 2779 if (Name[0] != CoprocOp) 2780 return -1; 2781 switch (Name[1]) { 2782 default: return -1; 2783 case '0': return 0; 2784 case '1': return 1; 2785 case '2': return 2; 2786 case '3': return 3; 2787 case '4': return 4; 2788 case '5': return 5; 2789 case '6': return 6; 2790 case '7': return 7; 2791 case '8': return 8; 2792 case '9': return 9; 2793 } 2794 case 3: 2795 if (Name[0] != CoprocOp || Name[1] != '1') 2796 return -1; 2797 switch (Name[2]) { 2798 default: return -1; 2799 case '0': return 10; 2800 case '1': return 11; 2801 case '2': return 12; 2802 case '3': return 13; 2803 case '4': return 14; 2804 case '5': return 15; 2805 } 2806 } 2807 } 2808 2809 /// parseITCondCode - Try to parse a condition code for an IT instruction. 2810 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2811 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2812 SMLoc S = Parser.getTok().getLoc(); 2813 const AsmToken &Tok = Parser.getTok(); 2814 if (!Tok.is(AsmToken::Identifier)) 2815 return MatchOperand_NoMatch; 2816 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2817 .Case("eq", ARMCC::EQ) 2818 .Case("ne", ARMCC::NE) 2819 .Case("hs", ARMCC::HS) 2820 .Case("cs", ARMCC::HS) 2821 .Case("lo", ARMCC::LO) 2822 .Case("cc", ARMCC::LO) 2823 .Case("mi", ARMCC::MI) 2824 .Case("pl", ARMCC::PL) 2825 .Case("vs", ARMCC::VS) 2826 .Case("vc", ARMCC::VC) 2827 .Case("hi", ARMCC::HI) 2828 .Case("ls", ARMCC::LS) 2829 .Case("ge", ARMCC::GE) 2830 .Case("lt", ARMCC::LT) 2831 .Case("gt", ARMCC::GT) 2832 .Case("le", ARMCC::LE) 2833 .Case("al", ARMCC::AL) 2834 .Default(~0U); 2835 if (CC == ~0U) 2836 return MatchOperand_NoMatch; 2837 Parser.Lex(); // Eat the token. 2838 2839 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2840 2841 return MatchOperand_Success; 2842 } 2843 2844 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2845 /// token must be an Identifier when called, and if it is a coprocessor 2846 /// number, the token is eaten and the operand is added to the operand list. 2847 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2848 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2849 SMLoc S = Parser.getTok().getLoc(); 2850 const AsmToken &Tok = Parser.getTok(); 2851 if (Tok.isNot(AsmToken::Identifier)) 2852 return MatchOperand_NoMatch; 2853 2854 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2855 if (Num == -1) 2856 return MatchOperand_NoMatch; 2857 2858 Parser.Lex(); // Eat identifier token. 2859 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2860 return MatchOperand_Success; 2861 } 2862 2863 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2864 /// token must be an Identifier when called, and if it is a coprocessor 2865 /// number, the token is eaten and the operand is added to the operand list. 2866 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2867 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2868 SMLoc S = Parser.getTok().getLoc(); 2869 const AsmToken &Tok = Parser.getTok(); 2870 if (Tok.isNot(AsmToken::Identifier)) 2871 return MatchOperand_NoMatch; 2872 2873 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2874 if (Reg == -1) 2875 return MatchOperand_NoMatch; 2876 2877 Parser.Lex(); // Eat identifier token. 2878 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2879 return MatchOperand_Success; 2880 } 2881 2882 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2883 /// coproc_option : '{' imm0_255 '}' 2884 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2885 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2886 SMLoc S = Parser.getTok().getLoc(); 2887 2888 // If this isn't a '{', this isn't a coprocessor immediate operand. 2889 if (Parser.getTok().isNot(AsmToken::LCurly)) 2890 return MatchOperand_NoMatch; 2891 Parser.Lex(); // Eat the '{' 2892 2893 const MCExpr *Expr; 2894 SMLoc Loc = Parser.getTok().getLoc(); 2895 if (getParser().parseExpression(Expr)) { 2896 Error(Loc, "illegal expression"); 2897 return MatchOperand_ParseFail; 2898 } 2899 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2900 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2901 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2902 return MatchOperand_ParseFail; 2903 } 2904 int Val = CE->getValue(); 2905 2906 // Check for and consume the closing '}' 2907 if (Parser.getTok().isNot(AsmToken::RCurly)) 2908 return MatchOperand_ParseFail; 2909 SMLoc E = Parser.getTok().getEndLoc(); 2910 Parser.Lex(); // Eat the '}' 2911 2912 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2913 return MatchOperand_Success; 2914 } 2915 2916 // For register list parsing, we need to map from raw GPR register numbering 2917 // to the enumeration values. The enumeration values aren't sorted by 2918 // register number due to our using "sp", "lr" and "pc" as canonical names. 2919 static unsigned getNextRegister(unsigned Reg) { 2920 // If this is a GPR, we need to do it manually, otherwise we can rely 2921 // on the sort ordering of the enumeration since the other reg-classes 2922 // are sane. 2923 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2924 return Reg + 1; 2925 switch(Reg) { 2926 default: llvm_unreachable("Invalid GPR number!"); 2927 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2928 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2929 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2930 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2931 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2932 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2933 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2934 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2935 } 2936 } 2937 2938 // Return the low-subreg of a given Q register. 2939 static unsigned getDRegFromQReg(unsigned QReg) { 2940 switch (QReg) { 2941 default: llvm_unreachable("expected a Q register!"); 2942 case ARM::Q0: return ARM::D0; 2943 case ARM::Q1: return ARM::D2; 2944 case ARM::Q2: return ARM::D4; 2945 case ARM::Q3: return ARM::D6; 2946 case ARM::Q4: return ARM::D8; 2947 case ARM::Q5: return ARM::D10; 2948 case ARM::Q6: return ARM::D12; 2949 case ARM::Q7: return ARM::D14; 2950 case ARM::Q8: return ARM::D16; 2951 case ARM::Q9: return ARM::D18; 2952 case ARM::Q10: return ARM::D20; 2953 case ARM::Q11: return ARM::D22; 2954 case ARM::Q12: return ARM::D24; 2955 case ARM::Q13: return ARM::D26; 2956 case ARM::Q14: return ARM::D28; 2957 case ARM::Q15: return ARM::D30; 2958 } 2959 } 2960 2961 /// Parse a register list. 2962 bool ARMAsmParser:: 2963 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2964 assert(Parser.getTok().is(AsmToken::LCurly) && 2965 "Token is not a Left Curly Brace"); 2966 SMLoc S = Parser.getTok().getLoc(); 2967 Parser.Lex(); // Eat '{' token. 2968 SMLoc RegLoc = Parser.getTok().getLoc(); 2969 2970 // Check the first register in the list to see what register class 2971 // this is a list of. 2972 int Reg = tryParseRegister(); 2973 if (Reg == -1) 2974 return Error(RegLoc, "register expected"); 2975 2976 // The reglist instructions have at most 16 registers, so reserve 2977 // space for that many. 2978 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2979 2980 // Allow Q regs and just interpret them as the two D sub-registers. 2981 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2982 Reg = getDRegFromQReg(Reg); 2983 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2984 ++Reg; 2985 } 2986 const MCRegisterClass *RC; 2987 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2988 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2989 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2990 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2991 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2992 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2993 else 2994 return Error(RegLoc, "invalid register in register list"); 2995 2996 // Store the register. 2997 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2998 2999 // This starts immediately after the first register token in the list, 3000 // so we can see either a comma or a minus (range separator) as a legal 3001 // next token. 3002 while (Parser.getTok().is(AsmToken::Comma) || 3003 Parser.getTok().is(AsmToken::Minus)) { 3004 if (Parser.getTok().is(AsmToken::Minus)) { 3005 Parser.Lex(); // Eat the minus. 3006 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3007 int EndReg = tryParseRegister(); 3008 if (EndReg == -1) 3009 return Error(AfterMinusLoc, "register expected"); 3010 // Allow Q regs and just interpret them as the two D sub-registers. 3011 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3012 EndReg = getDRegFromQReg(EndReg) + 1; 3013 // If the register is the same as the start reg, there's nothing 3014 // more to do. 3015 if (Reg == EndReg) 3016 continue; 3017 // The register must be in the same register class as the first. 3018 if (!RC->contains(EndReg)) 3019 return Error(AfterMinusLoc, "invalid register in register list"); 3020 // Ranges must go from low to high. 3021 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3022 return Error(AfterMinusLoc, "bad range in register list"); 3023 3024 // Add all the registers in the range to the register list. 3025 while (Reg != EndReg) { 3026 Reg = getNextRegister(Reg); 3027 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 3028 } 3029 continue; 3030 } 3031 Parser.Lex(); // Eat the comma. 3032 RegLoc = Parser.getTok().getLoc(); 3033 int OldReg = Reg; 3034 const AsmToken RegTok = Parser.getTok(); 3035 Reg = tryParseRegister(); 3036 if (Reg == -1) 3037 return Error(RegLoc, "register expected"); 3038 // Allow Q regs and just interpret them as the two D sub-registers. 3039 bool isQReg = false; 3040 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3041 Reg = getDRegFromQReg(Reg); 3042 isQReg = true; 3043 } 3044 // The register must be in the same register class as the first. 3045 if (!RC->contains(Reg)) 3046 return Error(RegLoc, "invalid register in register list"); 3047 // List must be monotonically increasing. 3048 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3049 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3050 Warning(RegLoc, "register list not in ascending order"); 3051 else 3052 return Error(RegLoc, "register list not in ascending order"); 3053 } 3054 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3055 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3056 ") in register list"); 3057 continue; 3058 } 3059 // VFP register lists must also be contiguous. 3060 // It's OK to use the enumeration values directly here rather, as the 3061 // VFP register classes have the enum sorted properly. 3062 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3063 Reg != OldReg + 1) 3064 return Error(RegLoc, "non-contiguous register range"); 3065 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 3066 if (isQReg) 3067 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 3068 } 3069 3070 if (Parser.getTok().isNot(AsmToken::RCurly)) 3071 return Error(Parser.getTok().getLoc(), "'}' expected"); 3072 SMLoc E = Parser.getTok().getEndLoc(); 3073 Parser.Lex(); // Eat '}' token. 3074 3075 // Push the register list operand. 3076 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3077 3078 // The ARM system instruction variants for LDM/STM have a '^' token here. 3079 if (Parser.getTok().is(AsmToken::Caret)) { 3080 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3081 Parser.Lex(); // Eat '^' token. 3082 } 3083 3084 return false; 3085 } 3086 3087 // Helper function to parse the lane index for vector lists. 3088 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3089 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3090 Index = 0; // Always return a defined index value. 3091 if (Parser.getTok().is(AsmToken::LBrac)) { 3092 Parser.Lex(); // Eat the '['. 3093 if (Parser.getTok().is(AsmToken::RBrac)) { 3094 // "Dn[]" is the 'all lanes' syntax. 3095 LaneKind = AllLanes; 3096 EndLoc = Parser.getTok().getEndLoc(); 3097 Parser.Lex(); // Eat the ']'. 3098 return MatchOperand_Success; 3099 } 3100 3101 // There's an optional '#' token here. Normally there wouldn't be, but 3102 // inline assemble puts one in, and it's friendly to accept that. 3103 if (Parser.getTok().is(AsmToken::Hash)) 3104 Parser.Lex(); // Eat '#' or '$'. 3105 3106 const MCExpr *LaneIndex; 3107 SMLoc Loc = Parser.getTok().getLoc(); 3108 if (getParser().parseExpression(LaneIndex)) { 3109 Error(Loc, "illegal expression"); 3110 return MatchOperand_ParseFail; 3111 } 3112 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3113 if (!CE) { 3114 Error(Loc, "lane index must be empty or an integer"); 3115 return MatchOperand_ParseFail; 3116 } 3117 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3118 Error(Parser.getTok().getLoc(), "']' expected"); 3119 return MatchOperand_ParseFail; 3120 } 3121 EndLoc = Parser.getTok().getEndLoc(); 3122 Parser.Lex(); // Eat the ']'. 3123 int64_t Val = CE->getValue(); 3124 3125 // FIXME: Make this range check context sensitive for .8, .16, .32. 3126 if (Val < 0 || Val > 7) { 3127 Error(Parser.getTok().getLoc(), "lane index out of range"); 3128 return MatchOperand_ParseFail; 3129 } 3130 Index = Val; 3131 LaneKind = IndexedLane; 3132 return MatchOperand_Success; 3133 } 3134 LaneKind = NoLanes; 3135 return MatchOperand_Success; 3136 } 3137 3138 // parse a vector register list 3139 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3140 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3141 VectorLaneTy LaneKind; 3142 unsigned LaneIndex; 3143 SMLoc S = Parser.getTok().getLoc(); 3144 // As an extension (to match gas), support a plain D register or Q register 3145 // (without encosing curly braces) as a single or double entry list, 3146 // respectively. 3147 if (Parser.getTok().is(AsmToken::Identifier)) { 3148 SMLoc E = Parser.getTok().getEndLoc(); 3149 int Reg = tryParseRegister(); 3150 if (Reg == -1) 3151 return MatchOperand_NoMatch; 3152 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3153 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3154 if (Res != MatchOperand_Success) 3155 return Res; 3156 switch (LaneKind) { 3157 case NoLanes: 3158 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3159 break; 3160 case AllLanes: 3161 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3162 S, E)); 3163 break; 3164 case IndexedLane: 3165 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3166 LaneIndex, 3167 false, S, E)); 3168 break; 3169 } 3170 return MatchOperand_Success; 3171 } 3172 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3173 Reg = getDRegFromQReg(Reg); 3174 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3175 if (Res != MatchOperand_Success) 3176 return Res; 3177 switch (LaneKind) { 3178 case NoLanes: 3179 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3180 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3181 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3182 break; 3183 case AllLanes: 3184 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3185 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3186 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3187 S, E)); 3188 break; 3189 case IndexedLane: 3190 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3191 LaneIndex, 3192 false, S, E)); 3193 break; 3194 } 3195 return MatchOperand_Success; 3196 } 3197 Error(S, "vector register expected"); 3198 return MatchOperand_ParseFail; 3199 } 3200 3201 if (Parser.getTok().isNot(AsmToken::LCurly)) 3202 return MatchOperand_NoMatch; 3203 3204 Parser.Lex(); // Eat '{' token. 3205 SMLoc RegLoc = Parser.getTok().getLoc(); 3206 3207 int Reg = tryParseRegister(); 3208 if (Reg == -1) { 3209 Error(RegLoc, "register expected"); 3210 return MatchOperand_ParseFail; 3211 } 3212 unsigned Count = 1; 3213 int Spacing = 0; 3214 unsigned FirstReg = Reg; 3215 // The list is of D registers, but we also allow Q regs and just interpret 3216 // them as the two D sub-registers. 3217 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3218 FirstReg = Reg = getDRegFromQReg(Reg); 3219 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3220 // it's ambiguous with four-register single spaced. 3221 ++Reg; 3222 ++Count; 3223 } 3224 3225 SMLoc E; 3226 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3227 return MatchOperand_ParseFail; 3228 3229 while (Parser.getTok().is(AsmToken::Comma) || 3230 Parser.getTok().is(AsmToken::Minus)) { 3231 if (Parser.getTok().is(AsmToken::Minus)) { 3232 if (!Spacing) 3233 Spacing = 1; // Register range implies a single spaced list. 3234 else if (Spacing == 2) { 3235 Error(Parser.getTok().getLoc(), 3236 "sequential registers in double spaced list"); 3237 return MatchOperand_ParseFail; 3238 } 3239 Parser.Lex(); // Eat the minus. 3240 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3241 int EndReg = tryParseRegister(); 3242 if (EndReg == -1) { 3243 Error(AfterMinusLoc, "register expected"); 3244 return MatchOperand_ParseFail; 3245 } 3246 // Allow Q regs and just interpret them as the two D sub-registers. 3247 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3248 EndReg = getDRegFromQReg(EndReg) + 1; 3249 // If the register is the same as the start reg, there's nothing 3250 // more to do. 3251 if (Reg == EndReg) 3252 continue; 3253 // The register must be in the same register class as the first. 3254 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3255 Error(AfterMinusLoc, "invalid register in register list"); 3256 return MatchOperand_ParseFail; 3257 } 3258 // Ranges must go from low to high. 3259 if (Reg > EndReg) { 3260 Error(AfterMinusLoc, "bad range in register list"); 3261 return MatchOperand_ParseFail; 3262 } 3263 // Parse the lane specifier if present. 3264 VectorLaneTy NextLaneKind; 3265 unsigned NextLaneIndex; 3266 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3267 MatchOperand_Success) 3268 return MatchOperand_ParseFail; 3269 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3270 Error(AfterMinusLoc, "mismatched lane index in register list"); 3271 return MatchOperand_ParseFail; 3272 } 3273 3274 // Add all the registers in the range to the register list. 3275 Count += EndReg - Reg; 3276 Reg = EndReg; 3277 continue; 3278 } 3279 Parser.Lex(); // Eat the comma. 3280 RegLoc = Parser.getTok().getLoc(); 3281 int OldReg = Reg; 3282 Reg = tryParseRegister(); 3283 if (Reg == -1) { 3284 Error(RegLoc, "register expected"); 3285 return MatchOperand_ParseFail; 3286 } 3287 // vector register lists must be contiguous. 3288 // It's OK to use the enumeration values directly here rather, as the 3289 // VFP register classes have the enum sorted properly. 3290 // 3291 // The list is of D registers, but we also allow Q regs and just interpret 3292 // them as the two D sub-registers. 3293 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3294 if (!Spacing) 3295 Spacing = 1; // Register range implies a single spaced list. 3296 else if (Spacing == 2) { 3297 Error(RegLoc, 3298 "invalid register in double-spaced list (must be 'D' register')"); 3299 return MatchOperand_ParseFail; 3300 } 3301 Reg = getDRegFromQReg(Reg); 3302 if (Reg != OldReg + 1) { 3303 Error(RegLoc, "non-contiguous register range"); 3304 return MatchOperand_ParseFail; 3305 } 3306 ++Reg; 3307 Count += 2; 3308 // Parse the lane specifier if present. 3309 VectorLaneTy NextLaneKind; 3310 unsigned NextLaneIndex; 3311 SMLoc LaneLoc = Parser.getTok().getLoc(); 3312 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3313 MatchOperand_Success) 3314 return MatchOperand_ParseFail; 3315 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3316 Error(LaneLoc, "mismatched lane index in register list"); 3317 return MatchOperand_ParseFail; 3318 } 3319 continue; 3320 } 3321 // Normal D register. 3322 // Figure out the register spacing (single or double) of the list if 3323 // we don't know it already. 3324 if (!Spacing) 3325 Spacing = 1 + (Reg == OldReg + 2); 3326 3327 // Just check that it's contiguous and keep going. 3328 if (Reg != OldReg + Spacing) { 3329 Error(RegLoc, "non-contiguous register range"); 3330 return MatchOperand_ParseFail; 3331 } 3332 ++Count; 3333 // Parse the lane specifier if present. 3334 VectorLaneTy NextLaneKind; 3335 unsigned NextLaneIndex; 3336 SMLoc EndLoc = Parser.getTok().getLoc(); 3337 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3338 return MatchOperand_ParseFail; 3339 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3340 Error(EndLoc, "mismatched lane index in register list"); 3341 return MatchOperand_ParseFail; 3342 } 3343 } 3344 3345 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3346 Error(Parser.getTok().getLoc(), "'}' expected"); 3347 return MatchOperand_ParseFail; 3348 } 3349 E = Parser.getTok().getEndLoc(); 3350 Parser.Lex(); // Eat '}' token. 3351 3352 switch (LaneKind) { 3353 case NoLanes: 3354 // Two-register operands have been converted to the 3355 // composite register classes. 3356 if (Count == 2) { 3357 const MCRegisterClass *RC = (Spacing == 1) ? 3358 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3359 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3360 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3361 } 3362 3363 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3364 (Spacing == 2), S, E)); 3365 break; 3366 case AllLanes: 3367 // Two-register operands have been converted to the 3368 // composite register classes. 3369 if (Count == 2) { 3370 const MCRegisterClass *RC = (Spacing == 1) ? 3371 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3372 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3373 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3374 } 3375 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3376 (Spacing == 2), 3377 S, E)); 3378 break; 3379 case IndexedLane: 3380 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3381 LaneIndex, 3382 (Spacing == 2), 3383 S, E)); 3384 break; 3385 } 3386 return MatchOperand_Success; 3387 } 3388 3389 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3390 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3391 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3392 SMLoc S = Parser.getTok().getLoc(); 3393 const AsmToken &Tok = Parser.getTok(); 3394 unsigned Opt; 3395 3396 if (Tok.is(AsmToken::Identifier)) { 3397 StringRef OptStr = Tok.getString(); 3398 3399 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3400 .Case("sy", ARM_MB::SY) 3401 .Case("st", ARM_MB::ST) 3402 .Case("sh", ARM_MB::ISH) 3403 .Case("ish", ARM_MB::ISH) 3404 .Case("shst", ARM_MB::ISHST) 3405 .Case("ishst", ARM_MB::ISHST) 3406 .Case("nsh", ARM_MB::NSH) 3407 .Case("un", ARM_MB::NSH) 3408 .Case("nshst", ARM_MB::NSHST) 3409 .Case("unst", ARM_MB::NSHST) 3410 .Case("osh", ARM_MB::OSH) 3411 .Case("oshst", ARM_MB::OSHST) 3412 .Default(~0U); 3413 3414 if (Opt == ~0U) 3415 return MatchOperand_NoMatch; 3416 3417 Parser.Lex(); // Eat identifier token. 3418 } else if (Tok.is(AsmToken::Hash) || 3419 Tok.is(AsmToken::Dollar) || 3420 Tok.is(AsmToken::Integer)) { 3421 if (Parser.getTok().isNot(AsmToken::Integer)) 3422 Parser.Lex(); // Eat '#' or '$'. 3423 SMLoc Loc = Parser.getTok().getLoc(); 3424 3425 const MCExpr *MemBarrierID; 3426 if (getParser().parseExpression(MemBarrierID)) { 3427 Error(Loc, "illegal expression"); 3428 return MatchOperand_ParseFail; 3429 } 3430 3431 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3432 if (!CE) { 3433 Error(Loc, "constant expression expected"); 3434 return MatchOperand_ParseFail; 3435 } 3436 3437 int Val = CE->getValue(); 3438 if (Val & ~0xf) { 3439 Error(Loc, "immediate value out of range"); 3440 return MatchOperand_ParseFail; 3441 } 3442 3443 Opt = ARM_MB::RESERVED_0 + Val; 3444 } else 3445 return MatchOperand_ParseFail; 3446 3447 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3448 return MatchOperand_Success; 3449 } 3450 3451 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3452 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3453 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3454 SMLoc S = Parser.getTok().getLoc(); 3455 const AsmToken &Tok = Parser.getTok(); 3456 unsigned Opt; 3457 3458 if (Tok.is(AsmToken::Identifier)) { 3459 StringRef OptStr = Tok.getString(); 3460 3461 if (OptStr.lower() == "sy") 3462 Opt = ARM_ISB::SY; 3463 else 3464 return MatchOperand_NoMatch; 3465 3466 Parser.Lex(); // Eat identifier token. 3467 } else if (Tok.is(AsmToken::Hash) || 3468 Tok.is(AsmToken::Dollar) || 3469 Tok.is(AsmToken::Integer)) { 3470 if (Parser.getTok().isNot(AsmToken::Integer)) 3471 Parser.Lex(); // Eat '#' or '$'. 3472 SMLoc Loc = Parser.getTok().getLoc(); 3473 3474 const MCExpr *ISBarrierID; 3475 if (getParser().parseExpression(ISBarrierID)) { 3476 Error(Loc, "illegal expression"); 3477 return MatchOperand_ParseFail; 3478 } 3479 3480 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3481 if (!CE) { 3482 Error(Loc, "constant expression expected"); 3483 return MatchOperand_ParseFail; 3484 } 3485 3486 int Val = CE->getValue(); 3487 if (Val & ~0xf) { 3488 Error(Loc, "immediate value out of range"); 3489 return MatchOperand_ParseFail; 3490 } 3491 3492 Opt = ARM_ISB::RESERVED_0 + Val; 3493 } else 3494 return MatchOperand_ParseFail; 3495 3496 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3497 (ARM_ISB::InstSyncBOpt)Opt, S)); 3498 return MatchOperand_Success; 3499 } 3500 3501 3502 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3503 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3504 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3505 SMLoc S = Parser.getTok().getLoc(); 3506 const AsmToken &Tok = Parser.getTok(); 3507 if (!Tok.is(AsmToken::Identifier)) 3508 return MatchOperand_NoMatch; 3509 StringRef IFlagsStr = Tok.getString(); 3510 3511 // An iflags string of "none" is interpreted to mean that none of the AIF 3512 // bits are set. Not a terribly useful instruction, but a valid encoding. 3513 unsigned IFlags = 0; 3514 if (IFlagsStr != "none") { 3515 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3516 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3517 .Case("a", ARM_PROC::A) 3518 .Case("i", ARM_PROC::I) 3519 .Case("f", ARM_PROC::F) 3520 .Default(~0U); 3521 3522 // If some specific iflag is already set, it means that some letter is 3523 // present more than once, this is not acceptable. 3524 if (Flag == ~0U || (IFlags & Flag)) 3525 return MatchOperand_NoMatch; 3526 3527 IFlags |= Flag; 3528 } 3529 } 3530 3531 Parser.Lex(); // Eat identifier token. 3532 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3533 return MatchOperand_Success; 3534 } 3535 3536 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3537 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3538 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3539 SMLoc S = Parser.getTok().getLoc(); 3540 const AsmToken &Tok = Parser.getTok(); 3541 if (!Tok.is(AsmToken::Identifier)) 3542 return MatchOperand_NoMatch; 3543 StringRef Mask = Tok.getString(); 3544 3545 if (isMClass()) { 3546 // See ARMv6-M 10.1.1 3547 std::string Name = Mask.lower(); 3548 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3549 // Note: in the documentation: 3550 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3551 // for MSR APSR_nzcvq. 3552 // but we do make it an alias here. This is so to get the "mask encoding" 3553 // bits correct on MSR APSR writes. 3554 // 3555 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3556 // should really only be allowed when writing a special register. Note 3557 // they get dropped in the MRS instruction reading a special register as 3558 // the SYSm field is only 8 bits. 3559 // 3560 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3561 // includes the DSP extension but that is not checked. 3562 .Case("apsr", 0x800) 3563 .Case("apsr_nzcvq", 0x800) 3564 .Case("apsr_g", 0x400) 3565 .Case("apsr_nzcvqg", 0xc00) 3566 .Case("iapsr", 0x801) 3567 .Case("iapsr_nzcvq", 0x801) 3568 .Case("iapsr_g", 0x401) 3569 .Case("iapsr_nzcvqg", 0xc01) 3570 .Case("eapsr", 0x802) 3571 .Case("eapsr_nzcvq", 0x802) 3572 .Case("eapsr_g", 0x402) 3573 .Case("eapsr_nzcvqg", 0xc02) 3574 .Case("xpsr", 0x803) 3575 .Case("xpsr_nzcvq", 0x803) 3576 .Case("xpsr_g", 0x403) 3577 .Case("xpsr_nzcvqg", 0xc03) 3578 .Case("ipsr", 0x805) 3579 .Case("epsr", 0x806) 3580 .Case("iepsr", 0x807) 3581 .Case("msp", 0x808) 3582 .Case("psp", 0x809) 3583 .Case("primask", 0x810) 3584 .Case("basepri", 0x811) 3585 .Case("basepri_max", 0x812) 3586 .Case("faultmask", 0x813) 3587 .Case("control", 0x814) 3588 .Default(~0U); 3589 3590 if (FlagsVal == ~0U) 3591 return MatchOperand_NoMatch; 3592 3593 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3594 // basepri, basepri_max and faultmask only valid for V7m. 3595 return MatchOperand_NoMatch; 3596 3597 Parser.Lex(); // Eat identifier token. 3598 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3599 return MatchOperand_Success; 3600 } 3601 3602 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3603 size_t Start = 0, Next = Mask.find('_'); 3604 StringRef Flags = ""; 3605 std::string SpecReg = Mask.slice(Start, Next).lower(); 3606 if (Next != StringRef::npos) 3607 Flags = Mask.slice(Next+1, Mask.size()); 3608 3609 // FlagsVal contains the complete mask: 3610 // 3-0: Mask 3611 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3612 unsigned FlagsVal = 0; 3613 3614 if (SpecReg == "apsr") { 3615 FlagsVal = StringSwitch<unsigned>(Flags) 3616 .Case("nzcvq", 0x8) // same as CPSR_f 3617 .Case("g", 0x4) // same as CPSR_s 3618 .Case("nzcvqg", 0xc) // same as CPSR_fs 3619 .Default(~0U); 3620 3621 if (FlagsVal == ~0U) { 3622 if (!Flags.empty()) 3623 return MatchOperand_NoMatch; 3624 else 3625 FlagsVal = 8; // No flag 3626 } 3627 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3628 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3629 if (Flags == "all" || Flags == "") 3630 Flags = "fc"; 3631 for (int i = 0, e = Flags.size(); i != e; ++i) { 3632 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3633 .Case("c", 1) 3634 .Case("x", 2) 3635 .Case("s", 4) 3636 .Case("f", 8) 3637 .Default(~0U); 3638 3639 // If some specific flag is already set, it means that some letter is 3640 // present more than once, this is not acceptable. 3641 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3642 return MatchOperand_NoMatch; 3643 FlagsVal |= Flag; 3644 } 3645 } else // No match for special register. 3646 return MatchOperand_NoMatch; 3647 3648 // Special register without flags is NOT equivalent to "fc" flags. 3649 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3650 // two lines would enable gas compatibility at the expense of breaking 3651 // round-tripping. 3652 // 3653 // if (!FlagsVal) 3654 // FlagsVal = 0x9; 3655 3656 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3657 if (SpecReg == "spsr") 3658 FlagsVal |= 16; 3659 3660 Parser.Lex(); // Eat identifier token. 3661 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3662 return MatchOperand_Success; 3663 } 3664 3665 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3666 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3667 int Low, int High) { 3668 const AsmToken &Tok = Parser.getTok(); 3669 if (Tok.isNot(AsmToken::Identifier)) { 3670 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3671 return MatchOperand_ParseFail; 3672 } 3673 StringRef ShiftName = Tok.getString(); 3674 std::string LowerOp = Op.lower(); 3675 std::string UpperOp = Op.upper(); 3676 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3677 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3678 return MatchOperand_ParseFail; 3679 } 3680 Parser.Lex(); // Eat shift type token. 3681 3682 // There must be a '#' and a shift amount. 3683 if (Parser.getTok().isNot(AsmToken::Hash) && 3684 Parser.getTok().isNot(AsmToken::Dollar)) { 3685 Error(Parser.getTok().getLoc(), "'#' expected"); 3686 return MatchOperand_ParseFail; 3687 } 3688 Parser.Lex(); // Eat hash token. 3689 3690 const MCExpr *ShiftAmount; 3691 SMLoc Loc = Parser.getTok().getLoc(); 3692 SMLoc EndLoc; 3693 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3694 Error(Loc, "illegal expression"); 3695 return MatchOperand_ParseFail; 3696 } 3697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3698 if (!CE) { 3699 Error(Loc, "constant expression expected"); 3700 return MatchOperand_ParseFail; 3701 } 3702 int Val = CE->getValue(); 3703 if (Val < Low || Val > High) { 3704 Error(Loc, "immediate value out of range"); 3705 return MatchOperand_ParseFail; 3706 } 3707 3708 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 3709 3710 return MatchOperand_Success; 3711 } 3712 3713 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3714 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3715 const AsmToken &Tok = Parser.getTok(); 3716 SMLoc S = Tok.getLoc(); 3717 if (Tok.isNot(AsmToken::Identifier)) { 3718 Error(S, "'be' or 'le' operand expected"); 3719 return MatchOperand_ParseFail; 3720 } 3721 int Val = StringSwitch<int>(Tok.getString().lower()) 3722 .Case("be", 1) 3723 .Case("le", 0) 3724 .Default(-1); 3725 Parser.Lex(); // Eat the token. 3726 3727 if (Val == -1) { 3728 Error(S, "'be' or 'le' operand expected"); 3729 return MatchOperand_ParseFail; 3730 } 3731 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3732 getContext()), 3733 S, Tok.getEndLoc())); 3734 return MatchOperand_Success; 3735 } 3736 3737 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3738 /// instructions. Legal values are: 3739 /// lsl #n 'n' in [0,31] 3740 /// asr #n 'n' in [1,32] 3741 /// n == 32 encoded as n == 0. 3742 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3743 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3744 const AsmToken &Tok = Parser.getTok(); 3745 SMLoc S = Tok.getLoc(); 3746 if (Tok.isNot(AsmToken::Identifier)) { 3747 Error(S, "shift operator 'asr' or 'lsl' expected"); 3748 return MatchOperand_ParseFail; 3749 } 3750 StringRef ShiftName = Tok.getString(); 3751 bool isASR; 3752 if (ShiftName == "lsl" || ShiftName == "LSL") 3753 isASR = false; 3754 else if (ShiftName == "asr" || ShiftName == "ASR") 3755 isASR = true; 3756 else { 3757 Error(S, "shift operator 'asr' or 'lsl' expected"); 3758 return MatchOperand_ParseFail; 3759 } 3760 Parser.Lex(); // Eat the operator. 3761 3762 // A '#' and a shift amount. 3763 if (Parser.getTok().isNot(AsmToken::Hash) && 3764 Parser.getTok().isNot(AsmToken::Dollar)) { 3765 Error(Parser.getTok().getLoc(), "'#' expected"); 3766 return MatchOperand_ParseFail; 3767 } 3768 Parser.Lex(); // Eat hash token. 3769 SMLoc ExLoc = Parser.getTok().getLoc(); 3770 3771 const MCExpr *ShiftAmount; 3772 SMLoc EndLoc; 3773 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3774 Error(ExLoc, "malformed shift expression"); 3775 return MatchOperand_ParseFail; 3776 } 3777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3778 if (!CE) { 3779 Error(ExLoc, "shift amount must be an immediate"); 3780 return MatchOperand_ParseFail; 3781 } 3782 3783 int64_t Val = CE->getValue(); 3784 if (isASR) { 3785 // Shift amount must be in [1,32] 3786 if (Val < 1 || Val > 32) { 3787 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 3788 return MatchOperand_ParseFail; 3789 } 3790 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3791 if (isThumb() && Val == 32) { 3792 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 3793 return MatchOperand_ParseFail; 3794 } 3795 if (Val == 32) Val = 0; 3796 } else { 3797 // Shift amount must be in [1,32] 3798 if (Val < 0 || Val > 31) { 3799 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 3800 return MatchOperand_ParseFail; 3801 } 3802 } 3803 3804 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 3805 3806 return MatchOperand_Success; 3807 } 3808 3809 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3810 /// of instructions. Legal values are: 3811 /// ror #n 'n' in {0, 8, 16, 24} 3812 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3813 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3814 const AsmToken &Tok = Parser.getTok(); 3815 SMLoc S = Tok.getLoc(); 3816 if (Tok.isNot(AsmToken::Identifier)) 3817 return MatchOperand_NoMatch; 3818 StringRef ShiftName = Tok.getString(); 3819 if (ShiftName != "ror" && ShiftName != "ROR") 3820 return MatchOperand_NoMatch; 3821 Parser.Lex(); // Eat the operator. 3822 3823 // A '#' and a rotate amount. 3824 if (Parser.getTok().isNot(AsmToken::Hash) && 3825 Parser.getTok().isNot(AsmToken::Dollar)) { 3826 Error(Parser.getTok().getLoc(), "'#' expected"); 3827 return MatchOperand_ParseFail; 3828 } 3829 Parser.Lex(); // Eat hash token. 3830 SMLoc ExLoc = Parser.getTok().getLoc(); 3831 3832 const MCExpr *ShiftAmount; 3833 SMLoc EndLoc; 3834 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3835 Error(ExLoc, "malformed rotate expression"); 3836 return MatchOperand_ParseFail; 3837 } 3838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3839 if (!CE) { 3840 Error(ExLoc, "rotate amount must be an immediate"); 3841 return MatchOperand_ParseFail; 3842 } 3843 3844 int64_t Val = CE->getValue(); 3845 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 3846 // normally, zero is represented in asm by omitting the rotate operand 3847 // entirely. 3848 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 3849 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 3850 return MatchOperand_ParseFail; 3851 } 3852 3853 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 3854 3855 return MatchOperand_Success; 3856 } 3857 3858 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3859 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3860 SMLoc S = Parser.getTok().getLoc(); 3861 // The bitfield descriptor is really two operands, the LSB and the width. 3862 if (Parser.getTok().isNot(AsmToken::Hash) && 3863 Parser.getTok().isNot(AsmToken::Dollar)) { 3864 Error(Parser.getTok().getLoc(), "'#' expected"); 3865 return MatchOperand_ParseFail; 3866 } 3867 Parser.Lex(); // Eat hash token. 3868 3869 const MCExpr *LSBExpr; 3870 SMLoc E = Parser.getTok().getLoc(); 3871 if (getParser().parseExpression(LSBExpr)) { 3872 Error(E, "malformed immediate expression"); 3873 return MatchOperand_ParseFail; 3874 } 3875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3876 if (!CE) { 3877 Error(E, "'lsb' operand must be an immediate"); 3878 return MatchOperand_ParseFail; 3879 } 3880 3881 int64_t LSB = CE->getValue(); 3882 // The LSB must be in the range [0,31] 3883 if (LSB < 0 || LSB > 31) { 3884 Error(E, "'lsb' operand must be in the range [0,31]"); 3885 return MatchOperand_ParseFail; 3886 } 3887 E = Parser.getTok().getLoc(); 3888 3889 // Expect another immediate operand. 3890 if (Parser.getTok().isNot(AsmToken::Comma)) { 3891 Error(Parser.getTok().getLoc(), "too few operands"); 3892 return MatchOperand_ParseFail; 3893 } 3894 Parser.Lex(); // Eat hash token. 3895 if (Parser.getTok().isNot(AsmToken::Hash) && 3896 Parser.getTok().isNot(AsmToken::Dollar)) { 3897 Error(Parser.getTok().getLoc(), "'#' expected"); 3898 return MatchOperand_ParseFail; 3899 } 3900 Parser.Lex(); // Eat hash token. 3901 3902 const MCExpr *WidthExpr; 3903 SMLoc EndLoc; 3904 if (getParser().parseExpression(WidthExpr, EndLoc)) { 3905 Error(E, "malformed immediate expression"); 3906 return MatchOperand_ParseFail; 3907 } 3908 CE = dyn_cast<MCConstantExpr>(WidthExpr); 3909 if (!CE) { 3910 Error(E, "'width' operand must be an immediate"); 3911 return MatchOperand_ParseFail; 3912 } 3913 3914 int64_t Width = CE->getValue(); 3915 // The LSB must be in the range [1,32-lsb] 3916 if (Width < 1 || Width > 32 - LSB) { 3917 Error(E, "'width' operand must be in the range [1,32-lsb]"); 3918 return MatchOperand_ParseFail; 3919 } 3920 3921 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 3922 3923 return MatchOperand_Success; 3924 } 3925 3926 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3927 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3928 // Check for a post-index addressing register operand. Specifically: 3929 // postidx_reg := '+' register {, shift} 3930 // | '-' register {, shift} 3931 // | register {, shift} 3932 3933 // This method must return MatchOperand_NoMatch without consuming any tokens 3934 // in the case where there is no match, as other alternatives take other 3935 // parse methods. 3936 AsmToken Tok = Parser.getTok(); 3937 SMLoc S = Tok.getLoc(); 3938 bool haveEaten = false; 3939 bool isAdd = true; 3940 if (Tok.is(AsmToken::Plus)) { 3941 Parser.Lex(); // Eat the '+' token. 3942 haveEaten = true; 3943 } else if (Tok.is(AsmToken::Minus)) { 3944 Parser.Lex(); // Eat the '-' token. 3945 isAdd = false; 3946 haveEaten = true; 3947 } 3948 3949 SMLoc E = Parser.getTok().getEndLoc(); 3950 int Reg = tryParseRegister(); 3951 if (Reg == -1) { 3952 if (!haveEaten) 3953 return MatchOperand_NoMatch; 3954 Error(Parser.getTok().getLoc(), "register expected"); 3955 return MatchOperand_ParseFail; 3956 } 3957 3958 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3959 unsigned ShiftImm = 0; 3960 if (Parser.getTok().is(AsmToken::Comma)) { 3961 Parser.Lex(); // Eat the ','. 3962 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 3963 return MatchOperand_ParseFail; 3964 3965 // FIXME: Only approximates end...may include intervening whitespace. 3966 E = Parser.getTok().getLoc(); 3967 } 3968 3969 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3970 ShiftImm, S, E)); 3971 3972 return MatchOperand_Success; 3973 } 3974 3975 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3976 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3977 // Check for a post-index addressing register operand. Specifically: 3978 // am3offset := '+' register 3979 // | '-' register 3980 // | register 3981 // | # imm 3982 // | # + imm 3983 // | # - imm 3984 3985 // This method must return MatchOperand_NoMatch without consuming any tokens 3986 // in the case where there is no match, as other alternatives take other 3987 // parse methods. 3988 AsmToken Tok = Parser.getTok(); 3989 SMLoc S = Tok.getLoc(); 3990 3991 // Do immediates first, as we always parse those if we have a '#'. 3992 if (Parser.getTok().is(AsmToken::Hash) || 3993 Parser.getTok().is(AsmToken::Dollar)) { 3994 Parser.Lex(); // Eat '#' or '$'. 3995 // Explicitly look for a '-', as we need to encode negative zero 3996 // differently. 3997 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3998 const MCExpr *Offset; 3999 SMLoc E; 4000 if (getParser().parseExpression(Offset, E)) 4001 return MatchOperand_ParseFail; 4002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4003 if (!CE) { 4004 Error(S, "constant expression expected"); 4005 return MatchOperand_ParseFail; 4006 } 4007 // Negative zero is encoded as the flag value INT32_MIN. 4008 int32_t Val = CE->getValue(); 4009 if (isNegative && Val == 0) 4010 Val = INT32_MIN; 4011 4012 Operands.push_back( 4013 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 4014 4015 return MatchOperand_Success; 4016 } 4017 4018 4019 bool haveEaten = false; 4020 bool isAdd = true; 4021 if (Tok.is(AsmToken::Plus)) { 4022 Parser.Lex(); // Eat the '+' token. 4023 haveEaten = true; 4024 } else if (Tok.is(AsmToken::Minus)) { 4025 Parser.Lex(); // Eat the '-' token. 4026 isAdd = false; 4027 haveEaten = true; 4028 } 4029 4030 Tok = Parser.getTok(); 4031 int Reg = tryParseRegister(); 4032 if (Reg == -1) { 4033 if (!haveEaten) 4034 return MatchOperand_NoMatch; 4035 Error(Tok.getLoc(), "register expected"); 4036 return MatchOperand_ParseFail; 4037 } 4038 4039 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 4040 0, S, Tok.getEndLoc())); 4041 4042 return MatchOperand_Success; 4043 } 4044 4045 /// cvtT2LdrdPre - Convert parsed operands to MCInst. 4046 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4047 /// when they refer multiple MIOperands inside a single one. 4048 void ARMAsmParser:: 4049 cvtT2LdrdPre(MCInst &Inst, 4050 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4051 // Rt, Rt2 4052 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4053 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4054 // Create a writeback register dummy placeholder. 4055 Inst.addOperand(MCOperand::CreateReg(0)); 4056 // addr 4057 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 4058 // pred 4059 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4060 } 4061 4062 /// cvtT2StrdPre - Convert parsed operands to MCInst. 4063 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4064 /// when they refer multiple MIOperands inside a single one. 4065 void ARMAsmParser:: 4066 cvtT2StrdPre(MCInst &Inst, 4067 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4068 // Create a writeback register dummy placeholder. 4069 Inst.addOperand(MCOperand::CreateReg(0)); 4070 // Rt, Rt2 4071 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4072 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4073 // addr 4074 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 4075 // pred 4076 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4077 } 4078 4079 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 4080 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4081 /// when they refer multiple MIOperands inside a single one. 4082 void ARMAsmParser:: 4083 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 4084 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4085 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4086 4087 // Create a writeback register dummy placeholder. 4088 Inst.addOperand(MCOperand::CreateImm(0)); 4089 4090 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 4091 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4092 } 4093 4094 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 4095 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4096 /// when they refer multiple MIOperands inside a single one. 4097 void ARMAsmParser:: 4098 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 4099 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4100 // Create a writeback register dummy placeholder. 4101 Inst.addOperand(MCOperand::CreateImm(0)); 4102 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4103 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 4104 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4105 } 4106 4107 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 4108 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4109 /// when they refer multiple MIOperands inside a single one. 4110 void ARMAsmParser:: 4111 cvtLdWriteBackRegAddrMode2(MCInst &Inst, 4112 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4113 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4114 4115 // Create a writeback register dummy placeholder. 4116 Inst.addOperand(MCOperand::CreateImm(0)); 4117 4118 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 4119 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4120 } 4121 4122 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 4123 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4124 /// when they refer multiple MIOperands inside a single one. 4125 void ARMAsmParser:: 4126 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 4127 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4128 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4129 4130 // Create a writeback register dummy placeholder. 4131 Inst.addOperand(MCOperand::CreateImm(0)); 4132 4133 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 4134 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4135 } 4136 4137 4138 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 4139 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4140 /// when they refer multiple MIOperands inside a single one. 4141 void ARMAsmParser:: 4142 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 4143 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4144 // Create a writeback register dummy placeholder. 4145 Inst.addOperand(MCOperand::CreateImm(0)); 4146 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4147 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 4148 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4149 } 4150 4151 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 4152 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4153 /// when they refer multiple MIOperands inside a single one. 4154 void ARMAsmParser:: 4155 cvtStWriteBackRegAddrMode2(MCInst &Inst, 4156 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4157 // Create a writeback register dummy placeholder. 4158 Inst.addOperand(MCOperand::CreateImm(0)); 4159 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4160 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 4161 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4162 } 4163 4164 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4165 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4166 /// when they refer multiple MIOperands inside a single one. 4167 void ARMAsmParser:: 4168 cvtStWriteBackRegAddrMode3(MCInst &Inst, 4169 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4170 // Create a writeback register dummy placeholder. 4171 Inst.addOperand(MCOperand::CreateImm(0)); 4172 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4173 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4174 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4175 } 4176 4177 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 4178 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4179 /// when they refer multiple MIOperands inside a single one. 4180 void ARMAsmParser:: 4181 cvtLdExtTWriteBackImm(MCInst &Inst, 4182 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4183 // Rt 4184 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4185 // Create a writeback register dummy placeholder. 4186 Inst.addOperand(MCOperand::CreateImm(0)); 4187 // addr 4188 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4189 // offset 4190 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4191 // pred 4192 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4193 } 4194 4195 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 4196 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4197 /// when they refer multiple MIOperands inside a single one. 4198 void ARMAsmParser:: 4199 cvtLdExtTWriteBackReg(MCInst &Inst, 4200 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4201 // Rt 4202 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4203 // Create a writeback register dummy placeholder. 4204 Inst.addOperand(MCOperand::CreateImm(0)); 4205 // addr 4206 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4207 // offset 4208 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4209 // pred 4210 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4211 } 4212 4213 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 4214 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4215 /// when they refer multiple MIOperands inside a single one. 4216 void ARMAsmParser:: 4217 cvtStExtTWriteBackImm(MCInst &Inst, 4218 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4219 // Create a writeback register dummy placeholder. 4220 Inst.addOperand(MCOperand::CreateImm(0)); 4221 // Rt 4222 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4223 // addr 4224 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4225 // offset 4226 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4227 // pred 4228 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4229 } 4230 4231 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 4232 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4233 /// when they refer multiple MIOperands inside a single one. 4234 void ARMAsmParser:: 4235 cvtStExtTWriteBackReg(MCInst &Inst, 4236 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4237 // Create a writeback register dummy placeholder. 4238 Inst.addOperand(MCOperand::CreateImm(0)); 4239 // Rt 4240 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4241 // addr 4242 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4243 // offset 4244 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4245 // pred 4246 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4247 } 4248 4249 /// cvtLdrdPre - Convert parsed operands to MCInst. 4250 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4251 /// when they refer multiple MIOperands inside a single one. 4252 void ARMAsmParser:: 4253 cvtLdrdPre(MCInst &Inst, 4254 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4255 // Rt, Rt2 4256 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4257 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4258 // Create a writeback register dummy placeholder. 4259 Inst.addOperand(MCOperand::CreateImm(0)); 4260 // addr 4261 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4262 // pred 4263 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4264 } 4265 4266 /// cvtStrdPre - Convert parsed operands to MCInst. 4267 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4268 /// when they refer multiple MIOperands inside a single one. 4269 void ARMAsmParser:: 4270 cvtStrdPre(MCInst &Inst, 4271 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4272 // Create a writeback register dummy placeholder. 4273 Inst.addOperand(MCOperand::CreateImm(0)); 4274 // Rt, Rt2 4275 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4276 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4277 // addr 4278 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4279 // pred 4280 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4281 } 4282 4283 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4284 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4285 /// when they refer multiple MIOperands inside a single one. 4286 void ARMAsmParser:: 4287 cvtLdWriteBackRegAddrMode3(MCInst &Inst, 4288 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4289 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4290 // Create a writeback register dummy placeholder. 4291 Inst.addOperand(MCOperand::CreateImm(0)); 4292 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4293 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4294 } 4295 4296 /// cvtThumbMultiply - Convert parsed operands to MCInst. 4297 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4298 /// when they refer multiple MIOperands inside a single one. 4299 void ARMAsmParser:: 4300 cvtThumbMultiply(MCInst &Inst, 4301 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4302 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4303 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4304 // If we have a three-operand form, make sure to set Rn to be the operand 4305 // that isn't the same as Rd. 4306 unsigned RegOp = 4; 4307 if (Operands.size() == 6 && 4308 ((ARMOperand*)Operands[4])->getReg() == 4309 ((ARMOperand*)Operands[3])->getReg()) 4310 RegOp = 5; 4311 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4312 Inst.addOperand(Inst.getOperand(0)); 4313 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4314 } 4315 4316 void ARMAsmParser:: 4317 cvtVLDwbFixed(MCInst &Inst, 4318 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4319 // Vd 4320 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4321 // Create a writeback register dummy placeholder. 4322 Inst.addOperand(MCOperand::CreateImm(0)); 4323 // Vn 4324 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4325 // pred 4326 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4327 } 4328 4329 void ARMAsmParser:: 4330 cvtVLDwbRegister(MCInst &Inst, 4331 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4332 // Vd 4333 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4334 // Create a writeback register dummy placeholder. 4335 Inst.addOperand(MCOperand::CreateImm(0)); 4336 // Vn 4337 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4338 // Vm 4339 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4340 // pred 4341 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4342 } 4343 4344 void ARMAsmParser:: 4345 cvtVSTwbFixed(MCInst &Inst, 4346 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4347 // Create a writeback register dummy placeholder. 4348 Inst.addOperand(MCOperand::CreateImm(0)); 4349 // Vn 4350 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4351 // Vt 4352 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4353 // pred 4354 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4355 } 4356 4357 void ARMAsmParser:: 4358 cvtVSTwbRegister(MCInst &Inst, 4359 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4360 // Create a writeback register dummy placeholder. 4361 Inst.addOperand(MCOperand::CreateImm(0)); 4362 // Vn 4363 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4364 // Vm 4365 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4366 // Vt 4367 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4368 // pred 4369 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4370 } 4371 4372 /// Parse an ARM memory expression, return false if successful else return true 4373 /// or an error. The first token must be a '[' when called. 4374 bool ARMAsmParser:: 4375 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4376 SMLoc S, E; 4377 assert(Parser.getTok().is(AsmToken::LBrac) && 4378 "Token is not a Left Bracket"); 4379 S = Parser.getTok().getLoc(); 4380 Parser.Lex(); // Eat left bracket token. 4381 4382 const AsmToken &BaseRegTok = Parser.getTok(); 4383 int BaseRegNum = tryParseRegister(); 4384 if (BaseRegNum == -1) 4385 return Error(BaseRegTok.getLoc(), "register expected"); 4386 4387 // The next token must either be a comma, a colon or a closing bracket. 4388 const AsmToken &Tok = Parser.getTok(); 4389 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 4390 !Tok.is(AsmToken::RBrac)) 4391 return Error(Tok.getLoc(), "malformed memory operand"); 4392 4393 if (Tok.is(AsmToken::RBrac)) { 4394 E = Tok.getEndLoc(); 4395 Parser.Lex(); // Eat right bracket token. 4396 4397 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4398 0, 0, false, S, E)); 4399 4400 // If there's a pre-indexing writeback marker, '!', just add it as a token 4401 // operand. It's rather odd, but syntactically valid. 4402 if (Parser.getTok().is(AsmToken::Exclaim)) { 4403 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4404 Parser.Lex(); // Eat the '!'. 4405 } 4406 4407 return false; 4408 } 4409 4410 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 4411 "Lost colon or comma in memory operand?!"); 4412 if (Tok.is(AsmToken::Comma)) { 4413 Parser.Lex(); // Eat the comma. 4414 } 4415 4416 // If we have a ':', it's an alignment specifier. 4417 if (Parser.getTok().is(AsmToken::Colon)) { 4418 Parser.Lex(); // Eat the ':'. 4419 E = Parser.getTok().getLoc(); 4420 4421 const MCExpr *Expr; 4422 if (getParser().parseExpression(Expr)) 4423 return true; 4424 4425 // The expression has to be a constant. Memory references with relocations 4426 // don't come through here, as they use the <label> forms of the relevant 4427 // instructions. 4428 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4429 if (!CE) 4430 return Error (E, "constant expression expected"); 4431 4432 unsigned Align = 0; 4433 switch (CE->getValue()) { 4434 default: 4435 return Error(E, 4436 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4437 case 16: Align = 2; break; 4438 case 32: Align = 4; break; 4439 case 64: Align = 8; break; 4440 case 128: Align = 16; break; 4441 case 256: Align = 32; break; 4442 } 4443 4444 // Now we should have the closing ']' 4445 if (Parser.getTok().isNot(AsmToken::RBrac)) 4446 return Error(Parser.getTok().getLoc(), "']' expected"); 4447 E = Parser.getTok().getEndLoc(); 4448 Parser.Lex(); // Eat right bracket token. 4449 4450 // Don't worry about range checking the value here. That's handled by 4451 // the is*() predicates. 4452 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4453 ARM_AM::no_shift, 0, Align, 4454 false, S, E)); 4455 4456 // If there's a pre-indexing writeback marker, '!', just add it as a token 4457 // operand. 4458 if (Parser.getTok().is(AsmToken::Exclaim)) { 4459 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4460 Parser.Lex(); // Eat the '!'. 4461 } 4462 4463 return false; 4464 } 4465 4466 // If we have a '#', it's an immediate offset, else assume it's a register 4467 // offset. Be friendly and also accept a plain integer (without a leading 4468 // hash) for gas compatibility. 4469 if (Parser.getTok().is(AsmToken::Hash) || 4470 Parser.getTok().is(AsmToken::Dollar) || 4471 Parser.getTok().is(AsmToken::Integer)) { 4472 if (Parser.getTok().isNot(AsmToken::Integer)) 4473 Parser.Lex(); // Eat '#' or '$'. 4474 E = Parser.getTok().getLoc(); 4475 4476 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4477 const MCExpr *Offset; 4478 if (getParser().parseExpression(Offset)) 4479 return true; 4480 4481 // The expression has to be a constant. Memory references with relocations 4482 // don't come through here, as they use the <label> forms of the relevant 4483 // instructions. 4484 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4485 if (!CE) 4486 return Error (E, "constant expression expected"); 4487 4488 // If the constant was #-0, represent it as INT32_MIN. 4489 int32_t Val = CE->getValue(); 4490 if (isNegative && Val == 0) 4491 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4492 4493 // Now we should have the closing ']' 4494 if (Parser.getTok().isNot(AsmToken::RBrac)) 4495 return Error(Parser.getTok().getLoc(), "']' expected"); 4496 E = Parser.getTok().getEndLoc(); 4497 Parser.Lex(); // Eat right bracket token. 4498 4499 // Don't worry about range checking the value here. That's handled by 4500 // the is*() predicates. 4501 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4502 ARM_AM::no_shift, 0, 0, 4503 false, S, E)); 4504 4505 // If there's a pre-indexing writeback marker, '!', just add it as a token 4506 // operand. 4507 if (Parser.getTok().is(AsmToken::Exclaim)) { 4508 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4509 Parser.Lex(); // Eat the '!'. 4510 } 4511 4512 return false; 4513 } 4514 4515 // The register offset is optionally preceded by a '+' or '-' 4516 bool isNegative = false; 4517 if (Parser.getTok().is(AsmToken::Minus)) { 4518 isNegative = true; 4519 Parser.Lex(); // Eat the '-'. 4520 } else if (Parser.getTok().is(AsmToken::Plus)) { 4521 // Nothing to do. 4522 Parser.Lex(); // Eat the '+'. 4523 } 4524 4525 E = Parser.getTok().getLoc(); 4526 int OffsetRegNum = tryParseRegister(); 4527 if (OffsetRegNum == -1) 4528 return Error(E, "register expected"); 4529 4530 // If there's a shift operator, handle it. 4531 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4532 unsigned ShiftImm = 0; 4533 if (Parser.getTok().is(AsmToken::Comma)) { 4534 Parser.Lex(); // Eat the ','. 4535 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4536 return true; 4537 } 4538 4539 // Now we should have the closing ']' 4540 if (Parser.getTok().isNot(AsmToken::RBrac)) 4541 return Error(Parser.getTok().getLoc(), "']' expected"); 4542 E = Parser.getTok().getEndLoc(); 4543 Parser.Lex(); // Eat right bracket token. 4544 4545 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4546 ShiftType, ShiftImm, 0, isNegative, 4547 S, E)); 4548 4549 // If there's a pre-indexing writeback marker, '!', just add it as a token 4550 // operand. 4551 if (Parser.getTok().is(AsmToken::Exclaim)) { 4552 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4553 Parser.Lex(); // Eat the '!'. 4554 } 4555 4556 return false; 4557 } 4558 4559 /// parseMemRegOffsetShift - one of these two: 4560 /// ( lsl | lsr | asr | ror ) , # shift_amount 4561 /// rrx 4562 /// return true if it parses a shift otherwise it returns false. 4563 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4564 unsigned &Amount) { 4565 SMLoc Loc = Parser.getTok().getLoc(); 4566 const AsmToken &Tok = Parser.getTok(); 4567 if (Tok.isNot(AsmToken::Identifier)) 4568 return true; 4569 StringRef ShiftName = Tok.getString(); 4570 if (ShiftName == "lsl" || ShiftName == "LSL" || 4571 ShiftName == "asl" || ShiftName == "ASL") 4572 St = ARM_AM::lsl; 4573 else if (ShiftName == "lsr" || ShiftName == "LSR") 4574 St = ARM_AM::lsr; 4575 else if (ShiftName == "asr" || ShiftName == "ASR") 4576 St = ARM_AM::asr; 4577 else if (ShiftName == "ror" || ShiftName == "ROR") 4578 St = ARM_AM::ror; 4579 else if (ShiftName == "rrx" || ShiftName == "RRX") 4580 St = ARM_AM::rrx; 4581 else 4582 return Error(Loc, "illegal shift operator"); 4583 Parser.Lex(); // Eat shift type token. 4584 4585 // rrx stands alone. 4586 Amount = 0; 4587 if (St != ARM_AM::rrx) { 4588 Loc = Parser.getTok().getLoc(); 4589 // A '#' and a shift amount. 4590 const AsmToken &HashTok = Parser.getTok(); 4591 if (HashTok.isNot(AsmToken::Hash) && 4592 HashTok.isNot(AsmToken::Dollar)) 4593 return Error(HashTok.getLoc(), "'#' expected"); 4594 Parser.Lex(); // Eat hash token. 4595 4596 const MCExpr *Expr; 4597 if (getParser().parseExpression(Expr)) 4598 return true; 4599 // Range check the immediate. 4600 // lsl, ror: 0 <= imm <= 31 4601 // lsr, asr: 0 <= imm <= 32 4602 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4603 if (!CE) 4604 return Error(Loc, "shift amount must be an immediate"); 4605 int64_t Imm = CE->getValue(); 4606 if (Imm < 0 || 4607 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4608 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4609 return Error(Loc, "immediate shift value out of range"); 4610 // If <ShiftTy> #0, turn it into a no_shift. 4611 if (Imm == 0) 4612 St = ARM_AM::lsl; 4613 // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 4614 if (Imm == 32) 4615 Imm = 0; 4616 Amount = Imm; 4617 } 4618 4619 return false; 4620 } 4621 4622 /// parseFPImm - A floating point immediate expression operand. 4623 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4624 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4625 // Anything that can accept a floating point constant as an operand 4626 // needs to go through here, as the regular parseExpression is 4627 // integer only. 4628 // 4629 // This routine still creates a generic Immediate operand, containing 4630 // a bitcast of the 64-bit floating point value. The various operands 4631 // that accept floats can check whether the value is valid for them 4632 // via the standard is*() predicates. 4633 4634 SMLoc S = Parser.getTok().getLoc(); 4635 4636 if (Parser.getTok().isNot(AsmToken::Hash) && 4637 Parser.getTok().isNot(AsmToken::Dollar)) 4638 return MatchOperand_NoMatch; 4639 4640 // Disambiguate the VMOV forms that can accept an FP immediate. 4641 // vmov.f32 <sreg>, #imm 4642 // vmov.f64 <dreg>, #imm 4643 // vmov.f32 <dreg>, #imm @ vector f32x2 4644 // vmov.f32 <qreg>, #imm @ vector f32x4 4645 // 4646 // There are also the NEON VMOV instructions which expect an 4647 // integer constant. Make sure we don't try to parse an FPImm 4648 // for these: 4649 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4650 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4651 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 4652 TyOp->getToken() != ".f64")) 4653 return MatchOperand_NoMatch; 4654 4655 Parser.Lex(); // Eat '#' or '$'. 4656 4657 // Handle negation, as that still comes through as a separate token. 4658 bool isNegative = false; 4659 if (Parser.getTok().is(AsmToken::Minus)) { 4660 isNegative = true; 4661 Parser.Lex(); 4662 } 4663 const AsmToken &Tok = Parser.getTok(); 4664 SMLoc Loc = Tok.getLoc(); 4665 if (Tok.is(AsmToken::Real)) { 4666 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4667 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4668 // If we had a '-' in front, toggle the sign bit. 4669 IntVal ^= (uint64_t)isNegative << 31; 4670 Parser.Lex(); // Eat the token. 4671 Operands.push_back(ARMOperand::CreateImm( 4672 MCConstantExpr::Create(IntVal, getContext()), 4673 S, Parser.getTok().getLoc())); 4674 return MatchOperand_Success; 4675 } 4676 // Also handle plain integers. Instructions which allow floating point 4677 // immediates also allow a raw encoded 8-bit value. 4678 if (Tok.is(AsmToken::Integer)) { 4679 int64_t Val = Tok.getIntVal(); 4680 Parser.Lex(); // Eat the token. 4681 if (Val > 255 || Val < 0) { 4682 Error(Loc, "encoded floating point value out of range"); 4683 return MatchOperand_ParseFail; 4684 } 4685 double RealVal = ARM_AM::getFPImmFloat(Val); 4686 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 4687 Operands.push_back(ARMOperand::CreateImm( 4688 MCConstantExpr::Create(Val, getContext()), S, 4689 Parser.getTok().getLoc())); 4690 return MatchOperand_Success; 4691 } 4692 4693 Error(Loc, "invalid floating point immediate"); 4694 return MatchOperand_ParseFail; 4695 } 4696 4697 /// Parse a arm instruction operand. For now this parses the operand regardless 4698 /// of the mnemonic. 4699 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4700 StringRef Mnemonic) { 4701 SMLoc S, E; 4702 4703 // Check if the current operand has a custom associated parser, if so, try to 4704 // custom parse the operand, or fallback to the general approach. 4705 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4706 if (ResTy == MatchOperand_Success) 4707 return false; 4708 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4709 // there was a match, but an error occurred, in which case, just return that 4710 // the operand parsing failed. 4711 if (ResTy == MatchOperand_ParseFail) 4712 return true; 4713 4714 switch (getLexer().getKind()) { 4715 default: 4716 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4717 return true; 4718 case AsmToken::Identifier: { 4719 // If we've seen a branch mnemonic, the next operand must be a label. This 4720 // is true even if the label is a register name. So "br r1" means branch to 4721 // label "r1". 4722 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 4723 if (!ExpectLabel) { 4724 if (!tryParseRegisterWithWriteBack(Operands)) 4725 return false; 4726 int Res = tryParseShiftRegister(Operands); 4727 if (Res == 0) // success 4728 return false; 4729 else if (Res == -1) // irrecoverable error 4730 return true; 4731 // If this is VMRS, check for the apsr_nzcv operand. 4732 if (Mnemonic == "vmrs" && 4733 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4734 S = Parser.getTok().getLoc(); 4735 Parser.Lex(); 4736 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4737 return false; 4738 } 4739 } 4740 4741 // Fall though for the Identifier case that is not a register or a 4742 // special name. 4743 } 4744 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4745 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4746 case AsmToken::String: // quoted label names. 4747 case AsmToken::Dot: { // . as a branch target 4748 // This was not a register so parse other operands that start with an 4749 // identifier (like labels) as expressions and create them as immediates. 4750 const MCExpr *IdVal; 4751 S = Parser.getTok().getLoc(); 4752 if (getParser().parseExpression(IdVal)) 4753 return true; 4754 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4755 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4756 return false; 4757 } 4758 case AsmToken::LBrac: 4759 return parseMemory(Operands); 4760 case AsmToken::LCurly: 4761 return parseRegisterList(Operands); 4762 case AsmToken::Dollar: 4763 case AsmToken::Hash: { 4764 // #42 -> immediate. 4765 S = Parser.getTok().getLoc(); 4766 Parser.Lex(); 4767 4768 if (Parser.getTok().isNot(AsmToken::Colon)) { 4769 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4770 const MCExpr *ImmVal; 4771 if (getParser().parseExpression(ImmVal)) 4772 return true; 4773 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4774 if (CE) { 4775 int32_t Val = CE->getValue(); 4776 if (isNegative && Val == 0) 4777 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4778 } 4779 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4780 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4781 4782 // There can be a trailing '!' on operands that we want as a separate 4783 // '!' Token operand. Handle that here. For example, the compatibilty 4784 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 4785 if (Parser.getTok().is(AsmToken::Exclaim)) { 4786 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 4787 Parser.getTok().getLoc())); 4788 Parser.Lex(); // Eat exclaim token 4789 } 4790 return false; 4791 } 4792 // w/ a ':' after the '#', it's just like a plain ':'. 4793 // FALLTHROUGH 4794 } 4795 case AsmToken::Colon: { 4796 // ":lower16:" and ":upper16:" expression prefixes 4797 // FIXME: Check it's an expression prefix, 4798 // e.g. (FOO - :lower16:BAR) isn't legal. 4799 ARMMCExpr::VariantKind RefKind; 4800 if (parsePrefix(RefKind)) 4801 return true; 4802 4803 const MCExpr *SubExprVal; 4804 if (getParser().parseExpression(SubExprVal)) 4805 return true; 4806 4807 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4808 getContext()); 4809 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4810 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4811 return false; 4812 } 4813 } 4814 } 4815 4816 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4817 // :lower16: and :upper16:. 4818 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4819 RefKind = ARMMCExpr::VK_ARM_None; 4820 4821 // :lower16: and :upper16: modifiers 4822 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4823 Parser.Lex(); // Eat ':' 4824 4825 if (getLexer().isNot(AsmToken::Identifier)) { 4826 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4827 return true; 4828 } 4829 4830 StringRef IDVal = Parser.getTok().getIdentifier(); 4831 if (IDVal == "lower16") { 4832 RefKind = ARMMCExpr::VK_ARM_LO16; 4833 } else if (IDVal == "upper16") { 4834 RefKind = ARMMCExpr::VK_ARM_HI16; 4835 } else { 4836 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4837 return true; 4838 } 4839 Parser.Lex(); 4840 4841 if (getLexer().isNot(AsmToken::Colon)) { 4842 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4843 return true; 4844 } 4845 Parser.Lex(); // Eat the last ':' 4846 return false; 4847 } 4848 4849 /// \brief Given a mnemonic, split out possible predication code and carry 4850 /// setting letters to form a canonical mnemonic and flags. 4851 // 4852 // FIXME: Would be nice to autogen this. 4853 // FIXME: This is a bit of a maze of special cases. 4854 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4855 unsigned &PredicationCode, 4856 bool &CarrySetting, 4857 unsigned &ProcessorIMod, 4858 StringRef &ITMask) { 4859 PredicationCode = ARMCC::AL; 4860 CarrySetting = false; 4861 ProcessorIMod = 0; 4862 4863 // Ignore some mnemonics we know aren't predicated forms. 4864 // 4865 // FIXME: Would be nice to autogen this. 4866 if ((Mnemonic == "movs" && isThumb()) || 4867 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4868 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4869 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4870 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4871 Mnemonic == "vaclt" || Mnemonic == "vacle" || 4872 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4873 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4874 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4875 Mnemonic == "fmuls") 4876 return Mnemonic; 4877 4878 // First, split out any predication code. Ignore mnemonics we know aren't 4879 // predicated but do have a carry-set and so weren't caught above. 4880 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4881 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4882 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4883 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4884 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4885 .Case("eq", ARMCC::EQ) 4886 .Case("ne", ARMCC::NE) 4887 .Case("hs", ARMCC::HS) 4888 .Case("cs", ARMCC::HS) 4889 .Case("lo", ARMCC::LO) 4890 .Case("cc", ARMCC::LO) 4891 .Case("mi", ARMCC::MI) 4892 .Case("pl", ARMCC::PL) 4893 .Case("vs", ARMCC::VS) 4894 .Case("vc", ARMCC::VC) 4895 .Case("hi", ARMCC::HI) 4896 .Case("ls", ARMCC::LS) 4897 .Case("ge", ARMCC::GE) 4898 .Case("lt", ARMCC::LT) 4899 .Case("gt", ARMCC::GT) 4900 .Case("le", ARMCC::LE) 4901 .Case("al", ARMCC::AL) 4902 .Default(~0U); 4903 if (CC != ~0U) { 4904 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4905 PredicationCode = CC; 4906 } 4907 } 4908 4909 // Next, determine if we have a carry setting bit. We explicitly ignore all 4910 // the instructions we know end in 's'. 4911 if (Mnemonic.endswith("s") && 4912 !(Mnemonic == "cps" || Mnemonic == "mls" || 4913 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4914 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4915 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4916 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4917 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4918 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4919 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4920 Mnemonic == "vfms" || Mnemonic == "vfnms" || 4921 (Mnemonic == "movs" && isThumb()))) { 4922 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4923 CarrySetting = true; 4924 } 4925 4926 // The "cps" instruction can have a interrupt mode operand which is glued into 4927 // the mnemonic. Check if this is the case, split it and parse the imod op 4928 if (Mnemonic.startswith("cps")) { 4929 // Split out any imod code. 4930 unsigned IMod = 4931 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4932 .Case("ie", ARM_PROC::IE) 4933 .Case("id", ARM_PROC::ID) 4934 .Default(~0U); 4935 if (IMod != ~0U) { 4936 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4937 ProcessorIMod = IMod; 4938 } 4939 } 4940 4941 // The "it" instruction has the condition mask on the end of the mnemonic. 4942 if (Mnemonic.startswith("it")) { 4943 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4944 Mnemonic = Mnemonic.slice(0, 2); 4945 } 4946 4947 return Mnemonic; 4948 } 4949 4950 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 4951 /// inclusion of carry set or predication code operands. 4952 // 4953 // FIXME: It would be nice to autogen this. 4954 void ARMAsmParser:: 4955 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4956 bool &CanAcceptPredicationCode) { 4957 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4958 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4959 Mnemonic == "add" || Mnemonic == "adc" || 4960 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4961 Mnemonic == "orr" || Mnemonic == "mvn" || 4962 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4963 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4964 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4965 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4966 Mnemonic == "mla" || Mnemonic == "smlal" || 4967 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4968 CanAcceptCarrySet = true; 4969 } else 4970 CanAcceptCarrySet = false; 4971 4972 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || 4973 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || 4974 Mnemonic == "trap" || Mnemonic == "setend" || 4975 Mnemonic.startswith("cps")) { 4976 // These mnemonics are never predicable 4977 CanAcceptPredicationCode = false; 4978 } else if (!isThumb()) { 4979 // Some instructions are only predicable in Thumb mode 4980 CanAcceptPredicationCode 4981 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && 4982 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && 4983 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" && 4984 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" && 4985 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && 4986 Mnemonic != "stc2" && Mnemonic != "stc2l" && 4987 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs"); 4988 } else if (isThumbOne()) { 4989 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; 4990 } else 4991 CanAcceptPredicationCode = true; 4992 } 4993 4994 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4995 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4996 // FIXME: This is all horribly hacky. We really need a better way to deal 4997 // with optional operands like this in the matcher table. 4998 4999 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 5000 // another does not. Specifically, the MOVW instruction does not. So we 5001 // special case it here and remove the defaulted (non-setting) cc_out 5002 // operand if that's the instruction we're trying to match. 5003 // 5004 // We do this as post-processing of the explicit operands rather than just 5005 // conditionally adding the cc_out in the first place because we need 5006 // to check the type of the parsed immediate operand. 5007 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 5008 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 5009 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 5010 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 5011 return true; 5012 5013 // Register-register 'add' for thumb does not have a cc_out operand 5014 // when there are only two register operands. 5015 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 5016 static_cast<ARMOperand*>(Operands[3])->isReg() && 5017 static_cast<ARMOperand*>(Operands[4])->isReg() && 5018 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 5019 return true; 5020 // Register-register 'add' for thumb does not have a cc_out operand 5021 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 5022 // have to check the immediate range here since Thumb2 has a variant 5023 // that can handle a different range and has a cc_out operand. 5024 if (((isThumb() && Mnemonic == "add") || 5025 (isThumbTwo() && Mnemonic == "sub")) && 5026 Operands.size() == 6 && 5027 static_cast<ARMOperand*>(Operands[3])->isReg() && 5028 static_cast<ARMOperand*>(Operands[4])->isReg() && 5029 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 5030 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5031 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 5032 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 5033 return true; 5034 // For Thumb2, add/sub immediate does not have a cc_out operand for the 5035 // imm0_4095 variant. That's the least-preferred variant when 5036 // selecting via the generic "add" mnemonic, so to know that we 5037 // should remove the cc_out operand, we have to explicitly check that 5038 // it's not one of the other variants. Ugh. 5039 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 5040 Operands.size() == 6 && 5041 static_cast<ARMOperand*>(Operands[3])->isReg() && 5042 static_cast<ARMOperand*>(Operands[4])->isReg() && 5043 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5044 // Nest conditions rather than one big 'if' statement for readability. 5045 // 5046 // If either register is a high reg, it's either one of the SP 5047 // variants (handled above) or a 32-bit encoding, so we just 5048 // check against T3. If the second register is the PC, this is an 5049 // alternate form of ADR, which uses encoding T4, so check for that too. 5050 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5051 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 5052 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 5053 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 5054 return false; 5055 // If both registers are low, we're in an IT block, and the immediate is 5056 // in range, we should use encoding T1 instead, which has a cc_out. 5057 if (inITBlock() && 5058 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 5059 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 5060 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 5061 return false; 5062 5063 // Otherwise, we use encoding T4, which does not have a cc_out 5064 // operand. 5065 return true; 5066 } 5067 5068 // The thumb2 multiply instruction doesn't have a CCOut register, so 5069 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 5070 // use the 16-bit encoding or not. 5071 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 5072 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5073 static_cast<ARMOperand*>(Operands[3])->isReg() && 5074 static_cast<ARMOperand*>(Operands[4])->isReg() && 5075 static_cast<ARMOperand*>(Operands[5])->isReg() && 5076 // If the registers aren't low regs, the destination reg isn't the 5077 // same as one of the source regs, or the cc_out operand is zero 5078 // outside of an IT block, we have to use the 32-bit encoding, so 5079 // remove the cc_out operand. 5080 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5081 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 5082 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 5083 !inITBlock() || 5084 (static_cast<ARMOperand*>(Operands[3])->getReg() != 5085 static_cast<ARMOperand*>(Operands[5])->getReg() && 5086 static_cast<ARMOperand*>(Operands[3])->getReg() != 5087 static_cast<ARMOperand*>(Operands[4])->getReg()))) 5088 return true; 5089 5090 // Also check the 'mul' syntax variant that doesn't specify an explicit 5091 // destination register. 5092 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 5093 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5094 static_cast<ARMOperand*>(Operands[3])->isReg() && 5095 static_cast<ARMOperand*>(Operands[4])->isReg() && 5096 // If the registers aren't low regs or the cc_out operand is zero 5097 // outside of an IT block, we have to use the 32-bit encoding, so 5098 // remove the cc_out operand. 5099 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5100 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 5101 !inITBlock())) 5102 return true; 5103 5104 5105 5106 // Register-register 'add/sub' for thumb does not have a cc_out operand 5107 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 5108 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 5109 // right, this will result in better diagnostics (which operand is off) 5110 // anyway. 5111 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 5112 (Operands.size() == 5 || Operands.size() == 6) && 5113 static_cast<ARMOperand*>(Operands[3])->isReg() && 5114 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 5115 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5116 (static_cast<ARMOperand*>(Operands[4])->isImm() || 5117 (Operands.size() == 6 && 5118 static_cast<ARMOperand*>(Operands[5])->isImm()))) 5119 return true; 5120 5121 return false; 5122 } 5123 5124 static bool isDataTypeToken(StringRef Tok) { 5125 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 5126 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 5127 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 5128 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 5129 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 5130 Tok == ".f" || Tok == ".d"; 5131 } 5132 5133 // FIXME: This bit should probably be handled via an explicit match class 5134 // in the .td files that matches the suffix instead of having it be 5135 // a literal string token the way it is now. 5136 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 5137 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 5138 } 5139 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, 5140 unsigned VariantID); 5141 /// Parse an arm instruction mnemonic followed by its operands. 5142 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 5143 SMLoc NameLoc, 5144 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5145 // Apply mnemonic aliases before doing anything else, as the destination 5146 // mnemnonic may include suffices and we want to handle them normally. 5147 // The generic tblgen'erated code does this later, at the start of 5148 // MatchInstructionImpl(), but that's too late for aliases that include 5149 // any sort of suffix. 5150 unsigned AvailableFeatures = getAvailableFeatures(); 5151 unsigned AssemblerDialect = getParser().getAssemblerDialect(); 5152 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 5153 5154 // First check for the ARM-specific .req directive. 5155 if (Parser.getTok().is(AsmToken::Identifier) && 5156 Parser.getTok().getIdentifier() == ".req") { 5157 parseDirectiveReq(Name, NameLoc); 5158 // We always return 'error' for this, as we're done with this 5159 // statement and don't need to match the 'instruction." 5160 return true; 5161 } 5162 5163 // Create the leading tokens for the mnemonic, split by '.' characters. 5164 size_t Start = 0, Next = Name.find('.'); 5165 StringRef Mnemonic = Name.slice(Start, Next); 5166 5167 // Split out the predication code and carry setting flag from the mnemonic. 5168 unsigned PredicationCode; 5169 unsigned ProcessorIMod; 5170 bool CarrySetting; 5171 StringRef ITMask; 5172 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5173 ProcessorIMod, ITMask); 5174 5175 // In Thumb1, only the branch (B) instruction can be predicated. 5176 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 5177 Parser.eatToEndOfStatement(); 5178 return Error(NameLoc, "conditional execution not supported in Thumb1"); 5179 } 5180 5181 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5182 5183 // Handle the IT instruction ITMask. Convert it to a bitmask. This 5184 // is the mask as it will be for the IT encoding if the conditional 5185 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5186 // where the conditional bit0 is zero, the instruction post-processing 5187 // will adjust the mask accordingly. 5188 if (Mnemonic == "it") { 5189 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5190 if (ITMask.size() > 3) { 5191 Parser.eatToEndOfStatement(); 5192 return Error(Loc, "too many conditions on IT instruction"); 5193 } 5194 unsigned Mask = 8; 5195 for (unsigned i = ITMask.size(); i != 0; --i) { 5196 char pos = ITMask[i - 1]; 5197 if (pos != 't' && pos != 'e') { 5198 Parser.eatToEndOfStatement(); 5199 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5200 } 5201 Mask >>= 1; 5202 if (ITMask[i - 1] == 't') 5203 Mask |= 8; 5204 } 5205 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5206 } 5207 5208 // FIXME: This is all a pretty gross hack. We should automatically handle 5209 // optional operands like this via tblgen. 5210 5211 // Next, add the CCOut and ConditionCode operands, if needed. 5212 // 5213 // For mnemonics which can ever incorporate a carry setting bit or predication 5214 // code, our matching model involves us always generating CCOut and 5215 // ConditionCode operands to match the mnemonic "as written" and then we let 5216 // the matcher deal with finding the right instruction or generating an 5217 // appropriate error. 5218 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5219 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 5220 5221 // If we had a carry-set on an instruction that can't do that, issue an 5222 // error. 5223 if (!CanAcceptCarrySet && CarrySetting) { 5224 Parser.eatToEndOfStatement(); 5225 return Error(NameLoc, "instruction '" + Mnemonic + 5226 "' can not set flags, but 's' suffix specified"); 5227 } 5228 // If we had a predication code on an instruction that can't do that, issue an 5229 // error. 5230 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5231 Parser.eatToEndOfStatement(); 5232 return Error(NameLoc, "instruction '" + Mnemonic + 5233 "' is not predicable, but condition code specified"); 5234 } 5235 5236 // Add the carry setting operand, if necessary. 5237 if (CanAcceptCarrySet) { 5238 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5239 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5240 Loc)); 5241 } 5242 5243 // Add the predication code operand, if necessary. 5244 if (CanAcceptPredicationCode) { 5245 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5246 CarrySetting); 5247 Operands.push_back(ARMOperand::CreateCondCode( 5248 ARMCC::CondCodes(PredicationCode), Loc)); 5249 } 5250 5251 // Add the processor imod operand, if necessary. 5252 if (ProcessorIMod) { 5253 Operands.push_back(ARMOperand::CreateImm( 5254 MCConstantExpr::Create(ProcessorIMod, getContext()), 5255 NameLoc, NameLoc)); 5256 } 5257 5258 // Add the remaining tokens in the mnemonic. 5259 while (Next != StringRef::npos) { 5260 Start = Next; 5261 Next = Name.find('.', Start + 1); 5262 StringRef ExtraToken = Name.slice(Start, Next); 5263 5264 // Some NEON instructions have an optional datatype suffix that is 5265 // completely ignored. Check for that. 5266 if (isDataTypeToken(ExtraToken) && 5267 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5268 continue; 5269 5270 // For for ARM mode generate an error if the .n qualifier is used. 5271 if (ExtraToken == ".n" && !isThumb()) { 5272 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5273 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 5274 "arm mode"); 5275 } 5276 5277 // The .n qualifier is always discarded as that is what the tables 5278 // and matcher expect. In ARM mode the .w qualifier has no effect, 5279 // so discard it to avoid errors that can be caused by the matcher. 5280 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { 5281 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5282 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5283 } 5284 } 5285 5286 // Read the remaining operands. 5287 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5288 // Read the first operand. 5289 if (parseOperand(Operands, Mnemonic)) { 5290 Parser.eatToEndOfStatement(); 5291 return true; 5292 } 5293 5294 while (getLexer().is(AsmToken::Comma)) { 5295 Parser.Lex(); // Eat the comma. 5296 5297 // Parse and remember the operand. 5298 if (parseOperand(Operands, Mnemonic)) { 5299 Parser.eatToEndOfStatement(); 5300 return true; 5301 } 5302 } 5303 } 5304 5305 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5306 SMLoc Loc = getLexer().getLoc(); 5307 Parser.eatToEndOfStatement(); 5308 return Error(Loc, "unexpected token in argument list"); 5309 } 5310 5311 Parser.Lex(); // Consume the EndOfStatement 5312 5313 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5314 // do and don't have a cc_out optional-def operand. With some spot-checks 5315 // of the operand list, we can figure out which variant we're trying to 5316 // parse and adjust accordingly before actually matching. We shouldn't ever 5317 // try to remove a cc_out operand that was explicitly set on the the 5318 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5319 // table driven matcher doesn't fit well with the ARM instruction set. 5320 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5321 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5322 Operands.erase(Operands.begin() + 1); 5323 delete Op; 5324 } 5325 5326 // ARM mode 'blx' need special handling, as the register operand version 5327 // is predicable, but the label operand version is not. So, we can't rely 5328 // on the Mnemonic based checking to correctly figure out when to put 5329 // a k_CondCode operand in the list. If we're trying to match the label 5330 // version, remove the k_CondCode operand here. 5331 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5332 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5333 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5334 Operands.erase(Operands.begin() + 1); 5335 delete Op; 5336 } 5337 5338 // Adjust operands of ldrexd/strexd to MCK_GPRPair. 5339 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 5340 // a single GPRPair reg operand is used in the .td file to replace the two 5341 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 5342 // expressed as a GPRPair, so we have to manually merge them. 5343 // FIXME: We would really like to be able to tablegen'erate this. 5344 if (!isThumb() && Operands.size() > 4 && 5345 (Mnemonic == "ldrexd" || Mnemonic == "strexd")) { 5346 bool isLoad = (Mnemonic == "ldrexd"); 5347 unsigned Idx = isLoad ? 2 : 3; 5348 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]); 5349 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]); 5350 5351 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 5352 // Adjust only if Op1 and Op2 are GPRs. 5353 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) && 5354 MRC.contains(Op2->getReg())) { 5355 unsigned Reg1 = Op1->getReg(); 5356 unsigned Reg2 = Op2->getReg(); 5357 unsigned Rt = MRI->getEncodingValue(Reg1); 5358 unsigned Rt2 = MRI->getEncodingValue(Reg2); 5359 5360 // Rt2 must be Rt + 1 and Rt must be even. 5361 if (Rt + 1 != Rt2 || (Rt & 1)) { 5362 Error(Op2->getStartLoc(), isLoad ? 5363 "destination operands must be sequential" : 5364 "source operands must be sequential"); 5365 return true; 5366 } 5367 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 5368 &(MRI->getRegClass(ARM::GPRPairRegClassID))); 5369 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2); 5370 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg( 5371 NewReg, Op1->getStartLoc(), Op2->getEndLoc())); 5372 delete Op1; 5373 delete Op2; 5374 } 5375 } 5376 5377 return false; 5378 } 5379 5380 // Validate context-sensitive operand constraints. 5381 5382 // return 'true' if register list contains non-low GPR registers, 5383 // 'false' otherwise. If Reg is in the register list or is HiReg, set 5384 // 'containsReg' to true. 5385 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5386 unsigned HiReg, bool &containsReg) { 5387 containsReg = false; 5388 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5389 unsigned OpReg = Inst.getOperand(i).getReg(); 5390 if (OpReg == Reg) 5391 containsReg = true; 5392 // Anything other than a low register isn't legal here. 5393 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5394 return true; 5395 } 5396 return false; 5397 } 5398 5399 // Check if the specified regisgter is in the register list of the inst, 5400 // starting at the indicated operand number. 5401 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5402 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5403 unsigned OpReg = Inst.getOperand(i).getReg(); 5404 if (OpReg == Reg) 5405 return true; 5406 } 5407 return false; 5408 } 5409 5410 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around 5411 // the ARMInsts array) instead. Getting that here requires awkward 5412 // API changes, though. Better way? 5413 namespace llvm { 5414 extern const MCInstrDesc ARMInsts[]; 5415 } 5416 static const MCInstrDesc &getInstDesc(unsigned Opcode) { 5417 return ARMInsts[Opcode]; 5418 } 5419 5420 // FIXME: We would really like to be able to tablegen'erate this. 5421 bool ARMAsmParser:: 5422 validateInstruction(MCInst &Inst, 5423 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5424 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5425 SMLoc Loc = Operands[0]->getStartLoc(); 5426 // Check the IT block state first. 5427 // NOTE: BKPT instruction has the interesting property of being 5428 // allowed in IT blocks, but not being predicable. It just always 5429 // executes. 5430 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && 5431 Inst.getOpcode() != ARM::BKPT) { 5432 unsigned bit = 1; 5433 if (ITState.FirstCond) 5434 ITState.FirstCond = false; 5435 else 5436 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5437 // The instruction must be predicable. 5438 if (!MCID.isPredicable()) 5439 return Error(Loc, "instructions in IT block must be predicable"); 5440 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5441 unsigned ITCond = bit ? ITState.Cond : 5442 ARMCC::getOppositeCondition(ITState.Cond); 5443 if (Cond != ITCond) { 5444 // Find the condition code Operand to get its SMLoc information. 5445 SMLoc CondLoc; 5446 for (unsigned i = 1; i < Operands.size(); ++i) 5447 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5448 CondLoc = Operands[i]->getStartLoc(); 5449 return Error(CondLoc, "incorrect condition in IT block; got '" + 5450 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5451 "', but expected '" + 5452 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5453 } 5454 // Check for non-'al' condition codes outside of the IT block. 5455 } else if (isThumbTwo() && MCID.isPredicable() && 5456 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5457 ARMCC::AL && Inst.getOpcode() != ARM::tB && 5458 Inst.getOpcode() != ARM::t2B) 5459 return Error(Loc, "predicated instructions must be in IT block"); 5460 5461 switch (Inst.getOpcode()) { 5462 case ARM::LDRD: 5463 case ARM::LDRD_PRE: 5464 case ARM::LDRD_POST: { 5465 // Rt2 must be Rt + 1. 5466 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5467 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5468 if (Rt2 != Rt + 1) 5469 return Error(Operands[3]->getStartLoc(), 5470 "destination operands must be sequential"); 5471 return false; 5472 } 5473 case ARM::STRD: { 5474 // Rt2 must be Rt + 1. 5475 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5476 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5477 if (Rt2 != Rt + 1) 5478 return Error(Operands[3]->getStartLoc(), 5479 "source operands must be sequential"); 5480 return false; 5481 } 5482 case ARM::STRD_PRE: 5483 case ARM::STRD_POST: { 5484 // Rt2 must be Rt + 1. 5485 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5486 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5487 if (Rt2 != Rt + 1) 5488 return Error(Operands[3]->getStartLoc(), 5489 "source operands must be sequential"); 5490 return false; 5491 } 5492 case ARM::SBFX: 5493 case ARM::UBFX: { 5494 // width must be in range [1, 32-lsb] 5495 unsigned lsb = Inst.getOperand(2).getImm(); 5496 unsigned widthm1 = Inst.getOperand(3).getImm(); 5497 if (widthm1 >= 32 - lsb) 5498 return Error(Operands[5]->getStartLoc(), 5499 "bitfield width must be in range [1,32-lsb]"); 5500 return false; 5501 } 5502 case ARM::tLDMIA: { 5503 // If we're parsing Thumb2, the .w variant is available and handles 5504 // most cases that are normally illegal for a Thumb1 LDM 5505 // instruction. We'll make the transformation in processInstruction() 5506 // if necessary. 5507 // 5508 // Thumb LDM instructions are writeback iff the base register is not 5509 // in the register list. 5510 unsigned Rn = Inst.getOperand(0).getReg(); 5511 bool hasWritebackToken = 5512 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5513 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5514 bool listContainsBase; 5515 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5516 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5517 "registers must be in range r0-r7"); 5518 // If we should have writeback, then there should be a '!' token. 5519 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 5520 return Error(Operands[2]->getStartLoc(), 5521 "writeback operator '!' expected"); 5522 // If we should not have writeback, there must not be a '!'. This is 5523 // true even for the 32-bit wide encodings. 5524 if (listContainsBase && hasWritebackToken) 5525 return Error(Operands[3]->getStartLoc(), 5526 "writeback operator '!' not allowed when base register " 5527 "in register list"); 5528 5529 break; 5530 } 5531 case ARM::t2LDMIA_UPD: { 5532 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5533 return Error(Operands[4]->getStartLoc(), 5534 "writeback operator '!' not allowed when base register " 5535 "in register list"); 5536 break; 5537 } 5538 case ARM::tMUL: { 5539 // The second source operand must be the same register as the destination 5540 // operand. 5541 // 5542 // In this case, we must directly check the parsed operands because the 5543 // cvtThumbMultiply() function is written in such a way that it guarantees 5544 // this first statement is always true for the new Inst. Essentially, the 5545 // destination is unconditionally copied into the second source operand 5546 // without checking to see if it matches what we actually parsed. 5547 if (Operands.size() == 6 && 5548 (((ARMOperand*)Operands[3])->getReg() != 5549 ((ARMOperand*)Operands[5])->getReg()) && 5550 (((ARMOperand*)Operands[3])->getReg() != 5551 ((ARMOperand*)Operands[4])->getReg())) { 5552 return Error(Operands[3]->getStartLoc(), 5553 "destination register must match source register"); 5554 } 5555 break; 5556 } 5557 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5558 // so only issue a diagnostic for thumb1. The instructions will be 5559 // switched to the t2 encodings in processInstruction() if necessary. 5560 case ARM::tPOP: { 5561 bool listContainsBase; 5562 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 5563 !isThumbTwo()) 5564 return Error(Operands[2]->getStartLoc(), 5565 "registers must be in range r0-r7 or pc"); 5566 break; 5567 } 5568 case ARM::tPUSH: { 5569 bool listContainsBase; 5570 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 5571 !isThumbTwo()) 5572 return Error(Operands[2]->getStartLoc(), 5573 "registers must be in range r0-r7 or lr"); 5574 break; 5575 } 5576 case ARM::tSTMIA_UPD: { 5577 bool listContainsBase; 5578 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 5579 return Error(Operands[4]->getStartLoc(), 5580 "registers must be in range r0-r7"); 5581 break; 5582 } 5583 case ARM::tADDrSP: { 5584 // If the non-SP source operand and the destination operand are not the 5585 // same, we need thumb2 (for the wide encoding), or we have an error. 5586 if (!isThumbTwo() && 5587 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5588 return Error(Operands[4]->getStartLoc(), 5589 "source register must be the same as destination"); 5590 } 5591 break; 5592 } 5593 } 5594 5595 return false; 5596 } 5597 5598 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5599 switch(Opc) { 5600 default: llvm_unreachable("unexpected opcode!"); 5601 // VST1LN 5602 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5603 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5604 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5605 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5606 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5607 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5608 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5609 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5610 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5611 5612 // VST2LN 5613 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5614 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5615 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5616 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5617 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5618 5619 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5620 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5621 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5622 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5623 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5624 5625 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5626 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5627 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5628 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5629 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5630 5631 // VST3LN 5632 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5633 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5634 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5635 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5636 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5637 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5638 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5639 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5640 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5641 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5642 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5643 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5644 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5645 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5646 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5647 5648 // VST3 5649 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5650 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5651 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5652 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5653 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5654 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5655 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5656 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5657 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5658 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5659 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5660 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5661 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5662 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5663 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5664 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5665 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5666 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5667 5668 // VST4LN 5669 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5670 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5671 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5672 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5673 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5674 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5675 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5676 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5677 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5678 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5679 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5680 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5681 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5682 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5683 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5684 5685 // VST4 5686 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5687 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5688 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5689 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5690 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5691 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5692 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5693 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5694 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5695 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5696 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5697 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5698 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5699 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5700 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5701 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5702 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5703 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5704 } 5705 } 5706 5707 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5708 switch(Opc) { 5709 default: llvm_unreachable("unexpected opcode!"); 5710 // VLD1LN 5711 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5712 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5713 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5714 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5715 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5716 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5717 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5718 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5719 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5720 5721 // VLD2LN 5722 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5723 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5724 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5725 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5726 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5727 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5728 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5729 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5730 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5731 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5732 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5733 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5734 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5735 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5736 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5737 5738 // VLD3DUP 5739 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5740 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5741 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5742 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5743 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5744 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5745 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5746 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5747 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5748 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5749 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5750 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5751 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5752 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5753 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5754 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5755 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5756 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5757 5758 // VLD3LN 5759 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5760 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5761 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5762 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5763 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5764 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5765 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5766 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5767 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5768 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5769 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5770 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5771 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5772 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5773 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5774 5775 // VLD3 5776 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5777 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5778 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5779 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5780 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5781 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5782 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5783 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5784 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5785 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5786 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5787 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5788 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5789 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5790 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5791 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5792 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5793 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5794 5795 // VLD4LN 5796 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5797 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5798 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5799 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5800 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5801 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5802 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5803 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5804 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5805 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5806 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5807 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5808 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5809 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5810 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5811 5812 // VLD4DUP 5813 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5814 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5815 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5816 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5817 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5818 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5819 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5820 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5821 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5822 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5823 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5824 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5825 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5826 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5827 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5828 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5829 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5830 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5831 5832 // VLD4 5833 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5834 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5835 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5836 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5837 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5838 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5839 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5840 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5841 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5842 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5843 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5844 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5845 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 5846 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 5847 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 5848 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 5849 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 5850 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 5851 } 5852 } 5853 5854 bool ARMAsmParser:: 5855 processInstruction(MCInst &Inst, 5856 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5857 switch (Inst.getOpcode()) { 5858 // Alias for alternate form of 'ADR Rd, #imm' instruction. 5859 case ARM::ADDri: { 5860 if (Inst.getOperand(1).getReg() != ARM::PC || 5861 Inst.getOperand(5).getReg() != 0) 5862 return false; 5863 MCInst TmpInst; 5864 TmpInst.setOpcode(ARM::ADR); 5865 TmpInst.addOperand(Inst.getOperand(0)); 5866 TmpInst.addOperand(Inst.getOperand(2)); 5867 TmpInst.addOperand(Inst.getOperand(3)); 5868 TmpInst.addOperand(Inst.getOperand(4)); 5869 Inst = TmpInst; 5870 return true; 5871 } 5872 // Aliases for alternate PC+imm syntax of LDR instructions. 5873 case ARM::t2LDRpcrel: 5874 // Select the narrow version if the immediate will fit. 5875 if (Inst.getOperand(1).getImm() > 0 && 5876 Inst.getOperand(1).getImm() <= 0xff && 5877 !(static_cast<ARMOperand*>(Operands[2])->isToken() && 5878 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w")) 5879 Inst.setOpcode(ARM::tLDRpci); 5880 else 5881 Inst.setOpcode(ARM::t2LDRpci); 5882 return true; 5883 case ARM::t2LDRBpcrel: 5884 Inst.setOpcode(ARM::t2LDRBpci); 5885 return true; 5886 case ARM::t2LDRHpcrel: 5887 Inst.setOpcode(ARM::t2LDRHpci); 5888 return true; 5889 case ARM::t2LDRSBpcrel: 5890 Inst.setOpcode(ARM::t2LDRSBpci); 5891 return true; 5892 case ARM::t2LDRSHpcrel: 5893 Inst.setOpcode(ARM::t2LDRSHpci); 5894 return true; 5895 // Handle NEON VST complex aliases. 5896 case ARM::VST1LNdWB_register_Asm_8: 5897 case ARM::VST1LNdWB_register_Asm_16: 5898 case ARM::VST1LNdWB_register_Asm_32: { 5899 MCInst TmpInst; 5900 // Shuffle the operands around so the lane index operand is in the 5901 // right place. 5902 unsigned Spacing; 5903 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5904 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5905 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5906 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5907 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5908 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5909 TmpInst.addOperand(Inst.getOperand(1)); // lane 5910 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5911 TmpInst.addOperand(Inst.getOperand(6)); 5912 Inst = TmpInst; 5913 return true; 5914 } 5915 5916 case ARM::VST2LNdWB_register_Asm_8: 5917 case ARM::VST2LNdWB_register_Asm_16: 5918 case ARM::VST2LNdWB_register_Asm_32: 5919 case ARM::VST2LNqWB_register_Asm_16: 5920 case ARM::VST2LNqWB_register_Asm_32: { 5921 MCInst TmpInst; 5922 // Shuffle the operands around so the lane index operand is in the 5923 // right place. 5924 unsigned Spacing; 5925 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5926 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5927 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5928 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5929 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5930 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5931 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5932 Spacing)); 5933 TmpInst.addOperand(Inst.getOperand(1)); // lane 5934 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5935 TmpInst.addOperand(Inst.getOperand(6)); 5936 Inst = TmpInst; 5937 return true; 5938 } 5939 5940 case ARM::VST3LNdWB_register_Asm_8: 5941 case ARM::VST3LNdWB_register_Asm_16: 5942 case ARM::VST3LNdWB_register_Asm_32: 5943 case ARM::VST3LNqWB_register_Asm_16: 5944 case ARM::VST3LNqWB_register_Asm_32: { 5945 MCInst TmpInst; 5946 // Shuffle the operands around so the lane index operand is in the 5947 // right place. 5948 unsigned Spacing; 5949 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5950 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5951 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5952 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5953 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5954 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5955 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5956 Spacing)); 5957 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5958 Spacing * 2)); 5959 TmpInst.addOperand(Inst.getOperand(1)); // lane 5960 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5961 TmpInst.addOperand(Inst.getOperand(6)); 5962 Inst = TmpInst; 5963 return true; 5964 } 5965 5966 case ARM::VST4LNdWB_register_Asm_8: 5967 case ARM::VST4LNdWB_register_Asm_16: 5968 case ARM::VST4LNdWB_register_Asm_32: 5969 case ARM::VST4LNqWB_register_Asm_16: 5970 case ARM::VST4LNqWB_register_Asm_32: { 5971 MCInst TmpInst; 5972 // Shuffle the operands around so the lane index operand is in the 5973 // right place. 5974 unsigned Spacing; 5975 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5976 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5977 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5978 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5979 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5980 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5981 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5982 Spacing)); 5983 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5984 Spacing * 2)); 5985 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5986 Spacing * 3)); 5987 TmpInst.addOperand(Inst.getOperand(1)); // lane 5988 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5989 TmpInst.addOperand(Inst.getOperand(6)); 5990 Inst = TmpInst; 5991 return true; 5992 } 5993 5994 case ARM::VST1LNdWB_fixed_Asm_8: 5995 case ARM::VST1LNdWB_fixed_Asm_16: 5996 case ARM::VST1LNdWB_fixed_Asm_32: { 5997 MCInst TmpInst; 5998 // Shuffle the operands around so the lane index operand is in the 5999 // right place. 6000 unsigned Spacing; 6001 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6002 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6003 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6004 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6005 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6006 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6007 TmpInst.addOperand(Inst.getOperand(1)); // lane 6008 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6009 TmpInst.addOperand(Inst.getOperand(5)); 6010 Inst = TmpInst; 6011 return true; 6012 } 6013 6014 case ARM::VST2LNdWB_fixed_Asm_8: 6015 case ARM::VST2LNdWB_fixed_Asm_16: 6016 case ARM::VST2LNdWB_fixed_Asm_32: 6017 case ARM::VST2LNqWB_fixed_Asm_16: 6018 case ARM::VST2LNqWB_fixed_Asm_32: { 6019 MCInst TmpInst; 6020 // Shuffle the operands around so the lane index operand is in the 6021 // right place. 6022 unsigned Spacing; 6023 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6024 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6025 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6026 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6027 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6028 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6029 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6030 Spacing)); 6031 TmpInst.addOperand(Inst.getOperand(1)); // lane 6032 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6033 TmpInst.addOperand(Inst.getOperand(5)); 6034 Inst = TmpInst; 6035 return true; 6036 } 6037 6038 case ARM::VST3LNdWB_fixed_Asm_8: 6039 case ARM::VST3LNdWB_fixed_Asm_16: 6040 case ARM::VST3LNdWB_fixed_Asm_32: 6041 case ARM::VST3LNqWB_fixed_Asm_16: 6042 case ARM::VST3LNqWB_fixed_Asm_32: { 6043 MCInst TmpInst; 6044 // Shuffle the operands around so the lane index operand is in the 6045 // right place. 6046 unsigned Spacing; 6047 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6048 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6049 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6050 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6051 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6052 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6053 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6054 Spacing)); 6055 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6056 Spacing * 2)); 6057 TmpInst.addOperand(Inst.getOperand(1)); // lane 6058 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6059 TmpInst.addOperand(Inst.getOperand(5)); 6060 Inst = TmpInst; 6061 return true; 6062 } 6063 6064 case ARM::VST4LNdWB_fixed_Asm_8: 6065 case ARM::VST4LNdWB_fixed_Asm_16: 6066 case ARM::VST4LNdWB_fixed_Asm_32: 6067 case ARM::VST4LNqWB_fixed_Asm_16: 6068 case ARM::VST4LNqWB_fixed_Asm_32: { 6069 MCInst TmpInst; 6070 // Shuffle the operands around so the lane index operand is in the 6071 // right place. 6072 unsigned Spacing; 6073 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6074 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6075 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6076 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6077 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6078 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6079 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6080 Spacing)); 6081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6082 Spacing * 2)); 6083 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6084 Spacing * 3)); 6085 TmpInst.addOperand(Inst.getOperand(1)); // lane 6086 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6087 TmpInst.addOperand(Inst.getOperand(5)); 6088 Inst = TmpInst; 6089 return true; 6090 } 6091 6092 case ARM::VST1LNdAsm_8: 6093 case ARM::VST1LNdAsm_16: 6094 case ARM::VST1LNdAsm_32: { 6095 MCInst TmpInst; 6096 // Shuffle the operands around so the lane index operand is in the 6097 // right place. 6098 unsigned Spacing; 6099 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6100 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6101 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6102 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6103 TmpInst.addOperand(Inst.getOperand(1)); // lane 6104 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6105 TmpInst.addOperand(Inst.getOperand(5)); 6106 Inst = TmpInst; 6107 return true; 6108 } 6109 6110 case ARM::VST2LNdAsm_8: 6111 case ARM::VST2LNdAsm_16: 6112 case ARM::VST2LNdAsm_32: 6113 case ARM::VST2LNqAsm_16: 6114 case ARM::VST2LNqAsm_32: { 6115 MCInst TmpInst; 6116 // Shuffle the operands around so the lane index operand is in the 6117 // right place. 6118 unsigned Spacing; 6119 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6120 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6121 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6122 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6123 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6124 Spacing)); 6125 TmpInst.addOperand(Inst.getOperand(1)); // lane 6126 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6127 TmpInst.addOperand(Inst.getOperand(5)); 6128 Inst = TmpInst; 6129 return true; 6130 } 6131 6132 case ARM::VST3LNdAsm_8: 6133 case ARM::VST3LNdAsm_16: 6134 case ARM::VST3LNdAsm_32: 6135 case ARM::VST3LNqAsm_16: 6136 case ARM::VST3LNqAsm_32: { 6137 MCInst TmpInst; 6138 // Shuffle the operands around so the lane index operand is in the 6139 // right place. 6140 unsigned Spacing; 6141 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6142 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6143 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6144 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6145 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6146 Spacing)); 6147 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6148 Spacing * 2)); 6149 TmpInst.addOperand(Inst.getOperand(1)); // lane 6150 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6151 TmpInst.addOperand(Inst.getOperand(5)); 6152 Inst = TmpInst; 6153 return true; 6154 } 6155 6156 case ARM::VST4LNdAsm_8: 6157 case ARM::VST4LNdAsm_16: 6158 case ARM::VST4LNdAsm_32: 6159 case ARM::VST4LNqAsm_16: 6160 case ARM::VST4LNqAsm_32: { 6161 MCInst TmpInst; 6162 // Shuffle the operands around so the lane index operand is in the 6163 // right place. 6164 unsigned Spacing; 6165 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6166 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6167 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6168 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6169 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6170 Spacing)); 6171 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6172 Spacing * 2)); 6173 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6174 Spacing * 3)); 6175 TmpInst.addOperand(Inst.getOperand(1)); // lane 6176 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6177 TmpInst.addOperand(Inst.getOperand(5)); 6178 Inst = TmpInst; 6179 return true; 6180 } 6181 6182 // Handle NEON VLD complex aliases. 6183 case ARM::VLD1LNdWB_register_Asm_8: 6184 case ARM::VLD1LNdWB_register_Asm_16: 6185 case ARM::VLD1LNdWB_register_Asm_32: { 6186 MCInst TmpInst; 6187 // Shuffle the operands around so the lane index operand is in the 6188 // right place. 6189 unsigned Spacing; 6190 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6191 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6192 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6193 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6194 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6195 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6196 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6197 TmpInst.addOperand(Inst.getOperand(1)); // lane 6198 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6199 TmpInst.addOperand(Inst.getOperand(6)); 6200 Inst = TmpInst; 6201 return true; 6202 } 6203 6204 case ARM::VLD2LNdWB_register_Asm_8: 6205 case ARM::VLD2LNdWB_register_Asm_16: 6206 case ARM::VLD2LNdWB_register_Asm_32: 6207 case ARM::VLD2LNqWB_register_Asm_16: 6208 case ARM::VLD2LNqWB_register_Asm_32: { 6209 MCInst TmpInst; 6210 // Shuffle the operands around so the lane index operand is in the 6211 // right place. 6212 unsigned Spacing; 6213 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6214 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6215 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6216 Spacing)); 6217 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6218 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6219 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6220 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6221 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6222 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6223 Spacing)); 6224 TmpInst.addOperand(Inst.getOperand(1)); // lane 6225 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6226 TmpInst.addOperand(Inst.getOperand(6)); 6227 Inst = TmpInst; 6228 return true; 6229 } 6230 6231 case ARM::VLD3LNdWB_register_Asm_8: 6232 case ARM::VLD3LNdWB_register_Asm_16: 6233 case ARM::VLD3LNdWB_register_Asm_32: 6234 case ARM::VLD3LNqWB_register_Asm_16: 6235 case ARM::VLD3LNqWB_register_Asm_32: { 6236 MCInst TmpInst; 6237 // Shuffle the operands around so the lane index operand is in the 6238 // right place. 6239 unsigned Spacing; 6240 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6241 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6242 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6243 Spacing)); 6244 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6245 Spacing * 2)); 6246 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6247 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6248 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6249 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6250 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6251 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6252 Spacing)); 6253 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6254 Spacing * 2)); 6255 TmpInst.addOperand(Inst.getOperand(1)); // lane 6256 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6257 TmpInst.addOperand(Inst.getOperand(6)); 6258 Inst = TmpInst; 6259 return true; 6260 } 6261 6262 case ARM::VLD4LNdWB_register_Asm_8: 6263 case ARM::VLD4LNdWB_register_Asm_16: 6264 case ARM::VLD4LNdWB_register_Asm_32: 6265 case ARM::VLD4LNqWB_register_Asm_16: 6266 case ARM::VLD4LNqWB_register_Asm_32: { 6267 MCInst TmpInst; 6268 // Shuffle the operands around so the lane index operand is in the 6269 // right place. 6270 unsigned Spacing; 6271 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6272 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6273 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6274 Spacing)); 6275 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6276 Spacing * 2)); 6277 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6278 Spacing * 3)); 6279 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6280 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6281 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6282 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6283 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6284 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6285 Spacing)); 6286 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6287 Spacing * 2)); 6288 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6289 Spacing * 3)); 6290 TmpInst.addOperand(Inst.getOperand(1)); // lane 6291 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6292 TmpInst.addOperand(Inst.getOperand(6)); 6293 Inst = TmpInst; 6294 return true; 6295 } 6296 6297 case ARM::VLD1LNdWB_fixed_Asm_8: 6298 case ARM::VLD1LNdWB_fixed_Asm_16: 6299 case ARM::VLD1LNdWB_fixed_Asm_32: { 6300 MCInst TmpInst; 6301 // Shuffle the operands around so the lane index operand is in the 6302 // right place. 6303 unsigned Spacing; 6304 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6305 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6306 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6307 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6308 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6309 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6310 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6311 TmpInst.addOperand(Inst.getOperand(1)); // lane 6312 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6313 TmpInst.addOperand(Inst.getOperand(5)); 6314 Inst = TmpInst; 6315 return true; 6316 } 6317 6318 case ARM::VLD2LNdWB_fixed_Asm_8: 6319 case ARM::VLD2LNdWB_fixed_Asm_16: 6320 case ARM::VLD2LNdWB_fixed_Asm_32: 6321 case ARM::VLD2LNqWB_fixed_Asm_16: 6322 case ARM::VLD2LNqWB_fixed_Asm_32: { 6323 MCInst TmpInst; 6324 // Shuffle the operands around so the lane index operand is in the 6325 // right place. 6326 unsigned Spacing; 6327 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6328 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6329 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6330 Spacing)); 6331 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6332 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6333 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6334 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6335 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6336 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6337 Spacing)); 6338 TmpInst.addOperand(Inst.getOperand(1)); // lane 6339 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6340 TmpInst.addOperand(Inst.getOperand(5)); 6341 Inst = TmpInst; 6342 return true; 6343 } 6344 6345 case ARM::VLD3LNdWB_fixed_Asm_8: 6346 case ARM::VLD3LNdWB_fixed_Asm_16: 6347 case ARM::VLD3LNdWB_fixed_Asm_32: 6348 case ARM::VLD3LNqWB_fixed_Asm_16: 6349 case ARM::VLD3LNqWB_fixed_Asm_32: { 6350 MCInst TmpInst; 6351 // Shuffle the operands around so the lane index operand is in the 6352 // right place. 6353 unsigned Spacing; 6354 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6355 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6356 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6357 Spacing)); 6358 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6359 Spacing * 2)); 6360 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6361 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6362 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6363 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6364 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6366 Spacing)); 6367 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6368 Spacing * 2)); 6369 TmpInst.addOperand(Inst.getOperand(1)); // lane 6370 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6371 TmpInst.addOperand(Inst.getOperand(5)); 6372 Inst = TmpInst; 6373 return true; 6374 } 6375 6376 case ARM::VLD4LNdWB_fixed_Asm_8: 6377 case ARM::VLD4LNdWB_fixed_Asm_16: 6378 case ARM::VLD4LNdWB_fixed_Asm_32: 6379 case ARM::VLD4LNqWB_fixed_Asm_16: 6380 case ARM::VLD4LNqWB_fixed_Asm_32: { 6381 MCInst TmpInst; 6382 // Shuffle the operands around so the lane index operand is in the 6383 // right place. 6384 unsigned Spacing; 6385 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6386 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6387 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6388 Spacing)); 6389 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6390 Spacing * 2)); 6391 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6392 Spacing * 3)); 6393 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6394 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6395 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6396 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6397 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6398 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6399 Spacing)); 6400 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6401 Spacing * 2)); 6402 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6403 Spacing * 3)); 6404 TmpInst.addOperand(Inst.getOperand(1)); // lane 6405 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6406 TmpInst.addOperand(Inst.getOperand(5)); 6407 Inst = TmpInst; 6408 return true; 6409 } 6410 6411 case ARM::VLD1LNdAsm_8: 6412 case ARM::VLD1LNdAsm_16: 6413 case ARM::VLD1LNdAsm_32: { 6414 MCInst TmpInst; 6415 // Shuffle the operands around so the lane index operand is in the 6416 // right place. 6417 unsigned Spacing; 6418 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6419 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6420 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6421 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6422 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6423 TmpInst.addOperand(Inst.getOperand(1)); // lane 6424 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6425 TmpInst.addOperand(Inst.getOperand(5)); 6426 Inst = TmpInst; 6427 return true; 6428 } 6429 6430 case ARM::VLD2LNdAsm_8: 6431 case ARM::VLD2LNdAsm_16: 6432 case ARM::VLD2LNdAsm_32: 6433 case ARM::VLD2LNqAsm_16: 6434 case ARM::VLD2LNqAsm_32: { 6435 MCInst TmpInst; 6436 // Shuffle the operands around so the lane index operand is in the 6437 // right place. 6438 unsigned Spacing; 6439 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6440 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6441 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6442 Spacing)); 6443 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6444 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6445 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6446 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6447 Spacing)); 6448 TmpInst.addOperand(Inst.getOperand(1)); // lane 6449 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6450 TmpInst.addOperand(Inst.getOperand(5)); 6451 Inst = TmpInst; 6452 return true; 6453 } 6454 6455 case ARM::VLD3LNdAsm_8: 6456 case ARM::VLD3LNdAsm_16: 6457 case ARM::VLD3LNdAsm_32: 6458 case ARM::VLD3LNqAsm_16: 6459 case ARM::VLD3LNqAsm_32: { 6460 MCInst TmpInst; 6461 // Shuffle the operands around so the lane index operand is in the 6462 // right place. 6463 unsigned Spacing; 6464 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6465 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6466 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6467 Spacing)); 6468 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6469 Spacing * 2)); 6470 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6471 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6472 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6473 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6474 Spacing)); 6475 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6476 Spacing * 2)); 6477 TmpInst.addOperand(Inst.getOperand(1)); // lane 6478 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6479 TmpInst.addOperand(Inst.getOperand(5)); 6480 Inst = TmpInst; 6481 return true; 6482 } 6483 6484 case ARM::VLD4LNdAsm_8: 6485 case ARM::VLD4LNdAsm_16: 6486 case ARM::VLD4LNdAsm_32: 6487 case ARM::VLD4LNqAsm_16: 6488 case ARM::VLD4LNqAsm_32: { 6489 MCInst TmpInst; 6490 // Shuffle the operands around so the lane index operand is in the 6491 // right place. 6492 unsigned Spacing; 6493 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6494 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6495 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6496 Spacing)); 6497 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6498 Spacing * 2)); 6499 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6500 Spacing * 3)); 6501 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6502 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6503 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6504 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6505 Spacing)); 6506 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6507 Spacing * 2)); 6508 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6509 Spacing * 3)); 6510 TmpInst.addOperand(Inst.getOperand(1)); // lane 6511 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6512 TmpInst.addOperand(Inst.getOperand(5)); 6513 Inst = TmpInst; 6514 return true; 6515 } 6516 6517 // VLD3DUP single 3-element structure to all lanes instructions. 6518 case ARM::VLD3DUPdAsm_8: 6519 case ARM::VLD3DUPdAsm_16: 6520 case ARM::VLD3DUPdAsm_32: 6521 case ARM::VLD3DUPqAsm_8: 6522 case ARM::VLD3DUPqAsm_16: 6523 case ARM::VLD3DUPqAsm_32: { 6524 MCInst TmpInst; 6525 unsigned Spacing; 6526 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6527 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6528 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6529 Spacing)); 6530 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6531 Spacing * 2)); 6532 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6533 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6534 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6535 TmpInst.addOperand(Inst.getOperand(4)); 6536 Inst = TmpInst; 6537 return true; 6538 } 6539 6540 case ARM::VLD3DUPdWB_fixed_Asm_8: 6541 case ARM::VLD3DUPdWB_fixed_Asm_16: 6542 case ARM::VLD3DUPdWB_fixed_Asm_32: 6543 case ARM::VLD3DUPqWB_fixed_Asm_8: 6544 case ARM::VLD3DUPqWB_fixed_Asm_16: 6545 case ARM::VLD3DUPqWB_fixed_Asm_32: { 6546 MCInst TmpInst; 6547 unsigned Spacing; 6548 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6549 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6550 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6551 Spacing)); 6552 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6553 Spacing * 2)); 6554 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6555 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6556 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6557 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6558 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6559 TmpInst.addOperand(Inst.getOperand(4)); 6560 Inst = TmpInst; 6561 return true; 6562 } 6563 6564 case ARM::VLD3DUPdWB_register_Asm_8: 6565 case ARM::VLD3DUPdWB_register_Asm_16: 6566 case ARM::VLD3DUPdWB_register_Asm_32: 6567 case ARM::VLD3DUPqWB_register_Asm_8: 6568 case ARM::VLD3DUPqWB_register_Asm_16: 6569 case ARM::VLD3DUPqWB_register_Asm_32: { 6570 MCInst TmpInst; 6571 unsigned Spacing; 6572 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6573 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6574 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6575 Spacing)); 6576 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6577 Spacing * 2)); 6578 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6579 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6580 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6581 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6582 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6583 TmpInst.addOperand(Inst.getOperand(5)); 6584 Inst = TmpInst; 6585 return true; 6586 } 6587 6588 // VLD3 multiple 3-element structure instructions. 6589 case ARM::VLD3dAsm_8: 6590 case ARM::VLD3dAsm_16: 6591 case ARM::VLD3dAsm_32: 6592 case ARM::VLD3qAsm_8: 6593 case ARM::VLD3qAsm_16: 6594 case ARM::VLD3qAsm_32: { 6595 MCInst TmpInst; 6596 unsigned Spacing; 6597 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6598 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6599 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6600 Spacing)); 6601 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6602 Spacing * 2)); 6603 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6604 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6605 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6606 TmpInst.addOperand(Inst.getOperand(4)); 6607 Inst = TmpInst; 6608 return true; 6609 } 6610 6611 case ARM::VLD3dWB_fixed_Asm_8: 6612 case ARM::VLD3dWB_fixed_Asm_16: 6613 case ARM::VLD3dWB_fixed_Asm_32: 6614 case ARM::VLD3qWB_fixed_Asm_8: 6615 case ARM::VLD3qWB_fixed_Asm_16: 6616 case ARM::VLD3qWB_fixed_Asm_32: { 6617 MCInst TmpInst; 6618 unsigned Spacing; 6619 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6620 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6621 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6622 Spacing)); 6623 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6624 Spacing * 2)); 6625 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6626 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6627 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6628 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6629 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6630 TmpInst.addOperand(Inst.getOperand(4)); 6631 Inst = TmpInst; 6632 return true; 6633 } 6634 6635 case ARM::VLD3dWB_register_Asm_8: 6636 case ARM::VLD3dWB_register_Asm_16: 6637 case ARM::VLD3dWB_register_Asm_32: 6638 case ARM::VLD3qWB_register_Asm_8: 6639 case ARM::VLD3qWB_register_Asm_16: 6640 case ARM::VLD3qWB_register_Asm_32: { 6641 MCInst TmpInst; 6642 unsigned Spacing; 6643 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6644 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6645 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6646 Spacing)); 6647 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6648 Spacing * 2)); 6649 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6650 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6651 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6652 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6653 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6654 TmpInst.addOperand(Inst.getOperand(5)); 6655 Inst = TmpInst; 6656 return true; 6657 } 6658 6659 // VLD4DUP single 3-element structure to all lanes instructions. 6660 case ARM::VLD4DUPdAsm_8: 6661 case ARM::VLD4DUPdAsm_16: 6662 case ARM::VLD4DUPdAsm_32: 6663 case ARM::VLD4DUPqAsm_8: 6664 case ARM::VLD4DUPqAsm_16: 6665 case ARM::VLD4DUPqAsm_32: { 6666 MCInst TmpInst; 6667 unsigned Spacing; 6668 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6669 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6670 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6671 Spacing)); 6672 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6673 Spacing * 2)); 6674 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6675 Spacing * 3)); 6676 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6677 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6678 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6679 TmpInst.addOperand(Inst.getOperand(4)); 6680 Inst = TmpInst; 6681 return true; 6682 } 6683 6684 case ARM::VLD4DUPdWB_fixed_Asm_8: 6685 case ARM::VLD4DUPdWB_fixed_Asm_16: 6686 case ARM::VLD4DUPdWB_fixed_Asm_32: 6687 case ARM::VLD4DUPqWB_fixed_Asm_8: 6688 case ARM::VLD4DUPqWB_fixed_Asm_16: 6689 case ARM::VLD4DUPqWB_fixed_Asm_32: { 6690 MCInst TmpInst; 6691 unsigned Spacing; 6692 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6693 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6695 Spacing)); 6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6697 Spacing * 2)); 6698 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6699 Spacing * 3)); 6700 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6701 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6702 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6703 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6704 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6705 TmpInst.addOperand(Inst.getOperand(4)); 6706 Inst = TmpInst; 6707 return true; 6708 } 6709 6710 case ARM::VLD4DUPdWB_register_Asm_8: 6711 case ARM::VLD4DUPdWB_register_Asm_16: 6712 case ARM::VLD4DUPdWB_register_Asm_32: 6713 case ARM::VLD4DUPqWB_register_Asm_8: 6714 case ARM::VLD4DUPqWB_register_Asm_16: 6715 case ARM::VLD4DUPqWB_register_Asm_32: { 6716 MCInst TmpInst; 6717 unsigned Spacing; 6718 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6719 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6720 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6721 Spacing)); 6722 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6723 Spacing * 2)); 6724 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6725 Spacing * 3)); 6726 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6727 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6728 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6729 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6730 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6731 TmpInst.addOperand(Inst.getOperand(5)); 6732 Inst = TmpInst; 6733 return true; 6734 } 6735 6736 // VLD4 multiple 4-element structure instructions. 6737 case ARM::VLD4dAsm_8: 6738 case ARM::VLD4dAsm_16: 6739 case ARM::VLD4dAsm_32: 6740 case ARM::VLD4qAsm_8: 6741 case ARM::VLD4qAsm_16: 6742 case ARM::VLD4qAsm_32: { 6743 MCInst TmpInst; 6744 unsigned Spacing; 6745 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6746 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6747 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6748 Spacing)); 6749 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6750 Spacing * 2)); 6751 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6752 Spacing * 3)); 6753 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6754 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6755 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6756 TmpInst.addOperand(Inst.getOperand(4)); 6757 Inst = TmpInst; 6758 return true; 6759 } 6760 6761 case ARM::VLD4dWB_fixed_Asm_8: 6762 case ARM::VLD4dWB_fixed_Asm_16: 6763 case ARM::VLD4dWB_fixed_Asm_32: 6764 case ARM::VLD4qWB_fixed_Asm_8: 6765 case ARM::VLD4qWB_fixed_Asm_16: 6766 case ARM::VLD4qWB_fixed_Asm_32: { 6767 MCInst TmpInst; 6768 unsigned Spacing; 6769 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6770 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6771 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6772 Spacing)); 6773 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6774 Spacing * 2)); 6775 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6776 Spacing * 3)); 6777 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6778 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6779 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6780 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6781 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6782 TmpInst.addOperand(Inst.getOperand(4)); 6783 Inst = TmpInst; 6784 return true; 6785 } 6786 6787 case ARM::VLD4dWB_register_Asm_8: 6788 case ARM::VLD4dWB_register_Asm_16: 6789 case ARM::VLD4dWB_register_Asm_32: 6790 case ARM::VLD4qWB_register_Asm_8: 6791 case ARM::VLD4qWB_register_Asm_16: 6792 case ARM::VLD4qWB_register_Asm_32: { 6793 MCInst TmpInst; 6794 unsigned Spacing; 6795 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6796 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6797 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6798 Spacing)); 6799 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6800 Spacing * 2)); 6801 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6802 Spacing * 3)); 6803 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6804 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6805 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6806 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6807 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6808 TmpInst.addOperand(Inst.getOperand(5)); 6809 Inst = TmpInst; 6810 return true; 6811 } 6812 6813 // VST3 multiple 3-element structure instructions. 6814 case ARM::VST3dAsm_8: 6815 case ARM::VST3dAsm_16: 6816 case ARM::VST3dAsm_32: 6817 case ARM::VST3qAsm_8: 6818 case ARM::VST3qAsm_16: 6819 case ARM::VST3qAsm_32: { 6820 MCInst TmpInst; 6821 unsigned Spacing; 6822 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6823 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6824 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6825 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6827 Spacing)); 6828 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6829 Spacing * 2)); 6830 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6831 TmpInst.addOperand(Inst.getOperand(4)); 6832 Inst = TmpInst; 6833 return true; 6834 } 6835 6836 case ARM::VST3dWB_fixed_Asm_8: 6837 case ARM::VST3dWB_fixed_Asm_16: 6838 case ARM::VST3dWB_fixed_Asm_32: 6839 case ARM::VST3qWB_fixed_Asm_8: 6840 case ARM::VST3qWB_fixed_Asm_16: 6841 case ARM::VST3qWB_fixed_Asm_32: { 6842 MCInst TmpInst; 6843 unsigned Spacing; 6844 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6845 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6846 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6847 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6848 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6849 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6850 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6851 Spacing)); 6852 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6853 Spacing * 2)); 6854 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6855 TmpInst.addOperand(Inst.getOperand(4)); 6856 Inst = TmpInst; 6857 return true; 6858 } 6859 6860 case ARM::VST3dWB_register_Asm_8: 6861 case ARM::VST3dWB_register_Asm_16: 6862 case ARM::VST3dWB_register_Asm_32: 6863 case ARM::VST3qWB_register_Asm_8: 6864 case ARM::VST3qWB_register_Asm_16: 6865 case ARM::VST3qWB_register_Asm_32: { 6866 MCInst TmpInst; 6867 unsigned Spacing; 6868 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6869 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6870 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6871 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6872 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6873 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6874 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6875 Spacing)); 6876 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6877 Spacing * 2)); 6878 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6879 TmpInst.addOperand(Inst.getOperand(5)); 6880 Inst = TmpInst; 6881 return true; 6882 } 6883 6884 // VST4 multiple 3-element structure instructions. 6885 case ARM::VST4dAsm_8: 6886 case ARM::VST4dAsm_16: 6887 case ARM::VST4dAsm_32: 6888 case ARM::VST4qAsm_8: 6889 case ARM::VST4qAsm_16: 6890 case ARM::VST4qAsm_32: { 6891 MCInst TmpInst; 6892 unsigned Spacing; 6893 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6894 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6895 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6896 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6897 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6898 Spacing)); 6899 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6900 Spacing * 2)); 6901 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6902 Spacing * 3)); 6903 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6904 TmpInst.addOperand(Inst.getOperand(4)); 6905 Inst = TmpInst; 6906 return true; 6907 } 6908 6909 case ARM::VST4dWB_fixed_Asm_8: 6910 case ARM::VST4dWB_fixed_Asm_16: 6911 case ARM::VST4dWB_fixed_Asm_32: 6912 case ARM::VST4qWB_fixed_Asm_8: 6913 case ARM::VST4qWB_fixed_Asm_16: 6914 case ARM::VST4qWB_fixed_Asm_32: { 6915 MCInst TmpInst; 6916 unsigned Spacing; 6917 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6918 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6919 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6920 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6921 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6922 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6923 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6924 Spacing)); 6925 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6926 Spacing * 2)); 6927 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6928 Spacing * 3)); 6929 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6930 TmpInst.addOperand(Inst.getOperand(4)); 6931 Inst = TmpInst; 6932 return true; 6933 } 6934 6935 case ARM::VST4dWB_register_Asm_8: 6936 case ARM::VST4dWB_register_Asm_16: 6937 case ARM::VST4dWB_register_Asm_32: 6938 case ARM::VST4qWB_register_Asm_8: 6939 case ARM::VST4qWB_register_Asm_16: 6940 case ARM::VST4qWB_register_Asm_32: { 6941 MCInst TmpInst; 6942 unsigned Spacing; 6943 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6944 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6945 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6946 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6947 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6948 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6949 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6950 Spacing)); 6951 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6952 Spacing * 2)); 6953 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6954 Spacing * 3)); 6955 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6956 TmpInst.addOperand(Inst.getOperand(5)); 6957 Inst = TmpInst; 6958 return true; 6959 } 6960 6961 // Handle encoding choice for the shift-immediate instructions. 6962 case ARM::t2LSLri: 6963 case ARM::t2LSRri: 6964 case ARM::t2ASRri: { 6965 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6966 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6967 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 6968 !(static_cast<ARMOperand*>(Operands[3])->isToken() && 6969 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 6970 unsigned NewOpc; 6971 switch (Inst.getOpcode()) { 6972 default: llvm_unreachable("unexpected opcode"); 6973 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6974 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6975 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6976 } 6977 // The Thumb1 operands aren't in the same order. Awesome, eh? 6978 MCInst TmpInst; 6979 TmpInst.setOpcode(NewOpc); 6980 TmpInst.addOperand(Inst.getOperand(0)); 6981 TmpInst.addOperand(Inst.getOperand(5)); 6982 TmpInst.addOperand(Inst.getOperand(1)); 6983 TmpInst.addOperand(Inst.getOperand(2)); 6984 TmpInst.addOperand(Inst.getOperand(3)); 6985 TmpInst.addOperand(Inst.getOperand(4)); 6986 Inst = TmpInst; 6987 return true; 6988 } 6989 return false; 6990 } 6991 6992 // Handle the Thumb2 mode MOV complex aliases. 6993 case ARM::t2MOVsr: 6994 case ARM::t2MOVSsr: { 6995 // Which instruction to expand to depends on the CCOut operand and 6996 // whether we're in an IT block if the register operands are low 6997 // registers. 6998 bool isNarrow = false; 6999 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7000 isARMLowRegister(Inst.getOperand(1).getReg()) && 7001 isARMLowRegister(Inst.getOperand(2).getReg()) && 7002 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7003 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 7004 isNarrow = true; 7005 MCInst TmpInst; 7006 unsigned newOpc; 7007 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 7008 default: llvm_unreachable("unexpected opcode!"); 7009 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 7010 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 7011 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 7012 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 7013 } 7014 TmpInst.setOpcode(newOpc); 7015 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7016 if (isNarrow) 7017 TmpInst.addOperand(MCOperand::CreateReg( 7018 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7019 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7020 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7021 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7022 TmpInst.addOperand(Inst.getOperand(5)); 7023 if (!isNarrow) 7024 TmpInst.addOperand(MCOperand::CreateReg( 7025 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7026 Inst = TmpInst; 7027 return true; 7028 } 7029 case ARM::t2MOVsi: 7030 case ARM::t2MOVSsi: { 7031 // Which instruction to expand to depends on the CCOut operand and 7032 // whether we're in an IT block if the register operands are low 7033 // registers. 7034 bool isNarrow = false; 7035 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7036 isARMLowRegister(Inst.getOperand(1).getReg()) && 7037 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 7038 isNarrow = true; 7039 MCInst TmpInst; 7040 unsigned newOpc; 7041 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 7042 default: llvm_unreachable("unexpected opcode!"); 7043 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 7044 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 7045 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 7046 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 7047 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 7048 } 7049 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 7050 if (Amount == 32) Amount = 0; 7051 TmpInst.setOpcode(newOpc); 7052 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7053 if (isNarrow) 7054 TmpInst.addOperand(MCOperand::CreateReg( 7055 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7056 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7057 if (newOpc != ARM::t2RRX) 7058 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 7059 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7060 TmpInst.addOperand(Inst.getOperand(4)); 7061 if (!isNarrow) 7062 TmpInst.addOperand(MCOperand::CreateReg( 7063 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7064 Inst = TmpInst; 7065 return true; 7066 } 7067 // Handle the ARM mode MOV complex aliases. 7068 case ARM::ASRr: 7069 case ARM::LSRr: 7070 case ARM::LSLr: 7071 case ARM::RORr: { 7072 ARM_AM::ShiftOpc ShiftTy; 7073 switch(Inst.getOpcode()) { 7074 default: llvm_unreachable("unexpected opcode!"); 7075 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 7076 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 7077 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 7078 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 7079 } 7080 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 7081 MCInst TmpInst; 7082 TmpInst.setOpcode(ARM::MOVsr); 7083 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7084 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7085 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7086 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7087 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7088 TmpInst.addOperand(Inst.getOperand(4)); 7089 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7090 Inst = TmpInst; 7091 return true; 7092 } 7093 case ARM::ASRi: 7094 case ARM::LSRi: 7095 case ARM::LSLi: 7096 case ARM::RORi: { 7097 ARM_AM::ShiftOpc ShiftTy; 7098 switch(Inst.getOpcode()) { 7099 default: llvm_unreachable("unexpected opcode!"); 7100 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 7101 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 7102 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 7103 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 7104 } 7105 // A shift by zero is a plain MOVr, not a MOVsi. 7106 unsigned Amt = Inst.getOperand(2).getImm(); 7107 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 7108 // A shift by 32 should be encoded as 0 when permitted 7109 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 7110 Amt = 0; 7111 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 7112 MCInst TmpInst; 7113 TmpInst.setOpcode(Opc); 7114 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7115 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7116 if (Opc == ARM::MOVsi) 7117 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7118 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7119 TmpInst.addOperand(Inst.getOperand(4)); 7120 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7121 Inst = TmpInst; 7122 return true; 7123 } 7124 case ARM::RRXi: { 7125 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 7126 MCInst TmpInst; 7127 TmpInst.setOpcode(ARM::MOVsi); 7128 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7129 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7130 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7131 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7132 TmpInst.addOperand(Inst.getOperand(3)); 7133 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 7134 Inst = TmpInst; 7135 return true; 7136 } 7137 case ARM::t2LDMIA_UPD: { 7138 // If this is a load of a single register, then we should use 7139 // a post-indexed LDR instruction instead, per the ARM ARM. 7140 if (Inst.getNumOperands() != 5) 7141 return false; 7142 MCInst TmpInst; 7143 TmpInst.setOpcode(ARM::t2LDR_POST); 7144 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7145 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7146 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7147 TmpInst.addOperand(MCOperand::CreateImm(4)); 7148 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7149 TmpInst.addOperand(Inst.getOperand(3)); 7150 Inst = TmpInst; 7151 return true; 7152 } 7153 case ARM::t2STMDB_UPD: { 7154 // If this is a store of a single register, then we should use 7155 // a pre-indexed STR instruction instead, per the ARM ARM. 7156 if (Inst.getNumOperands() != 5) 7157 return false; 7158 MCInst TmpInst; 7159 TmpInst.setOpcode(ARM::t2STR_PRE); 7160 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7161 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7162 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7163 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7164 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7165 TmpInst.addOperand(Inst.getOperand(3)); 7166 Inst = TmpInst; 7167 return true; 7168 } 7169 case ARM::LDMIA_UPD: 7170 // If this is a load of a single register via a 'pop', then we should use 7171 // a post-indexed LDR instruction instead, per the ARM ARM. 7172 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 7173 Inst.getNumOperands() == 5) { 7174 MCInst TmpInst; 7175 TmpInst.setOpcode(ARM::LDR_POST_IMM); 7176 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7177 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7178 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7179 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 7180 TmpInst.addOperand(MCOperand::CreateImm(4)); 7181 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7182 TmpInst.addOperand(Inst.getOperand(3)); 7183 Inst = TmpInst; 7184 return true; 7185 } 7186 break; 7187 case ARM::STMDB_UPD: 7188 // If this is a store of a single register via a 'push', then we should use 7189 // a pre-indexed STR instruction instead, per the ARM ARM. 7190 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 7191 Inst.getNumOperands() == 5) { 7192 MCInst TmpInst; 7193 TmpInst.setOpcode(ARM::STR_PRE_IMM); 7194 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7195 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7196 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 7197 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7198 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7199 TmpInst.addOperand(Inst.getOperand(3)); 7200 Inst = TmpInst; 7201 } 7202 break; 7203 case ARM::t2ADDri12: 7204 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 7205 // mnemonic was used (not "addw"), encoding T3 is preferred. 7206 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 7207 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7208 break; 7209 Inst.setOpcode(ARM::t2ADDri); 7210 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7211 break; 7212 case ARM::t2SUBri12: 7213 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 7214 // mnemonic was used (not "subw"), encoding T3 is preferred. 7215 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 7216 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7217 break; 7218 Inst.setOpcode(ARM::t2SUBri); 7219 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7220 break; 7221 case ARM::tADDi8: 7222 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7223 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7224 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7225 // to encoding T1 if <Rd> is omitted." 7226 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7227 Inst.setOpcode(ARM::tADDi3); 7228 return true; 7229 } 7230 break; 7231 case ARM::tSUBi8: 7232 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7233 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7234 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7235 // to encoding T1 if <Rd> is omitted." 7236 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7237 Inst.setOpcode(ARM::tSUBi3); 7238 return true; 7239 } 7240 break; 7241 case ARM::t2ADDri: 7242 case ARM::t2SUBri: { 7243 // If the destination and first source operand are the same, and 7244 // the flags are compatible with the current IT status, use encoding T2 7245 // instead of T3. For compatibility with the system 'as'. Make sure the 7246 // wide encoding wasn't explicit. 7247 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7248 !isARMLowRegister(Inst.getOperand(0).getReg()) || 7249 (unsigned)Inst.getOperand(2).getImm() > 255 || 7250 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 7251 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 7252 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7253 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7254 break; 7255 MCInst TmpInst; 7256 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7257 ARM::tADDi8 : ARM::tSUBi8); 7258 TmpInst.addOperand(Inst.getOperand(0)); 7259 TmpInst.addOperand(Inst.getOperand(5)); 7260 TmpInst.addOperand(Inst.getOperand(0)); 7261 TmpInst.addOperand(Inst.getOperand(2)); 7262 TmpInst.addOperand(Inst.getOperand(3)); 7263 TmpInst.addOperand(Inst.getOperand(4)); 7264 Inst = TmpInst; 7265 return true; 7266 } 7267 case ARM::t2ADDrr: { 7268 // If the destination and first source operand are the same, and 7269 // there's no setting of the flags, use encoding T2 instead of T3. 7270 // Note that this is only for ADD, not SUB. This mirrors the system 7271 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7272 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7273 Inst.getOperand(5).getReg() != 0 || 7274 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7275 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7276 break; 7277 MCInst TmpInst; 7278 TmpInst.setOpcode(ARM::tADDhirr); 7279 TmpInst.addOperand(Inst.getOperand(0)); 7280 TmpInst.addOperand(Inst.getOperand(0)); 7281 TmpInst.addOperand(Inst.getOperand(2)); 7282 TmpInst.addOperand(Inst.getOperand(3)); 7283 TmpInst.addOperand(Inst.getOperand(4)); 7284 Inst = TmpInst; 7285 return true; 7286 } 7287 case ARM::tADDrSP: { 7288 // If the non-SP source operand and the destination operand are not the 7289 // same, we need to use the 32-bit encoding if it's available. 7290 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7291 Inst.setOpcode(ARM::t2ADDrr); 7292 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7293 return true; 7294 } 7295 break; 7296 } 7297 case ARM::tB: 7298 // A Thumb conditional branch outside of an IT block is a tBcc. 7299 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7300 Inst.setOpcode(ARM::tBcc); 7301 return true; 7302 } 7303 break; 7304 case ARM::t2B: 7305 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7306 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7307 Inst.setOpcode(ARM::t2Bcc); 7308 return true; 7309 } 7310 break; 7311 case ARM::t2Bcc: 7312 // If the conditional is AL or we're in an IT block, we really want t2B. 7313 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7314 Inst.setOpcode(ARM::t2B); 7315 return true; 7316 } 7317 break; 7318 case ARM::tBcc: 7319 // If the conditional is AL, we really want tB. 7320 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7321 Inst.setOpcode(ARM::tB); 7322 return true; 7323 } 7324 break; 7325 case ARM::tLDMIA: { 7326 // If the register list contains any high registers, or if the writeback 7327 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7328 // instead if we're in Thumb2. Otherwise, this should have generated 7329 // an error in validateInstruction(). 7330 unsigned Rn = Inst.getOperand(0).getReg(); 7331 bool hasWritebackToken = 7332 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7333 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 7334 bool listContainsBase; 7335 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7336 (!listContainsBase && !hasWritebackToken) || 7337 (listContainsBase && hasWritebackToken)) { 7338 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7339 assert (isThumbTwo()); 7340 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7341 // If we're switching to the updating version, we need to insert 7342 // the writeback tied operand. 7343 if (hasWritebackToken) 7344 Inst.insert(Inst.begin(), 7345 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7346 return true; 7347 } 7348 break; 7349 } 7350 case ARM::tSTMIA_UPD: { 7351 // If the register list contains any high registers, we need to use 7352 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7353 // should have generated an error in validateInstruction(). 7354 unsigned Rn = Inst.getOperand(0).getReg(); 7355 bool listContainsBase; 7356 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7357 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7358 assert (isThumbTwo()); 7359 Inst.setOpcode(ARM::t2STMIA_UPD); 7360 return true; 7361 } 7362 break; 7363 } 7364 case ARM::tPOP: { 7365 bool listContainsBase; 7366 // If the register list contains any high registers, we need to use 7367 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7368 // should have generated an error in validateInstruction(). 7369 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7370 return false; 7371 assert (isThumbTwo()); 7372 Inst.setOpcode(ARM::t2LDMIA_UPD); 7373 // Add the base register and writeback operands. 7374 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7375 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7376 return true; 7377 } 7378 case ARM::tPUSH: { 7379 bool listContainsBase; 7380 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7381 return false; 7382 assert (isThumbTwo()); 7383 Inst.setOpcode(ARM::t2STMDB_UPD); 7384 // Add the base register and writeback operands. 7385 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7386 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7387 return true; 7388 } 7389 case ARM::t2MOVi: { 7390 // If we can use the 16-bit encoding and the user didn't explicitly 7391 // request the 32-bit variant, transform it here. 7392 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7393 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7394 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7395 Inst.getOperand(4).getReg() == ARM::CPSR) || 7396 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7397 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7398 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7399 // The operands aren't in the same order for tMOVi8... 7400 MCInst TmpInst; 7401 TmpInst.setOpcode(ARM::tMOVi8); 7402 TmpInst.addOperand(Inst.getOperand(0)); 7403 TmpInst.addOperand(Inst.getOperand(4)); 7404 TmpInst.addOperand(Inst.getOperand(1)); 7405 TmpInst.addOperand(Inst.getOperand(2)); 7406 TmpInst.addOperand(Inst.getOperand(3)); 7407 Inst = TmpInst; 7408 return true; 7409 } 7410 break; 7411 } 7412 case ARM::t2MOVr: { 7413 // If we can use the 16-bit encoding and the user didn't explicitly 7414 // request the 32-bit variant, transform it here. 7415 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7416 isARMLowRegister(Inst.getOperand(1).getReg()) && 7417 Inst.getOperand(2).getImm() == ARMCC::AL && 7418 Inst.getOperand(4).getReg() == ARM::CPSR && 7419 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7420 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7421 // The operands aren't the same for tMOV[S]r... (no cc_out) 7422 MCInst TmpInst; 7423 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 7424 TmpInst.addOperand(Inst.getOperand(0)); 7425 TmpInst.addOperand(Inst.getOperand(1)); 7426 TmpInst.addOperand(Inst.getOperand(2)); 7427 TmpInst.addOperand(Inst.getOperand(3)); 7428 Inst = TmpInst; 7429 return true; 7430 } 7431 break; 7432 } 7433 case ARM::t2SXTH: 7434 case ARM::t2SXTB: 7435 case ARM::t2UXTH: 7436 case ARM::t2UXTB: { 7437 // If we can use the 16-bit encoding and the user didn't explicitly 7438 // request the 32-bit variant, transform it here. 7439 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7440 isARMLowRegister(Inst.getOperand(1).getReg()) && 7441 Inst.getOperand(2).getImm() == 0 && 7442 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7443 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7444 unsigned NewOpc; 7445 switch (Inst.getOpcode()) { 7446 default: llvm_unreachable("Illegal opcode!"); 7447 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7448 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7449 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7450 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 7451 } 7452 // The operands aren't the same for thumb1 (no rotate operand). 7453 MCInst TmpInst; 7454 TmpInst.setOpcode(NewOpc); 7455 TmpInst.addOperand(Inst.getOperand(0)); 7456 TmpInst.addOperand(Inst.getOperand(1)); 7457 TmpInst.addOperand(Inst.getOperand(3)); 7458 TmpInst.addOperand(Inst.getOperand(4)); 7459 Inst = TmpInst; 7460 return true; 7461 } 7462 break; 7463 } 7464 case ARM::MOVsi: { 7465 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7466 // rrx shifts and asr/lsr of #32 is encoded as 0 7467 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7468 return false; 7469 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 7470 // Shifting by zero is accepted as a vanilla 'MOVr' 7471 MCInst TmpInst; 7472 TmpInst.setOpcode(ARM::MOVr); 7473 TmpInst.addOperand(Inst.getOperand(0)); 7474 TmpInst.addOperand(Inst.getOperand(1)); 7475 TmpInst.addOperand(Inst.getOperand(3)); 7476 TmpInst.addOperand(Inst.getOperand(4)); 7477 TmpInst.addOperand(Inst.getOperand(5)); 7478 Inst = TmpInst; 7479 return true; 7480 } 7481 return false; 7482 } 7483 case ARM::ANDrsi: 7484 case ARM::ORRrsi: 7485 case ARM::EORrsi: 7486 case ARM::BICrsi: 7487 case ARM::SUBrsi: 7488 case ARM::ADDrsi: { 7489 unsigned newOpc; 7490 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 7491 if (SOpc == ARM_AM::rrx) return false; 7492 switch (Inst.getOpcode()) { 7493 default: llvm_unreachable("unexpected opcode!"); 7494 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 7495 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 7496 case ARM::EORrsi: newOpc = ARM::EORrr; break; 7497 case ARM::BICrsi: newOpc = ARM::BICrr; break; 7498 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 7499 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 7500 } 7501 // If the shift is by zero, use the non-shifted instruction definition. 7502 // The exception is for right shifts, where 0 == 32 7503 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 7504 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 7505 MCInst TmpInst; 7506 TmpInst.setOpcode(newOpc); 7507 TmpInst.addOperand(Inst.getOperand(0)); 7508 TmpInst.addOperand(Inst.getOperand(1)); 7509 TmpInst.addOperand(Inst.getOperand(2)); 7510 TmpInst.addOperand(Inst.getOperand(4)); 7511 TmpInst.addOperand(Inst.getOperand(5)); 7512 TmpInst.addOperand(Inst.getOperand(6)); 7513 Inst = TmpInst; 7514 return true; 7515 } 7516 return false; 7517 } 7518 case ARM::ITasm: 7519 case ARM::t2IT: { 7520 // The mask bits for all but the first condition are represented as 7521 // the low bit of the condition code value implies 't'. We currently 7522 // always have 1 implies 't', so XOR toggle the bits if the low bit 7523 // of the condition code is zero. 7524 MCOperand &MO = Inst.getOperand(1); 7525 unsigned Mask = MO.getImm(); 7526 unsigned OrigMask = Mask; 7527 unsigned TZ = countTrailingZeros(Mask); 7528 if ((Inst.getOperand(0).getImm() & 1) == 0) { 7529 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 7530 Mask ^= (0xE << TZ) & 0xF; 7531 } 7532 MO.setImm(Mask); 7533 7534 // Set up the IT block state according to the IT instruction we just 7535 // matched. 7536 assert(!inITBlock() && "nested IT blocks?!"); 7537 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7538 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7539 ITState.CurPosition = 0; 7540 ITState.FirstCond = true; 7541 break; 7542 } 7543 case ARM::t2LSLrr: 7544 case ARM::t2LSRrr: 7545 case ARM::t2ASRrr: 7546 case ARM::t2SBCrr: 7547 case ARM::t2RORrr: 7548 case ARM::t2BICrr: 7549 { 7550 // Assemblers should use the narrow encodings of these instructions when permissible. 7551 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7552 isARMLowRegister(Inst.getOperand(2).getReg())) && 7553 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7554 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7555 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7556 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7557 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7558 unsigned NewOpc; 7559 switch (Inst.getOpcode()) { 7560 default: llvm_unreachable("unexpected opcode"); 7561 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 7562 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 7563 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 7564 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 7565 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 7566 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 7567 } 7568 MCInst TmpInst; 7569 TmpInst.setOpcode(NewOpc); 7570 TmpInst.addOperand(Inst.getOperand(0)); 7571 TmpInst.addOperand(Inst.getOperand(5)); 7572 TmpInst.addOperand(Inst.getOperand(1)); 7573 TmpInst.addOperand(Inst.getOperand(2)); 7574 TmpInst.addOperand(Inst.getOperand(3)); 7575 TmpInst.addOperand(Inst.getOperand(4)); 7576 Inst = TmpInst; 7577 return true; 7578 } 7579 return false; 7580 } 7581 case ARM::t2ANDrr: 7582 case ARM::t2EORrr: 7583 case ARM::t2ADCrr: 7584 case ARM::t2ORRrr: 7585 { 7586 // Assemblers should use the narrow encodings of these instructions when permissible. 7587 // These instructions are special in that they are commutable, so shorter encodings 7588 // are available more often. 7589 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7590 isARMLowRegister(Inst.getOperand(2).getReg())) && 7591 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 7592 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 7593 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7594 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7595 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7596 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7597 unsigned NewOpc; 7598 switch (Inst.getOpcode()) { 7599 default: llvm_unreachable("unexpected opcode"); 7600 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 7601 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 7602 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 7603 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 7604 } 7605 MCInst TmpInst; 7606 TmpInst.setOpcode(NewOpc); 7607 TmpInst.addOperand(Inst.getOperand(0)); 7608 TmpInst.addOperand(Inst.getOperand(5)); 7609 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 7610 TmpInst.addOperand(Inst.getOperand(1)); 7611 TmpInst.addOperand(Inst.getOperand(2)); 7612 } else { 7613 TmpInst.addOperand(Inst.getOperand(2)); 7614 TmpInst.addOperand(Inst.getOperand(1)); 7615 } 7616 TmpInst.addOperand(Inst.getOperand(3)); 7617 TmpInst.addOperand(Inst.getOperand(4)); 7618 Inst = TmpInst; 7619 return true; 7620 } 7621 return false; 7622 } 7623 } 7624 return false; 7625 } 7626 7627 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 7628 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 7629 // suffix depending on whether they're in an IT block or not. 7630 unsigned Opc = Inst.getOpcode(); 7631 const MCInstrDesc &MCID = getInstDesc(Opc); 7632 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 7633 assert(MCID.hasOptionalDef() && 7634 "optionally flag setting instruction missing optional def operand"); 7635 assert(MCID.NumOperands == Inst.getNumOperands() && 7636 "operand count mismatch!"); 7637 // Find the optional-def operand (cc_out). 7638 unsigned OpNo; 7639 for (OpNo = 0; 7640 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 7641 ++OpNo) 7642 ; 7643 // If we're parsing Thumb1, reject it completely. 7644 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 7645 return Match_MnemonicFail; 7646 // If we're parsing Thumb2, which form is legal depends on whether we're 7647 // in an IT block. 7648 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7649 !inITBlock()) 7650 return Match_RequiresITBlock; 7651 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7652 inITBlock()) 7653 return Match_RequiresNotITBlock; 7654 } 7655 // Some high-register supporting Thumb1 encodings only allow both registers 7656 // to be from r0-r7 when in Thumb2. 7657 else if (Opc == ARM::tADDhirr && isThumbOne() && 7658 isARMLowRegister(Inst.getOperand(1).getReg()) && 7659 isARMLowRegister(Inst.getOperand(2).getReg())) 7660 return Match_RequiresThumb2; 7661 // Others only require ARMv6 or later. 7662 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7663 isARMLowRegister(Inst.getOperand(0).getReg()) && 7664 isARMLowRegister(Inst.getOperand(1).getReg())) 7665 return Match_RequiresV6; 7666 return Match_Success; 7667 } 7668 7669 static const char *getSubtargetFeatureName(unsigned Val); 7670 bool ARMAsmParser:: 7671 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 7672 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7673 MCStreamer &Out, unsigned &ErrorInfo, 7674 bool MatchingInlineAsm) { 7675 MCInst Inst; 7676 unsigned MatchResult; 7677 7678 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 7679 MatchingInlineAsm); 7680 switch (MatchResult) { 7681 default: break; 7682 case Match_Success: 7683 // Context sensitive operand constraints aren't handled by the matcher, 7684 // so check them here. 7685 if (validateInstruction(Inst, Operands)) { 7686 // Still progress the IT block, otherwise one wrong condition causes 7687 // nasty cascading errors. 7688 forwardITPosition(); 7689 return true; 7690 } 7691 7692 // Some instructions need post-processing to, for example, tweak which 7693 // encoding is selected. Loop on it while changes happen so the 7694 // individual transformations can chain off each other. E.g., 7695 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 7696 while (processInstruction(Inst, Operands)) 7697 ; 7698 7699 // Only move forward at the very end so that everything in validate 7700 // and process gets a consistent answer about whether we're in an IT 7701 // block. 7702 forwardITPosition(); 7703 7704 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 7705 // doesn't actually encode. 7706 if (Inst.getOpcode() == ARM::ITasm) 7707 return false; 7708 7709 Inst.setLoc(IDLoc); 7710 Out.EmitInstruction(Inst); 7711 return false; 7712 case Match_MissingFeature: { 7713 assert(ErrorInfo && "Unknown missing feature!"); 7714 // Special case the error message for the very common case where only 7715 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 7716 std::string Msg = "instruction requires:"; 7717 unsigned Mask = 1; 7718 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 7719 if (ErrorInfo & Mask) { 7720 Msg += " "; 7721 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 7722 } 7723 Mask <<= 1; 7724 } 7725 return Error(IDLoc, Msg); 7726 } 7727 case Match_InvalidOperand: { 7728 SMLoc ErrorLoc = IDLoc; 7729 if (ErrorInfo != ~0U) { 7730 if (ErrorInfo >= Operands.size()) 7731 return Error(IDLoc, "too few operands for instruction"); 7732 7733 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7734 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7735 } 7736 7737 return Error(ErrorLoc, "invalid operand for instruction"); 7738 } 7739 case Match_MnemonicFail: 7740 return Error(IDLoc, "invalid instruction", 7741 ((ARMOperand*)Operands[0])->getLocRange()); 7742 case Match_RequiresNotITBlock: 7743 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 7744 case Match_RequiresITBlock: 7745 return Error(IDLoc, "instruction only valid inside IT block"); 7746 case Match_RequiresV6: 7747 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7748 case Match_RequiresThumb2: 7749 return Error(IDLoc, "instruction variant requires Thumb2"); 7750 case Match_ImmRange0_4: { 7751 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7752 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7753 return Error(ErrorLoc, "immediate operand must be in the range [0,4]"); 7754 } 7755 case Match_ImmRange0_15: { 7756 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7757 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7758 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 7759 } 7760 } 7761 7762 llvm_unreachable("Implement any new match types added!"); 7763 } 7764 7765 /// parseDirective parses the arm specific directives 7766 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7767 StringRef IDVal = DirectiveID.getIdentifier(); 7768 if (IDVal == ".word") 7769 return parseDirectiveWord(4, DirectiveID.getLoc()); 7770 else if (IDVal == ".thumb") 7771 return parseDirectiveThumb(DirectiveID.getLoc()); 7772 else if (IDVal == ".arm") 7773 return parseDirectiveARM(DirectiveID.getLoc()); 7774 else if (IDVal == ".thumb_func") 7775 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7776 else if (IDVal == ".code") 7777 return parseDirectiveCode(DirectiveID.getLoc()); 7778 else if (IDVal == ".syntax") 7779 return parseDirectiveSyntax(DirectiveID.getLoc()); 7780 else if (IDVal == ".unreq") 7781 return parseDirectiveUnreq(DirectiveID.getLoc()); 7782 else if (IDVal == ".arch") 7783 return parseDirectiveArch(DirectiveID.getLoc()); 7784 else if (IDVal == ".eabi_attribute") 7785 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7786 else if (IDVal == ".fnstart") 7787 return parseDirectiveFnStart(DirectiveID.getLoc()); 7788 else if (IDVal == ".fnend") 7789 return parseDirectiveFnEnd(DirectiveID.getLoc()); 7790 else if (IDVal == ".cantunwind") 7791 return parseDirectiveCantUnwind(DirectiveID.getLoc()); 7792 else if (IDVal == ".personality") 7793 return parseDirectivePersonality(DirectiveID.getLoc()); 7794 else if (IDVal == ".handlerdata") 7795 return parseDirectiveHandlerData(DirectiveID.getLoc()); 7796 else if (IDVal == ".setfp") 7797 return parseDirectiveSetFP(DirectiveID.getLoc()); 7798 else if (IDVal == ".pad") 7799 return parseDirectivePad(DirectiveID.getLoc()); 7800 else if (IDVal == ".save") 7801 return parseDirectiveRegSave(DirectiveID.getLoc(), false); 7802 else if (IDVal == ".vsave") 7803 return parseDirectiveRegSave(DirectiveID.getLoc(), true); 7804 return true; 7805 } 7806 7807 /// parseDirectiveWord 7808 /// ::= .word [ expression (, expression)* ] 7809 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 7810 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7811 for (;;) { 7812 const MCExpr *Value; 7813 if (getParser().parseExpression(Value)) 7814 return true; 7815 7816 getParser().getStreamer().EmitValue(Value, Size); 7817 7818 if (getLexer().is(AsmToken::EndOfStatement)) 7819 break; 7820 7821 // FIXME: Improve diagnostic. 7822 if (getLexer().isNot(AsmToken::Comma)) 7823 return Error(L, "unexpected token in directive"); 7824 Parser.Lex(); 7825 } 7826 } 7827 7828 Parser.Lex(); 7829 return false; 7830 } 7831 7832 /// parseDirectiveThumb 7833 /// ::= .thumb 7834 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 7835 if (getLexer().isNot(AsmToken::EndOfStatement)) 7836 return Error(L, "unexpected token in directive"); 7837 Parser.Lex(); 7838 7839 if (!hasThumb()) 7840 return Error(L, "target does not support Thumb mode"); 7841 7842 if (!isThumb()) 7843 SwitchMode(); 7844 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7845 return false; 7846 } 7847 7848 /// parseDirectiveARM 7849 /// ::= .arm 7850 bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 7851 if (getLexer().isNot(AsmToken::EndOfStatement)) 7852 return Error(L, "unexpected token in directive"); 7853 Parser.Lex(); 7854 7855 if (!hasARM()) 7856 return Error(L, "target does not support ARM mode"); 7857 7858 if (isThumb()) 7859 SwitchMode(); 7860 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7861 return false; 7862 } 7863 7864 /// parseDirectiveThumbFunc 7865 /// ::= .thumbfunc symbol_name 7866 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 7867 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 7868 bool isMachO = MAI->hasSubsectionsViaSymbols(); 7869 StringRef Name; 7870 bool needFuncName = true; 7871 7872 // Darwin asm has (optionally) function name after .thumb_func direction 7873 // ELF doesn't 7874 if (isMachO) { 7875 const AsmToken &Tok = Parser.getTok(); 7876 if (Tok.isNot(AsmToken::EndOfStatement)) { 7877 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 7878 return Error(L, "unexpected token in .thumb_func directive"); 7879 Name = Tok.getIdentifier(); 7880 Parser.Lex(); // Consume the identifier token. 7881 needFuncName = false; 7882 } 7883 } 7884 7885 if (getLexer().isNot(AsmToken::EndOfStatement)) 7886 return Error(L, "unexpected token in directive"); 7887 7888 // Eat the end of statement and any blank lines that follow. 7889 while (getLexer().is(AsmToken::EndOfStatement)) 7890 Parser.Lex(); 7891 7892 // FIXME: assuming function name will be the line following .thumb_func 7893 // We really should be checking the next symbol definition even if there's 7894 // stuff in between. 7895 if (needFuncName) { 7896 Name = Parser.getTok().getIdentifier(); 7897 } 7898 7899 // Mark symbol as a thumb symbol. 7900 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 7901 getParser().getStreamer().EmitThumbFunc(Func); 7902 return false; 7903 } 7904 7905 /// parseDirectiveSyntax 7906 /// ::= .syntax unified | divided 7907 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 7908 const AsmToken &Tok = Parser.getTok(); 7909 if (Tok.isNot(AsmToken::Identifier)) 7910 return Error(L, "unexpected token in .syntax directive"); 7911 StringRef Mode = Tok.getString(); 7912 if (Mode == "unified" || Mode == "UNIFIED") 7913 Parser.Lex(); 7914 else if (Mode == "divided" || Mode == "DIVIDED") 7915 return Error(L, "'.syntax divided' arm asssembly not supported"); 7916 else 7917 return Error(L, "unrecognized syntax mode in .syntax directive"); 7918 7919 if (getLexer().isNot(AsmToken::EndOfStatement)) 7920 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7921 Parser.Lex(); 7922 7923 // TODO tell the MC streamer the mode 7924 // getParser().getStreamer().Emit???(); 7925 return false; 7926 } 7927 7928 /// parseDirectiveCode 7929 /// ::= .code 16 | 32 7930 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 7931 const AsmToken &Tok = Parser.getTok(); 7932 if (Tok.isNot(AsmToken::Integer)) 7933 return Error(L, "unexpected token in .code directive"); 7934 int64_t Val = Parser.getTok().getIntVal(); 7935 if (Val == 16) 7936 Parser.Lex(); 7937 else if (Val == 32) 7938 Parser.Lex(); 7939 else 7940 return Error(L, "invalid operand to .code directive"); 7941 7942 if (getLexer().isNot(AsmToken::EndOfStatement)) 7943 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7944 Parser.Lex(); 7945 7946 if (Val == 16) { 7947 if (!hasThumb()) 7948 return Error(L, "target does not support Thumb mode"); 7949 7950 if (!isThumb()) 7951 SwitchMode(); 7952 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7953 } else { 7954 if (!hasARM()) 7955 return Error(L, "target does not support ARM mode"); 7956 7957 if (isThumb()) 7958 SwitchMode(); 7959 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7960 } 7961 7962 return false; 7963 } 7964 7965 /// parseDirectiveReq 7966 /// ::= name .req registername 7967 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 7968 Parser.Lex(); // Eat the '.req' token. 7969 unsigned Reg; 7970 SMLoc SRegLoc, ERegLoc; 7971 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 7972 Parser.eatToEndOfStatement(); 7973 return Error(SRegLoc, "register name expected"); 7974 } 7975 7976 // Shouldn't be anything else. 7977 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7978 Parser.eatToEndOfStatement(); 7979 return Error(Parser.getTok().getLoc(), 7980 "unexpected input in .req directive."); 7981 } 7982 7983 Parser.Lex(); // Consume the EndOfStatement 7984 7985 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 7986 return Error(SRegLoc, "redefinition of '" + Name + 7987 "' does not match original."); 7988 7989 return false; 7990 } 7991 7992 /// parseDirectiveUneq 7993 /// ::= .unreq registername 7994 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 7995 if (Parser.getTok().isNot(AsmToken::Identifier)) { 7996 Parser.eatToEndOfStatement(); 7997 return Error(L, "unexpected input in .unreq directive."); 7998 } 7999 RegisterReqs.erase(Parser.getTok().getIdentifier()); 8000 Parser.Lex(); // Eat the identifier. 8001 return false; 8002 } 8003 8004 /// parseDirectiveArch 8005 /// ::= .arch token 8006 bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 8007 return true; 8008 } 8009 8010 /// parseDirectiveEabiAttr 8011 /// ::= .eabi_attribute int, int 8012 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 8013 return true; 8014 } 8015 8016 /// parseDirectiveFnStart 8017 /// ::= .fnstart 8018 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { 8019 if (FnStartLoc.isValid()) { 8020 Error(L, ".fnstart starts before the end of previous one"); 8021 Error(FnStartLoc, "previous .fnstart starts here"); 8022 return true; 8023 } 8024 8025 FnStartLoc = L; 8026 getParser().getStreamer().EmitFnStart(); 8027 return false; 8028 } 8029 8030 /// parseDirectiveFnEnd 8031 /// ::= .fnend 8032 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { 8033 // Check the ordering of unwind directives 8034 if (!FnStartLoc.isValid()) 8035 return Error(L, ".fnstart must precede .fnend directive"); 8036 8037 // Reset the unwind directives parser state 8038 resetUnwindDirectiveParserState(); 8039 8040 getParser().getStreamer().EmitFnEnd(); 8041 return false; 8042 } 8043 8044 /// parseDirectiveCantUnwind 8045 /// ::= .cantunwind 8046 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { 8047 // Check the ordering of unwind directives 8048 CantUnwindLoc = L; 8049 if (!FnStartLoc.isValid()) 8050 return Error(L, ".fnstart must precede .cantunwind directive"); 8051 if (HandlerDataLoc.isValid()) { 8052 Error(L, ".cantunwind can't be used with .handlerdata directive"); 8053 Error(HandlerDataLoc, ".handlerdata was specified here"); 8054 return true; 8055 } 8056 if (PersonalityLoc.isValid()) { 8057 Error(L, ".cantunwind can't be used with .personality directive"); 8058 Error(PersonalityLoc, ".personality was specified here"); 8059 return true; 8060 } 8061 8062 getParser().getStreamer().EmitCantUnwind(); 8063 return false; 8064 } 8065 8066 /// parseDirectivePersonality 8067 /// ::= .personality name 8068 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { 8069 // Check the ordering of unwind directives 8070 PersonalityLoc = L; 8071 if (!FnStartLoc.isValid()) 8072 return Error(L, ".fnstart must precede .personality directive"); 8073 if (CantUnwindLoc.isValid()) { 8074 Error(L, ".personality can't be used with .cantunwind directive"); 8075 Error(CantUnwindLoc, ".cantunwind was specified here"); 8076 return true; 8077 } 8078 if (HandlerDataLoc.isValid()) { 8079 Error(L, ".personality must precede .handlerdata directive"); 8080 Error(HandlerDataLoc, ".handlerdata was specified here"); 8081 return true; 8082 } 8083 8084 // Parse the name of the personality routine 8085 if (Parser.getTok().isNot(AsmToken::Identifier)) { 8086 Parser.eatToEndOfStatement(); 8087 return Error(L, "unexpected input in .personality directive."); 8088 } 8089 StringRef Name(Parser.getTok().getIdentifier()); 8090 Parser.Lex(); 8091 8092 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name); 8093 getParser().getStreamer().EmitPersonality(PR); 8094 return false; 8095 } 8096 8097 /// parseDirectiveHandlerData 8098 /// ::= .handlerdata 8099 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { 8100 // Check the ordering of unwind directives 8101 HandlerDataLoc = L; 8102 if (!FnStartLoc.isValid()) 8103 return Error(L, ".fnstart must precede .personality directive"); 8104 if (CantUnwindLoc.isValid()) { 8105 Error(L, ".handlerdata can't be used with .cantunwind directive"); 8106 Error(CantUnwindLoc, ".cantunwind was specified here"); 8107 return true; 8108 } 8109 8110 getParser().getStreamer().EmitHandlerData(); 8111 return false; 8112 } 8113 8114 /// parseDirectiveSetFP 8115 /// ::= .setfp fpreg, spreg [, offset] 8116 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { 8117 // Check the ordering of unwind directives 8118 if (!FnStartLoc.isValid()) 8119 return Error(L, ".fnstart must precede .setfp directive"); 8120 if (HandlerDataLoc.isValid()) 8121 return Error(L, ".setfp must precede .handlerdata directive"); 8122 8123 // Parse fpreg 8124 SMLoc NewFPRegLoc = Parser.getTok().getLoc(); 8125 int NewFPReg = tryParseRegister(); 8126 if (NewFPReg == -1) 8127 return Error(NewFPRegLoc, "frame pointer register expected"); 8128 8129 // Consume comma 8130 if (!Parser.getTok().is(AsmToken::Comma)) 8131 return Error(Parser.getTok().getLoc(), "comma expected"); 8132 Parser.Lex(); // skip comma 8133 8134 // Parse spreg 8135 SMLoc NewSPRegLoc = Parser.getTok().getLoc(); 8136 int NewSPReg = tryParseRegister(); 8137 if (NewSPReg == -1) 8138 return Error(NewSPRegLoc, "stack pointer register expected"); 8139 8140 if (NewSPReg != ARM::SP && NewSPReg != FPReg) 8141 return Error(NewSPRegLoc, 8142 "register should be either $sp or the latest fp register"); 8143 8144 // Update the frame pointer register 8145 FPReg = NewFPReg; 8146 8147 // Parse offset 8148 int64_t Offset = 0; 8149 if (Parser.getTok().is(AsmToken::Comma)) { 8150 Parser.Lex(); // skip comma 8151 8152 if (Parser.getTok().isNot(AsmToken::Hash) && 8153 Parser.getTok().isNot(AsmToken::Dollar)) { 8154 return Error(Parser.getTok().getLoc(), "'#' expected"); 8155 } 8156 Parser.Lex(); // skip hash token. 8157 8158 const MCExpr *OffsetExpr; 8159 SMLoc ExLoc = Parser.getTok().getLoc(); 8160 SMLoc EndLoc; 8161 if (getParser().parseExpression(OffsetExpr, EndLoc)) 8162 return Error(ExLoc, "malformed setfp offset"); 8163 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8164 if (!CE) 8165 return Error(ExLoc, "setfp offset must be an immediate"); 8166 8167 Offset = CE->getValue(); 8168 } 8169 8170 getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg), 8171 static_cast<unsigned>(NewSPReg), 8172 Offset); 8173 return false; 8174 } 8175 8176 /// parseDirective 8177 /// ::= .pad offset 8178 bool ARMAsmParser::parseDirectivePad(SMLoc L) { 8179 // Check the ordering of unwind directives 8180 if (!FnStartLoc.isValid()) 8181 return Error(L, ".fnstart must precede .pad directive"); 8182 if (HandlerDataLoc.isValid()) 8183 return Error(L, ".pad must precede .handlerdata directive"); 8184 8185 // Parse the offset 8186 if (Parser.getTok().isNot(AsmToken::Hash) && 8187 Parser.getTok().isNot(AsmToken::Dollar)) { 8188 return Error(Parser.getTok().getLoc(), "'#' expected"); 8189 } 8190 Parser.Lex(); // skip hash token. 8191 8192 const MCExpr *OffsetExpr; 8193 SMLoc ExLoc = Parser.getTok().getLoc(); 8194 SMLoc EndLoc; 8195 if (getParser().parseExpression(OffsetExpr, EndLoc)) 8196 return Error(ExLoc, "malformed pad offset"); 8197 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8198 if (!CE) 8199 return Error(ExLoc, "pad offset must be an immediate"); 8200 8201 getParser().getStreamer().EmitPad(CE->getValue()); 8202 return false; 8203 } 8204 8205 /// parseDirectiveRegSave 8206 /// ::= .save { registers } 8207 /// ::= .vsave { registers } 8208 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { 8209 // Check the ordering of unwind directives 8210 if (!FnStartLoc.isValid()) 8211 return Error(L, ".fnstart must precede .save or .vsave directives"); 8212 if (HandlerDataLoc.isValid()) 8213 return Error(L, ".save or .vsave must precede .handlerdata directive"); 8214 8215 // Parse the register list 8216 SmallVector<MCParsedAsmOperand*, 1> Operands; 8217 if (parseRegisterList(Operands)) 8218 return true; 8219 ARMOperand *Op = (ARMOperand*)Operands[0]; 8220 if (!IsVector && !Op->isRegList()) 8221 return Error(L, ".save expects GPR registers"); 8222 if (IsVector && !Op->isDPRRegList()) 8223 return Error(L, ".vsave expects DPR registers"); 8224 8225 getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector); 8226 return false; 8227 } 8228 8229 /// Force static initialization. 8230 extern "C" void LLVMInitializeARMAsmParser() { 8231 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 8232 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 8233 } 8234 8235 #define GET_REGISTER_MATCHER 8236 #define GET_SUBTARGET_FEATURE_NAME 8237 #define GET_MATCHER_IMPLEMENTATION 8238 #include "ARMGenAsmMatcher.inc" 8239 8240 // Define this matcher function after the auto-generated include so we 8241 // have the match class enum definitions. 8242 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp, 8243 unsigned Kind) { 8244 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp); 8245 // If the kind is a token for a literal immediate, check if our asm 8246 // operand matches. This is for InstAliases which have a fixed-value 8247 // immediate in the syntax. 8248 if (Kind == MCK__35_0 && Op->isImm()) { 8249 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 8250 if (!CE) 8251 return Match_InvalidOperand; 8252 if (CE->getValue() == 0) 8253 return Match_Success; 8254 } 8255 return Match_InvalidOperand; 8256 } 8257