1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
49 
50 using namespace llvm;
51 
52 namespace {
53 
54 class ARMOperand;
55 
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
57 
58 class UnwindContext {
59   MCAsmParser &Parser;
60 
61   typedef SmallVector<SMLoc, 4> Locs;
62 
63   Locs FnStartLocs;
64   Locs CantUnwindLocs;
65   Locs PersonalityLocs;
66   Locs PersonalityIndexLocs;
67   Locs HandlerDataLocs;
68   int FPReg;
69 
70 public:
71   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
72 
73   bool hasFnStart() const { return !FnStartLocs.empty(); }
74   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76   bool hasPersonality() const {
77     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
78   }
79 
80   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
85 
86   void saveFPReg(int Reg) { FPReg = Reg; }
87   int getFPReg() const { return FPReg; }
88 
89   void emitFnStartLocNotes() const {
90     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
91          FI != FE; ++FI)
92       Parser.Note(*FI, ".fnstart was specified here");
93   }
94   void emitCantUnwindLocNotes() const {
95     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
97       Parser.Note(*UI, ".cantunwind was specified here");
98   }
99   void emitHandlerDataLocNotes() const {
100     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
102       Parser.Note(*HI, ".handlerdata was specified here");
103   }
104   void emitPersonalityLocNotes() const {
105     for (Locs::const_iterator PI = PersonalityLocs.begin(),
106                               PE = PersonalityLocs.end(),
107                               PII = PersonalityIndexLocs.begin(),
108                               PIE = PersonalityIndexLocs.end();
109          PI != PE || PII != PIE;) {
110       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111         Parser.Note(*PI++, ".personality was specified here");
112       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113         Parser.Note(*PII++, ".personalityindex was specified here");
114       else
115         llvm_unreachable(".personality and .personalityindex cannot be "
116                          "at the same location");
117     }
118   }
119 
120   void reset() {
121     FnStartLocs = Locs();
122     CantUnwindLocs = Locs();
123     PersonalityLocs = Locs();
124     HandlerDataLocs = Locs();
125     PersonalityIndexLocs = Locs();
126     FPReg = ARM::SP;
127   }
128 };
129 
130 class ARMAsmParser : public MCTargetAsmParser {
131   MCSubtargetInfo &STI;
132   MCAsmParser &Parser;
133   const MCInstrInfo &MII;
134   const MCRegisterInfo *MRI;
135   UnwindContext UC;
136 
137   ARMTargetStreamer &getTargetStreamer() {
138     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
139     return static_cast<ARMTargetStreamer &>(TS);
140   }
141 
142   // Map of register aliases registers via the .req directive.
143   StringMap<unsigned> RegisterReqs;
144 
145   bool NextSymbolIsThumb;
146 
147   struct {
148     ARMCC::CondCodes Cond;    // Condition for IT block.
149     unsigned Mask:4;          // Condition mask for instructions.
150                               // Starting at first 1 (from lsb).
151                               //   '1'  condition as indicated in IT.
152                               //   '0'  inverse of condition (else).
153                               // Count of instructions in IT block is
154                               // 4 - trailingzeroes(mask)
155 
156     bool FirstCond;           // Explicit flag for when we're parsing the
157                               // First instruction in the IT block. It's
158                               // implied in the mask, so needs special
159                               // handling.
160 
161     unsigned CurPosition;     // Current position in parsing of IT
162                               // block. In range [0,3]. Initialized
163                               // according to count of instructions in block.
164                               // ~0U if no active IT block.
165   } ITState;
166   bool inITBlock() { return ITState.CurPosition != ~0U;}
167   void forwardITPosition() {
168     if (!inITBlock()) return;
169     // Move to the next instruction in the IT block, if there is one. If not,
170     // mark the block as done.
171     unsigned TZ = countTrailingZeros(ITState.Mask);
172     if (++ITState.CurPosition == 5 - TZ)
173       ITState.CurPosition = ~0U; // Done with the IT block after this.
174   }
175 
176 
177   MCAsmParser &getParser() const { return Parser; }
178   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
179 
180   void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
181     return Parser.Note(L, Msg, Ranges);
182   }
183   bool Warning(SMLoc L, const Twine &Msg,
184                ArrayRef<SMRange> Ranges = None) {
185     return Parser.Warning(L, Msg, Ranges);
186   }
187   bool Error(SMLoc L, const Twine &Msg,
188              ArrayRef<SMRange> Ranges = None) {
189     return Parser.Error(L, Msg, Ranges);
190   }
191 
192   int tryParseRegister();
193   bool tryParseRegisterWithWriteBack(OperandVector &);
194   int tryParseShiftRegister(OperandVector &);
195   bool parseRegisterList(OperandVector &);
196   bool parseMemory(OperandVector &);
197   bool parseOperand(OperandVector &, StringRef Mnemonic);
198   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
199   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
200                               unsigned &ShiftAmount);
201   bool parseLiteralValues(unsigned Size, SMLoc L);
202   bool parseDirectiveThumb(SMLoc L);
203   bool parseDirectiveARM(SMLoc L);
204   bool parseDirectiveThumbFunc(SMLoc L);
205   bool parseDirectiveCode(SMLoc L);
206   bool parseDirectiveSyntax(SMLoc L);
207   bool parseDirectiveReq(StringRef Name, SMLoc L);
208   bool parseDirectiveUnreq(SMLoc L);
209   bool parseDirectiveArch(SMLoc L);
210   bool parseDirectiveEabiAttr(SMLoc L);
211   bool parseDirectiveCPU(SMLoc L);
212   bool parseDirectiveFPU(SMLoc L);
213   bool parseDirectiveFnStart(SMLoc L);
214   bool parseDirectiveFnEnd(SMLoc L);
215   bool parseDirectiveCantUnwind(SMLoc L);
216   bool parseDirectivePersonality(SMLoc L);
217   bool parseDirectiveHandlerData(SMLoc L);
218   bool parseDirectiveSetFP(SMLoc L);
219   bool parseDirectivePad(SMLoc L);
220   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
221   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
222   bool parseDirectiveLtorg(SMLoc L);
223   bool parseDirectiveEven(SMLoc L);
224   bool parseDirectivePersonalityIndex(SMLoc L);
225   bool parseDirectiveUnwindRaw(SMLoc L);
226   bool parseDirectiveTLSDescSeq(SMLoc L);
227   bool parseDirectiveMovSP(SMLoc L);
228   bool parseDirectiveObjectArch(SMLoc L);
229   bool parseDirectiveArchExtension(SMLoc L);
230   bool parseDirectiveAlign(SMLoc L);
231   bool parseDirectiveThumbSet(SMLoc L);
232 
233   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
234                           bool &CarrySetting, unsigned &ProcessorIMod,
235                           StringRef &ITMask);
236   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
237                              bool &CanAcceptCarrySet,
238                              bool &CanAcceptPredicationCode);
239 
240   bool isThumb() const {
241     // FIXME: Can tablegen auto-generate this?
242     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
243   }
244   bool isThumbOne() const {
245     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
246   }
247   bool isThumbTwo() const {
248     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
249   }
250   bool hasThumb() const {
251     return STI.getFeatureBits() & ARM::HasV4TOps;
252   }
253   bool hasV6Ops() const {
254     return STI.getFeatureBits() & ARM::HasV6Ops;
255   }
256   bool hasV6MOps() const {
257     return STI.getFeatureBits() & ARM::HasV6MOps;
258   }
259   bool hasV7Ops() const {
260     return STI.getFeatureBits() & ARM::HasV7Ops;
261   }
262   bool hasV8Ops() const {
263     return STI.getFeatureBits() & ARM::HasV8Ops;
264   }
265   bool hasARM() const {
266     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
267   }
268 
269   void SwitchMode() {
270     uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
271     setAvailableFeatures(FB);
272   }
273   bool isMClass() const {
274     return STI.getFeatureBits() & ARM::FeatureMClass;
275   }
276 
277   /// @name Auto-generated Match Functions
278   /// {
279 
280 #define GET_ASSEMBLER_HEADER
281 #include "ARMGenAsmMatcher.inc"
282 
283   /// }
284 
285   OperandMatchResultTy parseITCondCode(OperandVector &);
286   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
287   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
288   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
289   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
290   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
291   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
292   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
293   OperandMatchResultTy parseBankedRegOperand(OperandVector &);
294   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
295                                    int High);
296   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
297     return parsePKHImm(O, "lsl", 0, 31);
298   }
299   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
300     return parsePKHImm(O, "asr", 1, 32);
301   }
302   OperandMatchResultTy parseSetEndImm(OperandVector &);
303   OperandMatchResultTy parseShifterImm(OperandVector &);
304   OperandMatchResultTy parseRotImm(OperandVector &);
305   OperandMatchResultTy parseBitfield(OperandVector &);
306   OperandMatchResultTy parsePostIdxReg(OperandVector &);
307   OperandMatchResultTy parseAM3Offset(OperandVector &);
308   OperandMatchResultTy parseFPImm(OperandVector &);
309   OperandMatchResultTy parseVectorList(OperandVector &);
310   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
311                                        SMLoc &EndLoc);
312 
313   // Asm Match Converter Methods
314   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
315   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
316 
317   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
318   bool processInstruction(MCInst &Inst, const OperandVector &Ops);
319   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
320   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
321 
322 public:
323   enum ARMMatchResultTy {
324     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
325     Match_RequiresNotITBlock,
326     Match_RequiresV6,
327     Match_RequiresThumb2,
328 #define GET_OPERAND_DIAGNOSTIC_TYPES
329 #include "ARMGenAsmMatcher.inc"
330 
331   };
332 
333   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
334                const MCInstrInfo &MII,
335                const MCTargetOptions &Options)
336       : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
337     MCAsmParserExtension::Initialize(_Parser);
338 
339     // Cache the MCRegisterInfo.
340     MRI = getContext().getRegisterInfo();
341 
342     // Initialize the set of available features.
343     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
344 
345     // Not in an ITBlock to start with.
346     ITState.CurPosition = ~0U;
347 
348     NextSymbolIsThumb = false;
349   }
350 
351   // Implementation of the MCTargetAsmParser interface:
352   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
353   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
354                         SMLoc NameLoc, OperandVector &Operands) override;
355   bool ParseDirective(AsmToken DirectiveID) override;
356 
357   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
358                                       unsigned Kind) override;
359   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
360 
361   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
362                                OperandVector &Operands, MCStreamer &Out,
363                                uint64_t &ErrorInfo,
364                                bool MatchingInlineAsm) override;
365   void onLabelParsed(MCSymbol *Symbol) override;
366 };
367 } // end anonymous namespace
368 
369 namespace {
370 
371 /// ARMOperand - Instances of this class represent a parsed ARM machine
372 /// operand.
373 class ARMOperand : public MCParsedAsmOperand {
374   enum KindTy {
375     k_CondCode,
376     k_CCOut,
377     k_ITCondMask,
378     k_CoprocNum,
379     k_CoprocReg,
380     k_CoprocOption,
381     k_Immediate,
382     k_MemBarrierOpt,
383     k_InstSyncBarrierOpt,
384     k_Memory,
385     k_PostIndexRegister,
386     k_MSRMask,
387     k_BankedReg,
388     k_ProcIFlags,
389     k_VectorIndex,
390     k_Register,
391     k_RegisterList,
392     k_DPRRegisterList,
393     k_SPRRegisterList,
394     k_VectorList,
395     k_VectorListAllLanes,
396     k_VectorListIndexed,
397     k_ShiftedRegister,
398     k_ShiftedImmediate,
399     k_ShifterImmediate,
400     k_RotateImmediate,
401     k_BitfieldDescriptor,
402     k_Token
403   } Kind;
404 
405   SMLoc StartLoc, EndLoc, AlignmentLoc;
406   SmallVector<unsigned, 8> Registers;
407 
408   struct CCOp {
409     ARMCC::CondCodes Val;
410   };
411 
412   struct CopOp {
413     unsigned Val;
414   };
415 
416   struct CoprocOptionOp {
417     unsigned Val;
418   };
419 
420   struct ITMaskOp {
421     unsigned Mask:4;
422   };
423 
424   struct MBOptOp {
425     ARM_MB::MemBOpt Val;
426   };
427 
428   struct ISBOptOp {
429     ARM_ISB::InstSyncBOpt Val;
430   };
431 
432   struct IFlagsOp {
433     ARM_PROC::IFlags Val;
434   };
435 
436   struct MMaskOp {
437     unsigned Val;
438   };
439 
440   struct BankedRegOp {
441     unsigned Val;
442   };
443 
444   struct TokOp {
445     const char *Data;
446     unsigned Length;
447   };
448 
449   struct RegOp {
450     unsigned RegNum;
451   };
452 
453   // A vector register list is a sequential list of 1 to 4 registers.
454   struct VectorListOp {
455     unsigned RegNum;
456     unsigned Count;
457     unsigned LaneIndex;
458     bool isDoubleSpaced;
459   };
460 
461   struct VectorIndexOp {
462     unsigned Val;
463   };
464 
465   struct ImmOp {
466     const MCExpr *Val;
467   };
468 
469   /// Combined record for all forms of ARM address expressions.
470   struct MemoryOp {
471     unsigned BaseRegNum;
472     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
473     // was specified.
474     const MCConstantExpr *OffsetImm;  // Offset immediate value
475     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
476     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
477     unsigned ShiftImm;        // shift for OffsetReg.
478     unsigned Alignment;       // 0 = no alignment specified
479     // n = alignment in bytes (2, 4, 8, 16, or 32)
480     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
481   };
482 
483   struct PostIdxRegOp {
484     unsigned RegNum;
485     bool isAdd;
486     ARM_AM::ShiftOpc ShiftTy;
487     unsigned ShiftImm;
488   };
489 
490   struct ShifterImmOp {
491     bool isASR;
492     unsigned Imm;
493   };
494 
495   struct RegShiftedRegOp {
496     ARM_AM::ShiftOpc ShiftTy;
497     unsigned SrcReg;
498     unsigned ShiftReg;
499     unsigned ShiftImm;
500   };
501 
502   struct RegShiftedImmOp {
503     ARM_AM::ShiftOpc ShiftTy;
504     unsigned SrcReg;
505     unsigned ShiftImm;
506   };
507 
508   struct RotImmOp {
509     unsigned Imm;
510   };
511 
512   struct BitfieldOp {
513     unsigned LSB;
514     unsigned Width;
515   };
516 
517   union {
518     struct CCOp CC;
519     struct CopOp Cop;
520     struct CoprocOptionOp CoprocOption;
521     struct MBOptOp MBOpt;
522     struct ISBOptOp ISBOpt;
523     struct ITMaskOp ITMask;
524     struct IFlagsOp IFlags;
525     struct MMaskOp MMask;
526     struct BankedRegOp BankedReg;
527     struct TokOp Tok;
528     struct RegOp Reg;
529     struct VectorListOp VectorList;
530     struct VectorIndexOp VectorIndex;
531     struct ImmOp Imm;
532     struct MemoryOp Memory;
533     struct PostIdxRegOp PostIdxReg;
534     struct ShifterImmOp ShifterImm;
535     struct RegShiftedRegOp RegShiftedReg;
536     struct RegShiftedImmOp RegShiftedImm;
537     struct RotImmOp RotImm;
538     struct BitfieldOp Bitfield;
539   };
540 
541 public:
542   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
543   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
544     Kind = o.Kind;
545     StartLoc = o.StartLoc;
546     EndLoc = o.EndLoc;
547     switch (Kind) {
548     case k_CondCode:
549       CC = o.CC;
550       break;
551     case k_ITCondMask:
552       ITMask = o.ITMask;
553       break;
554     case k_Token:
555       Tok = o.Tok;
556       break;
557     case k_CCOut:
558     case k_Register:
559       Reg = o.Reg;
560       break;
561     case k_RegisterList:
562     case k_DPRRegisterList:
563     case k_SPRRegisterList:
564       Registers = o.Registers;
565       break;
566     case k_VectorList:
567     case k_VectorListAllLanes:
568     case k_VectorListIndexed:
569       VectorList = o.VectorList;
570       break;
571     case k_CoprocNum:
572     case k_CoprocReg:
573       Cop = o.Cop;
574       break;
575     case k_CoprocOption:
576       CoprocOption = o.CoprocOption;
577       break;
578     case k_Immediate:
579       Imm = o.Imm;
580       break;
581     case k_MemBarrierOpt:
582       MBOpt = o.MBOpt;
583       break;
584     case k_InstSyncBarrierOpt:
585       ISBOpt = o.ISBOpt;
586     case k_Memory:
587       Memory = o.Memory;
588       break;
589     case k_PostIndexRegister:
590       PostIdxReg = o.PostIdxReg;
591       break;
592     case k_MSRMask:
593       MMask = o.MMask;
594       break;
595     case k_BankedReg:
596       BankedReg = o.BankedReg;
597       break;
598     case k_ProcIFlags:
599       IFlags = o.IFlags;
600       break;
601     case k_ShifterImmediate:
602       ShifterImm = o.ShifterImm;
603       break;
604     case k_ShiftedRegister:
605       RegShiftedReg = o.RegShiftedReg;
606       break;
607     case k_ShiftedImmediate:
608       RegShiftedImm = o.RegShiftedImm;
609       break;
610     case k_RotateImmediate:
611       RotImm = o.RotImm;
612       break;
613     case k_BitfieldDescriptor:
614       Bitfield = o.Bitfield;
615       break;
616     case k_VectorIndex:
617       VectorIndex = o.VectorIndex;
618       break;
619     }
620   }
621 
622   /// getStartLoc - Get the location of the first token of this operand.
623   SMLoc getStartLoc() const override { return StartLoc; }
624   /// getEndLoc - Get the location of the last token of this operand.
625   SMLoc getEndLoc() const override { return EndLoc; }
626   /// getLocRange - Get the range between the first and last token of this
627   /// operand.
628   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
629 
630   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
631   SMLoc getAlignmentLoc() const {
632     assert(Kind == k_Memory && "Invalid access!");
633     return AlignmentLoc;
634   }
635 
636   ARMCC::CondCodes getCondCode() const {
637     assert(Kind == k_CondCode && "Invalid access!");
638     return CC.Val;
639   }
640 
641   unsigned getCoproc() const {
642     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
643     return Cop.Val;
644   }
645 
646   StringRef getToken() const {
647     assert(Kind == k_Token && "Invalid access!");
648     return StringRef(Tok.Data, Tok.Length);
649   }
650 
651   unsigned getReg() const override {
652     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
653     return Reg.RegNum;
654   }
655 
656   const SmallVectorImpl<unsigned> &getRegList() const {
657     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
658             Kind == k_SPRRegisterList) && "Invalid access!");
659     return Registers;
660   }
661 
662   const MCExpr *getImm() const {
663     assert(isImm() && "Invalid access!");
664     return Imm.Val;
665   }
666 
667   unsigned getVectorIndex() const {
668     assert(Kind == k_VectorIndex && "Invalid access!");
669     return VectorIndex.Val;
670   }
671 
672   ARM_MB::MemBOpt getMemBarrierOpt() const {
673     assert(Kind == k_MemBarrierOpt && "Invalid access!");
674     return MBOpt.Val;
675   }
676 
677   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
678     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
679     return ISBOpt.Val;
680   }
681 
682   ARM_PROC::IFlags getProcIFlags() const {
683     assert(Kind == k_ProcIFlags && "Invalid access!");
684     return IFlags.Val;
685   }
686 
687   unsigned getMSRMask() const {
688     assert(Kind == k_MSRMask && "Invalid access!");
689     return MMask.Val;
690   }
691 
692   unsigned getBankedReg() const {
693     assert(Kind == k_BankedReg && "Invalid access!");
694     return BankedReg.Val;
695   }
696 
697   bool isCoprocNum() const { return Kind == k_CoprocNum; }
698   bool isCoprocReg() const { return Kind == k_CoprocReg; }
699   bool isCoprocOption() const { return Kind == k_CoprocOption; }
700   bool isCondCode() const { return Kind == k_CondCode; }
701   bool isCCOut() const { return Kind == k_CCOut; }
702   bool isITMask() const { return Kind == k_ITCondMask; }
703   bool isITCondCode() const { return Kind == k_CondCode; }
704   bool isImm() const override { return Kind == k_Immediate; }
705   // checks whether this operand is an unsigned offset which fits is a field
706   // of specified width and scaled by a specific number of bits
707   template<unsigned width, unsigned scale>
708   bool isUnsignedOffset() const {
709     if (!isImm()) return false;
710     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
711     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
712       int64_t Val = CE->getValue();
713       int64_t Align = 1LL << scale;
714       int64_t Max = Align * ((1LL << width) - 1);
715       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
716     }
717     return false;
718   }
719   // checks whether this operand is an signed offset which fits is a field
720   // of specified width and scaled by a specific number of bits
721   template<unsigned width, unsigned scale>
722   bool isSignedOffset() const {
723     if (!isImm()) return false;
724     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
725     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
726       int64_t Val = CE->getValue();
727       int64_t Align = 1LL << scale;
728       int64_t Max = Align * ((1LL << (width-1)) - 1);
729       int64_t Min = -Align * (1LL << (width-1));
730       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
731     }
732     return false;
733   }
734 
735   // checks whether this operand is a memory operand computed as an offset
736   // applied to PC. the offset may have 8 bits of magnitude and is represented
737   // with two bits of shift. textually it may be either [pc, #imm], #imm or
738   // relocable expression...
739   bool isThumbMemPC() const {
740     int64_t Val = 0;
741     if (isImm()) {
742       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
743       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
744       if (!CE) return false;
745       Val = CE->getValue();
746     }
747     else if (isMem()) {
748       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
749       if(Memory.BaseRegNum != ARM::PC) return false;
750       Val = Memory.OffsetImm->getValue();
751     }
752     else return false;
753     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
754   }
755   bool isFPImm() const {
756     if (!isImm()) return false;
757     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758     if (!CE) return false;
759     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
760     return Val != -1;
761   }
762   bool isFBits16() const {
763     if (!isImm()) return false;
764     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765     if (!CE) return false;
766     int64_t Value = CE->getValue();
767     return Value >= 0 && Value <= 16;
768   }
769   bool isFBits32() const {
770     if (!isImm()) return false;
771     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
772     if (!CE) return false;
773     int64_t Value = CE->getValue();
774     return Value >= 1 && Value <= 32;
775   }
776   bool isImm8s4() const {
777     if (!isImm()) return false;
778     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779     if (!CE) return false;
780     int64_t Value = CE->getValue();
781     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
782   }
783   bool isImm0_1020s4() const {
784     if (!isImm()) return false;
785     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
786     if (!CE) return false;
787     int64_t Value = CE->getValue();
788     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
789   }
790   bool isImm0_508s4() const {
791     if (!isImm()) return false;
792     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
793     if (!CE) return false;
794     int64_t Value = CE->getValue();
795     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
796   }
797   bool isImm0_508s4Neg() const {
798     if (!isImm()) return false;
799     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
800     if (!CE) return false;
801     int64_t Value = -CE->getValue();
802     // explicitly exclude zero. we want that to use the normal 0_508 version.
803     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
804   }
805   bool isImm0_239() const {
806     if (!isImm()) return false;
807     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
808     if (!CE) return false;
809     int64_t Value = CE->getValue();
810     return Value >= 0 && Value < 240;
811   }
812   bool isImm0_255() const {
813     if (!isImm()) return false;
814     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
815     if (!CE) return false;
816     int64_t Value = CE->getValue();
817     return Value >= 0 && Value < 256;
818   }
819   bool isImm0_4095() const {
820     if (!isImm()) return false;
821     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
822     if (!CE) return false;
823     int64_t Value = CE->getValue();
824     return Value >= 0 && Value < 4096;
825   }
826   bool isImm0_4095Neg() const {
827     if (!isImm()) return false;
828     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829     if (!CE) return false;
830     int64_t Value = -CE->getValue();
831     return Value > 0 && Value < 4096;
832   }
833   bool isImm0_1() const {
834     if (!isImm()) return false;
835     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
836     if (!CE) return false;
837     int64_t Value = CE->getValue();
838     return Value >= 0 && Value < 2;
839   }
840   bool isImm0_3() const {
841     if (!isImm()) return false;
842     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
843     if (!CE) return false;
844     int64_t Value = CE->getValue();
845     return Value >= 0 && Value < 4;
846   }
847   bool isImm0_7() const {
848     if (!isImm()) return false;
849     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
850     if (!CE) return false;
851     int64_t Value = CE->getValue();
852     return Value >= 0 && Value < 8;
853   }
854   bool isImm0_15() const {
855     if (!isImm()) return false;
856     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
857     if (!CE) return false;
858     int64_t Value = CE->getValue();
859     return Value >= 0 && Value < 16;
860   }
861   bool isImm0_31() const {
862     if (!isImm()) return false;
863     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
864     if (!CE) return false;
865     int64_t Value = CE->getValue();
866     return Value >= 0 && Value < 32;
867   }
868   bool isImm0_63() const {
869     if (!isImm()) return false;
870     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
871     if (!CE) return false;
872     int64_t Value = CE->getValue();
873     return Value >= 0 && Value < 64;
874   }
875   bool isImm8() const {
876     if (!isImm()) return false;
877     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
878     if (!CE) return false;
879     int64_t Value = CE->getValue();
880     return Value == 8;
881   }
882   bool isImm16() const {
883     if (!isImm()) return false;
884     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
885     if (!CE) return false;
886     int64_t Value = CE->getValue();
887     return Value == 16;
888   }
889   bool isImm32() const {
890     if (!isImm()) return false;
891     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
892     if (!CE) return false;
893     int64_t Value = CE->getValue();
894     return Value == 32;
895   }
896   bool isShrImm8() const {
897     if (!isImm()) return false;
898     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
899     if (!CE) return false;
900     int64_t Value = CE->getValue();
901     return Value > 0 && Value <= 8;
902   }
903   bool isShrImm16() const {
904     if (!isImm()) return false;
905     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
906     if (!CE) return false;
907     int64_t Value = CE->getValue();
908     return Value > 0 && Value <= 16;
909   }
910   bool isShrImm32() const {
911     if (!isImm()) return false;
912     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913     if (!CE) return false;
914     int64_t Value = CE->getValue();
915     return Value > 0 && Value <= 32;
916   }
917   bool isShrImm64() const {
918     if (!isImm()) return false;
919     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
920     if (!CE) return false;
921     int64_t Value = CE->getValue();
922     return Value > 0 && Value <= 64;
923   }
924   bool isImm1_7() const {
925     if (!isImm()) return false;
926     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927     if (!CE) return false;
928     int64_t Value = CE->getValue();
929     return Value > 0 && Value < 8;
930   }
931   bool isImm1_15() const {
932     if (!isImm()) return false;
933     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934     if (!CE) return false;
935     int64_t Value = CE->getValue();
936     return Value > 0 && Value < 16;
937   }
938   bool isImm1_31() const {
939     if (!isImm()) return false;
940     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941     if (!CE) return false;
942     int64_t Value = CE->getValue();
943     return Value > 0 && Value < 32;
944   }
945   bool isImm1_16() const {
946     if (!isImm()) return false;
947     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948     if (!CE) return false;
949     int64_t Value = CE->getValue();
950     return Value > 0 && Value < 17;
951   }
952   bool isImm1_32() const {
953     if (!isImm()) return false;
954     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955     if (!CE) return false;
956     int64_t Value = CE->getValue();
957     return Value > 0 && Value < 33;
958   }
959   bool isImm0_32() const {
960     if (!isImm()) return false;
961     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
962     if (!CE) return false;
963     int64_t Value = CE->getValue();
964     return Value >= 0 && Value < 33;
965   }
966   bool isImm0_65535() const {
967     if (!isImm()) return false;
968     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
969     if (!CE) return false;
970     int64_t Value = CE->getValue();
971     return Value >= 0 && Value < 65536;
972   }
973   bool isImm256_65535Expr() const {
974     if (!isImm()) return false;
975     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
976     // If it's not a constant expression, it'll generate a fixup and be
977     // handled later.
978     if (!CE) return true;
979     int64_t Value = CE->getValue();
980     return Value >= 256 && Value < 65536;
981   }
982   bool isImm0_65535Expr() const {
983     if (!isImm()) return false;
984     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
985     // If it's not a constant expression, it'll generate a fixup and be
986     // handled later.
987     if (!CE) return true;
988     int64_t Value = CE->getValue();
989     return Value >= 0 && Value < 65536;
990   }
991   bool isImm24bit() const {
992     if (!isImm()) return false;
993     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
994     if (!CE) return false;
995     int64_t Value = CE->getValue();
996     return Value >= 0 && Value <= 0xffffff;
997   }
998   bool isImmThumbSR() const {
999     if (!isImm()) return false;
1000     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1001     if (!CE) return false;
1002     int64_t Value = CE->getValue();
1003     return Value > 0 && Value < 33;
1004   }
1005   bool isPKHLSLImm() const {
1006     if (!isImm()) return false;
1007     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1008     if (!CE) return false;
1009     int64_t Value = CE->getValue();
1010     return Value >= 0 && Value < 32;
1011   }
1012   bool isPKHASRImm() const {
1013     if (!isImm()) return false;
1014     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1015     if (!CE) return false;
1016     int64_t Value = CE->getValue();
1017     return Value > 0 && Value <= 32;
1018   }
1019   bool isAdrLabel() const {
1020     // If we have an immediate that's not a constant, treat it as a label
1021     // reference needing a fixup. If it is a constant, but it can't fit
1022     // into shift immediate encoding, we reject it.
1023     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1024     else return (isARMSOImm() || isARMSOImmNeg());
1025   }
1026   bool isARMSOImm() const {
1027     if (!isImm()) return false;
1028     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1029     if (!CE) return false;
1030     int64_t Value = CE->getValue();
1031     return ARM_AM::getSOImmVal(Value) != -1;
1032   }
1033   bool isARMSOImmNot() const {
1034     if (!isImm()) return false;
1035     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1036     if (!CE) return false;
1037     int64_t Value = CE->getValue();
1038     return ARM_AM::getSOImmVal(~Value) != -1;
1039   }
1040   bool isARMSOImmNeg() const {
1041     if (!isImm()) return false;
1042     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1043     if (!CE) return false;
1044     int64_t Value = CE->getValue();
1045     // Only use this when not representable as a plain so_imm.
1046     return ARM_AM::getSOImmVal(Value) == -1 &&
1047       ARM_AM::getSOImmVal(-Value) != -1;
1048   }
1049   bool isT2SOImm() const {
1050     if (!isImm()) return false;
1051     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1052     if (!CE) return false;
1053     int64_t Value = CE->getValue();
1054     return ARM_AM::getT2SOImmVal(Value) != -1;
1055   }
1056   bool isT2SOImmNot() const {
1057     if (!isImm()) return false;
1058     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1059     if (!CE) return false;
1060     int64_t Value = CE->getValue();
1061     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1062       ARM_AM::getT2SOImmVal(~Value) != -1;
1063   }
1064   bool isT2SOImmNeg() const {
1065     if (!isImm()) return false;
1066     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1067     if (!CE) return false;
1068     int64_t Value = CE->getValue();
1069     // Only use this when not representable as a plain so_imm.
1070     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1071       ARM_AM::getT2SOImmVal(-Value) != -1;
1072   }
1073   bool isSetEndImm() const {
1074     if (!isImm()) return false;
1075     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1076     if (!CE) return false;
1077     int64_t Value = CE->getValue();
1078     return Value == 1 || Value == 0;
1079   }
1080   bool isReg() const override { return Kind == k_Register; }
1081   bool isRegList() const { return Kind == k_RegisterList; }
1082   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1083   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1084   bool isToken() const override { return Kind == k_Token; }
1085   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1086   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1087   bool isMem() const override { return Kind == k_Memory; }
1088   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1089   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1090   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1091   bool isRotImm() const { return Kind == k_RotateImmediate; }
1092   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1093   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1094   bool isPostIdxReg() const {
1095     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1096   }
1097   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1098     if (!isMem())
1099       return false;
1100     // No offset of any kind.
1101     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1102      (alignOK || Memory.Alignment == Alignment);
1103   }
1104   bool isMemPCRelImm12() const {
1105     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1106       return false;
1107     // Base register must be PC.
1108     if (Memory.BaseRegNum != ARM::PC)
1109       return false;
1110     // Immediate offset in range [-4095, 4095].
1111     if (!Memory.OffsetImm) return true;
1112     int64_t Val = Memory.OffsetImm->getValue();
1113     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1114   }
1115   bool isAlignedMemory() const {
1116     return isMemNoOffset(true);
1117   }
1118   bool isAlignedMemoryNone() const {
1119     return isMemNoOffset(false, 0);
1120   }
1121   bool isDupAlignedMemoryNone() const {
1122     return isMemNoOffset(false, 0);
1123   }
1124   bool isAlignedMemory16() const {
1125     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1126       return true;
1127     return isMemNoOffset(false, 0);
1128   }
1129   bool isDupAlignedMemory16() const {
1130     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1131       return true;
1132     return isMemNoOffset(false, 0);
1133   }
1134   bool isAlignedMemory32() const {
1135     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1136       return true;
1137     return isMemNoOffset(false, 0);
1138   }
1139   bool isDupAlignedMemory32() const {
1140     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1141       return true;
1142     return isMemNoOffset(false, 0);
1143   }
1144   bool isAlignedMemory64() const {
1145     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1146       return true;
1147     return isMemNoOffset(false, 0);
1148   }
1149   bool isDupAlignedMemory64() const {
1150     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1151       return true;
1152     return isMemNoOffset(false, 0);
1153   }
1154   bool isAlignedMemory64or128() const {
1155     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1156       return true;
1157     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1158       return true;
1159     return isMemNoOffset(false, 0);
1160   }
1161   bool isDupAlignedMemory64or128() const {
1162     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1163       return true;
1164     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1165       return true;
1166     return isMemNoOffset(false, 0);
1167   }
1168   bool isAlignedMemory64or128or256() const {
1169     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1170       return true;
1171     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1172       return true;
1173     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1174       return true;
1175     return isMemNoOffset(false, 0);
1176   }
1177   bool isAddrMode2() const {
1178     if (!isMem() || Memory.Alignment != 0) return false;
1179     // Check for register offset.
1180     if (Memory.OffsetRegNum) return true;
1181     // Immediate offset in range [-4095, 4095].
1182     if (!Memory.OffsetImm) return true;
1183     int64_t Val = Memory.OffsetImm->getValue();
1184     return Val > -4096 && Val < 4096;
1185   }
1186   bool isAM2OffsetImm() const {
1187     if (!isImm()) return false;
1188     // Immediate offset in range [-4095, 4095].
1189     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1190     if (!CE) return false;
1191     int64_t Val = CE->getValue();
1192     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1193   }
1194   bool isAddrMode3() const {
1195     // If we have an immediate that's not a constant, treat it as a label
1196     // reference needing a fixup. If it is a constant, it's something else
1197     // and we reject it.
1198     if (isImm() && !isa<MCConstantExpr>(getImm()))
1199       return true;
1200     if (!isMem() || Memory.Alignment != 0) return false;
1201     // No shifts are legal for AM3.
1202     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1203     // Check for register offset.
1204     if (Memory.OffsetRegNum) return true;
1205     // Immediate offset in range [-255, 255].
1206     if (!Memory.OffsetImm) return true;
1207     int64_t Val = Memory.OffsetImm->getValue();
1208     // The #-0 offset is encoded as INT32_MIN, and we have to check
1209     // for this too.
1210     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1211   }
1212   bool isAM3Offset() const {
1213     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1214       return false;
1215     if (Kind == k_PostIndexRegister)
1216       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1217     // Immediate offset in range [-255, 255].
1218     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1219     if (!CE) return false;
1220     int64_t Val = CE->getValue();
1221     // Special case, #-0 is INT32_MIN.
1222     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1223   }
1224   bool isAddrMode5() const {
1225     // If we have an immediate that's not a constant, treat it as a label
1226     // reference needing a fixup. If it is a constant, it's something else
1227     // and we reject it.
1228     if (isImm() && !isa<MCConstantExpr>(getImm()))
1229       return true;
1230     if (!isMem() || Memory.Alignment != 0) return false;
1231     // Check for register offset.
1232     if (Memory.OffsetRegNum) return false;
1233     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1234     if (!Memory.OffsetImm) return true;
1235     int64_t Val = Memory.OffsetImm->getValue();
1236     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1237       Val == INT32_MIN;
1238   }
1239   bool isMemTBB() const {
1240     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1241         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1242       return false;
1243     return true;
1244   }
1245   bool isMemTBH() const {
1246     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1247         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1248         Memory.Alignment != 0 )
1249       return false;
1250     return true;
1251   }
1252   bool isMemRegOffset() const {
1253     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1254       return false;
1255     return true;
1256   }
1257   bool isT2MemRegOffset() const {
1258     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1259         Memory.Alignment != 0)
1260       return false;
1261     // Only lsl #{0, 1, 2, 3} allowed.
1262     if (Memory.ShiftType == ARM_AM::no_shift)
1263       return true;
1264     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1265       return false;
1266     return true;
1267   }
1268   bool isMemThumbRR() const {
1269     // Thumb reg+reg addressing is simple. Just two registers, a base and
1270     // an offset. No shifts, negations or any other complicating factors.
1271     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1272         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1273       return false;
1274     return isARMLowRegister(Memory.BaseRegNum) &&
1275       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1276   }
1277   bool isMemThumbRIs4() const {
1278     if (!isMem() || Memory.OffsetRegNum != 0 ||
1279         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1280       return false;
1281     // Immediate offset, multiple of 4 in range [0, 124].
1282     if (!Memory.OffsetImm) return true;
1283     int64_t Val = Memory.OffsetImm->getValue();
1284     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1285   }
1286   bool isMemThumbRIs2() const {
1287     if (!isMem() || Memory.OffsetRegNum != 0 ||
1288         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1289       return false;
1290     // Immediate offset, multiple of 4 in range [0, 62].
1291     if (!Memory.OffsetImm) return true;
1292     int64_t Val = Memory.OffsetImm->getValue();
1293     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1294   }
1295   bool isMemThumbRIs1() const {
1296     if (!isMem() || Memory.OffsetRegNum != 0 ||
1297         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1298       return false;
1299     // Immediate offset in range [0, 31].
1300     if (!Memory.OffsetImm) return true;
1301     int64_t Val = Memory.OffsetImm->getValue();
1302     return Val >= 0 && Val <= 31;
1303   }
1304   bool isMemThumbSPI() const {
1305     if (!isMem() || Memory.OffsetRegNum != 0 ||
1306         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1307       return false;
1308     // Immediate offset, multiple of 4 in range [0, 1020].
1309     if (!Memory.OffsetImm) return true;
1310     int64_t Val = Memory.OffsetImm->getValue();
1311     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1312   }
1313   bool isMemImm8s4Offset() const {
1314     // If we have an immediate that's not a constant, treat it as a label
1315     // reference needing a fixup. If it is a constant, it's something else
1316     // and we reject it.
1317     if (isImm() && !isa<MCConstantExpr>(getImm()))
1318       return true;
1319     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1320       return false;
1321     // Immediate offset a multiple of 4 in range [-1020, 1020].
1322     if (!Memory.OffsetImm) return true;
1323     int64_t Val = Memory.OffsetImm->getValue();
1324     // Special case, #-0 is INT32_MIN.
1325     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1326   }
1327   bool isMemImm0_1020s4Offset() const {
1328     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1329       return false;
1330     // Immediate offset a multiple of 4 in range [0, 1020].
1331     if (!Memory.OffsetImm) return true;
1332     int64_t Val = Memory.OffsetImm->getValue();
1333     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1334   }
1335   bool isMemImm8Offset() const {
1336     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1337       return false;
1338     // Base reg of PC isn't allowed for these encodings.
1339     if (Memory.BaseRegNum == ARM::PC) return false;
1340     // Immediate offset in range [-255, 255].
1341     if (!Memory.OffsetImm) return true;
1342     int64_t Val = Memory.OffsetImm->getValue();
1343     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1344   }
1345   bool isMemPosImm8Offset() const {
1346     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1347       return false;
1348     // Immediate offset in range [0, 255].
1349     if (!Memory.OffsetImm) return true;
1350     int64_t Val = Memory.OffsetImm->getValue();
1351     return Val >= 0 && Val < 256;
1352   }
1353   bool isMemNegImm8Offset() const {
1354     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1355       return false;
1356     // Base reg of PC isn't allowed for these encodings.
1357     if (Memory.BaseRegNum == ARM::PC) return false;
1358     // Immediate offset in range [-255, -1].
1359     if (!Memory.OffsetImm) return false;
1360     int64_t Val = Memory.OffsetImm->getValue();
1361     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1362   }
1363   bool isMemUImm12Offset() const {
1364     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1365       return false;
1366     // Immediate offset in range [0, 4095].
1367     if (!Memory.OffsetImm) return true;
1368     int64_t Val = Memory.OffsetImm->getValue();
1369     return (Val >= 0 && Val < 4096);
1370   }
1371   bool isMemImm12Offset() const {
1372     // If we have an immediate that's not a constant, treat it as a label
1373     // reference needing a fixup. If it is a constant, it's something else
1374     // and we reject it.
1375     if (isImm() && !isa<MCConstantExpr>(getImm()))
1376       return true;
1377 
1378     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1379       return false;
1380     // Immediate offset in range [-4095, 4095].
1381     if (!Memory.OffsetImm) return true;
1382     int64_t Val = Memory.OffsetImm->getValue();
1383     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1384   }
1385   bool isPostIdxImm8() const {
1386     if (!isImm()) return false;
1387     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1388     if (!CE) return false;
1389     int64_t Val = CE->getValue();
1390     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1391   }
1392   bool isPostIdxImm8s4() const {
1393     if (!isImm()) return false;
1394     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1395     if (!CE) return false;
1396     int64_t Val = CE->getValue();
1397     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1398       (Val == INT32_MIN);
1399   }
1400 
1401   bool isMSRMask() const { return Kind == k_MSRMask; }
1402   bool isBankedReg() const { return Kind == k_BankedReg; }
1403   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1404 
1405   // NEON operands.
1406   bool isSingleSpacedVectorList() const {
1407     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1408   }
1409   bool isDoubleSpacedVectorList() const {
1410     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1411   }
1412   bool isVecListOneD() const {
1413     if (!isSingleSpacedVectorList()) return false;
1414     return VectorList.Count == 1;
1415   }
1416 
1417   bool isVecListDPair() const {
1418     if (!isSingleSpacedVectorList()) return false;
1419     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1420               .contains(VectorList.RegNum));
1421   }
1422 
1423   bool isVecListThreeD() const {
1424     if (!isSingleSpacedVectorList()) return false;
1425     return VectorList.Count == 3;
1426   }
1427 
1428   bool isVecListFourD() const {
1429     if (!isSingleSpacedVectorList()) return false;
1430     return VectorList.Count == 4;
1431   }
1432 
1433   bool isVecListDPairSpaced() const {
1434     if (Kind != k_VectorList) return false;
1435     if (isSingleSpacedVectorList()) return false;
1436     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1437               .contains(VectorList.RegNum));
1438   }
1439 
1440   bool isVecListThreeQ() const {
1441     if (!isDoubleSpacedVectorList()) return false;
1442     return VectorList.Count == 3;
1443   }
1444 
1445   bool isVecListFourQ() const {
1446     if (!isDoubleSpacedVectorList()) return false;
1447     return VectorList.Count == 4;
1448   }
1449 
1450   bool isSingleSpacedVectorAllLanes() const {
1451     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1452   }
1453   bool isDoubleSpacedVectorAllLanes() const {
1454     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1455   }
1456   bool isVecListOneDAllLanes() const {
1457     if (!isSingleSpacedVectorAllLanes()) return false;
1458     return VectorList.Count == 1;
1459   }
1460 
1461   bool isVecListDPairAllLanes() const {
1462     if (!isSingleSpacedVectorAllLanes()) return false;
1463     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1464               .contains(VectorList.RegNum));
1465   }
1466 
1467   bool isVecListDPairSpacedAllLanes() const {
1468     if (!isDoubleSpacedVectorAllLanes()) return false;
1469     return VectorList.Count == 2;
1470   }
1471 
1472   bool isVecListThreeDAllLanes() const {
1473     if (!isSingleSpacedVectorAllLanes()) return false;
1474     return VectorList.Count == 3;
1475   }
1476 
1477   bool isVecListThreeQAllLanes() const {
1478     if (!isDoubleSpacedVectorAllLanes()) return false;
1479     return VectorList.Count == 3;
1480   }
1481 
1482   bool isVecListFourDAllLanes() const {
1483     if (!isSingleSpacedVectorAllLanes()) return false;
1484     return VectorList.Count == 4;
1485   }
1486 
1487   bool isVecListFourQAllLanes() const {
1488     if (!isDoubleSpacedVectorAllLanes()) return false;
1489     return VectorList.Count == 4;
1490   }
1491 
1492   bool isSingleSpacedVectorIndexed() const {
1493     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1494   }
1495   bool isDoubleSpacedVectorIndexed() const {
1496     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1497   }
1498   bool isVecListOneDByteIndexed() const {
1499     if (!isSingleSpacedVectorIndexed()) return false;
1500     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1501   }
1502 
1503   bool isVecListOneDHWordIndexed() const {
1504     if (!isSingleSpacedVectorIndexed()) return false;
1505     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1506   }
1507 
1508   bool isVecListOneDWordIndexed() const {
1509     if (!isSingleSpacedVectorIndexed()) return false;
1510     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1511   }
1512 
1513   bool isVecListTwoDByteIndexed() const {
1514     if (!isSingleSpacedVectorIndexed()) return false;
1515     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1516   }
1517 
1518   bool isVecListTwoDHWordIndexed() const {
1519     if (!isSingleSpacedVectorIndexed()) return false;
1520     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1521   }
1522 
1523   bool isVecListTwoQWordIndexed() const {
1524     if (!isDoubleSpacedVectorIndexed()) return false;
1525     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1526   }
1527 
1528   bool isVecListTwoQHWordIndexed() const {
1529     if (!isDoubleSpacedVectorIndexed()) return false;
1530     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1531   }
1532 
1533   bool isVecListTwoDWordIndexed() const {
1534     if (!isSingleSpacedVectorIndexed()) return false;
1535     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1536   }
1537 
1538   bool isVecListThreeDByteIndexed() const {
1539     if (!isSingleSpacedVectorIndexed()) return false;
1540     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1541   }
1542 
1543   bool isVecListThreeDHWordIndexed() const {
1544     if (!isSingleSpacedVectorIndexed()) return false;
1545     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1546   }
1547 
1548   bool isVecListThreeQWordIndexed() const {
1549     if (!isDoubleSpacedVectorIndexed()) return false;
1550     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1551   }
1552 
1553   bool isVecListThreeQHWordIndexed() const {
1554     if (!isDoubleSpacedVectorIndexed()) return false;
1555     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1556   }
1557 
1558   bool isVecListThreeDWordIndexed() const {
1559     if (!isSingleSpacedVectorIndexed()) return false;
1560     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1561   }
1562 
1563   bool isVecListFourDByteIndexed() const {
1564     if (!isSingleSpacedVectorIndexed()) return false;
1565     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1566   }
1567 
1568   bool isVecListFourDHWordIndexed() const {
1569     if (!isSingleSpacedVectorIndexed()) return false;
1570     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1571   }
1572 
1573   bool isVecListFourQWordIndexed() const {
1574     if (!isDoubleSpacedVectorIndexed()) return false;
1575     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1576   }
1577 
1578   bool isVecListFourQHWordIndexed() const {
1579     if (!isDoubleSpacedVectorIndexed()) return false;
1580     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1581   }
1582 
1583   bool isVecListFourDWordIndexed() const {
1584     if (!isSingleSpacedVectorIndexed()) return false;
1585     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1586   }
1587 
1588   bool isVectorIndex8() const {
1589     if (Kind != k_VectorIndex) return false;
1590     return VectorIndex.Val < 8;
1591   }
1592   bool isVectorIndex16() const {
1593     if (Kind != k_VectorIndex) return false;
1594     return VectorIndex.Val < 4;
1595   }
1596   bool isVectorIndex32() const {
1597     if (Kind != k_VectorIndex) return false;
1598     return VectorIndex.Val < 2;
1599   }
1600 
1601   bool isNEONi8splat() const {
1602     if (!isImm()) return false;
1603     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1604     // Must be a constant.
1605     if (!CE) return false;
1606     int64_t Value = CE->getValue();
1607     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1608     // value.
1609     return Value >= 0 && Value < 256;
1610   }
1611 
1612   bool isNEONi16splat() const {
1613     if (isNEONByteReplicate(2))
1614       return false; // Leave that for bytes replication and forbid by default.
1615     if (!isImm())
1616       return false;
1617     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618     // Must be a constant.
1619     if (!CE) return false;
1620     int64_t Value = CE->getValue();
1621     // i16 value in the range [0,255] or [0x0100, 0xff00]
1622     return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1623   }
1624 
1625   bool isNEONi32splat() const {
1626     if (isNEONByteReplicate(4))
1627       return false; // Leave that for bytes replication and forbid by default.
1628     if (!isImm())
1629       return false;
1630     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1631     // Must be a constant.
1632     if (!CE) return false;
1633     int64_t Value = CE->getValue();
1634     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1635     return (Value >= 0 && Value < 256) ||
1636       (Value >= 0x0100 && Value <= 0xff00) ||
1637       (Value >= 0x010000 && Value <= 0xff0000) ||
1638       (Value >= 0x01000000 && Value <= 0xff000000);
1639   }
1640 
1641   bool isNEONByteReplicate(unsigned NumBytes) const {
1642     if (!isImm())
1643       return false;
1644     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1645     // Must be a constant.
1646     if (!CE)
1647       return false;
1648     int64_t Value = CE->getValue();
1649     if (!Value)
1650       return false; // Don't bother with zero.
1651 
1652     unsigned char B = Value & 0xff;
1653     for (unsigned i = 1; i < NumBytes; ++i) {
1654       Value >>= 8;
1655       if ((Value & 0xff) != B)
1656         return false;
1657     }
1658     return true;
1659   }
1660   bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1661   bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1662   bool isNEONi32vmov() const {
1663     if (isNEONByteReplicate(4))
1664       return false; // Let it to be classified as byte-replicate case.
1665     if (!isImm())
1666       return false;
1667     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668     // Must be a constant.
1669     if (!CE)
1670       return false;
1671     int64_t Value = CE->getValue();
1672     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1673     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1674     return (Value >= 0 && Value < 256) ||
1675       (Value >= 0x0100 && Value <= 0xff00) ||
1676       (Value >= 0x010000 && Value <= 0xff0000) ||
1677       (Value >= 0x01000000 && Value <= 0xff000000) ||
1678       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1679       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1680   }
1681   bool isNEONi32vmovNeg() const {
1682     if (!isImm()) return false;
1683     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1684     // Must be a constant.
1685     if (!CE) return false;
1686     int64_t Value = ~CE->getValue();
1687     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1688     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1689     return (Value >= 0 && Value < 256) ||
1690       (Value >= 0x0100 && Value <= 0xff00) ||
1691       (Value >= 0x010000 && Value <= 0xff0000) ||
1692       (Value >= 0x01000000 && Value <= 0xff000000) ||
1693       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1694       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1695   }
1696 
1697   bool isNEONi64splat() const {
1698     if (!isImm()) return false;
1699     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1700     // Must be a constant.
1701     if (!CE) return false;
1702     uint64_t Value = CE->getValue();
1703     // i64 value with each byte being either 0 or 0xff.
1704     for (unsigned i = 0; i < 8; ++i)
1705       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1706     return true;
1707   }
1708 
1709   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1710     // Add as immediates when possible.  Null MCExpr = 0.
1711     if (!Expr)
1712       Inst.addOperand(MCOperand::CreateImm(0));
1713     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1714       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1715     else
1716       Inst.addOperand(MCOperand::CreateExpr(Expr));
1717   }
1718 
1719   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1720     assert(N == 2 && "Invalid number of operands!");
1721     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1722     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1723     Inst.addOperand(MCOperand::CreateReg(RegNum));
1724   }
1725 
1726   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1727     assert(N == 1 && "Invalid number of operands!");
1728     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1729   }
1730 
1731   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1732     assert(N == 1 && "Invalid number of operands!");
1733     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1734   }
1735 
1736   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1737     assert(N == 1 && "Invalid number of operands!");
1738     Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1739   }
1740 
1741   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1742     assert(N == 1 && "Invalid number of operands!");
1743     Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1744   }
1745 
1746   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1747     assert(N == 1 && "Invalid number of operands!");
1748     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1749   }
1750 
1751   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1752     assert(N == 1 && "Invalid number of operands!");
1753     Inst.addOperand(MCOperand::CreateReg(getReg()));
1754   }
1755 
1756   void addRegOperands(MCInst &Inst, unsigned N) const {
1757     assert(N == 1 && "Invalid number of operands!");
1758     Inst.addOperand(MCOperand::CreateReg(getReg()));
1759   }
1760 
1761   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1762     assert(N == 3 && "Invalid number of operands!");
1763     assert(isRegShiftedReg() &&
1764            "addRegShiftedRegOperands() on non-RegShiftedReg!");
1765     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1766     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1767     Inst.addOperand(MCOperand::CreateImm(
1768       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1769   }
1770 
1771   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1772     assert(N == 2 && "Invalid number of operands!");
1773     assert(isRegShiftedImm() &&
1774            "addRegShiftedImmOperands() on non-RegShiftedImm!");
1775     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1776     // Shift of #32 is encoded as 0 where permitted
1777     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1778     Inst.addOperand(MCOperand::CreateImm(
1779       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1780   }
1781 
1782   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1783     assert(N == 1 && "Invalid number of operands!");
1784     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1785                                          ShifterImm.Imm));
1786   }
1787 
1788   void addRegListOperands(MCInst &Inst, unsigned N) const {
1789     assert(N == 1 && "Invalid number of operands!");
1790     const SmallVectorImpl<unsigned> &RegList = getRegList();
1791     for (SmallVectorImpl<unsigned>::const_iterator
1792            I = RegList.begin(), E = RegList.end(); I != E; ++I)
1793       Inst.addOperand(MCOperand::CreateReg(*I));
1794   }
1795 
1796   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1797     addRegListOperands(Inst, N);
1798   }
1799 
1800   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1801     addRegListOperands(Inst, N);
1802   }
1803 
1804   void addRotImmOperands(MCInst &Inst, unsigned N) const {
1805     assert(N == 1 && "Invalid number of operands!");
1806     // Encoded as val>>3. The printer handles display as 8, 16, 24.
1807     Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1808   }
1809 
1810   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1811     assert(N == 1 && "Invalid number of operands!");
1812     // Munge the lsb/width into a bitfield mask.
1813     unsigned lsb = Bitfield.LSB;
1814     unsigned width = Bitfield.Width;
1815     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1816     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1817                       (32 - (lsb + width)));
1818     Inst.addOperand(MCOperand::CreateImm(Mask));
1819   }
1820 
1821   void addImmOperands(MCInst &Inst, unsigned N) const {
1822     assert(N == 1 && "Invalid number of operands!");
1823     addExpr(Inst, getImm());
1824   }
1825 
1826   void addFBits16Operands(MCInst &Inst, unsigned N) const {
1827     assert(N == 1 && "Invalid number of operands!");
1828     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1829     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1830   }
1831 
1832   void addFBits32Operands(MCInst &Inst, unsigned N) const {
1833     assert(N == 1 && "Invalid number of operands!");
1834     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1835     Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1836   }
1837 
1838   void addFPImmOperands(MCInst &Inst, unsigned N) const {
1839     assert(N == 1 && "Invalid number of operands!");
1840     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1841     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1842     Inst.addOperand(MCOperand::CreateImm(Val));
1843   }
1844 
1845   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1846     assert(N == 1 && "Invalid number of operands!");
1847     // FIXME: We really want to scale the value here, but the LDRD/STRD
1848     // instruction don't encode operands that way yet.
1849     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1850     Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1851   }
1852 
1853   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1854     assert(N == 1 && "Invalid number of operands!");
1855     // The immediate is scaled by four in the encoding and is stored
1856     // in the MCInst as such. Lop off the low two bits here.
1857     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1858     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1859   }
1860 
1861   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1862     assert(N == 1 && "Invalid number of operands!");
1863     // The immediate is scaled by four in the encoding and is stored
1864     // in the MCInst as such. Lop off the low two bits here.
1865     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1866     Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1867   }
1868 
1869   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1870     assert(N == 1 && "Invalid number of operands!");
1871     // The immediate is scaled by four in the encoding and is stored
1872     // in the MCInst as such. Lop off the low two bits here.
1873     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1874     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1875   }
1876 
1877   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1878     assert(N == 1 && "Invalid number of operands!");
1879     // The constant encodes as the immediate-1, and we store in the instruction
1880     // the bits as encoded, so subtract off one here.
1881     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1882     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1883   }
1884 
1885   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1886     assert(N == 1 && "Invalid number of operands!");
1887     // The constant encodes as the immediate-1, and we store in the instruction
1888     // the bits as encoded, so subtract off one here.
1889     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1890     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1891   }
1892 
1893   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1894     assert(N == 1 && "Invalid number of operands!");
1895     // The constant encodes as the immediate, except for 32, which encodes as
1896     // zero.
1897     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1898     unsigned Imm = CE->getValue();
1899     Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1900   }
1901 
1902   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1903     assert(N == 1 && "Invalid number of operands!");
1904     // An ASR value of 32 encodes as 0, so that's how we want to add it to
1905     // the instruction as well.
1906     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1907     int Val = CE->getValue();
1908     Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1909   }
1910 
1911   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1912     assert(N == 1 && "Invalid number of operands!");
1913     // The operand is actually a t2_so_imm, but we have its bitwise
1914     // negation in the assembly source, so twiddle it here.
1915     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1916     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1917   }
1918 
1919   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1920     assert(N == 1 && "Invalid number of operands!");
1921     // The operand is actually a t2_so_imm, but we have its
1922     // negation in the assembly source, so twiddle it here.
1923     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1924     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1925   }
1926 
1927   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1928     assert(N == 1 && "Invalid number of operands!");
1929     // The operand is actually an imm0_4095, but we have its
1930     // negation in the assembly source, so twiddle it here.
1931     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1932     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1933   }
1934 
1935   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1936     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1937       Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1938       return;
1939     }
1940 
1941     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1942     assert(SR && "Unknown value type!");
1943     Inst.addOperand(MCOperand::CreateExpr(SR));
1944   }
1945 
1946   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1947     assert(N == 1 && "Invalid number of operands!");
1948     if (isImm()) {
1949       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1950       if (CE) {
1951         Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1952         return;
1953       }
1954 
1955       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1956       assert(SR && "Unknown value type!");
1957       Inst.addOperand(MCOperand::CreateExpr(SR));
1958       return;
1959     }
1960 
1961     assert(isMem()  && "Unknown value type!");
1962     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1963     Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1964   }
1965 
1966   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1967     assert(N == 1 && "Invalid number of operands!");
1968     // The operand is actually a so_imm, but we have its bitwise
1969     // negation in the assembly source, so twiddle it here.
1970     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1971     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1972   }
1973 
1974   void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1975     assert(N == 1 && "Invalid number of operands!");
1976     // The operand is actually a so_imm, but we have its
1977     // negation in the assembly source, so twiddle it here.
1978     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1979     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1980   }
1981 
1982   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1983     assert(N == 1 && "Invalid number of operands!");
1984     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1985   }
1986 
1987   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1988     assert(N == 1 && "Invalid number of operands!");
1989     Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1990   }
1991 
1992   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1993     assert(N == 1 && "Invalid number of operands!");
1994     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1995   }
1996 
1997   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1998     assert(N == 1 && "Invalid number of operands!");
1999     int32_t Imm = Memory.OffsetImm->getValue();
2000     Inst.addOperand(MCOperand::CreateImm(Imm));
2001   }
2002 
2003   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2004     assert(N == 1 && "Invalid number of operands!");
2005     assert(isImm() && "Not an immediate!");
2006 
2007     // If we have an immediate that's not a constant, treat it as a label
2008     // reference needing a fixup.
2009     if (!isa<MCConstantExpr>(getImm())) {
2010       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2011       return;
2012     }
2013 
2014     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2015     int Val = CE->getValue();
2016     Inst.addOperand(MCOperand::CreateImm(Val));
2017   }
2018 
2019   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2020     assert(N == 2 && "Invalid number of operands!");
2021     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2022     Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2023   }
2024 
2025   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2026     addAlignedMemoryOperands(Inst, N);
2027   }
2028 
2029   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2030     addAlignedMemoryOperands(Inst, N);
2031   }
2032 
2033   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2034     addAlignedMemoryOperands(Inst, N);
2035   }
2036 
2037   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2038     addAlignedMemoryOperands(Inst, N);
2039   }
2040 
2041   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2042     addAlignedMemoryOperands(Inst, N);
2043   }
2044 
2045   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2046     addAlignedMemoryOperands(Inst, N);
2047   }
2048 
2049   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2050     addAlignedMemoryOperands(Inst, N);
2051   }
2052 
2053   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2054     addAlignedMemoryOperands(Inst, N);
2055   }
2056 
2057   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2058     addAlignedMemoryOperands(Inst, N);
2059   }
2060 
2061   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2062     addAlignedMemoryOperands(Inst, N);
2063   }
2064 
2065   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2066     addAlignedMemoryOperands(Inst, N);
2067   }
2068 
2069   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2070     assert(N == 3 && "Invalid number of operands!");
2071     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2072     if (!Memory.OffsetRegNum) {
2073       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2074       // Special case for #-0
2075       if (Val == INT32_MIN) Val = 0;
2076       if (Val < 0) Val = -Val;
2077       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2078     } else {
2079       // For register offset, we encode the shift type and negation flag
2080       // here.
2081       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2082                               Memory.ShiftImm, Memory.ShiftType);
2083     }
2084     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2085     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2086     Inst.addOperand(MCOperand::CreateImm(Val));
2087   }
2088 
2089   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2090     assert(N == 2 && "Invalid number of operands!");
2091     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2092     assert(CE && "non-constant AM2OffsetImm operand!");
2093     int32_t Val = CE->getValue();
2094     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2095     // Special case for #-0
2096     if (Val == INT32_MIN) Val = 0;
2097     if (Val < 0) Val = -Val;
2098     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2099     Inst.addOperand(MCOperand::CreateReg(0));
2100     Inst.addOperand(MCOperand::CreateImm(Val));
2101   }
2102 
2103   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2104     assert(N == 3 && "Invalid number of operands!");
2105     // If we have an immediate that's not a constant, treat it as a label
2106     // reference needing a fixup. If it is a constant, it's something else
2107     // and we reject it.
2108     if (isImm()) {
2109       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2110       Inst.addOperand(MCOperand::CreateReg(0));
2111       Inst.addOperand(MCOperand::CreateImm(0));
2112       return;
2113     }
2114 
2115     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2116     if (!Memory.OffsetRegNum) {
2117       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2118       // Special case for #-0
2119       if (Val == INT32_MIN) Val = 0;
2120       if (Val < 0) Val = -Val;
2121       Val = ARM_AM::getAM3Opc(AddSub, Val);
2122     } else {
2123       // For register offset, we encode the shift type and negation flag
2124       // here.
2125       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2126     }
2127     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2128     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2129     Inst.addOperand(MCOperand::CreateImm(Val));
2130   }
2131 
2132   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2133     assert(N == 2 && "Invalid number of operands!");
2134     if (Kind == k_PostIndexRegister) {
2135       int32_t Val =
2136         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2137       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2138       Inst.addOperand(MCOperand::CreateImm(Val));
2139       return;
2140     }
2141 
2142     // Constant offset.
2143     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2144     int32_t Val = CE->getValue();
2145     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2146     // Special case for #-0
2147     if (Val == INT32_MIN) Val = 0;
2148     if (Val < 0) Val = -Val;
2149     Val = ARM_AM::getAM3Opc(AddSub, Val);
2150     Inst.addOperand(MCOperand::CreateReg(0));
2151     Inst.addOperand(MCOperand::CreateImm(Val));
2152   }
2153 
2154   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2155     assert(N == 2 && "Invalid number of operands!");
2156     // If we have an immediate that's not a constant, treat it as a label
2157     // reference needing a fixup. If it is a constant, it's something else
2158     // and we reject it.
2159     if (isImm()) {
2160       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2161       Inst.addOperand(MCOperand::CreateImm(0));
2162       return;
2163     }
2164 
2165     // The lower two bits are always zero and as such are not encoded.
2166     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2167     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2168     // Special case for #-0
2169     if (Val == INT32_MIN) Val = 0;
2170     if (Val < 0) Val = -Val;
2171     Val = ARM_AM::getAM5Opc(AddSub, Val);
2172     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2173     Inst.addOperand(MCOperand::CreateImm(Val));
2174   }
2175 
2176   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2177     assert(N == 2 && "Invalid number of operands!");
2178     // If we have an immediate that's not a constant, treat it as a label
2179     // reference needing a fixup. If it is a constant, it's something else
2180     // and we reject it.
2181     if (isImm()) {
2182       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2183       Inst.addOperand(MCOperand::CreateImm(0));
2184       return;
2185     }
2186 
2187     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2188     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2189     Inst.addOperand(MCOperand::CreateImm(Val));
2190   }
2191 
2192   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2193     assert(N == 2 && "Invalid number of operands!");
2194     // The lower two bits are always zero and as such are not encoded.
2195     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2196     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2197     Inst.addOperand(MCOperand::CreateImm(Val));
2198   }
2199 
2200   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2201     assert(N == 2 && "Invalid number of operands!");
2202     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2203     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2204     Inst.addOperand(MCOperand::CreateImm(Val));
2205   }
2206 
2207   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2208     addMemImm8OffsetOperands(Inst, N);
2209   }
2210 
2211   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2212     addMemImm8OffsetOperands(Inst, N);
2213   }
2214 
2215   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2216     assert(N == 2 && "Invalid number of operands!");
2217     // If this is an immediate, it's a label reference.
2218     if (isImm()) {
2219       addExpr(Inst, getImm());
2220       Inst.addOperand(MCOperand::CreateImm(0));
2221       return;
2222     }
2223 
2224     // Otherwise, it's a normal memory reg+offset.
2225     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2226     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2227     Inst.addOperand(MCOperand::CreateImm(Val));
2228   }
2229 
2230   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2231     assert(N == 2 && "Invalid number of operands!");
2232     // If this is an immediate, it's a label reference.
2233     if (isImm()) {
2234       addExpr(Inst, getImm());
2235       Inst.addOperand(MCOperand::CreateImm(0));
2236       return;
2237     }
2238 
2239     // Otherwise, it's a normal memory reg+offset.
2240     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2241     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2242     Inst.addOperand(MCOperand::CreateImm(Val));
2243   }
2244 
2245   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2246     assert(N == 2 && "Invalid number of operands!");
2247     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2248     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2249   }
2250 
2251   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2252     assert(N == 2 && "Invalid number of operands!");
2253     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2254     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2255   }
2256 
2257   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2258     assert(N == 3 && "Invalid number of operands!");
2259     unsigned Val =
2260       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2261                         Memory.ShiftImm, Memory.ShiftType);
2262     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2263     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2264     Inst.addOperand(MCOperand::CreateImm(Val));
2265   }
2266 
2267   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2268     assert(N == 3 && "Invalid number of operands!");
2269     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2270     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2271     Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2272   }
2273 
2274   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2275     assert(N == 2 && "Invalid number of operands!");
2276     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2277     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2278   }
2279 
2280   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2281     assert(N == 2 && "Invalid number of operands!");
2282     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2283     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2284     Inst.addOperand(MCOperand::CreateImm(Val));
2285   }
2286 
2287   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2288     assert(N == 2 && "Invalid number of operands!");
2289     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2290     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2291     Inst.addOperand(MCOperand::CreateImm(Val));
2292   }
2293 
2294   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2295     assert(N == 2 && "Invalid number of operands!");
2296     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2297     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2298     Inst.addOperand(MCOperand::CreateImm(Val));
2299   }
2300 
2301   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2302     assert(N == 2 && "Invalid number of operands!");
2303     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2304     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2305     Inst.addOperand(MCOperand::CreateImm(Val));
2306   }
2307 
2308   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2309     assert(N == 1 && "Invalid number of operands!");
2310     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2311     assert(CE && "non-constant post-idx-imm8 operand!");
2312     int Imm = CE->getValue();
2313     bool isAdd = Imm >= 0;
2314     if (Imm == INT32_MIN) Imm = 0;
2315     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2316     Inst.addOperand(MCOperand::CreateImm(Imm));
2317   }
2318 
2319   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2320     assert(N == 1 && "Invalid number of operands!");
2321     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2322     assert(CE && "non-constant post-idx-imm8s4 operand!");
2323     int Imm = CE->getValue();
2324     bool isAdd = Imm >= 0;
2325     if (Imm == INT32_MIN) Imm = 0;
2326     // Immediate is scaled by 4.
2327     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2328     Inst.addOperand(MCOperand::CreateImm(Imm));
2329   }
2330 
2331   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2332     assert(N == 2 && "Invalid number of operands!");
2333     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2334     Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2335   }
2336 
2337   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2338     assert(N == 2 && "Invalid number of operands!");
2339     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2340     // The sign, shift type, and shift amount are encoded in a single operand
2341     // using the AM2 encoding helpers.
2342     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2343     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2344                                      PostIdxReg.ShiftTy);
2345     Inst.addOperand(MCOperand::CreateImm(Imm));
2346   }
2347 
2348   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2349     assert(N == 1 && "Invalid number of operands!");
2350     Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2351   }
2352 
2353   void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2354     assert(N == 1 && "Invalid number of operands!");
2355     Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2356   }
2357 
2358   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2359     assert(N == 1 && "Invalid number of operands!");
2360     Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2361   }
2362 
2363   void addVecListOperands(MCInst &Inst, unsigned N) const {
2364     assert(N == 1 && "Invalid number of operands!");
2365     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2366   }
2367 
2368   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2369     assert(N == 2 && "Invalid number of operands!");
2370     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2371     Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2372   }
2373 
2374   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2375     assert(N == 1 && "Invalid number of operands!");
2376     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2377   }
2378 
2379   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2380     assert(N == 1 && "Invalid number of operands!");
2381     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2382   }
2383 
2384   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2385     assert(N == 1 && "Invalid number of operands!");
2386     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2387   }
2388 
2389   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2390     assert(N == 1 && "Invalid number of operands!");
2391     // The immediate encodes the type of constant as well as the value.
2392     // Mask in that this is an i8 splat.
2393     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2394     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2395   }
2396 
2397   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2398     assert(N == 1 && "Invalid number of operands!");
2399     // The immediate encodes the type of constant as well as the value.
2400     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2401     unsigned Value = CE->getValue();
2402     if (Value >= 256)
2403       Value = (Value >> 8) | 0xa00;
2404     else
2405       Value |= 0x800;
2406     Inst.addOperand(MCOperand::CreateImm(Value));
2407   }
2408 
2409   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2410     assert(N == 1 && "Invalid number of operands!");
2411     // The immediate encodes the type of constant as well as the value.
2412     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2413     unsigned Value = CE->getValue();
2414     if (Value >= 256 && Value <= 0xff00)
2415       Value = (Value >> 8) | 0x200;
2416     else if (Value > 0xffff && Value <= 0xff0000)
2417       Value = (Value >> 16) | 0x400;
2418     else if (Value > 0xffffff)
2419       Value = (Value >> 24) | 0x600;
2420     Inst.addOperand(MCOperand::CreateImm(Value));
2421   }
2422 
2423   void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2424     assert(N == 1 && "Invalid number of operands!");
2425     // The immediate encodes the type of constant as well as the value.
2426     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2427     unsigned Value = CE->getValue();
2428     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2429             Inst.getOpcode() == ARM::VMOVv16i8) &&
2430            "All vmvn instructions that wants to replicate non-zero byte "
2431            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2432     unsigned B = ((~Value) & 0xff);
2433     B |= 0xe00; // cmode = 0b1110
2434     Inst.addOperand(MCOperand::CreateImm(B));
2435   }
2436   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2437     assert(N == 1 && "Invalid number of operands!");
2438     // The immediate encodes the type of constant as well as the value.
2439     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2440     unsigned Value = CE->getValue();
2441     if (Value >= 256 && Value <= 0xffff)
2442       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2443     else if (Value > 0xffff && Value <= 0xffffff)
2444       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2445     else if (Value > 0xffffff)
2446       Value = (Value >> 24) | 0x600;
2447     Inst.addOperand(MCOperand::CreateImm(Value));
2448   }
2449 
2450   void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2451     assert(N == 1 && "Invalid number of operands!");
2452     // The immediate encodes the type of constant as well as the value.
2453     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2454     unsigned Value = CE->getValue();
2455     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2456             Inst.getOpcode() == ARM::VMOVv16i8) &&
2457            "All instructions that wants to replicate non-zero byte "
2458            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2459     unsigned B = Value & 0xff;
2460     B |= 0xe00; // cmode = 0b1110
2461     Inst.addOperand(MCOperand::CreateImm(B));
2462   }
2463   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2464     assert(N == 1 && "Invalid number of operands!");
2465     // The immediate encodes the type of constant as well as the value.
2466     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2467     unsigned Value = ~CE->getValue();
2468     if (Value >= 256 && Value <= 0xffff)
2469       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2470     else if (Value > 0xffff && Value <= 0xffffff)
2471       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2472     else if (Value > 0xffffff)
2473       Value = (Value >> 24) | 0x600;
2474     Inst.addOperand(MCOperand::CreateImm(Value));
2475   }
2476 
2477   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2478     assert(N == 1 && "Invalid number of operands!");
2479     // The immediate encodes the type of constant as well as the value.
2480     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2481     uint64_t Value = CE->getValue();
2482     unsigned Imm = 0;
2483     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2484       Imm |= (Value & 1) << i;
2485     }
2486     Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2487   }
2488 
2489   void print(raw_ostream &OS) const override;
2490 
2491   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2492     auto Op = make_unique<ARMOperand>(k_ITCondMask);
2493     Op->ITMask.Mask = Mask;
2494     Op->StartLoc = S;
2495     Op->EndLoc = S;
2496     return Op;
2497   }
2498 
2499   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2500                                                     SMLoc S) {
2501     auto Op = make_unique<ARMOperand>(k_CondCode);
2502     Op->CC.Val = CC;
2503     Op->StartLoc = S;
2504     Op->EndLoc = S;
2505     return Op;
2506   }
2507 
2508   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2509     auto Op = make_unique<ARMOperand>(k_CoprocNum);
2510     Op->Cop.Val = CopVal;
2511     Op->StartLoc = S;
2512     Op->EndLoc = S;
2513     return Op;
2514   }
2515 
2516   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2517     auto Op = make_unique<ARMOperand>(k_CoprocReg);
2518     Op->Cop.Val = CopVal;
2519     Op->StartLoc = S;
2520     Op->EndLoc = S;
2521     return Op;
2522   }
2523 
2524   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2525                                                         SMLoc E) {
2526     auto Op = make_unique<ARMOperand>(k_CoprocOption);
2527     Op->Cop.Val = Val;
2528     Op->StartLoc = S;
2529     Op->EndLoc = E;
2530     return Op;
2531   }
2532 
2533   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2534     auto Op = make_unique<ARMOperand>(k_CCOut);
2535     Op->Reg.RegNum = RegNum;
2536     Op->StartLoc = S;
2537     Op->EndLoc = S;
2538     return Op;
2539   }
2540 
2541   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2542     auto Op = make_unique<ARMOperand>(k_Token);
2543     Op->Tok.Data = Str.data();
2544     Op->Tok.Length = Str.size();
2545     Op->StartLoc = S;
2546     Op->EndLoc = S;
2547     return Op;
2548   }
2549 
2550   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2551                                                SMLoc E) {
2552     auto Op = make_unique<ARMOperand>(k_Register);
2553     Op->Reg.RegNum = RegNum;
2554     Op->StartLoc = S;
2555     Op->EndLoc = E;
2556     return Op;
2557   }
2558 
2559   static std::unique_ptr<ARMOperand>
2560   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2561                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2562                         SMLoc E) {
2563     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2564     Op->RegShiftedReg.ShiftTy = ShTy;
2565     Op->RegShiftedReg.SrcReg = SrcReg;
2566     Op->RegShiftedReg.ShiftReg = ShiftReg;
2567     Op->RegShiftedReg.ShiftImm = ShiftImm;
2568     Op->StartLoc = S;
2569     Op->EndLoc = E;
2570     return Op;
2571   }
2572 
2573   static std::unique_ptr<ARMOperand>
2574   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2575                          unsigned ShiftImm, SMLoc S, SMLoc E) {
2576     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2577     Op->RegShiftedImm.ShiftTy = ShTy;
2578     Op->RegShiftedImm.SrcReg = SrcReg;
2579     Op->RegShiftedImm.ShiftImm = ShiftImm;
2580     Op->StartLoc = S;
2581     Op->EndLoc = E;
2582     return Op;
2583   }
2584 
2585   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2586                                                       SMLoc S, SMLoc E) {
2587     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2588     Op->ShifterImm.isASR = isASR;
2589     Op->ShifterImm.Imm = Imm;
2590     Op->StartLoc = S;
2591     Op->EndLoc = E;
2592     return Op;
2593   }
2594 
2595   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2596                                                   SMLoc E) {
2597     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2598     Op->RotImm.Imm = Imm;
2599     Op->StartLoc = S;
2600     Op->EndLoc = E;
2601     return Op;
2602   }
2603 
2604   static std::unique_ptr<ARMOperand>
2605   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2606     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2607     Op->Bitfield.LSB = LSB;
2608     Op->Bitfield.Width = Width;
2609     Op->StartLoc = S;
2610     Op->EndLoc = E;
2611     return Op;
2612   }
2613 
2614   static std::unique_ptr<ARMOperand>
2615   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2616                 SMLoc StartLoc, SMLoc EndLoc) {
2617     assert (Regs.size() > 0 && "RegList contains no registers?");
2618     KindTy Kind = k_RegisterList;
2619 
2620     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2621       Kind = k_DPRRegisterList;
2622     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2623              contains(Regs.front().second))
2624       Kind = k_SPRRegisterList;
2625 
2626     // Sort based on the register encoding values.
2627     array_pod_sort(Regs.begin(), Regs.end());
2628 
2629     auto Op = make_unique<ARMOperand>(Kind);
2630     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2631            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2632       Op->Registers.push_back(I->second);
2633     Op->StartLoc = StartLoc;
2634     Op->EndLoc = EndLoc;
2635     return Op;
2636   }
2637 
2638   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2639                                                       unsigned Count,
2640                                                       bool isDoubleSpaced,
2641                                                       SMLoc S, SMLoc E) {
2642     auto Op = make_unique<ARMOperand>(k_VectorList);
2643     Op->VectorList.RegNum = RegNum;
2644     Op->VectorList.Count = Count;
2645     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2646     Op->StartLoc = S;
2647     Op->EndLoc = E;
2648     return Op;
2649   }
2650 
2651   static std::unique_ptr<ARMOperand>
2652   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2653                            SMLoc S, SMLoc E) {
2654     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2655     Op->VectorList.RegNum = RegNum;
2656     Op->VectorList.Count = Count;
2657     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2658     Op->StartLoc = S;
2659     Op->EndLoc = E;
2660     return Op;
2661   }
2662 
2663   static std::unique_ptr<ARMOperand>
2664   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2665                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
2666     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2667     Op->VectorList.RegNum = RegNum;
2668     Op->VectorList.Count = Count;
2669     Op->VectorList.LaneIndex = Index;
2670     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2671     Op->StartLoc = S;
2672     Op->EndLoc = E;
2673     return Op;
2674   }
2675 
2676   static std::unique_ptr<ARMOperand>
2677   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2678     auto Op = make_unique<ARMOperand>(k_VectorIndex);
2679     Op->VectorIndex.Val = Idx;
2680     Op->StartLoc = S;
2681     Op->EndLoc = E;
2682     return Op;
2683   }
2684 
2685   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2686                                                SMLoc E) {
2687     auto Op = make_unique<ARMOperand>(k_Immediate);
2688     Op->Imm.Val = Val;
2689     Op->StartLoc = S;
2690     Op->EndLoc = E;
2691     return Op;
2692   }
2693 
2694   static std::unique_ptr<ARMOperand>
2695   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2696             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2697             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2698             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2699     auto Op = make_unique<ARMOperand>(k_Memory);
2700     Op->Memory.BaseRegNum = BaseRegNum;
2701     Op->Memory.OffsetImm = OffsetImm;
2702     Op->Memory.OffsetRegNum = OffsetRegNum;
2703     Op->Memory.ShiftType = ShiftType;
2704     Op->Memory.ShiftImm = ShiftImm;
2705     Op->Memory.Alignment = Alignment;
2706     Op->Memory.isNegative = isNegative;
2707     Op->StartLoc = S;
2708     Op->EndLoc = E;
2709     Op->AlignmentLoc = AlignmentLoc;
2710     return Op;
2711   }
2712 
2713   static std::unique_ptr<ARMOperand>
2714   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2715                    unsigned ShiftImm, SMLoc S, SMLoc E) {
2716     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2717     Op->PostIdxReg.RegNum = RegNum;
2718     Op->PostIdxReg.isAdd = isAdd;
2719     Op->PostIdxReg.ShiftTy = ShiftTy;
2720     Op->PostIdxReg.ShiftImm = ShiftImm;
2721     Op->StartLoc = S;
2722     Op->EndLoc = E;
2723     return Op;
2724   }
2725 
2726   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2727                                                          SMLoc S) {
2728     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2729     Op->MBOpt.Val = Opt;
2730     Op->StartLoc = S;
2731     Op->EndLoc = S;
2732     return Op;
2733   }
2734 
2735   static std::unique_ptr<ARMOperand>
2736   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2737     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2738     Op->ISBOpt.Val = Opt;
2739     Op->StartLoc = S;
2740     Op->EndLoc = S;
2741     return Op;
2742   }
2743 
2744   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2745                                                       SMLoc S) {
2746     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2747     Op->IFlags.Val = IFlags;
2748     Op->StartLoc = S;
2749     Op->EndLoc = S;
2750     return Op;
2751   }
2752 
2753   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2754     auto Op = make_unique<ARMOperand>(k_MSRMask);
2755     Op->MMask.Val = MMask;
2756     Op->StartLoc = S;
2757     Op->EndLoc = S;
2758     return Op;
2759   }
2760 
2761   static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2762     auto Op = make_unique<ARMOperand>(k_BankedReg);
2763     Op->BankedReg.Val = Reg;
2764     Op->StartLoc = S;
2765     Op->EndLoc = S;
2766     return Op;
2767   }
2768 };
2769 
2770 } // end anonymous namespace.
2771 
2772 void ARMOperand::print(raw_ostream &OS) const {
2773   switch (Kind) {
2774   case k_CondCode:
2775     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2776     break;
2777   case k_CCOut:
2778     OS << "<ccout " << getReg() << ">";
2779     break;
2780   case k_ITCondMask: {
2781     static const char *const MaskStr[] = {
2782       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2783       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2784     };
2785     assert((ITMask.Mask & 0xf) == ITMask.Mask);
2786     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2787     break;
2788   }
2789   case k_CoprocNum:
2790     OS << "<coprocessor number: " << getCoproc() << ">";
2791     break;
2792   case k_CoprocReg:
2793     OS << "<coprocessor register: " << getCoproc() << ">";
2794     break;
2795   case k_CoprocOption:
2796     OS << "<coprocessor option: " << CoprocOption.Val << ">";
2797     break;
2798   case k_MSRMask:
2799     OS << "<mask: " << getMSRMask() << ">";
2800     break;
2801   case k_BankedReg:
2802     OS << "<banked reg: " << getBankedReg() << ">";
2803     break;
2804   case k_Immediate:
2805     getImm()->print(OS);
2806     break;
2807   case k_MemBarrierOpt:
2808     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2809     break;
2810   case k_InstSyncBarrierOpt:
2811     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2812     break;
2813   case k_Memory:
2814     OS << "<memory "
2815        << " base:" << Memory.BaseRegNum;
2816     OS << ">";
2817     break;
2818   case k_PostIndexRegister:
2819     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2820        << PostIdxReg.RegNum;
2821     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2822       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2823          << PostIdxReg.ShiftImm;
2824     OS << ">";
2825     break;
2826   case k_ProcIFlags: {
2827     OS << "<ARM_PROC::";
2828     unsigned IFlags = getProcIFlags();
2829     for (int i=2; i >= 0; --i)
2830       if (IFlags & (1 << i))
2831         OS << ARM_PROC::IFlagsToString(1 << i);
2832     OS << ">";
2833     break;
2834   }
2835   case k_Register:
2836     OS << "<register " << getReg() << ">";
2837     break;
2838   case k_ShifterImmediate:
2839     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2840        << " #" << ShifterImm.Imm << ">";
2841     break;
2842   case k_ShiftedRegister:
2843     OS << "<so_reg_reg "
2844        << RegShiftedReg.SrcReg << " "
2845        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2846        << " " << RegShiftedReg.ShiftReg << ">";
2847     break;
2848   case k_ShiftedImmediate:
2849     OS << "<so_reg_imm "
2850        << RegShiftedImm.SrcReg << " "
2851        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2852        << " #" << RegShiftedImm.ShiftImm << ">";
2853     break;
2854   case k_RotateImmediate:
2855     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2856     break;
2857   case k_BitfieldDescriptor:
2858     OS << "<bitfield " << "lsb: " << Bitfield.LSB
2859        << ", width: " << Bitfield.Width << ">";
2860     break;
2861   case k_RegisterList:
2862   case k_DPRRegisterList:
2863   case k_SPRRegisterList: {
2864     OS << "<register_list ";
2865 
2866     const SmallVectorImpl<unsigned> &RegList = getRegList();
2867     for (SmallVectorImpl<unsigned>::const_iterator
2868            I = RegList.begin(), E = RegList.end(); I != E; ) {
2869       OS << *I;
2870       if (++I < E) OS << ", ";
2871     }
2872 
2873     OS << ">";
2874     break;
2875   }
2876   case k_VectorList:
2877     OS << "<vector_list " << VectorList.Count << " * "
2878        << VectorList.RegNum << ">";
2879     break;
2880   case k_VectorListAllLanes:
2881     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2882        << VectorList.RegNum << ">";
2883     break;
2884   case k_VectorListIndexed:
2885     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2886        << VectorList.Count << " * " << VectorList.RegNum << ">";
2887     break;
2888   case k_Token:
2889     OS << "'" << getToken() << "'";
2890     break;
2891   case k_VectorIndex:
2892     OS << "<vectorindex " << getVectorIndex() << ">";
2893     break;
2894   }
2895 }
2896 
2897 /// @name Auto-generated Match Functions
2898 /// {
2899 
2900 static unsigned MatchRegisterName(StringRef Name);
2901 
2902 /// }
2903 
2904 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2905                                  SMLoc &StartLoc, SMLoc &EndLoc) {
2906   StartLoc = Parser.getTok().getLoc();
2907   EndLoc = Parser.getTok().getEndLoc();
2908   RegNo = tryParseRegister();
2909 
2910   return (RegNo == (unsigned)-1);
2911 }
2912 
2913 /// Try to parse a register name.  The token must be an Identifier when called,
2914 /// and if it is a register name the token is eaten and the register number is
2915 /// returned.  Otherwise return -1.
2916 ///
2917 int ARMAsmParser::tryParseRegister() {
2918   const AsmToken &Tok = Parser.getTok();
2919   if (Tok.isNot(AsmToken::Identifier)) return -1;
2920 
2921   std::string lowerCase = Tok.getString().lower();
2922   unsigned RegNum = MatchRegisterName(lowerCase);
2923   if (!RegNum) {
2924     RegNum = StringSwitch<unsigned>(lowerCase)
2925       .Case("r13", ARM::SP)
2926       .Case("r14", ARM::LR)
2927       .Case("r15", ARM::PC)
2928       .Case("ip", ARM::R12)
2929       // Additional register name aliases for 'gas' compatibility.
2930       .Case("a1", ARM::R0)
2931       .Case("a2", ARM::R1)
2932       .Case("a3", ARM::R2)
2933       .Case("a4", ARM::R3)
2934       .Case("v1", ARM::R4)
2935       .Case("v2", ARM::R5)
2936       .Case("v3", ARM::R6)
2937       .Case("v4", ARM::R7)
2938       .Case("v5", ARM::R8)
2939       .Case("v6", ARM::R9)
2940       .Case("v7", ARM::R10)
2941       .Case("v8", ARM::R11)
2942       .Case("sb", ARM::R9)
2943       .Case("sl", ARM::R10)
2944       .Case("fp", ARM::R11)
2945       .Default(0);
2946   }
2947   if (!RegNum) {
2948     // Check for aliases registered via .req. Canonicalize to lower case.
2949     // That's more consistent since register names are case insensitive, and
2950     // it's how the original entry was passed in from MC/MCParser/AsmParser.
2951     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2952     // If no match, return failure.
2953     if (Entry == RegisterReqs.end())
2954       return -1;
2955     Parser.Lex(); // Eat identifier token.
2956     return Entry->getValue();
2957   }
2958 
2959   Parser.Lex(); // Eat identifier token.
2960 
2961   return RegNum;
2962 }
2963 
2964 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2965 // If a recoverable error occurs, return 1. If an irrecoverable error
2966 // occurs, return -1. An irrecoverable error is one where tokens have been
2967 // consumed in the process of trying to parse the shifter (i.e., when it is
2968 // indeed a shifter operand, but malformed).
2969 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
2970   SMLoc S = Parser.getTok().getLoc();
2971   const AsmToken &Tok = Parser.getTok();
2972   if (Tok.isNot(AsmToken::Identifier))
2973     return -1;
2974 
2975   std::string lowerCase = Tok.getString().lower();
2976   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2977       .Case("asl", ARM_AM::lsl)
2978       .Case("lsl", ARM_AM::lsl)
2979       .Case("lsr", ARM_AM::lsr)
2980       .Case("asr", ARM_AM::asr)
2981       .Case("ror", ARM_AM::ror)
2982       .Case("rrx", ARM_AM::rrx)
2983       .Default(ARM_AM::no_shift);
2984 
2985   if (ShiftTy == ARM_AM::no_shift)
2986     return 1;
2987 
2988   Parser.Lex(); // Eat the operator.
2989 
2990   // The source register for the shift has already been added to the
2991   // operand list, so we need to pop it off and combine it into the shifted
2992   // register operand instead.
2993   std::unique_ptr<ARMOperand> PrevOp(
2994       (ARMOperand *)Operands.pop_back_val().release());
2995   if (!PrevOp->isReg())
2996     return Error(PrevOp->getStartLoc(), "shift must be of a register");
2997   int SrcReg = PrevOp->getReg();
2998 
2999   SMLoc EndLoc;
3000   int64_t Imm = 0;
3001   int ShiftReg = 0;
3002   if (ShiftTy == ARM_AM::rrx) {
3003     // RRX Doesn't have an explicit shift amount. The encoder expects
3004     // the shift register to be the same as the source register. Seems odd,
3005     // but OK.
3006     ShiftReg = SrcReg;
3007   } else {
3008     // Figure out if this is shifted by a constant or a register (for non-RRX).
3009     if (Parser.getTok().is(AsmToken::Hash) ||
3010         Parser.getTok().is(AsmToken::Dollar)) {
3011       Parser.Lex(); // Eat hash.
3012       SMLoc ImmLoc = Parser.getTok().getLoc();
3013       const MCExpr *ShiftExpr = nullptr;
3014       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3015         Error(ImmLoc, "invalid immediate shift value");
3016         return -1;
3017       }
3018       // The expression must be evaluatable as an immediate.
3019       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3020       if (!CE) {
3021         Error(ImmLoc, "invalid immediate shift value");
3022         return -1;
3023       }
3024       // Range check the immediate.
3025       // lsl, ror: 0 <= imm <= 31
3026       // lsr, asr: 0 <= imm <= 32
3027       Imm = CE->getValue();
3028       if (Imm < 0 ||
3029           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3030           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3031         Error(ImmLoc, "immediate shift value out of range");
3032         return -1;
3033       }
3034       // shift by zero is a nop. Always send it through as lsl.
3035       // ('as' compatibility)
3036       if (Imm == 0)
3037         ShiftTy = ARM_AM::lsl;
3038     } else if (Parser.getTok().is(AsmToken::Identifier)) {
3039       SMLoc L = Parser.getTok().getLoc();
3040       EndLoc = Parser.getTok().getEndLoc();
3041       ShiftReg = tryParseRegister();
3042       if (ShiftReg == -1) {
3043         Error(L, "expected immediate or register in shift operand");
3044         return -1;
3045       }
3046     } else {
3047       Error(Parser.getTok().getLoc(),
3048             "expected immediate or register in shift operand");
3049       return -1;
3050     }
3051   }
3052 
3053   if (ShiftReg && ShiftTy != ARM_AM::rrx)
3054     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3055                                                          ShiftReg, Imm,
3056                                                          S, EndLoc));
3057   else
3058     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3059                                                           S, EndLoc));
3060 
3061   return 0;
3062 }
3063 
3064 
3065 /// Try to parse a register name.  The token must be an Identifier when called.
3066 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3067 /// if there is a "writeback". 'true' if it's not a register.
3068 ///
3069 /// TODO this is likely to change to allow different register types and or to
3070 /// parse for a specific register type.
3071 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3072   const AsmToken &RegTok = Parser.getTok();
3073   int RegNo = tryParseRegister();
3074   if (RegNo == -1)
3075     return true;
3076 
3077   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3078                                            RegTok.getEndLoc()));
3079 
3080   const AsmToken &ExclaimTok = Parser.getTok();
3081   if (ExclaimTok.is(AsmToken::Exclaim)) {
3082     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3083                                                ExclaimTok.getLoc()));
3084     Parser.Lex(); // Eat exclaim token
3085     return false;
3086   }
3087 
3088   // Also check for an index operand. This is only legal for vector registers,
3089   // but that'll get caught OK in operand matching, so we don't need to
3090   // explicitly filter everything else out here.
3091   if (Parser.getTok().is(AsmToken::LBrac)) {
3092     SMLoc SIdx = Parser.getTok().getLoc();
3093     Parser.Lex(); // Eat left bracket token.
3094 
3095     const MCExpr *ImmVal;
3096     if (getParser().parseExpression(ImmVal))
3097       return true;
3098     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3099     if (!MCE)
3100       return TokError("immediate value expected for vector index");
3101 
3102     if (Parser.getTok().isNot(AsmToken::RBrac))
3103       return Error(Parser.getTok().getLoc(), "']' expected");
3104 
3105     SMLoc E = Parser.getTok().getEndLoc();
3106     Parser.Lex(); // Eat right bracket token.
3107 
3108     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3109                                                      SIdx, E,
3110                                                      getContext()));
3111   }
3112 
3113   return false;
3114 }
3115 
3116 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3117 /// instruction with a symbolic operand name.
3118 /// We accept "crN" syntax for GAS compatibility.
3119 /// <operand-name> ::= <prefix><number>
3120 /// If CoprocOp is 'c', then:
3121 ///   <prefix> ::= c | cr
3122 /// If CoprocOp is 'p', then :
3123 ///   <prefix> ::= p
3124 /// <number> ::= integer in range [0, 15]
3125 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3126   // Use the same layout as the tablegen'erated register name matcher. Ugly,
3127   // but efficient.
3128   if (Name.size() < 2 || Name[0] != CoprocOp)
3129     return -1;
3130   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3131 
3132   switch (Name.size()) {
3133   default: return -1;
3134   case 1:
3135     switch (Name[0]) {
3136     default:  return -1;
3137     case '0': return 0;
3138     case '1': return 1;
3139     case '2': return 2;
3140     case '3': return 3;
3141     case '4': return 4;
3142     case '5': return 5;
3143     case '6': return 6;
3144     case '7': return 7;
3145     case '8': return 8;
3146     case '9': return 9;
3147     }
3148   case 2:
3149     if (Name[0] != '1')
3150       return -1;
3151     switch (Name[1]) {
3152     default:  return -1;
3153     // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3154     // However, old cores (v5/v6) did use them in that way.
3155     case '0': return 10;
3156     case '1': return 11;
3157     case '2': return 12;
3158     case '3': return 13;
3159     case '4': return 14;
3160     case '5': return 15;
3161     }
3162   }
3163 }
3164 
3165 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3166 ARMAsmParser::OperandMatchResultTy
3167 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3168   SMLoc S = Parser.getTok().getLoc();
3169   const AsmToken &Tok = Parser.getTok();
3170   if (!Tok.is(AsmToken::Identifier))
3171     return MatchOperand_NoMatch;
3172   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3173     .Case("eq", ARMCC::EQ)
3174     .Case("ne", ARMCC::NE)
3175     .Case("hs", ARMCC::HS)
3176     .Case("cs", ARMCC::HS)
3177     .Case("lo", ARMCC::LO)
3178     .Case("cc", ARMCC::LO)
3179     .Case("mi", ARMCC::MI)
3180     .Case("pl", ARMCC::PL)
3181     .Case("vs", ARMCC::VS)
3182     .Case("vc", ARMCC::VC)
3183     .Case("hi", ARMCC::HI)
3184     .Case("ls", ARMCC::LS)
3185     .Case("ge", ARMCC::GE)
3186     .Case("lt", ARMCC::LT)
3187     .Case("gt", ARMCC::GT)
3188     .Case("le", ARMCC::LE)
3189     .Case("al", ARMCC::AL)
3190     .Default(~0U);
3191   if (CC == ~0U)
3192     return MatchOperand_NoMatch;
3193   Parser.Lex(); // Eat the token.
3194 
3195   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3196 
3197   return MatchOperand_Success;
3198 }
3199 
3200 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3201 /// token must be an Identifier when called, and if it is a coprocessor
3202 /// number, the token is eaten and the operand is added to the operand list.
3203 ARMAsmParser::OperandMatchResultTy
3204 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3205   SMLoc S = Parser.getTok().getLoc();
3206   const AsmToken &Tok = Parser.getTok();
3207   if (Tok.isNot(AsmToken::Identifier))
3208     return MatchOperand_NoMatch;
3209 
3210   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3211   if (Num == -1)
3212     return MatchOperand_NoMatch;
3213   // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3214   if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3215     return MatchOperand_NoMatch;
3216 
3217   Parser.Lex(); // Eat identifier token.
3218   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3219   return MatchOperand_Success;
3220 }
3221 
3222 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3223 /// token must be an Identifier when called, and if it is a coprocessor
3224 /// number, the token is eaten and the operand is added to the operand list.
3225 ARMAsmParser::OperandMatchResultTy
3226 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3227   SMLoc S = Parser.getTok().getLoc();
3228   const AsmToken &Tok = Parser.getTok();
3229   if (Tok.isNot(AsmToken::Identifier))
3230     return MatchOperand_NoMatch;
3231 
3232   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3233   if (Reg == -1)
3234     return MatchOperand_NoMatch;
3235 
3236   Parser.Lex(); // Eat identifier token.
3237   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3238   return MatchOperand_Success;
3239 }
3240 
3241 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3242 /// coproc_option : '{' imm0_255 '}'
3243 ARMAsmParser::OperandMatchResultTy
3244 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3245   SMLoc S = Parser.getTok().getLoc();
3246 
3247   // If this isn't a '{', this isn't a coprocessor immediate operand.
3248   if (Parser.getTok().isNot(AsmToken::LCurly))
3249     return MatchOperand_NoMatch;
3250   Parser.Lex(); // Eat the '{'
3251 
3252   const MCExpr *Expr;
3253   SMLoc Loc = Parser.getTok().getLoc();
3254   if (getParser().parseExpression(Expr)) {
3255     Error(Loc, "illegal expression");
3256     return MatchOperand_ParseFail;
3257   }
3258   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3259   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3260     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3261     return MatchOperand_ParseFail;
3262   }
3263   int Val = CE->getValue();
3264 
3265   // Check for and consume the closing '}'
3266   if (Parser.getTok().isNot(AsmToken::RCurly))
3267     return MatchOperand_ParseFail;
3268   SMLoc E = Parser.getTok().getEndLoc();
3269   Parser.Lex(); // Eat the '}'
3270 
3271   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3272   return MatchOperand_Success;
3273 }
3274 
3275 // For register list parsing, we need to map from raw GPR register numbering
3276 // to the enumeration values. The enumeration values aren't sorted by
3277 // register number due to our using "sp", "lr" and "pc" as canonical names.
3278 static unsigned getNextRegister(unsigned Reg) {
3279   // If this is a GPR, we need to do it manually, otherwise we can rely
3280   // on the sort ordering of the enumeration since the other reg-classes
3281   // are sane.
3282   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3283     return Reg + 1;
3284   switch(Reg) {
3285   default: llvm_unreachable("Invalid GPR number!");
3286   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3287   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3288   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3289   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3290   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3291   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3292   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3293   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3294   }
3295 }
3296 
3297 // Return the low-subreg of a given Q register.
3298 static unsigned getDRegFromQReg(unsigned QReg) {
3299   switch (QReg) {
3300   default: llvm_unreachable("expected a Q register!");
3301   case ARM::Q0:  return ARM::D0;
3302   case ARM::Q1:  return ARM::D2;
3303   case ARM::Q2:  return ARM::D4;
3304   case ARM::Q3:  return ARM::D6;
3305   case ARM::Q4:  return ARM::D8;
3306   case ARM::Q5:  return ARM::D10;
3307   case ARM::Q6:  return ARM::D12;
3308   case ARM::Q7:  return ARM::D14;
3309   case ARM::Q8:  return ARM::D16;
3310   case ARM::Q9:  return ARM::D18;
3311   case ARM::Q10: return ARM::D20;
3312   case ARM::Q11: return ARM::D22;
3313   case ARM::Q12: return ARM::D24;
3314   case ARM::Q13: return ARM::D26;
3315   case ARM::Q14: return ARM::D28;
3316   case ARM::Q15: return ARM::D30;
3317   }
3318 }
3319 
3320 /// Parse a register list.
3321 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3322   assert(Parser.getTok().is(AsmToken::LCurly) &&
3323          "Token is not a Left Curly Brace");
3324   SMLoc S = Parser.getTok().getLoc();
3325   Parser.Lex(); // Eat '{' token.
3326   SMLoc RegLoc = Parser.getTok().getLoc();
3327 
3328   // Check the first register in the list to see what register class
3329   // this is a list of.
3330   int Reg = tryParseRegister();
3331   if (Reg == -1)
3332     return Error(RegLoc, "register expected");
3333 
3334   // The reglist instructions have at most 16 registers, so reserve
3335   // space for that many.
3336   int EReg = 0;
3337   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3338 
3339   // Allow Q regs and just interpret them as the two D sub-registers.
3340   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3341     Reg = getDRegFromQReg(Reg);
3342     EReg = MRI->getEncodingValue(Reg);
3343     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3344     ++Reg;
3345   }
3346   const MCRegisterClass *RC;
3347   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3348     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3349   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3350     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3351   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3352     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3353   else
3354     return Error(RegLoc, "invalid register in register list");
3355 
3356   // Store the register.
3357   EReg = MRI->getEncodingValue(Reg);
3358   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3359 
3360   // This starts immediately after the first register token in the list,
3361   // so we can see either a comma or a minus (range separator) as a legal
3362   // next token.
3363   while (Parser.getTok().is(AsmToken::Comma) ||
3364          Parser.getTok().is(AsmToken::Minus)) {
3365     if (Parser.getTok().is(AsmToken::Minus)) {
3366       Parser.Lex(); // Eat the minus.
3367       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3368       int EndReg = tryParseRegister();
3369       if (EndReg == -1)
3370         return Error(AfterMinusLoc, "register expected");
3371       // Allow Q regs and just interpret them as the two D sub-registers.
3372       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3373         EndReg = getDRegFromQReg(EndReg) + 1;
3374       // If the register is the same as the start reg, there's nothing
3375       // more to do.
3376       if (Reg == EndReg)
3377         continue;
3378       // The register must be in the same register class as the first.
3379       if (!RC->contains(EndReg))
3380         return Error(AfterMinusLoc, "invalid register in register list");
3381       // Ranges must go from low to high.
3382       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3383         return Error(AfterMinusLoc, "bad range in register list");
3384 
3385       // Add all the registers in the range to the register list.
3386       while (Reg != EndReg) {
3387         Reg = getNextRegister(Reg);
3388         EReg = MRI->getEncodingValue(Reg);
3389         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3390       }
3391       continue;
3392     }
3393     Parser.Lex(); // Eat the comma.
3394     RegLoc = Parser.getTok().getLoc();
3395     int OldReg = Reg;
3396     const AsmToken RegTok = Parser.getTok();
3397     Reg = tryParseRegister();
3398     if (Reg == -1)
3399       return Error(RegLoc, "register expected");
3400     // Allow Q regs and just interpret them as the two D sub-registers.
3401     bool isQReg = false;
3402     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3403       Reg = getDRegFromQReg(Reg);
3404       isQReg = true;
3405     }
3406     // The register must be in the same register class as the first.
3407     if (!RC->contains(Reg))
3408       return Error(RegLoc, "invalid register in register list");
3409     // List must be monotonically increasing.
3410     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3411       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3412         Warning(RegLoc, "register list not in ascending order");
3413       else
3414         return Error(RegLoc, "register list not in ascending order");
3415     }
3416     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3417       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3418               ") in register list");
3419       continue;
3420     }
3421     // VFP register lists must also be contiguous.
3422     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3423         Reg != OldReg + 1)
3424       return Error(RegLoc, "non-contiguous register range");
3425     EReg = MRI->getEncodingValue(Reg);
3426     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3427     if (isQReg) {
3428       EReg = MRI->getEncodingValue(++Reg);
3429       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3430     }
3431   }
3432 
3433   if (Parser.getTok().isNot(AsmToken::RCurly))
3434     return Error(Parser.getTok().getLoc(), "'}' expected");
3435   SMLoc E = Parser.getTok().getEndLoc();
3436   Parser.Lex(); // Eat '}' token.
3437 
3438   // Push the register list operand.
3439   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3440 
3441   // The ARM system instruction variants for LDM/STM have a '^' token here.
3442   if (Parser.getTok().is(AsmToken::Caret)) {
3443     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3444     Parser.Lex(); // Eat '^' token.
3445   }
3446 
3447   return false;
3448 }
3449 
3450 // Helper function to parse the lane index for vector lists.
3451 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3452 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3453   Index = 0; // Always return a defined index value.
3454   if (Parser.getTok().is(AsmToken::LBrac)) {
3455     Parser.Lex(); // Eat the '['.
3456     if (Parser.getTok().is(AsmToken::RBrac)) {
3457       // "Dn[]" is the 'all lanes' syntax.
3458       LaneKind = AllLanes;
3459       EndLoc = Parser.getTok().getEndLoc();
3460       Parser.Lex(); // Eat the ']'.
3461       return MatchOperand_Success;
3462     }
3463 
3464     // There's an optional '#' token here. Normally there wouldn't be, but
3465     // inline assemble puts one in, and it's friendly to accept that.
3466     if (Parser.getTok().is(AsmToken::Hash))
3467       Parser.Lex(); // Eat '#' or '$'.
3468 
3469     const MCExpr *LaneIndex;
3470     SMLoc Loc = Parser.getTok().getLoc();
3471     if (getParser().parseExpression(LaneIndex)) {
3472       Error(Loc, "illegal expression");
3473       return MatchOperand_ParseFail;
3474     }
3475     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3476     if (!CE) {
3477       Error(Loc, "lane index must be empty or an integer");
3478       return MatchOperand_ParseFail;
3479     }
3480     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3481       Error(Parser.getTok().getLoc(), "']' expected");
3482       return MatchOperand_ParseFail;
3483     }
3484     EndLoc = Parser.getTok().getEndLoc();
3485     Parser.Lex(); // Eat the ']'.
3486     int64_t Val = CE->getValue();
3487 
3488     // FIXME: Make this range check context sensitive for .8, .16, .32.
3489     if (Val < 0 || Val > 7) {
3490       Error(Parser.getTok().getLoc(), "lane index out of range");
3491       return MatchOperand_ParseFail;
3492     }
3493     Index = Val;
3494     LaneKind = IndexedLane;
3495     return MatchOperand_Success;
3496   }
3497   LaneKind = NoLanes;
3498   return MatchOperand_Success;
3499 }
3500 
3501 // parse a vector register list
3502 ARMAsmParser::OperandMatchResultTy
3503 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3504   VectorLaneTy LaneKind;
3505   unsigned LaneIndex;
3506   SMLoc S = Parser.getTok().getLoc();
3507   // As an extension (to match gas), support a plain D register or Q register
3508   // (without encosing curly braces) as a single or double entry list,
3509   // respectively.
3510   if (Parser.getTok().is(AsmToken::Identifier)) {
3511     SMLoc E = Parser.getTok().getEndLoc();
3512     int Reg = tryParseRegister();
3513     if (Reg == -1)
3514       return MatchOperand_NoMatch;
3515     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3516       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3517       if (Res != MatchOperand_Success)
3518         return Res;
3519       switch (LaneKind) {
3520       case NoLanes:
3521         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3522         break;
3523       case AllLanes:
3524         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3525                                                                 S, E));
3526         break;
3527       case IndexedLane:
3528         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3529                                                                LaneIndex,
3530                                                                false, S, E));
3531         break;
3532       }
3533       return MatchOperand_Success;
3534     }
3535     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3536       Reg = getDRegFromQReg(Reg);
3537       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3538       if (Res != MatchOperand_Success)
3539         return Res;
3540       switch (LaneKind) {
3541       case NoLanes:
3542         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3543                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3544         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3545         break;
3546       case AllLanes:
3547         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3548                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3549         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3550                                                                 S, E));
3551         break;
3552       case IndexedLane:
3553         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3554                                                                LaneIndex,
3555                                                                false, S, E));
3556         break;
3557       }
3558       return MatchOperand_Success;
3559     }
3560     Error(S, "vector register expected");
3561     return MatchOperand_ParseFail;
3562   }
3563 
3564   if (Parser.getTok().isNot(AsmToken::LCurly))
3565     return MatchOperand_NoMatch;
3566 
3567   Parser.Lex(); // Eat '{' token.
3568   SMLoc RegLoc = Parser.getTok().getLoc();
3569 
3570   int Reg = tryParseRegister();
3571   if (Reg == -1) {
3572     Error(RegLoc, "register expected");
3573     return MatchOperand_ParseFail;
3574   }
3575   unsigned Count = 1;
3576   int Spacing = 0;
3577   unsigned FirstReg = Reg;
3578   // The list is of D registers, but we also allow Q regs and just interpret
3579   // them as the two D sub-registers.
3580   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3581     FirstReg = Reg = getDRegFromQReg(Reg);
3582     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3583                  // it's ambiguous with four-register single spaced.
3584     ++Reg;
3585     ++Count;
3586   }
3587 
3588   SMLoc E;
3589   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3590     return MatchOperand_ParseFail;
3591 
3592   while (Parser.getTok().is(AsmToken::Comma) ||
3593          Parser.getTok().is(AsmToken::Minus)) {
3594     if (Parser.getTok().is(AsmToken::Minus)) {
3595       if (!Spacing)
3596         Spacing = 1; // Register range implies a single spaced list.
3597       else if (Spacing == 2) {
3598         Error(Parser.getTok().getLoc(),
3599               "sequential registers in double spaced list");
3600         return MatchOperand_ParseFail;
3601       }
3602       Parser.Lex(); // Eat the minus.
3603       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3604       int EndReg = tryParseRegister();
3605       if (EndReg == -1) {
3606         Error(AfterMinusLoc, "register expected");
3607         return MatchOperand_ParseFail;
3608       }
3609       // Allow Q regs and just interpret them as the two D sub-registers.
3610       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3611         EndReg = getDRegFromQReg(EndReg) + 1;
3612       // If the register is the same as the start reg, there's nothing
3613       // more to do.
3614       if (Reg == EndReg)
3615         continue;
3616       // The register must be in the same register class as the first.
3617       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3618         Error(AfterMinusLoc, "invalid register in register list");
3619         return MatchOperand_ParseFail;
3620       }
3621       // Ranges must go from low to high.
3622       if (Reg > EndReg) {
3623         Error(AfterMinusLoc, "bad range in register list");
3624         return MatchOperand_ParseFail;
3625       }
3626       // Parse the lane specifier if present.
3627       VectorLaneTy NextLaneKind;
3628       unsigned NextLaneIndex;
3629       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3630           MatchOperand_Success)
3631         return MatchOperand_ParseFail;
3632       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3633         Error(AfterMinusLoc, "mismatched lane index in register list");
3634         return MatchOperand_ParseFail;
3635       }
3636 
3637       // Add all the registers in the range to the register list.
3638       Count += EndReg - Reg;
3639       Reg = EndReg;
3640       continue;
3641     }
3642     Parser.Lex(); // Eat the comma.
3643     RegLoc = Parser.getTok().getLoc();
3644     int OldReg = Reg;
3645     Reg = tryParseRegister();
3646     if (Reg == -1) {
3647       Error(RegLoc, "register expected");
3648       return MatchOperand_ParseFail;
3649     }
3650     // vector register lists must be contiguous.
3651     // It's OK to use the enumeration values directly here rather, as the
3652     // VFP register classes have the enum sorted properly.
3653     //
3654     // The list is of D registers, but we also allow Q regs and just interpret
3655     // them as the two D sub-registers.
3656     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3657       if (!Spacing)
3658         Spacing = 1; // Register range implies a single spaced list.
3659       else if (Spacing == 2) {
3660         Error(RegLoc,
3661               "invalid register in double-spaced list (must be 'D' register')");
3662         return MatchOperand_ParseFail;
3663       }
3664       Reg = getDRegFromQReg(Reg);
3665       if (Reg != OldReg + 1) {
3666         Error(RegLoc, "non-contiguous register range");
3667         return MatchOperand_ParseFail;
3668       }
3669       ++Reg;
3670       Count += 2;
3671       // Parse the lane specifier if present.
3672       VectorLaneTy NextLaneKind;
3673       unsigned NextLaneIndex;
3674       SMLoc LaneLoc = Parser.getTok().getLoc();
3675       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3676           MatchOperand_Success)
3677         return MatchOperand_ParseFail;
3678       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3679         Error(LaneLoc, "mismatched lane index in register list");
3680         return MatchOperand_ParseFail;
3681       }
3682       continue;
3683     }
3684     // Normal D register.
3685     // Figure out the register spacing (single or double) of the list if
3686     // we don't know it already.
3687     if (!Spacing)
3688       Spacing = 1 + (Reg == OldReg + 2);
3689 
3690     // Just check that it's contiguous and keep going.
3691     if (Reg != OldReg + Spacing) {
3692       Error(RegLoc, "non-contiguous register range");
3693       return MatchOperand_ParseFail;
3694     }
3695     ++Count;
3696     // Parse the lane specifier if present.
3697     VectorLaneTy NextLaneKind;
3698     unsigned NextLaneIndex;
3699     SMLoc EndLoc = Parser.getTok().getLoc();
3700     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3701       return MatchOperand_ParseFail;
3702     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3703       Error(EndLoc, "mismatched lane index in register list");
3704       return MatchOperand_ParseFail;
3705     }
3706   }
3707 
3708   if (Parser.getTok().isNot(AsmToken::RCurly)) {
3709     Error(Parser.getTok().getLoc(), "'}' expected");
3710     return MatchOperand_ParseFail;
3711   }
3712   E = Parser.getTok().getEndLoc();
3713   Parser.Lex(); // Eat '}' token.
3714 
3715   switch (LaneKind) {
3716   case NoLanes:
3717     // Two-register operands have been converted to the
3718     // composite register classes.
3719     if (Count == 2) {
3720       const MCRegisterClass *RC = (Spacing == 1) ?
3721         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3722         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3723       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3724     }
3725 
3726     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3727                                                     (Spacing == 2), S, E));
3728     break;
3729   case AllLanes:
3730     // Two-register operands have been converted to the
3731     // composite register classes.
3732     if (Count == 2) {
3733       const MCRegisterClass *RC = (Spacing == 1) ?
3734         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3735         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3736       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3737     }
3738     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3739                                                             (Spacing == 2),
3740                                                             S, E));
3741     break;
3742   case IndexedLane:
3743     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3744                                                            LaneIndex,
3745                                                            (Spacing == 2),
3746                                                            S, E));
3747     break;
3748   }
3749   return MatchOperand_Success;
3750 }
3751 
3752 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3753 ARMAsmParser::OperandMatchResultTy
3754 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3755   SMLoc S = Parser.getTok().getLoc();
3756   const AsmToken &Tok = Parser.getTok();
3757   unsigned Opt;
3758 
3759   if (Tok.is(AsmToken::Identifier)) {
3760     StringRef OptStr = Tok.getString();
3761 
3762     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3763       .Case("sy",    ARM_MB::SY)
3764       .Case("st",    ARM_MB::ST)
3765       .Case("ld",    ARM_MB::LD)
3766       .Case("sh",    ARM_MB::ISH)
3767       .Case("ish",   ARM_MB::ISH)
3768       .Case("shst",  ARM_MB::ISHST)
3769       .Case("ishst", ARM_MB::ISHST)
3770       .Case("ishld", ARM_MB::ISHLD)
3771       .Case("nsh",   ARM_MB::NSH)
3772       .Case("un",    ARM_MB::NSH)
3773       .Case("nshst", ARM_MB::NSHST)
3774       .Case("nshld", ARM_MB::NSHLD)
3775       .Case("unst",  ARM_MB::NSHST)
3776       .Case("osh",   ARM_MB::OSH)
3777       .Case("oshst", ARM_MB::OSHST)
3778       .Case("oshld", ARM_MB::OSHLD)
3779       .Default(~0U);
3780 
3781     // ishld, oshld, nshld and ld are only available from ARMv8.
3782     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3783                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3784       Opt = ~0U;
3785 
3786     if (Opt == ~0U)
3787       return MatchOperand_NoMatch;
3788 
3789     Parser.Lex(); // Eat identifier token.
3790   } else if (Tok.is(AsmToken::Hash) ||
3791              Tok.is(AsmToken::Dollar) ||
3792              Tok.is(AsmToken::Integer)) {
3793     if (Parser.getTok().isNot(AsmToken::Integer))
3794       Parser.Lex(); // Eat '#' or '$'.
3795     SMLoc Loc = Parser.getTok().getLoc();
3796 
3797     const MCExpr *MemBarrierID;
3798     if (getParser().parseExpression(MemBarrierID)) {
3799       Error(Loc, "illegal expression");
3800       return MatchOperand_ParseFail;
3801     }
3802 
3803     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3804     if (!CE) {
3805       Error(Loc, "constant expression expected");
3806       return MatchOperand_ParseFail;
3807     }
3808 
3809     int Val = CE->getValue();
3810     if (Val & ~0xf) {
3811       Error(Loc, "immediate value out of range");
3812       return MatchOperand_ParseFail;
3813     }
3814 
3815     Opt = ARM_MB::RESERVED_0 + Val;
3816   } else
3817     return MatchOperand_ParseFail;
3818 
3819   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3820   return MatchOperand_Success;
3821 }
3822 
3823 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3824 ARMAsmParser::OperandMatchResultTy
3825 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3826   SMLoc S = Parser.getTok().getLoc();
3827   const AsmToken &Tok = Parser.getTok();
3828   unsigned Opt;
3829 
3830   if (Tok.is(AsmToken::Identifier)) {
3831     StringRef OptStr = Tok.getString();
3832 
3833     if (OptStr.equals_lower("sy"))
3834       Opt = ARM_ISB::SY;
3835     else
3836       return MatchOperand_NoMatch;
3837 
3838     Parser.Lex(); // Eat identifier token.
3839   } else if (Tok.is(AsmToken::Hash) ||
3840              Tok.is(AsmToken::Dollar) ||
3841              Tok.is(AsmToken::Integer)) {
3842     if (Parser.getTok().isNot(AsmToken::Integer))
3843       Parser.Lex(); // Eat '#' or '$'.
3844     SMLoc Loc = Parser.getTok().getLoc();
3845 
3846     const MCExpr *ISBarrierID;
3847     if (getParser().parseExpression(ISBarrierID)) {
3848       Error(Loc, "illegal expression");
3849       return MatchOperand_ParseFail;
3850     }
3851 
3852     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3853     if (!CE) {
3854       Error(Loc, "constant expression expected");
3855       return MatchOperand_ParseFail;
3856     }
3857 
3858     int Val = CE->getValue();
3859     if (Val & ~0xf) {
3860       Error(Loc, "immediate value out of range");
3861       return MatchOperand_ParseFail;
3862     }
3863 
3864     Opt = ARM_ISB::RESERVED_0 + Val;
3865   } else
3866     return MatchOperand_ParseFail;
3867 
3868   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3869           (ARM_ISB::InstSyncBOpt)Opt, S));
3870   return MatchOperand_Success;
3871 }
3872 
3873 
3874 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3875 ARMAsmParser::OperandMatchResultTy
3876 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3877   SMLoc S = Parser.getTok().getLoc();
3878   const AsmToken &Tok = Parser.getTok();
3879   if (!Tok.is(AsmToken::Identifier))
3880     return MatchOperand_NoMatch;
3881   StringRef IFlagsStr = Tok.getString();
3882 
3883   // An iflags string of "none" is interpreted to mean that none of the AIF
3884   // bits are set.  Not a terribly useful instruction, but a valid encoding.
3885   unsigned IFlags = 0;
3886   if (IFlagsStr != "none") {
3887         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3888       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3889         .Case("a", ARM_PROC::A)
3890         .Case("i", ARM_PROC::I)
3891         .Case("f", ARM_PROC::F)
3892         .Default(~0U);
3893 
3894       // If some specific iflag is already set, it means that some letter is
3895       // present more than once, this is not acceptable.
3896       if (Flag == ~0U || (IFlags & Flag))
3897         return MatchOperand_NoMatch;
3898 
3899       IFlags |= Flag;
3900     }
3901   }
3902 
3903   Parser.Lex(); // Eat identifier token.
3904   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3905   return MatchOperand_Success;
3906 }
3907 
3908 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3909 ARMAsmParser::OperandMatchResultTy
3910 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3911   SMLoc S = Parser.getTok().getLoc();
3912   const AsmToken &Tok = Parser.getTok();
3913   if (!Tok.is(AsmToken::Identifier))
3914     return MatchOperand_NoMatch;
3915   StringRef Mask = Tok.getString();
3916 
3917   if (isMClass()) {
3918     // See ARMv6-M 10.1.1
3919     std::string Name = Mask.lower();
3920     unsigned FlagsVal = StringSwitch<unsigned>(Name)
3921       // Note: in the documentation:
3922       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3923       //  for MSR APSR_nzcvq.
3924       // but we do make it an alias here.  This is so to get the "mask encoding"
3925       // bits correct on MSR APSR writes.
3926       //
3927       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3928       // should really only be allowed when writing a special register.  Note
3929       // they get dropped in the MRS instruction reading a special register as
3930       // the SYSm field is only 8 bits.
3931       //
3932       // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3933       // includes the DSP extension but that is not checked.
3934       .Case("apsr", 0x800)
3935       .Case("apsr_nzcvq", 0x800)
3936       .Case("apsr_g", 0x400)
3937       .Case("apsr_nzcvqg", 0xc00)
3938       .Case("iapsr", 0x801)
3939       .Case("iapsr_nzcvq", 0x801)
3940       .Case("iapsr_g", 0x401)
3941       .Case("iapsr_nzcvqg", 0xc01)
3942       .Case("eapsr", 0x802)
3943       .Case("eapsr_nzcvq", 0x802)
3944       .Case("eapsr_g", 0x402)
3945       .Case("eapsr_nzcvqg", 0xc02)
3946       .Case("xpsr", 0x803)
3947       .Case("xpsr_nzcvq", 0x803)
3948       .Case("xpsr_g", 0x403)
3949       .Case("xpsr_nzcvqg", 0xc03)
3950       .Case("ipsr", 0x805)
3951       .Case("epsr", 0x806)
3952       .Case("iepsr", 0x807)
3953       .Case("msp", 0x808)
3954       .Case("psp", 0x809)
3955       .Case("primask", 0x810)
3956       .Case("basepri", 0x811)
3957       .Case("basepri_max", 0x812)
3958       .Case("faultmask", 0x813)
3959       .Case("control", 0x814)
3960       .Default(~0U);
3961 
3962     if (FlagsVal == ~0U)
3963       return MatchOperand_NoMatch;
3964 
3965     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3966       // basepri, basepri_max and faultmask only valid for V7m.
3967       return MatchOperand_NoMatch;
3968 
3969     Parser.Lex(); // Eat identifier token.
3970     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3971     return MatchOperand_Success;
3972   }
3973 
3974   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3975   size_t Start = 0, Next = Mask.find('_');
3976   StringRef Flags = "";
3977   std::string SpecReg = Mask.slice(Start, Next).lower();
3978   if (Next != StringRef::npos)
3979     Flags = Mask.slice(Next+1, Mask.size());
3980 
3981   // FlagsVal contains the complete mask:
3982   // 3-0: Mask
3983   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3984   unsigned FlagsVal = 0;
3985 
3986   if (SpecReg == "apsr") {
3987     FlagsVal = StringSwitch<unsigned>(Flags)
3988     .Case("nzcvq",  0x8) // same as CPSR_f
3989     .Case("g",      0x4) // same as CPSR_s
3990     .Case("nzcvqg", 0xc) // same as CPSR_fs
3991     .Default(~0U);
3992 
3993     if (FlagsVal == ~0U) {
3994       if (!Flags.empty())
3995         return MatchOperand_NoMatch;
3996       else
3997         FlagsVal = 8; // No flag
3998     }
3999   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4000     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4001     if (Flags == "all" || Flags == "")
4002       Flags = "fc";
4003     for (int i = 0, e = Flags.size(); i != e; ++i) {
4004       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4005       .Case("c", 1)
4006       .Case("x", 2)
4007       .Case("s", 4)
4008       .Case("f", 8)
4009       .Default(~0U);
4010 
4011       // If some specific flag is already set, it means that some letter is
4012       // present more than once, this is not acceptable.
4013       if (FlagsVal == ~0U || (FlagsVal & Flag))
4014         return MatchOperand_NoMatch;
4015       FlagsVal |= Flag;
4016     }
4017   } else // No match for special register.
4018     return MatchOperand_NoMatch;
4019 
4020   // Special register without flags is NOT equivalent to "fc" flags.
4021   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
4022   // two lines would enable gas compatibility at the expense of breaking
4023   // round-tripping.
4024   //
4025   // if (!FlagsVal)
4026   //  FlagsVal = 0x9;
4027 
4028   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4029   if (SpecReg == "spsr")
4030     FlagsVal |= 16;
4031 
4032   Parser.Lex(); // Eat identifier token.
4033   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4034   return MatchOperand_Success;
4035 }
4036 
4037 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4038 /// use in the MRS/MSR instructions added to support virtualization.
4039 ARMAsmParser::OperandMatchResultTy
4040 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4041   SMLoc S = Parser.getTok().getLoc();
4042   const AsmToken &Tok = Parser.getTok();
4043   if (!Tok.is(AsmToken::Identifier))
4044     return MatchOperand_NoMatch;
4045   StringRef RegName = Tok.getString();
4046 
4047   // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4048   // and bit 5 is R.
4049   unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4050                           .Case("r8_usr", 0x00)
4051                           .Case("r9_usr", 0x01)
4052                           .Case("r10_usr", 0x02)
4053                           .Case("r11_usr", 0x03)
4054                           .Case("r12_usr", 0x04)
4055                           .Case("sp_usr", 0x05)
4056                           .Case("lr_usr", 0x06)
4057                           .Case("r8_fiq", 0x08)
4058                           .Case("r9_fiq", 0x09)
4059                           .Case("r10_fiq", 0x0a)
4060                           .Case("r11_fiq", 0x0b)
4061                           .Case("r12_fiq", 0x0c)
4062                           .Case("sp_fiq", 0x0d)
4063                           .Case("lr_fiq", 0x0e)
4064                           .Case("lr_irq", 0x10)
4065                           .Case("sp_irq", 0x11)
4066                           .Case("lr_svc", 0x12)
4067                           .Case("sp_svc", 0x13)
4068                           .Case("lr_abt", 0x14)
4069                           .Case("sp_abt", 0x15)
4070                           .Case("lr_und", 0x16)
4071                           .Case("sp_und", 0x17)
4072                           .Case("lr_mon", 0x1c)
4073                           .Case("sp_mon", 0x1d)
4074                           .Case("elr_hyp", 0x1e)
4075                           .Case("sp_hyp", 0x1f)
4076                           .Case("spsr_fiq", 0x2e)
4077                           .Case("spsr_irq", 0x30)
4078                           .Case("spsr_svc", 0x32)
4079                           .Case("spsr_abt", 0x34)
4080                           .Case("spsr_und", 0x36)
4081                           .Case("spsr_mon", 0x3c)
4082                           .Case("spsr_hyp", 0x3e)
4083                           .Default(~0U);
4084 
4085   if (Encoding == ~0U)
4086     return MatchOperand_NoMatch;
4087 
4088   Parser.Lex(); // Eat identifier token.
4089   Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4090   return MatchOperand_Success;
4091 }
4092 
4093 ARMAsmParser::OperandMatchResultTy
4094 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4095                           int High) {
4096   const AsmToken &Tok = Parser.getTok();
4097   if (Tok.isNot(AsmToken::Identifier)) {
4098     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4099     return MatchOperand_ParseFail;
4100   }
4101   StringRef ShiftName = Tok.getString();
4102   std::string LowerOp = Op.lower();
4103   std::string UpperOp = Op.upper();
4104   if (ShiftName != LowerOp && ShiftName != UpperOp) {
4105     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4106     return MatchOperand_ParseFail;
4107   }
4108   Parser.Lex(); // Eat shift type token.
4109 
4110   // There must be a '#' and a shift amount.
4111   if (Parser.getTok().isNot(AsmToken::Hash) &&
4112       Parser.getTok().isNot(AsmToken::Dollar)) {
4113     Error(Parser.getTok().getLoc(), "'#' expected");
4114     return MatchOperand_ParseFail;
4115   }
4116   Parser.Lex(); // Eat hash token.
4117 
4118   const MCExpr *ShiftAmount;
4119   SMLoc Loc = Parser.getTok().getLoc();
4120   SMLoc EndLoc;
4121   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4122     Error(Loc, "illegal expression");
4123     return MatchOperand_ParseFail;
4124   }
4125   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4126   if (!CE) {
4127     Error(Loc, "constant expression expected");
4128     return MatchOperand_ParseFail;
4129   }
4130   int Val = CE->getValue();
4131   if (Val < Low || Val > High) {
4132     Error(Loc, "immediate value out of range");
4133     return MatchOperand_ParseFail;
4134   }
4135 
4136   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4137 
4138   return MatchOperand_Success;
4139 }
4140 
4141 ARMAsmParser::OperandMatchResultTy
4142 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4143   const AsmToken &Tok = Parser.getTok();
4144   SMLoc S = Tok.getLoc();
4145   if (Tok.isNot(AsmToken::Identifier)) {
4146     Error(S, "'be' or 'le' operand expected");
4147     return MatchOperand_ParseFail;
4148   }
4149   int Val = StringSwitch<int>(Tok.getString().lower())
4150     .Case("be", 1)
4151     .Case("le", 0)
4152     .Default(-1);
4153   Parser.Lex(); // Eat the token.
4154 
4155   if (Val == -1) {
4156     Error(S, "'be' or 'le' operand expected");
4157     return MatchOperand_ParseFail;
4158   }
4159   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4160                                                                   getContext()),
4161                                            S, Tok.getEndLoc()));
4162   return MatchOperand_Success;
4163 }
4164 
4165 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4166 /// instructions. Legal values are:
4167 ///     lsl #n  'n' in [0,31]
4168 ///     asr #n  'n' in [1,32]
4169 ///             n == 32 encoded as n == 0.
4170 ARMAsmParser::OperandMatchResultTy
4171 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4172   const AsmToken &Tok = Parser.getTok();
4173   SMLoc S = Tok.getLoc();
4174   if (Tok.isNot(AsmToken::Identifier)) {
4175     Error(S, "shift operator 'asr' or 'lsl' expected");
4176     return MatchOperand_ParseFail;
4177   }
4178   StringRef ShiftName = Tok.getString();
4179   bool isASR;
4180   if (ShiftName == "lsl" || ShiftName == "LSL")
4181     isASR = false;
4182   else if (ShiftName == "asr" || ShiftName == "ASR")
4183     isASR = true;
4184   else {
4185     Error(S, "shift operator 'asr' or 'lsl' expected");
4186     return MatchOperand_ParseFail;
4187   }
4188   Parser.Lex(); // Eat the operator.
4189 
4190   // A '#' and a shift amount.
4191   if (Parser.getTok().isNot(AsmToken::Hash) &&
4192       Parser.getTok().isNot(AsmToken::Dollar)) {
4193     Error(Parser.getTok().getLoc(), "'#' expected");
4194     return MatchOperand_ParseFail;
4195   }
4196   Parser.Lex(); // Eat hash token.
4197   SMLoc ExLoc = Parser.getTok().getLoc();
4198 
4199   const MCExpr *ShiftAmount;
4200   SMLoc EndLoc;
4201   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4202     Error(ExLoc, "malformed shift expression");
4203     return MatchOperand_ParseFail;
4204   }
4205   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4206   if (!CE) {
4207     Error(ExLoc, "shift amount must be an immediate");
4208     return MatchOperand_ParseFail;
4209   }
4210 
4211   int64_t Val = CE->getValue();
4212   if (isASR) {
4213     // Shift amount must be in [1,32]
4214     if (Val < 1 || Val > 32) {
4215       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4216       return MatchOperand_ParseFail;
4217     }
4218     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4219     if (isThumb() && Val == 32) {
4220       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4221       return MatchOperand_ParseFail;
4222     }
4223     if (Val == 32) Val = 0;
4224   } else {
4225     // Shift amount must be in [1,32]
4226     if (Val < 0 || Val > 31) {
4227       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4228       return MatchOperand_ParseFail;
4229     }
4230   }
4231 
4232   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4233 
4234   return MatchOperand_Success;
4235 }
4236 
4237 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4238 /// of instructions. Legal values are:
4239 ///     ror #n  'n' in {0, 8, 16, 24}
4240 ARMAsmParser::OperandMatchResultTy
4241 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4242   const AsmToken &Tok = Parser.getTok();
4243   SMLoc S = Tok.getLoc();
4244   if (Tok.isNot(AsmToken::Identifier))
4245     return MatchOperand_NoMatch;
4246   StringRef ShiftName = Tok.getString();
4247   if (ShiftName != "ror" && ShiftName != "ROR")
4248     return MatchOperand_NoMatch;
4249   Parser.Lex(); // Eat the operator.
4250 
4251   // A '#' and a rotate amount.
4252   if (Parser.getTok().isNot(AsmToken::Hash) &&
4253       Parser.getTok().isNot(AsmToken::Dollar)) {
4254     Error(Parser.getTok().getLoc(), "'#' expected");
4255     return MatchOperand_ParseFail;
4256   }
4257   Parser.Lex(); // Eat hash token.
4258   SMLoc ExLoc = Parser.getTok().getLoc();
4259 
4260   const MCExpr *ShiftAmount;
4261   SMLoc EndLoc;
4262   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4263     Error(ExLoc, "malformed rotate expression");
4264     return MatchOperand_ParseFail;
4265   }
4266   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4267   if (!CE) {
4268     Error(ExLoc, "rotate amount must be an immediate");
4269     return MatchOperand_ParseFail;
4270   }
4271 
4272   int64_t Val = CE->getValue();
4273   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4274   // normally, zero is represented in asm by omitting the rotate operand
4275   // entirely.
4276   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4277     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4278     return MatchOperand_ParseFail;
4279   }
4280 
4281   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4282 
4283   return MatchOperand_Success;
4284 }
4285 
4286 ARMAsmParser::OperandMatchResultTy
4287 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4288   SMLoc S = Parser.getTok().getLoc();
4289   // The bitfield descriptor is really two operands, the LSB and the width.
4290   if (Parser.getTok().isNot(AsmToken::Hash) &&
4291       Parser.getTok().isNot(AsmToken::Dollar)) {
4292     Error(Parser.getTok().getLoc(), "'#' expected");
4293     return MatchOperand_ParseFail;
4294   }
4295   Parser.Lex(); // Eat hash token.
4296 
4297   const MCExpr *LSBExpr;
4298   SMLoc E = Parser.getTok().getLoc();
4299   if (getParser().parseExpression(LSBExpr)) {
4300     Error(E, "malformed immediate expression");
4301     return MatchOperand_ParseFail;
4302   }
4303   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4304   if (!CE) {
4305     Error(E, "'lsb' operand must be an immediate");
4306     return MatchOperand_ParseFail;
4307   }
4308 
4309   int64_t LSB = CE->getValue();
4310   // The LSB must be in the range [0,31]
4311   if (LSB < 0 || LSB > 31) {
4312     Error(E, "'lsb' operand must be in the range [0,31]");
4313     return MatchOperand_ParseFail;
4314   }
4315   E = Parser.getTok().getLoc();
4316 
4317   // Expect another immediate operand.
4318   if (Parser.getTok().isNot(AsmToken::Comma)) {
4319     Error(Parser.getTok().getLoc(), "too few operands");
4320     return MatchOperand_ParseFail;
4321   }
4322   Parser.Lex(); // Eat hash token.
4323   if (Parser.getTok().isNot(AsmToken::Hash) &&
4324       Parser.getTok().isNot(AsmToken::Dollar)) {
4325     Error(Parser.getTok().getLoc(), "'#' expected");
4326     return MatchOperand_ParseFail;
4327   }
4328   Parser.Lex(); // Eat hash token.
4329 
4330   const MCExpr *WidthExpr;
4331   SMLoc EndLoc;
4332   if (getParser().parseExpression(WidthExpr, EndLoc)) {
4333     Error(E, "malformed immediate expression");
4334     return MatchOperand_ParseFail;
4335   }
4336   CE = dyn_cast<MCConstantExpr>(WidthExpr);
4337   if (!CE) {
4338     Error(E, "'width' operand must be an immediate");
4339     return MatchOperand_ParseFail;
4340   }
4341 
4342   int64_t Width = CE->getValue();
4343   // The LSB must be in the range [1,32-lsb]
4344   if (Width < 1 || Width > 32 - LSB) {
4345     Error(E, "'width' operand must be in the range [1,32-lsb]");
4346     return MatchOperand_ParseFail;
4347   }
4348 
4349   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4350 
4351   return MatchOperand_Success;
4352 }
4353 
4354 ARMAsmParser::OperandMatchResultTy
4355 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4356   // Check for a post-index addressing register operand. Specifically:
4357   // postidx_reg := '+' register {, shift}
4358   //              | '-' register {, shift}
4359   //              | register {, shift}
4360 
4361   // This method must return MatchOperand_NoMatch without consuming any tokens
4362   // in the case where there is no match, as other alternatives take other
4363   // parse methods.
4364   AsmToken Tok = Parser.getTok();
4365   SMLoc S = Tok.getLoc();
4366   bool haveEaten = false;
4367   bool isAdd = true;
4368   if (Tok.is(AsmToken::Plus)) {
4369     Parser.Lex(); // Eat the '+' token.
4370     haveEaten = true;
4371   } else if (Tok.is(AsmToken::Minus)) {
4372     Parser.Lex(); // Eat the '-' token.
4373     isAdd = false;
4374     haveEaten = true;
4375   }
4376 
4377   SMLoc E = Parser.getTok().getEndLoc();
4378   int Reg = tryParseRegister();
4379   if (Reg == -1) {
4380     if (!haveEaten)
4381       return MatchOperand_NoMatch;
4382     Error(Parser.getTok().getLoc(), "register expected");
4383     return MatchOperand_ParseFail;
4384   }
4385 
4386   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4387   unsigned ShiftImm = 0;
4388   if (Parser.getTok().is(AsmToken::Comma)) {
4389     Parser.Lex(); // Eat the ','.
4390     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4391       return MatchOperand_ParseFail;
4392 
4393     // FIXME: Only approximates end...may include intervening whitespace.
4394     E = Parser.getTok().getLoc();
4395   }
4396 
4397   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4398                                                   ShiftImm, S, E));
4399 
4400   return MatchOperand_Success;
4401 }
4402 
4403 ARMAsmParser::OperandMatchResultTy
4404 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4405   // Check for a post-index addressing register operand. Specifically:
4406   // am3offset := '+' register
4407   //              | '-' register
4408   //              | register
4409   //              | # imm
4410   //              | # + imm
4411   //              | # - imm
4412 
4413   // This method must return MatchOperand_NoMatch without consuming any tokens
4414   // in the case where there is no match, as other alternatives take other
4415   // parse methods.
4416   AsmToken Tok = Parser.getTok();
4417   SMLoc S = Tok.getLoc();
4418 
4419   // Do immediates first, as we always parse those if we have a '#'.
4420   if (Parser.getTok().is(AsmToken::Hash) ||
4421       Parser.getTok().is(AsmToken::Dollar)) {
4422     Parser.Lex(); // Eat '#' or '$'.
4423     // Explicitly look for a '-', as we need to encode negative zero
4424     // differently.
4425     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4426     const MCExpr *Offset;
4427     SMLoc E;
4428     if (getParser().parseExpression(Offset, E))
4429       return MatchOperand_ParseFail;
4430     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4431     if (!CE) {
4432       Error(S, "constant expression expected");
4433       return MatchOperand_ParseFail;
4434     }
4435     // Negative zero is encoded as the flag value INT32_MIN.
4436     int32_t Val = CE->getValue();
4437     if (isNegative && Val == 0)
4438       Val = INT32_MIN;
4439 
4440     Operands.push_back(
4441       ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4442 
4443     return MatchOperand_Success;
4444   }
4445 
4446 
4447   bool haveEaten = false;
4448   bool isAdd = true;
4449   if (Tok.is(AsmToken::Plus)) {
4450     Parser.Lex(); // Eat the '+' token.
4451     haveEaten = true;
4452   } else if (Tok.is(AsmToken::Minus)) {
4453     Parser.Lex(); // Eat the '-' token.
4454     isAdd = false;
4455     haveEaten = true;
4456   }
4457 
4458   Tok = Parser.getTok();
4459   int Reg = tryParseRegister();
4460   if (Reg == -1) {
4461     if (!haveEaten)
4462       return MatchOperand_NoMatch;
4463     Error(Tok.getLoc(), "register expected");
4464     return MatchOperand_ParseFail;
4465   }
4466 
4467   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4468                                                   0, S, Tok.getEndLoc()));
4469 
4470   return MatchOperand_Success;
4471 }
4472 
4473 /// Convert parsed operands to MCInst.  Needed here because this instruction
4474 /// only has two register operands, but multiplication is commutative so
4475 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4476 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4477                                     const OperandVector &Operands) {
4478   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4479   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4480   // If we have a three-operand form, make sure to set Rn to be the operand
4481   // that isn't the same as Rd.
4482   unsigned RegOp = 4;
4483   if (Operands.size() == 6 &&
4484       ((ARMOperand &)*Operands[4]).getReg() ==
4485           ((ARMOperand &)*Operands[3]).getReg())
4486     RegOp = 5;
4487   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4488   Inst.addOperand(Inst.getOperand(0));
4489   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4490 }
4491 
4492 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4493                                     const OperandVector &Operands) {
4494   int CondOp = -1, ImmOp = -1;
4495   switch(Inst.getOpcode()) {
4496     case ARM::tB:
4497     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4498 
4499     case ARM::t2B:
4500     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4501 
4502     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4503   }
4504   // first decide whether or not the branch should be conditional
4505   // by looking at it's location relative to an IT block
4506   if(inITBlock()) {
4507     // inside an IT block we cannot have any conditional branches. any
4508     // such instructions needs to be converted to unconditional form
4509     switch(Inst.getOpcode()) {
4510       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4511       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4512     }
4513   } else {
4514     // outside IT blocks we can only have unconditional branches with AL
4515     // condition code or conditional branches with non-AL condition code
4516     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4517     switch(Inst.getOpcode()) {
4518       case ARM::tB:
4519       case ARM::tBcc:
4520         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4521         break;
4522       case ARM::t2B:
4523       case ARM::t2Bcc:
4524         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4525         break;
4526     }
4527   }
4528 
4529   // now decide on encoding size based on branch target range
4530   switch(Inst.getOpcode()) {
4531     // classify tB as either t2B or t1B based on range of immediate operand
4532     case ARM::tB: {
4533       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4534       if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4535         Inst.setOpcode(ARM::t2B);
4536       break;
4537     }
4538     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4539     case ARM::tBcc: {
4540       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4541       if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4542         Inst.setOpcode(ARM::t2Bcc);
4543       break;
4544     }
4545   }
4546   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4547   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4548 }
4549 
4550 /// Parse an ARM memory expression, return false if successful else return true
4551 /// or an error.  The first token must be a '[' when called.
4552 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4553   SMLoc S, E;
4554   assert(Parser.getTok().is(AsmToken::LBrac) &&
4555          "Token is not a Left Bracket");
4556   S = Parser.getTok().getLoc();
4557   Parser.Lex(); // Eat left bracket token.
4558 
4559   const AsmToken &BaseRegTok = Parser.getTok();
4560   int BaseRegNum = tryParseRegister();
4561   if (BaseRegNum == -1)
4562     return Error(BaseRegTok.getLoc(), "register expected");
4563 
4564   // The next token must either be a comma, a colon or a closing bracket.
4565   const AsmToken &Tok = Parser.getTok();
4566   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4567       !Tok.is(AsmToken::RBrac))
4568     return Error(Tok.getLoc(), "malformed memory operand");
4569 
4570   if (Tok.is(AsmToken::RBrac)) {
4571     E = Tok.getEndLoc();
4572     Parser.Lex(); // Eat right bracket token.
4573 
4574     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4575                                              ARM_AM::no_shift, 0, 0, false,
4576                                              S, E));
4577 
4578     // If there's a pre-indexing writeback marker, '!', just add it as a token
4579     // operand. It's rather odd, but syntactically valid.
4580     if (Parser.getTok().is(AsmToken::Exclaim)) {
4581       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4582       Parser.Lex(); // Eat the '!'.
4583     }
4584 
4585     return false;
4586   }
4587 
4588   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4589          "Lost colon or comma in memory operand?!");
4590   if (Tok.is(AsmToken::Comma)) {
4591     Parser.Lex(); // Eat the comma.
4592   }
4593 
4594   // If we have a ':', it's an alignment specifier.
4595   if (Parser.getTok().is(AsmToken::Colon)) {
4596     Parser.Lex(); // Eat the ':'.
4597     E = Parser.getTok().getLoc();
4598     SMLoc AlignmentLoc = Tok.getLoc();
4599 
4600     const MCExpr *Expr;
4601     if (getParser().parseExpression(Expr))
4602      return true;
4603 
4604     // The expression has to be a constant. Memory references with relocations
4605     // don't come through here, as they use the <label> forms of the relevant
4606     // instructions.
4607     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4608     if (!CE)
4609       return Error (E, "constant expression expected");
4610 
4611     unsigned Align = 0;
4612     switch (CE->getValue()) {
4613     default:
4614       return Error(E,
4615                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4616     case 16:  Align = 2; break;
4617     case 32:  Align = 4; break;
4618     case 64:  Align = 8; break;
4619     case 128: Align = 16; break;
4620     case 256: Align = 32; break;
4621     }
4622 
4623     // Now we should have the closing ']'
4624     if (Parser.getTok().isNot(AsmToken::RBrac))
4625       return Error(Parser.getTok().getLoc(), "']' expected");
4626     E = Parser.getTok().getEndLoc();
4627     Parser.Lex(); // Eat right bracket token.
4628 
4629     // Don't worry about range checking the value here. That's handled by
4630     // the is*() predicates.
4631     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4632                                              ARM_AM::no_shift, 0, Align,
4633                                              false, S, E, AlignmentLoc));
4634 
4635     // If there's a pre-indexing writeback marker, '!', just add it as a token
4636     // operand.
4637     if (Parser.getTok().is(AsmToken::Exclaim)) {
4638       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4639       Parser.Lex(); // Eat the '!'.
4640     }
4641 
4642     return false;
4643   }
4644 
4645   // If we have a '#', it's an immediate offset, else assume it's a register
4646   // offset. Be friendly and also accept a plain integer (without a leading
4647   // hash) for gas compatibility.
4648   if (Parser.getTok().is(AsmToken::Hash) ||
4649       Parser.getTok().is(AsmToken::Dollar) ||
4650       Parser.getTok().is(AsmToken::Integer)) {
4651     if (Parser.getTok().isNot(AsmToken::Integer))
4652       Parser.Lex(); // Eat '#' or '$'.
4653     E = Parser.getTok().getLoc();
4654 
4655     bool isNegative = getParser().getTok().is(AsmToken::Minus);
4656     const MCExpr *Offset;
4657     if (getParser().parseExpression(Offset))
4658      return true;
4659 
4660     // The expression has to be a constant. Memory references with relocations
4661     // don't come through here, as they use the <label> forms of the relevant
4662     // instructions.
4663     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4664     if (!CE)
4665       return Error (E, "constant expression expected");
4666 
4667     // If the constant was #-0, represent it as INT32_MIN.
4668     int32_t Val = CE->getValue();
4669     if (isNegative && Val == 0)
4670       CE = MCConstantExpr::Create(INT32_MIN, getContext());
4671 
4672     // Now we should have the closing ']'
4673     if (Parser.getTok().isNot(AsmToken::RBrac))
4674       return Error(Parser.getTok().getLoc(), "']' expected");
4675     E = Parser.getTok().getEndLoc();
4676     Parser.Lex(); // Eat right bracket token.
4677 
4678     // Don't worry about range checking the value here. That's handled by
4679     // the is*() predicates.
4680     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4681                                              ARM_AM::no_shift, 0, 0,
4682                                              false, S, E));
4683 
4684     // If there's a pre-indexing writeback marker, '!', just add it as a token
4685     // operand.
4686     if (Parser.getTok().is(AsmToken::Exclaim)) {
4687       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4688       Parser.Lex(); // Eat the '!'.
4689     }
4690 
4691     return false;
4692   }
4693 
4694   // The register offset is optionally preceded by a '+' or '-'
4695   bool isNegative = false;
4696   if (Parser.getTok().is(AsmToken::Minus)) {
4697     isNegative = true;
4698     Parser.Lex(); // Eat the '-'.
4699   } else if (Parser.getTok().is(AsmToken::Plus)) {
4700     // Nothing to do.
4701     Parser.Lex(); // Eat the '+'.
4702   }
4703 
4704   E = Parser.getTok().getLoc();
4705   int OffsetRegNum = tryParseRegister();
4706   if (OffsetRegNum == -1)
4707     return Error(E, "register expected");
4708 
4709   // If there's a shift operator, handle it.
4710   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4711   unsigned ShiftImm = 0;
4712   if (Parser.getTok().is(AsmToken::Comma)) {
4713     Parser.Lex(); // Eat the ','.
4714     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4715       return true;
4716   }
4717 
4718   // Now we should have the closing ']'
4719   if (Parser.getTok().isNot(AsmToken::RBrac))
4720     return Error(Parser.getTok().getLoc(), "']' expected");
4721   E = Parser.getTok().getEndLoc();
4722   Parser.Lex(); // Eat right bracket token.
4723 
4724   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4725                                            ShiftType, ShiftImm, 0, isNegative,
4726                                            S, E));
4727 
4728   // If there's a pre-indexing writeback marker, '!', just add it as a token
4729   // operand.
4730   if (Parser.getTok().is(AsmToken::Exclaim)) {
4731     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4732     Parser.Lex(); // Eat the '!'.
4733   }
4734 
4735   return false;
4736 }
4737 
4738 /// parseMemRegOffsetShift - one of these two:
4739 ///   ( lsl | lsr | asr | ror ) , # shift_amount
4740 ///   rrx
4741 /// return true if it parses a shift otherwise it returns false.
4742 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4743                                           unsigned &Amount) {
4744   SMLoc Loc = Parser.getTok().getLoc();
4745   const AsmToken &Tok = Parser.getTok();
4746   if (Tok.isNot(AsmToken::Identifier))
4747     return true;
4748   StringRef ShiftName = Tok.getString();
4749   if (ShiftName == "lsl" || ShiftName == "LSL" ||
4750       ShiftName == "asl" || ShiftName == "ASL")
4751     St = ARM_AM::lsl;
4752   else if (ShiftName == "lsr" || ShiftName == "LSR")
4753     St = ARM_AM::lsr;
4754   else if (ShiftName == "asr" || ShiftName == "ASR")
4755     St = ARM_AM::asr;
4756   else if (ShiftName == "ror" || ShiftName == "ROR")
4757     St = ARM_AM::ror;
4758   else if (ShiftName == "rrx" || ShiftName == "RRX")
4759     St = ARM_AM::rrx;
4760   else
4761     return Error(Loc, "illegal shift operator");
4762   Parser.Lex(); // Eat shift type token.
4763 
4764   // rrx stands alone.
4765   Amount = 0;
4766   if (St != ARM_AM::rrx) {
4767     Loc = Parser.getTok().getLoc();
4768     // A '#' and a shift amount.
4769     const AsmToken &HashTok = Parser.getTok();
4770     if (HashTok.isNot(AsmToken::Hash) &&
4771         HashTok.isNot(AsmToken::Dollar))
4772       return Error(HashTok.getLoc(), "'#' expected");
4773     Parser.Lex(); // Eat hash token.
4774 
4775     const MCExpr *Expr;
4776     if (getParser().parseExpression(Expr))
4777       return true;
4778     // Range check the immediate.
4779     // lsl, ror: 0 <= imm <= 31
4780     // lsr, asr: 0 <= imm <= 32
4781     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4782     if (!CE)
4783       return Error(Loc, "shift amount must be an immediate");
4784     int64_t Imm = CE->getValue();
4785     if (Imm < 0 ||
4786         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4787         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4788       return Error(Loc, "immediate shift value out of range");
4789     // If <ShiftTy> #0, turn it into a no_shift.
4790     if (Imm == 0)
4791       St = ARM_AM::lsl;
4792     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4793     if (Imm == 32)
4794       Imm = 0;
4795     Amount = Imm;
4796   }
4797 
4798   return false;
4799 }
4800 
4801 /// parseFPImm - A floating point immediate expression operand.
4802 ARMAsmParser::OperandMatchResultTy
4803 ARMAsmParser::parseFPImm(OperandVector &Operands) {
4804   // Anything that can accept a floating point constant as an operand
4805   // needs to go through here, as the regular parseExpression is
4806   // integer only.
4807   //
4808   // This routine still creates a generic Immediate operand, containing
4809   // a bitcast of the 64-bit floating point value. The various operands
4810   // that accept floats can check whether the value is valid for them
4811   // via the standard is*() predicates.
4812 
4813   SMLoc S = Parser.getTok().getLoc();
4814 
4815   if (Parser.getTok().isNot(AsmToken::Hash) &&
4816       Parser.getTok().isNot(AsmToken::Dollar))
4817     return MatchOperand_NoMatch;
4818 
4819   // Disambiguate the VMOV forms that can accept an FP immediate.
4820   // vmov.f32 <sreg>, #imm
4821   // vmov.f64 <dreg>, #imm
4822   // vmov.f32 <dreg>, #imm  @ vector f32x2
4823   // vmov.f32 <qreg>, #imm  @ vector f32x4
4824   //
4825   // There are also the NEON VMOV instructions which expect an
4826   // integer constant. Make sure we don't try to parse an FPImm
4827   // for these:
4828   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4829   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
4830   bool isVmovf = TyOp.isToken() &&
4831                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
4832   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
4833   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
4834                                          Mnemonic.getToken() == "fconsts");
4835   if (!(isVmovf || isFconst))
4836     return MatchOperand_NoMatch;
4837 
4838   Parser.Lex(); // Eat '#' or '$'.
4839 
4840   // Handle negation, as that still comes through as a separate token.
4841   bool isNegative = false;
4842   if (Parser.getTok().is(AsmToken::Minus)) {
4843     isNegative = true;
4844     Parser.Lex();
4845   }
4846   const AsmToken &Tok = Parser.getTok();
4847   SMLoc Loc = Tok.getLoc();
4848   if (Tok.is(AsmToken::Real) && isVmovf) {
4849     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4850     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4851     // If we had a '-' in front, toggle the sign bit.
4852     IntVal ^= (uint64_t)isNegative << 31;
4853     Parser.Lex(); // Eat the token.
4854     Operands.push_back(ARMOperand::CreateImm(
4855           MCConstantExpr::Create(IntVal, getContext()),
4856           S, Parser.getTok().getLoc()));
4857     return MatchOperand_Success;
4858   }
4859   // Also handle plain integers. Instructions which allow floating point
4860   // immediates also allow a raw encoded 8-bit value.
4861   if (Tok.is(AsmToken::Integer) && isFconst) {
4862     int64_t Val = Tok.getIntVal();
4863     Parser.Lex(); // Eat the token.
4864     if (Val > 255 || Val < 0) {
4865       Error(Loc, "encoded floating point value out of range");
4866       return MatchOperand_ParseFail;
4867     }
4868     float RealVal = ARM_AM::getFPImmFloat(Val);
4869     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4870 
4871     Operands.push_back(ARMOperand::CreateImm(
4872         MCConstantExpr::Create(Val, getContext()), S,
4873         Parser.getTok().getLoc()));
4874     return MatchOperand_Success;
4875   }
4876 
4877   Error(Loc, "invalid floating point immediate");
4878   return MatchOperand_ParseFail;
4879 }
4880 
4881 /// Parse a arm instruction operand.  For now this parses the operand regardless
4882 /// of the mnemonic.
4883 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
4884   SMLoc S, E;
4885 
4886   // Check if the current operand has a custom associated parser, if so, try to
4887   // custom parse the operand, or fallback to the general approach.
4888   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4889   if (ResTy == MatchOperand_Success)
4890     return false;
4891   // If there wasn't a custom match, try the generic matcher below. Otherwise,
4892   // there was a match, but an error occurred, in which case, just return that
4893   // the operand parsing failed.
4894   if (ResTy == MatchOperand_ParseFail)
4895     return true;
4896 
4897   switch (getLexer().getKind()) {
4898   default:
4899     Error(Parser.getTok().getLoc(), "unexpected token in operand");
4900     return true;
4901   case AsmToken::Identifier: {
4902     // If we've seen a branch mnemonic, the next operand must be a label.  This
4903     // is true even if the label is a register name.  So "br r1" means branch to
4904     // label "r1".
4905     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4906     if (!ExpectLabel) {
4907       if (!tryParseRegisterWithWriteBack(Operands))
4908         return false;
4909       int Res = tryParseShiftRegister(Operands);
4910       if (Res == 0) // success
4911         return false;
4912       else if (Res == -1) // irrecoverable error
4913         return true;
4914       // If this is VMRS, check for the apsr_nzcv operand.
4915       if (Mnemonic == "vmrs" &&
4916           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4917         S = Parser.getTok().getLoc();
4918         Parser.Lex();
4919         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4920         return false;
4921       }
4922     }
4923 
4924     // Fall though for the Identifier case that is not a register or a
4925     // special name.
4926   }
4927   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4928   case AsmToken::Integer: // things like 1f and 2b as a branch targets
4929   case AsmToken::String:  // quoted label names.
4930   case AsmToken::Dot: {   // . as a branch target
4931     // This was not a register so parse other operands that start with an
4932     // identifier (like labels) as expressions and create them as immediates.
4933     const MCExpr *IdVal;
4934     S = Parser.getTok().getLoc();
4935     if (getParser().parseExpression(IdVal))
4936       return true;
4937     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4938     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4939     return false;
4940   }
4941   case AsmToken::LBrac:
4942     return parseMemory(Operands);
4943   case AsmToken::LCurly:
4944     return parseRegisterList(Operands);
4945   case AsmToken::Dollar:
4946   case AsmToken::Hash: {
4947     // #42 -> immediate.
4948     S = Parser.getTok().getLoc();
4949     Parser.Lex();
4950 
4951     if (Parser.getTok().isNot(AsmToken::Colon)) {
4952       bool isNegative = Parser.getTok().is(AsmToken::Minus);
4953       const MCExpr *ImmVal;
4954       if (getParser().parseExpression(ImmVal))
4955         return true;
4956       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4957       if (CE) {
4958         int32_t Val = CE->getValue();
4959         if (isNegative && Val == 0)
4960           ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4961       }
4962       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4963       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4964 
4965       // There can be a trailing '!' on operands that we want as a separate
4966       // '!' Token operand. Handle that here. For example, the compatibility
4967       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4968       if (Parser.getTok().is(AsmToken::Exclaim)) {
4969         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4970                                                    Parser.getTok().getLoc()));
4971         Parser.Lex(); // Eat exclaim token
4972       }
4973       return false;
4974     }
4975     // w/ a ':' after the '#', it's just like a plain ':'.
4976     // FALLTHROUGH
4977   }
4978   case AsmToken::Colon: {
4979     // ":lower16:" and ":upper16:" expression prefixes
4980     // FIXME: Check it's an expression prefix,
4981     // e.g. (FOO - :lower16:BAR) isn't legal.
4982     ARMMCExpr::VariantKind RefKind;
4983     if (parsePrefix(RefKind))
4984       return true;
4985 
4986     const MCExpr *SubExprVal;
4987     if (getParser().parseExpression(SubExprVal))
4988       return true;
4989 
4990     const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4991                                               getContext());
4992     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4993     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4994     return false;
4995   }
4996   case AsmToken::Equal: {
4997     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4998       return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4999 
5000     Parser.Lex(); // Eat '='
5001     const MCExpr *SubExprVal;
5002     if (getParser().parseExpression(SubExprVal))
5003       return true;
5004     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5005 
5006     const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5007     Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5008     return false;
5009   }
5010   }
5011 }
5012 
5013 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5014 //  :lower16: and :upper16:.
5015 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5016   RefKind = ARMMCExpr::VK_ARM_None;
5017 
5018   // consume an optional '#' (GNU compatibility)
5019   if (getLexer().is(AsmToken::Hash))
5020     Parser.Lex();
5021 
5022   // :lower16: and :upper16: modifiers
5023   assert(getLexer().is(AsmToken::Colon) && "expected a :");
5024   Parser.Lex(); // Eat ':'
5025 
5026   if (getLexer().isNot(AsmToken::Identifier)) {
5027     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5028     return true;
5029   }
5030 
5031   StringRef IDVal = Parser.getTok().getIdentifier();
5032   if (IDVal == "lower16") {
5033     RefKind = ARMMCExpr::VK_ARM_LO16;
5034   } else if (IDVal == "upper16") {
5035     RefKind = ARMMCExpr::VK_ARM_HI16;
5036   } else {
5037     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5038     return true;
5039   }
5040   Parser.Lex();
5041 
5042   if (getLexer().isNot(AsmToken::Colon)) {
5043     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5044     return true;
5045   }
5046   Parser.Lex(); // Eat the last ':'
5047   return false;
5048 }
5049 
5050 /// \brief Given a mnemonic, split out possible predication code and carry
5051 /// setting letters to form a canonical mnemonic and flags.
5052 //
5053 // FIXME: Would be nice to autogen this.
5054 // FIXME: This is a bit of a maze of special cases.
5055 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5056                                       unsigned &PredicationCode,
5057                                       bool &CarrySetting,
5058                                       unsigned &ProcessorIMod,
5059                                       StringRef &ITMask) {
5060   PredicationCode = ARMCC::AL;
5061   CarrySetting = false;
5062   ProcessorIMod = 0;
5063 
5064   // Ignore some mnemonics we know aren't predicated forms.
5065   //
5066   // FIXME: Would be nice to autogen this.
5067   if ((Mnemonic == "movs" && isThumb()) ||
5068       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
5069       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
5070       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
5071       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
5072       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
5073       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
5074       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
5075       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5076       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5077       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
5078       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5079       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
5080     return Mnemonic;
5081 
5082   // First, split out any predication code. Ignore mnemonics we know aren't
5083   // predicated but do have a carry-set and so weren't caught above.
5084   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5085       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5086       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5087       Mnemonic != "sbcs" && Mnemonic != "rscs") {
5088     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5089       .Case("eq", ARMCC::EQ)
5090       .Case("ne", ARMCC::NE)
5091       .Case("hs", ARMCC::HS)
5092       .Case("cs", ARMCC::HS)
5093       .Case("lo", ARMCC::LO)
5094       .Case("cc", ARMCC::LO)
5095       .Case("mi", ARMCC::MI)
5096       .Case("pl", ARMCC::PL)
5097       .Case("vs", ARMCC::VS)
5098       .Case("vc", ARMCC::VC)
5099       .Case("hi", ARMCC::HI)
5100       .Case("ls", ARMCC::LS)
5101       .Case("ge", ARMCC::GE)
5102       .Case("lt", ARMCC::LT)
5103       .Case("gt", ARMCC::GT)
5104       .Case("le", ARMCC::LE)
5105       .Case("al", ARMCC::AL)
5106       .Default(~0U);
5107     if (CC != ~0U) {
5108       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5109       PredicationCode = CC;
5110     }
5111   }
5112 
5113   // Next, determine if we have a carry setting bit. We explicitly ignore all
5114   // the instructions we know end in 's'.
5115   if (Mnemonic.endswith("s") &&
5116       !(Mnemonic == "cps" || Mnemonic == "mls" ||
5117         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5118         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5119         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5120         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5121         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5122         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5123         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5124         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5125         (Mnemonic == "movs" && isThumb()))) {
5126     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5127     CarrySetting = true;
5128   }
5129 
5130   // The "cps" instruction can have a interrupt mode operand which is glued into
5131   // the mnemonic. Check if this is the case, split it and parse the imod op
5132   if (Mnemonic.startswith("cps")) {
5133     // Split out any imod code.
5134     unsigned IMod =
5135       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5136       .Case("ie", ARM_PROC::IE)
5137       .Case("id", ARM_PROC::ID)
5138       .Default(~0U);
5139     if (IMod != ~0U) {
5140       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5141       ProcessorIMod = IMod;
5142     }
5143   }
5144 
5145   // The "it" instruction has the condition mask on the end of the mnemonic.
5146   if (Mnemonic.startswith("it")) {
5147     ITMask = Mnemonic.slice(2, Mnemonic.size());
5148     Mnemonic = Mnemonic.slice(0, 2);
5149   }
5150 
5151   return Mnemonic;
5152 }
5153 
5154 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5155 /// inclusion of carry set or predication code operands.
5156 //
5157 // FIXME: It would be nice to autogen this.
5158 void ARMAsmParser::
5159 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5160                      bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5161   if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5162       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5163       Mnemonic == "add" || Mnemonic == "adc" ||
5164       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5165       Mnemonic == "orr" || Mnemonic == "mvn" ||
5166       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5167       Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5168       Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5169       (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5170                       Mnemonic == "mla" || Mnemonic == "smlal" ||
5171                       Mnemonic == "umlal" || Mnemonic == "umull"))) {
5172     CanAcceptCarrySet = true;
5173   } else
5174     CanAcceptCarrySet = false;
5175 
5176   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5177       Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
5178       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5179       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5180       Mnemonic.startswith("vsel") ||
5181       Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5182       Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5183       Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5184       Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5185       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5186       (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5187     // These mnemonics are never predicable
5188     CanAcceptPredicationCode = false;
5189   } else if (!isThumb()) {
5190     // Some instructions are only predicable in Thumb mode
5191     CanAcceptPredicationCode
5192       = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5193         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5194         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5195         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5196         Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5197         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5198         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5199   } else if (isThumbOne()) {
5200     if (hasV6MOps())
5201       CanAcceptPredicationCode = Mnemonic != "movs";
5202     else
5203       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5204   } else
5205     CanAcceptPredicationCode = true;
5206 }
5207 
5208 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5209                                           OperandVector &Operands) {
5210   // FIXME: This is all horribly hacky. We really need a better way to deal
5211   // with optional operands like this in the matcher table.
5212 
5213   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5214   // another does not. Specifically, the MOVW instruction does not. So we
5215   // special case it here and remove the defaulted (non-setting) cc_out
5216   // operand if that's the instruction we're trying to match.
5217   //
5218   // We do this as post-processing of the explicit operands rather than just
5219   // conditionally adding the cc_out in the first place because we need
5220   // to check the type of the parsed immediate operand.
5221   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5222       !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() &&
5223       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5224       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5225     return true;
5226 
5227   // Register-register 'add' for thumb does not have a cc_out operand
5228   // when there are only two register operands.
5229   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5230       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5231       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5232       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5233     return true;
5234   // Register-register 'add' for thumb does not have a cc_out operand
5235   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5236   // have to check the immediate range here since Thumb2 has a variant
5237   // that can handle a different range and has a cc_out operand.
5238   if (((isThumb() && Mnemonic == "add") ||
5239        (isThumbTwo() && Mnemonic == "sub")) &&
5240       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5241       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5242       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5243       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5244       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5245        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5246     return true;
5247   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5248   // imm0_4095 variant. That's the least-preferred variant when
5249   // selecting via the generic "add" mnemonic, so to know that we
5250   // should remove the cc_out operand, we have to explicitly check that
5251   // it's not one of the other variants. Ugh.
5252   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5253       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5254       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5255       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5256     // Nest conditions rather than one big 'if' statement for readability.
5257     //
5258     // If both registers are low, we're in an IT block, and the immediate is
5259     // in range, we should use encoding T1 instead, which has a cc_out.
5260     if (inITBlock() &&
5261         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5262         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5263         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5264       return false;
5265     // Check against T3. If the second register is the PC, this is an
5266     // alternate form of ADR, which uses encoding T4, so check for that too.
5267     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5268         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5269       return false;
5270 
5271     // Otherwise, we use encoding T4, which does not have a cc_out
5272     // operand.
5273     return true;
5274   }
5275 
5276   // The thumb2 multiply instruction doesn't have a CCOut register, so
5277   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5278   // use the 16-bit encoding or not.
5279   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5280       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5281       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5282       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5283       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5284       // If the registers aren't low regs, the destination reg isn't the
5285       // same as one of the source regs, or the cc_out operand is zero
5286       // outside of an IT block, we have to use the 32-bit encoding, so
5287       // remove the cc_out operand.
5288       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5289        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5290        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5291        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5292                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5293                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5294                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
5295     return true;
5296 
5297   // Also check the 'mul' syntax variant that doesn't specify an explicit
5298   // destination register.
5299   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5300       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5301       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5302       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5303       // If the registers aren't low regs  or the cc_out operand is zero
5304       // outside of an IT block, we have to use the 32-bit encoding, so
5305       // remove the cc_out operand.
5306       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5307        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5308        !inITBlock()))
5309     return true;
5310 
5311 
5312 
5313   // Register-register 'add/sub' for thumb does not have a cc_out operand
5314   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5315   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5316   // right, this will result in better diagnostics (which operand is off)
5317   // anyway.
5318   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5319       (Operands.size() == 5 || Operands.size() == 6) &&
5320       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5321       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5322       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5323       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5324        (Operands.size() == 6 &&
5325         static_cast<ARMOperand &>(*Operands[5]).isImm())))
5326     return true;
5327 
5328   return false;
5329 }
5330 
5331 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5332                                               OperandVector &Operands) {
5333   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5334   unsigned RegIdx = 3;
5335   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5336       static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5337     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5338         static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5339       RegIdx = 4;
5340 
5341     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5342         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5343              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5344          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5345              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5346       return true;
5347   }
5348   return false;
5349 }
5350 
5351 static bool isDataTypeToken(StringRef Tok) {
5352   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5353     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5354     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5355     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5356     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5357     Tok == ".f" || Tok == ".d";
5358 }
5359 
5360 // FIXME: This bit should probably be handled via an explicit match class
5361 // in the .td files that matches the suffix instead of having it be
5362 // a literal string token the way it is now.
5363 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5364   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5365 }
5366 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5367                                  unsigned VariantID);
5368 
5369 static bool RequiresVFPRegListValidation(StringRef Inst,
5370                                          bool &AcceptSinglePrecisionOnly,
5371                                          bool &AcceptDoublePrecisionOnly) {
5372   if (Inst.size() < 7)
5373     return false;
5374 
5375   if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5376     StringRef AddressingMode = Inst.substr(4, 2);
5377     if (AddressingMode == "ia" || AddressingMode == "db" ||
5378         AddressingMode == "ea" || AddressingMode == "fd") {
5379       AcceptSinglePrecisionOnly = Inst[6] == 's';
5380       AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5381       return true;
5382     }
5383   }
5384 
5385   return false;
5386 }
5387 
5388 /// Parse an arm instruction mnemonic followed by its operands.
5389 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5390                                     SMLoc NameLoc, OperandVector &Operands) {
5391   // FIXME: Can this be done via tablegen in some fashion?
5392   bool RequireVFPRegisterListCheck;
5393   bool AcceptSinglePrecisionOnly;
5394   bool AcceptDoublePrecisionOnly;
5395   RequireVFPRegisterListCheck =
5396     RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5397                                  AcceptDoublePrecisionOnly);
5398 
5399   // Apply mnemonic aliases before doing anything else, as the destination
5400   // mnemonic may include suffices and we want to handle them normally.
5401   // The generic tblgen'erated code does this later, at the start of
5402   // MatchInstructionImpl(), but that's too late for aliases that include
5403   // any sort of suffix.
5404   uint64_t AvailableFeatures = getAvailableFeatures();
5405   unsigned AssemblerDialect = getParser().getAssemblerDialect();
5406   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5407 
5408   // First check for the ARM-specific .req directive.
5409   if (Parser.getTok().is(AsmToken::Identifier) &&
5410       Parser.getTok().getIdentifier() == ".req") {
5411     parseDirectiveReq(Name, NameLoc);
5412     // We always return 'error' for this, as we're done with this
5413     // statement and don't need to match the 'instruction."
5414     return true;
5415   }
5416 
5417   // Create the leading tokens for the mnemonic, split by '.' characters.
5418   size_t Start = 0, Next = Name.find('.');
5419   StringRef Mnemonic = Name.slice(Start, Next);
5420 
5421   // Split out the predication code and carry setting flag from the mnemonic.
5422   unsigned PredicationCode;
5423   unsigned ProcessorIMod;
5424   bool CarrySetting;
5425   StringRef ITMask;
5426   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5427                            ProcessorIMod, ITMask);
5428 
5429   // In Thumb1, only the branch (B) instruction can be predicated.
5430   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5431     Parser.eatToEndOfStatement();
5432     return Error(NameLoc, "conditional execution not supported in Thumb1");
5433   }
5434 
5435   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5436 
5437   // Handle the IT instruction ITMask. Convert it to a bitmask. This
5438   // is the mask as it will be for the IT encoding if the conditional
5439   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5440   // where the conditional bit0 is zero, the instruction post-processing
5441   // will adjust the mask accordingly.
5442   if (Mnemonic == "it") {
5443     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5444     if (ITMask.size() > 3) {
5445       Parser.eatToEndOfStatement();
5446       return Error(Loc, "too many conditions on IT instruction");
5447     }
5448     unsigned Mask = 8;
5449     for (unsigned i = ITMask.size(); i != 0; --i) {
5450       char pos = ITMask[i - 1];
5451       if (pos != 't' && pos != 'e') {
5452         Parser.eatToEndOfStatement();
5453         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5454       }
5455       Mask >>= 1;
5456       if (ITMask[i - 1] == 't')
5457         Mask |= 8;
5458     }
5459     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5460   }
5461 
5462   // FIXME: This is all a pretty gross hack. We should automatically handle
5463   // optional operands like this via tblgen.
5464 
5465   // Next, add the CCOut and ConditionCode operands, if needed.
5466   //
5467   // For mnemonics which can ever incorporate a carry setting bit or predication
5468   // code, our matching model involves us always generating CCOut and
5469   // ConditionCode operands to match the mnemonic "as written" and then we let
5470   // the matcher deal with finding the right instruction or generating an
5471   // appropriate error.
5472   bool CanAcceptCarrySet, CanAcceptPredicationCode;
5473   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5474 
5475   // If we had a carry-set on an instruction that can't do that, issue an
5476   // error.
5477   if (!CanAcceptCarrySet && CarrySetting) {
5478     Parser.eatToEndOfStatement();
5479     return Error(NameLoc, "instruction '" + Mnemonic +
5480                  "' can not set flags, but 's' suffix specified");
5481   }
5482   // If we had a predication code on an instruction that can't do that, issue an
5483   // error.
5484   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5485     Parser.eatToEndOfStatement();
5486     return Error(NameLoc, "instruction '" + Mnemonic +
5487                  "' is not predicable, but condition code specified");
5488   }
5489 
5490   // Add the carry setting operand, if necessary.
5491   if (CanAcceptCarrySet) {
5492     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5493     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5494                                                Loc));
5495   }
5496 
5497   // Add the predication code operand, if necessary.
5498   if (CanAcceptPredicationCode) {
5499     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5500                                       CarrySetting);
5501     Operands.push_back(ARMOperand::CreateCondCode(
5502                          ARMCC::CondCodes(PredicationCode), Loc));
5503   }
5504 
5505   // Add the processor imod operand, if necessary.
5506   if (ProcessorIMod) {
5507     Operands.push_back(ARMOperand::CreateImm(
5508           MCConstantExpr::Create(ProcessorIMod, getContext()),
5509                                  NameLoc, NameLoc));
5510   }
5511 
5512   // Add the remaining tokens in the mnemonic.
5513   while (Next != StringRef::npos) {
5514     Start = Next;
5515     Next = Name.find('.', Start + 1);
5516     StringRef ExtraToken = Name.slice(Start, Next);
5517 
5518     // Some NEON instructions have an optional datatype suffix that is
5519     // completely ignored. Check for that.
5520     if (isDataTypeToken(ExtraToken) &&
5521         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5522       continue;
5523 
5524     // For for ARM mode generate an error if the .n qualifier is used.
5525     if (ExtraToken == ".n" && !isThumb()) {
5526       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5527       Parser.eatToEndOfStatement();
5528       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5529                    "arm mode");
5530     }
5531 
5532     // The .n qualifier is always discarded as that is what the tables
5533     // and matcher expect.  In ARM mode the .w qualifier has no effect,
5534     // so discard it to avoid errors that can be caused by the matcher.
5535     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5536       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5537       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5538     }
5539   }
5540 
5541   // Read the remaining operands.
5542   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5543     // Read the first operand.
5544     if (parseOperand(Operands, Mnemonic)) {
5545       Parser.eatToEndOfStatement();
5546       return true;
5547     }
5548 
5549     while (getLexer().is(AsmToken::Comma)) {
5550       Parser.Lex();  // Eat the comma.
5551 
5552       // Parse and remember the operand.
5553       if (parseOperand(Operands, Mnemonic)) {
5554         Parser.eatToEndOfStatement();
5555         return true;
5556       }
5557     }
5558   }
5559 
5560   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5561     SMLoc Loc = getLexer().getLoc();
5562     Parser.eatToEndOfStatement();
5563     return Error(Loc, "unexpected token in argument list");
5564   }
5565 
5566   Parser.Lex(); // Consume the EndOfStatement
5567 
5568   if (RequireVFPRegisterListCheck) {
5569     ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5570     if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5571       return Error(Op.getStartLoc(),
5572                    "VFP/Neon single precision register expected");
5573     if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5574       return Error(Op.getStartLoc(),
5575                    "VFP/Neon double precision register expected");
5576   }
5577 
5578   // Some instructions, mostly Thumb, have forms for the same mnemonic that
5579   // do and don't have a cc_out optional-def operand. With some spot-checks
5580   // of the operand list, we can figure out which variant we're trying to
5581   // parse and adjust accordingly before actually matching. We shouldn't ever
5582   // try to remove a cc_out operand that was explicitly set on the the
5583   // mnemonic, of course (CarrySetting == true). Reason number #317 the
5584   // table driven matcher doesn't fit well with the ARM instruction set.
5585   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5586     Operands.erase(Operands.begin() + 1);
5587 
5588   // Some instructions have the same mnemonic, but don't always
5589   // have a predicate. Distinguish them here and delete the
5590   // predicate if needed.
5591   if (shouldOmitPredicateOperand(Mnemonic, Operands))
5592     Operands.erase(Operands.begin() + 1);
5593 
5594   // ARM mode 'blx' need special handling, as the register operand version
5595   // is predicable, but the label operand version is not. So, we can't rely
5596   // on the Mnemonic based checking to correctly figure out when to put
5597   // a k_CondCode operand in the list. If we're trying to match the label
5598   // version, remove the k_CondCode operand here.
5599   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5600       static_cast<ARMOperand &>(*Operands[2]).isImm())
5601     Operands.erase(Operands.begin() + 1);
5602 
5603   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5604   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5605   // a single GPRPair reg operand is used in the .td file to replace the two
5606   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5607   // expressed as a GPRPair, so we have to manually merge them.
5608   // FIXME: We would really like to be able to tablegen'erate this.
5609   if (!isThumb() && Operands.size() > 4 &&
5610       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5611        Mnemonic == "stlexd")) {
5612     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5613     unsigned Idx = isLoad ? 2 : 3;
5614     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5615     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5616 
5617     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5618     // Adjust only if Op1 and Op2 are GPRs.
5619     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5620         MRC.contains(Op2.getReg())) {
5621       unsigned Reg1 = Op1.getReg();
5622       unsigned Reg2 = Op2.getReg();
5623       unsigned Rt = MRI->getEncodingValue(Reg1);
5624       unsigned Rt2 = MRI->getEncodingValue(Reg2);
5625 
5626       // Rt2 must be Rt + 1 and Rt must be even.
5627       if (Rt + 1 != Rt2 || (Rt & 1)) {
5628         Error(Op2.getStartLoc(), isLoad
5629                                      ? "destination operands must be sequential"
5630                                      : "source operands must be sequential");
5631         return true;
5632       }
5633       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5634           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5635       Operands[Idx] =
5636           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5637       Operands.erase(Operands.begin() + Idx + 1);
5638     }
5639   }
5640 
5641   // GNU Assembler extension (compatibility)
5642   if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5643     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5644     ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5645     if (Op3.isMem()) {
5646       assert(Op2.isReg() && "expected register argument");
5647 
5648       unsigned SuperReg = MRI->getMatchingSuperReg(
5649           Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5650 
5651       assert(SuperReg && "expected register pair");
5652 
5653       unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5654 
5655       Operands.insert(
5656           Operands.begin() + 3,
5657           ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5658     }
5659   }
5660 
5661   // FIXME: As said above, this is all a pretty gross hack.  This instruction
5662   // does not fit with other "subs" and tblgen.
5663   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5664   // so the Mnemonic is the original name "subs" and delete the predicate
5665   // operand so it will match the table entry.
5666   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5667       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5668       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5669       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5670       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5671       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5672     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5673     Operands.erase(Operands.begin() + 1);
5674   }
5675   return false;
5676 }
5677 
5678 // Validate context-sensitive operand constraints.
5679 
5680 // return 'true' if register list contains non-low GPR registers,
5681 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5682 // 'containsReg' to true.
5683 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5684                                  unsigned HiReg, bool &containsReg) {
5685   containsReg = false;
5686   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5687     unsigned OpReg = Inst.getOperand(i).getReg();
5688     if (OpReg == Reg)
5689       containsReg = true;
5690     // Anything other than a low register isn't legal here.
5691     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5692       return true;
5693   }
5694   return false;
5695 }
5696 
5697 // Check if the specified regisgter is in the register list of the inst,
5698 // starting at the indicated operand number.
5699 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5700   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5701     unsigned OpReg = Inst.getOperand(i).getReg();
5702     if (OpReg == Reg)
5703       return true;
5704   }
5705   return false;
5706 }
5707 
5708 // Return true if instruction has the interesting property of being
5709 // allowed in IT blocks, but not being predicable.
5710 static bool instIsBreakpoint(const MCInst &Inst) {
5711     return Inst.getOpcode() == ARM::tBKPT ||
5712            Inst.getOpcode() == ARM::BKPT ||
5713            Inst.getOpcode() == ARM::tHLT ||
5714            Inst.getOpcode() == ARM::HLT;
5715 
5716 }
5717 
5718 // FIXME: We would really like to be able to tablegen'erate this.
5719 bool ARMAsmParser::validateInstruction(MCInst &Inst,
5720                                        const OperandVector &Operands) {
5721   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5722   SMLoc Loc = Operands[0]->getStartLoc();
5723 
5724   // Check the IT block state first.
5725   // NOTE: BKPT and HLT instructions have the interesting property of being
5726   // allowed in IT blocks, but not being predicable. They just always execute.
5727   if (inITBlock() && !instIsBreakpoint(Inst)) {
5728     unsigned Bit = 1;
5729     if (ITState.FirstCond)
5730       ITState.FirstCond = false;
5731     else
5732       Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5733     // The instruction must be predicable.
5734     if (!MCID.isPredicable())
5735       return Error(Loc, "instructions in IT block must be predicable");
5736     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5737     unsigned ITCond = Bit ? ITState.Cond :
5738       ARMCC::getOppositeCondition(ITState.Cond);
5739     if (Cond != ITCond) {
5740       // Find the condition code Operand to get its SMLoc information.
5741       SMLoc CondLoc;
5742       for (unsigned I = 1; I < Operands.size(); ++I)
5743         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
5744           CondLoc = Operands[I]->getStartLoc();
5745       return Error(CondLoc, "incorrect condition in IT block; got '" +
5746                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5747                    "', but expected '" +
5748                    ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5749     }
5750   // Check for non-'al' condition codes outside of the IT block.
5751   } else if (isThumbTwo() && MCID.isPredicable() &&
5752              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5753              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5754              Inst.getOpcode() != ARM::t2Bcc)
5755     return Error(Loc, "predicated instructions must be in IT block");
5756 
5757   const unsigned Opcode = Inst.getOpcode();
5758   switch (Opcode) {
5759   case ARM::LDRD:
5760   case ARM::LDRD_PRE:
5761   case ARM::LDRD_POST: {
5762     const unsigned RtReg = Inst.getOperand(0).getReg();
5763 
5764     // Rt can't be R14.
5765     if (RtReg == ARM::LR)
5766       return Error(Operands[3]->getStartLoc(),
5767                    "Rt can't be R14");
5768 
5769     const unsigned Rt = MRI->getEncodingValue(RtReg);
5770     // Rt must be even-numbered.
5771     if ((Rt & 1) == 1)
5772       return Error(Operands[3]->getStartLoc(),
5773                    "Rt must be even-numbered");
5774 
5775     // Rt2 must be Rt + 1.
5776     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5777     if (Rt2 != Rt + 1)
5778       return Error(Operands[3]->getStartLoc(),
5779                    "destination operands must be sequential");
5780 
5781     if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5782       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5783       // For addressing modes with writeback, the base register needs to be
5784       // different from the destination registers.
5785       if (Rn == Rt || Rn == Rt2)
5786         return Error(Operands[3]->getStartLoc(),
5787                      "base register needs to be different from destination "
5788                      "registers");
5789     }
5790 
5791     return false;
5792   }
5793   case ARM::t2LDRDi8:
5794   case ARM::t2LDRD_PRE:
5795   case ARM::t2LDRD_POST: {
5796     // Rt2 must be different from Rt.
5797     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5798     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5799     if (Rt2 == Rt)
5800       return Error(Operands[3]->getStartLoc(),
5801                    "destination operands can't be identical");
5802     return false;
5803   }
5804   case ARM::STRD: {
5805     // Rt2 must be Rt + 1.
5806     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5807     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5808     if (Rt2 != Rt + 1)
5809       return Error(Operands[3]->getStartLoc(),
5810                    "source operands must be sequential");
5811     return false;
5812   }
5813   case ARM::STRD_PRE:
5814   case ARM::STRD_POST: {
5815     // Rt2 must be Rt + 1.
5816     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5817     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5818     if (Rt2 != Rt + 1)
5819       return Error(Operands[3]->getStartLoc(),
5820                    "source operands must be sequential");
5821     return false;
5822   }
5823   case ARM::STR_PRE_IMM:
5824   case ARM::STR_PRE_REG:
5825   case ARM::STR_POST_IMM:
5826   case ARM::STR_POST_REG:
5827   case ARM::STRH_PRE:
5828   case ARM::STRH_POST:
5829   case ARM::STRB_PRE_IMM:
5830   case ARM::STRB_PRE_REG:
5831   case ARM::STRB_POST_IMM:
5832   case ARM::STRB_POST_REG: {
5833     // Rt must be different from Rn.
5834     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5835     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5836 
5837     if (Rt == Rn)
5838       return Error(Operands[3]->getStartLoc(),
5839                    "source register and base register can't be identical");
5840     return false;
5841   }
5842   case ARM::LDR_PRE_IMM:
5843   case ARM::LDR_PRE_REG:
5844   case ARM::LDR_POST_IMM:
5845   case ARM::LDR_POST_REG:
5846   case ARM::LDRH_PRE:
5847   case ARM::LDRH_POST:
5848   case ARM::LDRSH_PRE:
5849   case ARM::LDRSH_POST:
5850   case ARM::LDRB_PRE_IMM:
5851   case ARM::LDRB_PRE_REG:
5852   case ARM::LDRB_POST_IMM:
5853   case ARM::LDRB_POST_REG:
5854   case ARM::LDRSB_PRE:
5855   case ARM::LDRSB_POST: {
5856     // Rt must be different from Rn.
5857     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5858     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5859 
5860     if (Rt == Rn)
5861       return Error(Operands[3]->getStartLoc(),
5862                    "destination register and base register can't be identical");
5863     return false;
5864   }
5865   case ARM::SBFX:
5866   case ARM::UBFX: {
5867     // Width must be in range [1, 32-lsb].
5868     unsigned LSB = Inst.getOperand(2).getImm();
5869     unsigned Widthm1 = Inst.getOperand(3).getImm();
5870     if (Widthm1 >= 32 - LSB)
5871       return Error(Operands[5]->getStartLoc(),
5872                    "bitfield width must be in range [1,32-lsb]");
5873     return false;
5874   }
5875   // Notionally handles ARM::tLDMIA_UPD too.
5876   case ARM::tLDMIA: {
5877     // If we're parsing Thumb2, the .w variant is available and handles
5878     // most cases that are normally illegal for a Thumb1 LDM instruction.
5879     // We'll make the transformation in processInstruction() if necessary.
5880     //
5881     // Thumb LDM instructions are writeback iff the base register is not
5882     // in the register list.
5883     unsigned Rn = Inst.getOperand(0).getReg();
5884     bool HasWritebackToken =
5885         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5886          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
5887     bool ListContainsBase;
5888     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5889       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5890                    "registers must be in range r0-r7");
5891     // If we should have writeback, then there should be a '!' token.
5892     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5893       return Error(Operands[2]->getStartLoc(),
5894                    "writeback operator '!' expected");
5895     // If we should not have writeback, there must not be a '!'. This is
5896     // true even for the 32-bit wide encodings.
5897     if (ListContainsBase && HasWritebackToken)
5898       return Error(Operands[3]->getStartLoc(),
5899                    "writeback operator '!' not allowed when base register "
5900                    "in register list");
5901 
5902     break;
5903   }
5904   case ARM::LDMIA_UPD:
5905   case ARM::LDMDB_UPD:
5906   case ARM::LDMIB_UPD:
5907   case ARM::LDMDA_UPD:
5908     // ARM variants loading and updating the same register are only officially
5909     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5910     if (!hasV7Ops())
5911       break;
5912     // Fallthrough
5913   case ARM::t2LDMIA_UPD:
5914   case ARM::t2LDMDB_UPD:
5915   case ARM::t2STMIA_UPD:
5916   case ARM::t2STMDB_UPD: {
5917     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5918       return Error(Operands.back()->getStartLoc(),
5919                    "writeback register not allowed in register list");
5920     break;
5921   }
5922   case ARM::sysLDMIA_UPD:
5923   case ARM::sysLDMDA_UPD:
5924   case ARM::sysLDMDB_UPD:
5925   case ARM::sysLDMIB_UPD:
5926     if (!listContainsReg(Inst, 3, ARM::PC))
5927       return Error(Operands[4]->getStartLoc(),
5928                    "writeback register only allowed on system LDM "
5929                    "if PC in register-list");
5930     break;
5931   case ARM::sysSTMIA_UPD:
5932   case ARM::sysSTMDA_UPD:
5933   case ARM::sysSTMDB_UPD:
5934   case ARM::sysSTMIB_UPD:
5935     return Error(Operands[2]->getStartLoc(),
5936                  "system STM cannot have writeback register");
5937   case ARM::tMUL: {
5938     // The second source operand must be the same register as the destination
5939     // operand.
5940     //
5941     // In this case, we must directly check the parsed operands because the
5942     // cvtThumbMultiply() function is written in such a way that it guarantees
5943     // this first statement is always true for the new Inst.  Essentially, the
5944     // destination is unconditionally copied into the second source operand
5945     // without checking to see if it matches what we actually parsed.
5946     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
5947                                  ((ARMOperand &)*Operands[5]).getReg()) &&
5948         (((ARMOperand &)*Operands[3]).getReg() !=
5949          ((ARMOperand &)*Operands[4]).getReg())) {
5950       return Error(Operands[3]->getStartLoc(),
5951                    "destination register must match source register");
5952     }
5953     break;
5954   }
5955   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5956   // so only issue a diagnostic for thumb1. The instructions will be
5957   // switched to the t2 encodings in processInstruction() if necessary.
5958   case ARM::tPOP: {
5959     bool ListContainsBase;
5960     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5961         !isThumbTwo())
5962       return Error(Operands[2]->getStartLoc(),
5963                    "registers must be in range r0-r7 or pc");
5964     break;
5965   }
5966   case ARM::tPUSH: {
5967     bool ListContainsBase;
5968     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5969         !isThumbTwo())
5970       return Error(Operands[2]->getStartLoc(),
5971                    "registers must be in range r0-r7 or lr");
5972     break;
5973   }
5974   case ARM::tSTMIA_UPD: {
5975     bool ListContainsBase, InvalidLowList;
5976     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5977                                           0, ListContainsBase);
5978     if (InvalidLowList && !isThumbTwo())
5979       return Error(Operands[4]->getStartLoc(),
5980                    "registers must be in range r0-r7");
5981 
5982     // This would be converted to a 32-bit stm, but that's not valid if the
5983     // writeback register is in the list.
5984     if (InvalidLowList && ListContainsBase)
5985       return Error(Operands[4]->getStartLoc(),
5986                    "writeback operator '!' not allowed when base register "
5987                    "in register list");
5988     break;
5989   }
5990   case ARM::tADDrSP: {
5991     // If the non-SP source operand and the destination operand are not the
5992     // same, we need thumb2 (for the wide encoding), or we have an error.
5993     if (!isThumbTwo() &&
5994         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5995       return Error(Operands[4]->getStartLoc(),
5996                    "source register must be the same as destination");
5997     }
5998     break;
5999   }
6000   // Final range checking for Thumb unconditional branch instructions.
6001   case ARM::tB:
6002     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6003       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6004     break;
6005   case ARM::t2B: {
6006     int op = (Operands[2]->isImm()) ? 2 : 3;
6007     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6008       return Error(Operands[op]->getStartLoc(), "branch target out of range");
6009     break;
6010   }
6011   // Final range checking for Thumb conditional branch instructions.
6012   case ARM::tBcc:
6013     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6014       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6015     break;
6016   case ARM::t2Bcc: {
6017     int Op = (Operands[2]->isImm()) ? 2 : 3;
6018     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6019       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6020     break;
6021   }
6022   case ARM::MOVi16:
6023   case ARM::t2MOVi16:
6024   case ARM::t2MOVTi16:
6025     {
6026     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6027     // especially when we turn it into a movw and the expression <symbol> does
6028     // not have a :lower16: or :upper16 as part of the expression.  We don't
6029     // want the behavior of silently truncating, which can be unexpected and
6030     // lead to bugs that are difficult to find since this is an easy mistake
6031     // to make.
6032     int i = (Operands[3]->isImm()) ? 3 : 4;
6033     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6034     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6035     if (CE) break;
6036     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6037     if (!E) break;
6038     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6039     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6040                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6041       return Error(
6042           Op.getStartLoc(),
6043           "immediate expression for mov requires :lower16: or :upper16");
6044     break;
6045   }
6046   }
6047 
6048   return false;
6049 }
6050 
6051 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6052   switch(Opc) {
6053   default: llvm_unreachable("unexpected opcode!");
6054   // VST1LN
6055   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6056   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6057   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6058   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6059   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6060   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6061   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
6062   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6063   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6064 
6065   // VST2LN
6066   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6067   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6068   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6069   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6070   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6071 
6072   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6073   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6074   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6075   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6076   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6077 
6078   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
6079   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6080   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6081   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6082   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6083 
6084   // VST3LN
6085   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6086   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6087   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6088   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6089   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6090   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6091   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6092   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6093   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6094   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6095   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
6096   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6097   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6098   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6099   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6100 
6101   // VST3
6102   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6103   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6104   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6105   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6106   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6107   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6108   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6109   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6110   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6111   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6112   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6113   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6114   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
6115   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6116   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6117   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
6118   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6119   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6120 
6121   // VST4LN
6122   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6123   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6124   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6125   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6126   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6127   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6128   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6129   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6130   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6131   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6132   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
6133   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6134   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6135   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6136   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6137 
6138   // VST4
6139   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6140   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6141   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6142   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6143   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6144   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6145   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6146   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6147   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6148   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6149   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6150   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6151   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
6152   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6153   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6154   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
6155   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6156   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6157   }
6158 }
6159 
6160 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6161   switch(Opc) {
6162   default: llvm_unreachable("unexpected opcode!");
6163   // VLD1LN
6164   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6165   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6166   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6167   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6168   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6169   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6170   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
6171   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6172   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6173 
6174   // VLD2LN
6175   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6176   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6177   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6178   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6179   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6180   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6181   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6182   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6183   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6184   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6185   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
6186   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6187   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6188   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6189   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6190 
6191   // VLD3DUP
6192   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6193   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6194   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6195   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6196   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6197   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6198   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6199   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6200   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6201   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6202   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6203   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6204   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
6205   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6206   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6207   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6208   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6209   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6210 
6211   // VLD3LN
6212   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6213   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6214   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6215   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6216   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6217   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6218   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6219   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6220   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6221   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6222   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
6223   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6224   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6225   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6226   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6227 
6228   // VLD3
6229   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6230   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6231   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6232   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6233   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6234   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6235   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6236   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6237   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6238   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6239   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6240   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6241   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
6242   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6243   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6244   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
6245   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6246   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6247 
6248   // VLD4LN
6249   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6250   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6251   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6252   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6253   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6254   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6255   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6256   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6257   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6258   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6259   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
6260   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6261   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6262   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6263   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6264 
6265   // VLD4DUP
6266   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6267   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6268   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6269   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6270   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6271   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6272   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6273   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6274   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6275   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6276   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6277   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6278   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
6279   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6280   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6281   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6282   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6283   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6284 
6285   // VLD4
6286   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6287   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6288   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6289   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6290   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6291   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6292   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6293   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6294   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6295   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6296   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6297   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6298   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
6299   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6300   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6301   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
6302   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6303   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6304   }
6305 }
6306 
6307 bool ARMAsmParser::processInstruction(MCInst &Inst,
6308                                       const OperandVector &Operands) {
6309   switch (Inst.getOpcode()) {
6310   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6311   case ARM::LDRT_POST:
6312   case ARM::LDRBT_POST: {
6313     const unsigned Opcode =
6314       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6315                                            : ARM::LDRBT_POST_IMM;
6316     MCInst TmpInst;
6317     TmpInst.setOpcode(Opcode);
6318     TmpInst.addOperand(Inst.getOperand(0));
6319     TmpInst.addOperand(Inst.getOperand(1));
6320     TmpInst.addOperand(Inst.getOperand(1));
6321     TmpInst.addOperand(MCOperand::CreateReg(0));
6322     TmpInst.addOperand(MCOperand::CreateImm(0));
6323     TmpInst.addOperand(Inst.getOperand(2));
6324     TmpInst.addOperand(Inst.getOperand(3));
6325     Inst = TmpInst;
6326     return true;
6327   }
6328   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6329   case ARM::STRT_POST:
6330   case ARM::STRBT_POST: {
6331     const unsigned Opcode =
6332       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6333                                            : ARM::STRBT_POST_IMM;
6334     MCInst TmpInst;
6335     TmpInst.setOpcode(Opcode);
6336     TmpInst.addOperand(Inst.getOperand(1));
6337     TmpInst.addOperand(Inst.getOperand(0));
6338     TmpInst.addOperand(Inst.getOperand(1));
6339     TmpInst.addOperand(MCOperand::CreateReg(0));
6340     TmpInst.addOperand(MCOperand::CreateImm(0));
6341     TmpInst.addOperand(Inst.getOperand(2));
6342     TmpInst.addOperand(Inst.getOperand(3));
6343     Inst = TmpInst;
6344     return true;
6345   }
6346   // Alias for alternate form of 'ADR Rd, #imm' instruction.
6347   case ARM::ADDri: {
6348     if (Inst.getOperand(1).getReg() != ARM::PC ||
6349         Inst.getOperand(5).getReg() != 0)
6350       return false;
6351     MCInst TmpInst;
6352     TmpInst.setOpcode(ARM::ADR);
6353     TmpInst.addOperand(Inst.getOperand(0));
6354     TmpInst.addOperand(Inst.getOperand(2));
6355     TmpInst.addOperand(Inst.getOperand(3));
6356     TmpInst.addOperand(Inst.getOperand(4));
6357     Inst = TmpInst;
6358     return true;
6359   }
6360   // Aliases for alternate PC+imm syntax of LDR instructions.
6361   case ARM::t2LDRpcrel:
6362     // Select the narrow version if the immediate will fit.
6363     if (Inst.getOperand(1).getImm() > 0 &&
6364         Inst.getOperand(1).getImm() <= 0xff &&
6365         !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6366           static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6367       Inst.setOpcode(ARM::tLDRpci);
6368     else
6369       Inst.setOpcode(ARM::t2LDRpci);
6370     return true;
6371   case ARM::t2LDRBpcrel:
6372     Inst.setOpcode(ARM::t2LDRBpci);
6373     return true;
6374   case ARM::t2LDRHpcrel:
6375     Inst.setOpcode(ARM::t2LDRHpci);
6376     return true;
6377   case ARM::t2LDRSBpcrel:
6378     Inst.setOpcode(ARM::t2LDRSBpci);
6379     return true;
6380   case ARM::t2LDRSHpcrel:
6381     Inst.setOpcode(ARM::t2LDRSHpci);
6382     return true;
6383   // Handle NEON VST complex aliases.
6384   case ARM::VST1LNdWB_register_Asm_8:
6385   case ARM::VST1LNdWB_register_Asm_16:
6386   case ARM::VST1LNdWB_register_Asm_32: {
6387     MCInst TmpInst;
6388     // Shuffle the operands around so the lane index operand is in the
6389     // right place.
6390     unsigned Spacing;
6391     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6392     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6393     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6394     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6395     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6396     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6397     TmpInst.addOperand(Inst.getOperand(1)); // lane
6398     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6399     TmpInst.addOperand(Inst.getOperand(6));
6400     Inst = TmpInst;
6401     return true;
6402   }
6403 
6404   case ARM::VST2LNdWB_register_Asm_8:
6405   case ARM::VST2LNdWB_register_Asm_16:
6406   case ARM::VST2LNdWB_register_Asm_32:
6407   case ARM::VST2LNqWB_register_Asm_16:
6408   case ARM::VST2LNqWB_register_Asm_32: {
6409     MCInst TmpInst;
6410     // Shuffle the operands around so the lane index operand is in the
6411     // right place.
6412     unsigned Spacing;
6413     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6414     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6415     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6416     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6417     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6418     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6419     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6420                                             Spacing));
6421     TmpInst.addOperand(Inst.getOperand(1)); // lane
6422     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6423     TmpInst.addOperand(Inst.getOperand(6));
6424     Inst = TmpInst;
6425     return true;
6426   }
6427 
6428   case ARM::VST3LNdWB_register_Asm_8:
6429   case ARM::VST3LNdWB_register_Asm_16:
6430   case ARM::VST3LNdWB_register_Asm_32:
6431   case ARM::VST3LNqWB_register_Asm_16:
6432   case ARM::VST3LNqWB_register_Asm_32: {
6433     MCInst TmpInst;
6434     // Shuffle the operands around so the lane index operand is in the
6435     // right place.
6436     unsigned Spacing;
6437     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6438     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6439     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6440     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6441     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6442     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6443     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6444                                             Spacing));
6445     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6446                                             Spacing * 2));
6447     TmpInst.addOperand(Inst.getOperand(1)); // lane
6448     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6449     TmpInst.addOperand(Inst.getOperand(6));
6450     Inst = TmpInst;
6451     return true;
6452   }
6453 
6454   case ARM::VST4LNdWB_register_Asm_8:
6455   case ARM::VST4LNdWB_register_Asm_16:
6456   case ARM::VST4LNdWB_register_Asm_32:
6457   case ARM::VST4LNqWB_register_Asm_16:
6458   case ARM::VST4LNqWB_register_Asm_32: {
6459     MCInst TmpInst;
6460     // Shuffle the operands around so the lane index operand is in the
6461     // right place.
6462     unsigned Spacing;
6463     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6464     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6465     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6466     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6467     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6468     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6469     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6470                                             Spacing));
6471     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6472                                             Spacing * 2));
6473     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6474                                             Spacing * 3));
6475     TmpInst.addOperand(Inst.getOperand(1)); // lane
6476     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6477     TmpInst.addOperand(Inst.getOperand(6));
6478     Inst = TmpInst;
6479     return true;
6480   }
6481 
6482   case ARM::VST1LNdWB_fixed_Asm_8:
6483   case ARM::VST1LNdWB_fixed_Asm_16:
6484   case ARM::VST1LNdWB_fixed_Asm_32: {
6485     MCInst TmpInst;
6486     // Shuffle the operands around so the lane index operand is in the
6487     // right place.
6488     unsigned Spacing;
6489     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6490     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6491     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6492     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6493     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6494     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6495     TmpInst.addOperand(Inst.getOperand(1)); // lane
6496     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6497     TmpInst.addOperand(Inst.getOperand(5));
6498     Inst = TmpInst;
6499     return true;
6500   }
6501 
6502   case ARM::VST2LNdWB_fixed_Asm_8:
6503   case ARM::VST2LNdWB_fixed_Asm_16:
6504   case ARM::VST2LNdWB_fixed_Asm_32:
6505   case ARM::VST2LNqWB_fixed_Asm_16:
6506   case ARM::VST2LNqWB_fixed_Asm_32: {
6507     MCInst TmpInst;
6508     // Shuffle the operands around so the lane index operand is in the
6509     // right place.
6510     unsigned Spacing;
6511     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6512     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6513     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6514     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6515     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6516     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6517     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6518                                             Spacing));
6519     TmpInst.addOperand(Inst.getOperand(1)); // lane
6520     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6521     TmpInst.addOperand(Inst.getOperand(5));
6522     Inst = TmpInst;
6523     return true;
6524   }
6525 
6526   case ARM::VST3LNdWB_fixed_Asm_8:
6527   case ARM::VST3LNdWB_fixed_Asm_16:
6528   case ARM::VST3LNdWB_fixed_Asm_32:
6529   case ARM::VST3LNqWB_fixed_Asm_16:
6530   case ARM::VST3LNqWB_fixed_Asm_32: {
6531     MCInst TmpInst;
6532     // Shuffle the operands around so the lane index operand is in the
6533     // right place.
6534     unsigned Spacing;
6535     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6536     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6537     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6538     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6539     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6540     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6541     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6542                                             Spacing));
6543     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6544                                             Spacing * 2));
6545     TmpInst.addOperand(Inst.getOperand(1)); // lane
6546     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6547     TmpInst.addOperand(Inst.getOperand(5));
6548     Inst = TmpInst;
6549     return true;
6550   }
6551 
6552   case ARM::VST4LNdWB_fixed_Asm_8:
6553   case ARM::VST4LNdWB_fixed_Asm_16:
6554   case ARM::VST4LNdWB_fixed_Asm_32:
6555   case ARM::VST4LNqWB_fixed_Asm_16:
6556   case ARM::VST4LNqWB_fixed_Asm_32: {
6557     MCInst TmpInst;
6558     // Shuffle the operands around so the lane index operand is in the
6559     // right place.
6560     unsigned Spacing;
6561     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6562     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6563     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6564     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6565     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6566     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6567     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6568                                             Spacing));
6569     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6570                                             Spacing * 2));
6571     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572                                             Spacing * 3));
6573     TmpInst.addOperand(Inst.getOperand(1)); // lane
6574     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6575     TmpInst.addOperand(Inst.getOperand(5));
6576     Inst = TmpInst;
6577     return true;
6578   }
6579 
6580   case ARM::VST1LNdAsm_8:
6581   case ARM::VST1LNdAsm_16:
6582   case ARM::VST1LNdAsm_32: {
6583     MCInst TmpInst;
6584     // Shuffle the operands around so the lane index operand is in the
6585     // right place.
6586     unsigned Spacing;
6587     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6588     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6589     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6590     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6591     TmpInst.addOperand(Inst.getOperand(1)); // lane
6592     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6593     TmpInst.addOperand(Inst.getOperand(5));
6594     Inst = TmpInst;
6595     return true;
6596   }
6597 
6598   case ARM::VST2LNdAsm_8:
6599   case ARM::VST2LNdAsm_16:
6600   case ARM::VST2LNdAsm_32:
6601   case ARM::VST2LNqAsm_16:
6602   case ARM::VST2LNqAsm_32: {
6603     MCInst TmpInst;
6604     // Shuffle the operands around so the lane index operand is in the
6605     // right place.
6606     unsigned Spacing;
6607     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6608     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6609     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6610     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6611     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6612                                             Spacing));
6613     TmpInst.addOperand(Inst.getOperand(1)); // lane
6614     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6615     TmpInst.addOperand(Inst.getOperand(5));
6616     Inst = TmpInst;
6617     return true;
6618   }
6619 
6620   case ARM::VST3LNdAsm_8:
6621   case ARM::VST3LNdAsm_16:
6622   case ARM::VST3LNdAsm_32:
6623   case ARM::VST3LNqAsm_16:
6624   case ARM::VST3LNqAsm_32: {
6625     MCInst TmpInst;
6626     // Shuffle the operands around so the lane index operand is in the
6627     // right place.
6628     unsigned Spacing;
6629     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6630     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6631     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6632     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6633     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6634                                             Spacing));
6635     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6636                                             Spacing * 2));
6637     TmpInst.addOperand(Inst.getOperand(1)); // lane
6638     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6639     TmpInst.addOperand(Inst.getOperand(5));
6640     Inst = TmpInst;
6641     return true;
6642   }
6643 
6644   case ARM::VST4LNdAsm_8:
6645   case ARM::VST4LNdAsm_16:
6646   case ARM::VST4LNdAsm_32:
6647   case ARM::VST4LNqAsm_16:
6648   case ARM::VST4LNqAsm_32: {
6649     MCInst TmpInst;
6650     // Shuffle the operands around so the lane index operand is in the
6651     // right place.
6652     unsigned Spacing;
6653     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6654     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6655     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6656     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6657     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6658                                             Spacing));
6659     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6660                                             Spacing * 2));
6661     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6662                                             Spacing * 3));
6663     TmpInst.addOperand(Inst.getOperand(1)); // lane
6664     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6665     TmpInst.addOperand(Inst.getOperand(5));
6666     Inst = TmpInst;
6667     return true;
6668   }
6669 
6670   // Handle NEON VLD complex aliases.
6671   case ARM::VLD1LNdWB_register_Asm_8:
6672   case ARM::VLD1LNdWB_register_Asm_16:
6673   case ARM::VLD1LNdWB_register_Asm_32: {
6674     MCInst TmpInst;
6675     // Shuffle the operands around so the lane index operand is in the
6676     // right place.
6677     unsigned Spacing;
6678     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6679     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6680     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6681     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6682     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6683     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6684     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6685     TmpInst.addOperand(Inst.getOperand(1)); // lane
6686     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6687     TmpInst.addOperand(Inst.getOperand(6));
6688     Inst = TmpInst;
6689     return true;
6690   }
6691 
6692   case ARM::VLD2LNdWB_register_Asm_8:
6693   case ARM::VLD2LNdWB_register_Asm_16:
6694   case ARM::VLD2LNdWB_register_Asm_32:
6695   case ARM::VLD2LNqWB_register_Asm_16:
6696   case ARM::VLD2LNqWB_register_Asm_32: {
6697     MCInst TmpInst;
6698     // Shuffle the operands around so the lane index operand is in the
6699     // right place.
6700     unsigned Spacing;
6701     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6702     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6703     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6704                                             Spacing));
6705     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6706     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6707     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6708     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6709     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6710     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6711                                             Spacing));
6712     TmpInst.addOperand(Inst.getOperand(1)); // lane
6713     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6714     TmpInst.addOperand(Inst.getOperand(6));
6715     Inst = TmpInst;
6716     return true;
6717   }
6718 
6719   case ARM::VLD3LNdWB_register_Asm_8:
6720   case ARM::VLD3LNdWB_register_Asm_16:
6721   case ARM::VLD3LNdWB_register_Asm_32:
6722   case ARM::VLD3LNqWB_register_Asm_16:
6723   case ARM::VLD3LNqWB_register_Asm_32: {
6724     MCInst TmpInst;
6725     // Shuffle the operands around so the lane index operand is in the
6726     // right place.
6727     unsigned Spacing;
6728     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6729     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6730     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6731                                             Spacing));
6732     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6733                                             Spacing * 2));
6734     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6735     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6736     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6737     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6738     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6739     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6740                                             Spacing));
6741     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6742                                             Spacing * 2));
6743     TmpInst.addOperand(Inst.getOperand(1)); // lane
6744     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6745     TmpInst.addOperand(Inst.getOperand(6));
6746     Inst = TmpInst;
6747     return true;
6748   }
6749 
6750   case ARM::VLD4LNdWB_register_Asm_8:
6751   case ARM::VLD4LNdWB_register_Asm_16:
6752   case ARM::VLD4LNdWB_register_Asm_32:
6753   case ARM::VLD4LNqWB_register_Asm_16:
6754   case ARM::VLD4LNqWB_register_Asm_32: {
6755     MCInst TmpInst;
6756     // Shuffle the operands around so the lane index operand is in the
6757     // right place.
6758     unsigned Spacing;
6759     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6760     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6761     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6762                                             Spacing));
6763     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6764                                             Spacing * 2));
6765     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6766                                             Spacing * 3));
6767     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6768     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6769     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6770     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6771     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6772     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6773                                             Spacing));
6774     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6775                                             Spacing * 2));
6776     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6777                                             Spacing * 3));
6778     TmpInst.addOperand(Inst.getOperand(1)); // lane
6779     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6780     TmpInst.addOperand(Inst.getOperand(6));
6781     Inst = TmpInst;
6782     return true;
6783   }
6784 
6785   case ARM::VLD1LNdWB_fixed_Asm_8:
6786   case ARM::VLD1LNdWB_fixed_Asm_16:
6787   case ARM::VLD1LNdWB_fixed_Asm_32: {
6788     MCInst TmpInst;
6789     // Shuffle the operands around so the lane index operand is in the
6790     // right place.
6791     unsigned Spacing;
6792     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6793     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6794     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6795     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6796     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6797     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6798     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6799     TmpInst.addOperand(Inst.getOperand(1)); // lane
6800     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6801     TmpInst.addOperand(Inst.getOperand(5));
6802     Inst = TmpInst;
6803     return true;
6804   }
6805 
6806   case ARM::VLD2LNdWB_fixed_Asm_8:
6807   case ARM::VLD2LNdWB_fixed_Asm_16:
6808   case ARM::VLD2LNdWB_fixed_Asm_32:
6809   case ARM::VLD2LNqWB_fixed_Asm_16:
6810   case ARM::VLD2LNqWB_fixed_Asm_32: {
6811     MCInst TmpInst;
6812     // Shuffle the operands around so the lane index operand is in the
6813     // right place.
6814     unsigned Spacing;
6815     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6816     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6817     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6818                                             Spacing));
6819     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6820     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6821     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6822     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6823     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6824     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6825                                             Spacing));
6826     TmpInst.addOperand(Inst.getOperand(1)); // lane
6827     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6828     TmpInst.addOperand(Inst.getOperand(5));
6829     Inst = TmpInst;
6830     return true;
6831   }
6832 
6833   case ARM::VLD3LNdWB_fixed_Asm_8:
6834   case ARM::VLD3LNdWB_fixed_Asm_16:
6835   case ARM::VLD3LNdWB_fixed_Asm_32:
6836   case ARM::VLD3LNqWB_fixed_Asm_16:
6837   case ARM::VLD3LNqWB_fixed_Asm_32: {
6838     MCInst TmpInst;
6839     // Shuffle the operands around so the lane index operand is in the
6840     // right place.
6841     unsigned Spacing;
6842     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6843     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6844     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6845                                             Spacing));
6846     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6847                                             Spacing * 2));
6848     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6849     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6850     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6851     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6852     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6853     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6854                                             Spacing));
6855     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6856                                             Spacing * 2));
6857     TmpInst.addOperand(Inst.getOperand(1)); // lane
6858     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6859     TmpInst.addOperand(Inst.getOperand(5));
6860     Inst = TmpInst;
6861     return true;
6862   }
6863 
6864   case ARM::VLD4LNdWB_fixed_Asm_8:
6865   case ARM::VLD4LNdWB_fixed_Asm_16:
6866   case ARM::VLD4LNdWB_fixed_Asm_32:
6867   case ARM::VLD4LNqWB_fixed_Asm_16:
6868   case ARM::VLD4LNqWB_fixed_Asm_32: {
6869     MCInst TmpInst;
6870     // Shuffle the operands around so the lane index operand is in the
6871     // right place.
6872     unsigned Spacing;
6873     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6874     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6875     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6876                                             Spacing));
6877     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6878                                             Spacing * 2));
6879     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6880                                             Spacing * 3));
6881     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6882     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6883     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6884     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6885     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6886     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6887                                             Spacing));
6888     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6889                                             Spacing * 2));
6890     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6891                                             Spacing * 3));
6892     TmpInst.addOperand(Inst.getOperand(1)); // lane
6893     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6894     TmpInst.addOperand(Inst.getOperand(5));
6895     Inst = TmpInst;
6896     return true;
6897   }
6898 
6899   case ARM::VLD1LNdAsm_8:
6900   case ARM::VLD1LNdAsm_16:
6901   case ARM::VLD1LNdAsm_32: {
6902     MCInst TmpInst;
6903     // Shuffle the operands around so the lane index operand is in the
6904     // right place.
6905     unsigned Spacing;
6906     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6907     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6908     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6909     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6910     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6911     TmpInst.addOperand(Inst.getOperand(1)); // lane
6912     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6913     TmpInst.addOperand(Inst.getOperand(5));
6914     Inst = TmpInst;
6915     return true;
6916   }
6917 
6918   case ARM::VLD2LNdAsm_8:
6919   case ARM::VLD2LNdAsm_16:
6920   case ARM::VLD2LNdAsm_32:
6921   case ARM::VLD2LNqAsm_16:
6922   case ARM::VLD2LNqAsm_32: {
6923     MCInst TmpInst;
6924     // Shuffle the operands around so the lane index operand is in the
6925     // right place.
6926     unsigned Spacing;
6927     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6928     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6929     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6930                                             Spacing));
6931     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6932     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6933     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6934     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6935                                             Spacing));
6936     TmpInst.addOperand(Inst.getOperand(1)); // lane
6937     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6938     TmpInst.addOperand(Inst.getOperand(5));
6939     Inst = TmpInst;
6940     return true;
6941   }
6942 
6943   case ARM::VLD3LNdAsm_8:
6944   case ARM::VLD3LNdAsm_16:
6945   case ARM::VLD3LNdAsm_32:
6946   case ARM::VLD3LNqAsm_16:
6947   case ARM::VLD3LNqAsm_32: {
6948     MCInst TmpInst;
6949     // Shuffle the operands around so the lane index operand is in the
6950     // right place.
6951     unsigned Spacing;
6952     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6953     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6954     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6955                                             Spacing));
6956     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6957                                             Spacing * 2));
6958     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6959     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6960     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6961     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6962                                             Spacing));
6963     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6964                                             Spacing * 2));
6965     TmpInst.addOperand(Inst.getOperand(1)); // lane
6966     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6967     TmpInst.addOperand(Inst.getOperand(5));
6968     Inst = TmpInst;
6969     return true;
6970   }
6971 
6972   case ARM::VLD4LNdAsm_8:
6973   case ARM::VLD4LNdAsm_16:
6974   case ARM::VLD4LNdAsm_32:
6975   case ARM::VLD4LNqAsm_16:
6976   case ARM::VLD4LNqAsm_32: {
6977     MCInst TmpInst;
6978     // Shuffle the operands around so the lane index operand is in the
6979     // right place.
6980     unsigned Spacing;
6981     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6982     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6983     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6984                                             Spacing));
6985     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6986                                             Spacing * 2));
6987     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6988                                             Spacing * 3));
6989     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6990     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6991     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6992     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6993                                             Spacing));
6994     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6995                                             Spacing * 2));
6996     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6997                                             Spacing * 3));
6998     TmpInst.addOperand(Inst.getOperand(1)); // lane
6999     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7000     TmpInst.addOperand(Inst.getOperand(5));
7001     Inst = TmpInst;
7002     return true;
7003   }
7004 
7005   // VLD3DUP single 3-element structure to all lanes instructions.
7006   case ARM::VLD3DUPdAsm_8:
7007   case ARM::VLD3DUPdAsm_16:
7008   case ARM::VLD3DUPdAsm_32:
7009   case ARM::VLD3DUPqAsm_8:
7010   case ARM::VLD3DUPqAsm_16:
7011   case ARM::VLD3DUPqAsm_32: {
7012     MCInst TmpInst;
7013     unsigned Spacing;
7014     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7015     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7016     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7017                                             Spacing));
7018     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7019                                             Spacing * 2));
7020     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7021     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7022     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7023     TmpInst.addOperand(Inst.getOperand(4));
7024     Inst = TmpInst;
7025     return true;
7026   }
7027 
7028   case ARM::VLD3DUPdWB_fixed_Asm_8:
7029   case ARM::VLD3DUPdWB_fixed_Asm_16:
7030   case ARM::VLD3DUPdWB_fixed_Asm_32:
7031   case ARM::VLD3DUPqWB_fixed_Asm_8:
7032   case ARM::VLD3DUPqWB_fixed_Asm_16:
7033   case ARM::VLD3DUPqWB_fixed_Asm_32: {
7034     MCInst TmpInst;
7035     unsigned Spacing;
7036     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7037     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7038     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7039                                             Spacing));
7040     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7041                                             Spacing * 2));
7042     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7043     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7044     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7045     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7046     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7047     TmpInst.addOperand(Inst.getOperand(4));
7048     Inst = TmpInst;
7049     return true;
7050   }
7051 
7052   case ARM::VLD3DUPdWB_register_Asm_8:
7053   case ARM::VLD3DUPdWB_register_Asm_16:
7054   case ARM::VLD3DUPdWB_register_Asm_32:
7055   case ARM::VLD3DUPqWB_register_Asm_8:
7056   case ARM::VLD3DUPqWB_register_Asm_16:
7057   case ARM::VLD3DUPqWB_register_Asm_32: {
7058     MCInst TmpInst;
7059     unsigned Spacing;
7060     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7061     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7062     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7063                                             Spacing));
7064     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7065                                             Spacing * 2));
7066     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7067     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7068     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7069     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7070     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7071     TmpInst.addOperand(Inst.getOperand(5));
7072     Inst = TmpInst;
7073     return true;
7074   }
7075 
7076   // VLD3 multiple 3-element structure instructions.
7077   case ARM::VLD3dAsm_8:
7078   case ARM::VLD3dAsm_16:
7079   case ARM::VLD3dAsm_32:
7080   case ARM::VLD3qAsm_8:
7081   case ARM::VLD3qAsm_16:
7082   case ARM::VLD3qAsm_32: {
7083     MCInst TmpInst;
7084     unsigned Spacing;
7085     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7086     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7087     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7088                                             Spacing));
7089     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7090                                             Spacing * 2));
7091     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7092     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7093     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7094     TmpInst.addOperand(Inst.getOperand(4));
7095     Inst = TmpInst;
7096     return true;
7097   }
7098 
7099   case ARM::VLD3dWB_fixed_Asm_8:
7100   case ARM::VLD3dWB_fixed_Asm_16:
7101   case ARM::VLD3dWB_fixed_Asm_32:
7102   case ARM::VLD3qWB_fixed_Asm_8:
7103   case ARM::VLD3qWB_fixed_Asm_16:
7104   case ARM::VLD3qWB_fixed_Asm_32: {
7105     MCInst TmpInst;
7106     unsigned Spacing;
7107     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7108     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7109     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7110                                             Spacing));
7111     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7112                                             Spacing * 2));
7113     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7114     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7115     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7116     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7117     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7118     TmpInst.addOperand(Inst.getOperand(4));
7119     Inst = TmpInst;
7120     return true;
7121   }
7122 
7123   case ARM::VLD3dWB_register_Asm_8:
7124   case ARM::VLD3dWB_register_Asm_16:
7125   case ARM::VLD3dWB_register_Asm_32:
7126   case ARM::VLD3qWB_register_Asm_8:
7127   case ARM::VLD3qWB_register_Asm_16:
7128   case ARM::VLD3qWB_register_Asm_32: {
7129     MCInst TmpInst;
7130     unsigned Spacing;
7131     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7132     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7133     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7134                                             Spacing));
7135     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7136                                             Spacing * 2));
7137     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7138     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7139     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7140     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7141     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7142     TmpInst.addOperand(Inst.getOperand(5));
7143     Inst = TmpInst;
7144     return true;
7145   }
7146 
7147   // VLD4DUP single 3-element structure to all lanes instructions.
7148   case ARM::VLD4DUPdAsm_8:
7149   case ARM::VLD4DUPdAsm_16:
7150   case ARM::VLD4DUPdAsm_32:
7151   case ARM::VLD4DUPqAsm_8:
7152   case ARM::VLD4DUPqAsm_16:
7153   case ARM::VLD4DUPqAsm_32: {
7154     MCInst TmpInst;
7155     unsigned Spacing;
7156     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7157     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7158     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7159                                             Spacing));
7160     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7161                                             Spacing * 2));
7162     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7163                                             Spacing * 3));
7164     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7165     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7166     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7167     TmpInst.addOperand(Inst.getOperand(4));
7168     Inst = TmpInst;
7169     return true;
7170   }
7171 
7172   case ARM::VLD4DUPdWB_fixed_Asm_8:
7173   case ARM::VLD4DUPdWB_fixed_Asm_16:
7174   case ARM::VLD4DUPdWB_fixed_Asm_32:
7175   case ARM::VLD4DUPqWB_fixed_Asm_8:
7176   case ARM::VLD4DUPqWB_fixed_Asm_16:
7177   case ARM::VLD4DUPqWB_fixed_Asm_32: {
7178     MCInst TmpInst;
7179     unsigned Spacing;
7180     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7181     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7182     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7183                                             Spacing));
7184     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7185                                             Spacing * 2));
7186     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7187                                             Spacing * 3));
7188     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7189     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7190     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7191     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7192     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7193     TmpInst.addOperand(Inst.getOperand(4));
7194     Inst = TmpInst;
7195     return true;
7196   }
7197 
7198   case ARM::VLD4DUPdWB_register_Asm_8:
7199   case ARM::VLD4DUPdWB_register_Asm_16:
7200   case ARM::VLD4DUPdWB_register_Asm_32:
7201   case ARM::VLD4DUPqWB_register_Asm_8:
7202   case ARM::VLD4DUPqWB_register_Asm_16:
7203   case ARM::VLD4DUPqWB_register_Asm_32: {
7204     MCInst TmpInst;
7205     unsigned Spacing;
7206     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7207     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7208     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7209                                             Spacing));
7210     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7211                                             Spacing * 2));
7212     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7213                                             Spacing * 3));
7214     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7215     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7216     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7217     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7218     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7219     TmpInst.addOperand(Inst.getOperand(5));
7220     Inst = TmpInst;
7221     return true;
7222   }
7223 
7224   // VLD4 multiple 4-element structure instructions.
7225   case ARM::VLD4dAsm_8:
7226   case ARM::VLD4dAsm_16:
7227   case ARM::VLD4dAsm_32:
7228   case ARM::VLD4qAsm_8:
7229   case ARM::VLD4qAsm_16:
7230   case ARM::VLD4qAsm_32: {
7231     MCInst TmpInst;
7232     unsigned Spacing;
7233     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7234     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7235     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7236                                             Spacing));
7237     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7238                                             Spacing * 2));
7239     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7240                                             Spacing * 3));
7241     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7242     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7243     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7244     TmpInst.addOperand(Inst.getOperand(4));
7245     Inst = TmpInst;
7246     return true;
7247   }
7248 
7249   case ARM::VLD4dWB_fixed_Asm_8:
7250   case ARM::VLD4dWB_fixed_Asm_16:
7251   case ARM::VLD4dWB_fixed_Asm_32:
7252   case ARM::VLD4qWB_fixed_Asm_8:
7253   case ARM::VLD4qWB_fixed_Asm_16:
7254   case ARM::VLD4qWB_fixed_Asm_32: {
7255     MCInst TmpInst;
7256     unsigned Spacing;
7257     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7258     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7259     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7260                                             Spacing));
7261     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7262                                             Spacing * 2));
7263     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7264                                             Spacing * 3));
7265     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7266     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7267     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7268     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7269     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7270     TmpInst.addOperand(Inst.getOperand(4));
7271     Inst = TmpInst;
7272     return true;
7273   }
7274 
7275   case ARM::VLD4dWB_register_Asm_8:
7276   case ARM::VLD4dWB_register_Asm_16:
7277   case ARM::VLD4dWB_register_Asm_32:
7278   case ARM::VLD4qWB_register_Asm_8:
7279   case ARM::VLD4qWB_register_Asm_16:
7280   case ARM::VLD4qWB_register_Asm_32: {
7281     MCInst TmpInst;
7282     unsigned Spacing;
7283     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7284     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7285     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7286                                             Spacing));
7287     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7288                                             Spacing * 2));
7289     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7290                                             Spacing * 3));
7291     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7292     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7293     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7294     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7295     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7296     TmpInst.addOperand(Inst.getOperand(5));
7297     Inst = TmpInst;
7298     return true;
7299   }
7300 
7301   // VST3 multiple 3-element structure instructions.
7302   case ARM::VST3dAsm_8:
7303   case ARM::VST3dAsm_16:
7304   case ARM::VST3dAsm_32:
7305   case ARM::VST3qAsm_8:
7306   case ARM::VST3qAsm_16:
7307   case ARM::VST3qAsm_32: {
7308     MCInst TmpInst;
7309     unsigned Spacing;
7310     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7311     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7312     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7313     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7314     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7315                                             Spacing));
7316     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7317                                             Spacing * 2));
7318     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7319     TmpInst.addOperand(Inst.getOperand(4));
7320     Inst = TmpInst;
7321     return true;
7322   }
7323 
7324   case ARM::VST3dWB_fixed_Asm_8:
7325   case ARM::VST3dWB_fixed_Asm_16:
7326   case ARM::VST3dWB_fixed_Asm_32:
7327   case ARM::VST3qWB_fixed_Asm_8:
7328   case ARM::VST3qWB_fixed_Asm_16:
7329   case ARM::VST3qWB_fixed_Asm_32: {
7330     MCInst TmpInst;
7331     unsigned Spacing;
7332     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7333     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7334     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7335     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7336     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7337     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7338     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7339                                             Spacing));
7340     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7341                                             Spacing * 2));
7342     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7343     TmpInst.addOperand(Inst.getOperand(4));
7344     Inst = TmpInst;
7345     return true;
7346   }
7347 
7348   case ARM::VST3dWB_register_Asm_8:
7349   case ARM::VST3dWB_register_Asm_16:
7350   case ARM::VST3dWB_register_Asm_32:
7351   case ARM::VST3qWB_register_Asm_8:
7352   case ARM::VST3qWB_register_Asm_16:
7353   case ARM::VST3qWB_register_Asm_32: {
7354     MCInst TmpInst;
7355     unsigned Spacing;
7356     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7357     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7358     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7359     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7360     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7361     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7362     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7363                                             Spacing));
7364     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7365                                             Spacing * 2));
7366     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7367     TmpInst.addOperand(Inst.getOperand(5));
7368     Inst = TmpInst;
7369     return true;
7370   }
7371 
7372   // VST4 multiple 3-element structure instructions.
7373   case ARM::VST4dAsm_8:
7374   case ARM::VST4dAsm_16:
7375   case ARM::VST4dAsm_32:
7376   case ARM::VST4qAsm_8:
7377   case ARM::VST4qAsm_16:
7378   case ARM::VST4qAsm_32: {
7379     MCInst TmpInst;
7380     unsigned Spacing;
7381     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7382     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7383     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7384     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7385     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7386                                             Spacing));
7387     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7388                                             Spacing * 2));
7389     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7390                                             Spacing * 3));
7391     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7392     TmpInst.addOperand(Inst.getOperand(4));
7393     Inst = TmpInst;
7394     return true;
7395   }
7396 
7397   case ARM::VST4dWB_fixed_Asm_8:
7398   case ARM::VST4dWB_fixed_Asm_16:
7399   case ARM::VST4dWB_fixed_Asm_32:
7400   case ARM::VST4qWB_fixed_Asm_8:
7401   case ARM::VST4qWB_fixed_Asm_16:
7402   case ARM::VST4qWB_fixed_Asm_32: {
7403     MCInst TmpInst;
7404     unsigned Spacing;
7405     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7406     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7407     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7408     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7409     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7410     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7411     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7412                                             Spacing));
7413     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7414                                             Spacing * 2));
7415     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7416                                             Spacing * 3));
7417     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7418     TmpInst.addOperand(Inst.getOperand(4));
7419     Inst = TmpInst;
7420     return true;
7421   }
7422 
7423   case ARM::VST4dWB_register_Asm_8:
7424   case ARM::VST4dWB_register_Asm_16:
7425   case ARM::VST4dWB_register_Asm_32:
7426   case ARM::VST4qWB_register_Asm_8:
7427   case ARM::VST4qWB_register_Asm_16:
7428   case ARM::VST4qWB_register_Asm_32: {
7429     MCInst TmpInst;
7430     unsigned Spacing;
7431     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7432     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7433     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7434     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7435     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7436     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7437     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7438                                             Spacing));
7439     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7440                                             Spacing * 2));
7441     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7442                                             Spacing * 3));
7443     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7444     TmpInst.addOperand(Inst.getOperand(5));
7445     Inst = TmpInst;
7446     return true;
7447   }
7448 
7449   // Handle encoding choice for the shift-immediate instructions.
7450   case ARM::t2LSLri:
7451   case ARM::t2LSRri:
7452   case ARM::t2ASRri: {
7453     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7454         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7455         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7456         !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7457           static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7458       unsigned NewOpc;
7459       switch (Inst.getOpcode()) {
7460       default: llvm_unreachable("unexpected opcode");
7461       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7462       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7463       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7464       }
7465       // The Thumb1 operands aren't in the same order. Awesome, eh?
7466       MCInst TmpInst;
7467       TmpInst.setOpcode(NewOpc);
7468       TmpInst.addOperand(Inst.getOperand(0));
7469       TmpInst.addOperand(Inst.getOperand(5));
7470       TmpInst.addOperand(Inst.getOperand(1));
7471       TmpInst.addOperand(Inst.getOperand(2));
7472       TmpInst.addOperand(Inst.getOperand(3));
7473       TmpInst.addOperand(Inst.getOperand(4));
7474       Inst = TmpInst;
7475       return true;
7476     }
7477     return false;
7478   }
7479 
7480   // Handle the Thumb2 mode MOV complex aliases.
7481   case ARM::t2MOVsr:
7482   case ARM::t2MOVSsr: {
7483     // Which instruction to expand to depends on the CCOut operand and
7484     // whether we're in an IT block if the register operands are low
7485     // registers.
7486     bool isNarrow = false;
7487     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7488         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7489         isARMLowRegister(Inst.getOperand(2).getReg()) &&
7490         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7491         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7492       isNarrow = true;
7493     MCInst TmpInst;
7494     unsigned newOpc;
7495     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7496     default: llvm_unreachable("unexpected opcode!");
7497     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7498     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7499     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7500     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7501     }
7502     TmpInst.setOpcode(newOpc);
7503     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7504     if (isNarrow)
7505       TmpInst.addOperand(MCOperand::CreateReg(
7506           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7507     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7508     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7509     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7510     TmpInst.addOperand(Inst.getOperand(5));
7511     if (!isNarrow)
7512       TmpInst.addOperand(MCOperand::CreateReg(
7513           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7514     Inst = TmpInst;
7515     return true;
7516   }
7517   case ARM::t2MOVsi:
7518   case ARM::t2MOVSsi: {
7519     // Which instruction to expand to depends on the CCOut operand and
7520     // whether we're in an IT block if the register operands are low
7521     // registers.
7522     bool isNarrow = false;
7523     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7524         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7525         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7526       isNarrow = true;
7527     MCInst TmpInst;
7528     unsigned newOpc;
7529     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7530     default: llvm_unreachable("unexpected opcode!");
7531     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7532     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7533     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7534     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7535     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7536     }
7537     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7538     if (Amount == 32) Amount = 0;
7539     TmpInst.setOpcode(newOpc);
7540     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7541     if (isNarrow)
7542       TmpInst.addOperand(MCOperand::CreateReg(
7543           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7544     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7545     if (newOpc != ARM::t2RRX)
7546       TmpInst.addOperand(MCOperand::CreateImm(Amount));
7547     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7548     TmpInst.addOperand(Inst.getOperand(4));
7549     if (!isNarrow)
7550       TmpInst.addOperand(MCOperand::CreateReg(
7551           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7552     Inst = TmpInst;
7553     return true;
7554   }
7555   // Handle the ARM mode MOV complex aliases.
7556   case ARM::ASRr:
7557   case ARM::LSRr:
7558   case ARM::LSLr:
7559   case ARM::RORr: {
7560     ARM_AM::ShiftOpc ShiftTy;
7561     switch(Inst.getOpcode()) {
7562     default: llvm_unreachable("unexpected opcode!");
7563     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7564     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7565     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7566     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7567     }
7568     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7569     MCInst TmpInst;
7570     TmpInst.setOpcode(ARM::MOVsr);
7571     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7572     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7573     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7574     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7575     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7576     TmpInst.addOperand(Inst.getOperand(4));
7577     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7578     Inst = TmpInst;
7579     return true;
7580   }
7581   case ARM::ASRi:
7582   case ARM::LSRi:
7583   case ARM::LSLi:
7584   case ARM::RORi: {
7585     ARM_AM::ShiftOpc ShiftTy;
7586     switch(Inst.getOpcode()) {
7587     default: llvm_unreachable("unexpected opcode!");
7588     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7589     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7590     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7591     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7592     }
7593     // A shift by zero is a plain MOVr, not a MOVsi.
7594     unsigned Amt = Inst.getOperand(2).getImm();
7595     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7596     // A shift by 32 should be encoded as 0 when permitted
7597     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7598       Amt = 0;
7599     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7600     MCInst TmpInst;
7601     TmpInst.setOpcode(Opc);
7602     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7603     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7604     if (Opc == ARM::MOVsi)
7605       TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7606     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7607     TmpInst.addOperand(Inst.getOperand(4));
7608     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7609     Inst = TmpInst;
7610     return true;
7611   }
7612   case ARM::RRXi: {
7613     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7614     MCInst TmpInst;
7615     TmpInst.setOpcode(ARM::MOVsi);
7616     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7617     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7618     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7619     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7620     TmpInst.addOperand(Inst.getOperand(3));
7621     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7622     Inst = TmpInst;
7623     return true;
7624   }
7625   case ARM::t2LDMIA_UPD: {
7626     // If this is a load of a single register, then we should use
7627     // a post-indexed LDR instruction instead, per the ARM ARM.
7628     if (Inst.getNumOperands() != 5)
7629       return false;
7630     MCInst TmpInst;
7631     TmpInst.setOpcode(ARM::t2LDR_POST);
7632     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7633     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7634     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7635     TmpInst.addOperand(MCOperand::CreateImm(4));
7636     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7637     TmpInst.addOperand(Inst.getOperand(3));
7638     Inst = TmpInst;
7639     return true;
7640   }
7641   case ARM::t2STMDB_UPD: {
7642     // If this is a store of a single register, then we should use
7643     // a pre-indexed STR instruction instead, per the ARM ARM.
7644     if (Inst.getNumOperands() != 5)
7645       return false;
7646     MCInst TmpInst;
7647     TmpInst.setOpcode(ARM::t2STR_PRE);
7648     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7649     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7650     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7651     TmpInst.addOperand(MCOperand::CreateImm(-4));
7652     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7653     TmpInst.addOperand(Inst.getOperand(3));
7654     Inst = TmpInst;
7655     return true;
7656   }
7657   case ARM::LDMIA_UPD:
7658     // If this is a load of a single register via a 'pop', then we should use
7659     // a post-indexed LDR instruction instead, per the ARM ARM.
7660     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
7661         Inst.getNumOperands() == 5) {
7662       MCInst TmpInst;
7663       TmpInst.setOpcode(ARM::LDR_POST_IMM);
7664       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7665       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7666       TmpInst.addOperand(Inst.getOperand(1)); // Rn
7667       TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7668       TmpInst.addOperand(MCOperand::CreateImm(4));
7669       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7670       TmpInst.addOperand(Inst.getOperand(3));
7671       Inst = TmpInst;
7672       return true;
7673     }
7674     break;
7675   case ARM::STMDB_UPD:
7676     // If this is a store of a single register via a 'push', then we should use
7677     // a pre-indexed STR instruction instead, per the ARM ARM.
7678     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
7679         Inst.getNumOperands() == 5) {
7680       MCInst TmpInst;
7681       TmpInst.setOpcode(ARM::STR_PRE_IMM);
7682       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7683       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7684       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7685       TmpInst.addOperand(MCOperand::CreateImm(-4));
7686       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7687       TmpInst.addOperand(Inst.getOperand(3));
7688       Inst = TmpInst;
7689     }
7690     break;
7691   case ARM::t2ADDri12:
7692     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7693     // mnemonic was used (not "addw"), encoding T3 is preferred.
7694     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
7695         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7696       break;
7697     Inst.setOpcode(ARM::t2ADDri);
7698     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7699     break;
7700   case ARM::t2SUBri12:
7701     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7702     // mnemonic was used (not "subw"), encoding T3 is preferred.
7703     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
7704         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7705       break;
7706     Inst.setOpcode(ARM::t2SUBri);
7707     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7708     break;
7709   case ARM::tADDi8:
7710     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7711     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7712     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7713     // to encoding T1 if <Rd> is omitted."
7714     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7715       Inst.setOpcode(ARM::tADDi3);
7716       return true;
7717     }
7718     break;
7719   case ARM::tSUBi8:
7720     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7721     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7722     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7723     // to encoding T1 if <Rd> is omitted."
7724     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7725       Inst.setOpcode(ARM::tSUBi3);
7726       return true;
7727     }
7728     break;
7729   case ARM::t2ADDri:
7730   case ARM::t2SUBri: {
7731     // If the destination and first source operand are the same, and
7732     // the flags are compatible with the current IT status, use encoding T2
7733     // instead of T3. For compatibility with the system 'as'. Make sure the
7734     // wide encoding wasn't explicit.
7735     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7736         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7737         (unsigned)Inst.getOperand(2).getImm() > 255 ||
7738         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7739          (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7740         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7741          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7742       break;
7743     MCInst TmpInst;
7744     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7745                       ARM::tADDi8 : ARM::tSUBi8);
7746     TmpInst.addOperand(Inst.getOperand(0));
7747     TmpInst.addOperand(Inst.getOperand(5));
7748     TmpInst.addOperand(Inst.getOperand(0));
7749     TmpInst.addOperand(Inst.getOperand(2));
7750     TmpInst.addOperand(Inst.getOperand(3));
7751     TmpInst.addOperand(Inst.getOperand(4));
7752     Inst = TmpInst;
7753     return true;
7754   }
7755   case ARM::t2ADDrr: {
7756     // If the destination and first source operand are the same, and
7757     // there's no setting of the flags, use encoding T2 instead of T3.
7758     // Note that this is only for ADD, not SUB. This mirrors the system
7759     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7760     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7761         Inst.getOperand(5).getReg() != 0 ||
7762         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7763          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7764       break;
7765     MCInst TmpInst;
7766     TmpInst.setOpcode(ARM::tADDhirr);
7767     TmpInst.addOperand(Inst.getOperand(0));
7768     TmpInst.addOperand(Inst.getOperand(0));
7769     TmpInst.addOperand(Inst.getOperand(2));
7770     TmpInst.addOperand(Inst.getOperand(3));
7771     TmpInst.addOperand(Inst.getOperand(4));
7772     Inst = TmpInst;
7773     return true;
7774   }
7775   case ARM::tADDrSP: {
7776     // If the non-SP source operand and the destination operand are not the
7777     // same, we need to use the 32-bit encoding if it's available.
7778     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7779       Inst.setOpcode(ARM::t2ADDrr);
7780       Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7781       return true;
7782     }
7783     break;
7784   }
7785   case ARM::tB:
7786     // A Thumb conditional branch outside of an IT block is a tBcc.
7787     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7788       Inst.setOpcode(ARM::tBcc);
7789       return true;
7790     }
7791     break;
7792   case ARM::t2B:
7793     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7794     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7795       Inst.setOpcode(ARM::t2Bcc);
7796       return true;
7797     }
7798     break;
7799   case ARM::t2Bcc:
7800     // If the conditional is AL or we're in an IT block, we really want t2B.
7801     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7802       Inst.setOpcode(ARM::t2B);
7803       return true;
7804     }
7805     break;
7806   case ARM::tBcc:
7807     // If the conditional is AL, we really want tB.
7808     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7809       Inst.setOpcode(ARM::tB);
7810       return true;
7811     }
7812     break;
7813   case ARM::tLDMIA: {
7814     // If the register list contains any high registers, or if the writeback
7815     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7816     // instead if we're in Thumb2. Otherwise, this should have generated
7817     // an error in validateInstruction().
7818     unsigned Rn = Inst.getOperand(0).getReg();
7819     bool hasWritebackToken =
7820         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7821          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7822     bool listContainsBase;
7823     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7824         (!listContainsBase && !hasWritebackToken) ||
7825         (listContainsBase && hasWritebackToken)) {
7826       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7827       assert (isThumbTwo());
7828       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7829       // If we're switching to the updating version, we need to insert
7830       // the writeback tied operand.
7831       if (hasWritebackToken)
7832         Inst.insert(Inst.begin(),
7833                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7834       return true;
7835     }
7836     break;
7837   }
7838   case ARM::tSTMIA_UPD: {
7839     // If the register list contains any high registers, we need to use
7840     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7841     // should have generated an error in validateInstruction().
7842     unsigned Rn = Inst.getOperand(0).getReg();
7843     bool listContainsBase;
7844     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7845       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7846       assert (isThumbTwo());
7847       Inst.setOpcode(ARM::t2STMIA_UPD);
7848       return true;
7849     }
7850     break;
7851   }
7852   case ARM::tPOP: {
7853     bool listContainsBase;
7854     // If the register list contains any high registers, we need to use
7855     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7856     // should have generated an error in validateInstruction().
7857     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7858       return false;
7859     assert (isThumbTwo());
7860     Inst.setOpcode(ARM::t2LDMIA_UPD);
7861     // Add the base register and writeback operands.
7862     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7863     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7864     return true;
7865   }
7866   case ARM::tPUSH: {
7867     bool listContainsBase;
7868     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7869       return false;
7870     assert (isThumbTwo());
7871     Inst.setOpcode(ARM::t2STMDB_UPD);
7872     // Add the base register and writeback operands.
7873     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7874     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7875     return true;
7876   }
7877   case ARM::t2MOVi: {
7878     // If we can use the 16-bit encoding and the user didn't explicitly
7879     // request the 32-bit variant, transform it here.
7880     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7881         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7882         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7883           Inst.getOperand(4).getReg() == ARM::CPSR) ||
7884          (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7885         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7886          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7887       // The operands aren't in the same order for tMOVi8...
7888       MCInst TmpInst;
7889       TmpInst.setOpcode(ARM::tMOVi8);
7890       TmpInst.addOperand(Inst.getOperand(0));
7891       TmpInst.addOperand(Inst.getOperand(4));
7892       TmpInst.addOperand(Inst.getOperand(1));
7893       TmpInst.addOperand(Inst.getOperand(2));
7894       TmpInst.addOperand(Inst.getOperand(3));
7895       Inst = TmpInst;
7896       return true;
7897     }
7898     break;
7899   }
7900   case ARM::t2MOVr: {
7901     // If we can use the 16-bit encoding and the user didn't explicitly
7902     // request the 32-bit variant, transform it here.
7903     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7904         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7905         Inst.getOperand(2).getImm() == ARMCC::AL &&
7906         Inst.getOperand(4).getReg() == ARM::CPSR &&
7907         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7908          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7909       // The operands aren't the same for tMOV[S]r... (no cc_out)
7910       MCInst TmpInst;
7911       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7912       TmpInst.addOperand(Inst.getOperand(0));
7913       TmpInst.addOperand(Inst.getOperand(1));
7914       TmpInst.addOperand(Inst.getOperand(2));
7915       TmpInst.addOperand(Inst.getOperand(3));
7916       Inst = TmpInst;
7917       return true;
7918     }
7919     break;
7920   }
7921   case ARM::t2SXTH:
7922   case ARM::t2SXTB:
7923   case ARM::t2UXTH:
7924   case ARM::t2UXTB: {
7925     // If we can use the 16-bit encoding and the user didn't explicitly
7926     // request the 32-bit variant, transform it here.
7927     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7928         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7929         Inst.getOperand(2).getImm() == 0 &&
7930         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7931          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7932       unsigned NewOpc;
7933       switch (Inst.getOpcode()) {
7934       default: llvm_unreachable("Illegal opcode!");
7935       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7936       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7937       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7938       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7939       }
7940       // The operands aren't the same for thumb1 (no rotate operand).
7941       MCInst TmpInst;
7942       TmpInst.setOpcode(NewOpc);
7943       TmpInst.addOperand(Inst.getOperand(0));
7944       TmpInst.addOperand(Inst.getOperand(1));
7945       TmpInst.addOperand(Inst.getOperand(3));
7946       TmpInst.addOperand(Inst.getOperand(4));
7947       Inst = TmpInst;
7948       return true;
7949     }
7950     break;
7951   }
7952   case ARM::MOVsi: {
7953     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7954     // rrx shifts and asr/lsr of #32 is encoded as 0
7955     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7956       return false;
7957     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7958       // Shifting by zero is accepted as a vanilla 'MOVr'
7959       MCInst TmpInst;
7960       TmpInst.setOpcode(ARM::MOVr);
7961       TmpInst.addOperand(Inst.getOperand(0));
7962       TmpInst.addOperand(Inst.getOperand(1));
7963       TmpInst.addOperand(Inst.getOperand(3));
7964       TmpInst.addOperand(Inst.getOperand(4));
7965       TmpInst.addOperand(Inst.getOperand(5));
7966       Inst = TmpInst;
7967       return true;
7968     }
7969     return false;
7970   }
7971   case ARM::ANDrsi:
7972   case ARM::ORRrsi:
7973   case ARM::EORrsi:
7974   case ARM::BICrsi:
7975   case ARM::SUBrsi:
7976   case ARM::ADDrsi: {
7977     unsigned newOpc;
7978     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7979     if (SOpc == ARM_AM::rrx) return false;
7980     switch (Inst.getOpcode()) {
7981     default: llvm_unreachable("unexpected opcode!");
7982     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7983     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7984     case ARM::EORrsi: newOpc = ARM::EORrr; break;
7985     case ARM::BICrsi: newOpc = ARM::BICrr; break;
7986     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7987     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7988     }
7989     // If the shift is by zero, use the non-shifted instruction definition.
7990     // The exception is for right shifts, where 0 == 32
7991     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7992         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7993       MCInst TmpInst;
7994       TmpInst.setOpcode(newOpc);
7995       TmpInst.addOperand(Inst.getOperand(0));
7996       TmpInst.addOperand(Inst.getOperand(1));
7997       TmpInst.addOperand(Inst.getOperand(2));
7998       TmpInst.addOperand(Inst.getOperand(4));
7999       TmpInst.addOperand(Inst.getOperand(5));
8000       TmpInst.addOperand(Inst.getOperand(6));
8001       Inst = TmpInst;
8002       return true;
8003     }
8004     return false;
8005   }
8006   case ARM::ITasm:
8007   case ARM::t2IT: {
8008     // The mask bits for all but the first condition are represented as
8009     // the low bit of the condition code value implies 't'. We currently
8010     // always have 1 implies 't', so XOR toggle the bits if the low bit
8011     // of the condition code is zero.
8012     MCOperand &MO = Inst.getOperand(1);
8013     unsigned Mask = MO.getImm();
8014     unsigned OrigMask = Mask;
8015     unsigned TZ = countTrailingZeros(Mask);
8016     if ((Inst.getOperand(0).getImm() & 1) == 0) {
8017       assert(Mask && TZ <= 3 && "illegal IT mask value!");
8018       Mask ^= (0xE << TZ) & 0xF;
8019     }
8020     MO.setImm(Mask);
8021 
8022     // Set up the IT block state according to the IT instruction we just
8023     // matched.
8024     assert(!inITBlock() && "nested IT blocks?!");
8025     ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8026     ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8027     ITState.CurPosition = 0;
8028     ITState.FirstCond = true;
8029     break;
8030   }
8031   case ARM::t2LSLrr:
8032   case ARM::t2LSRrr:
8033   case ARM::t2ASRrr:
8034   case ARM::t2SBCrr:
8035   case ARM::t2RORrr:
8036   case ARM::t2BICrr:
8037   {
8038     // Assemblers should use the narrow encodings of these instructions when permissible.
8039     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8040          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8041         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8042         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8043          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8044         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8045          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8046              ".w"))) {
8047       unsigned NewOpc;
8048       switch (Inst.getOpcode()) {
8049         default: llvm_unreachable("unexpected opcode");
8050         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8051         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8052         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8053         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8054         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8055         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8056       }
8057       MCInst TmpInst;
8058       TmpInst.setOpcode(NewOpc);
8059       TmpInst.addOperand(Inst.getOperand(0));
8060       TmpInst.addOperand(Inst.getOperand(5));
8061       TmpInst.addOperand(Inst.getOperand(1));
8062       TmpInst.addOperand(Inst.getOperand(2));
8063       TmpInst.addOperand(Inst.getOperand(3));
8064       TmpInst.addOperand(Inst.getOperand(4));
8065       Inst = TmpInst;
8066       return true;
8067     }
8068     return false;
8069   }
8070   case ARM::t2ANDrr:
8071   case ARM::t2EORrr:
8072   case ARM::t2ADCrr:
8073   case ARM::t2ORRrr:
8074   {
8075     // Assemblers should use the narrow encodings of these instructions when permissible.
8076     // These instructions are special in that they are commutable, so shorter encodings
8077     // are available more often.
8078     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8079          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8080         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8081          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8082         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8083          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8084         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8085          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8086              ".w"))) {
8087       unsigned NewOpc;
8088       switch (Inst.getOpcode()) {
8089         default: llvm_unreachable("unexpected opcode");
8090         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8091         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8092         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8093         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8094       }
8095       MCInst TmpInst;
8096       TmpInst.setOpcode(NewOpc);
8097       TmpInst.addOperand(Inst.getOperand(0));
8098       TmpInst.addOperand(Inst.getOperand(5));
8099       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8100         TmpInst.addOperand(Inst.getOperand(1));
8101         TmpInst.addOperand(Inst.getOperand(2));
8102       } else {
8103         TmpInst.addOperand(Inst.getOperand(2));
8104         TmpInst.addOperand(Inst.getOperand(1));
8105       }
8106       TmpInst.addOperand(Inst.getOperand(3));
8107       TmpInst.addOperand(Inst.getOperand(4));
8108       Inst = TmpInst;
8109       return true;
8110     }
8111     return false;
8112   }
8113   }
8114   return false;
8115 }
8116 
8117 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8118   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8119   // suffix depending on whether they're in an IT block or not.
8120   unsigned Opc = Inst.getOpcode();
8121   const MCInstrDesc &MCID = MII.get(Opc);
8122   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8123     assert(MCID.hasOptionalDef() &&
8124            "optionally flag setting instruction missing optional def operand");
8125     assert(MCID.NumOperands == Inst.getNumOperands() &&
8126            "operand count mismatch!");
8127     // Find the optional-def operand (cc_out).
8128     unsigned OpNo;
8129     for (OpNo = 0;
8130          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8131          ++OpNo)
8132       ;
8133     // If we're parsing Thumb1, reject it completely.
8134     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8135       return Match_MnemonicFail;
8136     // If we're parsing Thumb2, which form is legal depends on whether we're
8137     // in an IT block.
8138     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8139         !inITBlock())
8140       return Match_RequiresITBlock;
8141     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8142         inITBlock())
8143       return Match_RequiresNotITBlock;
8144   }
8145   // Some high-register supporting Thumb1 encodings only allow both registers
8146   // to be from r0-r7 when in Thumb2.
8147   else if (Opc == ARM::tADDhirr && isThumbOne() &&
8148            isARMLowRegister(Inst.getOperand(1).getReg()) &&
8149            isARMLowRegister(Inst.getOperand(2).getReg()))
8150     return Match_RequiresThumb2;
8151   // Others only require ARMv6 or later.
8152   else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8153            isARMLowRegister(Inst.getOperand(0).getReg()) &&
8154            isARMLowRegister(Inst.getOperand(1).getReg()))
8155     return Match_RequiresV6;
8156   return Match_Success;
8157 }
8158 
8159 namespace llvm {
8160 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8161   return true; // In an assembly source, no need to second-guess
8162 }
8163 }
8164 
8165 static const char *getSubtargetFeatureName(uint64_t Val);
8166 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8167                                            OperandVector &Operands,
8168                                            MCStreamer &Out, uint64_t &ErrorInfo,
8169                                            bool MatchingInlineAsm) {
8170   MCInst Inst;
8171   unsigned MatchResult;
8172 
8173   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8174                                      MatchingInlineAsm);
8175   switch (MatchResult) {
8176   default: break;
8177   case Match_Success:
8178     // Context sensitive operand constraints aren't handled by the matcher,
8179     // so check them here.
8180     if (validateInstruction(Inst, Operands)) {
8181       // Still progress the IT block, otherwise one wrong condition causes
8182       // nasty cascading errors.
8183       forwardITPosition();
8184       return true;
8185     }
8186 
8187     { // processInstruction() updates inITBlock state, we need to save it away
8188       bool wasInITBlock = inITBlock();
8189 
8190       // Some instructions need post-processing to, for example, tweak which
8191       // encoding is selected. Loop on it while changes happen so the
8192       // individual transformations can chain off each other. E.g.,
8193       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8194       while (processInstruction(Inst, Operands))
8195         ;
8196 
8197       // Only after the instruction is fully processed, we can validate it
8198       if (wasInITBlock && hasV8Ops() && isThumb() &&
8199           !isV8EligibleForIT(&Inst)) {
8200         Warning(IDLoc, "deprecated instruction in IT block");
8201       }
8202     }
8203 
8204     // Only move forward at the very end so that everything in validate
8205     // and process gets a consistent answer about whether we're in an IT
8206     // block.
8207     forwardITPosition();
8208 
8209     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8210     // doesn't actually encode.
8211     if (Inst.getOpcode() == ARM::ITasm)
8212       return false;
8213 
8214     Inst.setLoc(IDLoc);
8215     Out.EmitInstruction(Inst, STI);
8216     return false;
8217   case Match_MissingFeature: {
8218     assert(ErrorInfo && "Unknown missing feature!");
8219     // Special case the error message for the very common case where only
8220     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8221     std::string Msg = "instruction requires:";
8222     uint64_t Mask = 1;
8223     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8224       if (ErrorInfo & Mask) {
8225         Msg += " ";
8226         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8227       }
8228       Mask <<= 1;
8229     }
8230     return Error(IDLoc, Msg);
8231   }
8232   case Match_InvalidOperand: {
8233     SMLoc ErrorLoc = IDLoc;
8234     if (ErrorInfo != ~0ULL) {
8235       if (ErrorInfo >= Operands.size())
8236         return Error(IDLoc, "too few operands for instruction");
8237 
8238       ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8239       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8240     }
8241 
8242     return Error(ErrorLoc, "invalid operand for instruction");
8243   }
8244   case Match_MnemonicFail:
8245     return Error(IDLoc, "invalid instruction",
8246                  ((ARMOperand &)*Operands[0]).getLocRange());
8247   case Match_RequiresNotITBlock:
8248     return Error(IDLoc, "flag setting instruction only valid outside IT block");
8249   case Match_RequiresITBlock:
8250     return Error(IDLoc, "instruction only valid inside IT block");
8251   case Match_RequiresV6:
8252     return Error(IDLoc, "instruction variant requires ARMv6 or later");
8253   case Match_RequiresThumb2:
8254     return Error(IDLoc, "instruction variant requires Thumb2");
8255   case Match_ImmRange0_15: {
8256     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8257     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8258     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8259   }
8260   case Match_ImmRange0_239: {
8261     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8262     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8263     return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8264   }
8265   case Match_AlignedMemoryRequiresNone:
8266   case Match_DupAlignedMemoryRequiresNone:
8267   case Match_AlignedMemoryRequires16:
8268   case Match_DupAlignedMemoryRequires16:
8269   case Match_AlignedMemoryRequires32:
8270   case Match_DupAlignedMemoryRequires32:
8271   case Match_AlignedMemoryRequires64:
8272   case Match_DupAlignedMemoryRequires64:
8273   case Match_AlignedMemoryRequires64or128:
8274   case Match_DupAlignedMemoryRequires64or128:
8275   case Match_AlignedMemoryRequires64or128or256:
8276   {
8277     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8278     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8279     switch (MatchResult) {
8280       default:
8281         llvm_unreachable("Missing Match_Aligned type");
8282       case Match_AlignedMemoryRequiresNone:
8283       case Match_DupAlignedMemoryRequiresNone:
8284         return Error(ErrorLoc, "alignment must be omitted");
8285       case Match_AlignedMemoryRequires16:
8286       case Match_DupAlignedMemoryRequires16:
8287         return Error(ErrorLoc, "alignment must be 16 or omitted");
8288       case Match_AlignedMemoryRequires32:
8289       case Match_DupAlignedMemoryRequires32:
8290         return Error(ErrorLoc, "alignment must be 32 or omitted");
8291       case Match_AlignedMemoryRequires64:
8292       case Match_DupAlignedMemoryRequires64:
8293         return Error(ErrorLoc, "alignment must be 64 or omitted");
8294       case Match_AlignedMemoryRequires64or128:
8295       case Match_DupAlignedMemoryRequires64or128:
8296         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8297       case Match_AlignedMemoryRequires64or128or256:
8298         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8299     }
8300   }
8301   }
8302 
8303   llvm_unreachable("Implement any new match types added!");
8304 }
8305 
8306 /// parseDirective parses the arm specific directives
8307 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8308   const MCObjectFileInfo::Environment Format =
8309     getContext().getObjectFileInfo()->getObjectFileType();
8310   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8311 
8312   StringRef IDVal = DirectiveID.getIdentifier();
8313   if (IDVal == ".word")
8314     return parseLiteralValues(4, DirectiveID.getLoc());
8315   else if (IDVal == ".short" || IDVal == ".hword")
8316     return parseLiteralValues(2, DirectiveID.getLoc());
8317   else if (IDVal == ".thumb")
8318     return parseDirectiveThumb(DirectiveID.getLoc());
8319   else if (IDVal == ".arm")
8320     return parseDirectiveARM(DirectiveID.getLoc());
8321   else if (IDVal == ".thumb_func")
8322     return parseDirectiveThumbFunc(DirectiveID.getLoc());
8323   else if (IDVal == ".code")
8324     return parseDirectiveCode(DirectiveID.getLoc());
8325   else if (IDVal == ".syntax")
8326     return parseDirectiveSyntax(DirectiveID.getLoc());
8327   else if (IDVal == ".unreq")
8328     return parseDirectiveUnreq(DirectiveID.getLoc());
8329   else if (IDVal == ".fnend")
8330     return parseDirectiveFnEnd(DirectiveID.getLoc());
8331   else if (IDVal == ".cantunwind")
8332     return parseDirectiveCantUnwind(DirectiveID.getLoc());
8333   else if (IDVal == ".personality")
8334     return parseDirectivePersonality(DirectiveID.getLoc());
8335   else if (IDVal == ".handlerdata")
8336     return parseDirectiveHandlerData(DirectiveID.getLoc());
8337   else if (IDVal == ".setfp")
8338     return parseDirectiveSetFP(DirectiveID.getLoc());
8339   else if (IDVal == ".pad")
8340     return parseDirectivePad(DirectiveID.getLoc());
8341   else if (IDVal == ".save")
8342     return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8343   else if (IDVal == ".vsave")
8344     return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8345   else if (IDVal == ".ltorg" || IDVal == ".pool")
8346     return parseDirectiveLtorg(DirectiveID.getLoc());
8347   else if (IDVal == ".even")
8348     return parseDirectiveEven(DirectiveID.getLoc());
8349   else if (IDVal == ".personalityindex")
8350     return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8351   else if (IDVal == ".unwind_raw")
8352     return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8353   else if (IDVal == ".movsp")
8354     return parseDirectiveMovSP(DirectiveID.getLoc());
8355   else if (IDVal == ".arch_extension")
8356     return parseDirectiveArchExtension(DirectiveID.getLoc());
8357   else if (IDVal == ".align")
8358     return parseDirectiveAlign(DirectiveID.getLoc());
8359   else if (IDVal == ".thumb_set")
8360     return parseDirectiveThumbSet(DirectiveID.getLoc());
8361 
8362   if (!IsMachO) {
8363     if (IDVal == ".arch")
8364       return parseDirectiveArch(DirectiveID.getLoc());
8365     else if (IDVal == ".cpu")
8366       return parseDirectiveCPU(DirectiveID.getLoc());
8367     else if (IDVal == ".eabi_attribute")
8368       return parseDirectiveEabiAttr(DirectiveID.getLoc());
8369     else if (IDVal == ".fpu")
8370       return parseDirectiveFPU(DirectiveID.getLoc());
8371     else if (IDVal == ".fnstart")
8372       return parseDirectiveFnStart(DirectiveID.getLoc());
8373     else if (IDVal == ".inst")
8374       return parseDirectiveInst(DirectiveID.getLoc());
8375     else if (IDVal == ".inst.n")
8376       return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8377     else if (IDVal == ".inst.w")
8378       return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8379     else if (IDVal == ".object_arch")
8380       return parseDirectiveObjectArch(DirectiveID.getLoc());
8381     else if (IDVal == ".tlsdescseq")
8382       return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8383   }
8384 
8385   return true;
8386 }
8387 
8388 /// parseLiteralValues
8389 ///  ::= .hword expression [, expression]*
8390 ///  ::= .short expression [, expression]*
8391 ///  ::= .word expression [, expression]*
8392 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8393   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8394     for (;;) {
8395       const MCExpr *Value;
8396       if (getParser().parseExpression(Value)) {
8397         Parser.eatToEndOfStatement();
8398         return false;
8399       }
8400 
8401       getParser().getStreamer().EmitValue(Value, Size);
8402 
8403       if (getLexer().is(AsmToken::EndOfStatement))
8404         break;
8405 
8406       // FIXME: Improve diagnostic.
8407       if (getLexer().isNot(AsmToken::Comma)) {
8408         Error(L, "unexpected token in directive");
8409         return false;
8410       }
8411       Parser.Lex();
8412     }
8413   }
8414 
8415   Parser.Lex();
8416   return false;
8417 }
8418 
8419 /// parseDirectiveThumb
8420 ///  ::= .thumb
8421 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8422   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8423     Error(L, "unexpected token in directive");
8424     return false;
8425   }
8426   Parser.Lex();
8427 
8428   if (!hasThumb()) {
8429     Error(L, "target does not support Thumb mode");
8430     return false;
8431   }
8432 
8433   if (!isThumb())
8434     SwitchMode();
8435 
8436   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8437   return false;
8438 }
8439 
8440 /// parseDirectiveARM
8441 ///  ::= .arm
8442 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8443   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8444     Error(L, "unexpected token in directive");
8445     return false;
8446   }
8447   Parser.Lex();
8448 
8449   if (!hasARM()) {
8450     Error(L, "target does not support ARM mode");
8451     return false;
8452   }
8453 
8454   if (isThumb())
8455     SwitchMode();
8456 
8457   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8458   return false;
8459 }
8460 
8461 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8462   if (NextSymbolIsThumb) {
8463     getParser().getStreamer().EmitThumbFunc(Symbol);
8464     NextSymbolIsThumb = false;
8465   }
8466 }
8467 
8468 /// parseDirectiveThumbFunc
8469 ///  ::= .thumbfunc symbol_name
8470 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8471   const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8472   bool isMachO = MAI->hasSubsectionsViaSymbols();
8473 
8474   // Darwin asm has (optionally) function name after .thumb_func direction
8475   // ELF doesn't
8476   if (isMachO) {
8477     const AsmToken &Tok = Parser.getTok();
8478     if (Tok.isNot(AsmToken::EndOfStatement)) {
8479       if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8480         Error(L, "unexpected token in .thumb_func directive");
8481         return false;
8482       }
8483 
8484       MCSymbol *Func =
8485           getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8486       getParser().getStreamer().EmitThumbFunc(Func);
8487       Parser.Lex(); // Consume the identifier token.
8488       return false;
8489     }
8490   }
8491 
8492   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8493     Error(L, "unexpected token in directive");
8494     return false;
8495   }
8496 
8497   NextSymbolIsThumb = true;
8498   return false;
8499 }
8500 
8501 /// parseDirectiveSyntax
8502 ///  ::= .syntax unified | divided
8503 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8504   const AsmToken &Tok = Parser.getTok();
8505   if (Tok.isNot(AsmToken::Identifier)) {
8506     Error(L, "unexpected token in .syntax directive");
8507     return false;
8508   }
8509 
8510   StringRef Mode = Tok.getString();
8511   if (Mode == "unified" || Mode == "UNIFIED") {
8512     Parser.Lex();
8513   } else if (Mode == "divided" || Mode == "DIVIDED") {
8514     Error(L, "'.syntax divided' arm asssembly not supported");
8515     return false;
8516   } else {
8517     Error(L, "unrecognized syntax mode in .syntax directive");
8518     return false;
8519   }
8520 
8521   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8522     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8523     return false;
8524   }
8525   Parser.Lex();
8526 
8527   // TODO tell the MC streamer the mode
8528   // getParser().getStreamer().Emit???();
8529   return false;
8530 }
8531 
8532 /// parseDirectiveCode
8533 ///  ::= .code 16 | 32
8534 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8535   const AsmToken &Tok = Parser.getTok();
8536   if (Tok.isNot(AsmToken::Integer)) {
8537     Error(L, "unexpected token in .code directive");
8538     return false;
8539   }
8540   int64_t Val = Parser.getTok().getIntVal();
8541   if (Val != 16 && Val != 32) {
8542     Error(L, "invalid operand to .code directive");
8543     return false;
8544   }
8545   Parser.Lex();
8546 
8547   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8548     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8549     return false;
8550   }
8551   Parser.Lex();
8552 
8553   if (Val == 16) {
8554     if (!hasThumb()) {
8555       Error(L, "target does not support Thumb mode");
8556       return false;
8557     }
8558 
8559     if (!isThumb())
8560       SwitchMode();
8561     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8562   } else {
8563     if (!hasARM()) {
8564       Error(L, "target does not support ARM mode");
8565       return false;
8566     }
8567 
8568     if (isThumb())
8569       SwitchMode();
8570     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8571   }
8572 
8573   return false;
8574 }
8575 
8576 /// parseDirectiveReq
8577 ///  ::= name .req registername
8578 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8579   Parser.Lex(); // Eat the '.req' token.
8580   unsigned Reg;
8581   SMLoc SRegLoc, ERegLoc;
8582   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8583     Parser.eatToEndOfStatement();
8584     Error(SRegLoc, "register name expected");
8585     return false;
8586   }
8587 
8588   // Shouldn't be anything else.
8589   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8590     Parser.eatToEndOfStatement();
8591     Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8592     return false;
8593   }
8594 
8595   Parser.Lex(); // Consume the EndOfStatement
8596 
8597   if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8598     Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8599     return false;
8600   }
8601 
8602   return false;
8603 }
8604 
8605 /// parseDirectiveUneq
8606 ///  ::= .unreq registername
8607 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8608   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8609     Parser.eatToEndOfStatement();
8610     Error(L, "unexpected input in .unreq directive.");
8611     return false;
8612   }
8613   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8614   Parser.Lex(); // Eat the identifier.
8615   return false;
8616 }
8617 
8618 /// parseDirectiveArch
8619 ///  ::= .arch token
8620 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8621   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8622 
8623   unsigned ID = StringSwitch<unsigned>(Arch)
8624 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8625     .Case(NAME, ARM::ID)
8626 #define ARM_ARCH_ALIAS(NAME, ID) \
8627     .Case(NAME, ARM::ID)
8628 #include "MCTargetDesc/ARMArchName.def"
8629     .Default(ARM::INVALID_ARCH);
8630 
8631   if (ID == ARM::INVALID_ARCH) {
8632     Error(L, "Unknown arch name");
8633     return false;
8634   }
8635 
8636   getTargetStreamer().emitArch(ID);
8637   return false;
8638 }
8639 
8640 /// parseDirectiveEabiAttr
8641 ///  ::= .eabi_attribute int, int [, "str"]
8642 ///  ::= .eabi_attribute Tag_name, int [, "str"]
8643 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8644   int64_t Tag;
8645   SMLoc TagLoc;
8646   TagLoc = Parser.getTok().getLoc();
8647   if (Parser.getTok().is(AsmToken::Identifier)) {
8648     StringRef Name = Parser.getTok().getIdentifier();
8649     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8650     if (Tag == -1) {
8651       Error(TagLoc, "attribute name not recognised: " + Name);
8652       Parser.eatToEndOfStatement();
8653       return false;
8654     }
8655     Parser.Lex();
8656   } else {
8657     const MCExpr *AttrExpr;
8658 
8659     TagLoc = Parser.getTok().getLoc();
8660     if (Parser.parseExpression(AttrExpr)) {
8661       Parser.eatToEndOfStatement();
8662       return false;
8663     }
8664 
8665     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8666     if (!CE) {
8667       Error(TagLoc, "expected numeric constant");
8668       Parser.eatToEndOfStatement();
8669       return false;
8670     }
8671 
8672     Tag = CE->getValue();
8673   }
8674 
8675   if (Parser.getTok().isNot(AsmToken::Comma)) {
8676     Error(Parser.getTok().getLoc(), "comma expected");
8677     Parser.eatToEndOfStatement();
8678     return false;
8679   }
8680   Parser.Lex(); // skip comma
8681 
8682   StringRef StringValue = "";
8683   bool IsStringValue = false;
8684 
8685   int64_t IntegerValue = 0;
8686   bool IsIntegerValue = false;
8687 
8688   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8689     IsStringValue = true;
8690   else if (Tag == ARMBuildAttrs::compatibility) {
8691     IsStringValue = true;
8692     IsIntegerValue = true;
8693   } else if (Tag < 32 || Tag % 2 == 0)
8694     IsIntegerValue = true;
8695   else if (Tag % 2 == 1)
8696     IsStringValue = true;
8697   else
8698     llvm_unreachable("invalid tag type");
8699 
8700   if (IsIntegerValue) {
8701     const MCExpr *ValueExpr;
8702     SMLoc ValueExprLoc = Parser.getTok().getLoc();
8703     if (Parser.parseExpression(ValueExpr)) {
8704       Parser.eatToEndOfStatement();
8705       return false;
8706     }
8707 
8708     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8709     if (!CE) {
8710       Error(ValueExprLoc, "expected numeric constant");
8711       Parser.eatToEndOfStatement();
8712       return false;
8713     }
8714 
8715     IntegerValue = CE->getValue();
8716   }
8717 
8718   if (Tag == ARMBuildAttrs::compatibility) {
8719     if (Parser.getTok().isNot(AsmToken::Comma))
8720       IsStringValue = false;
8721     else
8722       Parser.Lex();
8723   }
8724 
8725   if (IsStringValue) {
8726     if (Parser.getTok().isNot(AsmToken::String)) {
8727       Error(Parser.getTok().getLoc(), "bad string constant");
8728       Parser.eatToEndOfStatement();
8729       return false;
8730     }
8731 
8732     StringValue = Parser.getTok().getStringContents();
8733     Parser.Lex();
8734   }
8735 
8736   if (IsIntegerValue && IsStringValue) {
8737     assert(Tag == ARMBuildAttrs::compatibility);
8738     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8739   } else if (IsIntegerValue)
8740     getTargetStreamer().emitAttribute(Tag, IntegerValue);
8741   else if (IsStringValue)
8742     getTargetStreamer().emitTextAttribute(Tag, StringValue);
8743   return false;
8744 }
8745 
8746 /// parseDirectiveCPU
8747 ///  ::= .cpu str
8748 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8749   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8750   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8751   return false;
8752 }
8753 
8754 // FIXME: This is duplicated in getARMFPUFeatures() in
8755 // tools/clang/lib/Driver/Tools.cpp
8756 static const struct {
8757   const unsigned Fpu;
8758   const uint64_t Enabled;
8759   const uint64_t Disabled;
8760 } Fpus[] = {
8761       {ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON},
8762       {ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON},
8763       {ARM::VFPV3, ARM::FeatureVFP3, ARM::FeatureNEON},
8764       {ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},
8765       {ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},
8766       {ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},
8767       {ARM::FP_ARMV8, ARM::FeatureFPARMv8,
8768        ARM::FeatureNEON | ARM::FeatureCrypto},
8769       {ARM::NEON, ARM::FeatureNEON, 0},
8770       {ARM::NEON_VFPV4, ARM::FeatureVFP4 | ARM::FeatureNEON, 0},
8771       {ARM::NEON_FP_ARMV8, ARM::FeatureFPARMv8 | ARM::FeatureNEON,
8772        ARM::FeatureCrypto},
8773       {ARM::CRYPTO_NEON_FP_ARMV8,
8774        ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, 0},
8775       {ARM::SOFTVFP, 0, 0},
8776 };
8777 
8778 /// parseDirectiveFPU
8779 ///  ::= .fpu str
8780 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8781   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8782 
8783   unsigned ID = StringSwitch<unsigned>(FPU)
8784 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8785 #include "ARMFPUName.def"
8786     .Default(ARM::INVALID_FPU);
8787 
8788   if (ID == ARM::INVALID_FPU) {
8789     Error(L, "Unknown FPU name");
8790     return false;
8791   }
8792 
8793   for (const auto &Fpu : Fpus) {
8794     if (Fpu.Fpu != ID)
8795       continue;
8796 
8797     // Need to toggle features that should be on but are off and that
8798     // should off but are on.
8799     uint64_t Toggle = (Fpu.Enabled & ~STI.getFeatureBits()) |
8800                       (Fpu.Disabled & STI.getFeatureBits());
8801     setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
8802     break;
8803   }
8804 
8805   getTargetStreamer().emitFPU(ID);
8806   return false;
8807 }
8808 
8809 /// parseDirectiveFnStart
8810 ///  ::= .fnstart
8811 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8812   if (UC.hasFnStart()) {
8813     Error(L, ".fnstart starts before the end of previous one");
8814     UC.emitFnStartLocNotes();
8815     return false;
8816   }
8817 
8818   // Reset the unwind directives parser state
8819   UC.reset();
8820 
8821   getTargetStreamer().emitFnStart();
8822 
8823   UC.recordFnStart(L);
8824   return false;
8825 }
8826 
8827 /// parseDirectiveFnEnd
8828 ///  ::= .fnend
8829 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8830   // Check the ordering of unwind directives
8831   if (!UC.hasFnStart()) {
8832     Error(L, ".fnstart must precede .fnend directive");
8833     return false;
8834   }
8835 
8836   // Reset the unwind directives parser state
8837   getTargetStreamer().emitFnEnd();
8838 
8839   UC.reset();
8840   return false;
8841 }
8842 
8843 /// parseDirectiveCantUnwind
8844 ///  ::= .cantunwind
8845 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8846   UC.recordCantUnwind(L);
8847 
8848   // Check the ordering of unwind directives
8849   if (!UC.hasFnStart()) {
8850     Error(L, ".fnstart must precede .cantunwind directive");
8851     return false;
8852   }
8853   if (UC.hasHandlerData()) {
8854     Error(L, ".cantunwind can't be used with .handlerdata directive");
8855     UC.emitHandlerDataLocNotes();
8856     return false;
8857   }
8858   if (UC.hasPersonality()) {
8859     Error(L, ".cantunwind can't be used with .personality directive");
8860     UC.emitPersonalityLocNotes();
8861     return false;
8862   }
8863 
8864   getTargetStreamer().emitCantUnwind();
8865   return false;
8866 }
8867 
8868 /// parseDirectivePersonality
8869 ///  ::= .personality name
8870 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8871   bool HasExistingPersonality = UC.hasPersonality();
8872 
8873   UC.recordPersonality(L);
8874 
8875   // Check the ordering of unwind directives
8876   if (!UC.hasFnStart()) {
8877     Error(L, ".fnstart must precede .personality directive");
8878     return false;
8879   }
8880   if (UC.cantUnwind()) {
8881     Error(L, ".personality can't be used with .cantunwind directive");
8882     UC.emitCantUnwindLocNotes();
8883     return false;
8884   }
8885   if (UC.hasHandlerData()) {
8886     Error(L, ".personality must precede .handlerdata directive");
8887     UC.emitHandlerDataLocNotes();
8888     return false;
8889   }
8890   if (HasExistingPersonality) {
8891     Parser.eatToEndOfStatement();
8892     Error(L, "multiple personality directives");
8893     UC.emitPersonalityLocNotes();
8894     return false;
8895   }
8896 
8897   // Parse the name of the personality routine
8898   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8899     Parser.eatToEndOfStatement();
8900     Error(L, "unexpected input in .personality directive.");
8901     return false;
8902   }
8903   StringRef Name(Parser.getTok().getIdentifier());
8904   Parser.Lex();
8905 
8906   MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8907   getTargetStreamer().emitPersonality(PR);
8908   return false;
8909 }
8910 
8911 /// parseDirectiveHandlerData
8912 ///  ::= .handlerdata
8913 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8914   UC.recordHandlerData(L);
8915 
8916   // Check the ordering of unwind directives
8917   if (!UC.hasFnStart()) {
8918     Error(L, ".fnstart must precede .personality directive");
8919     return false;
8920   }
8921   if (UC.cantUnwind()) {
8922     Error(L, ".handlerdata can't be used with .cantunwind directive");
8923     UC.emitCantUnwindLocNotes();
8924     return false;
8925   }
8926 
8927   getTargetStreamer().emitHandlerData();
8928   return false;
8929 }
8930 
8931 /// parseDirectiveSetFP
8932 ///  ::= .setfp fpreg, spreg [, offset]
8933 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8934   // Check the ordering of unwind directives
8935   if (!UC.hasFnStart()) {
8936     Error(L, ".fnstart must precede .setfp directive");
8937     return false;
8938   }
8939   if (UC.hasHandlerData()) {
8940     Error(L, ".setfp must precede .handlerdata directive");
8941     return false;
8942   }
8943 
8944   // Parse fpreg
8945   SMLoc FPRegLoc = Parser.getTok().getLoc();
8946   int FPReg = tryParseRegister();
8947   if (FPReg == -1) {
8948     Error(FPRegLoc, "frame pointer register expected");
8949     return false;
8950   }
8951 
8952   // Consume comma
8953   if (Parser.getTok().isNot(AsmToken::Comma)) {
8954     Error(Parser.getTok().getLoc(), "comma expected");
8955     return false;
8956   }
8957   Parser.Lex(); // skip comma
8958 
8959   // Parse spreg
8960   SMLoc SPRegLoc = Parser.getTok().getLoc();
8961   int SPReg = tryParseRegister();
8962   if (SPReg == -1) {
8963     Error(SPRegLoc, "stack pointer register expected");
8964     return false;
8965   }
8966 
8967   if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8968     Error(SPRegLoc, "register should be either $sp or the latest fp register");
8969     return false;
8970   }
8971 
8972   // Update the frame pointer register
8973   UC.saveFPReg(FPReg);
8974 
8975   // Parse offset
8976   int64_t Offset = 0;
8977   if (Parser.getTok().is(AsmToken::Comma)) {
8978     Parser.Lex(); // skip comma
8979 
8980     if (Parser.getTok().isNot(AsmToken::Hash) &&
8981         Parser.getTok().isNot(AsmToken::Dollar)) {
8982       Error(Parser.getTok().getLoc(), "'#' expected");
8983       return false;
8984     }
8985     Parser.Lex(); // skip hash token.
8986 
8987     const MCExpr *OffsetExpr;
8988     SMLoc ExLoc = Parser.getTok().getLoc();
8989     SMLoc EndLoc;
8990     if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8991       Error(ExLoc, "malformed setfp offset");
8992       return false;
8993     }
8994     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8995     if (!CE) {
8996       Error(ExLoc, "setfp offset must be an immediate");
8997       return false;
8998     }
8999 
9000     Offset = CE->getValue();
9001   }
9002 
9003   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9004                                 static_cast<unsigned>(SPReg), Offset);
9005   return false;
9006 }
9007 
9008 /// parseDirective
9009 ///  ::= .pad offset
9010 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9011   // Check the ordering of unwind directives
9012   if (!UC.hasFnStart()) {
9013     Error(L, ".fnstart must precede .pad directive");
9014     return false;
9015   }
9016   if (UC.hasHandlerData()) {
9017     Error(L, ".pad must precede .handlerdata directive");
9018     return false;
9019   }
9020 
9021   // Parse the offset
9022   if (Parser.getTok().isNot(AsmToken::Hash) &&
9023       Parser.getTok().isNot(AsmToken::Dollar)) {
9024     Error(Parser.getTok().getLoc(), "'#' expected");
9025     return false;
9026   }
9027   Parser.Lex(); // skip hash token.
9028 
9029   const MCExpr *OffsetExpr;
9030   SMLoc ExLoc = Parser.getTok().getLoc();
9031   SMLoc EndLoc;
9032   if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9033     Error(ExLoc, "malformed pad offset");
9034     return false;
9035   }
9036   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9037   if (!CE) {
9038     Error(ExLoc, "pad offset must be an immediate");
9039     return false;
9040   }
9041 
9042   getTargetStreamer().emitPad(CE->getValue());
9043   return false;
9044 }
9045 
9046 /// parseDirectiveRegSave
9047 ///  ::= .save  { registers }
9048 ///  ::= .vsave { registers }
9049 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9050   // Check the ordering of unwind directives
9051   if (!UC.hasFnStart()) {
9052     Error(L, ".fnstart must precede .save or .vsave directives");
9053     return false;
9054   }
9055   if (UC.hasHandlerData()) {
9056     Error(L, ".save or .vsave must precede .handlerdata directive");
9057     return false;
9058   }
9059 
9060   // RAII object to make sure parsed operands are deleted.
9061   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9062 
9063   // Parse the register list
9064   if (parseRegisterList(Operands))
9065     return false;
9066   ARMOperand &Op = (ARMOperand &)*Operands[0];
9067   if (!IsVector && !Op.isRegList()) {
9068     Error(L, ".save expects GPR registers");
9069     return false;
9070   }
9071   if (IsVector && !Op.isDPRRegList()) {
9072     Error(L, ".vsave expects DPR registers");
9073     return false;
9074   }
9075 
9076   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9077   return false;
9078 }
9079 
9080 /// parseDirectiveInst
9081 ///  ::= .inst opcode [, ...]
9082 ///  ::= .inst.n opcode [, ...]
9083 ///  ::= .inst.w opcode [, ...]
9084 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9085   int Width;
9086 
9087   if (isThumb()) {
9088     switch (Suffix) {
9089     case 'n':
9090       Width = 2;
9091       break;
9092     case 'w':
9093       Width = 4;
9094       break;
9095     default:
9096       Parser.eatToEndOfStatement();
9097       Error(Loc, "cannot determine Thumb instruction size, "
9098                  "use inst.n/inst.w instead");
9099       return false;
9100     }
9101   } else {
9102     if (Suffix) {
9103       Parser.eatToEndOfStatement();
9104       Error(Loc, "width suffixes are invalid in ARM mode");
9105       return false;
9106     }
9107     Width = 4;
9108   }
9109 
9110   if (getLexer().is(AsmToken::EndOfStatement)) {
9111     Parser.eatToEndOfStatement();
9112     Error(Loc, "expected expression following directive");
9113     return false;
9114   }
9115 
9116   for (;;) {
9117     const MCExpr *Expr;
9118 
9119     if (getParser().parseExpression(Expr)) {
9120       Error(Loc, "expected expression");
9121       return false;
9122     }
9123 
9124     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9125     if (!Value) {
9126       Error(Loc, "expected constant expression");
9127       return false;
9128     }
9129 
9130     switch (Width) {
9131     case 2:
9132       if (Value->getValue() > 0xffff) {
9133         Error(Loc, "inst.n operand is too big, use inst.w instead");
9134         return false;
9135       }
9136       break;
9137     case 4:
9138       if (Value->getValue() > 0xffffffff) {
9139         Error(Loc,
9140               StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9141         return false;
9142       }
9143       break;
9144     default:
9145       llvm_unreachable("only supported widths are 2 and 4");
9146     }
9147 
9148     getTargetStreamer().emitInst(Value->getValue(), Suffix);
9149 
9150     if (getLexer().is(AsmToken::EndOfStatement))
9151       break;
9152 
9153     if (getLexer().isNot(AsmToken::Comma)) {
9154       Error(Loc, "unexpected token in directive");
9155       return false;
9156     }
9157 
9158     Parser.Lex();
9159   }
9160 
9161   Parser.Lex();
9162   return false;
9163 }
9164 
9165 /// parseDirectiveLtorg
9166 ///  ::= .ltorg | .pool
9167 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9168   getTargetStreamer().emitCurrentConstantPool();
9169   return false;
9170 }
9171 
9172 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9173   const MCSection *Section = getStreamer().getCurrentSection().first;
9174 
9175   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9176     TokError("unexpected token in directive");
9177     return false;
9178   }
9179 
9180   if (!Section) {
9181     getStreamer().InitSections();
9182     Section = getStreamer().getCurrentSection().first;
9183   }
9184 
9185   assert(Section && "must have section to emit alignment");
9186   if (Section->UseCodeAlign())
9187     getStreamer().EmitCodeAlignment(2);
9188   else
9189     getStreamer().EmitValueToAlignment(2);
9190 
9191   return false;
9192 }
9193 
9194 /// parseDirectivePersonalityIndex
9195 ///   ::= .personalityindex index
9196 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9197   bool HasExistingPersonality = UC.hasPersonality();
9198 
9199   UC.recordPersonalityIndex(L);
9200 
9201   if (!UC.hasFnStart()) {
9202     Parser.eatToEndOfStatement();
9203     Error(L, ".fnstart must precede .personalityindex directive");
9204     return false;
9205   }
9206   if (UC.cantUnwind()) {
9207     Parser.eatToEndOfStatement();
9208     Error(L, ".personalityindex cannot be used with .cantunwind");
9209     UC.emitCantUnwindLocNotes();
9210     return false;
9211   }
9212   if (UC.hasHandlerData()) {
9213     Parser.eatToEndOfStatement();
9214     Error(L, ".personalityindex must precede .handlerdata directive");
9215     UC.emitHandlerDataLocNotes();
9216     return false;
9217   }
9218   if (HasExistingPersonality) {
9219     Parser.eatToEndOfStatement();
9220     Error(L, "multiple personality directives");
9221     UC.emitPersonalityLocNotes();
9222     return false;
9223   }
9224 
9225   const MCExpr *IndexExpression;
9226   SMLoc IndexLoc = Parser.getTok().getLoc();
9227   if (Parser.parseExpression(IndexExpression)) {
9228     Parser.eatToEndOfStatement();
9229     return false;
9230   }
9231 
9232   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9233   if (!CE) {
9234     Parser.eatToEndOfStatement();
9235     Error(IndexLoc, "index must be a constant number");
9236     return false;
9237   }
9238   if (CE->getValue() < 0 ||
9239       CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9240     Parser.eatToEndOfStatement();
9241     Error(IndexLoc, "personality routine index should be in range [0-3]");
9242     return false;
9243   }
9244 
9245   getTargetStreamer().emitPersonalityIndex(CE->getValue());
9246   return false;
9247 }
9248 
9249 /// parseDirectiveUnwindRaw
9250 ///   ::= .unwind_raw offset, opcode [, opcode...]
9251 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9252   if (!UC.hasFnStart()) {
9253     Parser.eatToEndOfStatement();
9254     Error(L, ".fnstart must precede .unwind_raw directives");
9255     return false;
9256   }
9257 
9258   int64_t StackOffset;
9259 
9260   const MCExpr *OffsetExpr;
9261   SMLoc OffsetLoc = getLexer().getLoc();
9262   if (getLexer().is(AsmToken::EndOfStatement) ||
9263       getParser().parseExpression(OffsetExpr)) {
9264     Error(OffsetLoc, "expected expression");
9265     Parser.eatToEndOfStatement();
9266     return false;
9267   }
9268 
9269   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9270   if (!CE) {
9271     Error(OffsetLoc, "offset must be a constant");
9272     Parser.eatToEndOfStatement();
9273     return false;
9274   }
9275 
9276   StackOffset = CE->getValue();
9277 
9278   if (getLexer().isNot(AsmToken::Comma)) {
9279     Error(getLexer().getLoc(), "expected comma");
9280     Parser.eatToEndOfStatement();
9281     return false;
9282   }
9283   Parser.Lex();
9284 
9285   SmallVector<uint8_t, 16> Opcodes;
9286   for (;;) {
9287     const MCExpr *OE;
9288 
9289     SMLoc OpcodeLoc = getLexer().getLoc();
9290     if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9291       Error(OpcodeLoc, "expected opcode expression");
9292       Parser.eatToEndOfStatement();
9293       return false;
9294     }
9295 
9296     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9297     if (!OC) {
9298       Error(OpcodeLoc, "opcode value must be a constant");
9299       Parser.eatToEndOfStatement();
9300       return false;
9301     }
9302 
9303     const int64_t Opcode = OC->getValue();
9304     if (Opcode & ~0xff) {
9305       Error(OpcodeLoc, "invalid opcode");
9306       Parser.eatToEndOfStatement();
9307       return false;
9308     }
9309 
9310     Opcodes.push_back(uint8_t(Opcode));
9311 
9312     if (getLexer().is(AsmToken::EndOfStatement))
9313       break;
9314 
9315     if (getLexer().isNot(AsmToken::Comma)) {
9316       Error(getLexer().getLoc(), "unexpected token in directive");
9317       Parser.eatToEndOfStatement();
9318       return false;
9319     }
9320 
9321     Parser.Lex();
9322   }
9323 
9324   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9325 
9326   Parser.Lex();
9327   return false;
9328 }
9329 
9330 /// parseDirectiveTLSDescSeq
9331 ///   ::= .tlsdescseq tls-variable
9332 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9333   if (getLexer().isNot(AsmToken::Identifier)) {
9334     TokError("expected variable after '.tlsdescseq' directive");
9335     Parser.eatToEndOfStatement();
9336     return false;
9337   }
9338 
9339   const MCSymbolRefExpr *SRE =
9340     MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9341                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9342   Lex();
9343 
9344   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9345     Error(Parser.getTok().getLoc(), "unexpected token");
9346     Parser.eatToEndOfStatement();
9347     return false;
9348   }
9349 
9350   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9351   return false;
9352 }
9353 
9354 /// parseDirectiveMovSP
9355 ///  ::= .movsp reg [, #offset]
9356 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9357   if (!UC.hasFnStart()) {
9358     Parser.eatToEndOfStatement();
9359     Error(L, ".fnstart must precede .movsp directives");
9360     return false;
9361   }
9362   if (UC.getFPReg() != ARM::SP) {
9363     Parser.eatToEndOfStatement();
9364     Error(L, "unexpected .movsp directive");
9365     return false;
9366   }
9367 
9368   SMLoc SPRegLoc = Parser.getTok().getLoc();
9369   int SPReg = tryParseRegister();
9370   if (SPReg == -1) {
9371     Parser.eatToEndOfStatement();
9372     Error(SPRegLoc, "register expected");
9373     return false;
9374   }
9375 
9376   if (SPReg == ARM::SP || SPReg == ARM::PC) {
9377     Parser.eatToEndOfStatement();
9378     Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9379     return false;
9380   }
9381 
9382   int64_t Offset = 0;
9383   if (Parser.getTok().is(AsmToken::Comma)) {
9384     Parser.Lex();
9385 
9386     if (Parser.getTok().isNot(AsmToken::Hash)) {
9387       Error(Parser.getTok().getLoc(), "expected #constant");
9388       Parser.eatToEndOfStatement();
9389       return false;
9390     }
9391     Parser.Lex();
9392 
9393     const MCExpr *OffsetExpr;
9394     SMLoc OffsetLoc = Parser.getTok().getLoc();
9395     if (Parser.parseExpression(OffsetExpr)) {
9396       Parser.eatToEndOfStatement();
9397       Error(OffsetLoc, "malformed offset expression");
9398       return false;
9399     }
9400 
9401     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9402     if (!CE) {
9403       Parser.eatToEndOfStatement();
9404       Error(OffsetLoc, "offset must be an immediate constant");
9405       return false;
9406     }
9407 
9408     Offset = CE->getValue();
9409   }
9410 
9411   getTargetStreamer().emitMovSP(SPReg, Offset);
9412   UC.saveFPReg(SPReg);
9413 
9414   return false;
9415 }
9416 
9417 /// parseDirectiveObjectArch
9418 ///   ::= .object_arch name
9419 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9420   if (getLexer().isNot(AsmToken::Identifier)) {
9421     Error(getLexer().getLoc(), "unexpected token");
9422     Parser.eatToEndOfStatement();
9423     return false;
9424   }
9425 
9426   StringRef Arch = Parser.getTok().getString();
9427   SMLoc ArchLoc = Parser.getTok().getLoc();
9428   getLexer().Lex();
9429 
9430   unsigned ID = StringSwitch<unsigned>(Arch)
9431 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9432     .Case(NAME, ARM::ID)
9433 #define ARM_ARCH_ALIAS(NAME, ID) \
9434     .Case(NAME, ARM::ID)
9435 #include "MCTargetDesc/ARMArchName.def"
9436 #undef ARM_ARCH_NAME
9437 #undef ARM_ARCH_ALIAS
9438     .Default(ARM::INVALID_ARCH);
9439 
9440   if (ID == ARM::INVALID_ARCH) {
9441     Error(ArchLoc, "unknown architecture '" + Arch + "'");
9442     Parser.eatToEndOfStatement();
9443     return false;
9444   }
9445 
9446   getTargetStreamer().emitObjectArch(ID);
9447 
9448   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9449     Error(getLexer().getLoc(), "unexpected token");
9450     Parser.eatToEndOfStatement();
9451   }
9452 
9453   return false;
9454 }
9455 
9456 /// parseDirectiveAlign
9457 ///   ::= .align
9458 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9459   // NOTE: if this is not the end of the statement, fall back to the target
9460   // agnostic handling for this directive which will correctly handle this.
9461   if (getLexer().isNot(AsmToken::EndOfStatement))
9462     return true;
9463 
9464   // '.align' is target specifically handled to mean 2**2 byte alignment.
9465   if (getStreamer().getCurrentSection().first->UseCodeAlign())
9466     getStreamer().EmitCodeAlignment(4, 0);
9467   else
9468     getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9469 
9470   return false;
9471 }
9472 
9473 /// parseDirectiveThumbSet
9474 ///  ::= .thumb_set name, value
9475 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9476   StringRef Name;
9477   if (Parser.parseIdentifier(Name)) {
9478     TokError("expected identifier after '.thumb_set'");
9479     Parser.eatToEndOfStatement();
9480     return false;
9481   }
9482 
9483   if (getLexer().isNot(AsmToken::Comma)) {
9484     TokError("expected comma after name '" + Name + "'");
9485     Parser.eatToEndOfStatement();
9486     return false;
9487   }
9488   Lex();
9489 
9490   const MCExpr *Value;
9491   if (Parser.parseExpression(Value)) {
9492     TokError("missing expression");
9493     Parser.eatToEndOfStatement();
9494     return false;
9495   }
9496 
9497   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9498     TokError("unexpected token");
9499     Parser.eatToEndOfStatement();
9500     return false;
9501   }
9502   Lex();
9503 
9504   MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9505   getTargetStreamer().emitThumbSet(Alias, Value);
9506   return false;
9507 }
9508 
9509 /// Force static initialization.
9510 extern "C" void LLVMInitializeARMAsmParser() {
9511   RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9512   RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9513   RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9514   RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9515 }
9516 
9517 #define GET_REGISTER_MATCHER
9518 #define GET_SUBTARGET_FEATURE_NAME
9519 #define GET_MATCHER_IMPLEMENTATION
9520 #include "ARMGenAsmMatcher.inc"
9521 
9522 static const struct {
9523   const char *Name;
9524   const unsigned ArchCheck;
9525   const uint64_t Features;
9526 } Extensions[] = {
9527   { "crc", Feature_HasV8, ARM::FeatureCRC },
9528   { "crypto",  Feature_HasV8,
9529     ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9530   { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9531   { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9532     ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9533   // FIXME: iWMMXT not supported
9534   { "iwmmxt", Feature_None, 0 },
9535   // FIXME: iWMMXT2 not supported
9536   { "iwmmxt2", Feature_None, 0 },
9537   // FIXME: Maverick not supported
9538   { "maverick", Feature_None, 0 },
9539   { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9540   // FIXME: ARMv6-m OS Extensions feature not checked
9541   { "os", Feature_None, 0 },
9542   // FIXME: Also available in ARMv6-K
9543   { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9544   { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9545   // FIXME: Only available in A-class, isel not predicated
9546   { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9547   // FIXME: xscale not supported
9548   { "xscale", Feature_None, 0 },
9549 };
9550 
9551 /// parseDirectiveArchExtension
9552 ///   ::= .arch_extension [no]feature
9553 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9554   if (getLexer().isNot(AsmToken::Identifier)) {
9555     Error(getLexer().getLoc(), "unexpected token");
9556     Parser.eatToEndOfStatement();
9557     return false;
9558   }
9559 
9560   StringRef Name = Parser.getTok().getString();
9561   SMLoc ExtLoc = Parser.getTok().getLoc();
9562   getLexer().Lex();
9563 
9564   bool EnableFeature = true;
9565   if (Name.startswith_lower("no")) {
9566     EnableFeature = false;
9567     Name = Name.substr(2);
9568   }
9569 
9570   for (const auto &Extension : Extensions) {
9571     if (Extension.Name != Name)
9572       continue;
9573 
9574     if (!Extension.Features)
9575       report_fatal_error("unsupported architectural extension: " + Name);
9576 
9577     if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
9578       Error(ExtLoc, "architectural extension '" + Name + "' is not "
9579             "allowed for the current base architecture");
9580       return false;
9581     }
9582 
9583     uint64_t ToggleFeatures = EnableFeature
9584                                   ? (~STI.getFeatureBits() & Extension.Features)
9585                                   : ( STI.getFeatureBits() & Extension.Features);
9586     uint64_t Features =
9587         ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
9588     setAvailableFeatures(Features);
9589     return false;
9590   }
9591 
9592   Error(ExtLoc, "unknown architectural extension: " + Name);
9593   Parser.eatToEndOfStatement();
9594   return false;
9595 }
9596 
9597 // Define this matcher function after the auto-generated include so we
9598 // have the match class enum definitions.
9599 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
9600                                                   unsigned Kind) {
9601   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
9602   // If the kind is a token for a literal immediate, check if our asm
9603   // operand matches. This is for InstAliases which have a fixed-value
9604   // immediate in the syntax.
9605   switch (Kind) {
9606   default: break;
9607   case MCK__35_0:
9608     if (Op.isImm())
9609       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
9610         if (CE->getValue() == 0)
9611           return Match_Success;
9612     break;
9613   case MCK_ARMSOImm:
9614     if (Op.isImm()) {
9615       const MCExpr *SOExpr = Op.getImm();
9616       int64_t Value;
9617       if (!SOExpr->EvaluateAsAbsolute(Value))
9618         return Match_Success;
9619       assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
9620              "expression value must be representable in 32 bits");
9621     }
9622     break;
9623   case MCK_GPRPair:
9624     if (Op.isReg() &&
9625         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
9626       return Match_Success;
9627     break;
9628   }
9629   return Match_InvalidOperand;
9630 }
9631