1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
49 
50 using namespace llvm;
51 
52 namespace {
53 
54 class ARMOperand;
55 
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
57 
58 class UnwindContext {
59   MCAsmParser &Parser;
60 
61   typedef SmallVector<SMLoc, 4> Locs;
62 
63   Locs FnStartLocs;
64   Locs CantUnwindLocs;
65   Locs PersonalityLocs;
66   Locs PersonalityIndexLocs;
67   Locs HandlerDataLocs;
68   int FPReg;
69 
70 public:
71   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
72 
73   bool hasFnStart() const { return !FnStartLocs.empty(); }
74   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76   bool hasPersonality() const {
77     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
78   }
79 
80   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
85 
86   void saveFPReg(int Reg) { FPReg = Reg; }
87   int getFPReg() const { return FPReg; }
88 
89   void emitFnStartLocNotes() const {
90     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
91          FI != FE; ++FI)
92       Parser.Note(*FI, ".fnstart was specified here");
93   }
94   void emitCantUnwindLocNotes() const {
95     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
97       Parser.Note(*UI, ".cantunwind was specified here");
98   }
99   void emitHandlerDataLocNotes() const {
100     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
102       Parser.Note(*HI, ".handlerdata was specified here");
103   }
104   void emitPersonalityLocNotes() const {
105     for (Locs::const_iterator PI = PersonalityLocs.begin(),
106                               PE = PersonalityLocs.end(),
107                               PII = PersonalityIndexLocs.begin(),
108                               PIE = PersonalityIndexLocs.end();
109          PI != PE || PII != PIE;) {
110       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111         Parser.Note(*PI++, ".personality was specified here");
112       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113         Parser.Note(*PII++, ".personalityindex was specified here");
114       else
115         llvm_unreachable(".personality and .personalityindex cannot be "
116                          "at the same location");
117     }
118   }
119 
120   void reset() {
121     FnStartLocs = Locs();
122     CantUnwindLocs = Locs();
123     PersonalityLocs = Locs();
124     HandlerDataLocs = Locs();
125     PersonalityIndexLocs = Locs();
126     FPReg = ARM::SP;
127   }
128 };
129 
130 class ARMAsmParser : public MCTargetAsmParser {
131   MCSubtargetInfo &STI;
132   MCAsmParser &Parser;
133   const MCInstrInfo &MII;
134   const MCRegisterInfo *MRI;
135   UnwindContext UC;
136 
137   ARMTargetStreamer &getTargetStreamer() {
138     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
139     return static_cast<ARMTargetStreamer &>(TS);
140   }
141 
142   // Map of register aliases registers via the .req directive.
143   StringMap<unsigned> RegisterReqs;
144 
145   bool NextSymbolIsThumb;
146 
147   struct {
148     ARMCC::CondCodes Cond;    // Condition for IT block.
149     unsigned Mask:4;          // Condition mask for instructions.
150                               // Starting at first 1 (from lsb).
151                               //   '1'  condition as indicated in IT.
152                               //   '0'  inverse of condition (else).
153                               // Count of instructions in IT block is
154                               // 4 - trailingzeroes(mask)
155 
156     bool FirstCond;           // Explicit flag for when we're parsing the
157                               // First instruction in the IT block. It's
158                               // implied in the mask, so needs special
159                               // handling.
160 
161     unsigned CurPosition;     // Current position in parsing of IT
162                               // block. In range [0,3]. Initialized
163                               // according to count of instructions in block.
164                               // ~0U if no active IT block.
165   } ITState;
166   bool inITBlock() { return ITState.CurPosition != ~0U;}
167   void forwardITPosition() {
168     if (!inITBlock()) return;
169     // Move to the next instruction in the IT block, if there is one. If not,
170     // mark the block as done.
171     unsigned TZ = countTrailingZeros(ITState.Mask);
172     if (++ITState.CurPosition == 5 - TZ)
173       ITState.CurPosition = ~0U; // Done with the IT block after this.
174   }
175 
176 
177   MCAsmParser &getParser() const { return Parser; }
178   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
179 
180   void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
181     return Parser.Note(L, Msg, Ranges);
182   }
183   bool Warning(SMLoc L, const Twine &Msg,
184                ArrayRef<SMRange> Ranges = None) {
185     return Parser.Warning(L, Msg, Ranges);
186   }
187   bool Error(SMLoc L, const Twine &Msg,
188              ArrayRef<SMRange> Ranges = None) {
189     return Parser.Error(L, Msg, Ranges);
190   }
191 
192   int tryParseRegister();
193   bool tryParseRegisterWithWriteBack(OperandVector &);
194   int tryParseShiftRegister(OperandVector &);
195   bool parseRegisterList(OperandVector &);
196   bool parseMemory(OperandVector &);
197   bool parseOperand(OperandVector &, StringRef Mnemonic);
198   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
199   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
200                               unsigned &ShiftAmount);
201   bool parseLiteralValues(unsigned Size, SMLoc L);
202   bool parseDirectiveThumb(SMLoc L);
203   bool parseDirectiveARM(SMLoc L);
204   bool parseDirectiveThumbFunc(SMLoc L);
205   bool parseDirectiveCode(SMLoc L);
206   bool parseDirectiveSyntax(SMLoc L);
207   bool parseDirectiveReq(StringRef Name, SMLoc L);
208   bool parseDirectiveUnreq(SMLoc L);
209   bool parseDirectiveArch(SMLoc L);
210   bool parseDirectiveEabiAttr(SMLoc L);
211   bool parseDirectiveCPU(SMLoc L);
212   bool parseDirectiveFPU(SMLoc L);
213   bool parseDirectiveFnStart(SMLoc L);
214   bool parseDirectiveFnEnd(SMLoc L);
215   bool parseDirectiveCantUnwind(SMLoc L);
216   bool parseDirectivePersonality(SMLoc L);
217   bool parseDirectiveHandlerData(SMLoc L);
218   bool parseDirectiveSetFP(SMLoc L);
219   bool parseDirectivePad(SMLoc L);
220   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
221   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
222   bool parseDirectiveLtorg(SMLoc L);
223   bool parseDirectiveEven(SMLoc L);
224   bool parseDirectivePersonalityIndex(SMLoc L);
225   bool parseDirectiveUnwindRaw(SMLoc L);
226   bool parseDirectiveTLSDescSeq(SMLoc L);
227   bool parseDirectiveMovSP(SMLoc L);
228   bool parseDirectiveObjectArch(SMLoc L);
229   bool parseDirectiveArchExtension(SMLoc L);
230   bool parseDirectiveAlign(SMLoc L);
231   bool parseDirectiveThumbSet(SMLoc L);
232 
233   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
234                           bool &CarrySetting, unsigned &ProcessorIMod,
235                           StringRef &ITMask);
236   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
237                              bool &CanAcceptCarrySet,
238                              bool &CanAcceptPredicationCode);
239 
240   bool isThumb() const {
241     // FIXME: Can tablegen auto-generate this?
242     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
243   }
244   bool isThumbOne() const {
245     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
246   }
247   bool isThumbTwo() const {
248     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
249   }
250   bool hasThumb() const {
251     return STI.getFeatureBits() & ARM::HasV4TOps;
252   }
253   bool hasV6Ops() const {
254     return STI.getFeatureBits() & ARM::HasV6Ops;
255   }
256   bool hasV6MOps() const {
257     return STI.getFeatureBits() & ARM::HasV6MOps;
258   }
259   bool hasV7Ops() const {
260     return STI.getFeatureBits() & ARM::HasV7Ops;
261   }
262   bool hasV8Ops() const {
263     return STI.getFeatureBits() & ARM::HasV8Ops;
264   }
265   bool hasARM() const {
266     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
267   }
268 
269   void SwitchMode() {
270     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
271     setAvailableFeatures(FB);
272   }
273   bool isMClass() const {
274     return STI.getFeatureBits() & ARM::FeatureMClass;
275   }
276 
277   /// @name Auto-generated Match Functions
278   /// {
279 
280 #define GET_ASSEMBLER_HEADER
281 #include "ARMGenAsmMatcher.inc"
282 
283   /// }
284 
285   OperandMatchResultTy parseITCondCode(OperandVector &);
286   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
287   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
288   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
289   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
290   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
291   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
292   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
293   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
294                                    int High);
295   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
296     return parsePKHImm(O, "lsl", 0, 31);
297   }
298   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
299     return parsePKHImm(O, "asr", 1, 32);
300   }
301   OperandMatchResultTy parseSetEndImm(OperandVector &);
302   OperandMatchResultTy parseShifterImm(OperandVector &);
303   OperandMatchResultTy parseRotImm(OperandVector &);
304   OperandMatchResultTy parseBitfield(OperandVector &);
305   OperandMatchResultTy parsePostIdxReg(OperandVector &);
306   OperandMatchResultTy parseAM3Offset(OperandVector &);
307   OperandMatchResultTy parseFPImm(OperandVector &);
308   OperandMatchResultTy parseVectorList(OperandVector &);
309   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
310                                        SMLoc &EndLoc);
311 
312   // Asm Match Converter Methods
313   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
314   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
315 
316   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
317   bool processInstruction(MCInst &Inst, const OperandVector &Ops);
318   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
319   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
320 
321 public:
322   enum ARMMatchResultTy {
323     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
324     Match_RequiresNotITBlock,
325     Match_RequiresV6,
326     Match_RequiresThumb2,
327 #define GET_OPERAND_DIAGNOSTIC_TYPES
328 #include "ARMGenAsmMatcher.inc"
329 
330   };
331 
332   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
333                const MCInstrInfo &MII,
334                const MCTargetOptions &Options)
335       : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
336     MCAsmParserExtension::Initialize(_Parser);
337 
338     // Cache the MCRegisterInfo.
339     MRI = getContext().getRegisterInfo();
340 
341     // Initialize the set of available features.
342     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
343 
344     // Not in an ITBlock to start with.
345     ITState.CurPosition = ~0U;
346 
347     NextSymbolIsThumb = false;
348   }
349 
350   // Implementation of the MCTargetAsmParser interface:
351   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
352   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
353                         SMLoc NameLoc, OperandVector &Operands) override;
354   bool ParseDirective(AsmToken DirectiveID) override;
355 
356   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
357                                       unsigned Kind) override;
358   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
359 
360   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
361                                OperandVector &Operands, MCStreamer &Out,
362                                unsigned &ErrorInfo,
363                                bool MatchingInlineAsm) override;
364   void onLabelParsed(MCSymbol *Symbol) override;
365 };
366 } // end anonymous namespace
367 
368 namespace {
369 
370 /// ARMOperand - Instances of this class represent a parsed ARM machine
371 /// operand.
372 class ARMOperand : public MCParsedAsmOperand {
373   enum KindTy {
374     k_CondCode,
375     k_CCOut,
376     k_ITCondMask,
377     k_CoprocNum,
378     k_CoprocReg,
379     k_CoprocOption,
380     k_Immediate,
381     k_MemBarrierOpt,
382     k_InstSyncBarrierOpt,
383     k_Memory,
384     k_PostIndexRegister,
385     k_MSRMask,
386     k_ProcIFlags,
387     k_VectorIndex,
388     k_Register,
389     k_RegisterList,
390     k_DPRRegisterList,
391     k_SPRRegisterList,
392     k_VectorList,
393     k_VectorListAllLanes,
394     k_VectorListIndexed,
395     k_ShiftedRegister,
396     k_ShiftedImmediate,
397     k_ShifterImmediate,
398     k_RotateImmediate,
399     k_BitfieldDescriptor,
400     k_Token
401   } Kind;
402 
403   SMLoc StartLoc, EndLoc, AlignmentLoc;
404   SmallVector<unsigned, 8> Registers;
405 
406   struct CCOp {
407     ARMCC::CondCodes Val;
408   };
409 
410   struct CopOp {
411     unsigned Val;
412   };
413 
414   struct CoprocOptionOp {
415     unsigned Val;
416   };
417 
418   struct ITMaskOp {
419     unsigned Mask:4;
420   };
421 
422   struct MBOptOp {
423     ARM_MB::MemBOpt Val;
424   };
425 
426   struct ISBOptOp {
427     ARM_ISB::InstSyncBOpt Val;
428   };
429 
430   struct IFlagsOp {
431     ARM_PROC::IFlags Val;
432   };
433 
434   struct MMaskOp {
435     unsigned Val;
436   };
437 
438   struct TokOp {
439     const char *Data;
440     unsigned Length;
441   };
442 
443   struct RegOp {
444     unsigned RegNum;
445   };
446 
447   // A vector register list is a sequential list of 1 to 4 registers.
448   struct VectorListOp {
449     unsigned RegNum;
450     unsigned Count;
451     unsigned LaneIndex;
452     bool isDoubleSpaced;
453   };
454 
455   struct VectorIndexOp {
456     unsigned Val;
457   };
458 
459   struct ImmOp {
460     const MCExpr *Val;
461   };
462 
463   /// Combined record for all forms of ARM address expressions.
464   struct MemoryOp {
465     unsigned BaseRegNum;
466     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
467     // was specified.
468     const MCConstantExpr *OffsetImm;  // Offset immediate value
469     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
470     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
471     unsigned ShiftImm;        // shift for OffsetReg.
472     unsigned Alignment;       // 0 = no alignment specified
473     // n = alignment in bytes (2, 4, 8, 16, or 32)
474     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
475   };
476 
477   struct PostIdxRegOp {
478     unsigned RegNum;
479     bool isAdd;
480     ARM_AM::ShiftOpc ShiftTy;
481     unsigned ShiftImm;
482   };
483 
484   struct ShifterImmOp {
485     bool isASR;
486     unsigned Imm;
487   };
488 
489   struct RegShiftedRegOp {
490     ARM_AM::ShiftOpc ShiftTy;
491     unsigned SrcReg;
492     unsigned ShiftReg;
493     unsigned ShiftImm;
494   };
495 
496   struct RegShiftedImmOp {
497     ARM_AM::ShiftOpc ShiftTy;
498     unsigned SrcReg;
499     unsigned ShiftImm;
500   };
501 
502   struct RotImmOp {
503     unsigned Imm;
504   };
505 
506   struct BitfieldOp {
507     unsigned LSB;
508     unsigned Width;
509   };
510 
511   union {
512     struct CCOp CC;
513     struct CopOp Cop;
514     struct CoprocOptionOp CoprocOption;
515     struct MBOptOp MBOpt;
516     struct ISBOptOp ISBOpt;
517     struct ITMaskOp ITMask;
518     struct IFlagsOp IFlags;
519     struct MMaskOp MMask;
520     struct TokOp Tok;
521     struct RegOp Reg;
522     struct VectorListOp VectorList;
523     struct VectorIndexOp VectorIndex;
524     struct ImmOp Imm;
525     struct MemoryOp Memory;
526     struct PostIdxRegOp PostIdxReg;
527     struct ShifterImmOp ShifterImm;
528     struct RegShiftedRegOp RegShiftedReg;
529     struct RegShiftedImmOp RegShiftedImm;
530     struct RotImmOp RotImm;
531     struct BitfieldOp Bitfield;
532   };
533 
534 public:
535   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
536   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
537     Kind = o.Kind;
538     StartLoc = o.StartLoc;
539     EndLoc = o.EndLoc;
540     switch (Kind) {
541     case k_CondCode:
542       CC = o.CC;
543       break;
544     case k_ITCondMask:
545       ITMask = o.ITMask;
546       break;
547     case k_Token:
548       Tok = o.Tok;
549       break;
550     case k_CCOut:
551     case k_Register:
552       Reg = o.Reg;
553       break;
554     case k_RegisterList:
555     case k_DPRRegisterList:
556     case k_SPRRegisterList:
557       Registers = o.Registers;
558       break;
559     case k_VectorList:
560     case k_VectorListAllLanes:
561     case k_VectorListIndexed:
562       VectorList = o.VectorList;
563       break;
564     case k_CoprocNum:
565     case k_CoprocReg:
566       Cop = o.Cop;
567       break;
568     case k_CoprocOption:
569       CoprocOption = o.CoprocOption;
570       break;
571     case k_Immediate:
572       Imm = o.Imm;
573       break;
574     case k_MemBarrierOpt:
575       MBOpt = o.MBOpt;
576       break;
577     case k_InstSyncBarrierOpt:
578       ISBOpt = o.ISBOpt;
579     case k_Memory:
580       Memory = o.Memory;
581       break;
582     case k_PostIndexRegister:
583       PostIdxReg = o.PostIdxReg;
584       break;
585     case k_MSRMask:
586       MMask = o.MMask;
587       break;
588     case k_ProcIFlags:
589       IFlags = o.IFlags;
590       break;
591     case k_ShifterImmediate:
592       ShifterImm = o.ShifterImm;
593       break;
594     case k_ShiftedRegister:
595       RegShiftedReg = o.RegShiftedReg;
596       break;
597     case k_ShiftedImmediate:
598       RegShiftedImm = o.RegShiftedImm;
599       break;
600     case k_RotateImmediate:
601       RotImm = o.RotImm;
602       break;
603     case k_BitfieldDescriptor:
604       Bitfield = o.Bitfield;
605       break;
606     case k_VectorIndex:
607       VectorIndex = o.VectorIndex;
608       break;
609     }
610   }
611 
612   /// getStartLoc - Get the location of the first token of this operand.
613   SMLoc getStartLoc() const override { return StartLoc; }
614   /// getEndLoc - Get the location of the last token of this operand.
615   SMLoc getEndLoc() const override { return EndLoc; }
616   /// getLocRange - Get the range between the first and last token of this
617   /// operand.
618   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
619 
620   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
621   SMLoc getAlignmentLoc() const {
622     assert(Kind == k_Memory && "Invalid access!");
623     return AlignmentLoc;
624   }
625 
626   ARMCC::CondCodes getCondCode() const {
627     assert(Kind == k_CondCode && "Invalid access!");
628     return CC.Val;
629   }
630 
631   unsigned getCoproc() const {
632     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
633     return Cop.Val;
634   }
635 
636   StringRef getToken() const {
637     assert(Kind == k_Token && "Invalid access!");
638     return StringRef(Tok.Data, Tok.Length);
639   }
640 
641   unsigned getReg() const override {
642     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
643     return Reg.RegNum;
644   }
645 
646   const SmallVectorImpl<unsigned> &getRegList() const {
647     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
648             Kind == k_SPRRegisterList) && "Invalid access!");
649     return Registers;
650   }
651 
652   const MCExpr *getImm() const {
653     assert(isImm() && "Invalid access!");
654     return Imm.Val;
655   }
656 
657   unsigned getVectorIndex() const {
658     assert(Kind == k_VectorIndex && "Invalid access!");
659     return VectorIndex.Val;
660   }
661 
662   ARM_MB::MemBOpt getMemBarrierOpt() const {
663     assert(Kind == k_MemBarrierOpt && "Invalid access!");
664     return MBOpt.Val;
665   }
666 
667   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
668     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
669     return ISBOpt.Val;
670   }
671 
672   ARM_PROC::IFlags getProcIFlags() const {
673     assert(Kind == k_ProcIFlags && "Invalid access!");
674     return IFlags.Val;
675   }
676 
677   unsigned getMSRMask() const {
678     assert(Kind == k_MSRMask && "Invalid access!");
679     return MMask.Val;
680   }
681 
682   bool isCoprocNum() const { return Kind == k_CoprocNum; }
683   bool isCoprocReg() const { return Kind == k_CoprocReg; }
684   bool isCoprocOption() const { return Kind == k_CoprocOption; }
685   bool isCondCode() const { return Kind == k_CondCode; }
686   bool isCCOut() const { return Kind == k_CCOut; }
687   bool isITMask() const { return Kind == k_ITCondMask; }
688   bool isITCondCode() const { return Kind == k_CondCode; }
689   bool isImm() const override { return Kind == k_Immediate; }
690   // checks whether this operand is an unsigned offset which fits is a field
691   // of specified width and scaled by a specific number of bits
692   template<unsigned width, unsigned scale>
693   bool isUnsignedOffset() const {
694     if (!isImm()) return false;
695     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
696     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
697       int64_t Val = CE->getValue();
698       int64_t Align = 1LL << scale;
699       int64_t Max = Align * ((1LL << width) - 1);
700       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
701     }
702     return false;
703   }
704   // checks whether this operand is an signed offset which fits is a field
705   // of specified width and scaled by a specific number of bits
706   template<unsigned width, unsigned scale>
707   bool isSignedOffset() const {
708     if (!isImm()) return false;
709     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
710     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
711       int64_t Val = CE->getValue();
712       int64_t Align = 1LL << scale;
713       int64_t Max = Align * ((1LL << (width-1)) - 1);
714       int64_t Min = -Align * (1LL << (width-1));
715       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
716     }
717     return false;
718   }
719 
720   // checks whether this operand is a memory operand computed as an offset
721   // applied to PC. the offset may have 8 bits of magnitude and is represented
722   // with two bits of shift. textually it may be either [pc, #imm], #imm or
723   // relocable expression...
724   bool isThumbMemPC() const {
725     int64_t Val = 0;
726     if (isImm()) {
727       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
728       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
729       if (!CE) return false;
730       Val = CE->getValue();
731     }
732     else if (isMem()) {
733       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
734       if(Memory.BaseRegNum != ARM::PC) return false;
735       Val = Memory.OffsetImm->getValue();
736     }
737     else return false;
738     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
739   }
740   bool isFPImm() const {
741     if (!isImm()) return false;
742     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743     if (!CE) return false;
744     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
745     return Val != -1;
746   }
747   bool isFBits16() const {
748     if (!isImm()) return false;
749     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
750     if (!CE) return false;
751     int64_t Value = CE->getValue();
752     return Value >= 0 && Value <= 16;
753   }
754   bool isFBits32() const {
755     if (!isImm()) return false;
756     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
757     if (!CE) return false;
758     int64_t Value = CE->getValue();
759     return Value >= 1 && Value <= 32;
760   }
761   bool isImm8s4() const {
762     if (!isImm()) return false;
763     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764     if (!CE) return false;
765     int64_t Value = CE->getValue();
766     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
767   }
768   bool isImm0_1020s4() const {
769     if (!isImm()) return false;
770     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771     if (!CE) return false;
772     int64_t Value = CE->getValue();
773     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
774   }
775   bool isImm0_508s4() const {
776     if (!isImm()) return false;
777     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778     if (!CE) return false;
779     int64_t Value = CE->getValue();
780     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
781   }
782   bool isImm0_508s4Neg() const {
783     if (!isImm()) return false;
784     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785     if (!CE) return false;
786     int64_t Value = -CE->getValue();
787     // explicitly exclude zero. we want that to use the normal 0_508 version.
788     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
789   }
790   bool isImm0_239() const {
791     if (!isImm()) return false;
792     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
793     if (!CE) return false;
794     int64_t Value = CE->getValue();
795     return Value >= 0 && Value < 240;
796   }
797   bool isImm0_255() const {
798     if (!isImm()) return false;
799     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
800     if (!CE) return false;
801     int64_t Value = CE->getValue();
802     return Value >= 0 && Value < 256;
803   }
804   bool isImm0_4095() const {
805     if (!isImm()) return false;
806     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807     if (!CE) return false;
808     int64_t Value = CE->getValue();
809     return Value >= 0 && Value < 4096;
810   }
811   bool isImm0_4095Neg() const {
812     if (!isImm()) return false;
813     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
814     if (!CE) return false;
815     int64_t Value = -CE->getValue();
816     return Value > 0 && Value < 4096;
817   }
818   bool isImm0_1() const {
819     if (!isImm()) return false;
820     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
821     if (!CE) return false;
822     int64_t Value = CE->getValue();
823     return Value >= 0 && Value < 2;
824   }
825   bool isImm0_3() const {
826     if (!isImm()) return false;
827     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
828     if (!CE) return false;
829     int64_t Value = CE->getValue();
830     return Value >= 0 && Value < 4;
831   }
832   bool isImm0_7() const {
833     if (!isImm()) return false;
834     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
835     if (!CE) return false;
836     int64_t Value = CE->getValue();
837     return Value >= 0 && Value < 8;
838   }
839   bool isImm0_15() const {
840     if (!isImm()) return false;
841     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
842     if (!CE) return false;
843     int64_t Value = CE->getValue();
844     return Value >= 0 && Value < 16;
845   }
846   bool isImm0_31() const {
847     if (!isImm()) return false;
848     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
849     if (!CE) return false;
850     int64_t Value = CE->getValue();
851     return Value >= 0 && Value < 32;
852   }
853   bool isImm0_63() const {
854     if (!isImm()) return false;
855     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
856     if (!CE) return false;
857     int64_t Value = CE->getValue();
858     return Value >= 0 && Value < 64;
859   }
860   bool isImm8() const {
861     if (!isImm()) return false;
862     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
863     if (!CE) return false;
864     int64_t Value = CE->getValue();
865     return Value == 8;
866   }
867   bool isImm16() const {
868     if (!isImm()) return false;
869     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
870     if (!CE) return false;
871     int64_t Value = CE->getValue();
872     return Value == 16;
873   }
874   bool isImm32() const {
875     if (!isImm()) return false;
876     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
877     if (!CE) return false;
878     int64_t Value = CE->getValue();
879     return Value == 32;
880   }
881   bool isShrImm8() const {
882     if (!isImm()) return false;
883     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884     if (!CE) return false;
885     int64_t Value = CE->getValue();
886     return Value > 0 && Value <= 8;
887   }
888   bool isShrImm16() const {
889     if (!isImm()) return false;
890     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
891     if (!CE) return false;
892     int64_t Value = CE->getValue();
893     return Value > 0 && Value <= 16;
894   }
895   bool isShrImm32() const {
896     if (!isImm()) return false;
897     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
898     if (!CE) return false;
899     int64_t Value = CE->getValue();
900     return Value > 0 && Value <= 32;
901   }
902   bool isShrImm64() const {
903     if (!isImm()) return false;
904     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
905     if (!CE) return false;
906     int64_t Value = CE->getValue();
907     return Value > 0 && Value <= 64;
908   }
909   bool isImm1_7() const {
910     if (!isImm()) return false;
911     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
912     if (!CE) return false;
913     int64_t Value = CE->getValue();
914     return Value > 0 && Value < 8;
915   }
916   bool isImm1_15() const {
917     if (!isImm()) return false;
918     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
919     if (!CE) return false;
920     int64_t Value = CE->getValue();
921     return Value > 0 && Value < 16;
922   }
923   bool isImm1_31() const {
924     if (!isImm()) return false;
925     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
926     if (!CE) return false;
927     int64_t Value = CE->getValue();
928     return Value > 0 && Value < 32;
929   }
930   bool isImm1_16() const {
931     if (!isImm()) return false;
932     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933     if (!CE) return false;
934     int64_t Value = CE->getValue();
935     return Value > 0 && Value < 17;
936   }
937   bool isImm1_32() const {
938     if (!isImm()) return false;
939     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940     if (!CE) return false;
941     int64_t Value = CE->getValue();
942     return Value > 0 && Value < 33;
943   }
944   bool isImm0_32() const {
945     if (!isImm()) return false;
946     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
947     if (!CE) return false;
948     int64_t Value = CE->getValue();
949     return Value >= 0 && Value < 33;
950   }
951   bool isImm0_65535() const {
952     if (!isImm()) return false;
953     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
954     if (!CE) return false;
955     int64_t Value = CE->getValue();
956     return Value >= 0 && Value < 65536;
957   }
958   bool isImm256_65535Expr() const {
959     if (!isImm()) return false;
960     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
961     // If it's not a constant expression, it'll generate a fixup and be
962     // handled later.
963     if (!CE) return true;
964     int64_t Value = CE->getValue();
965     return Value >= 256 && Value < 65536;
966   }
967   bool isImm0_65535Expr() const {
968     if (!isImm()) return false;
969     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
970     // If it's not a constant expression, it'll generate a fixup and be
971     // handled later.
972     if (!CE) return true;
973     int64_t Value = CE->getValue();
974     return Value >= 0 && Value < 65536;
975   }
976   bool isImm24bit() const {
977     if (!isImm()) return false;
978     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
979     if (!CE) return false;
980     int64_t Value = CE->getValue();
981     return Value >= 0 && Value <= 0xffffff;
982   }
983   bool isImmThumbSR() const {
984     if (!isImm()) return false;
985     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
986     if (!CE) return false;
987     int64_t Value = CE->getValue();
988     return Value > 0 && Value < 33;
989   }
990   bool isPKHLSLImm() const {
991     if (!isImm()) return false;
992     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
993     if (!CE) return false;
994     int64_t Value = CE->getValue();
995     return Value >= 0 && Value < 32;
996   }
997   bool isPKHASRImm() const {
998     if (!isImm()) return false;
999     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1000     if (!CE) return false;
1001     int64_t Value = CE->getValue();
1002     return Value > 0 && Value <= 32;
1003   }
1004   bool isAdrLabel() const {
1005     // If we have an immediate that's not a constant, treat it as a label
1006     // reference needing a fixup. If it is a constant, but it can't fit
1007     // into shift immediate encoding, we reject it.
1008     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1009     else return (isARMSOImm() || isARMSOImmNeg());
1010   }
1011   bool isARMSOImm() const {
1012     if (!isImm()) return false;
1013     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1014     if (!CE) return false;
1015     int64_t Value = CE->getValue();
1016     return ARM_AM::getSOImmVal(Value) != -1;
1017   }
1018   bool isARMSOImmNot() const {
1019     if (!isImm()) return false;
1020     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1021     if (!CE) return false;
1022     int64_t Value = CE->getValue();
1023     return ARM_AM::getSOImmVal(~Value) != -1;
1024   }
1025   bool isARMSOImmNeg() const {
1026     if (!isImm()) return false;
1027     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1028     if (!CE) return false;
1029     int64_t Value = CE->getValue();
1030     // Only use this when not representable as a plain so_imm.
1031     return ARM_AM::getSOImmVal(Value) == -1 &&
1032       ARM_AM::getSOImmVal(-Value) != -1;
1033   }
1034   bool isT2SOImm() const {
1035     if (!isImm()) return false;
1036     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1037     if (!CE) return false;
1038     int64_t Value = CE->getValue();
1039     return ARM_AM::getT2SOImmVal(Value) != -1;
1040   }
1041   bool isT2SOImmNot() const {
1042     if (!isImm()) return false;
1043     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1044     if (!CE) return false;
1045     int64_t Value = CE->getValue();
1046     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1047       ARM_AM::getT2SOImmVal(~Value) != -1;
1048   }
1049   bool isT2SOImmNeg() const {
1050     if (!isImm()) return false;
1051     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1052     if (!CE) return false;
1053     int64_t Value = CE->getValue();
1054     // Only use this when not representable as a plain so_imm.
1055     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1056       ARM_AM::getT2SOImmVal(-Value) != -1;
1057   }
1058   bool isSetEndImm() const {
1059     if (!isImm()) return false;
1060     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1061     if (!CE) return false;
1062     int64_t Value = CE->getValue();
1063     return Value == 1 || Value == 0;
1064   }
1065   bool isReg() const override { return Kind == k_Register; }
1066   bool isRegList() const { return Kind == k_RegisterList; }
1067   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1068   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1069   bool isToken() const override { return Kind == k_Token; }
1070   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1071   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1072   bool isMem() const override { return Kind == k_Memory; }
1073   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1074   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1075   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1076   bool isRotImm() const { return Kind == k_RotateImmediate; }
1077   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1078   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1079   bool isPostIdxReg() const {
1080     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1081   }
1082   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1083     if (!isMem())
1084       return false;
1085     // No offset of any kind.
1086     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1087      (alignOK || Memory.Alignment == Alignment);
1088   }
1089   bool isMemPCRelImm12() const {
1090     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1091       return false;
1092     // Base register must be PC.
1093     if (Memory.BaseRegNum != ARM::PC)
1094       return false;
1095     // Immediate offset in range [-4095, 4095].
1096     if (!Memory.OffsetImm) return true;
1097     int64_t Val = Memory.OffsetImm->getValue();
1098     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1099   }
1100   bool isAlignedMemory() const {
1101     return isMemNoOffset(true);
1102   }
1103   bool isAlignedMemoryNone() const {
1104     return isMemNoOffset(false, 0);
1105   }
1106   bool isDupAlignedMemoryNone() const {
1107     return isMemNoOffset(false, 0);
1108   }
1109   bool isAlignedMemory16() const {
1110     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1111       return true;
1112     return isMemNoOffset(false, 0);
1113   }
1114   bool isDupAlignedMemory16() const {
1115     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1116       return true;
1117     return isMemNoOffset(false, 0);
1118   }
1119   bool isAlignedMemory32() const {
1120     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1121       return true;
1122     return isMemNoOffset(false, 0);
1123   }
1124   bool isDupAlignedMemory32() const {
1125     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1126       return true;
1127     return isMemNoOffset(false, 0);
1128   }
1129   bool isAlignedMemory64() const {
1130     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1131       return true;
1132     return isMemNoOffset(false, 0);
1133   }
1134   bool isDupAlignedMemory64() const {
1135     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1136       return true;
1137     return isMemNoOffset(false, 0);
1138   }
1139   bool isAlignedMemory64or128() const {
1140     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1141       return true;
1142     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1143       return true;
1144     return isMemNoOffset(false, 0);
1145   }
1146   bool isDupAlignedMemory64or128() const {
1147     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1148       return true;
1149     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1150       return true;
1151     return isMemNoOffset(false, 0);
1152   }
1153   bool isAlignedMemory64or128or256() const {
1154     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1155       return true;
1156     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1157       return true;
1158     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1159       return true;
1160     return isMemNoOffset(false, 0);
1161   }
1162   bool isAddrMode2() const {
1163     if (!isMem() || Memory.Alignment != 0) return false;
1164     // Check for register offset.
1165     if (Memory.OffsetRegNum) return true;
1166     // Immediate offset in range [-4095, 4095].
1167     if (!Memory.OffsetImm) return true;
1168     int64_t Val = Memory.OffsetImm->getValue();
1169     return Val > -4096 && Val < 4096;
1170   }
1171   bool isAM2OffsetImm() const {
1172     if (!isImm()) return false;
1173     // Immediate offset in range [-4095, 4095].
1174     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1175     if (!CE) return false;
1176     int64_t Val = CE->getValue();
1177     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1178   }
1179   bool isAddrMode3() const {
1180     // If we have an immediate that's not a constant, treat it as a label
1181     // reference needing a fixup. If it is a constant, it's something else
1182     // and we reject it.
1183     if (isImm() && !isa<MCConstantExpr>(getImm()))
1184       return true;
1185     if (!isMem() || Memory.Alignment != 0) return false;
1186     // No shifts are legal for AM3.
1187     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1188     // Check for register offset.
1189     if (Memory.OffsetRegNum) return true;
1190     // Immediate offset in range [-255, 255].
1191     if (!Memory.OffsetImm) return true;
1192     int64_t Val = Memory.OffsetImm->getValue();
1193     // The #-0 offset is encoded as INT32_MIN, and we have to check
1194     // for this too.
1195     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1196   }
1197   bool isAM3Offset() const {
1198     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1199       return false;
1200     if (Kind == k_PostIndexRegister)
1201       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1202     // Immediate offset in range [-255, 255].
1203     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1204     if (!CE) return false;
1205     int64_t Val = CE->getValue();
1206     // Special case, #-0 is INT32_MIN.
1207     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1208   }
1209   bool isAddrMode5() const {
1210     // If we have an immediate that's not a constant, treat it as a label
1211     // reference needing a fixup. If it is a constant, it's something else
1212     // and we reject it.
1213     if (isImm() && !isa<MCConstantExpr>(getImm()))
1214       return true;
1215     if (!isMem() || Memory.Alignment != 0) return false;
1216     // Check for register offset.
1217     if (Memory.OffsetRegNum) return false;
1218     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1219     if (!Memory.OffsetImm) return true;
1220     int64_t Val = Memory.OffsetImm->getValue();
1221     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1222       Val == INT32_MIN;
1223   }
1224   bool isMemTBB() const {
1225     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1226         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1227       return false;
1228     return true;
1229   }
1230   bool isMemTBH() const {
1231     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1232         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1233         Memory.Alignment != 0 )
1234       return false;
1235     return true;
1236   }
1237   bool isMemRegOffset() const {
1238     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1239       return false;
1240     return true;
1241   }
1242   bool isT2MemRegOffset() const {
1243     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1244         Memory.Alignment != 0)
1245       return false;
1246     // Only lsl #{0, 1, 2, 3} allowed.
1247     if (Memory.ShiftType == ARM_AM::no_shift)
1248       return true;
1249     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1250       return false;
1251     return true;
1252   }
1253   bool isMemThumbRR() const {
1254     // Thumb reg+reg addressing is simple. Just two registers, a base and
1255     // an offset. No shifts, negations or any other complicating factors.
1256     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1257         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1258       return false;
1259     return isARMLowRegister(Memory.BaseRegNum) &&
1260       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1261   }
1262   bool isMemThumbRIs4() const {
1263     if (!isMem() || Memory.OffsetRegNum != 0 ||
1264         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1265       return false;
1266     // Immediate offset, multiple of 4 in range [0, 124].
1267     if (!Memory.OffsetImm) return true;
1268     int64_t Val = Memory.OffsetImm->getValue();
1269     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1270   }
1271   bool isMemThumbRIs2() const {
1272     if (!isMem() || Memory.OffsetRegNum != 0 ||
1273         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1274       return false;
1275     // Immediate offset, multiple of 4 in range [0, 62].
1276     if (!Memory.OffsetImm) return true;
1277     int64_t Val = Memory.OffsetImm->getValue();
1278     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1279   }
1280   bool isMemThumbRIs1() const {
1281     if (!isMem() || Memory.OffsetRegNum != 0 ||
1282         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1283       return false;
1284     // Immediate offset in range [0, 31].
1285     if (!Memory.OffsetImm) return true;
1286     int64_t Val = Memory.OffsetImm->getValue();
1287     return Val >= 0 && Val <= 31;
1288   }
1289   bool isMemThumbSPI() const {
1290     if (!isMem() || Memory.OffsetRegNum != 0 ||
1291         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1292       return false;
1293     // Immediate offset, multiple of 4 in range [0, 1020].
1294     if (!Memory.OffsetImm) return true;
1295     int64_t Val = Memory.OffsetImm->getValue();
1296     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1297   }
1298   bool isMemImm8s4Offset() const {
1299     // If we have an immediate that's not a constant, treat it as a label
1300     // reference needing a fixup. If it is a constant, it's something else
1301     // and we reject it.
1302     if (isImm() && !isa<MCConstantExpr>(getImm()))
1303       return true;
1304     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1305       return false;
1306     // Immediate offset a multiple of 4 in range [-1020, 1020].
1307     if (!Memory.OffsetImm) return true;
1308     int64_t Val = Memory.OffsetImm->getValue();
1309     // Special case, #-0 is INT32_MIN.
1310     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1311   }
1312   bool isMemImm0_1020s4Offset() const {
1313     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1314       return false;
1315     // Immediate offset a multiple of 4 in range [0, 1020].
1316     if (!Memory.OffsetImm) return true;
1317     int64_t Val = Memory.OffsetImm->getValue();
1318     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1319   }
1320   bool isMemImm8Offset() const {
1321     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1322       return false;
1323     // Base reg of PC isn't allowed for these encodings.
1324     if (Memory.BaseRegNum == ARM::PC) return false;
1325     // Immediate offset in range [-255, 255].
1326     if (!Memory.OffsetImm) return true;
1327     int64_t Val = Memory.OffsetImm->getValue();
1328     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1329   }
1330   bool isMemPosImm8Offset() const {
1331     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1332       return false;
1333     // Immediate offset in range [0, 255].
1334     if (!Memory.OffsetImm) return true;
1335     int64_t Val = Memory.OffsetImm->getValue();
1336     return Val >= 0 && Val < 256;
1337   }
1338   bool isMemNegImm8Offset() const {
1339     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1340       return false;
1341     // Base reg of PC isn't allowed for these encodings.
1342     if (Memory.BaseRegNum == ARM::PC) return false;
1343     // Immediate offset in range [-255, -1].
1344     if (!Memory.OffsetImm) return false;
1345     int64_t Val = Memory.OffsetImm->getValue();
1346     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1347   }
1348   bool isMemUImm12Offset() const {
1349     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1350       return false;
1351     // Immediate offset in range [0, 4095].
1352     if (!Memory.OffsetImm) return true;
1353     int64_t Val = Memory.OffsetImm->getValue();
1354     return (Val >= 0 && Val < 4096);
1355   }
1356   bool isMemImm12Offset() const {
1357     // If we have an immediate that's not a constant, treat it as a label
1358     // reference needing a fixup. If it is a constant, it's something else
1359     // and we reject it.
1360     if (isImm() && !isa<MCConstantExpr>(getImm()))
1361       return true;
1362 
1363     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1364       return false;
1365     // Immediate offset in range [-4095, 4095].
1366     if (!Memory.OffsetImm) return true;
1367     int64_t Val = Memory.OffsetImm->getValue();
1368     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1369   }
1370   bool isPostIdxImm8() const {
1371     if (!isImm()) return false;
1372     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1373     if (!CE) return false;
1374     int64_t Val = CE->getValue();
1375     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1376   }
1377   bool isPostIdxImm8s4() const {
1378     if (!isImm()) return false;
1379     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1380     if (!CE) return false;
1381     int64_t Val = CE->getValue();
1382     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1383       (Val == INT32_MIN);
1384   }
1385 
1386   bool isMSRMask() const { return Kind == k_MSRMask; }
1387   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1388 
1389   // NEON operands.
1390   bool isSingleSpacedVectorList() const {
1391     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1392   }
1393   bool isDoubleSpacedVectorList() const {
1394     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1395   }
1396   bool isVecListOneD() const {
1397     if (!isSingleSpacedVectorList()) return false;
1398     return VectorList.Count == 1;
1399   }
1400 
1401   bool isVecListDPair() const {
1402     if (!isSingleSpacedVectorList()) return false;
1403     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1404               .contains(VectorList.RegNum));
1405   }
1406 
1407   bool isVecListThreeD() const {
1408     if (!isSingleSpacedVectorList()) return false;
1409     return VectorList.Count == 3;
1410   }
1411 
1412   bool isVecListFourD() const {
1413     if (!isSingleSpacedVectorList()) return false;
1414     return VectorList.Count == 4;
1415   }
1416 
1417   bool isVecListDPairSpaced() const {
1418     if (Kind != k_VectorList) return false;
1419     if (isSingleSpacedVectorList()) return false;
1420     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1421               .contains(VectorList.RegNum));
1422   }
1423 
1424   bool isVecListThreeQ() const {
1425     if (!isDoubleSpacedVectorList()) return false;
1426     return VectorList.Count == 3;
1427   }
1428 
1429   bool isVecListFourQ() const {
1430     if (!isDoubleSpacedVectorList()) return false;
1431     return VectorList.Count == 4;
1432   }
1433 
1434   bool isSingleSpacedVectorAllLanes() const {
1435     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1436   }
1437   bool isDoubleSpacedVectorAllLanes() const {
1438     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1439   }
1440   bool isVecListOneDAllLanes() const {
1441     if (!isSingleSpacedVectorAllLanes()) return false;
1442     return VectorList.Count == 1;
1443   }
1444 
1445   bool isVecListDPairAllLanes() const {
1446     if (!isSingleSpacedVectorAllLanes()) return false;
1447     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1448               .contains(VectorList.RegNum));
1449   }
1450 
1451   bool isVecListDPairSpacedAllLanes() const {
1452     if (!isDoubleSpacedVectorAllLanes()) return false;
1453     return VectorList.Count == 2;
1454   }
1455 
1456   bool isVecListThreeDAllLanes() const {
1457     if (!isSingleSpacedVectorAllLanes()) return false;
1458     return VectorList.Count == 3;
1459   }
1460 
1461   bool isVecListThreeQAllLanes() const {
1462     if (!isDoubleSpacedVectorAllLanes()) return false;
1463     return VectorList.Count == 3;
1464   }
1465 
1466   bool isVecListFourDAllLanes() const {
1467     if (!isSingleSpacedVectorAllLanes()) return false;
1468     return VectorList.Count == 4;
1469   }
1470 
1471   bool isVecListFourQAllLanes() const {
1472     if (!isDoubleSpacedVectorAllLanes()) return false;
1473     return VectorList.Count == 4;
1474   }
1475 
1476   bool isSingleSpacedVectorIndexed() const {
1477     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1478   }
1479   bool isDoubleSpacedVectorIndexed() const {
1480     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1481   }
1482   bool isVecListOneDByteIndexed() const {
1483     if (!isSingleSpacedVectorIndexed()) return false;
1484     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1485   }
1486 
1487   bool isVecListOneDHWordIndexed() const {
1488     if (!isSingleSpacedVectorIndexed()) return false;
1489     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1490   }
1491 
1492   bool isVecListOneDWordIndexed() const {
1493     if (!isSingleSpacedVectorIndexed()) return false;
1494     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1495   }
1496 
1497   bool isVecListTwoDByteIndexed() const {
1498     if (!isSingleSpacedVectorIndexed()) return false;
1499     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1500   }
1501 
1502   bool isVecListTwoDHWordIndexed() const {
1503     if (!isSingleSpacedVectorIndexed()) return false;
1504     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1505   }
1506 
1507   bool isVecListTwoQWordIndexed() const {
1508     if (!isDoubleSpacedVectorIndexed()) return false;
1509     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1510   }
1511 
1512   bool isVecListTwoQHWordIndexed() const {
1513     if (!isDoubleSpacedVectorIndexed()) return false;
1514     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1515   }
1516 
1517   bool isVecListTwoDWordIndexed() const {
1518     if (!isSingleSpacedVectorIndexed()) return false;
1519     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1520   }
1521 
1522   bool isVecListThreeDByteIndexed() const {
1523     if (!isSingleSpacedVectorIndexed()) return false;
1524     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1525   }
1526 
1527   bool isVecListThreeDHWordIndexed() const {
1528     if (!isSingleSpacedVectorIndexed()) return false;
1529     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1530   }
1531 
1532   bool isVecListThreeQWordIndexed() const {
1533     if (!isDoubleSpacedVectorIndexed()) return false;
1534     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1535   }
1536 
1537   bool isVecListThreeQHWordIndexed() const {
1538     if (!isDoubleSpacedVectorIndexed()) return false;
1539     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1540   }
1541 
1542   bool isVecListThreeDWordIndexed() const {
1543     if (!isSingleSpacedVectorIndexed()) return false;
1544     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1545   }
1546 
1547   bool isVecListFourDByteIndexed() const {
1548     if (!isSingleSpacedVectorIndexed()) return false;
1549     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1550   }
1551 
1552   bool isVecListFourDHWordIndexed() const {
1553     if (!isSingleSpacedVectorIndexed()) return false;
1554     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1555   }
1556 
1557   bool isVecListFourQWordIndexed() const {
1558     if (!isDoubleSpacedVectorIndexed()) return false;
1559     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1560   }
1561 
1562   bool isVecListFourQHWordIndexed() const {
1563     if (!isDoubleSpacedVectorIndexed()) return false;
1564     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1565   }
1566 
1567   bool isVecListFourDWordIndexed() const {
1568     if (!isSingleSpacedVectorIndexed()) return false;
1569     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1570   }
1571 
1572   bool isVectorIndex8() const {
1573     if (Kind != k_VectorIndex) return false;
1574     return VectorIndex.Val < 8;
1575   }
1576   bool isVectorIndex16() const {
1577     if (Kind != k_VectorIndex) return false;
1578     return VectorIndex.Val < 4;
1579   }
1580   bool isVectorIndex32() const {
1581     if (Kind != k_VectorIndex) return false;
1582     return VectorIndex.Val < 2;
1583   }
1584 
1585   bool isNEONi8splat() const {
1586     if (!isImm()) return false;
1587     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1588     // Must be a constant.
1589     if (!CE) return false;
1590     int64_t Value = CE->getValue();
1591     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1592     // value.
1593     return Value >= 0 && Value < 256;
1594   }
1595 
1596   bool isNEONi16splat() const {
1597     if (isNEONByteReplicate(2))
1598       return false; // Leave that for bytes replication and forbid by default.
1599     if (!isImm())
1600       return false;
1601     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602     // Must be a constant.
1603     if (!CE) return false;
1604     int64_t Value = CE->getValue();
1605     // i16 value in the range [0,255] or [0x0100, 0xff00]
1606     return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1607   }
1608 
1609   bool isNEONi32splat() const {
1610     if (isNEONByteReplicate(4))
1611       return false; // Leave that for bytes replication and forbid by default.
1612     if (!isImm())
1613       return false;
1614     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1615     // Must be a constant.
1616     if (!CE) return false;
1617     int64_t Value = CE->getValue();
1618     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1619     return (Value >= 0 && Value < 256) ||
1620       (Value >= 0x0100 && Value <= 0xff00) ||
1621       (Value >= 0x010000 && Value <= 0xff0000) ||
1622       (Value >= 0x01000000 && Value <= 0xff000000);
1623   }
1624 
1625   bool isNEONByteReplicate(unsigned NumBytes) const {
1626     if (!isImm())
1627       return false;
1628     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1629     // Must be a constant.
1630     if (!CE)
1631       return false;
1632     int64_t Value = CE->getValue();
1633     if (!Value)
1634       return false; // Don't bother with zero.
1635 
1636     unsigned char B = Value & 0xff;
1637     for (unsigned i = 1; i < NumBytes; ++i) {
1638       Value >>= 8;
1639       if ((Value & 0xff) != B)
1640         return false;
1641     }
1642     return true;
1643   }
1644   bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1645   bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1646   bool isNEONi32vmov() const {
1647     if (isNEONByteReplicate(4))
1648       return false; // Let it to be classified as byte-replicate case.
1649     if (!isImm())
1650       return false;
1651     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1652     // Must be a constant.
1653     if (!CE)
1654       return false;
1655     int64_t Value = CE->getValue();
1656     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1657     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1658     return (Value >= 0 && Value < 256) ||
1659       (Value >= 0x0100 && Value <= 0xff00) ||
1660       (Value >= 0x010000 && Value <= 0xff0000) ||
1661       (Value >= 0x01000000 && Value <= 0xff000000) ||
1662       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1663       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1664   }
1665   bool isNEONi32vmovNeg() const {
1666     if (!isImm()) return false;
1667     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668     // Must be a constant.
1669     if (!CE) return false;
1670     int64_t Value = ~CE->getValue();
1671     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1672     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1673     return (Value >= 0 && Value < 256) ||
1674       (Value >= 0x0100 && Value <= 0xff00) ||
1675       (Value >= 0x010000 && Value <= 0xff0000) ||
1676       (Value >= 0x01000000 && Value <= 0xff000000) ||
1677       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1678       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1679   }
1680 
1681   bool isNEONi64splat() const {
1682     if (!isImm()) return false;
1683     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1684     // Must be a constant.
1685     if (!CE) return false;
1686     uint64_t Value = CE->getValue();
1687     // i64 value with each byte being either 0 or 0xff.
1688     for (unsigned i = 0; i < 8; ++i)
1689       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1690     return true;
1691   }
1692 
1693   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1694     // Add as immediates when possible.  Null MCExpr = 0.
1695     if (!Expr)
1696       Inst.addOperand(MCOperand::CreateImm(0));
1697     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1698       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1699     else
1700       Inst.addOperand(MCOperand::CreateExpr(Expr));
1701   }
1702 
1703   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1704     assert(N == 2 && "Invalid number of operands!");
1705     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1706     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1707     Inst.addOperand(MCOperand::CreateReg(RegNum));
1708   }
1709 
1710   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1711     assert(N == 1 && "Invalid number of operands!");
1712     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1713   }
1714 
1715   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1716     assert(N == 1 && "Invalid number of operands!");
1717     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1718   }
1719 
1720   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1721     assert(N == 1 && "Invalid number of operands!");
1722     Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1723   }
1724 
1725   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1726     assert(N == 1 && "Invalid number of operands!");
1727     Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1728   }
1729 
1730   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1731     assert(N == 1 && "Invalid number of operands!");
1732     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1733   }
1734 
1735   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1736     assert(N == 1 && "Invalid number of operands!");
1737     Inst.addOperand(MCOperand::CreateReg(getReg()));
1738   }
1739 
1740   void addRegOperands(MCInst &Inst, unsigned N) const {
1741     assert(N == 1 && "Invalid number of operands!");
1742     Inst.addOperand(MCOperand::CreateReg(getReg()));
1743   }
1744 
1745   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1746     assert(N == 3 && "Invalid number of operands!");
1747     assert(isRegShiftedReg() &&
1748            "addRegShiftedRegOperands() on non-RegShiftedReg!");
1749     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1750     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1751     Inst.addOperand(MCOperand::CreateImm(
1752       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1753   }
1754 
1755   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1756     assert(N == 2 && "Invalid number of operands!");
1757     assert(isRegShiftedImm() &&
1758            "addRegShiftedImmOperands() on non-RegShiftedImm!");
1759     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1760     // Shift of #32 is encoded as 0 where permitted
1761     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1762     Inst.addOperand(MCOperand::CreateImm(
1763       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1764   }
1765 
1766   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1767     assert(N == 1 && "Invalid number of operands!");
1768     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1769                                          ShifterImm.Imm));
1770   }
1771 
1772   void addRegListOperands(MCInst &Inst, unsigned N) const {
1773     assert(N == 1 && "Invalid number of operands!");
1774     const SmallVectorImpl<unsigned> &RegList = getRegList();
1775     for (SmallVectorImpl<unsigned>::const_iterator
1776            I = RegList.begin(), E = RegList.end(); I != E; ++I)
1777       Inst.addOperand(MCOperand::CreateReg(*I));
1778   }
1779 
1780   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1781     addRegListOperands(Inst, N);
1782   }
1783 
1784   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1785     addRegListOperands(Inst, N);
1786   }
1787 
1788   void addRotImmOperands(MCInst &Inst, unsigned N) const {
1789     assert(N == 1 && "Invalid number of operands!");
1790     // Encoded as val>>3. The printer handles display as 8, 16, 24.
1791     Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1792   }
1793 
1794   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1795     assert(N == 1 && "Invalid number of operands!");
1796     // Munge the lsb/width into a bitfield mask.
1797     unsigned lsb = Bitfield.LSB;
1798     unsigned width = Bitfield.Width;
1799     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1800     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1801                       (32 - (lsb + width)));
1802     Inst.addOperand(MCOperand::CreateImm(Mask));
1803   }
1804 
1805   void addImmOperands(MCInst &Inst, unsigned N) const {
1806     assert(N == 1 && "Invalid number of operands!");
1807     addExpr(Inst, getImm());
1808   }
1809 
1810   void addFBits16Operands(MCInst &Inst, unsigned N) const {
1811     assert(N == 1 && "Invalid number of operands!");
1812     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1813     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1814   }
1815 
1816   void addFBits32Operands(MCInst &Inst, unsigned N) const {
1817     assert(N == 1 && "Invalid number of operands!");
1818     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1819     Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1820   }
1821 
1822   void addFPImmOperands(MCInst &Inst, unsigned N) const {
1823     assert(N == 1 && "Invalid number of operands!");
1824     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1825     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1826     Inst.addOperand(MCOperand::CreateImm(Val));
1827   }
1828 
1829   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1830     assert(N == 1 && "Invalid number of operands!");
1831     // FIXME: We really want to scale the value here, but the LDRD/STRD
1832     // instruction don't encode operands that way yet.
1833     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1834     Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1835   }
1836 
1837   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1838     assert(N == 1 && "Invalid number of operands!");
1839     // The immediate is scaled by four in the encoding and is stored
1840     // in the MCInst as such. Lop off the low two bits here.
1841     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1842     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1843   }
1844 
1845   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1846     assert(N == 1 && "Invalid number of operands!");
1847     // The immediate is scaled by four in the encoding and is stored
1848     // in the MCInst as such. Lop off the low two bits here.
1849     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1850     Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1851   }
1852 
1853   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1854     assert(N == 1 && "Invalid number of operands!");
1855     // The immediate is scaled by four in the encoding and is stored
1856     // in the MCInst as such. Lop off the low two bits here.
1857     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1858     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1859   }
1860 
1861   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1862     assert(N == 1 && "Invalid number of operands!");
1863     // The constant encodes as the immediate-1, and we store in the instruction
1864     // the bits as encoded, so subtract off one here.
1865     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1866     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1867   }
1868 
1869   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1870     assert(N == 1 && "Invalid number of operands!");
1871     // The constant encodes as the immediate-1, and we store in the instruction
1872     // the bits as encoded, so subtract off one here.
1873     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1874     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1875   }
1876 
1877   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1878     assert(N == 1 && "Invalid number of operands!");
1879     // The constant encodes as the immediate, except for 32, which encodes as
1880     // zero.
1881     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1882     unsigned Imm = CE->getValue();
1883     Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1884   }
1885 
1886   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1887     assert(N == 1 && "Invalid number of operands!");
1888     // An ASR value of 32 encodes as 0, so that's how we want to add it to
1889     // the instruction as well.
1890     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1891     int Val = CE->getValue();
1892     Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1893   }
1894 
1895   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1896     assert(N == 1 && "Invalid number of operands!");
1897     // The operand is actually a t2_so_imm, but we have its bitwise
1898     // negation in the assembly source, so twiddle it here.
1899     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1900     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1901   }
1902 
1903   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1904     assert(N == 1 && "Invalid number of operands!");
1905     // The operand is actually a t2_so_imm, but we have its
1906     // negation in the assembly source, so twiddle it here.
1907     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1908     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1909   }
1910 
1911   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1912     assert(N == 1 && "Invalid number of operands!");
1913     // The operand is actually an imm0_4095, but we have its
1914     // negation in the assembly source, so twiddle it here.
1915     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1916     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1917   }
1918 
1919   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1920     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1921       Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1922       return;
1923     }
1924 
1925     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1926     assert(SR && "Unknown value type!");
1927     Inst.addOperand(MCOperand::CreateExpr(SR));
1928   }
1929 
1930   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1931     assert(N == 1 && "Invalid number of operands!");
1932     if (isImm()) {
1933       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1934       if (CE) {
1935         Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1936         return;
1937       }
1938 
1939       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1940       assert(SR && "Unknown value type!");
1941       Inst.addOperand(MCOperand::CreateExpr(SR));
1942       return;
1943     }
1944 
1945     assert(isMem()  && "Unknown value type!");
1946     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1947     Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1948   }
1949 
1950   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1951     assert(N == 1 && "Invalid number of operands!");
1952     // The operand is actually a so_imm, but we have its bitwise
1953     // negation in the assembly source, so twiddle it here.
1954     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1955     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1956   }
1957 
1958   void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1959     assert(N == 1 && "Invalid number of operands!");
1960     // The operand is actually a so_imm, but we have its
1961     // negation in the assembly source, so twiddle it here.
1962     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1963     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1964   }
1965 
1966   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1967     assert(N == 1 && "Invalid number of operands!");
1968     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1969   }
1970 
1971   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1972     assert(N == 1 && "Invalid number of operands!");
1973     Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1974   }
1975 
1976   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1977     assert(N == 1 && "Invalid number of operands!");
1978     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1979   }
1980 
1981   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1982     assert(N == 1 && "Invalid number of operands!");
1983     int32_t Imm = Memory.OffsetImm->getValue();
1984     Inst.addOperand(MCOperand::CreateImm(Imm));
1985   }
1986 
1987   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1988     assert(N == 1 && "Invalid number of operands!");
1989     assert(isImm() && "Not an immediate!");
1990 
1991     // If we have an immediate that's not a constant, treat it as a label
1992     // reference needing a fixup.
1993     if (!isa<MCConstantExpr>(getImm())) {
1994       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1995       return;
1996     }
1997 
1998     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1999     int Val = CE->getValue();
2000     Inst.addOperand(MCOperand::CreateImm(Val));
2001   }
2002 
2003   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2004     assert(N == 2 && "Invalid number of operands!");
2005     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2006     Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2007   }
2008 
2009   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2010     addAlignedMemoryOperands(Inst, N);
2011   }
2012 
2013   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2014     addAlignedMemoryOperands(Inst, N);
2015   }
2016 
2017   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2018     addAlignedMemoryOperands(Inst, N);
2019   }
2020 
2021   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2022     addAlignedMemoryOperands(Inst, N);
2023   }
2024 
2025   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2026     addAlignedMemoryOperands(Inst, N);
2027   }
2028 
2029   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2030     addAlignedMemoryOperands(Inst, N);
2031   }
2032 
2033   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2034     addAlignedMemoryOperands(Inst, N);
2035   }
2036 
2037   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2038     addAlignedMemoryOperands(Inst, N);
2039   }
2040 
2041   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2042     addAlignedMemoryOperands(Inst, N);
2043   }
2044 
2045   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2046     addAlignedMemoryOperands(Inst, N);
2047   }
2048 
2049   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2050     addAlignedMemoryOperands(Inst, N);
2051   }
2052 
2053   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2054     assert(N == 3 && "Invalid number of operands!");
2055     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2056     if (!Memory.OffsetRegNum) {
2057       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2058       // Special case for #-0
2059       if (Val == INT32_MIN) Val = 0;
2060       if (Val < 0) Val = -Val;
2061       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2062     } else {
2063       // For register offset, we encode the shift type and negation flag
2064       // here.
2065       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2066                               Memory.ShiftImm, Memory.ShiftType);
2067     }
2068     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2069     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2070     Inst.addOperand(MCOperand::CreateImm(Val));
2071   }
2072 
2073   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2074     assert(N == 2 && "Invalid number of operands!");
2075     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2076     assert(CE && "non-constant AM2OffsetImm operand!");
2077     int32_t Val = CE->getValue();
2078     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2079     // Special case for #-0
2080     if (Val == INT32_MIN) Val = 0;
2081     if (Val < 0) Val = -Val;
2082     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2083     Inst.addOperand(MCOperand::CreateReg(0));
2084     Inst.addOperand(MCOperand::CreateImm(Val));
2085   }
2086 
2087   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2088     assert(N == 3 && "Invalid number of operands!");
2089     // If we have an immediate that's not a constant, treat it as a label
2090     // reference needing a fixup. If it is a constant, it's something else
2091     // and we reject it.
2092     if (isImm()) {
2093       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2094       Inst.addOperand(MCOperand::CreateReg(0));
2095       Inst.addOperand(MCOperand::CreateImm(0));
2096       return;
2097     }
2098 
2099     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2100     if (!Memory.OffsetRegNum) {
2101       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2102       // Special case for #-0
2103       if (Val == INT32_MIN) Val = 0;
2104       if (Val < 0) Val = -Val;
2105       Val = ARM_AM::getAM3Opc(AddSub, Val);
2106     } else {
2107       // For register offset, we encode the shift type and negation flag
2108       // here.
2109       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2110     }
2111     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2112     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2113     Inst.addOperand(MCOperand::CreateImm(Val));
2114   }
2115 
2116   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2117     assert(N == 2 && "Invalid number of operands!");
2118     if (Kind == k_PostIndexRegister) {
2119       int32_t Val =
2120         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2121       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2122       Inst.addOperand(MCOperand::CreateImm(Val));
2123       return;
2124     }
2125 
2126     // Constant offset.
2127     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2128     int32_t Val = CE->getValue();
2129     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2130     // Special case for #-0
2131     if (Val == INT32_MIN) Val = 0;
2132     if (Val < 0) Val = -Val;
2133     Val = ARM_AM::getAM3Opc(AddSub, Val);
2134     Inst.addOperand(MCOperand::CreateReg(0));
2135     Inst.addOperand(MCOperand::CreateImm(Val));
2136   }
2137 
2138   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2139     assert(N == 2 && "Invalid number of operands!");
2140     // If we have an immediate that's not a constant, treat it as a label
2141     // reference needing a fixup. If it is a constant, it's something else
2142     // and we reject it.
2143     if (isImm()) {
2144       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2145       Inst.addOperand(MCOperand::CreateImm(0));
2146       return;
2147     }
2148 
2149     // The lower two bits are always zero and as such are not encoded.
2150     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2151     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2152     // Special case for #-0
2153     if (Val == INT32_MIN) Val = 0;
2154     if (Val < 0) Val = -Val;
2155     Val = ARM_AM::getAM5Opc(AddSub, Val);
2156     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2157     Inst.addOperand(MCOperand::CreateImm(Val));
2158   }
2159 
2160   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2161     assert(N == 2 && "Invalid number of operands!");
2162     // If we have an immediate that's not a constant, treat it as a label
2163     // reference needing a fixup. If it is a constant, it's something else
2164     // and we reject it.
2165     if (isImm()) {
2166       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2167       Inst.addOperand(MCOperand::CreateImm(0));
2168       return;
2169     }
2170 
2171     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2172     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2173     Inst.addOperand(MCOperand::CreateImm(Val));
2174   }
2175 
2176   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2177     assert(N == 2 && "Invalid number of operands!");
2178     // The lower two bits are always zero and as such are not encoded.
2179     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2180     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2181     Inst.addOperand(MCOperand::CreateImm(Val));
2182   }
2183 
2184   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2185     assert(N == 2 && "Invalid number of operands!");
2186     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2187     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2188     Inst.addOperand(MCOperand::CreateImm(Val));
2189   }
2190 
2191   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2192     addMemImm8OffsetOperands(Inst, N);
2193   }
2194 
2195   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2196     addMemImm8OffsetOperands(Inst, N);
2197   }
2198 
2199   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2200     assert(N == 2 && "Invalid number of operands!");
2201     // If this is an immediate, it's a label reference.
2202     if (isImm()) {
2203       addExpr(Inst, getImm());
2204       Inst.addOperand(MCOperand::CreateImm(0));
2205       return;
2206     }
2207 
2208     // Otherwise, it's a normal memory reg+offset.
2209     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2210     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2211     Inst.addOperand(MCOperand::CreateImm(Val));
2212   }
2213 
2214   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2215     assert(N == 2 && "Invalid number of operands!");
2216     // If this is an immediate, it's a label reference.
2217     if (isImm()) {
2218       addExpr(Inst, getImm());
2219       Inst.addOperand(MCOperand::CreateImm(0));
2220       return;
2221     }
2222 
2223     // Otherwise, it's a normal memory reg+offset.
2224     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2225     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2226     Inst.addOperand(MCOperand::CreateImm(Val));
2227   }
2228 
2229   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2230     assert(N == 2 && "Invalid number of operands!");
2231     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2232     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2233   }
2234 
2235   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2236     assert(N == 2 && "Invalid number of operands!");
2237     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2238     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2239   }
2240 
2241   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2242     assert(N == 3 && "Invalid number of operands!");
2243     unsigned Val =
2244       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2245                         Memory.ShiftImm, Memory.ShiftType);
2246     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2247     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2248     Inst.addOperand(MCOperand::CreateImm(Val));
2249   }
2250 
2251   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2252     assert(N == 3 && "Invalid number of operands!");
2253     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2254     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2255     Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2256   }
2257 
2258   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2259     assert(N == 2 && "Invalid number of operands!");
2260     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2261     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2262   }
2263 
2264   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2265     assert(N == 2 && "Invalid number of operands!");
2266     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2267     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2268     Inst.addOperand(MCOperand::CreateImm(Val));
2269   }
2270 
2271   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2272     assert(N == 2 && "Invalid number of operands!");
2273     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2274     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2275     Inst.addOperand(MCOperand::CreateImm(Val));
2276   }
2277 
2278   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2279     assert(N == 2 && "Invalid number of operands!");
2280     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2281     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2282     Inst.addOperand(MCOperand::CreateImm(Val));
2283   }
2284 
2285   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2286     assert(N == 2 && "Invalid number of operands!");
2287     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2288     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2289     Inst.addOperand(MCOperand::CreateImm(Val));
2290   }
2291 
2292   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2293     assert(N == 1 && "Invalid number of operands!");
2294     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2295     assert(CE && "non-constant post-idx-imm8 operand!");
2296     int Imm = CE->getValue();
2297     bool isAdd = Imm >= 0;
2298     if (Imm == INT32_MIN) Imm = 0;
2299     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2300     Inst.addOperand(MCOperand::CreateImm(Imm));
2301   }
2302 
2303   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2304     assert(N == 1 && "Invalid number of operands!");
2305     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2306     assert(CE && "non-constant post-idx-imm8s4 operand!");
2307     int Imm = CE->getValue();
2308     bool isAdd = Imm >= 0;
2309     if (Imm == INT32_MIN) Imm = 0;
2310     // Immediate is scaled by 4.
2311     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2312     Inst.addOperand(MCOperand::CreateImm(Imm));
2313   }
2314 
2315   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2316     assert(N == 2 && "Invalid number of operands!");
2317     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2318     Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2319   }
2320 
2321   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2322     assert(N == 2 && "Invalid number of operands!");
2323     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2324     // The sign, shift type, and shift amount are encoded in a single operand
2325     // using the AM2 encoding helpers.
2326     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2327     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2328                                      PostIdxReg.ShiftTy);
2329     Inst.addOperand(MCOperand::CreateImm(Imm));
2330   }
2331 
2332   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2333     assert(N == 1 && "Invalid number of operands!");
2334     Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2335   }
2336 
2337   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2338     assert(N == 1 && "Invalid number of operands!");
2339     Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2340   }
2341 
2342   void addVecListOperands(MCInst &Inst, unsigned N) const {
2343     assert(N == 1 && "Invalid number of operands!");
2344     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2345   }
2346 
2347   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2348     assert(N == 2 && "Invalid number of operands!");
2349     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2350     Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2351   }
2352 
2353   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2354     assert(N == 1 && "Invalid number of operands!");
2355     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2356   }
2357 
2358   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2359     assert(N == 1 && "Invalid number of operands!");
2360     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2361   }
2362 
2363   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2364     assert(N == 1 && "Invalid number of operands!");
2365     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2366   }
2367 
2368   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2369     assert(N == 1 && "Invalid number of operands!");
2370     // The immediate encodes the type of constant as well as the value.
2371     // Mask in that this is an i8 splat.
2372     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2373     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2374   }
2375 
2376   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2377     assert(N == 1 && "Invalid number of operands!");
2378     // The immediate encodes the type of constant as well as the value.
2379     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2380     unsigned Value = CE->getValue();
2381     if (Value >= 256)
2382       Value = (Value >> 8) | 0xa00;
2383     else
2384       Value |= 0x800;
2385     Inst.addOperand(MCOperand::CreateImm(Value));
2386   }
2387 
2388   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2389     assert(N == 1 && "Invalid number of operands!");
2390     // The immediate encodes the type of constant as well as the value.
2391     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2392     unsigned Value = CE->getValue();
2393     if (Value >= 256 && Value <= 0xff00)
2394       Value = (Value >> 8) | 0x200;
2395     else if (Value > 0xffff && Value <= 0xff0000)
2396       Value = (Value >> 16) | 0x400;
2397     else if (Value > 0xffffff)
2398       Value = (Value >> 24) | 0x600;
2399     Inst.addOperand(MCOperand::CreateImm(Value));
2400   }
2401 
2402   void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2403     assert(N == 1 && "Invalid number of operands!");
2404     // The immediate encodes the type of constant as well as the value.
2405     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2406     unsigned Value = CE->getValue();
2407     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2408             Inst.getOpcode() == ARM::VMOVv16i8) &&
2409            "All vmvn instructions that wants to replicate non-zero byte "
2410            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2411     unsigned B = ((~Value) & 0xff);
2412     B |= 0xe00; // cmode = 0b1110
2413     Inst.addOperand(MCOperand::CreateImm(B));
2414   }
2415   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2416     assert(N == 1 && "Invalid number of operands!");
2417     // The immediate encodes the type of constant as well as the value.
2418     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2419     unsigned Value = CE->getValue();
2420     if (Value >= 256 && Value <= 0xffff)
2421       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2422     else if (Value > 0xffff && Value <= 0xffffff)
2423       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2424     else if (Value > 0xffffff)
2425       Value = (Value >> 24) | 0x600;
2426     Inst.addOperand(MCOperand::CreateImm(Value));
2427   }
2428 
2429   void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2430     assert(N == 1 && "Invalid number of operands!");
2431     // The immediate encodes the type of constant as well as the value.
2432     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2433     unsigned Value = CE->getValue();
2434     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2435             Inst.getOpcode() == ARM::VMOVv16i8) &&
2436            "All instructions that wants to replicate non-zero byte "
2437            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2438     unsigned B = Value & 0xff;
2439     B |= 0xe00; // cmode = 0b1110
2440     Inst.addOperand(MCOperand::CreateImm(B));
2441   }
2442   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2443     assert(N == 1 && "Invalid number of operands!");
2444     // The immediate encodes the type of constant as well as the value.
2445     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2446     unsigned Value = ~CE->getValue();
2447     if (Value >= 256 && Value <= 0xffff)
2448       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2449     else if (Value > 0xffff && Value <= 0xffffff)
2450       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2451     else if (Value > 0xffffff)
2452       Value = (Value >> 24) | 0x600;
2453     Inst.addOperand(MCOperand::CreateImm(Value));
2454   }
2455 
2456   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2457     assert(N == 1 && "Invalid number of operands!");
2458     // The immediate encodes the type of constant as well as the value.
2459     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2460     uint64_t Value = CE->getValue();
2461     unsigned Imm = 0;
2462     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2463       Imm |= (Value & 1) << i;
2464     }
2465     Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2466   }
2467 
2468   void print(raw_ostream &OS) const override;
2469 
2470   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2471     auto Op = make_unique<ARMOperand>(k_ITCondMask);
2472     Op->ITMask.Mask = Mask;
2473     Op->StartLoc = S;
2474     Op->EndLoc = S;
2475     return Op;
2476   }
2477 
2478   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2479                                                     SMLoc S) {
2480     auto Op = make_unique<ARMOperand>(k_CondCode);
2481     Op->CC.Val = CC;
2482     Op->StartLoc = S;
2483     Op->EndLoc = S;
2484     return Op;
2485   }
2486 
2487   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2488     auto Op = make_unique<ARMOperand>(k_CoprocNum);
2489     Op->Cop.Val = CopVal;
2490     Op->StartLoc = S;
2491     Op->EndLoc = S;
2492     return Op;
2493   }
2494 
2495   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2496     auto Op = make_unique<ARMOperand>(k_CoprocReg);
2497     Op->Cop.Val = CopVal;
2498     Op->StartLoc = S;
2499     Op->EndLoc = S;
2500     return Op;
2501   }
2502 
2503   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2504                                                         SMLoc E) {
2505     auto Op = make_unique<ARMOperand>(k_CoprocOption);
2506     Op->Cop.Val = Val;
2507     Op->StartLoc = S;
2508     Op->EndLoc = E;
2509     return Op;
2510   }
2511 
2512   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2513     auto Op = make_unique<ARMOperand>(k_CCOut);
2514     Op->Reg.RegNum = RegNum;
2515     Op->StartLoc = S;
2516     Op->EndLoc = S;
2517     return Op;
2518   }
2519 
2520   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2521     auto Op = make_unique<ARMOperand>(k_Token);
2522     Op->Tok.Data = Str.data();
2523     Op->Tok.Length = Str.size();
2524     Op->StartLoc = S;
2525     Op->EndLoc = S;
2526     return Op;
2527   }
2528 
2529   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2530                                                SMLoc E) {
2531     auto Op = make_unique<ARMOperand>(k_Register);
2532     Op->Reg.RegNum = RegNum;
2533     Op->StartLoc = S;
2534     Op->EndLoc = E;
2535     return Op;
2536   }
2537 
2538   static std::unique_ptr<ARMOperand>
2539   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2540                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2541                         SMLoc E) {
2542     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2543     Op->RegShiftedReg.ShiftTy = ShTy;
2544     Op->RegShiftedReg.SrcReg = SrcReg;
2545     Op->RegShiftedReg.ShiftReg = ShiftReg;
2546     Op->RegShiftedReg.ShiftImm = ShiftImm;
2547     Op->StartLoc = S;
2548     Op->EndLoc = E;
2549     return Op;
2550   }
2551 
2552   static std::unique_ptr<ARMOperand>
2553   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2554                          unsigned ShiftImm, SMLoc S, SMLoc E) {
2555     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2556     Op->RegShiftedImm.ShiftTy = ShTy;
2557     Op->RegShiftedImm.SrcReg = SrcReg;
2558     Op->RegShiftedImm.ShiftImm = ShiftImm;
2559     Op->StartLoc = S;
2560     Op->EndLoc = E;
2561     return Op;
2562   }
2563 
2564   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2565                                                       SMLoc S, SMLoc E) {
2566     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2567     Op->ShifterImm.isASR = isASR;
2568     Op->ShifterImm.Imm = Imm;
2569     Op->StartLoc = S;
2570     Op->EndLoc = E;
2571     return Op;
2572   }
2573 
2574   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2575                                                   SMLoc E) {
2576     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2577     Op->RotImm.Imm = Imm;
2578     Op->StartLoc = S;
2579     Op->EndLoc = E;
2580     return Op;
2581   }
2582 
2583   static std::unique_ptr<ARMOperand>
2584   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2585     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2586     Op->Bitfield.LSB = LSB;
2587     Op->Bitfield.Width = Width;
2588     Op->StartLoc = S;
2589     Op->EndLoc = E;
2590     return Op;
2591   }
2592 
2593   static std::unique_ptr<ARMOperand>
2594   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2595                 SMLoc StartLoc, SMLoc EndLoc) {
2596     assert (Regs.size() > 0 && "RegList contains no registers?");
2597     KindTy Kind = k_RegisterList;
2598 
2599     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2600       Kind = k_DPRRegisterList;
2601     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2602              contains(Regs.front().second))
2603       Kind = k_SPRRegisterList;
2604 
2605     // Sort based on the register encoding values.
2606     array_pod_sort(Regs.begin(), Regs.end());
2607 
2608     auto Op = make_unique<ARMOperand>(Kind);
2609     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2610            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2611       Op->Registers.push_back(I->second);
2612     Op->StartLoc = StartLoc;
2613     Op->EndLoc = EndLoc;
2614     return Op;
2615   }
2616 
2617   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2618                                                       unsigned Count,
2619                                                       bool isDoubleSpaced,
2620                                                       SMLoc S, SMLoc E) {
2621     auto Op = make_unique<ARMOperand>(k_VectorList);
2622     Op->VectorList.RegNum = RegNum;
2623     Op->VectorList.Count = Count;
2624     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2625     Op->StartLoc = S;
2626     Op->EndLoc = E;
2627     return Op;
2628   }
2629 
2630   static std::unique_ptr<ARMOperand>
2631   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2632                            SMLoc S, SMLoc E) {
2633     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2634     Op->VectorList.RegNum = RegNum;
2635     Op->VectorList.Count = Count;
2636     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2637     Op->StartLoc = S;
2638     Op->EndLoc = E;
2639     return Op;
2640   }
2641 
2642   static std::unique_ptr<ARMOperand>
2643   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2644                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
2645     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2646     Op->VectorList.RegNum = RegNum;
2647     Op->VectorList.Count = Count;
2648     Op->VectorList.LaneIndex = Index;
2649     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2650     Op->StartLoc = S;
2651     Op->EndLoc = E;
2652     return Op;
2653   }
2654 
2655   static std::unique_ptr<ARMOperand>
2656   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2657     auto Op = make_unique<ARMOperand>(k_VectorIndex);
2658     Op->VectorIndex.Val = Idx;
2659     Op->StartLoc = S;
2660     Op->EndLoc = E;
2661     return Op;
2662   }
2663 
2664   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2665                                                SMLoc E) {
2666     auto Op = make_unique<ARMOperand>(k_Immediate);
2667     Op->Imm.Val = Val;
2668     Op->StartLoc = S;
2669     Op->EndLoc = E;
2670     return Op;
2671   }
2672 
2673   static std::unique_ptr<ARMOperand>
2674   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2675             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2676             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2677             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2678     auto Op = make_unique<ARMOperand>(k_Memory);
2679     Op->Memory.BaseRegNum = BaseRegNum;
2680     Op->Memory.OffsetImm = OffsetImm;
2681     Op->Memory.OffsetRegNum = OffsetRegNum;
2682     Op->Memory.ShiftType = ShiftType;
2683     Op->Memory.ShiftImm = ShiftImm;
2684     Op->Memory.Alignment = Alignment;
2685     Op->Memory.isNegative = isNegative;
2686     Op->StartLoc = S;
2687     Op->EndLoc = E;
2688     Op->AlignmentLoc = AlignmentLoc;
2689     return Op;
2690   }
2691 
2692   static std::unique_ptr<ARMOperand>
2693   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2694                    unsigned ShiftImm, SMLoc S, SMLoc E) {
2695     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2696     Op->PostIdxReg.RegNum = RegNum;
2697     Op->PostIdxReg.isAdd = isAdd;
2698     Op->PostIdxReg.ShiftTy = ShiftTy;
2699     Op->PostIdxReg.ShiftImm = ShiftImm;
2700     Op->StartLoc = S;
2701     Op->EndLoc = E;
2702     return Op;
2703   }
2704 
2705   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2706                                                          SMLoc S) {
2707     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2708     Op->MBOpt.Val = Opt;
2709     Op->StartLoc = S;
2710     Op->EndLoc = S;
2711     return Op;
2712   }
2713 
2714   static std::unique_ptr<ARMOperand>
2715   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2716     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2717     Op->ISBOpt.Val = Opt;
2718     Op->StartLoc = S;
2719     Op->EndLoc = S;
2720     return Op;
2721   }
2722 
2723   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2724                                                       SMLoc S) {
2725     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2726     Op->IFlags.Val = IFlags;
2727     Op->StartLoc = S;
2728     Op->EndLoc = S;
2729     return Op;
2730   }
2731 
2732   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2733     auto Op = make_unique<ARMOperand>(k_MSRMask);
2734     Op->MMask.Val = MMask;
2735     Op->StartLoc = S;
2736     Op->EndLoc = S;
2737     return Op;
2738   }
2739 };
2740 
2741 } // end anonymous namespace.
2742 
2743 void ARMOperand::print(raw_ostream &OS) const {
2744   switch (Kind) {
2745   case k_CondCode:
2746     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2747     break;
2748   case k_CCOut:
2749     OS << "<ccout " << getReg() << ">";
2750     break;
2751   case k_ITCondMask: {
2752     static const char *const MaskStr[] = {
2753       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2754       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2755     };
2756     assert((ITMask.Mask & 0xf) == ITMask.Mask);
2757     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2758     break;
2759   }
2760   case k_CoprocNum:
2761     OS << "<coprocessor number: " << getCoproc() << ">";
2762     break;
2763   case k_CoprocReg:
2764     OS << "<coprocessor register: " << getCoproc() << ">";
2765     break;
2766   case k_CoprocOption:
2767     OS << "<coprocessor option: " << CoprocOption.Val << ">";
2768     break;
2769   case k_MSRMask:
2770     OS << "<mask: " << getMSRMask() << ">";
2771     break;
2772   case k_Immediate:
2773     getImm()->print(OS);
2774     break;
2775   case k_MemBarrierOpt:
2776     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2777     break;
2778   case k_InstSyncBarrierOpt:
2779     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2780     break;
2781   case k_Memory:
2782     OS << "<memory "
2783        << " base:" << Memory.BaseRegNum;
2784     OS << ">";
2785     break;
2786   case k_PostIndexRegister:
2787     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2788        << PostIdxReg.RegNum;
2789     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2790       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2791          << PostIdxReg.ShiftImm;
2792     OS << ">";
2793     break;
2794   case k_ProcIFlags: {
2795     OS << "<ARM_PROC::";
2796     unsigned IFlags = getProcIFlags();
2797     for (int i=2; i >= 0; --i)
2798       if (IFlags & (1 << i))
2799         OS << ARM_PROC::IFlagsToString(1 << i);
2800     OS << ">";
2801     break;
2802   }
2803   case k_Register:
2804     OS << "<register " << getReg() << ">";
2805     break;
2806   case k_ShifterImmediate:
2807     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2808        << " #" << ShifterImm.Imm << ">";
2809     break;
2810   case k_ShiftedRegister:
2811     OS << "<so_reg_reg "
2812        << RegShiftedReg.SrcReg << " "
2813        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2814        << " " << RegShiftedReg.ShiftReg << ">";
2815     break;
2816   case k_ShiftedImmediate:
2817     OS << "<so_reg_imm "
2818        << RegShiftedImm.SrcReg << " "
2819        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2820        << " #" << RegShiftedImm.ShiftImm << ">";
2821     break;
2822   case k_RotateImmediate:
2823     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2824     break;
2825   case k_BitfieldDescriptor:
2826     OS << "<bitfield " << "lsb: " << Bitfield.LSB
2827        << ", width: " << Bitfield.Width << ">";
2828     break;
2829   case k_RegisterList:
2830   case k_DPRRegisterList:
2831   case k_SPRRegisterList: {
2832     OS << "<register_list ";
2833 
2834     const SmallVectorImpl<unsigned> &RegList = getRegList();
2835     for (SmallVectorImpl<unsigned>::const_iterator
2836            I = RegList.begin(), E = RegList.end(); I != E; ) {
2837       OS << *I;
2838       if (++I < E) OS << ", ";
2839     }
2840 
2841     OS << ">";
2842     break;
2843   }
2844   case k_VectorList:
2845     OS << "<vector_list " << VectorList.Count << " * "
2846        << VectorList.RegNum << ">";
2847     break;
2848   case k_VectorListAllLanes:
2849     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2850        << VectorList.RegNum << ">";
2851     break;
2852   case k_VectorListIndexed:
2853     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2854        << VectorList.Count << " * " << VectorList.RegNum << ">";
2855     break;
2856   case k_Token:
2857     OS << "'" << getToken() << "'";
2858     break;
2859   case k_VectorIndex:
2860     OS << "<vectorindex " << getVectorIndex() << ">";
2861     break;
2862   }
2863 }
2864 
2865 /// @name Auto-generated Match Functions
2866 /// {
2867 
2868 static unsigned MatchRegisterName(StringRef Name);
2869 
2870 /// }
2871 
2872 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2873                                  SMLoc &StartLoc, SMLoc &EndLoc) {
2874   StartLoc = Parser.getTok().getLoc();
2875   EndLoc = Parser.getTok().getEndLoc();
2876   RegNo = tryParseRegister();
2877 
2878   return (RegNo == (unsigned)-1);
2879 }
2880 
2881 /// Try to parse a register name.  The token must be an Identifier when called,
2882 /// and if it is a register name the token is eaten and the register number is
2883 /// returned.  Otherwise return -1.
2884 ///
2885 int ARMAsmParser::tryParseRegister() {
2886   const AsmToken &Tok = Parser.getTok();
2887   if (Tok.isNot(AsmToken::Identifier)) return -1;
2888 
2889   std::string lowerCase = Tok.getString().lower();
2890   unsigned RegNum = MatchRegisterName(lowerCase);
2891   if (!RegNum) {
2892     RegNum = StringSwitch<unsigned>(lowerCase)
2893       .Case("r13", ARM::SP)
2894       .Case("r14", ARM::LR)
2895       .Case("r15", ARM::PC)
2896       .Case("ip", ARM::R12)
2897       // Additional register name aliases for 'gas' compatibility.
2898       .Case("a1", ARM::R0)
2899       .Case("a2", ARM::R1)
2900       .Case("a3", ARM::R2)
2901       .Case("a4", ARM::R3)
2902       .Case("v1", ARM::R4)
2903       .Case("v2", ARM::R5)
2904       .Case("v3", ARM::R6)
2905       .Case("v4", ARM::R7)
2906       .Case("v5", ARM::R8)
2907       .Case("v6", ARM::R9)
2908       .Case("v7", ARM::R10)
2909       .Case("v8", ARM::R11)
2910       .Case("sb", ARM::R9)
2911       .Case("sl", ARM::R10)
2912       .Case("fp", ARM::R11)
2913       .Default(0);
2914   }
2915   if (!RegNum) {
2916     // Check for aliases registered via .req. Canonicalize to lower case.
2917     // That's more consistent since register names are case insensitive, and
2918     // it's how the original entry was passed in from MC/MCParser/AsmParser.
2919     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2920     // If no match, return failure.
2921     if (Entry == RegisterReqs.end())
2922       return -1;
2923     Parser.Lex(); // Eat identifier token.
2924     return Entry->getValue();
2925   }
2926 
2927   Parser.Lex(); // Eat identifier token.
2928 
2929   return RegNum;
2930 }
2931 
2932 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2933 // If a recoverable error occurs, return 1. If an irrecoverable error
2934 // occurs, return -1. An irrecoverable error is one where tokens have been
2935 // consumed in the process of trying to parse the shifter (i.e., when it is
2936 // indeed a shifter operand, but malformed).
2937 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
2938   SMLoc S = Parser.getTok().getLoc();
2939   const AsmToken &Tok = Parser.getTok();
2940   if (Tok.isNot(AsmToken::Identifier))
2941     return -1;
2942 
2943   std::string lowerCase = Tok.getString().lower();
2944   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2945       .Case("asl", ARM_AM::lsl)
2946       .Case("lsl", ARM_AM::lsl)
2947       .Case("lsr", ARM_AM::lsr)
2948       .Case("asr", ARM_AM::asr)
2949       .Case("ror", ARM_AM::ror)
2950       .Case("rrx", ARM_AM::rrx)
2951       .Default(ARM_AM::no_shift);
2952 
2953   if (ShiftTy == ARM_AM::no_shift)
2954     return 1;
2955 
2956   Parser.Lex(); // Eat the operator.
2957 
2958   // The source register for the shift has already been added to the
2959   // operand list, so we need to pop it off and combine it into the shifted
2960   // register operand instead.
2961   std::unique_ptr<ARMOperand> PrevOp(
2962       (ARMOperand *)Operands.pop_back_val().release());
2963   if (!PrevOp->isReg())
2964     return Error(PrevOp->getStartLoc(), "shift must be of a register");
2965   int SrcReg = PrevOp->getReg();
2966 
2967   SMLoc EndLoc;
2968   int64_t Imm = 0;
2969   int ShiftReg = 0;
2970   if (ShiftTy == ARM_AM::rrx) {
2971     // RRX Doesn't have an explicit shift amount. The encoder expects
2972     // the shift register to be the same as the source register. Seems odd,
2973     // but OK.
2974     ShiftReg = SrcReg;
2975   } else {
2976     // Figure out if this is shifted by a constant or a register (for non-RRX).
2977     if (Parser.getTok().is(AsmToken::Hash) ||
2978         Parser.getTok().is(AsmToken::Dollar)) {
2979       Parser.Lex(); // Eat hash.
2980       SMLoc ImmLoc = Parser.getTok().getLoc();
2981       const MCExpr *ShiftExpr = nullptr;
2982       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2983         Error(ImmLoc, "invalid immediate shift value");
2984         return -1;
2985       }
2986       // The expression must be evaluatable as an immediate.
2987       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2988       if (!CE) {
2989         Error(ImmLoc, "invalid immediate shift value");
2990         return -1;
2991       }
2992       // Range check the immediate.
2993       // lsl, ror: 0 <= imm <= 31
2994       // lsr, asr: 0 <= imm <= 32
2995       Imm = CE->getValue();
2996       if (Imm < 0 ||
2997           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2998           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2999         Error(ImmLoc, "immediate shift value out of range");
3000         return -1;
3001       }
3002       // shift by zero is a nop. Always send it through as lsl.
3003       // ('as' compatibility)
3004       if (Imm == 0)
3005         ShiftTy = ARM_AM::lsl;
3006     } else if (Parser.getTok().is(AsmToken::Identifier)) {
3007       SMLoc L = Parser.getTok().getLoc();
3008       EndLoc = Parser.getTok().getEndLoc();
3009       ShiftReg = tryParseRegister();
3010       if (ShiftReg == -1) {
3011         Error(L, "expected immediate or register in shift operand");
3012         return -1;
3013       }
3014     } else {
3015       Error(Parser.getTok().getLoc(),
3016             "expected immediate or register in shift operand");
3017       return -1;
3018     }
3019   }
3020 
3021   if (ShiftReg && ShiftTy != ARM_AM::rrx)
3022     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3023                                                          ShiftReg, Imm,
3024                                                          S, EndLoc));
3025   else
3026     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3027                                                           S, EndLoc));
3028 
3029   return 0;
3030 }
3031 
3032 
3033 /// Try to parse a register name.  The token must be an Identifier when called.
3034 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3035 /// if there is a "writeback". 'true' if it's not a register.
3036 ///
3037 /// TODO this is likely to change to allow different register types and or to
3038 /// parse for a specific register type.
3039 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3040   const AsmToken &RegTok = Parser.getTok();
3041   int RegNo = tryParseRegister();
3042   if (RegNo == -1)
3043     return true;
3044 
3045   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3046                                            RegTok.getEndLoc()));
3047 
3048   const AsmToken &ExclaimTok = Parser.getTok();
3049   if (ExclaimTok.is(AsmToken::Exclaim)) {
3050     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3051                                                ExclaimTok.getLoc()));
3052     Parser.Lex(); // Eat exclaim token
3053     return false;
3054   }
3055 
3056   // Also check for an index operand. This is only legal for vector registers,
3057   // but that'll get caught OK in operand matching, so we don't need to
3058   // explicitly filter everything else out here.
3059   if (Parser.getTok().is(AsmToken::LBrac)) {
3060     SMLoc SIdx = Parser.getTok().getLoc();
3061     Parser.Lex(); // Eat left bracket token.
3062 
3063     const MCExpr *ImmVal;
3064     if (getParser().parseExpression(ImmVal))
3065       return true;
3066     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3067     if (!MCE)
3068       return TokError("immediate value expected for vector index");
3069 
3070     if (Parser.getTok().isNot(AsmToken::RBrac))
3071       return Error(Parser.getTok().getLoc(), "']' expected");
3072 
3073     SMLoc E = Parser.getTok().getEndLoc();
3074     Parser.Lex(); // Eat right bracket token.
3075 
3076     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3077                                                      SIdx, E,
3078                                                      getContext()));
3079   }
3080 
3081   return false;
3082 }
3083 
3084 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3085 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
3086 /// "c5", ...
3087 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3088   // Use the same layout as the tablegen'erated register name matcher. Ugly,
3089   // but efficient.
3090   switch (Name.size()) {
3091   default: return -1;
3092   case 2:
3093     if (Name[0] != CoprocOp)
3094       return -1;
3095     switch (Name[1]) {
3096     default:  return -1;
3097     case '0': return 0;
3098     case '1': return 1;
3099     case '2': return 2;
3100     case '3': return 3;
3101     case '4': return 4;
3102     case '5': return 5;
3103     case '6': return 6;
3104     case '7': return 7;
3105     case '8': return 8;
3106     case '9': return 9;
3107     }
3108   case 3:
3109     if (Name[0] != CoprocOp || Name[1] != '1')
3110       return -1;
3111     switch (Name[2]) {
3112     default:  return -1;
3113     // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
3114     case '0': return CoprocOp == 'p'? -1: 10;
3115     case '1': return CoprocOp == 'p'? -1: 11;
3116     case '2': return 12;
3117     case '3': return 13;
3118     case '4': return 14;
3119     case '5': return 15;
3120     }
3121   }
3122 }
3123 
3124 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3125 ARMAsmParser::OperandMatchResultTy
3126 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3127   SMLoc S = Parser.getTok().getLoc();
3128   const AsmToken &Tok = Parser.getTok();
3129   if (!Tok.is(AsmToken::Identifier))
3130     return MatchOperand_NoMatch;
3131   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3132     .Case("eq", ARMCC::EQ)
3133     .Case("ne", ARMCC::NE)
3134     .Case("hs", ARMCC::HS)
3135     .Case("cs", ARMCC::HS)
3136     .Case("lo", ARMCC::LO)
3137     .Case("cc", ARMCC::LO)
3138     .Case("mi", ARMCC::MI)
3139     .Case("pl", ARMCC::PL)
3140     .Case("vs", ARMCC::VS)
3141     .Case("vc", ARMCC::VC)
3142     .Case("hi", ARMCC::HI)
3143     .Case("ls", ARMCC::LS)
3144     .Case("ge", ARMCC::GE)
3145     .Case("lt", ARMCC::LT)
3146     .Case("gt", ARMCC::GT)
3147     .Case("le", ARMCC::LE)
3148     .Case("al", ARMCC::AL)
3149     .Default(~0U);
3150   if (CC == ~0U)
3151     return MatchOperand_NoMatch;
3152   Parser.Lex(); // Eat the token.
3153 
3154   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3155 
3156   return MatchOperand_Success;
3157 }
3158 
3159 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3160 /// token must be an Identifier when called, and if it is a coprocessor
3161 /// number, the token is eaten and the operand is added to the operand list.
3162 ARMAsmParser::OperandMatchResultTy
3163 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3164   SMLoc S = Parser.getTok().getLoc();
3165   const AsmToken &Tok = Parser.getTok();
3166   if (Tok.isNot(AsmToken::Identifier))
3167     return MatchOperand_NoMatch;
3168 
3169   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3170   if (Num == -1)
3171     return MatchOperand_NoMatch;
3172 
3173   Parser.Lex(); // Eat identifier token.
3174   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3175   return MatchOperand_Success;
3176 }
3177 
3178 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3179 /// token must be an Identifier when called, and if it is a coprocessor
3180 /// number, the token is eaten and the operand is added to the operand list.
3181 ARMAsmParser::OperandMatchResultTy
3182 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3183   SMLoc S = Parser.getTok().getLoc();
3184   const AsmToken &Tok = Parser.getTok();
3185   if (Tok.isNot(AsmToken::Identifier))
3186     return MatchOperand_NoMatch;
3187 
3188   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3189   if (Reg == -1)
3190     return MatchOperand_NoMatch;
3191 
3192   Parser.Lex(); // Eat identifier token.
3193   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3194   return MatchOperand_Success;
3195 }
3196 
3197 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3198 /// coproc_option : '{' imm0_255 '}'
3199 ARMAsmParser::OperandMatchResultTy
3200 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3201   SMLoc S = Parser.getTok().getLoc();
3202 
3203   // If this isn't a '{', this isn't a coprocessor immediate operand.
3204   if (Parser.getTok().isNot(AsmToken::LCurly))
3205     return MatchOperand_NoMatch;
3206   Parser.Lex(); // Eat the '{'
3207 
3208   const MCExpr *Expr;
3209   SMLoc Loc = Parser.getTok().getLoc();
3210   if (getParser().parseExpression(Expr)) {
3211     Error(Loc, "illegal expression");
3212     return MatchOperand_ParseFail;
3213   }
3214   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3215   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3216     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3217     return MatchOperand_ParseFail;
3218   }
3219   int Val = CE->getValue();
3220 
3221   // Check for and consume the closing '}'
3222   if (Parser.getTok().isNot(AsmToken::RCurly))
3223     return MatchOperand_ParseFail;
3224   SMLoc E = Parser.getTok().getEndLoc();
3225   Parser.Lex(); // Eat the '}'
3226 
3227   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3228   return MatchOperand_Success;
3229 }
3230 
3231 // For register list parsing, we need to map from raw GPR register numbering
3232 // to the enumeration values. The enumeration values aren't sorted by
3233 // register number due to our using "sp", "lr" and "pc" as canonical names.
3234 static unsigned getNextRegister(unsigned Reg) {
3235   // If this is a GPR, we need to do it manually, otherwise we can rely
3236   // on the sort ordering of the enumeration since the other reg-classes
3237   // are sane.
3238   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3239     return Reg + 1;
3240   switch(Reg) {
3241   default: llvm_unreachable("Invalid GPR number!");
3242   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3243   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3244   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3245   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3246   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3247   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3248   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3249   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3250   }
3251 }
3252 
3253 // Return the low-subreg of a given Q register.
3254 static unsigned getDRegFromQReg(unsigned QReg) {
3255   switch (QReg) {
3256   default: llvm_unreachable("expected a Q register!");
3257   case ARM::Q0:  return ARM::D0;
3258   case ARM::Q1:  return ARM::D2;
3259   case ARM::Q2:  return ARM::D4;
3260   case ARM::Q3:  return ARM::D6;
3261   case ARM::Q4:  return ARM::D8;
3262   case ARM::Q5:  return ARM::D10;
3263   case ARM::Q6:  return ARM::D12;
3264   case ARM::Q7:  return ARM::D14;
3265   case ARM::Q8:  return ARM::D16;
3266   case ARM::Q9:  return ARM::D18;
3267   case ARM::Q10: return ARM::D20;
3268   case ARM::Q11: return ARM::D22;
3269   case ARM::Q12: return ARM::D24;
3270   case ARM::Q13: return ARM::D26;
3271   case ARM::Q14: return ARM::D28;
3272   case ARM::Q15: return ARM::D30;
3273   }
3274 }
3275 
3276 /// Parse a register list.
3277 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3278   assert(Parser.getTok().is(AsmToken::LCurly) &&
3279          "Token is not a Left Curly Brace");
3280   SMLoc S = Parser.getTok().getLoc();
3281   Parser.Lex(); // Eat '{' token.
3282   SMLoc RegLoc = Parser.getTok().getLoc();
3283 
3284   // Check the first register in the list to see what register class
3285   // this is a list of.
3286   int Reg = tryParseRegister();
3287   if (Reg == -1)
3288     return Error(RegLoc, "register expected");
3289 
3290   // The reglist instructions have at most 16 registers, so reserve
3291   // space for that many.
3292   int EReg = 0;
3293   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3294 
3295   // Allow Q regs and just interpret them as the two D sub-registers.
3296   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3297     Reg = getDRegFromQReg(Reg);
3298     EReg = MRI->getEncodingValue(Reg);
3299     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3300     ++Reg;
3301   }
3302   const MCRegisterClass *RC;
3303   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3304     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3305   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3306     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3307   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3308     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3309   else
3310     return Error(RegLoc, "invalid register in register list");
3311 
3312   // Store the register.
3313   EReg = MRI->getEncodingValue(Reg);
3314   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3315 
3316   // This starts immediately after the first register token in the list,
3317   // so we can see either a comma or a minus (range separator) as a legal
3318   // next token.
3319   while (Parser.getTok().is(AsmToken::Comma) ||
3320          Parser.getTok().is(AsmToken::Minus)) {
3321     if (Parser.getTok().is(AsmToken::Minus)) {
3322       Parser.Lex(); // Eat the minus.
3323       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3324       int EndReg = tryParseRegister();
3325       if (EndReg == -1)
3326         return Error(AfterMinusLoc, "register expected");
3327       // Allow Q regs and just interpret them as the two D sub-registers.
3328       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3329         EndReg = getDRegFromQReg(EndReg) + 1;
3330       // If the register is the same as the start reg, there's nothing
3331       // more to do.
3332       if (Reg == EndReg)
3333         continue;
3334       // The register must be in the same register class as the first.
3335       if (!RC->contains(EndReg))
3336         return Error(AfterMinusLoc, "invalid register in register list");
3337       // Ranges must go from low to high.
3338       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3339         return Error(AfterMinusLoc, "bad range in register list");
3340 
3341       // Add all the registers in the range to the register list.
3342       while (Reg != EndReg) {
3343         Reg = getNextRegister(Reg);
3344         EReg = MRI->getEncodingValue(Reg);
3345         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3346       }
3347       continue;
3348     }
3349     Parser.Lex(); // Eat the comma.
3350     RegLoc = Parser.getTok().getLoc();
3351     int OldReg = Reg;
3352     const AsmToken RegTok = Parser.getTok();
3353     Reg = tryParseRegister();
3354     if (Reg == -1)
3355       return Error(RegLoc, "register expected");
3356     // Allow Q regs and just interpret them as the two D sub-registers.
3357     bool isQReg = false;
3358     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3359       Reg = getDRegFromQReg(Reg);
3360       isQReg = true;
3361     }
3362     // The register must be in the same register class as the first.
3363     if (!RC->contains(Reg))
3364       return Error(RegLoc, "invalid register in register list");
3365     // List must be monotonically increasing.
3366     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3367       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3368         Warning(RegLoc, "register list not in ascending order");
3369       else
3370         return Error(RegLoc, "register list not in ascending order");
3371     }
3372     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3373       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3374               ") in register list");
3375       continue;
3376     }
3377     // VFP register lists must also be contiguous.
3378     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3379         Reg != OldReg + 1)
3380       return Error(RegLoc, "non-contiguous register range");
3381     EReg = MRI->getEncodingValue(Reg);
3382     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3383     if (isQReg) {
3384       EReg = MRI->getEncodingValue(++Reg);
3385       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3386     }
3387   }
3388 
3389   if (Parser.getTok().isNot(AsmToken::RCurly))
3390     return Error(Parser.getTok().getLoc(), "'}' expected");
3391   SMLoc E = Parser.getTok().getEndLoc();
3392   Parser.Lex(); // Eat '}' token.
3393 
3394   // Push the register list operand.
3395   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3396 
3397   // The ARM system instruction variants for LDM/STM have a '^' token here.
3398   if (Parser.getTok().is(AsmToken::Caret)) {
3399     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3400     Parser.Lex(); // Eat '^' token.
3401   }
3402 
3403   return false;
3404 }
3405 
3406 // Helper function to parse the lane index for vector lists.
3407 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3408 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3409   Index = 0; // Always return a defined index value.
3410   if (Parser.getTok().is(AsmToken::LBrac)) {
3411     Parser.Lex(); // Eat the '['.
3412     if (Parser.getTok().is(AsmToken::RBrac)) {
3413       // "Dn[]" is the 'all lanes' syntax.
3414       LaneKind = AllLanes;
3415       EndLoc = Parser.getTok().getEndLoc();
3416       Parser.Lex(); // Eat the ']'.
3417       return MatchOperand_Success;
3418     }
3419 
3420     // There's an optional '#' token here. Normally there wouldn't be, but
3421     // inline assemble puts one in, and it's friendly to accept that.
3422     if (Parser.getTok().is(AsmToken::Hash))
3423       Parser.Lex(); // Eat '#' or '$'.
3424 
3425     const MCExpr *LaneIndex;
3426     SMLoc Loc = Parser.getTok().getLoc();
3427     if (getParser().parseExpression(LaneIndex)) {
3428       Error(Loc, "illegal expression");
3429       return MatchOperand_ParseFail;
3430     }
3431     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3432     if (!CE) {
3433       Error(Loc, "lane index must be empty or an integer");
3434       return MatchOperand_ParseFail;
3435     }
3436     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3437       Error(Parser.getTok().getLoc(), "']' expected");
3438       return MatchOperand_ParseFail;
3439     }
3440     EndLoc = Parser.getTok().getEndLoc();
3441     Parser.Lex(); // Eat the ']'.
3442     int64_t Val = CE->getValue();
3443 
3444     // FIXME: Make this range check context sensitive for .8, .16, .32.
3445     if (Val < 0 || Val > 7) {
3446       Error(Parser.getTok().getLoc(), "lane index out of range");
3447       return MatchOperand_ParseFail;
3448     }
3449     Index = Val;
3450     LaneKind = IndexedLane;
3451     return MatchOperand_Success;
3452   }
3453   LaneKind = NoLanes;
3454   return MatchOperand_Success;
3455 }
3456 
3457 // parse a vector register list
3458 ARMAsmParser::OperandMatchResultTy
3459 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3460   VectorLaneTy LaneKind;
3461   unsigned LaneIndex;
3462   SMLoc S = Parser.getTok().getLoc();
3463   // As an extension (to match gas), support a plain D register or Q register
3464   // (without encosing curly braces) as a single or double entry list,
3465   // respectively.
3466   if (Parser.getTok().is(AsmToken::Identifier)) {
3467     SMLoc E = Parser.getTok().getEndLoc();
3468     int Reg = tryParseRegister();
3469     if (Reg == -1)
3470       return MatchOperand_NoMatch;
3471     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3472       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3473       if (Res != MatchOperand_Success)
3474         return Res;
3475       switch (LaneKind) {
3476       case NoLanes:
3477         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3478         break;
3479       case AllLanes:
3480         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3481                                                                 S, E));
3482         break;
3483       case IndexedLane:
3484         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3485                                                                LaneIndex,
3486                                                                false, S, E));
3487         break;
3488       }
3489       return MatchOperand_Success;
3490     }
3491     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3492       Reg = getDRegFromQReg(Reg);
3493       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3494       if (Res != MatchOperand_Success)
3495         return Res;
3496       switch (LaneKind) {
3497       case NoLanes:
3498         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3499                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3500         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3501         break;
3502       case AllLanes:
3503         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3504                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3505         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3506                                                                 S, E));
3507         break;
3508       case IndexedLane:
3509         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3510                                                                LaneIndex,
3511                                                                false, S, E));
3512         break;
3513       }
3514       return MatchOperand_Success;
3515     }
3516     Error(S, "vector register expected");
3517     return MatchOperand_ParseFail;
3518   }
3519 
3520   if (Parser.getTok().isNot(AsmToken::LCurly))
3521     return MatchOperand_NoMatch;
3522 
3523   Parser.Lex(); // Eat '{' token.
3524   SMLoc RegLoc = Parser.getTok().getLoc();
3525 
3526   int Reg = tryParseRegister();
3527   if (Reg == -1) {
3528     Error(RegLoc, "register expected");
3529     return MatchOperand_ParseFail;
3530   }
3531   unsigned Count = 1;
3532   int Spacing = 0;
3533   unsigned FirstReg = Reg;
3534   // The list is of D registers, but we also allow Q regs and just interpret
3535   // them as the two D sub-registers.
3536   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3537     FirstReg = Reg = getDRegFromQReg(Reg);
3538     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3539                  // it's ambiguous with four-register single spaced.
3540     ++Reg;
3541     ++Count;
3542   }
3543 
3544   SMLoc E;
3545   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3546     return MatchOperand_ParseFail;
3547 
3548   while (Parser.getTok().is(AsmToken::Comma) ||
3549          Parser.getTok().is(AsmToken::Minus)) {
3550     if (Parser.getTok().is(AsmToken::Minus)) {
3551       if (!Spacing)
3552         Spacing = 1; // Register range implies a single spaced list.
3553       else if (Spacing == 2) {
3554         Error(Parser.getTok().getLoc(),
3555               "sequential registers in double spaced list");
3556         return MatchOperand_ParseFail;
3557       }
3558       Parser.Lex(); // Eat the minus.
3559       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3560       int EndReg = tryParseRegister();
3561       if (EndReg == -1) {
3562         Error(AfterMinusLoc, "register expected");
3563         return MatchOperand_ParseFail;
3564       }
3565       // Allow Q regs and just interpret them as the two D sub-registers.
3566       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3567         EndReg = getDRegFromQReg(EndReg) + 1;
3568       // If the register is the same as the start reg, there's nothing
3569       // more to do.
3570       if (Reg == EndReg)
3571         continue;
3572       // The register must be in the same register class as the first.
3573       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3574         Error(AfterMinusLoc, "invalid register in register list");
3575         return MatchOperand_ParseFail;
3576       }
3577       // Ranges must go from low to high.
3578       if (Reg > EndReg) {
3579         Error(AfterMinusLoc, "bad range in register list");
3580         return MatchOperand_ParseFail;
3581       }
3582       // Parse the lane specifier if present.
3583       VectorLaneTy NextLaneKind;
3584       unsigned NextLaneIndex;
3585       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3586           MatchOperand_Success)
3587         return MatchOperand_ParseFail;
3588       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3589         Error(AfterMinusLoc, "mismatched lane index in register list");
3590         return MatchOperand_ParseFail;
3591       }
3592 
3593       // Add all the registers in the range to the register list.
3594       Count += EndReg - Reg;
3595       Reg = EndReg;
3596       continue;
3597     }
3598     Parser.Lex(); // Eat the comma.
3599     RegLoc = Parser.getTok().getLoc();
3600     int OldReg = Reg;
3601     Reg = tryParseRegister();
3602     if (Reg == -1) {
3603       Error(RegLoc, "register expected");
3604       return MatchOperand_ParseFail;
3605     }
3606     // vector register lists must be contiguous.
3607     // It's OK to use the enumeration values directly here rather, as the
3608     // VFP register classes have the enum sorted properly.
3609     //
3610     // The list is of D registers, but we also allow Q regs and just interpret
3611     // them as the two D sub-registers.
3612     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3613       if (!Spacing)
3614         Spacing = 1; // Register range implies a single spaced list.
3615       else if (Spacing == 2) {
3616         Error(RegLoc,
3617               "invalid register in double-spaced list (must be 'D' register')");
3618         return MatchOperand_ParseFail;
3619       }
3620       Reg = getDRegFromQReg(Reg);
3621       if (Reg != OldReg + 1) {
3622         Error(RegLoc, "non-contiguous register range");
3623         return MatchOperand_ParseFail;
3624       }
3625       ++Reg;
3626       Count += 2;
3627       // Parse the lane specifier if present.
3628       VectorLaneTy NextLaneKind;
3629       unsigned NextLaneIndex;
3630       SMLoc LaneLoc = Parser.getTok().getLoc();
3631       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3632           MatchOperand_Success)
3633         return MatchOperand_ParseFail;
3634       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3635         Error(LaneLoc, "mismatched lane index in register list");
3636         return MatchOperand_ParseFail;
3637       }
3638       continue;
3639     }
3640     // Normal D register.
3641     // Figure out the register spacing (single or double) of the list if
3642     // we don't know it already.
3643     if (!Spacing)
3644       Spacing = 1 + (Reg == OldReg + 2);
3645 
3646     // Just check that it's contiguous and keep going.
3647     if (Reg != OldReg + Spacing) {
3648       Error(RegLoc, "non-contiguous register range");
3649       return MatchOperand_ParseFail;
3650     }
3651     ++Count;
3652     // Parse the lane specifier if present.
3653     VectorLaneTy NextLaneKind;
3654     unsigned NextLaneIndex;
3655     SMLoc EndLoc = Parser.getTok().getLoc();
3656     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3657       return MatchOperand_ParseFail;
3658     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3659       Error(EndLoc, "mismatched lane index in register list");
3660       return MatchOperand_ParseFail;
3661     }
3662   }
3663 
3664   if (Parser.getTok().isNot(AsmToken::RCurly)) {
3665     Error(Parser.getTok().getLoc(), "'}' expected");
3666     return MatchOperand_ParseFail;
3667   }
3668   E = Parser.getTok().getEndLoc();
3669   Parser.Lex(); // Eat '}' token.
3670 
3671   switch (LaneKind) {
3672   case NoLanes:
3673     // Two-register operands have been converted to the
3674     // composite register classes.
3675     if (Count == 2) {
3676       const MCRegisterClass *RC = (Spacing == 1) ?
3677         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3678         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3679       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3680     }
3681 
3682     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3683                                                     (Spacing == 2), S, E));
3684     break;
3685   case AllLanes:
3686     // Two-register operands have been converted to the
3687     // composite register classes.
3688     if (Count == 2) {
3689       const MCRegisterClass *RC = (Spacing == 1) ?
3690         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3691         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3692       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3693     }
3694     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3695                                                             (Spacing == 2),
3696                                                             S, E));
3697     break;
3698   case IndexedLane:
3699     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3700                                                            LaneIndex,
3701                                                            (Spacing == 2),
3702                                                            S, E));
3703     break;
3704   }
3705   return MatchOperand_Success;
3706 }
3707 
3708 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3709 ARMAsmParser::OperandMatchResultTy
3710 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3711   SMLoc S = Parser.getTok().getLoc();
3712   const AsmToken &Tok = Parser.getTok();
3713   unsigned Opt;
3714 
3715   if (Tok.is(AsmToken::Identifier)) {
3716     StringRef OptStr = Tok.getString();
3717 
3718     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3719       .Case("sy",    ARM_MB::SY)
3720       .Case("st",    ARM_MB::ST)
3721       .Case("ld",    ARM_MB::LD)
3722       .Case("sh",    ARM_MB::ISH)
3723       .Case("ish",   ARM_MB::ISH)
3724       .Case("shst",  ARM_MB::ISHST)
3725       .Case("ishst", ARM_MB::ISHST)
3726       .Case("ishld", ARM_MB::ISHLD)
3727       .Case("nsh",   ARM_MB::NSH)
3728       .Case("un",    ARM_MB::NSH)
3729       .Case("nshst", ARM_MB::NSHST)
3730       .Case("nshld", ARM_MB::NSHLD)
3731       .Case("unst",  ARM_MB::NSHST)
3732       .Case("osh",   ARM_MB::OSH)
3733       .Case("oshst", ARM_MB::OSHST)
3734       .Case("oshld", ARM_MB::OSHLD)
3735       .Default(~0U);
3736 
3737     // ishld, oshld, nshld and ld are only available from ARMv8.
3738     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3739                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3740       Opt = ~0U;
3741 
3742     if (Opt == ~0U)
3743       return MatchOperand_NoMatch;
3744 
3745     Parser.Lex(); // Eat identifier token.
3746   } else if (Tok.is(AsmToken::Hash) ||
3747              Tok.is(AsmToken::Dollar) ||
3748              Tok.is(AsmToken::Integer)) {
3749     if (Parser.getTok().isNot(AsmToken::Integer))
3750       Parser.Lex(); // Eat '#' or '$'.
3751     SMLoc Loc = Parser.getTok().getLoc();
3752 
3753     const MCExpr *MemBarrierID;
3754     if (getParser().parseExpression(MemBarrierID)) {
3755       Error(Loc, "illegal expression");
3756       return MatchOperand_ParseFail;
3757     }
3758 
3759     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3760     if (!CE) {
3761       Error(Loc, "constant expression expected");
3762       return MatchOperand_ParseFail;
3763     }
3764 
3765     int Val = CE->getValue();
3766     if (Val & ~0xf) {
3767       Error(Loc, "immediate value out of range");
3768       return MatchOperand_ParseFail;
3769     }
3770 
3771     Opt = ARM_MB::RESERVED_0 + Val;
3772   } else
3773     return MatchOperand_ParseFail;
3774 
3775   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3776   return MatchOperand_Success;
3777 }
3778 
3779 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3780 ARMAsmParser::OperandMatchResultTy
3781 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3782   SMLoc S = Parser.getTok().getLoc();
3783   const AsmToken &Tok = Parser.getTok();
3784   unsigned Opt;
3785 
3786   if (Tok.is(AsmToken::Identifier)) {
3787     StringRef OptStr = Tok.getString();
3788 
3789     if (OptStr.equals_lower("sy"))
3790       Opt = ARM_ISB::SY;
3791     else
3792       return MatchOperand_NoMatch;
3793 
3794     Parser.Lex(); // Eat identifier token.
3795   } else if (Tok.is(AsmToken::Hash) ||
3796              Tok.is(AsmToken::Dollar) ||
3797              Tok.is(AsmToken::Integer)) {
3798     if (Parser.getTok().isNot(AsmToken::Integer))
3799       Parser.Lex(); // Eat '#' or '$'.
3800     SMLoc Loc = Parser.getTok().getLoc();
3801 
3802     const MCExpr *ISBarrierID;
3803     if (getParser().parseExpression(ISBarrierID)) {
3804       Error(Loc, "illegal expression");
3805       return MatchOperand_ParseFail;
3806     }
3807 
3808     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3809     if (!CE) {
3810       Error(Loc, "constant expression expected");
3811       return MatchOperand_ParseFail;
3812     }
3813 
3814     int Val = CE->getValue();
3815     if (Val & ~0xf) {
3816       Error(Loc, "immediate value out of range");
3817       return MatchOperand_ParseFail;
3818     }
3819 
3820     Opt = ARM_ISB::RESERVED_0 + Val;
3821   } else
3822     return MatchOperand_ParseFail;
3823 
3824   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3825           (ARM_ISB::InstSyncBOpt)Opt, S));
3826   return MatchOperand_Success;
3827 }
3828 
3829 
3830 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3831 ARMAsmParser::OperandMatchResultTy
3832 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3833   SMLoc S = Parser.getTok().getLoc();
3834   const AsmToken &Tok = Parser.getTok();
3835   if (!Tok.is(AsmToken::Identifier))
3836     return MatchOperand_NoMatch;
3837   StringRef IFlagsStr = Tok.getString();
3838 
3839   // An iflags string of "none" is interpreted to mean that none of the AIF
3840   // bits are set.  Not a terribly useful instruction, but a valid encoding.
3841   unsigned IFlags = 0;
3842   if (IFlagsStr != "none") {
3843         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3844       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3845         .Case("a", ARM_PROC::A)
3846         .Case("i", ARM_PROC::I)
3847         .Case("f", ARM_PROC::F)
3848         .Default(~0U);
3849 
3850       // If some specific iflag is already set, it means that some letter is
3851       // present more than once, this is not acceptable.
3852       if (Flag == ~0U || (IFlags & Flag))
3853         return MatchOperand_NoMatch;
3854 
3855       IFlags |= Flag;
3856     }
3857   }
3858 
3859   Parser.Lex(); // Eat identifier token.
3860   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3861   return MatchOperand_Success;
3862 }
3863 
3864 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3865 ARMAsmParser::OperandMatchResultTy
3866 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3867   SMLoc S = Parser.getTok().getLoc();
3868   const AsmToken &Tok = Parser.getTok();
3869   if (!Tok.is(AsmToken::Identifier))
3870     return MatchOperand_NoMatch;
3871   StringRef Mask = Tok.getString();
3872 
3873   if (isMClass()) {
3874     // See ARMv6-M 10.1.1
3875     std::string Name = Mask.lower();
3876     unsigned FlagsVal = StringSwitch<unsigned>(Name)
3877       // Note: in the documentation:
3878       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3879       //  for MSR APSR_nzcvq.
3880       // but we do make it an alias here.  This is so to get the "mask encoding"
3881       // bits correct on MSR APSR writes.
3882       //
3883       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3884       // should really only be allowed when writing a special register.  Note
3885       // they get dropped in the MRS instruction reading a special register as
3886       // the SYSm field is only 8 bits.
3887       //
3888       // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3889       // includes the DSP extension but that is not checked.
3890       .Case("apsr", 0x800)
3891       .Case("apsr_nzcvq", 0x800)
3892       .Case("apsr_g", 0x400)
3893       .Case("apsr_nzcvqg", 0xc00)
3894       .Case("iapsr", 0x801)
3895       .Case("iapsr_nzcvq", 0x801)
3896       .Case("iapsr_g", 0x401)
3897       .Case("iapsr_nzcvqg", 0xc01)
3898       .Case("eapsr", 0x802)
3899       .Case("eapsr_nzcvq", 0x802)
3900       .Case("eapsr_g", 0x402)
3901       .Case("eapsr_nzcvqg", 0xc02)
3902       .Case("xpsr", 0x803)
3903       .Case("xpsr_nzcvq", 0x803)
3904       .Case("xpsr_g", 0x403)
3905       .Case("xpsr_nzcvqg", 0xc03)
3906       .Case("ipsr", 0x805)
3907       .Case("epsr", 0x806)
3908       .Case("iepsr", 0x807)
3909       .Case("msp", 0x808)
3910       .Case("psp", 0x809)
3911       .Case("primask", 0x810)
3912       .Case("basepri", 0x811)
3913       .Case("basepri_max", 0x812)
3914       .Case("faultmask", 0x813)
3915       .Case("control", 0x814)
3916       .Default(~0U);
3917 
3918     if (FlagsVal == ~0U)
3919       return MatchOperand_NoMatch;
3920 
3921     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3922       // basepri, basepri_max and faultmask only valid for V7m.
3923       return MatchOperand_NoMatch;
3924 
3925     Parser.Lex(); // Eat identifier token.
3926     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3927     return MatchOperand_Success;
3928   }
3929 
3930   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3931   size_t Start = 0, Next = Mask.find('_');
3932   StringRef Flags = "";
3933   std::string SpecReg = Mask.slice(Start, Next).lower();
3934   if (Next != StringRef::npos)
3935     Flags = Mask.slice(Next+1, Mask.size());
3936 
3937   // FlagsVal contains the complete mask:
3938   // 3-0: Mask
3939   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3940   unsigned FlagsVal = 0;
3941 
3942   if (SpecReg == "apsr") {
3943     FlagsVal = StringSwitch<unsigned>(Flags)
3944     .Case("nzcvq",  0x8) // same as CPSR_f
3945     .Case("g",      0x4) // same as CPSR_s
3946     .Case("nzcvqg", 0xc) // same as CPSR_fs
3947     .Default(~0U);
3948 
3949     if (FlagsVal == ~0U) {
3950       if (!Flags.empty())
3951         return MatchOperand_NoMatch;
3952       else
3953         FlagsVal = 8; // No flag
3954     }
3955   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3956     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3957     if (Flags == "all" || Flags == "")
3958       Flags = "fc";
3959     for (int i = 0, e = Flags.size(); i != e; ++i) {
3960       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3961       .Case("c", 1)
3962       .Case("x", 2)
3963       .Case("s", 4)
3964       .Case("f", 8)
3965       .Default(~0U);
3966 
3967       // If some specific flag is already set, it means that some letter is
3968       // present more than once, this is not acceptable.
3969       if (FlagsVal == ~0U || (FlagsVal & Flag))
3970         return MatchOperand_NoMatch;
3971       FlagsVal |= Flag;
3972     }
3973   } else // No match for special register.
3974     return MatchOperand_NoMatch;
3975 
3976   // Special register without flags is NOT equivalent to "fc" flags.
3977   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3978   // two lines would enable gas compatibility at the expense of breaking
3979   // round-tripping.
3980   //
3981   // if (!FlagsVal)
3982   //  FlagsVal = 0x9;
3983 
3984   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3985   if (SpecReg == "spsr")
3986     FlagsVal |= 16;
3987 
3988   Parser.Lex(); // Eat identifier token.
3989   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3990   return MatchOperand_Success;
3991 }
3992 
3993 ARMAsmParser::OperandMatchResultTy
3994 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
3995                           int High) {
3996   const AsmToken &Tok = Parser.getTok();
3997   if (Tok.isNot(AsmToken::Identifier)) {
3998     Error(Parser.getTok().getLoc(), Op + " operand expected.");
3999     return MatchOperand_ParseFail;
4000   }
4001   StringRef ShiftName = Tok.getString();
4002   std::string LowerOp = Op.lower();
4003   std::string UpperOp = Op.upper();
4004   if (ShiftName != LowerOp && ShiftName != UpperOp) {
4005     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4006     return MatchOperand_ParseFail;
4007   }
4008   Parser.Lex(); // Eat shift type token.
4009 
4010   // There must be a '#' and a shift amount.
4011   if (Parser.getTok().isNot(AsmToken::Hash) &&
4012       Parser.getTok().isNot(AsmToken::Dollar)) {
4013     Error(Parser.getTok().getLoc(), "'#' expected");
4014     return MatchOperand_ParseFail;
4015   }
4016   Parser.Lex(); // Eat hash token.
4017 
4018   const MCExpr *ShiftAmount;
4019   SMLoc Loc = Parser.getTok().getLoc();
4020   SMLoc EndLoc;
4021   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4022     Error(Loc, "illegal expression");
4023     return MatchOperand_ParseFail;
4024   }
4025   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4026   if (!CE) {
4027     Error(Loc, "constant expression expected");
4028     return MatchOperand_ParseFail;
4029   }
4030   int Val = CE->getValue();
4031   if (Val < Low || Val > High) {
4032     Error(Loc, "immediate value out of range");
4033     return MatchOperand_ParseFail;
4034   }
4035 
4036   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4037 
4038   return MatchOperand_Success;
4039 }
4040 
4041 ARMAsmParser::OperandMatchResultTy
4042 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4043   const AsmToken &Tok = Parser.getTok();
4044   SMLoc S = Tok.getLoc();
4045   if (Tok.isNot(AsmToken::Identifier)) {
4046     Error(S, "'be' or 'le' operand expected");
4047     return MatchOperand_ParseFail;
4048   }
4049   int Val = StringSwitch<int>(Tok.getString().lower())
4050     .Case("be", 1)
4051     .Case("le", 0)
4052     .Default(-1);
4053   Parser.Lex(); // Eat the token.
4054 
4055   if (Val == -1) {
4056     Error(S, "'be' or 'le' operand expected");
4057     return MatchOperand_ParseFail;
4058   }
4059   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4060                                                                   getContext()),
4061                                            S, Tok.getEndLoc()));
4062   return MatchOperand_Success;
4063 }
4064 
4065 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4066 /// instructions. Legal values are:
4067 ///     lsl #n  'n' in [0,31]
4068 ///     asr #n  'n' in [1,32]
4069 ///             n == 32 encoded as n == 0.
4070 ARMAsmParser::OperandMatchResultTy
4071 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4072   const AsmToken &Tok = Parser.getTok();
4073   SMLoc S = Tok.getLoc();
4074   if (Tok.isNot(AsmToken::Identifier)) {
4075     Error(S, "shift operator 'asr' or 'lsl' expected");
4076     return MatchOperand_ParseFail;
4077   }
4078   StringRef ShiftName = Tok.getString();
4079   bool isASR;
4080   if (ShiftName == "lsl" || ShiftName == "LSL")
4081     isASR = false;
4082   else if (ShiftName == "asr" || ShiftName == "ASR")
4083     isASR = true;
4084   else {
4085     Error(S, "shift operator 'asr' or 'lsl' expected");
4086     return MatchOperand_ParseFail;
4087   }
4088   Parser.Lex(); // Eat the operator.
4089 
4090   // A '#' and a shift amount.
4091   if (Parser.getTok().isNot(AsmToken::Hash) &&
4092       Parser.getTok().isNot(AsmToken::Dollar)) {
4093     Error(Parser.getTok().getLoc(), "'#' expected");
4094     return MatchOperand_ParseFail;
4095   }
4096   Parser.Lex(); // Eat hash token.
4097   SMLoc ExLoc = Parser.getTok().getLoc();
4098 
4099   const MCExpr *ShiftAmount;
4100   SMLoc EndLoc;
4101   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4102     Error(ExLoc, "malformed shift expression");
4103     return MatchOperand_ParseFail;
4104   }
4105   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4106   if (!CE) {
4107     Error(ExLoc, "shift amount must be an immediate");
4108     return MatchOperand_ParseFail;
4109   }
4110 
4111   int64_t Val = CE->getValue();
4112   if (isASR) {
4113     // Shift amount must be in [1,32]
4114     if (Val < 1 || Val > 32) {
4115       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4116       return MatchOperand_ParseFail;
4117     }
4118     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4119     if (isThumb() && Val == 32) {
4120       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4121       return MatchOperand_ParseFail;
4122     }
4123     if (Val == 32) Val = 0;
4124   } else {
4125     // Shift amount must be in [1,32]
4126     if (Val < 0 || Val > 31) {
4127       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4128       return MatchOperand_ParseFail;
4129     }
4130   }
4131 
4132   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4133 
4134   return MatchOperand_Success;
4135 }
4136 
4137 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4138 /// of instructions. Legal values are:
4139 ///     ror #n  'n' in {0, 8, 16, 24}
4140 ARMAsmParser::OperandMatchResultTy
4141 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4142   const AsmToken &Tok = Parser.getTok();
4143   SMLoc S = Tok.getLoc();
4144   if (Tok.isNot(AsmToken::Identifier))
4145     return MatchOperand_NoMatch;
4146   StringRef ShiftName = Tok.getString();
4147   if (ShiftName != "ror" && ShiftName != "ROR")
4148     return MatchOperand_NoMatch;
4149   Parser.Lex(); // Eat the operator.
4150 
4151   // A '#' and a rotate amount.
4152   if (Parser.getTok().isNot(AsmToken::Hash) &&
4153       Parser.getTok().isNot(AsmToken::Dollar)) {
4154     Error(Parser.getTok().getLoc(), "'#' expected");
4155     return MatchOperand_ParseFail;
4156   }
4157   Parser.Lex(); // Eat hash token.
4158   SMLoc ExLoc = Parser.getTok().getLoc();
4159 
4160   const MCExpr *ShiftAmount;
4161   SMLoc EndLoc;
4162   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4163     Error(ExLoc, "malformed rotate expression");
4164     return MatchOperand_ParseFail;
4165   }
4166   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4167   if (!CE) {
4168     Error(ExLoc, "rotate amount must be an immediate");
4169     return MatchOperand_ParseFail;
4170   }
4171 
4172   int64_t Val = CE->getValue();
4173   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4174   // normally, zero is represented in asm by omitting the rotate operand
4175   // entirely.
4176   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4177     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4178     return MatchOperand_ParseFail;
4179   }
4180 
4181   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4182 
4183   return MatchOperand_Success;
4184 }
4185 
4186 ARMAsmParser::OperandMatchResultTy
4187 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4188   SMLoc S = Parser.getTok().getLoc();
4189   // The bitfield descriptor is really two operands, the LSB and the width.
4190   if (Parser.getTok().isNot(AsmToken::Hash) &&
4191       Parser.getTok().isNot(AsmToken::Dollar)) {
4192     Error(Parser.getTok().getLoc(), "'#' expected");
4193     return MatchOperand_ParseFail;
4194   }
4195   Parser.Lex(); // Eat hash token.
4196 
4197   const MCExpr *LSBExpr;
4198   SMLoc E = Parser.getTok().getLoc();
4199   if (getParser().parseExpression(LSBExpr)) {
4200     Error(E, "malformed immediate expression");
4201     return MatchOperand_ParseFail;
4202   }
4203   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4204   if (!CE) {
4205     Error(E, "'lsb' operand must be an immediate");
4206     return MatchOperand_ParseFail;
4207   }
4208 
4209   int64_t LSB = CE->getValue();
4210   // The LSB must be in the range [0,31]
4211   if (LSB < 0 || LSB > 31) {
4212     Error(E, "'lsb' operand must be in the range [0,31]");
4213     return MatchOperand_ParseFail;
4214   }
4215   E = Parser.getTok().getLoc();
4216 
4217   // Expect another immediate operand.
4218   if (Parser.getTok().isNot(AsmToken::Comma)) {
4219     Error(Parser.getTok().getLoc(), "too few operands");
4220     return MatchOperand_ParseFail;
4221   }
4222   Parser.Lex(); // Eat hash token.
4223   if (Parser.getTok().isNot(AsmToken::Hash) &&
4224       Parser.getTok().isNot(AsmToken::Dollar)) {
4225     Error(Parser.getTok().getLoc(), "'#' expected");
4226     return MatchOperand_ParseFail;
4227   }
4228   Parser.Lex(); // Eat hash token.
4229 
4230   const MCExpr *WidthExpr;
4231   SMLoc EndLoc;
4232   if (getParser().parseExpression(WidthExpr, EndLoc)) {
4233     Error(E, "malformed immediate expression");
4234     return MatchOperand_ParseFail;
4235   }
4236   CE = dyn_cast<MCConstantExpr>(WidthExpr);
4237   if (!CE) {
4238     Error(E, "'width' operand must be an immediate");
4239     return MatchOperand_ParseFail;
4240   }
4241 
4242   int64_t Width = CE->getValue();
4243   // The LSB must be in the range [1,32-lsb]
4244   if (Width < 1 || Width > 32 - LSB) {
4245     Error(E, "'width' operand must be in the range [1,32-lsb]");
4246     return MatchOperand_ParseFail;
4247   }
4248 
4249   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4250 
4251   return MatchOperand_Success;
4252 }
4253 
4254 ARMAsmParser::OperandMatchResultTy
4255 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4256   // Check for a post-index addressing register operand. Specifically:
4257   // postidx_reg := '+' register {, shift}
4258   //              | '-' register {, shift}
4259   //              | register {, shift}
4260 
4261   // This method must return MatchOperand_NoMatch without consuming any tokens
4262   // in the case where there is no match, as other alternatives take other
4263   // parse methods.
4264   AsmToken Tok = Parser.getTok();
4265   SMLoc S = Tok.getLoc();
4266   bool haveEaten = false;
4267   bool isAdd = true;
4268   if (Tok.is(AsmToken::Plus)) {
4269     Parser.Lex(); // Eat the '+' token.
4270     haveEaten = true;
4271   } else if (Tok.is(AsmToken::Minus)) {
4272     Parser.Lex(); // Eat the '-' token.
4273     isAdd = false;
4274     haveEaten = true;
4275   }
4276 
4277   SMLoc E = Parser.getTok().getEndLoc();
4278   int Reg = tryParseRegister();
4279   if (Reg == -1) {
4280     if (!haveEaten)
4281       return MatchOperand_NoMatch;
4282     Error(Parser.getTok().getLoc(), "register expected");
4283     return MatchOperand_ParseFail;
4284   }
4285 
4286   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4287   unsigned ShiftImm = 0;
4288   if (Parser.getTok().is(AsmToken::Comma)) {
4289     Parser.Lex(); // Eat the ','.
4290     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4291       return MatchOperand_ParseFail;
4292 
4293     // FIXME: Only approximates end...may include intervening whitespace.
4294     E = Parser.getTok().getLoc();
4295   }
4296 
4297   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4298                                                   ShiftImm, S, E));
4299 
4300   return MatchOperand_Success;
4301 }
4302 
4303 ARMAsmParser::OperandMatchResultTy
4304 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4305   // Check for a post-index addressing register operand. Specifically:
4306   // am3offset := '+' register
4307   //              | '-' register
4308   //              | register
4309   //              | # imm
4310   //              | # + imm
4311   //              | # - imm
4312 
4313   // This method must return MatchOperand_NoMatch without consuming any tokens
4314   // in the case where there is no match, as other alternatives take other
4315   // parse methods.
4316   AsmToken Tok = Parser.getTok();
4317   SMLoc S = Tok.getLoc();
4318 
4319   // Do immediates first, as we always parse those if we have a '#'.
4320   if (Parser.getTok().is(AsmToken::Hash) ||
4321       Parser.getTok().is(AsmToken::Dollar)) {
4322     Parser.Lex(); // Eat '#' or '$'.
4323     // Explicitly look for a '-', as we need to encode negative zero
4324     // differently.
4325     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4326     const MCExpr *Offset;
4327     SMLoc E;
4328     if (getParser().parseExpression(Offset, E))
4329       return MatchOperand_ParseFail;
4330     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4331     if (!CE) {
4332       Error(S, "constant expression expected");
4333       return MatchOperand_ParseFail;
4334     }
4335     // Negative zero is encoded as the flag value INT32_MIN.
4336     int32_t Val = CE->getValue();
4337     if (isNegative && Val == 0)
4338       Val = INT32_MIN;
4339 
4340     Operands.push_back(
4341       ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4342 
4343     return MatchOperand_Success;
4344   }
4345 
4346 
4347   bool haveEaten = false;
4348   bool isAdd = true;
4349   if (Tok.is(AsmToken::Plus)) {
4350     Parser.Lex(); // Eat the '+' token.
4351     haveEaten = true;
4352   } else if (Tok.is(AsmToken::Minus)) {
4353     Parser.Lex(); // Eat the '-' token.
4354     isAdd = false;
4355     haveEaten = true;
4356   }
4357 
4358   Tok = Parser.getTok();
4359   int Reg = tryParseRegister();
4360   if (Reg == -1) {
4361     if (!haveEaten)
4362       return MatchOperand_NoMatch;
4363     Error(Tok.getLoc(), "register expected");
4364     return MatchOperand_ParseFail;
4365   }
4366 
4367   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4368                                                   0, S, Tok.getEndLoc()));
4369 
4370   return MatchOperand_Success;
4371 }
4372 
4373 /// Convert parsed operands to MCInst.  Needed here because this instruction
4374 /// only has two register operands, but multiplication is commutative so
4375 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4376 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4377                                     const OperandVector &Operands) {
4378   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4379   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4380   // If we have a three-operand form, make sure to set Rn to be the operand
4381   // that isn't the same as Rd.
4382   unsigned RegOp = 4;
4383   if (Operands.size() == 6 &&
4384       ((ARMOperand &)*Operands[4]).getReg() ==
4385           ((ARMOperand &)*Operands[3]).getReg())
4386     RegOp = 5;
4387   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4388   Inst.addOperand(Inst.getOperand(0));
4389   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4390 }
4391 
4392 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4393                                     const OperandVector &Operands) {
4394   int CondOp = -1, ImmOp = -1;
4395   switch(Inst.getOpcode()) {
4396     case ARM::tB:
4397     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4398 
4399     case ARM::t2B:
4400     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4401 
4402     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4403   }
4404   // first decide whether or not the branch should be conditional
4405   // by looking at it's location relative to an IT block
4406   if(inITBlock()) {
4407     // inside an IT block we cannot have any conditional branches. any
4408     // such instructions needs to be converted to unconditional form
4409     switch(Inst.getOpcode()) {
4410       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4411       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4412     }
4413   } else {
4414     // outside IT blocks we can only have unconditional branches with AL
4415     // condition code or conditional branches with non-AL condition code
4416     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4417     switch(Inst.getOpcode()) {
4418       case ARM::tB:
4419       case ARM::tBcc:
4420         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4421         break;
4422       case ARM::t2B:
4423       case ARM::t2Bcc:
4424         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4425         break;
4426     }
4427   }
4428 
4429   // now decide on encoding size based on branch target range
4430   switch(Inst.getOpcode()) {
4431     // classify tB as either t2B or t1B based on range of immediate operand
4432     case ARM::tB: {
4433       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4434       if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4435         Inst.setOpcode(ARM::t2B);
4436       break;
4437     }
4438     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4439     case ARM::tBcc: {
4440       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4441       if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4442         Inst.setOpcode(ARM::t2Bcc);
4443       break;
4444     }
4445   }
4446   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4447   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4448 }
4449 
4450 /// Parse an ARM memory expression, return false if successful else return true
4451 /// or an error.  The first token must be a '[' when called.
4452 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4453   SMLoc S, E;
4454   assert(Parser.getTok().is(AsmToken::LBrac) &&
4455          "Token is not a Left Bracket");
4456   S = Parser.getTok().getLoc();
4457   Parser.Lex(); // Eat left bracket token.
4458 
4459   const AsmToken &BaseRegTok = Parser.getTok();
4460   int BaseRegNum = tryParseRegister();
4461   if (BaseRegNum == -1)
4462     return Error(BaseRegTok.getLoc(), "register expected");
4463 
4464   // The next token must either be a comma, a colon or a closing bracket.
4465   const AsmToken &Tok = Parser.getTok();
4466   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4467       !Tok.is(AsmToken::RBrac))
4468     return Error(Tok.getLoc(), "malformed memory operand");
4469 
4470   if (Tok.is(AsmToken::RBrac)) {
4471     E = Tok.getEndLoc();
4472     Parser.Lex(); // Eat right bracket token.
4473 
4474     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4475                                              ARM_AM::no_shift, 0, 0, false,
4476                                              S, E));
4477 
4478     // If there's a pre-indexing writeback marker, '!', just add it as a token
4479     // operand. It's rather odd, but syntactically valid.
4480     if (Parser.getTok().is(AsmToken::Exclaim)) {
4481       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4482       Parser.Lex(); // Eat the '!'.
4483     }
4484 
4485     return false;
4486   }
4487 
4488   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4489          "Lost colon or comma in memory operand?!");
4490   if (Tok.is(AsmToken::Comma)) {
4491     Parser.Lex(); // Eat the comma.
4492   }
4493 
4494   // If we have a ':', it's an alignment specifier.
4495   if (Parser.getTok().is(AsmToken::Colon)) {
4496     Parser.Lex(); // Eat the ':'.
4497     E = Parser.getTok().getLoc();
4498     SMLoc AlignmentLoc = Tok.getLoc();
4499 
4500     const MCExpr *Expr;
4501     if (getParser().parseExpression(Expr))
4502      return true;
4503 
4504     // The expression has to be a constant. Memory references with relocations
4505     // don't come through here, as they use the <label> forms of the relevant
4506     // instructions.
4507     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4508     if (!CE)
4509       return Error (E, "constant expression expected");
4510 
4511     unsigned Align = 0;
4512     switch (CE->getValue()) {
4513     default:
4514       return Error(E,
4515                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4516     case 16:  Align = 2; break;
4517     case 32:  Align = 4; break;
4518     case 64:  Align = 8; break;
4519     case 128: Align = 16; break;
4520     case 256: Align = 32; break;
4521     }
4522 
4523     // Now we should have the closing ']'
4524     if (Parser.getTok().isNot(AsmToken::RBrac))
4525       return Error(Parser.getTok().getLoc(), "']' expected");
4526     E = Parser.getTok().getEndLoc();
4527     Parser.Lex(); // Eat right bracket token.
4528 
4529     // Don't worry about range checking the value here. That's handled by
4530     // the is*() predicates.
4531     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4532                                              ARM_AM::no_shift, 0, Align,
4533                                              false, S, E, AlignmentLoc));
4534 
4535     // If there's a pre-indexing writeback marker, '!', just add it as a token
4536     // operand.
4537     if (Parser.getTok().is(AsmToken::Exclaim)) {
4538       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4539       Parser.Lex(); // Eat the '!'.
4540     }
4541 
4542     return false;
4543   }
4544 
4545   // If we have a '#', it's an immediate offset, else assume it's a register
4546   // offset. Be friendly and also accept a plain integer (without a leading
4547   // hash) for gas compatibility.
4548   if (Parser.getTok().is(AsmToken::Hash) ||
4549       Parser.getTok().is(AsmToken::Dollar) ||
4550       Parser.getTok().is(AsmToken::Integer)) {
4551     if (Parser.getTok().isNot(AsmToken::Integer))
4552       Parser.Lex(); // Eat '#' or '$'.
4553     E = Parser.getTok().getLoc();
4554 
4555     bool isNegative = getParser().getTok().is(AsmToken::Minus);
4556     const MCExpr *Offset;
4557     if (getParser().parseExpression(Offset))
4558      return true;
4559 
4560     // The expression has to be a constant. Memory references with relocations
4561     // don't come through here, as they use the <label> forms of the relevant
4562     // instructions.
4563     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4564     if (!CE)
4565       return Error (E, "constant expression expected");
4566 
4567     // If the constant was #-0, represent it as INT32_MIN.
4568     int32_t Val = CE->getValue();
4569     if (isNegative && Val == 0)
4570       CE = MCConstantExpr::Create(INT32_MIN, getContext());
4571 
4572     // Now we should have the closing ']'
4573     if (Parser.getTok().isNot(AsmToken::RBrac))
4574       return Error(Parser.getTok().getLoc(), "']' expected");
4575     E = Parser.getTok().getEndLoc();
4576     Parser.Lex(); // Eat right bracket token.
4577 
4578     // Don't worry about range checking the value here. That's handled by
4579     // the is*() predicates.
4580     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4581                                              ARM_AM::no_shift, 0, 0,
4582                                              false, S, E));
4583 
4584     // If there's a pre-indexing writeback marker, '!', just add it as a token
4585     // operand.
4586     if (Parser.getTok().is(AsmToken::Exclaim)) {
4587       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4588       Parser.Lex(); // Eat the '!'.
4589     }
4590 
4591     return false;
4592   }
4593 
4594   // The register offset is optionally preceded by a '+' or '-'
4595   bool isNegative = false;
4596   if (Parser.getTok().is(AsmToken::Minus)) {
4597     isNegative = true;
4598     Parser.Lex(); // Eat the '-'.
4599   } else if (Parser.getTok().is(AsmToken::Plus)) {
4600     // Nothing to do.
4601     Parser.Lex(); // Eat the '+'.
4602   }
4603 
4604   E = Parser.getTok().getLoc();
4605   int OffsetRegNum = tryParseRegister();
4606   if (OffsetRegNum == -1)
4607     return Error(E, "register expected");
4608 
4609   // If there's a shift operator, handle it.
4610   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4611   unsigned ShiftImm = 0;
4612   if (Parser.getTok().is(AsmToken::Comma)) {
4613     Parser.Lex(); // Eat the ','.
4614     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4615       return true;
4616   }
4617 
4618   // Now we should have the closing ']'
4619   if (Parser.getTok().isNot(AsmToken::RBrac))
4620     return Error(Parser.getTok().getLoc(), "']' expected");
4621   E = Parser.getTok().getEndLoc();
4622   Parser.Lex(); // Eat right bracket token.
4623 
4624   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4625                                            ShiftType, ShiftImm, 0, isNegative,
4626                                            S, E));
4627 
4628   // If there's a pre-indexing writeback marker, '!', just add it as a token
4629   // operand.
4630   if (Parser.getTok().is(AsmToken::Exclaim)) {
4631     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4632     Parser.Lex(); // Eat the '!'.
4633   }
4634 
4635   return false;
4636 }
4637 
4638 /// parseMemRegOffsetShift - one of these two:
4639 ///   ( lsl | lsr | asr | ror ) , # shift_amount
4640 ///   rrx
4641 /// return true if it parses a shift otherwise it returns false.
4642 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4643                                           unsigned &Amount) {
4644   SMLoc Loc = Parser.getTok().getLoc();
4645   const AsmToken &Tok = Parser.getTok();
4646   if (Tok.isNot(AsmToken::Identifier))
4647     return true;
4648   StringRef ShiftName = Tok.getString();
4649   if (ShiftName == "lsl" || ShiftName == "LSL" ||
4650       ShiftName == "asl" || ShiftName == "ASL")
4651     St = ARM_AM::lsl;
4652   else if (ShiftName == "lsr" || ShiftName == "LSR")
4653     St = ARM_AM::lsr;
4654   else if (ShiftName == "asr" || ShiftName == "ASR")
4655     St = ARM_AM::asr;
4656   else if (ShiftName == "ror" || ShiftName == "ROR")
4657     St = ARM_AM::ror;
4658   else if (ShiftName == "rrx" || ShiftName == "RRX")
4659     St = ARM_AM::rrx;
4660   else
4661     return Error(Loc, "illegal shift operator");
4662   Parser.Lex(); // Eat shift type token.
4663 
4664   // rrx stands alone.
4665   Amount = 0;
4666   if (St != ARM_AM::rrx) {
4667     Loc = Parser.getTok().getLoc();
4668     // A '#' and a shift amount.
4669     const AsmToken &HashTok = Parser.getTok();
4670     if (HashTok.isNot(AsmToken::Hash) &&
4671         HashTok.isNot(AsmToken::Dollar))
4672       return Error(HashTok.getLoc(), "'#' expected");
4673     Parser.Lex(); // Eat hash token.
4674 
4675     const MCExpr *Expr;
4676     if (getParser().parseExpression(Expr))
4677       return true;
4678     // Range check the immediate.
4679     // lsl, ror: 0 <= imm <= 31
4680     // lsr, asr: 0 <= imm <= 32
4681     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4682     if (!CE)
4683       return Error(Loc, "shift amount must be an immediate");
4684     int64_t Imm = CE->getValue();
4685     if (Imm < 0 ||
4686         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4687         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4688       return Error(Loc, "immediate shift value out of range");
4689     // If <ShiftTy> #0, turn it into a no_shift.
4690     if (Imm == 0)
4691       St = ARM_AM::lsl;
4692     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4693     if (Imm == 32)
4694       Imm = 0;
4695     Amount = Imm;
4696   }
4697 
4698   return false;
4699 }
4700 
4701 /// parseFPImm - A floating point immediate expression operand.
4702 ARMAsmParser::OperandMatchResultTy
4703 ARMAsmParser::parseFPImm(OperandVector &Operands) {
4704   // Anything that can accept a floating point constant as an operand
4705   // needs to go through here, as the regular parseExpression is
4706   // integer only.
4707   //
4708   // This routine still creates a generic Immediate operand, containing
4709   // a bitcast of the 64-bit floating point value. The various operands
4710   // that accept floats can check whether the value is valid for them
4711   // via the standard is*() predicates.
4712 
4713   SMLoc S = Parser.getTok().getLoc();
4714 
4715   if (Parser.getTok().isNot(AsmToken::Hash) &&
4716       Parser.getTok().isNot(AsmToken::Dollar))
4717     return MatchOperand_NoMatch;
4718 
4719   // Disambiguate the VMOV forms that can accept an FP immediate.
4720   // vmov.f32 <sreg>, #imm
4721   // vmov.f64 <dreg>, #imm
4722   // vmov.f32 <dreg>, #imm  @ vector f32x2
4723   // vmov.f32 <qreg>, #imm  @ vector f32x4
4724   //
4725   // There are also the NEON VMOV instructions which expect an
4726   // integer constant. Make sure we don't try to parse an FPImm
4727   // for these:
4728   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4729   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
4730   bool isVmovf = TyOp.isToken() &&
4731                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
4732   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
4733   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
4734                                          Mnemonic.getToken() == "fconsts");
4735   if (!(isVmovf || isFconst))
4736     return MatchOperand_NoMatch;
4737 
4738   Parser.Lex(); // Eat '#' or '$'.
4739 
4740   // Handle negation, as that still comes through as a separate token.
4741   bool isNegative = false;
4742   if (Parser.getTok().is(AsmToken::Minus)) {
4743     isNegative = true;
4744     Parser.Lex();
4745   }
4746   const AsmToken &Tok = Parser.getTok();
4747   SMLoc Loc = Tok.getLoc();
4748   if (Tok.is(AsmToken::Real) && isVmovf) {
4749     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4750     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4751     // If we had a '-' in front, toggle the sign bit.
4752     IntVal ^= (uint64_t)isNegative << 31;
4753     Parser.Lex(); // Eat the token.
4754     Operands.push_back(ARMOperand::CreateImm(
4755           MCConstantExpr::Create(IntVal, getContext()),
4756           S, Parser.getTok().getLoc()));
4757     return MatchOperand_Success;
4758   }
4759   // Also handle plain integers. Instructions which allow floating point
4760   // immediates also allow a raw encoded 8-bit value.
4761   if (Tok.is(AsmToken::Integer) && isFconst) {
4762     int64_t Val = Tok.getIntVal();
4763     Parser.Lex(); // Eat the token.
4764     if (Val > 255 || Val < 0) {
4765       Error(Loc, "encoded floating point value out of range");
4766       return MatchOperand_ParseFail;
4767     }
4768     float RealVal = ARM_AM::getFPImmFloat(Val);
4769     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4770 
4771     Operands.push_back(ARMOperand::CreateImm(
4772         MCConstantExpr::Create(Val, getContext()), S,
4773         Parser.getTok().getLoc()));
4774     return MatchOperand_Success;
4775   }
4776 
4777   Error(Loc, "invalid floating point immediate");
4778   return MatchOperand_ParseFail;
4779 }
4780 
4781 /// Parse a arm instruction operand.  For now this parses the operand regardless
4782 /// of the mnemonic.
4783 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
4784   SMLoc S, E;
4785 
4786   // Check if the current operand has a custom associated parser, if so, try to
4787   // custom parse the operand, or fallback to the general approach.
4788   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4789   if (ResTy == MatchOperand_Success)
4790     return false;
4791   // If there wasn't a custom match, try the generic matcher below. Otherwise,
4792   // there was a match, but an error occurred, in which case, just return that
4793   // the operand parsing failed.
4794   if (ResTy == MatchOperand_ParseFail)
4795     return true;
4796 
4797   switch (getLexer().getKind()) {
4798   default:
4799     Error(Parser.getTok().getLoc(), "unexpected token in operand");
4800     return true;
4801   case AsmToken::Identifier: {
4802     // If we've seen a branch mnemonic, the next operand must be a label.  This
4803     // is true even if the label is a register name.  So "br r1" means branch to
4804     // label "r1".
4805     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4806     if (!ExpectLabel) {
4807       if (!tryParseRegisterWithWriteBack(Operands))
4808         return false;
4809       int Res = tryParseShiftRegister(Operands);
4810       if (Res == 0) // success
4811         return false;
4812       else if (Res == -1) // irrecoverable error
4813         return true;
4814       // If this is VMRS, check for the apsr_nzcv operand.
4815       if (Mnemonic == "vmrs" &&
4816           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4817         S = Parser.getTok().getLoc();
4818         Parser.Lex();
4819         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4820         return false;
4821       }
4822     }
4823 
4824     // Fall though for the Identifier case that is not a register or a
4825     // special name.
4826   }
4827   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4828   case AsmToken::Integer: // things like 1f and 2b as a branch targets
4829   case AsmToken::String:  // quoted label names.
4830   case AsmToken::Dot: {   // . as a branch target
4831     // This was not a register so parse other operands that start with an
4832     // identifier (like labels) as expressions and create them as immediates.
4833     const MCExpr *IdVal;
4834     S = Parser.getTok().getLoc();
4835     if (getParser().parseExpression(IdVal))
4836       return true;
4837     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4838     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4839     return false;
4840   }
4841   case AsmToken::LBrac:
4842     return parseMemory(Operands);
4843   case AsmToken::LCurly:
4844     return parseRegisterList(Operands);
4845   case AsmToken::Dollar:
4846   case AsmToken::Hash: {
4847     // #42 -> immediate.
4848     S = Parser.getTok().getLoc();
4849     Parser.Lex();
4850 
4851     if (Parser.getTok().isNot(AsmToken::Colon)) {
4852       bool isNegative = Parser.getTok().is(AsmToken::Minus);
4853       const MCExpr *ImmVal;
4854       if (getParser().parseExpression(ImmVal))
4855         return true;
4856       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4857       if (CE) {
4858         int32_t Val = CE->getValue();
4859         if (isNegative && Val == 0)
4860           ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4861       }
4862       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4863       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4864 
4865       // There can be a trailing '!' on operands that we want as a separate
4866       // '!' Token operand. Handle that here. For example, the compatibility
4867       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4868       if (Parser.getTok().is(AsmToken::Exclaim)) {
4869         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4870                                                    Parser.getTok().getLoc()));
4871         Parser.Lex(); // Eat exclaim token
4872       }
4873       return false;
4874     }
4875     // w/ a ':' after the '#', it's just like a plain ':'.
4876     // FALLTHROUGH
4877   }
4878   case AsmToken::Colon: {
4879     // ":lower16:" and ":upper16:" expression prefixes
4880     // FIXME: Check it's an expression prefix,
4881     // e.g. (FOO - :lower16:BAR) isn't legal.
4882     ARMMCExpr::VariantKind RefKind;
4883     if (parsePrefix(RefKind))
4884       return true;
4885 
4886     const MCExpr *SubExprVal;
4887     if (getParser().parseExpression(SubExprVal))
4888       return true;
4889 
4890     const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4891                                               getContext());
4892     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4893     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4894     return false;
4895   }
4896   case AsmToken::Equal: {
4897     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4898       return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4899 
4900     Parser.Lex(); // Eat '='
4901     const MCExpr *SubExprVal;
4902     if (getParser().parseExpression(SubExprVal))
4903       return true;
4904     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4905 
4906     const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4907     Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4908     return false;
4909   }
4910   }
4911 }
4912 
4913 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4914 //  :lower16: and :upper16:.
4915 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4916   RefKind = ARMMCExpr::VK_ARM_None;
4917 
4918   // consume an optional '#' (GNU compatibility)
4919   if (getLexer().is(AsmToken::Hash))
4920     Parser.Lex();
4921 
4922   // :lower16: and :upper16: modifiers
4923   assert(getLexer().is(AsmToken::Colon) && "expected a :");
4924   Parser.Lex(); // Eat ':'
4925 
4926   if (getLexer().isNot(AsmToken::Identifier)) {
4927     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4928     return true;
4929   }
4930 
4931   StringRef IDVal = Parser.getTok().getIdentifier();
4932   if (IDVal == "lower16") {
4933     RefKind = ARMMCExpr::VK_ARM_LO16;
4934   } else if (IDVal == "upper16") {
4935     RefKind = ARMMCExpr::VK_ARM_HI16;
4936   } else {
4937     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4938     return true;
4939   }
4940   Parser.Lex();
4941 
4942   if (getLexer().isNot(AsmToken::Colon)) {
4943     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4944     return true;
4945   }
4946   Parser.Lex(); // Eat the last ':'
4947   return false;
4948 }
4949 
4950 /// \brief Given a mnemonic, split out possible predication code and carry
4951 /// setting letters to form a canonical mnemonic and flags.
4952 //
4953 // FIXME: Would be nice to autogen this.
4954 // FIXME: This is a bit of a maze of special cases.
4955 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4956                                       unsigned &PredicationCode,
4957                                       bool &CarrySetting,
4958                                       unsigned &ProcessorIMod,
4959                                       StringRef &ITMask) {
4960   PredicationCode = ARMCC::AL;
4961   CarrySetting = false;
4962   ProcessorIMod = 0;
4963 
4964   // Ignore some mnemonics we know aren't predicated forms.
4965   //
4966   // FIXME: Would be nice to autogen this.
4967   if ((Mnemonic == "movs" && isThumb()) ||
4968       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4969       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4970       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4971       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4972       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
4973       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4974       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4975       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4976       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4977       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
4978       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4979       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4980     return Mnemonic;
4981 
4982   // First, split out any predication code. Ignore mnemonics we know aren't
4983   // predicated but do have a carry-set and so weren't caught above.
4984   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4985       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4986       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4987       Mnemonic != "sbcs" && Mnemonic != "rscs") {
4988     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4989       .Case("eq", ARMCC::EQ)
4990       .Case("ne", ARMCC::NE)
4991       .Case("hs", ARMCC::HS)
4992       .Case("cs", ARMCC::HS)
4993       .Case("lo", ARMCC::LO)
4994       .Case("cc", ARMCC::LO)
4995       .Case("mi", ARMCC::MI)
4996       .Case("pl", ARMCC::PL)
4997       .Case("vs", ARMCC::VS)
4998       .Case("vc", ARMCC::VC)
4999       .Case("hi", ARMCC::HI)
5000       .Case("ls", ARMCC::LS)
5001       .Case("ge", ARMCC::GE)
5002       .Case("lt", ARMCC::LT)
5003       .Case("gt", ARMCC::GT)
5004       .Case("le", ARMCC::LE)
5005       .Case("al", ARMCC::AL)
5006       .Default(~0U);
5007     if (CC != ~0U) {
5008       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5009       PredicationCode = CC;
5010     }
5011   }
5012 
5013   // Next, determine if we have a carry setting bit. We explicitly ignore all
5014   // the instructions we know end in 's'.
5015   if (Mnemonic.endswith("s") &&
5016       !(Mnemonic == "cps" || Mnemonic == "mls" ||
5017         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5018         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5019         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5020         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5021         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5022         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5023         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5024         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5025         (Mnemonic == "movs" && isThumb()))) {
5026     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5027     CarrySetting = true;
5028   }
5029 
5030   // The "cps" instruction can have a interrupt mode operand which is glued into
5031   // the mnemonic. Check if this is the case, split it and parse the imod op
5032   if (Mnemonic.startswith("cps")) {
5033     // Split out any imod code.
5034     unsigned IMod =
5035       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5036       .Case("ie", ARM_PROC::IE)
5037       .Case("id", ARM_PROC::ID)
5038       .Default(~0U);
5039     if (IMod != ~0U) {
5040       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5041       ProcessorIMod = IMod;
5042     }
5043   }
5044 
5045   // The "it" instruction has the condition mask on the end of the mnemonic.
5046   if (Mnemonic.startswith("it")) {
5047     ITMask = Mnemonic.slice(2, Mnemonic.size());
5048     Mnemonic = Mnemonic.slice(0, 2);
5049   }
5050 
5051   return Mnemonic;
5052 }
5053 
5054 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5055 /// inclusion of carry set or predication code operands.
5056 //
5057 // FIXME: It would be nice to autogen this.
5058 void ARMAsmParser::
5059 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5060                      bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5061   if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5062       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5063       Mnemonic == "add" || Mnemonic == "adc" ||
5064       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5065       Mnemonic == "orr" || Mnemonic == "mvn" ||
5066       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5067       Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5068       Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5069       (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5070                       Mnemonic == "mla" || Mnemonic == "smlal" ||
5071                       Mnemonic == "umlal" || Mnemonic == "umull"))) {
5072     CanAcceptCarrySet = true;
5073   } else
5074     CanAcceptCarrySet = false;
5075 
5076   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5077       Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
5078       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5079       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5080       Mnemonic.startswith("vsel") ||
5081       Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5082       Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5083       Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5084       Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5085       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5086       (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5087     // These mnemonics are never predicable
5088     CanAcceptPredicationCode = false;
5089   } else if (!isThumb()) {
5090     // Some instructions are only predicable in Thumb mode
5091     CanAcceptPredicationCode
5092       = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5093         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5094         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5095         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5096         Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5097         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5098         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5099   } else if (isThumbOne()) {
5100     if (hasV6MOps())
5101       CanAcceptPredicationCode = Mnemonic != "movs";
5102     else
5103       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5104   } else
5105     CanAcceptPredicationCode = true;
5106 }
5107 
5108 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5109                                           OperandVector &Operands) {
5110   // FIXME: This is all horribly hacky. We really need a better way to deal
5111   // with optional operands like this in the matcher table.
5112 
5113   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5114   // another does not. Specifically, the MOVW instruction does not. So we
5115   // special case it here and remove the defaulted (non-setting) cc_out
5116   // operand if that's the instruction we're trying to match.
5117   //
5118   // We do this as post-processing of the explicit operands rather than just
5119   // conditionally adding the cc_out in the first place because we need
5120   // to check the type of the parsed immediate operand.
5121   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5122       !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() &&
5123       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5124       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5125     return true;
5126 
5127   // Register-register 'add' for thumb does not have a cc_out operand
5128   // when there are only two register operands.
5129   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5130       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5131       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5132       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5133     return true;
5134   // Register-register 'add' for thumb does not have a cc_out operand
5135   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5136   // have to check the immediate range here since Thumb2 has a variant
5137   // that can handle a different range and has a cc_out operand.
5138   if (((isThumb() && Mnemonic == "add") ||
5139        (isThumbTwo() && Mnemonic == "sub")) &&
5140       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5141       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5142       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5143       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5144       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5145        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5146     return true;
5147   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5148   // imm0_4095 variant. That's the least-preferred variant when
5149   // selecting via the generic "add" mnemonic, so to know that we
5150   // should remove the cc_out operand, we have to explicitly check that
5151   // it's not one of the other variants. Ugh.
5152   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5153       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5154       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5155       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5156     // Nest conditions rather than one big 'if' statement for readability.
5157     //
5158     // If both registers are low, we're in an IT block, and the immediate is
5159     // in range, we should use encoding T1 instead, which has a cc_out.
5160     if (inITBlock() &&
5161         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5162         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5163         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5164       return false;
5165     // Check against T3. If the second register is the PC, this is an
5166     // alternate form of ADR, which uses encoding T4, so check for that too.
5167     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5168         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5169       return false;
5170 
5171     // Otherwise, we use encoding T4, which does not have a cc_out
5172     // operand.
5173     return true;
5174   }
5175 
5176   // The thumb2 multiply instruction doesn't have a CCOut register, so
5177   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5178   // use the 16-bit encoding or not.
5179   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5180       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5181       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5182       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5183       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5184       // If the registers aren't low regs, the destination reg isn't the
5185       // same as one of the source regs, or the cc_out operand is zero
5186       // outside of an IT block, we have to use the 32-bit encoding, so
5187       // remove the cc_out operand.
5188       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5189        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5190        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5191        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5192                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5193                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5194                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
5195     return true;
5196 
5197   // Also check the 'mul' syntax variant that doesn't specify an explicit
5198   // destination register.
5199   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5200       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5201       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5202       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5203       // If the registers aren't low regs  or the cc_out operand is zero
5204       // outside of an IT block, we have to use the 32-bit encoding, so
5205       // remove the cc_out operand.
5206       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5207        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5208        !inITBlock()))
5209     return true;
5210 
5211 
5212 
5213   // Register-register 'add/sub' for thumb does not have a cc_out operand
5214   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5215   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5216   // right, this will result in better diagnostics (which operand is off)
5217   // anyway.
5218   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5219       (Operands.size() == 5 || Operands.size() == 6) &&
5220       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5221       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5222       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5223       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5224        (Operands.size() == 6 &&
5225         static_cast<ARMOperand &>(*Operands[5]).isImm())))
5226     return true;
5227 
5228   return false;
5229 }
5230 
5231 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5232                                               OperandVector &Operands) {
5233   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5234   unsigned RegIdx = 3;
5235   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5236       static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5237     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5238         static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5239       RegIdx = 4;
5240 
5241     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5242         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5243              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5244          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5245              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5246       return true;
5247   }
5248   return false;
5249 }
5250 
5251 static bool isDataTypeToken(StringRef Tok) {
5252   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5253     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5254     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5255     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5256     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5257     Tok == ".f" || Tok == ".d";
5258 }
5259 
5260 // FIXME: This bit should probably be handled via an explicit match class
5261 // in the .td files that matches the suffix instead of having it be
5262 // a literal string token the way it is now.
5263 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5264   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5265 }
5266 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5267                                  unsigned VariantID);
5268 
5269 static bool RequiresVFPRegListValidation(StringRef Inst,
5270                                          bool &AcceptSinglePrecisionOnly,
5271                                          bool &AcceptDoublePrecisionOnly) {
5272   if (Inst.size() < 7)
5273     return false;
5274 
5275   if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5276     StringRef AddressingMode = Inst.substr(4, 2);
5277     if (AddressingMode == "ia" || AddressingMode == "db" ||
5278         AddressingMode == "ea" || AddressingMode == "fd") {
5279       AcceptSinglePrecisionOnly = Inst[6] == 's';
5280       AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5281       return true;
5282     }
5283   }
5284 
5285   return false;
5286 }
5287 
5288 /// Parse an arm instruction mnemonic followed by its operands.
5289 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5290                                     SMLoc NameLoc, OperandVector &Operands) {
5291   // FIXME: Can this be done via tablegen in some fashion?
5292   bool RequireVFPRegisterListCheck;
5293   bool AcceptSinglePrecisionOnly;
5294   bool AcceptDoublePrecisionOnly;
5295   RequireVFPRegisterListCheck =
5296     RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5297                                  AcceptDoublePrecisionOnly);
5298 
5299   // Apply mnemonic aliases before doing anything else, as the destination
5300   // mnemonic may include suffices and we want to handle them normally.
5301   // The generic tblgen'erated code does this later, at the start of
5302   // MatchInstructionImpl(), but that's too late for aliases that include
5303   // any sort of suffix.
5304   unsigned AvailableFeatures = getAvailableFeatures();
5305   unsigned AssemblerDialect = getParser().getAssemblerDialect();
5306   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5307 
5308   // First check for the ARM-specific .req directive.
5309   if (Parser.getTok().is(AsmToken::Identifier) &&
5310       Parser.getTok().getIdentifier() == ".req") {
5311     parseDirectiveReq(Name, NameLoc);
5312     // We always return 'error' for this, as we're done with this
5313     // statement and don't need to match the 'instruction."
5314     return true;
5315   }
5316 
5317   // Create the leading tokens for the mnemonic, split by '.' characters.
5318   size_t Start = 0, Next = Name.find('.');
5319   StringRef Mnemonic = Name.slice(Start, Next);
5320 
5321   // Split out the predication code and carry setting flag from the mnemonic.
5322   unsigned PredicationCode;
5323   unsigned ProcessorIMod;
5324   bool CarrySetting;
5325   StringRef ITMask;
5326   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5327                            ProcessorIMod, ITMask);
5328 
5329   // In Thumb1, only the branch (B) instruction can be predicated.
5330   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5331     Parser.eatToEndOfStatement();
5332     return Error(NameLoc, "conditional execution not supported in Thumb1");
5333   }
5334 
5335   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5336 
5337   // Handle the IT instruction ITMask. Convert it to a bitmask. This
5338   // is the mask as it will be for the IT encoding if the conditional
5339   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5340   // where the conditional bit0 is zero, the instruction post-processing
5341   // will adjust the mask accordingly.
5342   if (Mnemonic == "it") {
5343     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5344     if (ITMask.size() > 3) {
5345       Parser.eatToEndOfStatement();
5346       return Error(Loc, "too many conditions on IT instruction");
5347     }
5348     unsigned Mask = 8;
5349     for (unsigned i = ITMask.size(); i != 0; --i) {
5350       char pos = ITMask[i - 1];
5351       if (pos != 't' && pos != 'e') {
5352         Parser.eatToEndOfStatement();
5353         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5354       }
5355       Mask >>= 1;
5356       if (ITMask[i - 1] == 't')
5357         Mask |= 8;
5358     }
5359     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5360   }
5361 
5362   // FIXME: This is all a pretty gross hack. We should automatically handle
5363   // optional operands like this via tblgen.
5364 
5365   // Next, add the CCOut and ConditionCode operands, if needed.
5366   //
5367   // For mnemonics which can ever incorporate a carry setting bit or predication
5368   // code, our matching model involves us always generating CCOut and
5369   // ConditionCode operands to match the mnemonic "as written" and then we let
5370   // the matcher deal with finding the right instruction or generating an
5371   // appropriate error.
5372   bool CanAcceptCarrySet, CanAcceptPredicationCode;
5373   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5374 
5375   // If we had a carry-set on an instruction that can't do that, issue an
5376   // error.
5377   if (!CanAcceptCarrySet && CarrySetting) {
5378     Parser.eatToEndOfStatement();
5379     return Error(NameLoc, "instruction '" + Mnemonic +
5380                  "' can not set flags, but 's' suffix specified");
5381   }
5382   // If we had a predication code on an instruction that can't do that, issue an
5383   // error.
5384   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5385     Parser.eatToEndOfStatement();
5386     return Error(NameLoc, "instruction '" + Mnemonic +
5387                  "' is not predicable, but condition code specified");
5388   }
5389 
5390   // Add the carry setting operand, if necessary.
5391   if (CanAcceptCarrySet) {
5392     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5393     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5394                                                Loc));
5395   }
5396 
5397   // Add the predication code operand, if necessary.
5398   if (CanAcceptPredicationCode) {
5399     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5400                                       CarrySetting);
5401     Operands.push_back(ARMOperand::CreateCondCode(
5402                          ARMCC::CondCodes(PredicationCode), Loc));
5403   }
5404 
5405   // Add the processor imod operand, if necessary.
5406   if (ProcessorIMod) {
5407     Operands.push_back(ARMOperand::CreateImm(
5408           MCConstantExpr::Create(ProcessorIMod, getContext()),
5409                                  NameLoc, NameLoc));
5410   }
5411 
5412   // Add the remaining tokens in the mnemonic.
5413   while (Next != StringRef::npos) {
5414     Start = Next;
5415     Next = Name.find('.', Start + 1);
5416     StringRef ExtraToken = Name.slice(Start, Next);
5417 
5418     // Some NEON instructions have an optional datatype suffix that is
5419     // completely ignored. Check for that.
5420     if (isDataTypeToken(ExtraToken) &&
5421         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5422       continue;
5423 
5424     // For for ARM mode generate an error if the .n qualifier is used.
5425     if (ExtraToken == ".n" && !isThumb()) {
5426       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5427       Parser.eatToEndOfStatement();
5428       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5429                    "arm mode");
5430     }
5431 
5432     // The .n qualifier is always discarded as that is what the tables
5433     // and matcher expect.  In ARM mode the .w qualifier has no effect,
5434     // so discard it to avoid errors that can be caused by the matcher.
5435     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5436       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5437       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5438     }
5439   }
5440 
5441   // Read the remaining operands.
5442   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5443     // Read the first operand.
5444     if (parseOperand(Operands, Mnemonic)) {
5445       Parser.eatToEndOfStatement();
5446       return true;
5447     }
5448 
5449     while (getLexer().is(AsmToken::Comma)) {
5450       Parser.Lex();  // Eat the comma.
5451 
5452       // Parse and remember the operand.
5453       if (parseOperand(Operands, Mnemonic)) {
5454         Parser.eatToEndOfStatement();
5455         return true;
5456       }
5457     }
5458   }
5459 
5460   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5461     SMLoc Loc = getLexer().getLoc();
5462     Parser.eatToEndOfStatement();
5463     return Error(Loc, "unexpected token in argument list");
5464   }
5465 
5466   Parser.Lex(); // Consume the EndOfStatement
5467 
5468   if (RequireVFPRegisterListCheck) {
5469     ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5470     if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5471       return Error(Op.getStartLoc(),
5472                    "VFP/Neon single precision register expected");
5473     if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5474       return Error(Op.getStartLoc(),
5475                    "VFP/Neon double precision register expected");
5476   }
5477 
5478   // Some instructions, mostly Thumb, have forms for the same mnemonic that
5479   // do and don't have a cc_out optional-def operand. With some spot-checks
5480   // of the operand list, we can figure out which variant we're trying to
5481   // parse and adjust accordingly before actually matching. We shouldn't ever
5482   // try to remove a cc_out operand that was explicitly set on the the
5483   // mnemonic, of course (CarrySetting == true). Reason number #317 the
5484   // table driven matcher doesn't fit well with the ARM instruction set.
5485   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5486     Operands.erase(Operands.begin() + 1);
5487 
5488   // Some instructions have the same mnemonic, but don't always
5489   // have a predicate. Distinguish them here and delete the
5490   // predicate if needed.
5491   if (shouldOmitPredicateOperand(Mnemonic, Operands))
5492     Operands.erase(Operands.begin() + 1);
5493 
5494   // ARM mode 'blx' need special handling, as the register operand version
5495   // is predicable, but the label operand version is not. So, we can't rely
5496   // on the Mnemonic based checking to correctly figure out when to put
5497   // a k_CondCode operand in the list. If we're trying to match the label
5498   // version, remove the k_CondCode operand here.
5499   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5500       static_cast<ARMOperand &>(*Operands[2]).isImm())
5501     Operands.erase(Operands.begin() + 1);
5502 
5503   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5504   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5505   // a single GPRPair reg operand is used in the .td file to replace the two
5506   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5507   // expressed as a GPRPair, so we have to manually merge them.
5508   // FIXME: We would really like to be able to tablegen'erate this.
5509   if (!isThumb() && Operands.size() > 4 &&
5510       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5511        Mnemonic == "stlexd")) {
5512     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5513     unsigned Idx = isLoad ? 2 : 3;
5514     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5515     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5516 
5517     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5518     // Adjust only if Op1 and Op2 are GPRs.
5519     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5520         MRC.contains(Op2.getReg())) {
5521       unsigned Reg1 = Op1.getReg();
5522       unsigned Reg2 = Op2.getReg();
5523       unsigned Rt = MRI->getEncodingValue(Reg1);
5524       unsigned Rt2 = MRI->getEncodingValue(Reg2);
5525 
5526       // Rt2 must be Rt + 1 and Rt must be even.
5527       if (Rt + 1 != Rt2 || (Rt & 1)) {
5528         Error(Op2.getStartLoc(), isLoad
5529                                      ? "destination operands must be sequential"
5530                                      : "source operands must be sequential");
5531         return true;
5532       }
5533       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5534           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5535       Operands[Idx] =
5536           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5537       Operands.erase(Operands.begin() + Idx + 1);
5538     }
5539   }
5540 
5541   // GNU Assembler extension (compatibility)
5542   if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5543     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5544     ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5545     if (Op3.isMem()) {
5546       assert(Op2.isReg() && "expected register argument");
5547 
5548       unsigned SuperReg = MRI->getMatchingSuperReg(
5549           Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5550 
5551       assert(SuperReg && "expected register pair");
5552 
5553       unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5554 
5555       Operands.insert(
5556           Operands.begin() + 3,
5557           ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5558     }
5559   }
5560 
5561   // FIXME: As said above, this is all a pretty gross hack.  This instruction
5562   // does not fit with other "subs" and tblgen.
5563   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5564   // so the Mnemonic is the original name "subs" and delete the predicate
5565   // operand so it will match the table entry.
5566   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5567       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5568       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5569       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5570       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5571       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5572     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5573     Operands.erase(Operands.begin() + 1);
5574   }
5575   return false;
5576 }
5577 
5578 // Validate context-sensitive operand constraints.
5579 
5580 // return 'true' if register list contains non-low GPR registers,
5581 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5582 // 'containsReg' to true.
5583 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5584                                  unsigned HiReg, bool &containsReg) {
5585   containsReg = false;
5586   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5587     unsigned OpReg = Inst.getOperand(i).getReg();
5588     if (OpReg == Reg)
5589       containsReg = true;
5590     // Anything other than a low register isn't legal here.
5591     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5592       return true;
5593   }
5594   return false;
5595 }
5596 
5597 // Check if the specified regisgter is in the register list of the inst,
5598 // starting at the indicated operand number.
5599 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5600   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5601     unsigned OpReg = Inst.getOperand(i).getReg();
5602     if (OpReg == Reg)
5603       return true;
5604   }
5605   return false;
5606 }
5607 
5608 // Return true if instruction has the interesting property of being
5609 // allowed in IT blocks, but not being predicable.
5610 static bool instIsBreakpoint(const MCInst &Inst) {
5611     return Inst.getOpcode() == ARM::tBKPT ||
5612            Inst.getOpcode() == ARM::BKPT ||
5613            Inst.getOpcode() == ARM::tHLT ||
5614            Inst.getOpcode() == ARM::HLT;
5615 
5616 }
5617 
5618 // FIXME: We would really like to be able to tablegen'erate this.
5619 bool ARMAsmParser::validateInstruction(MCInst &Inst,
5620                                        const OperandVector &Operands) {
5621   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5622   SMLoc Loc = Operands[0]->getStartLoc();
5623 
5624   // Check the IT block state first.
5625   // NOTE: BKPT and HLT instructions have the interesting property of being
5626   // allowed in IT blocks, but not being predicable. They just always execute.
5627   if (inITBlock() && !instIsBreakpoint(Inst)) {
5628     unsigned Bit = 1;
5629     if (ITState.FirstCond)
5630       ITState.FirstCond = false;
5631     else
5632       Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5633     // The instruction must be predicable.
5634     if (!MCID.isPredicable())
5635       return Error(Loc, "instructions in IT block must be predicable");
5636     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5637     unsigned ITCond = Bit ? ITState.Cond :
5638       ARMCC::getOppositeCondition(ITState.Cond);
5639     if (Cond != ITCond) {
5640       // Find the condition code Operand to get its SMLoc information.
5641       SMLoc CondLoc;
5642       for (unsigned I = 1; I < Operands.size(); ++I)
5643         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
5644           CondLoc = Operands[I]->getStartLoc();
5645       return Error(CondLoc, "incorrect condition in IT block; got '" +
5646                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5647                    "', but expected '" +
5648                    ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5649     }
5650   // Check for non-'al' condition codes outside of the IT block.
5651   } else if (isThumbTwo() && MCID.isPredicable() &&
5652              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5653              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5654              Inst.getOpcode() != ARM::t2Bcc)
5655     return Error(Loc, "predicated instructions must be in IT block");
5656 
5657   const unsigned Opcode = Inst.getOpcode();
5658   switch (Opcode) {
5659   case ARM::LDRD:
5660   case ARM::LDRD_PRE:
5661   case ARM::LDRD_POST: {
5662     const unsigned RtReg = Inst.getOperand(0).getReg();
5663 
5664     // Rt can't be R14.
5665     if (RtReg == ARM::LR)
5666       return Error(Operands[3]->getStartLoc(),
5667                    "Rt can't be R14");
5668 
5669     const unsigned Rt = MRI->getEncodingValue(RtReg);
5670     // Rt must be even-numbered.
5671     if ((Rt & 1) == 1)
5672       return Error(Operands[3]->getStartLoc(),
5673                    "Rt must be even-numbered");
5674 
5675     // Rt2 must be Rt + 1.
5676     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5677     if (Rt2 != Rt + 1)
5678       return Error(Operands[3]->getStartLoc(),
5679                    "destination operands must be sequential");
5680 
5681     if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5682       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5683       // For addressing modes with writeback, the base register needs to be
5684       // different from the destination registers.
5685       if (Rn == Rt || Rn == Rt2)
5686         return Error(Operands[3]->getStartLoc(),
5687                      "base register needs to be different from destination "
5688                      "registers");
5689     }
5690 
5691     return false;
5692   }
5693   case ARM::t2LDRDi8:
5694   case ARM::t2LDRD_PRE:
5695   case ARM::t2LDRD_POST: {
5696     // Rt2 must be different from Rt.
5697     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5698     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5699     if (Rt2 == Rt)
5700       return Error(Operands[3]->getStartLoc(),
5701                    "destination operands can't be identical");
5702     return false;
5703   }
5704   case ARM::STRD: {
5705     // Rt2 must be Rt + 1.
5706     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5707     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5708     if (Rt2 != Rt + 1)
5709       return Error(Operands[3]->getStartLoc(),
5710                    "source operands must be sequential");
5711     return false;
5712   }
5713   case ARM::STRD_PRE:
5714   case ARM::STRD_POST: {
5715     // Rt2 must be Rt + 1.
5716     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5717     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5718     if (Rt2 != Rt + 1)
5719       return Error(Operands[3]->getStartLoc(),
5720                    "source operands must be sequential");
5721     return false;
5722   }
5723   case ARM::SBFX:
5724   case ARM::UBFX: {
5725     // Width must be in range [1, 32-lsb].
5726     unsigned LSB = Inst.getOperand(2).getImm();
5727     unsigned Widthm1 = Inst.getOperand(3).getImm();
5728     if (Widthm1 >= 32 - LSB)
5729       return Error(Operands[5]->getStartLoc(),
5730                    "bitfield width must be in range [1,32-lsb]");
5731     return false;
5732   }
5733   // Notionally handles ARM::tLDMIA_UPD too.
5734   case ARM::tLDMIA: {
5735     // If we're parsing Thumb2, the .w variant is available and handles
5736     // most cases that are normally illegal for a Thumb1 LDM instruction.
5737     // We'll make the transformation in processInstruction() if necessary.
5738     //
5739     // Thumb LDM instructions are writeback iff the base register is not
5740     // in the register list.
5741     unsigned Rn = Inst.getOperand(0).getReg();
5742     bool HasWritebackToken =
5743         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5744          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
5745     bool ListContainsBase;
5746     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5747       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5748                    "registers must be in range r0-r7");
5749     // If we should have writeback, then there should be a '!' token.
5750     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5751       return Error(Operands[2]->getStartLoc(),
5752                    "writeback operator '!' expected");
5753     // If we should not have writeback, there must not be a '!'. This is
5754     // true even for the 32-bit wide encodings.
5755     if (ListContainsBase && HasWritebackToken)
5756       return Error(Operands[3]->getStartLoc(),
5757                    "writeback operator '!' not allowed when base register "
5758                    "in register list");
5759 
5760     break;
5761   }
5762   case ARM::LDMIA_UPD:
5763   case ARM::LDMDB_UPD:
5764   case ARM::LDMIB_UPD:
5765   case ARM::LDMDA_UPD:
5766     // ARM variants loading and updating the same register are only officially
5767     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5768     if (!hasV7Ops())
5769       break;
5770     // Fallthrough
5771   case ARM::t2LDMIA_UPD:
5772   case ARM::t2LDMDB_UPD:
5773   case ARM::t2STMIA_UPD:
5774   case ARM::t2STMDB_UPD: {
5775     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5776       return Error(Operands.back()->getStartLoc(),
5777                    "writeback register not allowed in register list");
5778     break;
5779   }
5780   case ARM::sysLDMIA_UPD:
5781   case ARM::sysLDMDA_UPD:
5782   case ARM::sysLDMDB_UPD:
5783   case ARM::sysLDMIB_UPD:
5784     if (!listContainsReg(Inst, 3, ARM::PC))
5785       return Error(Operands[4]->getStartLoc(),
5786                    "writeback register only allowed on system LDM "
5787                    "if PC in register-list");
5788     break;
5789   case ARM::sysSTMIA_UPD:
5790   case ARM::sysSTMDA_UPD:
5791   case ARM::sysSTMDB_UPD:
5792   case ARM::sysSTMIB_UPD:
5793     return Error(Operands[2]->getStartLoc(),
5794                  "system STM cannot have writeback register");
5795   case ARM::tMUL: {
5796     // The second source operand must be the same register as the destination
5797     // operand.
5798     //
5799     // In this case, we must directly check the parsed operands because the
5800     // cvtThumbMultiply() function is written in such a way that it guarantees
5801     // this first statement is always true for the new Inst.  Essentially, the
5802     // destination is unconditionally copied into the second source operand
5803     // without checking to see if it matches what we actually parsed.
5804     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
5805                                  ((ARMOperand &)*Operands[5]).getReg()) &&
5806         (((ARMOperand &)*Operands[3]).getReg() !=
5807          ((ARMOperand &)*Operands[4]).getReg())) {
5808       return Error(Operands[3]->getStartLoc(),
5809                    "destination register must match source register");
5810     }
5811     break;
5812   }
5813   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5814   // so only issue a diagnostic for thumb1. The instructions will be
5815   // switched to the t2 encodings in processInstruction() if necessary.
5816   case ARM::tPOP: {
5817     bool ListContainsBase;
5818     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5819         !isThumbTwo())
5820       return Error(Operands[2]->getStartLoc(),
5821                    "registers must be in range r0-r7 or pc");
5822     break;
5823   }
5824   case ARM::tPUSH: {
5825     bool ListContainsBase;
5826     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5827         !isThumbTwo())
5828       return Error(Operands[2]->getStartLoc(),
5829                    "registers must be in range r0-r7 or lr");
5830     break;
5831   }
5832   case ARM::tSTMIA_UPD: {
5833     bool ListContainsBase, InvalidLowList;
5834     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5835                                           0, ListContainsBase);
5836     if (InvalidLowList && !isThumbTwo())
5837       return Error(Operands[4]->getStartLoc(),
5838                    "registers must be in range r0-r7");
5839 
5840     // This would be converted to a 32-bit stm, but that's not valid if the
5841     // writeback register is in the list.
5842     if (InvalidLowList && ListContainsBase)
5843       return Error(Operands[4]->getStartLoc(),
5844                    "writeback operator '!' not allowed when base register "
5845                    "in register list");
5846     break;
5847   }
5848   case ARM::tADDrSP: {
5849     // If the non-SP source operand and the destination operand are not the
5850     // same, we need thumb2 (for the wide encoding), or we have an error.
5851     if (!isThumbTwo() &&
5852         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5853       return Error(Operands[4]->getStartLoc(),
5854                    "source register must be the same as destination");
5855     }
5856     break;
5857   }
5858   // Final range checking for Thumb unconditional branch instructions.
5859   case ARM::tB:
5860     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
5861       return Error(Operands[2]->getStartLoc(), "branch target out of range");
5862     break;
5863   case ARM::t2B: {
5864     int op = (Operands[2]->isImm()) ? 2 : 3;
5865     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
5866       return Error(Operands[op]->getStartLoc(), "branch target out of range");
5867     break;
5868   }
5869   // Final range checking for Thumb conditional branch instructions.
5870   case ARM::tBcc:
5871     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
5872       return Error(Operands[2]->getStartLoc(), "branch target out of range");
5873     break;
5874   case ARM::t2Bcc: {
5875     int Op = (Operands[2]->isImm()) ? 2 : 3;
5876     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
5877       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5878     break;
5879   }
5880   case ARM::MOVi16:
5881   case ARM::t2MOVi16:
5882   case ARM::t2MOVTi16:
5883     {
5884     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
5885     // especially when we turn it into a movw and the expression <symbol> does
5886     // not have a :lower16: or :upper16 as part of the expression.  We don't
5887     // want the behavior of silently truncating, which can be unexpected and
5888     // lead to bugs that are difficult to find since this is an easy mistake
5889     // to make.
5890     int i = (Operands[3]->isImm()) ? 3 : 4;
5891     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
5892     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
5893     if (CE) break;
5894     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
5895     if (!E) break;
5896     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
5897     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
5898                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
5899       return Error(
5900           Op.getStartLoc(),
5901           "immediate expression for mov requires :lower16: or :upper16");
5902     break;
5903   }
5904   }
5905 
5906   return false;
5907 }
5908 
5909 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5910   switch(Opc) {
5911   default: llvm_unreachable("unexpected opcode!");
5912   // VST1LN
5913   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5914   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5915   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5916   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5917   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5918   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5919   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5920   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5921   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5922 
5923   // VST2LN
5924   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5925   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5926   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5927   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5928   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5929 
5930   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5931   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5932   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5933   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5934   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5935 
5936   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5937   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5938   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5939   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5940   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5941 
5942   // VST3LN
5943   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5944   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5945   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5946   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5947   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5948   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5949   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5950   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5951   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5952   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5953   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5954   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5955   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5956   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5957   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5958 
5959   // VST3
5960   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5961   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5962   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5963   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5964   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5965   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5966   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5967   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5968   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5969   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5970   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5971   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5972   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5973   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5974   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5975   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5976   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5977   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5978 
5979   // VST4LN
5980   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5981   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5982   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5983   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5984   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5985   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5986   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5987   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5988   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5989   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5990   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5991   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5992   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5993   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5994   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5995 
5996   // VST4
5997   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5998   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5999   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6000   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6001   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6002   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6003   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6004   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6005   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6006   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6007   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6008   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6009   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
6010   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6011   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6012   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
6013   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6014   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6015   }
6016 }
6017 
6018 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6019   switch(Opc) {
6020   default: llvm_unreachable("unexpected opcode!");
6021   // VLD1LN
6022   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6023   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6024   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6025   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6026   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6027   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6028   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
6029   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6030   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6031 
6032   // VLD2LN
6033   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6034   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6035   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6036   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6037   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6038   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6039   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6040   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6041   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6042   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6043   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
6044   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6045   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6046   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6047   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6048 
6049   // VLD3DUP
6050   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6051   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6052   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6053   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6054   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6055   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6056   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6057   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6058   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6059   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6060   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6061   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6062   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
6063   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6064   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6065   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6066   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6067   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6068 
6069   // VLD3LN
6070   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6071   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6072   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6073   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6074   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6075   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6076   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6077   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6078   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6079   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6080   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
6081   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6082   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6083   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6084   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6085 
6086   // VLD3
6087   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6088   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6089   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6090   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6091   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6092   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6093   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6094   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6095   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6096   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6097   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6098   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6099   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
6100   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6101   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6102   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
6103   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6104   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6105 
6106   // VLD4LN
6107   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6108   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6109   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6110   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6111   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6112   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6113   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6114   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6115   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6116   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6117   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
6118   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6119   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6120   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6121   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6122 
6123   // VLD4DUP
6124   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6125   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6126   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6127   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6128   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6129   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6130   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6131   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6132   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6133   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6134   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6135   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6136   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
6137   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6138   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6139   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6140   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6141   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6142 
6143   // VLD4
6144   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6145   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6146   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6147   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6148   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6149   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6150   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6151   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6152   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6153   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6154   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6155   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6156   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
6157   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6158   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6159   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
6160   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6161   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6162   }
6163 }
6164 
6165 bool ARMAsmParser::processInstruction(MCInst &Inst,
6166                                       const OperandVector &Operands) {
6167   switch (Inst.getOpcode()) {
6168   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6169   case ARM::LDRT_POST:
6170   case ARM::LDRBT_POST: {
6171     const unsigned Opcode =
6172       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6173                                            : ARM::LDRBT_POST_IMM;
6174     MCInst TmpInst;
6175     TmpInst.setOpcode(Opcode);
6176     TmpInst.addOperand(Inst.getOperand(0));
6177     TmpInst.addOperand(Inst.getOperand(1));
6178     TmpInst.addOperand(Inst.getOperand(1));
6179     TmpInst.addOperand(MCOperand::CreateReg(0));
6180     TmpInst.addOperand(MCOperand::CreateImm(0));
6181     TmpInst.addOperand(Inst.getOperand(2));
6182     TmpInst.addOperand(Inst.getOperand(3));
6183     Inst = TmpInst;
6184     return true;
6185   }
6186   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6187   case ARM::STRT_POST:
6188   case ARM::STRBT_POST: {
6189     const unsigned Opcode =
6190       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6191                                            : ARM::STRBT_POST_IMM;
6192     MCInst TmpInst;
6193     TmpInst.setOpcode(Opcode);
6194     TmpInst.addOperand(Inst.getOperand(1));
6195     TmpInst.addOperand(Inst.getOperand(0));
6196     TmpInst.addOperand(Inst.getOperand(1));
6197     TmpInst.addOperand(MCOperand::CreateReg(0));
6198     TmpInst.addOperand(MCOperand::CreateImm(0));
6199     TmpInst.addOperand(Inst.getOperand(2));
6200     TmpInst.addOperand(Inst.getOperand(3));
6201     Inst = TmpInst;
6202     return true;
6203   }
6204   // Alias for alternate form of 'ADR Rd, #imm' instruction.
6205   case ARM::ADDri: {
6206     if (Inst.getOperand(1).getReg() != ARM::PC ||
6207         Inst.getOperand(5).getReg() != 0)
6208       return false;
6209     MCInst TmpInst;
6210     TmpInst.setOpcode(ARM::ADR);
6211     TmpInst.addOperand(Inst.getOperand(0));
6212     TmpInst.addOperand(Inst.getOperand(2));
6213     TmpInst.addOperand(Inst.getOperand(3));
6214     TmpInst.addOperand(Inst.getOperand(4));
6215     Inst = TmpInst;
6216     return true;
6217   }
6218   // Aliases for alternate PC+imm syntax of LDR instructions.
6219   case ARM::t2LDRpcrel:
6220     // Select the narrow version if the immediate will fit.
6221     if (Inst.getOperand(1).getImm() > 0 &&
6222         Inst.getOperand(1).getImm() <= 0xff &&
6223         !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6224           static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6225       Inst.setOpcode(ARM::tLDRpci);
6226     else
6227       Inst.setOpcode(ARM::t2LDRpci);
6228     return true;
6229   case ARM::t2LDRBpcrel:
6230     Inst.setOpcode(ARM::t2LDRBpci);
6231     return true;
6232   case ARM::t2LDRHpcrel:
6233     Inst.setOpcode(ARM::t2LDRHpci);
6234     return true;
6235   case ARM::t2LDRSBpcrel:
6236     Inst.setOpcode(ARM::t2LDRSBpci);
6237     return true;
6238   case ARM::t2LDRSHpcrel:
6239     Inst.setOpcode(ARM::t2LDRSHpci);
6240     return true;
6241   // Handle NEON VST complex aliases.
6242   case ARM::VST1LNdWB_register_Asm_8:
6243   case ARM::VST1LNdWB_register_Asm_16:
6244   case ARM::VST1LNdWB_register_Asm_32: {
6245     MCInst TmpInst;
6246     // Shuffle the operands around so the lane index operand is in the
6247     // right place.
6248     unsigned Spacing;
6249     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6250     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6251     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6252     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6253     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6254     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6255     TmpInst.addOperand(Inst.getOperand(1)); // lane
6256     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6257     TmpInst.addOperand(Inst.getOperand(6));
6258     Inst = TmpInst;
6259     return true;
6260   }
6261 
6262   case ARM::VST2LNdWB_register_Asm_8:
6263   case ARM::VST2LNdWB_register_Asm_16:
6264   case ARM::VST2LNdWB_register_Asm_32:
6265   case ARM::VST2LNqWB_register_Asm_16:
6266   case ARM::VST2LNqWB_register_Asm_32: {
6267     MCInst TmpInst;
6268     // Shuffle the operands around so the lane index operand is in the
6269     // right place.
6270     unsigned Spacing;
6271     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6272     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6273     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6274     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6275     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6276     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6277     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6278                                             Spacing));
6279     TmpInst.addOperand(Inst.getOperand(1)); // lane
6280     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6281     TmpInst.addOperand(Inst.getOperand(6));
6282     Inst = TmpInst;
6283     return true;
6284   }
6285 
6286   case ARM::VST3LNdWB_register_Asm_8:
6287   case ARM::VST3LNdWB_register_Asm_16:
6288   case ARM::VST3LNdWB_register_Asm_32:
6289   case ARM::VST3LNqWB_register_Asm_16:
6290   case ARM::VST3LNqWB_register_Asm_32: {
6291     MCInst TmpInst;
6292     // Shuffle the operands around so the lane index operand is in the
6293     // right place.
6294     unsigned Spacing;
6295     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6296     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6297     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6298     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6299     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6300     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6301     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6302                                             Spacing));
6303     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6304                                             Spacing * 2));
6305     TmpInst.addOperand(Inst.getOperand(1)); // lane
6306     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6307     TmpInst.addOperand(Inst.getOperand(6));
6308     Inst = TmpInst;
6309     return true;
6310   }
6311 
6312   case ARM::VST4LNdWB_register_Asm_8:
6313   case ARM::VST4LNdWB_register_Asm_16:
6314   case ARM::VST4LNdWB_register_Asm_32:
6315   case ARM::VST4LNqWB_register_Asm_16:
6316   case ARM::VST4LNqWB_register_Asm_32: {
6317     MCInst TmpInst;
6318     // Shuffle the operands around so the lane index operand is in the
6319     // right place.
6320     unsigned Spacing;
6321     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6322     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6323     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6324     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6325     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6326     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6327     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6328                                             Spacing));
6329     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6330                                             Spacing * 2));
6331     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6332                                             Spacing * 3));
6333     TmpInst.addOperand(Inst.getOperand(1)); // lane
6334     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6335     TmpInst.addOperand(Inst.getOperand(6));
6336     Inst = TmpInst;
6337     return true;
6338   }
6339 
6340   case ARM::VST1LNdWB_fixed_Asm_8:
6341   case ARM::VST1LNdWB_fixed_Asm_16:
6342   case ARM::VST1LNdWB_fixed_Asm_32: {
6343     MCInst TmpInst;
6344     // Shuffle the operands around so the lane index operand is in the
6345     // right place.
6346     unsigned Spacing;
6347     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6348     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6349     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6350     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6351     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6352     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6353     TmpInst.addOperand(Inst.getOperand(1)); // lane
6354     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6355     TmpInst.addOperand(Inst.getOperand(5));
6356     Inst = TmpInst;
6357     return true;
6358   }
6359 
6360   case ARM::VST2LNdWB_fixed_Asm_8:
6361   case ARM::VST2LNdWB_fixed_Asm_16:
6362   case ARM::VST2LNdWB_fixed_Asm_32:
6363   case ARM::VST2LNqWB_fixed_Asm_16:
6364   case ARM::VST2LNqWB_fixed_Asm_32: {
6365     MCInst TmpInst;
6366     // Shuffle the operands around so the lane index operand is in the
6367     // right place.
6368     unsigned Spacing;
6369     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6370     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6371     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6372     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6373     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6374     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6375     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6376                                             Spacing));
6377     TmpInst.addOperand(Inst.getOperand(1)); // lane
6378     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6379     TmpInst.addOperand(Inst.getOperand(5));
6380     Inst = TmpInst;
6381     return true;
6382   }
6383 
6384   case ARM::VST3LNdWB_fixed_Asm_8:
6385   case ARM::VST3LNdWB_fixed_Asm_16:
6386   case ARM::VST3LNdWB_fixed_Asm_32:
6387   case ARM::VST3LNqWB_fixed_Asm_16:
6388   case ARM::VST3LNqWB_fixed_Asm_32: {
6389     MCInst TmpInst;
6390     // Shuffle the operands around so the lane index operand is in the
6391     // right place.
6392     unsigned Spacing;
6393     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6394     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6395     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6396     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6397     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6398     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6399     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6400                                             Spacing));
6401     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6402                                             Spacing * 2));
6403     TmpInst.addOperand(Inst.getOperand(1)); // lane
6404     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6405     TmpInst.addOperand(Inst.getOperand(5));
6406     Inst = TmpInst;
6407     return true;
6408   }
6409 
6410   case ARM::VST4LNdWB_fixed_Asm_8:
6411   case ARM::VST4LNdWB_fixed_Asm_16:
6412   case ARM::VST4LNdWB_fixed_Asm_32:
6413   case ARM::VST4LNqWB_fixed_Asm_16:
6414   case ARM::VST4LNqWB_fixed_Asm_32: {
6415     MCInst TmpInst;
6416     // Shuffle the operands around so the lane index operand is in the
6417     // right place.
6418     unsigned Spacing;
6419     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6420     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6421     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6422     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6423     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6424     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6425     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6426                                             Spacing));
6427     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6428                                             Spacing * 2));
6429     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6430                                             Spacing * 3));
6431     TmpInst.addOperand(Inst.getOperand(1)); // lane
6432     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6433     TmpInst.addOperand(Inst.getOperand(5));
6434     Inst = TmpInst;
6435     return true;
6436   }
6437 
6438   case ARM::VST1LNdAsm_8:
6439   case ARM::VST1LNdAsm_16:
6440   case ARM::VST1LNdAsm_32: {
6441     MCInst TmpInst;
6442     // Shuffle the operands around so the lane index operand is in the
6443     // right place.
6444     unsigned Spacing;
6445     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6446     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6447     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6448     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6449     TmpInst.addOperand(Inst.getOperand(1)); // lane
6450     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6451     TmpInst.addOperand(Inst.getOperand(5));
6452     Inst = TmpInst;
6453     return true;
6454   }
6455 
6456   case ARM::VST2LNdAsm_8:
6457   case ARM::VST2LNdAsm_16:
6458   case ARM::VST2LNdAsm_32:
6459   case ARM::VST2LNqAsm_16:
6460   case ARM::VST2LNqAsm_32: {
6461     MCInst TmpInst;
6462     // Shuffle the operands around so the lane index operand is in the
6463     // right place.
6464     unsigned Spacing;
6465     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6466     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6467     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6468     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6469     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6470                                             Spacing));
6471     TmpInst.addOperand(Inst.getOperand(1)); // lane
6472     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6473     TmpInst.addOperand(Inst.getOperand(5));
6474     Inst = TmpInst;
6475     return true;
6476   }
6477 
6478   case ARM::VST3LNdAsm_8:
6479   case ARM::VST3LNdAsm_16:
6480   case ARM::VST3LNdAsm_32:
6481   case ARM::VST3LNqAsm_16:
6482   case ARM::VST3LNqAsm_32: {
6483     MCInst TmpInst;
6484     // Shuffle the operands around so the lane index operand is in the
6485     // right place.
6486     unsigned Spacing;
6487     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6488     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6489     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6490     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6491     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6492                                             Spacing));
6493     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6494                                             Spacing * 2));
6495     TmpInst.addOperand(Inst.getOperand(1)); // lane
6496     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6497     TmpInst.addOperand(Inst.getOperand(5));
6498     Inst = TmpInst;
6499     return true;
6500   }
6501 
6502   case ARM::VST4LNdAsm_8:
6503   case ARM::VST4LNdAsm_16:
6504   case ARM::VST4LNdAsm_32:
6505   case ARM::VST4LNqAsm_16:
6506   case ARM::VST4LNqAsm_32: {
6507     MCInst TmpInst;
6508     // Shuffle the operands around so the lane index operand is in the
6509     // right place.
6510     unsigned Spacing;
6511     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6512     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6513     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6514     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6515     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6516                                             Spacing));
6517     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6518                                             Spacing * 2));
6519     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6520                                             Spacing * 3));
6521     TmpInst.addOperand(Inst.getOperand(1)); // lane
6522     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6523     TmpInst.addOperand(Inst.getOperand(5));
6524     Inst = TmpInst;
6525     return true;
6526   }
6527 
6528   // Handle NEON VLD complex aliases.
6529   case ARM::VLD1LNdWB_register_Asm_8:
6530   case ARM::VLD1LNdWB_register_Asm_16:
6531   case ARM::VLD1LNdWB_register_Asm_32: {
6532     MCInst TmpInst;
6533     // Shuffle the operands around so the lane index operand is in the
6534     // right place.
6535     unsigned Spacing;
6536     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6537     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6538     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6539     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6540     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6541     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6542     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6543     TmpInst.addOperand(Inst.getOperand(1)); // lane
6544     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6545     TmpInst.addOperand(Inst.getOperand(6));
6546     Inst = TmpInst;
6547     return true;
6548   }
6549 
6550   case ARM::VLD2LNdWB_register_Asm_8:
6551   case ARM::VLD2LNdWB_register_Asm_16:
6552   case ARM::VLD2LNdWB_register_Asm_32:
6553   case ARM::VLD2LNqWB_register_Asm_16:
6554   case ARM::VLD2LNqWB_register_Asm_32: {
6555     MCInst TmpInst;
6556     // Shuffle the operands around so the lane index operand is in the
6557     // right place.
6558     unsigned Spacing;
6559     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6560     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6561     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6562                                             Spacing));
6563     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6564     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6565     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6566     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6567     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6568     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6569                                             Spacing));
6570     TmpInst.addOperand(Inst.getOperand(1)); // lane
6571     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6572     TmpInst.addOperand(Inst.getOperand(6));
6573     Inst = TmpInst;
6574     return true;
6575   }
6576 
6577   case ARM::VLD3LNdWB_register_Asm_8:
6578   case ARM::VLD3LNdWB_register_Asm_16:
6579   case ARM::VLD3LNdWB_register_Asm_32:
6580   case ARM::VLD3LNqWB_register_Asm_16:
6581   case ARM::VLD3LNqWB_register_Asm_32: {
6582     MCInst TmpInst;
6583     // Shuffle the operands around so the lane index operand is in the
6584     // right place.
6585     unsigned Spacing;
6586     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6587     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6588     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6589                                             Spacing));
6590     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6591                                             Spacing * 2));
6592     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6593     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6594     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6595     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6596     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6597     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6598                                             Spacing));
6599     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6600                                             Spacing * 2));
6601     TmpInst.addOperand(Inst.getOperand(1)); // lane
6602     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6603     TmpInst.addOperand(Inst.getOperand(6));
6604     Inst = TmpInst;
6605     return true;
6606   }
6607 
6608   case ARM::VLD4LNdWB_register_Asm_8:
6609   case ARM::VLD4LNdWB_register_Asm_16:
6610   case ARM::VLD4LNdWB_register_Asm_32:
6611   case ARM::VLD4LNqWB_register_Asm_16:
6612   case ARM::VLD4LNqWB_register_Asm_32: {
6613     MCInst TmpInst;
6614     // Shuffle the operands around so the lane index operand is in the
6615     // right place.
6616     unsigned Spacing;
6617     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6618     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6619     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6620                                             Spacing));
6621     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6622                                             Spacing * 2));
6623     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6624                                             Spacing * 3));
6625     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6626     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6627     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6628     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6629     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6630     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6631                                             Spacing));
6632     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6633                                             Spacing * 2));
6634     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6635                                             Spacing * 3));
6636     TmpInst.addOperand(Inst.getOperand(1)); // lane
6637     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6638     TmpInst.addOperand(Inst.getOperand(6));
6639     Inst = TmpInst;
6640     return true;
6641   }
6642 
6643   case ARM::VLD1LNdWB_fixed_Asm_8:
6644   case ARM::VLD1LNdWB_fixed_Asm_16:
6645   case ARM::VLD1LNdWB_fixed_Asm_32: {
6646     MCInst TmpInst;
6647     // Shuffle the operands around so the lane index operand is in the
6648     // right place.
6649     unsigned Spacing;
6650     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6651     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6652     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6653     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6654     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6655     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6656     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6657     TmpInst.addOperand(Inst.getOperand(1)); // lane
6658     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6659     TmpInst.addOperand(Inst.getOperand(5));
6660     Inst = TmpInst;
6661     return true;
6662   }
6663 
6664   case ARM::VLD2LNdWB_fixed_Asm_8:
6665   case ARM::VLD2LNdWB_fixed_Asm_16:
6666   case ARM::VLD2LNdWB_fixed_Asm_32:
6667   case ARM::VLD2LNqWB_fixed_Asm_16:
6668   case ARM::VLD2LNqWB_fixed_Asm_32: {
6669     MCInst TmpInst;
6670     // Shuffle the operands around so the lane index operand is in the
6671     // right place.
6672     unsigned Spacing;
6673     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6674     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6675     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6676                                             Spacing));
6677     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6678     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6679     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6680     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6681     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6682     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6683                                             Spacing));
6684     TmpInst.addOperand(Inst.getOperand(1)); // lane
6685     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6686     TmpInst.addOperand(Inst.getOperand(5));
6687     Inst = TmpInst;
6688     return true;
6689   }
6690 
6691   case ARM::VLD3LNdWB_fixed_Asm_8:
6692   case ARM::VLD3LNdWB_fixed_Asm_16:
6693   case ARM::VLD3LNdWB_fixed_Asm_32:
6694   case ARM::VLD3LNqWB_fixed_Asm_16:
6695   case ARM::VLD3LNqWB_fixed_Asm_32: {
6696     MCInst TmpInst;
6697     // Shuffle the operands around so the lane index operand is in the
6698     // right place.
6699     unsigned Spacing;
6700     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6701     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6702     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6703                                             Spacing));
6704     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6705                                             Spacing * 2));
6706     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6707     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6708     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6709     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6710     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6711     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6712                                             Spacing));
6713     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6714                                             Spacing * 2));
6715     TmpInst.addOperand(Inst.getOperand(1)); // lane
6716     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6717     TmpInst.addOperand(Inst.getOperand(5));
6718     Inst = TmpInst;
6719     return true;
6720   }
6721 
6722   case ARM::VLD4LNdWB_fixed_Asm_8:
6723   case ARM::VLD4LNdWB_fixed_Asm_16:
6724   case ARM::VLD4LNdWB_fixed_Asm_32:
6725   case ARM::VLD4LNqWB_fixed_Asm_16:
6726   case ARM::VLD4LNqWB_fixed_Asm_32: {
6727     MCInst TmpInst;
6728     // Shuffle the operands around so the lane index operand is in the
6729     // right place.
6730     unsigned Spacing;
6731     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6732     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6733     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6734                                             Spacing));
6735     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6736                                             Spacing * 2));
6737     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6738                                             Spacing * 3));
6739     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6740     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6741     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6742     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6743     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6744     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6745                                             Spacing));
6746     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6747                                             Spacing * 2));
6748     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6749                                             Spacing * 3));
6750     TmpInst.addOperand(Inst.getOperand(1)); // lane
6751     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6752     TmpInst.addOperand(Inst.getOperand(5));
6753     Inst = TmpInst;
6754     return true;
6755   }
6756 
6757   case ARM::VLD1LNdAsm_8:
6758   case ARM::VLD1LNdAsm_16:
6759   case ARM::VLD1LNdAsm_32: {
6760     MCInst TmpInst;
6761     // Shuffle the operands around so the lane index operand is in the
6762     // right place.
6763     unsigned Spacing;
6764     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6765     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6766     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6767     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6768     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6769     TmpInst.addOperand(Inst.getOperand(1)); // lane
6770     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6771     TmpInst.addOperand(Inst.getOperand(5));
6772     Inst = TmpInst;
6773     return true;
6774   }
6775 
6776   case ARM::VLD2LNdAsm_8:
6777   case ARM::VLD2LNdAsm_16:
6778   case ARM::VLD2LNdAsm_32:
6779   case ARM::VLD2LNqAsm_16:
6780   case ARM::VLD2LNqAsm_32: {
6781     MCInst TmpInst;
6782     // Shuffle the operands around so the lane index operand is in the
6783     // right place.
6784     unsigned Spacing;
6785     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6786     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6787     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6788                                             Spacing));
6789     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6790     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6791     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6792     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6793                                             Spacing));
6794     TmpInst.addOperand(Inst.getOperand(1)); // lane
6795     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6796     TmpInst.addOperand(Inst.getOperand(5));
6797     Inst = TmpInst;
6798     return true;
6799   }
6800 
6801   case ARM::VLD3LNdAsm_8:
6802   case ARM::VLD3LNdAsm_16:
6803   case ARM::VLD3LNdAsm_32:
6804   case ARM::VLD3LNqAsm_16:
6805   case ARM::VLD3LNqAsm_32: {
6806     MCInst TmpInst;
6807     // Shuffle the operands around so the lane index operand is in the
6808     // right place.
6809     unsigned Spacing;
6810     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6811     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6812     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6813                                             Spacing));
6814     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6815                                             Spacing * 2));
6816     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6817     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6818     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6819     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6820                                             Spacing));
6821     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6822                                             Spacing * 2));
6823     TmpInst.addOperand(Inst.getOperand(1)); // lane
6824     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6825     TmpInst.addOperand(Inst.getOperand(5));
6826     Inst = TmpInst;
6827     return true;
6828   }
6829 
6830   case ARM::VLD4LNdAsm_8:
6831   case ARM::VLD4LNdAsm_16:
6832   case ARM::VLD4LNdAsm_32:
6833   case ARM::VLD4LNqAsm_16:
6834   case ARM::VLD4LNqAsm_32: {
6835     MCInst TmpInst;
6836     // Shuffle the operands around so the lane index operand is in the
6837     // right place.
6838     unsigned Spacing;
6839     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6840     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6841     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6842                                             Spacing));
6843     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6844                                             Spacing * 2));
6845     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6846                                             Spacing * 3));
6847     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6848     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6849     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6850     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6851                                             Spacing));
6852     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6853                                             Spacing * 2));
6854     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6855                                             Spacing * 3));
6856     TmpInst.addOperand(Inst.getOperand(1)); // lane
6857     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6858     TmpInst.addOperand(Inst.getOperand(5));
6859     Inst = TmpInst;
6860     return true;
6861   }
6862 
6863   // VLD3DUP single 3-element structure to all lanes instructions.
6864   case ARM::VLD3DUPdAsm_8:
6865   case ARM::VLD3DUPdAsm_16:
6866   case ARM::VLD3DUPdAsm_32:
6867   case ARM::VLD3DUPqAsm_8:
6868   case ARM::VLD3DUPqAsm_16:
6869   case ARM::VLD3DUPqAsm_32: {
6870     MCInst TmpInst;
6871     unsigned Spacing;
6872     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6873     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6874     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6875                                             Spacing));
6876     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6877                                             Spacing * 2));
6878     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6879     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6880     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6881     TmpInst.addOperand(Inst.getOperand(4));
6882     Inst = TmpInst;
6883     return true;
6884   }
6885 
6886   case ARM::VLD3DUPdWB_fixed_Asm_8:
6887   case ARM::VLD3DUPdWB_fixed_Asm_16:
6888   case ARM::VLD3DUPdWB_fixed_Asm_32:
6889   case ARM::VLD3DUPqWB_fixed_Asm_8:
6890   case ARM::VLD3DUPqWB_fixed_Asm_16:
6891   case ARM::VLD3DUPqWB_fixed_Asm_32: {
6892     MCInst TmpInst;
6893     unsigned Spacing;
6894     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6895     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6896     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6897                                             Spacing));
6898     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6899                                             Spacing * 2));
6900     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6901     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6902     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6903     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6904     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6905     TmpInst.addOperand(Inst.getOperand(4));
6906     Inst = TmpInst;
6907     return true;
6908   }
6909 
6910   case ARM::VLD3DUPdWB_register_Asm_8:
6911   case ARM::VLD3DUPdWB_register_Asm_16:
6912   case ARM::VLD3DUPdWB_register_Asm_32:
6913   case ARM::VLD3DUPqWB_register_Asm_8:
6914   case ARM::VLD3DUPqWB_register_Asm_16:
6915   case ARM::VLD3DUPqWB_register_Asm_32: {
6916     MCInst TmpInst;
6917     unsigned Spacing;
6918     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6919     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6920     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6921                                             Spacing));
6922     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6923                                             Spacing * 2));
6924     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6925     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6926     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6927     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6928     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6929     TmpInst.addOperand(Inst.getOperand(5));
6930     Inst = TmpInst;
6931     return true;
6932   }
6933 
6934   // VLD3 multiple 3-element structure instructions.
6935   case ARM::VLD3dAsm_8:
6936   case ARM::VLD3dAsm_16:
6937   case ARM::VLD3dAsm_32:
6938   case ARM::VLD3qAsm_8:
6939   case ARM::VLD3qAsm_16:
6940   case ARM::VLD3qAsm_32: {
6941     MCInst TmpInst;
6942     unsigned Spacing;
6943     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6944     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6945     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6946                                             Spacing));
6947     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6948                                             Spacing * 2));
6949     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6950     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6951     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6952     TmpInst.addOperand(Inst.getOperand(4));
6953     Inst = TmpInst;
6954     return true;
6955   }
6956 
6957   case ARM::VLD3dWB_fixed_Asm_8:
6958   case ARM::VLD3dWB_fixed_Asm_16:
6959   case ARM::VLD3dWB_fixed_Asm_32:
6960   case ARM::VLD3qWB_fixed_Asm_8:
6961   case ARM::VLD3qWB_fixed_Asm_16:
6962   case ARM::VLD3qWB_fixed_Asm_32: {
6963     MCInst TmpInst;
6964     unsigned Spacing;
6965     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6966     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6967     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6968                                             Spacing));
6969     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6970                                             Spacing * 2));
6971     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6972     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6973     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6974     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6975     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6976     TmpInst.addOperand(Inst.getOperand(4));
6977     Inst = TmpInst;
6978     return true;
6979   }
6980 
6981   case ARM::VLD3dWB_register_Asm_8:
6982   case ARM::VLD3dWB_register_Asm_16:
6983   case ARM::VLD3dWB_register_Asm_32:
6984   case ARM::VLD3qWB_register_Asm_8:
6985   case ARM::VLD3qWB_register_Asm_16:
6986   case ARM::VLD3qWB_register_Asm_32: {
6987     MCInst TmpInst;
6988     unsigned Spacing;
6989     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6990     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6991     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6992                                             Spacing));
6993     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6994                                             Spacing * 2));
6995     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6996     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6997     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6998     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6999     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7000     TmpInst.addOperand(Inst.getOperand(5));
7001     Inst = TmpInst;
7002     return true;
7003   }
7004 
7005   // VLD4DUP single 3-element structure to all lanes instructions.
7006   case ARM::VLD4DUPdAsm_8:
7007   case ARM::VLD4DUPdAsm_16:
7008   case ARM::VLD4DUPdAsm_32:
7009   case ARM::VLD4DUPqAsm_8:
7010   case ARM::VLD4DUPqAsm_16:
7011   case ARM::VLD4DUPqAsm_32: {
7012     MCInst TmpInst;
7013     unsigned Spacing;
7014     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7015     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7016     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7017                                             Spacing));
7018     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7019                                             Spacing * 2));
7020     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7021                                             Spacing * 3));
7022     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7023     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7024     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7025     TmpInst.addOperand(Inst.getOperand(4));
7026     Inst = TmpInst;
7027     return true;
7028   }
7029 
7030   case ARM::VLD4DUPdWB_fixed_Asm_8:
7031   case ARM::VLD4DUPdWB_fixed_Asm_16:
7032   case ARM::VLD4DUPdWB_fixed_Asm_32:
7033   case ARM::VLD4DUPqWB_fixed_Asm_8:
7034   case ARM::VLD4DUPqWB_fixed_Asm_16:
7035   case ARM::VLD4DUPqWB_fixed_Asm_32: {
7036     MCInst TmpInst;
7037     unsigned Spacing;
7038     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7039     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7040     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7041                                             Spacing));
7042     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7043                                             Spacing * 2));
7044     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7045                                             Spacing * 3));
7046     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7047     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7048     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7049     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7050     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7051     TmpInst.addOperand(Inst.getOperand(4));
7052     Inst = TmpInst;
7053     return true;
7054   }
7055 
7056   case ARM::VLD4DUPdWB_register_Asm_8:
7057   case ARM::VLD4DUPdWB_register_Asm_16:
7058   case ARM::VLD4DUPdWB_register_Asm_32:
7059   case ARM::VLD4DUPqWB_register_Asm_8:
7060   case ARM::VLD4DUPqWB_register_Asm_16:
7061   case ARM::VLD4DUPqWB_register_Asm_32: {
7062     MCInst TmpInst;
7063     unsigned Spacing;
7064     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7065     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7066     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7067                                             Spacing));
7068     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7069                                             Spacing * 2));
7070     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7071                                             Spacing * 3));
7072     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7073     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7074     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7075     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7076     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7077     TmpInst.addOperand(Inst.getOperand(5));
7078     Inst = TmpInst;
7079     return true;
7080   }
7081 
7082   // VLD4 multiple 4-element structure instructions.
7083   case ARM::VLD4dAsm_8:
7084   case ARM::VLD4dAsm_16:
7085   case ARM::VLD4dAsm_32:
7086   case ARM::VLD4qAsm_8:
7087   case ARM::VLD4qAsm_16:
7088   case ARM::VLD4qAsm_32: {
7089     MCInst TmpInst;
7090     unsigned Spacing;
7091     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7092     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7093     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7094                                             Spacing));
7095     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7096                                             Spacing * 2));
7097     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7098                                             Spacing * 3));
7099     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7100     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7101     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7102     TmpInst.addOperand(Inst.getOperand(4));
7103     Inst = TmpInst;
7104     return true;
7105   }
7106 
7107   case ARM::VLD4dWB_fixed_Asm_8:
7108   case ARM::VLD4dWB_fixed_Asm_16:
7109   case ARM::VLD4dWB_fixed_Asm_32:
7110   case ARM::VLD4qWB_fixed_Asm_8:
7111   case ARM::VLD4qWB_fixed_Asm_16:
7112   case ARM::VLD4qWB_fixed_Asm_32: {
7113     MCInst TmpInst;
7114     unsigned Spacing;
7115     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7116     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7117     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7118                                             Spacing));
7119     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7120                                             Spacing * 2));
7121     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7122                                             Spacing * 3));
7123     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7124     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7125     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7126     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7127     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7128     TmpInst.addOperand(Inst.getOperand(4));
7129     Inst = TmpInst;
7130     return true;
7131   }
7132 
7133   case ARM::VLD4dWB_register_Asm_8:
7134   case ARM::VLD4dWB_register_Asm_16:
7135   case ARM::VLD4dWB_register_Asm_32:
7136   case ARM::VLD4qWB_register_Asm_8:
7137   case ARM::VLD4qWB_register_Asm_16:
7138   case ARM::VLD4qWB_register_Asm_32: {
7139     MCInst TmpInst;
7140     unsigned Spacing;
7141     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7142     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7143     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7144                                             Spacing));
7145     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7146                                             Spacing * 2));
7147     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7148                                             Spacing * 3));
7149     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7150     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7151     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7152     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7153     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7154     TmpInst.addOperand(Inst.getOperand(5));
7155     Inst = TmpInst;
7156     return true;
7157   }
7158 
7159   // VST3 multiple 3-element structure instructions.
7160   case ARM::VST3dAsm_8:
7161   case ARM::VST3dAsm_16:
7162   case ARM::VST3dAsm_32:
7163   case ARM::VST3qAsm_8:
7164   case ARM::VST3qAsm_16:
7165   case ARM::VST3qAsm_32: {
7166     MCInst TmpInst;
7167     unsigned Spacing;
7168     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7169     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7170     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7171     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7172     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7173                                             Spacing));
7174     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7175                                             Spacing * 2));
7176     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7177     TmpInst.addOperand(Inst.getOperand(4));
7178     Inst = TmpInst;
7179     return true;
7180   }
7181 
7182   case ARM::VST3dWB_fixed_Asm_8:
7183   case ARM::VST3dWB_fixed_Asm_16:
7184   case ARM::VST3dWB_fixed_Asm_32:
7185   case ARM::VST3qWB_fixed_Asm_8:
7186   case ARM::VST3qWB_fixed_Asm_16:
7187   case ARM::VST3qWB_fixed_Asm_32: {
7188     MCInst TmpInst;
7189     unsigned Spacing;
7190     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7191     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7192     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7193     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7194     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7195     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7196     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7197                                             Spacing));
7198     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7199                                             Spacing * 2));
7200     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7201     TmpInst.addOperand(Inst.getOperand(4));
7202     Inst = TmpInst;
7203     return true;
7204   }
7205 
7206   case ARM::VST3dWB_register_Asm_8:
7207   case ARM::VST3dWB_register_Asm_16:
7208   case ARM::VST3dWB_register_Asm_32:
7209   case ARM::VST3qWB_register_Asm_8:
7210   case ARM::VST3qWB_register_Asm_16:
7211   case ARM::VST3qWB_register_Asm_32: {
7212     MCInst TmpInst;
7213     unsigned Spacing;
7214     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7215     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7216     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7217     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7218     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7219     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7220     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7221                                             Spacing));
7222     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7223                                             Spacing * 2));
7224     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7225     TmpInst.addOperand(Inst.getOperand(5));
7226     Inst = TmpInst;
7227     return true;
7228   }
7229 
7230   // VST4 multiple 3-element structure instructions.
7231   case ARM::VST4dAsm_8:
7232   case ARM::VST4dAsm_16:
7233   case ARM::VST4dAsm_32:
7234   case ARM::VST4qAsm_8:
7235   case ARM::VST4qAsm_16:
7236   case ARM::VST4qAsm_32: {
7237     MCInst TmpInst;
7238     unsigned Spacing;
7239     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7240     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7241     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7242     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7243     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7244                                             Spacing));
7245     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7246                                             Spacing * 2));
7247     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7248                                             Spacing * 3));
7249     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7250     TmpInst.addOperand(Inst.getOperand(4));
7251     Inst = TmpInst;
7252     return true;
7253   }
7254 
7255   case ARM::VST4dWB_fixed_Asm_8:
7256   case ARM::VST4dWB_fixed_Asm_16:
7257   case ARM::VST4dWB_fixed_Asm_32:
7258   case ARM::VST4qWB_fixed_Asm_8:
7259   case ARM::VST4qWB_fixed_Asm_16:
7260   case ARM::VST4qWB_fixed_Asm_32: {
7261     MCInst TmpInst;
7262     unsigned Spacing;
7263     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7264     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7265     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7266     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7267     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7268     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7269     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7270                                             Spacing));
7271     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7272                                             Spacing * 2));
7273     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7274                                             Spacing * 3));
7275     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7276     TmpInst.addOperand(Inst.getOperand(4));
7277     Inst = TmpInst;
7278     return true;
7279   }
7280 
7281   case ARM::VST4dWB_register_Asm_8:
7282   case ARM::VST4dWB_register_Asm_16:
7283   case ARM::VST4dWB_register_Asm_32:
7284   case ARM::VST4qWB_register_Asm_8:
7285   case ARM::VST4qWB_register_Asm_16:
7286   case ARM::VST4qWB_register_Asm_32: {
7287     MCInst TmpInst;
7288     unsigned Spacing;
7289     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7290     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7291     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7292     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7293     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7294     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7295     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7296                                             Spacing));
7297     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7298                                             Spacing * 2));
7299     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7300                                             Spacing * 3));
7301     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7302     TmpInst.addOperand(Inst.getOperand(5));
7303     Inst = TmpInst;
7304     return true;
7305   }
7306 
7307   // Handle encoding choice for the shift-immediate instructions.
7308   case ARM::t2LSLri:
7309   case ARM::t2LSRri:
7310   case ARM::t2ASRri: {
7311     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7312         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7313         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7314         !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7315           static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7316       unsigned NewOpc;
7317       switch (Inst.getOpcode()) {
7318       default: llvm_unreachable("unexpected opcode");
7319       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7320       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7321       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7322       }
7323       // The Thumb1 operands aren't in the same order. Awesome, eh?
7324       MCInst TmpInst;
7325       TmpInst.setOpcode(NewOpc);
7326       TmpInst.addOperand(Inst.getOperand(0));
7327       TmpInst.addOperand(Inst.getOperand(5));
7328       TmpInst.addOperand(Inst.getOperand(1));
7329       TmpInst.addOperand(Inst.getOperand(2));
7330       TmpInst.addOperand(Inst.getOperand(3));
7331       TmpInst.addOperand(Inst.getOperand(4));
7332       Inst = TmpInst;
7333       return true;
7334     }
7335     return false;
7336   }
7337 
7338   // Handle the Thumb2 mode MOV complex aliases.
7339   case ARM::t2MOVsr:
7340   case ARM::t2MOVSsr: {
7341     // Which instruction to expand to depends on the CCOut operand and
7342     // whether we're in an IT block if the register operands are low
7343     // registers.
7344     bool isNarrow = false;
7345     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7346         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7347         isARMLowRegister(Inst.getOperand(2).getReg()) &&
7348         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7349         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7350       isNarrow = true;
7351     MCInst TmpInst;
7352     unsigned newOpc;
7353     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7354     default: llvm_unreachable("unexpected opcode!");
7355     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7356     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7357     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7358     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7359     }
7360     TmpInst.setOpcode(newOpc);
7361     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7362     if (isNarrow)
7363       TmpInst.addOperand(MCOperand::CreateReg(
7364           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7365     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7366     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7367     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7368     TmpInst.addOperand(Inst.getOperand(5));
7369     if (!isNarrow)
7370       TmpInst.addOperand(MCOperand::CreateReg(
7371           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7372     Inst = TmpInst;
7373     return true;
7374   }
7375   case ARM::t2MOVsi:
7376   case ARM::t2MOVSsi: {
7377     // Which instruction to expand to depends on the CCOut operand and
7378     // whether we're in an IT block if the register operands are low
7379     // registers.
7380     bool isNarrow = false;
7381     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7382         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7383         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7384       isNarrow = true;
7385     MCInst TmpInst;
7386     unsigned newOpc;
7387     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7388     default: llvm_unreachable("unexpected opcode!");
7389     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7390     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7391     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7392     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7393     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7394     }
7395     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7396     if (Amount == 32) Amount = 0;
7397     TmpInst.setOpcode(newOpc);
7398     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7399     if (isNarrow)
7400       TmpInst.addOperand(MCOperand::CreateReg(
7401           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7402     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7403     if (newOpc != ARM::t2RRX)
7404       TmpInst.addOperand(MCOperand::CreateImm(Amount));
7405     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7406     TmpInst.addOperand(Inst.getOperand(4));
7407     if (!isNarrow)
7408       TmpInst.addOperand(MCOperand::CreateReg(
7409           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7410     Inst = TmpInst;
7411     return true;
7412   }
7413   // Handle the ARM mode MOV complex aliases.
7414   case ARM::ASRr:
7415   case ARM::LSRr:
7416   case ARM::LSLr:
7417   case ARM::RORr: {
7418     ARM_AM::ShiftOpc ShiftTy;
7419     switch(Inst.getOpcode()) {
7420     default: llvm_unreachable("unexpected opcode!");
7421     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7422     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7423     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7424     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7425     }
7426     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7427     MCInst TmpInst;
7428     TmpInst.setOpcode(ARM::MOVsr);
7429     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7430     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7431     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7432     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7433     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7434     TmpInst.addOperand(Inst.getOperand(4));
7435     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7436     Inst = TmpInst;
7437     return true;
7438   }
7439   case ARM::ASRi:
7440   case ARM::LSRi:
7441   case ARM::LSLi:
7442   case ARM::RORi: {
7443     ARM_AM::ShiftOpc ShiftTy;
7444     switch(Inst.getOpcode()) {
7445     default: llvm_unreachable("unexpected opcode!");
7446     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7447     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7448     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7449     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7450     }
7451     // A shift by zero is a plain MOVr, not a MOVsi.
7452     unsigned Amt = Inst.getOperand(2).getImm();
7453     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7454     // A shift by 32 should be encoded as 0 when permitted
7455     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7456       Amt = 0;
7457     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7458     MCInst TmpInst;
7459     TmpInst.setOpcode(Opc);
7460     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7461     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7462     if (Opc == ARM::MOVsi)
7463       TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7464     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7465     TmpInst.addOperand(Inst.getOperand(4));
7466     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7467     Inst = TmpInst;
7468     return true;
7469   }
7470   case ARM::RRXi: {
7471     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7472     MCInst TmpInst;
7473     TmpInst.setOpcode(ARM::MOVsi);
7474     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7475     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7476     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7477     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7478     TmpInst.addOperand(Inst.getOperand(3));
7479     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7480     Inst = TmpInst;
7481     return true;
7482   }
7483   case ARM::t2LDMIA_UPD: {
7484     // If this is a load of a single register, then we should use
7485     // a post-indexed LDR instruction instead, per the ARM ARM.
7486     if (Inst.getNumOperands() != 5)
7487       return false;
7488     MCInst TmpInst;
7489     TmpInst.setOpcode(ARM::t2LDR_POST);
7490     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7491     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7492     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7493     TmpInst.addOperand(MCOperand::CreateImm(4));
7494     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7495     TmpInst.addOperand(Inst.getOperand(3));
7496     Inst = TmpInst;
7497     return true;
7498   }
7499   case ARM::t2STMDB_UPD: {
7500     // If this is a store of a single register, then we should use
7501     // a pre-indexed STR instruction instead, per the ARM ARM.
7502     if (Inst.getNumOperands() != 5)
7503       return false;
7504     MCInst TmpInst;
7505     TmpInst.setOpcode(ARM::t2STR_PRE);
7506     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7507     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7508     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7509     TmpInst.addOperand(MCOperand::CreateImm(-4));
7510     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7511     TmpInst.addOperand(Inst.getOperand(3));
7512     Inst = TmpInst;
7513     return true;
7514   }
7515   case ARM::LDMIA_UPD:
7516     // If this is a load of a single register via a 'pop', then we should use
7517     // a post-indexed LDR instruction instead, per the ARM ARM.
7518     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
7519         Inst.getNumOperands() == 5) {
7520       MCInst TmpInst;
7521       TmpInst.setOpcode(ARM::LDR_POST_IMM);
7522       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7523       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7524       TmpInst.addOperand(Inst.getOperand(1)); // Rn
7525       TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7526       TmpInst.addOperand(MCOperand::CreateImm(4));
7527       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7528       TmpInst.addOperand(Inst.getOperand(3));
7529       Inst = TmpInst;
7530       return true;
7531     }
7532     break;
7533   case ARM::STMDB_UPD:
7534     // If this is a store of a single register via a 'push', then we should use
7535     // a pre-indexed STR instruction instead, per the ARM ARM.
7536     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
7537         Inst.getNumOperands() == 5) {
7538       MCInst TmpInst;
7539       TmpInst.setOpcode(ARM::STR_PRE_IMM);
7540       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7541       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7542       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7543       TmpInst.addOperand(MCOperand::CreateImm(-4));
7544       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7545       TmpInst.addOperand(Inst.getOperand(3));
7546       Inst = TmpInst;
7547     }
7548     break;
7549   case ARM::t2ADDri12:
7550     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7551     // mnemonic was used (not "addw"), encoding T3 is preferred.
7552     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
7553         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7554       break;
7555     Inst.setOpcode(ARM::t2ADDri);
7556     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7557     break;
7558   case ARM::t2SUBri12:
7559     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7560     // mnemonic was used (not "subw"), encoding T3 is preferred.
7561     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
7562         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7563       break;
7564     Inst.setOpcode(ARM::t2SUBri);
7565     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7566     break;
7567   case ARM::tADDi8:
7568     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7569     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7570     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7571     // to encoding T1 if <Rd> is omitted."
7572     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7573       Inst.setOpcode(ARM::tADDi3);
7574       return true;
7575     }
7576     break;
7577   case ARM::tSUBi8:
7578     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7579     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7580     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7581     // to encoding T1 if <Rd> is omitted."
7582     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7583       Inst.setOpcode(ARM::tSUBi3);
7584       return true;
7585     }
7586     break;
7587   case ARM::t2ADDri:
7588   case ARM::t2SUBri: {
7589     // If the destination and first source operand are the same, and
7590     // the flags are compatible with the current IT status, use encoding T2
7591     // instead of T3. For compatibility with the system 'as'. Make sure the
7592     // wide encoding wasn't explicit.
7593     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7594         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7595         (unsigned)Inst.getOperand(2).getImm() > 255 ||
7596         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7597          (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7598         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7599          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7600       break;
7601     MCInst TmpInst;
7602     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7603                       ARM::tADDi8 : ARM::tSUBi8);
7604     TmpInst.addOperand(Inst.getOperand(0));
7605     TmpInst.addOperand(Inst.getOperand(5));
7606     TmpInst.addOperand(Inst.getOperand(0));
7607     TmpInst.addOperand(Inst.getOperand(2));
7608     TmpInst.addOperand(Inst.getOperand(3));
7609     TmpInst.addOperand(Inst.getOperand(4));
7610     Inst = TmpInst;
7611     return true;
7612   }
7613   case ARM::t2ADDrr: {
7614     // If the destination and first source operand are the same, and
7615     // there's no setting of the flags, use encoding T2 instead of T3.
7616     // Note that this is only for ADD, not SUB. This mirrors the system
7617     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7618     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7619         Inst.getOperand(5).getReg() != 0 ||
7620         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7621          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7622       break;
7623     MCInst TmpInst;
7624     TmpInst.setOpcode(ARM::tADDhirr);
7625     TmpInst.addOperand(Inst.getOperand(0));
7626     TmpInst.addOperand(Inst.getOperand(0));
7627     TmpInst.addOperand(Inst.getOperand(2));
7628     TmpInst.addOperand(Inst.getOperand(3));
7629     TmpInst.addOperand(Inst.getOperand(4));
7630     Inst = TmpInst;
7631     return true;
7632   }
7633   case ARM::tADDrSP: {
7634     // If the non-SP source operand and the destination operand are not the
7635     // same, we need to use the 32-bit encoding if it's available.
7636     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7637       Inst.setOpcode(ARM::t2ADDrr);
7638       Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7639       return true;
7640     }
7641     break;
7642   }
7643   case ARM::tB:
7644     // A Thumb conditional branch outside of an IT block is a tBcc.
7645     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7646       Inst.setOpcode(ARM::tBcc);
7647       return true;
7648     }
7649     break;
7650   case ARM::t2B:
7651     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7652     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7653       Inst.setOpcode(ARM::t2Bcc);
7654       return true;
7655     }
7656     break;
7657   case ARM::t2Bcc:
7658     // If the conditional is AL or we're in an IT block, we really want t2B.
7659     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7660       Inst.setOpcode(ARM::t2B);
7661       return true;
7662     }
7663     break;
7664   case ARM::tBcc:
7665     // If the conditional is AL, we really want tB.
7666     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7667       Inst.setOpcode(ARM::tB);
7668       return true;
7669     }
7670     break;
7671   case ARM::tLDMIA: {
7672     // If the register list contains any high registers, or if the writeback
7673     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7674     // instead if we're in Thumb2. Otherwise, this should have generated
7675     // an error in validateInstruction().
7676     unsigned Rn = Inst.getOperand(0).getReg();
7677     bool hasWritebackToken =
7678         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7679          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7680     bool listContainsBase;
7681     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7682         (!listContainsBase && !hasWritebackToken) ||
7683         (listContainsBase && hasWritebackToken)) {
7684       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7685       assert (isThumbTwo());
7686       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7687       // If we're switching to the updating version, we need to insert
7688       // the writeback tied operand.
7689       if (hasWritebackToken)
7690         Inst.insert(Inst.begin(),
7691                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7692       return true;
7693     }
7694     break;
7695   }
7696   case ARM::tSTMIA_UPD: {
7697     // If the register list contains any high registers, we need to use
7698     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7699     // should have generated an error in validateInstruction().
7700     unsigned Rn = Inst.getOperand(0).getReg();
7701     bool listContainsBase;
7702     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7703       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7704       assert (isThumbTwo());
7705       Inst.setOpcode(ARM::t2STMIA_UPD);
7706       return true;
7707     }
7708     break;
7709   }
7710   case ARM::tPOP: {
7711     bool listContainsBase;
7712     // If the register list contains any high registers, we need to use
7713     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7714     // should have generated an error in validateInstruction().
7715     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7716       return false;
7717     assert (isThumbTwo());
7718     Inst.setOpcode(ARM::t2LDMIA_UPD);
7719     // Add the base register and writeback operands.
7720     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7721     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7722     return true;
7723   }
7724   case ARM::tPUSH: {
7725     bool listContainsBase;
7726     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7727       return false;
7728     assert (isThumbTwo());
7729     Inst.setOpcode(ARM::t2STMDB_UPD);
7730     // Add the base register and writeback operands.
7731     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7732     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7733     return true;
7734   }
7735   case ARM::t2MOVi: {
7736     // If we can use the 16-bit encoding and the user didn't explicitly
7737     // request the 32-bit variant, transform it here.
7738     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7739         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7740         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7741           Inst.getOperand(4).getReg() == ARM::CPSR) ||
7742          (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7743         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7744          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7745       // The operands aren't in the same order for tMOVi8...
7746       MCInst TmpInst;
7747       TmpInst.setOpcode(ARM::tMOVi8);
7748       TmpInst.addOperand(Inst.getOperand(0));
7749       TmpInst.addOperand(Inst.getOperand(4));
7750       TmpInst.addOperand(Inst.getOperand(1));
7751       TmpInst.addOperand(Inst.getOperand(2));
7752       TmpInst.addOperand(Inst.getOperand(3));
7753       Inst = TmpInst;
7754       return true;
7755     }
7756     break;
7757   }
7758   case ARM::t2MOVr: {
7759     // If we can use the 16-bit encoding and the user didn't explicitly
7760     // request the 32-bit variant, transform it here.
7761     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7762         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7763         Inst.getOperand(2).getImm() == ARMCC::AL &&
7764         Inst.getOperand(4).getReg() == ARM::CPSR &&
7765         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7766          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7767       // The operands aren't the same for tMOV[S]r... (no cc_out)
7768       MCInst TmpInst;
7769       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7770       TmpInst.addOperand(Inst.getOperand(0));
7771       TmpInst.addOperand(Inst.getOperand(1));
7772       TmpInst.addOperand(Inst.getOperand(2));
7773       TmpInst.addOperand(Inst.getOperand(3));
7774       Inst = TmpInst;
7775       return true;
7776     }
7777     break;
7778   }
7779   case ARM::t2SXTH:
7780   case ARM::t2SXTB:
7781   case ARM::t2UXTH:
7782   case ARM::t2UXTB: {
7783     // If we can use the 16-bit encoding and the user didn't explicitly
7784     // request the 32-bit variant, transform it here.
7785     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7786         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7787         Inst.getOperand(2).getImm() == 0 &&
7788         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7789          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7790       unsigned NewOpc;
7791       switch (Inst.getOpcode()) {
7792       default: llvm_unreachable("Illegal opcode!");
7793       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7794       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7795       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7796       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7797       }
7798       // The operands aren't the same for thumb1 (no rotate operand).
7799       MCInst TmpInst;
7800       TmpInst.setOpcode(NewOpc);
7801       TmpInst.addOperand(Inst.getOperand(0));
7802       TmpInst.addOperand(Inst.getOperand(1));
7803       TmpInst.addOperand(Inst.getOperand(3));
7804       TmpInst.addOperand(Inst.getOperand(4));
7805       Inst = TmpInst;
7806       return true;
7807     }
7808     break;
7809   }
7810   case ARM::MOVsi: {
7811     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7812     // rrx shifts and asr/lsr of #32 is encoded as 0
7813     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7814       return false;
7815     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7816       // Shifting by zero is accepted as a vanilla 'MOVr'
7817       MCInst TmpInst;
7818       TmpInst.setOpcode(ARM::MOVr);
7819       TmpInst.addOperand(Inst.getOperand(0));
7820       TmpInst.addOperand(Inst.getOperand(1));
7821       TmpInst.addOperand(Inst.getOperand(3));
7822       TmpInst.addOperand(Inst.getOperand(4));
7823       TmpInst.addOperand(Inst.getOperand(5));
7824       Inst = TmpInst;
7825       return true;
7826     }
7827     return false;
7828   }
7829   case ARM::ANDrsi:
7830   case ARM::ORRrsi:
7831   case ARM::EORrsi:
7832   case ARM::BICrsi:
7833   case ARM::SUBrsi:
7834   case ARM::ADDrsi: {
7835     unsigned newOpc;
7836     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7837     if (SOpc == ARM_AM::rrx) return false;
7838     switch (Inst.getOpcode()) {
7839     default: llvm_unreachable("unexpected opcode!");
7840     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7841     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7842     case ARM::EORrsi: newOpc = ARM::EORrr; break;
7843     case ARM::BICrsi: newOpc = ARM::BICrr; break;
7844     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7845     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7846     }
7847     // If the shift is by zero, use the non-shifted instruction definition.
7848     // The exception is for right shifts, where 0 == 32
7849     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7850         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7851       MCInst TmpInst;
7852       TmpInst.setOpcode(newOpc);
7853       TmpInst.addOperand(Inst.getOperand(0));
7854       TmpInst.addOperand(Inst.getOperand(1));
7855       TmpInst.addOperand(Inst.getOperand(2));
7856       TmpInst.addOperand(Inst.getOperand(4));
7857       TmpInst.addOperand(Inst.getOperand(5));
7858       TmpInst.addOperand(Inst.getOperand(6));
7859       Inst = TmpInst;
7860       return true;
7861     }
7862     return false;
7863   }
7864   case ARM::ITasm:
7865   case ARM::t2IT: {
7866     // The mask bits for all but the first condition are represented as
7867     // the low bit of the condition code value implies 't'. We currently
7868     // always have 1 implies 't', so XOR toggle the bits if the low bit
7869     // of the condition code is zero.
7870     MCOperand &MO = Inst.getOperand(1);
7871     unsigned Mask = MO.getImm();
7872     unsigned OrigMask = Mask;
7873     unsigned TZ = countTrailingZeros(Mask);
7874     if ((Inst.getOperand(0).getImm() & 1) == 0) {
7875       assert(Mask && TZ <= 3 && "illegal IT mask value!");
7876       Mask ^= (0xE << TZ) & 0xF;
7877     }
7878     MO.setImm(Mask);
7879 
7880     // Set up the IT block state according to the IT instruction we just
7881     // matched.
7882     assert(!inITBlock() && "nested IT blocks?!");
7883     ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7884     ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7885     ITState.CurPosition = 0;
7886     ITState.FirstCond = true;
7887     break;
7888   }
7889   case ARM::t2LSLrr:
7890   case ARM::t2LSRrr:
7891   case ARM::t2ASRrr:
7892   case ARM::t2SBCrr:
7893   case ARM::t2RORrr:
7894   case ARM::t2BICrr:
7895   {
7896     // Assemblers should use the narrow encodings of these instructions when permissible.
7897     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7898          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7899         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7900         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7901          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7902         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
7903          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
7904              ".w"))) {
7905       unsigned NewOpc;
7906       switch (Inst.getOpcode()) {
7907         default: llvm_unreachable("unexpected opcode");
7908         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7909         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7910         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7911         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7912         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7913         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7914       }
7915       MCInst TmpInst;
7916       TmpInst.setOpcode(NewOpc);
7917       TmpInst.addOperand(Inst.getOperand(0));
7918       TmpInst.addOperand(Inst.getOperand(5));
7919       TmpInst.addOperand(Inst.getOperand(1));
7920       TmpInst.addOperand(Inst.getOperand(2));
7921       TmpInst.addOperand(Inst.getOperand(3));
7922       TmpInst.addOperand(Inst.getOperand(4));
7923       Inst = TmpInst;
7924       return true;
7925     }
7926     return false;
7927   }
7928   case ARM::t2ANDrr:
7929   case ARM::t2EORrr:
7930   case ARM::t2ADCrr:
7931   case ARM::t2ORRrr:
7932   {
7933     // Assemblers should use the narrow encodings of these instructions when permissible.
7934     // These instructions are special in that they are commutable, so shorter encodings
7935     // are available more often.
7936     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7937          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7938         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7939          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7940         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7941          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7942         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
7943          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
7944              ".w"))) {
7945       unsigned NewOpc;
7946       switch (Inst.getOpcode()) {
7947         default: llvm_unreachable("unexpected opcode");
7948         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7949         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7950         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7951         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7952       }
7953       MCInst TmpInst;
7954       TmpInst.setOpcode(NewOpc);
7955       TmpInst.addOperand(Inst.getOperand(0));
7956       TmpInst.addOperand(Inst.getOperand(5));
7957       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7958         TmpInst.addOperand(Inst.getOperand(1));
7959         TmpInst.addOperand(Inst.getOperand(2));
7960       } else {
7961         TmpInst.addOperand(Inst.getOperand(2));
7962         TmpInst.addOperand(Inst.getOperand(1));
7963       }
7964       TmpInst.addOperand(Inst.getOperand(3));
7965       TmpInst.addOperand(Inst.getOperand(4));
7966       Inst = TmpInst;
7967       return true;
7968     }
7969     return false;
7970   }
7971   }
7972   return false;
7973 }
7974 
7975 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7976   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7977   // suffix depending on whether they're in an IT block or not.
7978   unsigned Opc = Inst.getOpcode();
7979   const MCInstrDesc &MCID = MII.get(Opc);
7980   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7981     assert(MCID.hasOptionalDef() &&
7982            "optionally flag setting instruction missing optional def operand");
7983     assert(MCID.NumOperands == Inst.getNumOperands() &&
7984            "operand count mismatch!");
7985     // Find the optional-def operand (cc_out).
7986     unsigned OpNo;
7987     for (OpNo = 0;
7988          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7989          ++OpNo)
7990       ;
7991     // If we're parsing Thumb1, reject it completely.
7992     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7993       return Match_MnemonicFail;
7994     // If we're parsing Thumb2, which form is legal depends on whether we're
7995     // in an IT block.
7996     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7997         !inITBlock())
7998       return Match_RequiresITBlock;
7999     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8000         inITBlock())
8001       return Match_RequiresNotITBlock;
8002   }
8003   // Some high-register supporting Thumb1 encodings only allow both registers
8004   // to be from r0-r7 when in Thumb2.
8005   else if (Opc == ARM::tADDhirr && isThumbOne() &&
8006            isARMLowRegister(Inst.getOperand(1).getReg()) &&
8007            isARMLowRegister(Inst.getOperand(2).getReg()))
8008     return Match_RequiresThumb2;
8009   // Others only require ARMv6 or later.
8010   else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8011            isARMLowRegister(Inst.getOperand(0).getReg()) &&
8012            isARMLowRegister(Inst.getOperand(1).getReg()))
8013     return Match_RequiresV6;
8014   return Match_Success;
8015 }
8016 
8017 namespace llvm {
8018 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8019   return true; // In an assembly source, no need to second-guess
8020 }
8021 }
8022 
8023 static const char *getSubtargetFeatureName(unsigned Val);
8024 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8025                                            OperandVector &Operands,
8026                                            MCStreamer &Out, unsigned &ErrorInfo,
8027                                            bool MatchingInlineAsm) {
8028   MCInst Inst;
8029   unsigned MatchResult;
8030 
8031   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8032                                      MatchingInlineAsm);
8033   switch (MatchResult) {
8034   default: break;
8035   case Match_Success:
8036     // Context sensitive operand constraints aren't handled by the matcher,
8037     // so check them here.
8038     if (validateInstruction(Inst, Operands)) {
8039       // Still progress the IT block, otherwise one wrong condition causes
8040       // nasty cascading errors.
8041       forwardITPosition();
8042       return true;
8043     }
8044 
8045     { // processInstruction() updates inITBlock state, we need to save it away
8046       bool wasInITBlock = inITBlock();
8047 
8048       // Some instructions need post-processing to, for example, tweak which
8049       // encoding is selected. Loop on it while changes happen so the
8050       // individual transformations can chain off each other. E.g.,
8051       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8052       while (processInstruction(Inst, Operands))
8053         ;
8054 
8055       // Only after the instruction is fully processed, we can validate it
8056       if (wasInITBlock && hasV8Ops() && isThumb() &&
8057           !isV8EligibleForIT(&Inst)) {
8058         Warning(IDLoc, "deprecated instruction in IT block");
8059       }
8060     }
8061 
8062     // Only move forward at the very end so that everything in validate
8063     // and process gets a consistent answer about whether we're in an IT
8064     // block.
8065     forwardITPosition();
8066 
8067     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8068     // doesn't actually encode.
8069     if (Inst.getOpcode() == ARM::ITasm)
8070       return false;
8071 
8072     Inst.setLoc(IDLoc);
8073     Out.EmitInstruction(Inst, STI);
8074     return false;
8075   case Match_MissingFeature: {
8076     assert(ErrorInfo && "Unknown missing feature!");
8077     // Special case the error message for the very common case where only
8078     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8079     std::string Msg = "instruction requires:";
8080     unsigned Mask = 1;
8081     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8082       if (ErrorInfo & Mask) {
8083         Msg += " ";
8084         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8085       }
8086       Mask <<= 1;
8087     }
8088     return Error(IDLoc, Msg);
8089   }
8090   case Match_InvalidOperand: {
8091     SMLoc ErrorLoc = IDLoc;
8092     if (ErrorInfo != ~0U) {
8093       if (ErrorInfo >= Operands.size())
8094         return Error(IDLoc, "too few operands for instruction");
8095 
8096       ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8097       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8098     }
8099 
8100     return Error(ErrorLoc, "invalid operand for instruction");
8101   }
8102   case Match_MnemonicFail:
8103     return Error(IDLoc, "invalid instruction",
8104                  ((ARMOperand &)*Operands[0]).getLocRange());
8105   case Match_RequiresNotITBlock:
8106     return Error(IDLoc, "flag setting instruction only valid outside IT block");
8107   case Match_RequiresITBlock:
8108     return Error(IDLoc, "instruction only valid inside IT block");
8109   case Match_RequiresV6:
8110     return Error(IDLoc, "instruction variant requires ARMv6 or later");
8111   case Match_RequiresThumb2:
8112     return Error(IDLoc, "instruction variant requires Thumb2");
8113   case Match_ImmRange0_15: {
8114     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8115     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8116     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8117   }
8118   case Match_ImmRange0_239: {
8119     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8120     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8121     return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8122   }
8123   case Match_AlignedMemoryRequiresNone:
8124   case Match_DupAlignedMemoryRequiresNone:
8125   case Match_AlignedMemoryRequires16:
8126   case Match_DupAlignedMemoryRequires16:
8127   case Match_AlignedMemoryRequires32:
8128   case Match_DupAlignedMemoryRequires32:
8129   case Match_AlignedMemoryRequires64:
8130   case Match_DupAlignedMemoryRequires64:
8131   case Match_AlignedMemoryRequires64or128:
8132   case Match_DupAlignedMemoryRequires64or128:
8133   case Match_AlignedMemoryRequires64or128or256:
8134   {
8135     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8136     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8137     switch (MatchResult) {
8138       default:
8139         llvm_unreachable("Missing Match_Aligned type");
8140       case Match_AlignedMemoryRequiresNone:
8141       case Match_DupAlignedMemoryRequiresNone:
8142         return Error(ErrorLoc, "alignment must be omitted");
8143       case Match_AlignedMemoryRequires16:
8144       case Match_DupAlignedMemoryRequires16:
8145         return Error(ErrorLoc, "alignment must be 16 or omitted");
8146       case Match_AlignedMemoryRequires32:
8147       case Match_DupAlignedMemoryRequires32:
8148         return Error(ErrorLoc, "alignment must be 32 or omitted");
8149       case Match_AlignedMemoryRequires64:
8150       case Match_DupAlignedMemoryRequires64:
8151         return Error(ErrorLoc, "alignment must be 64 or omitted");
8152       case Match_AlignedMemoryRequires64or128:
8153       case Match_DupAlignedMemoryRequires64or128:
8154         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8155       case Match_AlignedMemoryRequires64or128or256:
8156         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8157     }
8158   }
8159   }
8160 
8161   llvm_unreachable("Implement any new match types added!");
8162 }
8163 
8164 /// parseDirective parses the arm specific directives
8165 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8166   const MCObjectFileInfo::Environment Format =
8167     getContext().getObjectFileInfo()->getObjectFileType();
8168   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8169 
8170   StringRef IDVal = DirectiveID.getIdentifier();
8171   if (IDVal == ".word")
8172     return parseLiteralValues(4, DirectiveID.getLoc());
8173   else if (IDVal == ".short" || IDVal == ".hword")
8174     return parseLiteralValues(2, DirectiveID.getLoc());
8175   else if (IDVal == ".thumb")
8176     return parseDirectiveThumb(DirectiveID.getLoc());
8177   else if (IDVal == ".arm")
8178     return parseDirectiveARM(DirectiveID.getLoc());
8179   else if (IDVal == ".thumb_func")
8180     return parseDirectiveThumbFunc(DirectiveID.getLoc());
8181   else if (IDVal == ".code")
8182     return parseDirectiveCode(DirectiveID.getLoc());
8183   else if (IDVal == ".syntax")
8184     return parseDirectiveSyntax(DirectiveID.getLoc());
8185   else if (IDVal == ".unreq")
8186     return parseDirectiveUnreq(DirectiveID.getLoc());
8187   else if (IDVal == ".fnend")
8188     return parseDirectiveFnEnd(DirectiveID.getLoc());
8189   else if (IDVal == ".cantunwind")
8190     return parseDirectiveCantUnwind(DirectiveID.getLoc());
8191   else if (IDVal == ".personality")
8192     return parseDirectivePersonality(DirectiveID.getLoc());
8193   else if (IDVal == ".handlerdata")
8194     return parseDirectiveHandlerData(DirectiveID.getLoc());
8195   else if (IDVal == ".setfp")
8196     return parseDirectiveSetFP(DirectiveID.getLoc());
8197   else if (IDVal == ".pad")
8198     return parseDirectivePad(DirectiveID.getLoc());
8199   else if (IDVal == ".save")
8200     return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8201   else if (IDVal == ".vsave")
8202     return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8203   else if (IDVal == ".ltorg" || IDVal == ".pool")
8204     return parseDirectiveLtorg(DirectiveID.getLoc());
8205   else if (IDVal == ".even")
8206     return parseDirectiveEven(DirectiveID.getLoc());
8207   else if (IDVal == ".personalityindex")
8208     return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8209   else if (IDVal == ".unwind_raw")
8210     return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8211   else if (IDVal == ".movsp")
8212     return parseDirectiveMovSP(DirectiveID.getLoc());
8213   else if (IDVal == ".arch_extension")
8214     return parseDirectiveArchExtension(DirectiveID.getLoc());
8215   else if (IDVal == ".align")
8216     return parseDirectiveAlign(DirectiveID.getLoc());
8217   else if (IDVal == ".thumb_set")
8218     return parseDirectiveThumbSet(DirectiveID.getLoc());
8219 
8220   if (!IsMachO) {
8221     if (IDVal == ".arch")
8222       return parseDirectiveArch(DirectiveID.getLoc());
8223     else if (IDVal == ".cpu")
8224       return parseDirectiveCPU(DirectiveID.getLoc());
8225     else if (IDVal == ".eabi_attribute")
8226       return parseDirectiveEabiAttr(DirectiveID.getLoc());
8227     else if (IDVal == ".fpu")
8228       return parseDirectiveFPU(DirectiveID.getLoc());
8229     else if (IDVal == ".fnstart")
8230       return parseDirectiveFnStart(DirectiveID.getLoc());
8231     else if (IDVal == ".inst")
8232       return parseDirectiveInst(DirectiveID.getLoc());
8233     else if (IDVal == ".inst.n")
8234       return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8235     else if (IDVal == ".inst.w")
8236       return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8237     else if (IDVal == ".object_arch")
8238       return parseDirectiveObjectArch(DirectiveID.getLoc());
8239     else if (IDVal == ".tlsdescseq")
8240       return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8241   }
8242 
8243   return true;
8244 }
8245 
8246 /// parseLiteralValues
8247 ///  ::= .hword expression [, expression]*
8248 ///  ::= .short expression [, expression]*
8249 ///  ::= .word expression [, expression]*
8250 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8251   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8252     for (;;) {
8253       const MCExpr *Value;
8254       if (getParser().parseExpression(Value)) {
8255         Parser.eatToEndOfStatement();
8256         return false;
8257       }
8258 
8259       getParser().getStreamer().EmitValue(Value, Size);
8260 
8261       if (getLexer().is(AsmToken::EndOfStatement))
8262         break;
8263 
8264       // FIXME: Improve diagnostic.
8265       if (getLexer().isNot(AsmToken::Comma)) {
8266         Error(L, "unexpected token in directive");
8267         return false;
8268       }
8269       Parser.Lex();
8270     }
8271   }
8272 
8273   Parser.Lex();
8274   return false;
8275 }
8276 
8277 /// parseDirectiveThumb
8278 ///  ::= .thumb
8279 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8280   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8281     Error(L, "unexpected token in directive");
8282     return false;
8283   }
8284   Parser.Lex();
8285 
8286   if (!hasThumb()) {
8287     Error(L, "target does not support Thumb mode");
8288     return false;
8289   }
8290 
8291   if (!isThumb())
8292     SwitchMode();
8293 
8294   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8295   return false;
8296 }
8297 
8298 /// parseDirectiveARM
8299 ///  ::= .arm
8300 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8301   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8302     Error(L, "unexpected token in directive");
8303     return false;
8304   }
8305   Parser.Lex();
8306 
8307   if (!hasARM()) {
8308     Error(L, "target does not support ARM mode");
8309     return false;
8310   }
8311 
8312   if (isThumb())
8313     SwitchMode();
8314 
8315   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8316   return false;
8317 }
8318 
8319 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8320   if (NextSymbolIsThumb) {
8321     getParser().getStreamer().EmitThumbFunc(Symbol);
8322     NextSymbolIsThumb = false;
8323   }
8324 }
8325 
8326 /// parseDirectiveThumbFunc
8327 ///  ::= .thumbfunc symbol_name
8328 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8329   const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8330   bool isMachO = MAI->hasSubsectionsViaSymbols();
8331 
8332   // Darwin asm has (optionally) function name after .thumb_func direction
8333   // ELF doesn't
8334   if (isMachO) {
8335     const AsmToken &Tok = Parser.getTok();
8336     if (Tok.isNot(AsmToken::EndOfStatement)) {
8337       if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8338         Error(L, "unexpected token in .thumb_func directive");
8339         return false;
8340       }
8341 
8342       MCSymbol *Func =
8343           getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8344       getParser().getStreamer().EmitThumbFunc(Func);
8345       Parser.Lex(); // Consume the identifier token.
8346       return false;
8347     }
8348   }
8349 
8350   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8351     Error(L, "unexpected token in directive");
8352     return false;
8353   }
8354 
8355   NextSymbolIsThumb = true;
8356   return false;
8357 }
8358 
8359 /// parseDirectiveSyntax
8360 ///  ::= .syntax unified | divided
8361 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8362   const AsmToken &Tok = Parser.getTok();
8363   if (Tok.isNot(AsmToken::Identifier)) {
8364     Error(L, "unexpected token in .syntax directive");
8365     return false;
8366   }
8367 
8368   StringRef Mode = Tok.getString();
8369   if (Mode == "unified" || Mode == "UNIFIED") {
8370     Parser.Lex();
8371   } else if (Mode == "divided" || Mode == "DIVIDED") {
8372     Error(L, "'.syntax divided' arm asssembly not supported");
8373     return false;
8374   } else {
8375     Error(L, "unrecognized syntax mode in .syntax directive");
8376     return false;
8377   }
8378 
8379   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8380     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8381     return false;
8382   }
8383   Parser.Lex();
8384 
8385   // TODO tell the MC streamer the mode
8386   // getParser().getStreamer().Emit???();
8387   return false;
8388 }
8389 
8390 /// parseDirectiveCode
8391 ///  ::= .code 16 | 32
8392 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8393   const AsmToken &Tok = Parser.getTok();
8394   if (Tok.isNot(AsmToken::Integer)) {
8395     Error(L, "unexpected token in .code directive");
8396     return false;
8397   }
8398   int64_t Val = Parser.getTok().getIntVal();
8399   if (Val != 16 && Val != 32) {
8400     Error(L, "invalid operand to .code directive");
8401     return false;
8402   }
8403   Parser.Lex();
8404 
8405   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8406     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8407     return false;
8408   }
8409   Parser.Lex();
8410 
8411   if (Val == 16) {
8412     if (!hasThumb()) {
8413       Error(L, "target does not support Thumb mode");
8414       return false;
8415     }
8416 
8417     if (!isThumb())
8418       SwitchMode();
8419     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8420   } else {
8421     if (!hasARM()) {
8422       Error(L, "target does not support ARM mode");
8423       return false;
8424     }
8425 
8426     if (isThumb())
8427       SwitchMode();
8428     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8429   }
8430 
8431   return false;
8432 }
8433 
8434 /// parseDirectiveReq
8435 ///  ::= name .req registername
8436 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8437   Parser.Lex(); // Eat the '.req' token.
8438   unsigned Reg;
8439   SMLoc SRegLoc, ERegLoc;
8440   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8441     Parser.eatToEndOfStatement();
8442     Error(SRegLoc, "register name expected");
8443     return false;
8444   }
8445 
8446   // Shouldn't be anything else.
8447   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8448     Parser.eatToEndOfStatement();
8449     Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8450     return false;
8451   }
8452 
8453   Parser.Lex(); // Consume the EndOfStatement
8454 
8455   if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8456     Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8457     return false;
8458   }
8459 
8460   return false;
8461 }
8462 
8463 /// parseDirectiveUneq
8464 ///  ::= .unreq registername
8465 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8466   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8467     Parser.eatToEndOfStatement();
8468     Error(L, "unexpected input in .unreq directive.");
8469     return false;
8470   }
8471   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8472   Parser.Lex(); // Eat the identifier.
8473   return false;
8474 }
8475 
8476 /// parseDirectiveArch
8477 ///  ::= .arch token
8478 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8479   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8480 
8481   unsigned ID = StringSwitch<unsigned>(Arch)
8482 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8483     .Case(NAME, ARM::ID)
8484 #define ARM_ARCH_ALIAS(NAME, ID) \
8485     .Case(NAME, ARM::ID)
8486 #include "MCTargetDesc/ARMArchName.def"
8487     .Default(ARM::INVALID_ARCH);
8488 
8489   if (ID == ARM::INVALID_ARCH) {
8490     Error(L, "Unknown arch name");
8491     return false;
8492   }
8493 
8494   getTargetStreamer().emitArch(ID);
8495   return false;
8496 }
8497 
8498 /// parseDirectiveEabiAttr
8499 ///  ::= .eabi_attribute int, int [, "str"]
8500 ///  ::= .eabi_attribute Tag_name, int [, "str"]
8501 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8502   int64_t Tag;
8503   SMLoc TagLoc;
8504   TagLoc = Parser.getTok().getLoc();
8505   if (Parser.getTok().is(AsmToken::Identifier)) {
8506     StringRef Name = Parser.getTok().getIdentifier();
8507     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8508     if (Tag == -1) {
8509       Error(TagLoc, "attribute name not recognised: " + Name);
8510       Parser.eatToEndOfStatement();
8511       return false;
8512     }
8513     Parser.Lex();
8514   } else {
8515     const MCExpr *AttrExpr;
8516 
8517     TagLoc = Parser.getTok().getLoc();
8518     if (Parser.parseExpression(AttrExpr)) {
8519       Parser.eatToEndOfStatement();
8520       return false;
8521     }
8522 
8523     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8524     if (!CE) {
8525       Error(TagLoc, "expected numeric constant");
8526       Parser.eatToEndOfStatement();
8527       return false;
8528     }
8529 
8530     Tag = CE->getValue();
8531   }
8532 
8533   if (Parser.getTok().isNot(AsmToken::Comma)) {
8534     Error(Parser.getTok().getLoc(), "comma expected");
8535     Parser.eatToEndOfStatement();
8536     return false;
8537   }
8538   Parser.Lex(); // skip comma
8539 
8540   StringRef StringValue = "";
8541   bool IsStringValue = false;
8542 
8543   int64_t IntegerValue = 0;
8544   bool IsIntegerValue = false;
8545 
8546   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8547     IsStringValue = true;
8548   else if (Tag == ARMBuildAttrs::compatibility) {
8549     IsStringValue = true;
8550     IsIntegerValue = true;
8551   } else if (Tag < 32 || Tag % 2 == 0)
8552     IsIntegerValue = true;
8553   else if (Tag % 2 == 1)
8554     IsStringValue = true;
8555   else
8556     llvm_unreachable("invalid tag type");
8557 
8558   if (IsIntegerValue) {
8559     const MCExpr *ValueExpr;
8560     SMLoc ValueExprLoc = Parser.getTok().getLoc();
8561     if (Parser.parseExpression(ValueExpr)) {
8562       Parser.eatToEndOfStatement();
8563       return false;
8564     }
8565 
8566     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8567     if (!CE) {
8568       Error(ValueExprLoc, "expected numeric constant");
8569       Parser.eatToEndOfStatement();
8570       return false;
8571     }
8572 
8573     IntegerValue = CE->getValue();
8574   }
8575 
8576   if (Tag == ARMBuildAttrs::compatibility) {
8577     if (Parser.getTok().isNot(AsmToken::Comma))
8578       IsStringValue = false;
8579     else
8580       Parser.Lex();
8581   }
8582 
8583   if (IsStringValue) {
8584     if (Parser.getTok().isNot(AsmToken::String)) {
8585       Error(Parser.getTok().getLoc(), "bad string constant");
8586       Parser.eatToEndOfStatement();
8587       return false;
8588     }
8589 
8590     StringValue = Parser.getTok().getStringContents();
8591     Parser.Lex();
8592   }
8593 
8594   if (IsIntegerValue && IsStringValue) {
8595     assert(Tag == ARMBuildAttrs::compatibility);
8596     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8597   } else if (IsIntegerValue)
8598     getTargetStreamer().emitAttribute(Tag, IntegerValue);
8599   else if (IsStringValue)
8600     getTargetStreamer().emitTextAttribute(Tag, StringValue);
8601   return false;
8602 }
8603 
8604 /// parseDirectiveCPU
8605 ///  ::= .cpu str
8606 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8607   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8608   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8609   return false;
8610 }
8611 
8612 /// parseDirectiveFPU
8613 ///  ::= .fpu str
8614 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8615   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8616 
8617   unsigned ID = StringSwitch<unsigned>(FPU)
8618 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8619 #include "ARMFPUName.def"
8620     .Default(ARM::INVALID_FPU);
8621 
8622   if (ID == ARM::INVALID_FPU) {
8623     Error(L, "Unknown FPU name");
8624     return false;
8625   }
8626 
8627   getTargetStreamer().emitFPU(ID);
8628   return false;
8629 }
8630 
8631 /// parseDirectiveFnStart
8632 ///  ::= .fnstart
8633 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8634   if (UC.hasFnStart()) {
8635     Error(L, ".fnstart starts before the end of previous one");
8636     UC.emitFnStartLocNotes();
8637     return false;
8638   }
8639 
8640   // Reset the unwind directives parser state
8641   UC.reset();
8642 
8643   getTargetStreamer().emitFnStart();
8644 
8645   UC.recordFnStart(L);
8646   return false;
8647 }
8648 
8649 /// parseDirectiveFnEnd
8650 ///  ::= .fnend
8651 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8652   // Check the ordering of unwind directives
8653   if (!UC.hasFnStart()) {
8654     Error(L, ".fnstart must precede .fnend directive");
8655     return false;
8656   }
8657 
8658   // Reset the unwind directives parser state
8659   getTargetStreamer().emitFnEnd();
8660 
8661   UC.reset();
8662   return false;
8663 }
8664 
8665 /// parseDirectiveCantUnwind
8666 ///  ::= .cantunwind
8667 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8668   UC.recordCantUnwind(L);
8669 
8670   // Check the ordering of unwind directives
8671   if (!UC.hasFnStart()) {
8672     Error(L, ".fnstart must precede .cantunwind directive");
8673     return false;
8674   }
8675   if (UC.hasHandlerData()) {
8676     Error(L, ".cantunwind can't be used with .handlerdata directive");
8677     UC.emitHandlerDataLocNotes();
8678     return false;
8679   }
8680   if (UC.hasPersonality()) {
8681     Error(L, ".cantunwind can't be used with .personality directive");
8682     UC.emitPersonalityLocNotes();
8683     return false;
8684   }
8685 
8686   getTargetStreamer().emitCantUnwind();
8687   return false;
8688 }
8689 
8690 /// parseDirectivePersonality
8691 ///  ::= .personality name
8692 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8693   bool HasExistingPersonality = UC.hasPersonality();
8694 
8695   UC.recordPersonality(L);
8696 
8697   // Check the ordering of unwind directives
8698   if (!UC.hasFnStart()) {
8699     Error(L, ".fnstart must precede .personality directive");
8700     return false;
8701   }
8702   if (UC.cantUnwind()) {
8703     Error(L, ".personality can't be used with .cantunwind directive");
8704     UC.emitCantUnwindLocNotes();
8705     return false;
8706   }
8707   if (UC.hasHandlerData()) {
8708     Error(L, ".personality must precede .handlerdata directive");
8709     UC.emitHandlerDataLocNotes();
8710     return false;
8711   }
8712   if (HasExistingPersonality) {
8713     Parser.eatToEndOfStatement();
8714     Error(L, "multiple personality directives");
8715     UC.emitPersonalityLocNotes();
8716     return false;
8717   }
8718 
8719   // Parse the name of the personality routine
8720   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8721     Parser.eatToEndOfStatement();
8722     Error(L, "unexpected input in .personality directive.");
8723     return false;
8724   }
8725   StringRef Name(Parser.getTok().getIdentifier());
8726   Parser.Lex();
8727 
8728   MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8729   getTargetStreamer().emitPersonality(PR);
8730   return false;
8731 }
8732 
8733 /// parseDirectiveHandlerData
8734 ///  ::= .handlerdata
8735 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8736   UC.recordHandlerData(L);
8737 
8738   // Check the ordering of unwind directives
8739   if (!UC.hasFnStart()) {
8740     Error(L, ".fnstart must precede .personality directive");
8741     return false;
8742   }
8743   if (UC.cantUnwind()) {
8744     Error(L, ".handlerdata can't be used with .cantunwind directive");
8745     UC.emitCantUnwindLocNotes();
8746     return false;
8747   }
8748 
8749   getTargetStreamer().emitHandlerData();
8750   return false;
8751 }
8752 
8753 /// parseDirectiveSetFP
8754 ///  ::= .setfp fpreg, spreg [, offset]
8755 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8756   // Check the ordering of unwind directives
8757   if (!UC.hasFnStart()) {
8758     Error(L, ".fnstart must precede .setfp directive");
8759     return false;
8760   }
8761   if (UC.hasHandlerData()) {
8762     Error(L, ".setfp must precede .handlerdata directive");
8763     return false;
8764   }
8765 
8766   // Parse fpreg
8767   SMLoc FPRegLoc = Parser.getTok().getLoc();
8768   int FPReg = tryParseRegister();
8769   if (FPReg == -1) {
8770     Error(FPRegLoc, "frame pointer register expected");
8771     return false;
8772   }
8773 
8774   // Consume comma
8775   if (Parser.getTok().isNot(AsmToken::Comma)) {
8776     Error(Parser.getTok().getLoc(), "comma expected");
8777     return false;
8778   }
8779   Parser.Lex(); // skip comma
8780 
8781   // Parse spreg
8782   SMLoc SPRegLoc = Parser.getTok().getLoc();
8783   int SPReg = tryParseRegister();
8784   if (SPReg == -1) {
8785     Error(SPRegLoc, "stack pointer register expected");
8786     return false;
8787   }
8788 
8789   if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8790     Error(SPRegLoc, "register should be either $sp or the latest fp register");
8791     return false;
8792   }
8793 
8794   // Update the frame pointer register
8795   UC.saveFPReg(FPReg);
8796 
8797   // Parse offset
8798   int64_t Offset = 0;
8799   if (Parser.getTok().is(AsmToken::Comma)) {
8800     Parser.Lex(); // skip comma
8801 
8802     if (Parser.getTok().isNot(AsmToken::Hash) &&
8803         Parser.getTok().isNot(AsmToken::Dollar)) {
8804       Error(Parser.getTok().getLoc(), "'#' expected");
8805       return false;
8806     }
8807     Parser.Lex(); // skip hash token.
8808 
8809     const MCExpr *OffsetExpr;
8810     SMLoc ExLoc = Parser.getTok().getLoc();
8811     SMLoc EndLoc;
8812     if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8813       Error(ExLoc, "malformed setfp offset");
8814       return false;
8815     }
8816     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8817     if (!CE) {
8818       Error(ExLoc, "setfp offset must be an immediate");
8819       return false;
8820     }
8821 
8822     Offset = CE->getValue();
8823   }
8824 
8825   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8826                                 static_cast<unsigned>(SPReg), Offset);
8827   return false;
8828 }
8829 
8830 /// parseDirective
8831 ///  ::= .pad offset
8832 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8833   // Check the ordering of unwind directives
8834   if (!UC.hasFnStart()) {
8835     Error(L, ".fnstart must precede .pad directive");
8836     return false;
8837   }
8838   if (UC.hasHandlerData()) {
8839     Error(L, ".pad must precede .handlerdata directive");
8840     return false;
8841   }
8842 
8843   // Parse the offset
8844   if (Parser.getTok().isNot(AsmToken::Hash) &&
8845       Parser.getTok().isNot(AsmToken::Dollar)) {
8846     Error(Parser.getTok().getLoc(), "'#' expected");
8847     return false;
8848   }
8849   Parser.Lex(); // skip hash token.
8850 
8851   const MCExpr *OffsetExpr;
8852   SMLoc ExLoc = Parser.getTok().getLoc();
8853   SMLoc EndLoc;
8854   if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8855     Error(ExLoc, "malformed pad offset");
8856     return false;
8857   }
8858   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8859   if (!CE) {
8860     Error(ExLoc, "pad offset must be an immediate");
8861     return false;
8862   }
8863 
8864   getTargetStreamer().emitPad(CE->getValue());
8865   return false;
8866 }
8867 
8868 /// parseDirectiveRegSave
8869 ///  ::= .save  { registers }
8870 ///  ::= .vsave { registers }
8871 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8872   // Check the ordering of unwind directives
8873   if (!UC.hasFnStart()) {
8874     Error(L, ".fnstart must precede .save or .vsave directives");
8875     return false;
8876   }
8877   if (UC.hasHandlerData()) {
8878     Error(L, ".save or .vsave must precede .handlerdata directive");
8879     return false;
8880   }
8881 
8882   // RAII object to make sure parsed operands are deleted.
8883   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
8884 
8885   // Parse the register list
8886   if (parseRegisterList(Operands))
8887     return false;
8888   ARMOperand &Op = (ARMOperand &)*Operands[0];
8889   if (!IsVector && !Op.isRegList()) {
8890     Error(L, ".save expects GPR registers");
8891     return false;
8892   }
8893   if (IsVector && !Op.isDPRRegList()) {
8894     Error(L, ".vsave expects DPR registers");
8895     return false;
8896   }
8897 
8898   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
8899   return false;
8900 }
8901 
8902 /// parseDirectiveInst
8903 ///  ::= .inst opcode [, ...]
8904 ///  ::= .inst.n opcode [, ...]
8905 ///  ::= .inst.w opcode [, ...]
8906 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8907   int Width;
8908 
8909   if (isThumb()) {
8910     switch (Suffix) {
8911     case 'n':
8912       Width = 2;
8913       break;
8914     case 'w':
8915       Width = 4;
8916       break;
8917     default:
8918       Parser.eatToEndOfStatement();
8919       Error(Loc, "cannot determine Thumb instruction size, "
8920                  "use inst.n/inst.w instead");
8921       return false;
8922     }
8923   } else {
8924     if (Suffix) {
8925       Parser.eatToEndOfStatement();
8926       Error(Loc, "width suffixes are invalid in ARM mode");
8927       return false;
8928     }
8929     Width = 4;
8930   }
8931 
8932   if (getLexer().is(AsmToken::EndOfStatement)) {
8933     Parser.eatToEndOfStatement();
8934     Error(Loc, "expected expression following directive");
8935     return false;
8936   }
8937 
8938   for (;;) {
8939     const MCExpr *Expr;
8940 
8941     if (getParser().parseExpression(Expr)) {
8942       Error(Loc, "expected expression");
8943       return false;
8944     }
8945 
8946     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8947     if (!Value) {
8948       Error(Loc, "expected constant expression");
8949       return false;
8950     }
8951 
8952     switch (Width) {
8953     case 2:
8954       if (Value->getValue() > 0xffff) {
8955         Error(Loc, "inst.n operand is too big, use inst.w instead");
8956         return false;
8957       }
8958       break;
8959     case 4:
8960       if (Value->getValue() > 0xffffffff) {
8961         Error(Loc,
8962               StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8963         return false;
8964       }
8965       break;
8966     default:
8967       llvm_unreachable("only supported widths are 2 and 4");
8968     }
8969 
8970     getTargetStreamer().emitInst(Value->getValue(), Suffix);
8971 
8972     if (getLexer().is(AsmToken::EndOfStatement))
8973       break;
8974 
8975     if (getLexer().isNot(AsmToken::Comma)) {
8976       Error(Loc, "unexpected token in directive");
8977       return false;
8978     }
8979 
8980     Parser.Lex();
8981   }
8982 
8983   Parser.Lex();
8984   return false;
8985 }
8986 
8987 /// parseDirectiveLtorg
8988 ///  ::= .ltorg | .pool
8989 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
8990   getTargetStreamer().emitCurrentConstantPool();
8991   return false;
8992 }
8993 
8994 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
8995   const MCSection *Section = getStreamer().getCurrentSection().first;
8996 
8997   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8998     TokError("unexpected token in directive");
8999     return false;
9000   }
9001 
9002   if (!Section) {
9003     getStreamer().InitSections();
9004     Section = getStreamer().getCurrentSection().first;
9005   }
9006 
9007   assert(Section && "must have section to emit alignment");
9008   if (Section->UseCodeAlign())
9009     getStreamer().EmitCodeAlignment(2);
9010   else
9011     getStreamer().EmitValueToAlignment(2);
9012 
9013   return false;
9014 }
9015 
9016 /// parseDirectivePersonalityIndex
9017 ///   ::= .personalityindex index
9018 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9019   bool HasExistingPersonality = UC.hasPersonality();
9020 
9021   UC.recordPersonalityIndex(L);
9022 
9023   if (!UC.hasFnStart()) {
9024     Parser.eatToEndOfStatement();
9025     Error(L, ".fnstart must precede .personalityindex directive");
9026     return false;
9027   }
9028   if (UC.cantUnwind()) {
9029     Parser.eatToEndOfStatement();
9030     Error(L, ".personalityindex cannot be used with .cantunwind");
9031     UC.emitCantUnwindLocNotes();
9032     return false;
9033   }
9034   if (UC.hasHandlerData()) {
9035     Parser.eatToEndOfStatement();
9036     Error(L, ".personalityindex must precede .handlerdata directive");
9037     UC.emitHandlerDataLocNotes();
9038     return false;
9039   }
9040   if (HasExistingPersonality) {
9041     Parser.eatToEndOfStatement();
9042     Error(L, "multiple personality directives");
9043     UC.emitPersonalityLocNotes();
9044     return false;
9045   }
9046 
9047   const MCExpr *IndexExpression;
9048   SMLoc IndexLoc = Parser.getTok().getLoc();
9049   if (Parser.parseExpression(IndexExpression)) {
9050     Parser.eatToEndOfStatement();
9051     return false;
9052   }
9053 
9054   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9055   if (!CE) {
9056     Parser.eatToEndOfStatement();
9057     Error(IndexLoc, "index must be a constant number");
9058     return false;
9059   }
9060   if (CE->getValue() < 0 ||
9061       CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9062     Parser.eatToEndOfStatement();
9063     Error(IndexLoc, "personality routine index should be in range [0-3]");
9064     return false;
9065   }
9066 
9067   getTargetStreamer().emitPersonalityIndex(CE->getValue());
9068   return false;
9069 }
9070 
9071 /// parseDirectiveUnwindRaw
9072 ///   ::= .unwind_raw offset, opcode [, opcode...]
9073 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9074   if (!UC.hasFnStart()) {
9075     Parser.eatToEndOfStatement();
9076     Error(L, ".fnstart must precede .unwind_raw directives");
9077     return false;
9078   }
9079 
9080   int64_t StackOffset;
9081 
9082   const MCExpr *OffsetExpr;
9083   SMLoc OffsetLoc = getLexer().getLoc();
9084   if (getLexer().is(AsmToken::EndOfStatement) ||
9085       getParser().parseExpression(OffsetExpr)) {
9086     Error(OffsetLoc, "expected expression");
9087     Parser.eatToEndOfStatement();
9088     return false;
9089   }
9090 
9091   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9092   if (!CE) {
9093     Error(OffsetLoc, "offset must be a constant");
9094     Parser.eatToEndOfStatement();
9095     return false;
9096   }
9097 
9098   StackOffset = CE->getValue();
9099 
9100   if (getLexer().isNot(AsmToken::Comma)) {
9101     Error(getLexer().getLoc(), "expected comma");
9102     Parser.eatToEndOfStatement();
9103     return false;
9104   }
9105   Parser.Lex();
9106 
9107   SmallVector<uint8_t, 16> Opcodes;
9108   for (;;) {
9109     const MCExpr *OE;
9110 
9111     SMLoc OpcodeLoc = getLexer().getLoc();
9112     if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9113       Error(OpcodeLoc, "expected opcode expression");
9114       Parser.eatToEndOfStatement();
9115       return false;
9116     }
9117 
9118     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9119     if (!OC) {
9120       Error(OpcodeLoc, "opcode value must be a constant");
9121       Parser.eatToEndOfStatement();
9122       return false;
9123     }
9124 
9125     const int64_t Opcode = OC->getValue();
9126     if (Opcode & ~0xff) {
9127       Error(OpcodeLoc, "invalid opcode");
9128       Parser.eatToEndOfStatement();
9129       return false;
9130     }
9131 
9132     Opcodes.push_back(uint8_t(Opcode));
9133 
9134     if (getLexer().is(AsmToken::EndOfStatement))
9135       break;
9136 
9137     if (getLexer().isNot(AsmToken::Comma)) {
9138       Error(getLexer().getLoc(), "unexpected token in directive");
9139       Parser.eatToEndOfStatement();
9140       return false;
9141     }
9142 
9143     Parser.Lex();
9144   }
9145 
9146   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9147 
9148   Parser.Lex();
9149   return false;
9150 }
9151 
9152 /// parseDirectiveTLSDescSeq
9153 ///   ::= .tlsdescseq tls-variable
9154 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9155   if (getLexer().isNot(AsmToken::Identifier)) {
9156     TokError("expected variable after '.tlsdescseq' directive");
9157     Parser.eatToEndOfStatement();
9158     return false;
9159   }
9160 
9161   const MCSymbolRefExpr *SRE =
9162     MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9163                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9164   Lex();
9165 
9166   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9167     Error(Parser.getTok().getLoc(), "unexpected token");
9168     Parser.eatToEndOfStatement();
9169     return false;
9170   }
9171 
9172   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9173   return false;
9174 }
9175 
9176 /// parseDirectiveMovSP
9177 ///  ::= .movsp reg [, #offset]
9178 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9179   if (!UC.hasFnStart()) {
9180     Parser.eatToEndOfStatement();
9181     Error(L, ".fnstart must precede .movsp directives");
9182     return false;
9183   }
9184   if (UC.getFPReg() != ARM::SP) {
9185     Parser.eatToEndOfStatement();
9186     Error(L, "unexpected .movsp directive");
9187     return false;
9188   }
9189 
9190   SMLoc SPRegLoc = Parser.getTok().getLoc();
9191   int SPReg = tryParseRegister();
9192   if (SPReg == -1) {
9193     Parser.eatToEndOfStatement();
9194     Error(SPRegLoc, "register expected");
9195     return false;
9196   }
9197 
9198   if (SPReg == ARM::SP || SPReg == ARM::PC) {
9199     Parser.eatToEndOfStatement();
9200     Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9201     return false;
9202   }
9203 
9204   int64_t Offset = 0;
9205   if (Parser.getTok().is(AsmToken::Comma)) {
9206     Parser.Lex();
9207 
9208     if (Parser.getTok().isNot(AsmToken::Hash)) {
9209       Error(Parser.getTok().getLoc(), "expected #constant");
9210       Parser.eatToEndOfStatement();
9211       return false;
9212     }
9213     Parser.Lex();
9214 
9215     const MCExpr *OffsetExpr;
9216     SMLoc OffsetLoc = Parser.getTok().getLoc();
9217     if (Parser.parseExpression(OffsetExpr)) {
9218       Parser.eatToEndOfStatement();
9219       Error(OffsetLoc, "malformed offset expression");
9220       return false;
9221     }
9222 
9223     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9224     if (!CE) {
9225       Parser.eatToEndOfStatement();
9226       Error(OffsetLoc, "offset must be an immediate constant");
9227       return false;
9228     }
9229 
9230     Offset = CE->getValue();
9231   }
9232 
9233   getTargetStreamer().emitMovSP(SPReg, Offset);
9234   UC.saveFPReg(SPReg);
9235 
9236   return false;
9237 }
9238 
9239 /// parseDirectiveObjectArch
9240 ///   ::= .object_arch name
9241 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9242   if (getLexer().isNot(AsmToken::Identifier)) {
9243     Error(getLexer().getLoc(), "unexpected token");
9244     Parser.eatToEndOfStatement();
9245     return false;
9246   }
9247 
9248   StringRef Arch = Parser.getTok().getString();
9249   SMLoc ArchLoc = Parser.getTok().getLoc();
9250   getLexer().Lex();
9251 
9252   unsigned ID = StringSwitch<unsigned>(Arch)
9253 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9254     .Case(NAME, ARM::ID)
9255 #define ARM_ARCH_ALIAS(NAME, ID) \
9256     .Case(NAME, ARM::ID)
9257 #include "MCTargetDesc/ARMArchName.def"
9258 #undef ARM_ARCH_NAME
9259 #undef ARM_ARCH_ALIAS
9260     .Default(ARM::INVALID_ARCH);
9261 
9262   if (ID == ARM::INVALID_ARCH) {
9263     Error(ArchLoc, "unknown architecture '" + Arch + "'");
9264     Parser.eatToEndOfStatement();
9265     return false;
9266   }
9267 
9268   getTargetStreamer().emitObjectArch(ID);
9269 
9270   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9271     Error(getLexer().getLoc(), "unexpected token");
9272     Parser.eatToEndOfStatement();
9273   }
9274 
9275   return false;
9276 }
9277 
9278 /// parseDirectiveAlign
9279 ///   ::= .align
9280 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9281   // NOTE: if this is not the end of the statement, fall back to the target
9282   // agnostic handling for this directive which will correctly handle this.
9283   if (getLexer().isNot(AsmToken::EndOfStatement))
9284     return true;
9285 
9286   // '.align' is target specifically handled to mean 2**2 byte alignment.
9287   if (getStreamer().getCurrentSection().first->UseCodeAlign())
9288     getStreamer().EmitCodeAlignment(4, 0);
9289   else
9290     getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9291 
9292   return false;
9293 }
9294 
9295 /// parseDirectiveThumbSet
9296 ///  ::= .thumb_set name, value
9297 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9298   StringRef Name;
9299   if (Parser.parseIdentifier(Name)) {
9300     TokError("expected identifier after '.thumb_set'");
9301     Parser.eatToEndOfStatement();
9302     return false;
9303   }
9304 
9305   if (getLexer().isNot(AsmToken::Comma)) {
9306     TokError("expected comma after name '" + Name + "'");
9307     Parser.eatToEndOfStatement();
9308     return false;
9309   }
9310   Lex();
9311 
9312   const MCExpr *Value;
9313   if (Parser.parseExpression(Value)) {
9314     TokError("missing expression");
9315     Parser.eatToEndOfStatement();
9316     return false;
9317   }
9318 
9319   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9320     TokError("unexpected token");
9321     Parser.eatToEndOfStatement();
9322     return false;
9323   }
9324   Lex();
9325 
9326   MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9327   getTargetStreamer().emitThumbSet(Alias, Value);
9328   return false;
9329 }
9330 
9331 /// Force static initialization.
9332 extern "C" void LLVMInitializeARMAsmParser() {
9333   RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9334   RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9335   RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9336   RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9337 }
9338 
9339 #define GET_REGISTER_MATCHER
9340 #define GET_SUBTARGET_FEATURE_NAME
9341 #define GET_MATCHER_IMPLEMENTATION
9342 #include "ARMGenAsmMatcher.inc"
9343 
9344 static const struct ExtMapEntry {
9345   const char *Extension;
9346   const unsigned ArchCheck;
9347   const uint64_t Features;
9348 } Extensions[] = {
9349   { "crc", Feature_HasV8, ARM::FeatureCRC },
9350   { "crypto",  Feature_HasV8,
9351     ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9352   { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9353   { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9354     ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9355   // FIXME: iWMMXT not supported
9356   { "iwmmxt", Feature_None, 0 },
9357   // FIXME: iWMMXT2 not supported
9358   { "iwmmxt2", Feature_None, 0 },
9359   // FIXME: Maverick not supported
9360   { "maverick", Feature_None, 0 },
9361   { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9362   // FIXME: ARMv6-m OS Extensions feature not checked
9363   { "os", Feature_None, 0 },
9364   // FIXME: Also available in ARMv6-K
9365   { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9366   { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9367   // FIXME: Only available in A-class, isel not predicated
9368   { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9369   // FIXME: xscale not supported
9370   { "xscale", Feature_None, 0 },
9371 };
9372 
9373 /// parseDirectiveArchExtension
9374 ///   ::= .arch_extension [no]feature
9375 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9376   if (getLexer().isNot(AsmToken::Identifier)) {
9377     Error(getLexer().getLoc(), "unexpected token");
9378     Parser.eatToEndOfStatement();
9379     return false;
9380   }
9381 
9382   StringRef Extension = Parser.getTok().getString();
9383   SMLoc ExtLoc = Parser.getTok().getLoc();
9384   getLexer().Lex();
9385 
9386   bool EnableFeature = true;
9387   if (Extension.startswith_lower("no")) {
9388     EnableFeature = false;
9389     Extension = Extension.substr(2);
9390   }
9391 
9392   for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) {
9393     if (Extensions[EI].Extension != Extension)
9394       continue;
9395 
9396     unsigned FB = getAvailableFeatures();
9397     if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
9398       Error(ExtLoc, "architectural extension '" + Extension + "' is not "
9399             "allowed for the current base architecture");
9400       return false;
9401     }
9402 
9403     if (!Extensions[EI].Features)
9404       report_fatal_error("unsupported architectural extension: " + Extension);
9405 
9406     if (EnableFeature)
9407       FB |= ComputeAvailableFeatures(Extensions[EI].Features);
9408     else
9409       FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
9410 
9411     setAvailableFeatures(FB);
9412     return false;
9413   }
9414 
9415   Error(ExtLoc, "unknown architectural extension: " + Extension);
9416   Parser.eatToEndOfStatement();
9417   return false;
9418 }
9419 
9420 // Define this matcher function after the auto-generated include so we
9421 // have the match class enum definitions.
9422 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
9423                                                   unsigned Kind) {
9424   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
9425   // If the kind is a token for a literal immediate, check if our asm
9426   // operand matches. This is for InstAliases which have a fixed-value
9427   // immediate in the syntax.
9428   switch (Kind) {
9429   default: break;
9430   case MCK__35_0:
9431     if (Op.isImm())
9432       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
9433         if (CE->getValue() == 0)
9434           return Match_Success;
9435     break;
9436   case MCK_ARMSOImm:
9437     if (Op.isImm()) {
9438       const MCExpr *SOExpr = Op.getImm();
9439       int64_t Value;
9440       if (!SOExpr->EvaluateAsAbsolute(Value))
9441         return Match_Success;
9442       assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
9443              "expression value must be representable in 32 bits");
9444     }
9445     break;
9446   case MCK_GPRPair:
9447     if (Op.isReg() &&
9448         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
9449       return Match_Success;
9450     break;
9451   }
9452   return Match_InvalidOperand;
9453 }
9454