1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/MC/MCTargetAsmParser.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/OwningPtr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCParser/MCAsmLexer.h"
28 #include "llvm/MC/MCParser/MCAsmParser.h"
29 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/SourceMgr.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
38 
39 using namespace llvm;
40 
41 namespace {
42 
43 class ARMOperand;
44 
45 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
46 
47 class ARMAsmParser : public MCTargetAsmParser {
48   MCSubtargetInfo &STI;
49   MCAsmParser &Parser;
50   const MCRegisterInfo *MRI;
51 
52   // Unwind directives state
53   SMLoc FnStartLoc;
54   SMLoc CantUnwindLoc;
55   SMLoc PersonalityLoc;
56   SMLoc HandlerDataLoc;
57   int FPReg;
58   void resetUnwindDirectiveParserState() {
59     FnStartLoc = SMLoc();
60     CantUnwindLoc = SMLoc();
61     PersonalityLoc = SMLoc();
62     HandlerDataLoc = SMLoc();
63     FPReg = -1;
64   }
65 
66   // Map of register aliases registers via the .req directive.
67   StringMap<unsigned> RegisterReqs;
68 
69   struct {
70     ARMCC::CondCodes Cond;    // Condition for IT block.
71     unsigned Mask:4;          // Condition mask for instructions.
72                               // Starting at first 1 (from lsb).
73                               //   '1'  condition as indicated in IT.
74                               //   '0'  inverse of condition (else).
75                               // Count of instructions in IT block is
76                               // 4 - trailingzeroes(mask)
77 
78     bool FirstCond;           // Explicit flag for when we're parsing the
79                               // First instruction in the IT block. It's
80                               // implied in the mask, so needs special
81                               // handling.
82 
83     unsigned CurPosition;     // Current position in parsing of IT
84                               // block. In range [0,3]. Initialized
85                               // according to count of instructions in block.
86                               // ~0U if no active IT block.
87   } ITState;
88   bool inITBlock() { return ITState.CurPosition != ~0U;}
89   void forwardITPosition() {
90     if (!inITBlock()) return;
91     // Move to the next instruction in the IT block, if there is one. If not,
92     // mark the block as done.
93     unsigned TZ = countTrailingZeros(ITState.Mask);
94     if (++ITState.CurPosition == 5 - TZ)
95       ITState.CurPosition = ~0U; // Done with the IT block after this.
96   }
97 
98 
99   MCAsmParser &getParser() const { return Parser; }
100   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101 
102   bool Warning(SMLoc L, const Twine &Msg,
103                ArrayRef<SMRange> Ranges = None) {
104     return Parser.Warning(L, Msg, Ranges);
105   }
106   bool Error(SMLoc L, const Twine &Msg,
107              ArrayRef<SMRange> Ranges = None) {
108     return Parser.Error(L, Msg, Ranges);
109   }
110 
111   int tryParseRegister();
112   bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
113   int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
114   bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
115   bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
116   bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
117   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
118   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
119                               unsigned &ShiftAmount);
120   bool parseDirectiveWord(unsigned Size, SMLoc L);
121   bool parseDirectiveThumb(SMLoc L);
122   bool parseDirectiveARM(SMLoc L);
123   bool parseDirectiveThumbFunc(SMLoc L);
124   bool parseDirectiveCode(SMLoc L);
125   bool parseDirectiveSyntax(SMLoc L);
126   bool parseDirectiveReq(StringRef Name, SMLoc L);
127   bool parseDirectiveUnreq(SMLoc L);
128   bool parseDirectiveArch(SMLoc L);
129   bool parseDirectiveEabiAttr(SMLoc L);
130   bool parseDirectiveFnStart(SMLoc L);
131   bool parseDirectiveFnEnd(SMLoc L);
132   bool parseDirectiveCantUnwind(SMLoc L);
133   bool parseDirectivePersonality(SMLoc L);
134   bool parseDirectiveHandlerData(SMLoc L);
135   bool parseDirectiveSetFP(SMLoc L);
136   bool parseDirectivePad(SMLoc L);
137   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
138 
139   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
140                           bool &CarrySetting, unsigned &ProcessorIMod,
141                           StringRef &ITMask);
142   void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
143                              bool &CanAcceptPredicationCode);
144 
145   bool isThumb() const {
146     // FIXME: Can tablegen auto-generate this?
147     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
148   }
149   bool isThumbOne() const {
150     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
151   }
152   bool isThumbTwo() const {
153     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
154   }
155   bool hasThumb() const {
156     return STI.getFeatureBits() & ARM::HasV4TOps;
157   }
158   bool hasV6Ops() const {
159     return STI.getFeatureBits() & ARM::HasV6Ops;
160   }
161   bool hasV7Ops() const {
162     return STI.getFeatureBits() & ARM::HasV7Ops;
163   }
164   bool hasV8Ops() const {
165     return STI.getFeatureBits() & ARM::HasV8Ops;
166   }
167   bool hasARM() const {
168     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
169   }
170 
171   void SwitchMode() {
172     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
173     setAvailableFeatures(FB);
174   }
175   bool isMClass() const {
176     return STI.getFeatureBits() & ARM::FeatureMClass;
177   }
178 
179   /// @name Auto-generated Match Functions
180   /// {
181 
182 #define GET_ASSEMBLER_HEADER
183 #include "ARMGenAsmMatcher.inc"
184 
185   /// }
186 
187   OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
188   OperandMatchResultTy parseCoprocNumOperand(
189     SmallVectorImpl<MCParsedAsmOperand*>&);
190   OperandMatchResultTy parseCoprocRegOperand(
191     SmallVectorImpl<MCParsedAsmOperand*>&);
192   OperandMatchResultTy parseCoprocOptionOperand(
193     SmallVectorImpl<MCParsedAsmOperand*>&);
194   OperandMatchResultTy parseMemBarrierOptOperand(
195     SmallVectorImpl<MCParsedAsmOperand*>&);
196   OperandMatchResultTy parseInstSyncBarrierOptOperand(
197     SmallVectorImpl<MCParsedAsmOperand*>&);
198   OperandMatchResultTy parseProcIFlagsOperand(
199     SmallVectorImpl<MCParsedAsmOperand*>&);
200   OperandMatchResultTy parseMSRMaskOperand(
201     SmallVectorImpl<MCParsedAsmOperand*>&);
202   OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
203                                    StringRef Op, int Low, int High);
204   OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
205     return parsePKHImm(O, "lsl", 0, 31);
206   }
207   OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
208     return parsePKHImm(O, "asr", 1, 32);
209   }
210   OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
211   OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
212   OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
213   OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
214   OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
215   OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
216   OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
217   OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
218   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
219                                        SMLoc &EndLoc);
220 
221   // Asm Match Converter Methods
222   void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
223   void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
224   void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
225                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
226   void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
227                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
228   void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
229                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
230   void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
231                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
232   void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
233                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
234   void cvtStWriteBackRegAddrMode2(MCInst &Inst,
235                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
236   void cvtStWriteBackRegAddrMode3(MCInst &Inst,
237                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
238   void cvtLdExtTWriteBackImm(MCInst &Inst,
239                              const SmallVectorImpl<MCParsedAsmOperand*> &);
240   void cvtLdExtTWriteBackReg(MCInst &Inst,
241                              const SmallVectorImpl<MCParsedAsmOperand*> &);
242   void cvtStExtTWriteBackImm(MCInst &Inst,
243                              const SmallVectorImpl<MCParsedAsmOperand*> &);
244   void cvtStExtTWriteBackReg(MCInst &Inst,
245                              const SmallVectorImpl<MCParsedAsmOperand*> &);
246   void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
247   void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
248   void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
249                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
250   void cvtThumbMultiply(MCInst &Inst,
251                         const SmallVectorImpl<MCParsedAsmOperand*> &);
252   void cvtVLDwbFixed(MCInst &Inst,
253                      const SmallVectorImpl<MCParsedAsmOperand*> &);
254   void cvtVLDwbRegister(MCInst &Inst,
255                         const SmallVectorImpl<MCParsedAsmOperand*> &);
256   void cvtVSTwbFixed(MCInst &Inst,
257                      const SmallVectorImpl<MCParsedAsmOperand*> &);
258   void cvtVSTwbRegister(MCInst &Inst,
259                         const SmallVectorImpl<MCParsedAsmOperand*> &);
260   bool validateInstruction(MCInst &Inst,
261                            const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
262   bool processInstruction(MCInst &Inst,
263                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
264   bool shouldOmitCCOutOperand(StringRef Mnemonic,
265                               SmallVectorImpl<MCParsedAsmOperand*> &Operands);
266 
267 public:
268   enum ARMMatchResultTy {
269     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
270     Match_RequiresNotITBlock,
271     Match_RequiresV6,
272     Match_RequiresThumb2,
273 #define GET_OPERAND_DIAGNOSTIC_TYPES
274 #include "ARMGenAsmMatcher.inc"
275 
276   };
277 
278   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
279     : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) {
280     MCAsmParserExtension::Initialize(_Parser);
281 
282     // Cache the MCRegisterInfo.
283     MRI = getContext().getRegisterInfo();
284 
285     // Initialize the set of available features.
286     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
287 
288     // Not in an ITBlock to start with.
289     ITState.CurPosition = ~0U;
290 
291     // Set ELF header flags.
292     // FIXME: This should eventually end up somewhere else where more
293     // intelligent flag decisions can be made. For now we are just maintaining
294     // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
295     if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
296       MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
297   }
298 
299   // Implementation of the MCTargetAsmParser interface:
300   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
301   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
302                         SMLoc NameLoc,
303                         SmallVectorImpl<MCParsedAsmOperand*> &Operands);
304   bool ParseDirective(AsmToken DirectiveID);
305 
306   unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
307   unsigned checkTargetMatchPredicate(MCInst &Inst);
308 
309   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
310                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
311                                MCStreamer &Out, unsigned &ErrorInfo,
312                                bool MatchingInlineAsm);
313 };
314 } // end anonymous namespace
315 
316 namespace {
317 
318 /// ARMOperand - Instances of this class represent a parsed ARM machine
319 /// operand.
320 class ARMOperand : public MCParsedAsmOperand {
321   enum KindTy {
322     k_CondCode,
323     k_CCOut,
324     k_ITCondMask,
325     k_CoprocNum,
326     k_CoprocReg,
327     k_CoprocOption,
328     k_Immediate,
329     k_MemBarrierOpt,
330     k_InstSyncBarrierOpt,
331     k_Memory,
332     k_PostIndexRegister,
333     k_MSRMask,
334     k_ProcIFlags,
335     k_VectorIndex,
336     k_Register,
337     k_RegisterList,
338     k_DPRRegisterList,
339     k_SPRRegisterList,
340     k_VectorList,
341     k_VectorListAllLanes,
342     k_VectorListIndexed,
343     k_ShiftedRegister,
344     k_ShiftedImmediate,
345     k_ShifterImmediate,
346     k_RotateImmediate,
347     k_BitfieldDescriptor,
348     k_Token
349   } Kind;
350 
351   SMLoc StartLoc, EndLoc;
352   SmallVector<unsigned, 8> Registers;
353 
354   struct CCOp {
355     ARMCC::CondCodes Val;
356   };
357 
358   struct CopOp {
359     unsigned Val;
360   };
361 
362   struct CoprocOptionOp {
363     unsigned Val;
364   };
365 
366   struct ITMaskOp {
367     unsigned Mask:4;
368   };
369 
370   struct MBOptOp {
371     ARM_MB::MemBOpt Val;
372   };
373 
374   struct ISBOptOp {
375     ARM_ISB::InstSyncBOpt Val;
376   };
377 
378   struct IFlagsOp {
379     ARM_PROC::IFlags Val;
380   };
381 
382   struct MMaskOp {
383     unsigned Val;
384   };
385 
386   struct TokOp {
387     const char *Data;
388     unsigned Length;
389   };
390 
391   struct RegOp {
392     unsigned RegNum;
393   };
394 
395   // A vector register list is a sequential list of 1 to 4 registers.
396   struct VectorListOp {
397     unsigned RegNum;
398     unsigned Count;
399     unsigned LaneIndex;
400     bool isDoubleSpaced;
401   };
402 
403   struct VectorIndexOp {
404     unsigned Val;
405   };
406 
407   struct ImmOp {
408     const MCExpr *Val;
409   };
410 
411   /// Combined record for all forms of ARM address expressions.
412   struct MemoryOp {
413     unsigned BaseRegNum;
414     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
415     // was specified.
416     const MCConstantExpr *OffsetImm;  // Offset immediate value
417     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
418     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
419     unsigned ShiftImm;        // shift for OffsetReg.
420     unsigned Alignment;       // 0 = no alignment specified
421     // n = alignment in bytes (2, 4, 8, 16, or 32)
422     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
423   };
424 
425   struct PostIdxRegOp {
426     unsigned RegNum;
427     bool isAdd;
428     ARM_AM::ShiftOpc ShiftTy;
429     unsigned ShiftImm;
430   };
431 
432   struct ShifterImmOp {
433     bool isASR;
434     unsigned Imm;
435   };
436 
437   struct RegShiftedRegOp {
438     ARM_AM::ShiftOpc ShiftTy;
439     unsigned SrcReg;
440     unsigned ShiftReg;
441     unsigned ShiftImm;
442   };
443 
444   struct RegShiftedImmOp {
445     ARM_AM::ShiftOpc ShiftTy;
446     unsigned SrcReg;
447     unsigned ShiftImm;
448   };
449 
450   struct RotImmOp {
451     unsigned Imm;
452   };
453 
454   struct BitfieldOp {
455     unsigned LSB;
456     unsigned Width;
457   };
458 
459   union {
460     struct CCOp CC;
461     struct CopOp Cop;
462     struct CoprocOptionOp CoprocOption;
463     struct MBOptOp MBOpt;
464     struct ISBOptOp ISBOpt;
465     struct ITMaskOp ITMask;
466     struct IFlagsOp IFlags;
467     struct MMaskOp MMask;
468     struct TokOp Tok;
469     struct RegOp Reg;
470     struct VectorListOp VectorList;
471     struct VectorIndexOp VectorIndex;
472     struct ImmOp Imm;
473     struct MemoryOp Memory;
474     struct PostIdxRegOp PostIdxReg;
475     struct ShifterImmOp ShifterImm;
476     struct RegShiftedRegOp RegShiftedReg;
477     struct RegShiftedImmOp RegShiftedImm;
478     struct RotImmOp RotImm;
479     struct BitfieldOp Bitfield;
480   };
481 
482   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
483 public:
484   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
485     Kind = o.Kind;
486     StartLoc = o.StartLoc;
487     EndLoc = o.EndLoc;
488     switch (Kind) {
489     case k_CondCode:
490       CC = o.CC;
491       break;
492     case k_ITCondMask:
493       ITMask = o.ITMask;
494       break;
495     case k_Token:
496       Tok = o.Tok;
497       break;
498     case k_CCOut:
499     case k_Register:
500       Reg = o.Reg;
501       break;
502     case k_RegisterList:
503     case k_DPRRegisterList:
504     case k_SPRRegisterList:
505       Registers = o.Registers;
506       break;
507     case k_VectorList:
508     case k_VectorListAllLanes:
509     case k_VectorListIndexed:
510       VectorList = o.VectorList;
511       break;
512     case k_CoprocNum:
513     case k_CoprocReg:
514       Cop = o.Cop;
515       break;
516     case k_CoprocOption:
517       CoprocOption = o.CoprocOption;
518       break;
519     case k_Immediate:
520       Imm = o.Imm;
521       break;
522     case k_MemBarrierOpt:
523       MBOpt = o.MBOpt;
524       break;
525     case k_InstSyncBarrierOpt:
526       ISBOpt = o.ISBOpt;
527     case k_Memory:
528       Memory = o.Memory;
529       break;
530     case k_PostIndexRegister:
531       PostIdxReg = o.PostIdxReg;
532       break;
533     case k_MSRMask:
534       MMask = o.MMask;
535       break;
536     case k_ProcIFlags:
537       IFlags = o.IFlags;
538       break;
539     case k_ShifterImmediate:
540       ShifterImm = o.ShifterImm;
541       break;
542     case k_ShiftedRegister:
543       RegShiftedReg = o.RegShiftedReg;
544       break;
545     case k_ShiftedImmediate:
546       RegShiftedImm = o.RegShiftedImm;
547       break;
548     case k_RotateImmediate:
549       RotImm = o.RotImm;
550       break;
551     case k_BitfieldDescriptor:
552       Bitfield = o.Bitfield;
553       break;
554     case k_VectorIndex:
555       VectorIndex = o.VectorIndex;
556       break;
557     }
558   }
559 
560   /// getStartLoc - Get the location of the first token of this operand.
561   SMLoc getStartLoc() const { return StartLoc; }
562   /// getEndLoc - Get the location of the last token of this operand.
563   SMLoc getEndLoc() const { return EndLoc; }
564   /// getLocRange - Get the range between the first and last token of this
565   /// operand.
566   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
567 
568   ARMCC::CondCodes getCondCode() const {
569     assert(Kind == k_CondCode && "Invalid access!");
570     return CC.Val;
571   }
572 
573   unsigned getCoproc() const {
574     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
575     return Cop.Val;
576   }
577 
578   StringRef getToken() const {
579     assert(Kind == k_Token && "Invalid access!");
580     return StringRef(Tok.Data, Tok.Length);
581   }
582 
583   unsigned getReg() const {
584     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
585     return Reg.RegNum;
586   }
587 
588   const SmallVectorImpl<unsigned> &getRegList() const {
589     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
590             Kind == k_SPRRegisterList) && "Invalid access!");
591     return Registers;
592   }
593 
594   const MCExpr *getImm() const {
595     assert(isImm() && "Invalid access!");
596     return Imm.Val;
597   }
598 
599   unsigned getVectorIndex() const {
600     assert(Kind == k_VectorIndex && "Invalid access!");
601     return VectorIndex.Val;
602   }
603 
604   ARM_MB::MemBOpt getMemBarrierOpt() const {
605     assert(Kind == k_MemBarrierOpt && "Invalid access!");
606     return MBOpt.Val;
607   }
608 
609   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
610     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
611     return ISBOpt.Val;
612   }
613 
614   ARM_PROC::IFlags getProcIFlags() const {
615     assert(Kind == k_ProcIFlags && "Invalid access!");
616     return IFlags.Val;
617   }
618 
619   unsigned getMSRMask() const {
620     assert(Kind == k_MSRMask && "Invalid access!");
621     return MMask.Val;
622   }
623 
624   bool isCoprocNum() const { return Kind == k_CoprocNum; }
625   bool isCoprocReg() const { return Kind == k_CoprocReg; }
626   bool isCoprocOption() const { return Kind == k_CoprocOption; }
627   bool isCondCode() const { return Kind == k_CondCode; }
628   bool isCCOut() const { return Kind == k_CCOut; }
629   bool isITMask() const { return Kind == k_ITCondMask; }
630   bool isITCondCode() const { return Kind == k_CondCode; }
631   bool isImm() const { return Kind == k_Immediate; }
632   // checks whether this operand is an unsigned offset which fits is a field
633   // of specified width and scaled by a specific number of bits
634   template<unsigned width, unsigned scale>
635   bool isUnsignedOffset() const {
636     if (!isImm()) return false;
637     if (dyn_cast<MCSymbolRefExpr>(Imm.Val)) return true;
638     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
639       int64_t Val = CE->getValue();
640       int64_t Align = 1LL << scale;
641       int64_t Max = Align * ((1LL << width) - 1);
642       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
643     }
644     return false;
645   }
646   bool isFPImm() const {
647     if (!isImm()) return false;
648     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
649     if (!CE) return false;
650     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
651     return Val != -1;
652   }
653   bool isFBits16() const {
654     if (!isImm()) return false;
655     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
656     if (!CE) return false;
657     int64_t Value = CE->getValue();
658     return Value >= 0 && Value <= 16;
659   }
660   bool isFBits32() const {
661     if (!isImm()) return false;
662     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
663     if (!CE) return false;
664     int64_t Value = CE->getValue();
665     return Value >= 1 && Value <= 32;
666   }
667   bool isImm8s4() const {
668     if (!isImm()) return false;
669     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
670     if (!CE) return false;
671     int64_t Value = CE->getValue();
672     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
673   }
674   bool isImm0_4() const {
675     if (!isImm()) return false;
676     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
677     if (!CE) return false;
678     int64_t Value = CE->getValue();
679     return Value >= 0 && Value < 5;
680   }
681   bool isImm0_1020s4() const {
682     if (!isImm()) return false;
683     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
684     if (!CE) return false;
685     int64_t Value = CE->getValue();
686     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
687   }
688   bool isImm0_508s4() const {
689     if (!isImm()) return false;
690     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
691     if (!CE) return false;
692     int64_t Value = CE->getValue();
693     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
694   }
695   bool isImm0_508s4Neg() const {
696     if (!isImm()) return false;
697     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
698     if (!CE) return false;
699     int64_t Value = -CE->getValue();
700     // explicitly exclude zero. we want that to use the normal 0_508 version.
701     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
702   }
703   bool isImm0_255() const {
704     if (!isImm()) return false;
705     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
706     if (!CE) return false;
707     int64_t Value = CE->getValue();
708     return Value >= 0 && Value < 256;
709   }
710   bool isImm0_4095() const {
711     if (!isImm()) return false;
712     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
713     if (!CE) return false;
714     int64_t Value = CE->getValue();
715     return Value >= 0 && Value < 4096;
716   }
717   bool isImm0_4095Neg() const {
718     if (!isImm()) return false;
719     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
720     if (!CE) return false;
721     int64_t Value = -CE->getValue();
722     return Value > 0 && Value < 4096;
723   }
724   bool isImm0_1() const {
725     if (!isImm()) return false;
726     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
727     if (!CE) return false;
728     int64_t Value = CE->getValue();
729     return Value >= 0 && Value < 2;
730   }
731   bool isImm0_3() const {
732     if (!isImm()) return false;
733     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734     if (!CE) return false;
735     int64_t Value = CE->getValue();
736     return Value >= 0 && Value < 4;
737   }
738   bool isImm0_7() const {
739     if (!isImm()) return false;
740     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
741     if (!CE) return false;
742     int64_t Value = CE->getValue();
743     return Value >= 0 && Value < 8;
744   }
745   bool isImm0_15() const {
746     if (!isImm()) return false;
747     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748     if (!CE) return false;
749     int64_t Value = CE->getValue();
750     return Value >= 0 && Value < 16;
751   }
752   bool isImm0_31() const {
753     if (!isImm()) return false;
754     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755     if (!CE) return false;
756     int64_t Value = CE->getValue();
757     return Value >= 0 && Value < 32;
758   }
759   bool isImm0_63() const {
760     if (!isImm()) return false;
761     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762     if (!CE) return false;
763     int64_t Value = CE->getValue();
764     return Value >= 0 && Value < 64;
765   }
766   bool isImm8() const {
767     if (!isImm()) return false;
768     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
769     if (!CE) return false;
770     int64_t Value = CE->getValue();
771     return Value == 8;
772   }
773   bool isImm16() const {
774     if (!isImm()) return false;
775     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776     if (!CE) return false;
777     int64_t Value = CE->getValue();
778     return Value == 16;
779   }
780   bool isImm32() const {
781     if (!isImm()) return false;
782     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783     if (!CE) return false;
784     int64_t Value = CE->getValue();
785     return Value == 32;
786   }
787   bool isShrImm8() const {
788     if (!isImm()) return false;
789     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790     if (!CE) return false;
791     int64_t Value = CE->getValue();
792     return Value > 0 && Value <= 8;
793   }
794   bool isShrImm16() const {
795     if (!isImm()) return false;
796     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797     if (!CE) return false;
798     int64_t Value = CE->getValue();
799     return Value > 0 && Value <= 16;
800   }
801   bool isShrImm32() const {
802     if (!isImm()) return false;
803     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804     if (!CE) return false;
805     int64_t Value = CE->getValue();
806     return Value > 0 && Value <= 32;
807   }
808   bool isShrImm64() const {
809     if (!isImm()) return false;
810     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
811     if (!CE) return false;
812     int64_t Value = CE->getValue();
813     return Value > 0 && Value <= 64;
814   }
815   bool isImm1_7() const {
816     if (!isImm()) return false;
817     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818     if (!CE) return false;
819     int64_t Value = CE->getValue();
820     return Value > 0 && Value < 8;
821   }
822   bool isImm1_15() const {
823     if (!isImm()) return false;
824     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825     if (!CE) return false;
826     int64_t Value = CE->getValue();
827     return Value > 0 && Value < 16;
828   }
829   bool isImm1_31() const {
830     if (!isImm()) return false;
831     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832     if (!CE) return false;
833     int64_t Value = CE->getValue();
834     return Value > 0 && Value < 32;
835   }
836   bool isImm1_16() const {
837     if (!isImm()) return false;
838     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839     if (!CE) return false;
840     int64_t Value = CE->getValue();
841     return Value > 0 && Value < 17;
842   }
843   bool isImm1_32() const {
844     if (!isImm()) return false;
845     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846     if (!CE) return false;
847     int64_t Value = CE->getValue();
848     return Value > 0 && Value < 33;
849   }
850   bool isImm0_32() const {
851     if (!isImm()) return false;
852     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853     if (!CE) return false;
854     int64_t Value = CE->getValue();
855     return Value >= 0 && Value < 33;
856   }
857   bool isImm0_65535() const {
858     if (!isImm()) return false;
859     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
860     if (!CE) return false;
861     int64_t Value = CE->getValue();
862     return Value >= 0 && Value < 65536;
863   }
864   bool isImm0_65535Expr() const {
865     if (!isImm()) return false;
866     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
867     // If it's not a constant expression, it'll generate a fixup and be
868     // handled later.
869     if (!CE) return true;
870     int64_t Value = CE->getValue();
871     return Value >= 0 && Value < 65536;
872   }
873   bool isImm24bit() const {
874     if (!isImm()) return false;
875     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876     if (!CE) return false;
877     int64_t Value = CE->getValue();
878     return Value >= 0 && Value <= 0xffffff;
879   }
880   bool isImmThumbSR() const {
881     if (!isImm()) return false;
882     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883     if (!CE) return false;
884     int64_t Value = CE->getValue();
885     return Value > 0 && Value < 33;
886   }
887   bool isPKHLSLImm() const {
888     if (!isImm()) return false;
889     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
890     if (!CE) return false;
891     int64_t Value = CE->getValue();
892     return Value >= 0 && Value < 32;
893   }
894   bool isPKHASRImm() const {
895     if (!isImm()) return false;
896     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897     if (!CE) return false;
898     int64_t Value = CE->getValue();
899     return Value > 0 && Value <= 32;
900   }
901   bool isAdrLabel() const {
902     // If we have an immediate that's not a constant, treat it as a label
903     // reference needing a fixup. If it is a constant, but it can't fit
904     // into shift immediate encoding, we reject it.
905     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
906     else return (isARMSOImm() || isARMSOImmNeg());
907   }
908   bool isARMSOImm() const {
909     if (!isImm()) return false;
910     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911     if (!CE) return false;
912     int64_t Value = CE->getValue();
913     return ARM_AM::getSOImmVal(Value) != -1;
914   }
915   bool isARMSOImmNot() const {
916     if (!isImm()) return false;
917     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918     if (!CE) return false;
919     int64_t Value = CE->getValue();
920     return ARM_AM::getSOImmVal(~Value) != -1;
921   }
922   bool isARMSOImmNeg() const {
923     if (!isImm()) return false;
924     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925     if (!CE) return false;
926     int64_t Value = CE->getValue();
927     // Only use this when not representable as a plain so_imm.
928     return ARM_AM::getSOImmVal(Value) == -1 &&
929       ARM_AM::getSOImmVal(-Value) != -1;
930   }
931   bool isT2SOImm() const {
932     if (!isImm()) return false;
933     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934     if (!CE) return false;
935     int64_t Value = CE->getValue();
936     return ARM_AM::getT2SOImmVal(Value) != -1;
937   }
938   bool isT2SOImmNot() const {
939     if (!isImm()) return false;
940     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941     if (!CE) return false;
942     int64_t Value = CE->getValue();
943     return ARM_AM::getT2SOImmVal(~Value) != -1;
944   }
945   bool isT2SOImmNeg() const {
946     if (!isImm()) return false;
947     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948     if (!CE) return false;
949     int64_t Value = CE->getValue();
950     // Only use this when not representable as a plain so_imm.
951     return ARM_AM::getT2SOImmVal(Value) == -1 &&
952       ARM_AM::getT2SOImmVal(-Value) != -1;
953   }
954   bool isSetEndImm() const {
955     if (!isImm()) return false;
956     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
957     if (!CE) return false;
958     int64_t Value = CE->getValue();
959     return Value == 1 || Value == 0;
960   }
961   bool isReg() const { return Kind == k_Register; }
962   bool isRegList() const { return Kind == k_RegisterList; }
963   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
964   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
965   bool isToken() const { return Kind == k_Token; }
966   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
967   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
968   bool isMem() const { return Kind == k_Memory; }
969   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
970   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
971   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
972   bool isRotImm() const { return Kind == k_RotateImmediate; }
973   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
974   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
975   bool isPostIdxReg() const {
976     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
977   }
978   bool isMemNoOffset(bool alignOK = false) const {
979     if (!isMem())
980       return false;
981     // No offset of any kind.
982     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
983      (alignOK || Memory.Alignment == 0);
984   }
985   bool isMemPCRelImm12() const {
986     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
987       return false;
988     // Base register must be PC.
989     if (Memory.BaseRegNum != ARM::PC)
990       return false;
991     // Immediate offset in range [-4095, 4095].
992     if (!Memory.OffsetImm) return true;
993     int64_t Val = Memory.OffsetImm->getValue();
994     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
995   }
996   bool isAlignedMemory() const {
997     return isMemNoOffset(true);
998   }
999   bool isAddrMode2() const {
1000     if (!isMem() || Memory.Alignment != 0) return false;
1001     // Check for register offset.
1002     if (Memory.OffsetRegNum) return true;
1003     // Immediate offset in range [-4095, 4095].
1004     if (!Memory.OffsetImm) return true;
1005     int64_t Val = Memory.OffsetImm->getValue();
1006     return Val > -4096 && Val < 4096;
1007   }
1008   bool isAM2OffsetImm() const {
1009     if (!isImm()) return false;
1010     // Immediate offset in range [-4095, 4095].
1011     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1012     if (!CE) return false;
1013     int64_t Val = CE->getValue();
1014     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1015   }
1016   bool isAddrMode3() const {
1017     // If we have an immediate that's not a constant, treat it as a label
1018     // reference needing a fixup. If it is a constant, it's something else
1019     // and we reject it.
1020     if (isImm() && !isa<MCConstantExpr>(getImm()))
1021       return true;
1022     if (!isMem() || Memory.Alignment != 0) return false;
1023     // No shifts are legal for AM3.
1024     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1025     // Check for register offset.
1026     if (Memory.OffsetRegNum) return true;
1027     // Immediate offset in range [-255, 255].
1028     if (!Memory.OffsetImm) return true;
1029     int64_t Val = Memory.OffsetImm->getValue();
1030     // The #-0 offset is encoded as INT32_MIN, and we have to check
1031     // for this too.
1032     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1033   }
1034   bool isAM3Offset() const {
1035     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1036       return false;
1037     if (Kind == k_PostIndexRegister)
1038       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1039     // Immediate offset in range [-255, 255].
1040     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041     if (!CE) return false;
1042     int64_t Val = CE->getValue();
1043     // Special case, #-0 is INT32_MIN.
1044     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1045   }
1046   bool isAddrMode5() const {
1047     // If we have an immediate that's not a constant, treat it as a label
1048     // reference needing a fixup. If it is a constant, it's something else
1049     // and we reject it.
1050     if (isImm() && !isa<MCConstantExpr>(getImm()))
1051       return true;
1052     if (!isMem() || Memory.Alignment != 0) return false;
1053     // Check for register offset.
1054     if (Memory.OffsetRegNum) return false;
1055     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1056     if (!Memory.OffsetImm) return true;
1057     int64_t Val = Memory.OffsetImm->getValue();
1058     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1059       Val == INT32_MIN;
1060   }
1061   bool isMemTBB() const {
1062     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1063         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1064       return false;
1065     return true;
1066   }
1067   bool isMemTBH() const {
1068     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1069         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1070         Memory.Alignment != 0 )
1071       return false;
1072     return true;
1073   }
1074   bool isMemRegOffset() const {
1075     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1076       return false;
1077     return true;
1078   }
1079   bool isT2MemRegOffset() const {
1080     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1081         Memory.Alignment != 0)
1082       return false;
1083     // Only lsl #{0, 1, 2, 3} allowed.
1084     if (Memory.ShiftType == ARM_AM::no_shift)
1085       return true;
1086     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1087       return false;
1088     return true;
1089   }
1090   bool isMemThumbRR() const {
1091     // Thumb reg+reg addressing is simple. Just two registers, a base and
1092     // an offset. No shifts, negations or any other complicating factors.
1093     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1094         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1095       return false;
1096     return isARMLowRegister(Memory.BaseRegNum) &&
1097       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1098   }
1099   bool isMemThumbRIs4() const {
1100     if (!isMem() || Memory.OffsetRegNum != 0 ||
1101         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1102       return false;
1103     // Immediate offset, multiple of 4 in range [0, 124].
1104     if (!Memory.OffsetImm) return true;
1105     int64_t Val = Memory.OffsetImm->getValue();
1106     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1107   }
1108   bool isMemThumbRIs2() const {
1109     if (!isMem() || Memory.OffsetRegNum != 0 ||
1110         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1111       return false;
1112     // Immediate offset, multiple of 4 in range [0, 62].
1113     if (!Memory.OffsetImm) return true;
1114     int64_t Val = Memory.OffsetImm->getValue();
1115     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1116   }
1117   bool isMemThumbRIs1() const {
1118     if (!isMem() || Memory.OffsetRegNum != 0 ||
1119         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1120       return false;
1121     // Immediate offset in range [0, 31].
1122     if (!Memory.OffsetImm) return true;
1123     int64_t Val = Memory.OffsetImm->getValue();
1124     return Val >= 0 && Val <= 31;
1125   }
1126   bool isMemThumbSPI() const {
1127     if (!isMem() || Memory.OffsetRegNum != 0 ||
1128         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1129       return false;
1130     // Immediate offset, multiple of 4 in range [0, 1020].
1131     if (!Memory.OffsetImm) return true;
1132     int64_t Val = Memory.OffsetImm->getValue();
1133     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1134   }
1135   bool isMemImm8s4Offset() const {
1136     // If we have an immediate that's not a constant, treat it as a label
1137     // reference needing a fixup. If it is a constant, it's something else
1138     // and we reject it.
1139     if (isImm() && !isa<MCConstantExpr>(getImm()))
1140       return true;
1141     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1142       return false;
1143     // Immediate offset a multiple of 4 in range [-1020, 1020].
1144     if (!Memory.OffsetImm) return true;
1145     int64_t Val = Memory.OffsetImm->getValue();
1146     // Special case, #-0 is INT32_MIN.
1147     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1148   }
1149   bool isMemImm0_1020s4Offset() const {
1150     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1151       return false;
1152     // Immediate offset a multiple of 4 in range [0, 1020].
1153     if (!Memory.OffsetImm) return true;
1154     int64_t Val = Memory.OffsetImm->getValue();
1155     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1156   }
1157   bool isMemImm8Offset() const {
1158     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1159       return false;
1160     // Base reg of PC isn't allowed for these encodings.
1161     if (Memory.BaseRegNum == ARM::PC) return false;
1162     // Immediate offset in range [-255, 255].
1163     if (!Memory.OffsetImm) return true;
1164     int64_t Val = Memory.OffsetImm->getValue();
1165     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1166   }
1167   bool isMemPosImm8Offset() const {
1168     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1169       return false;
1170     // Immediate offset in range [0, 255].
1171     if (!Memory.OffsetImm) return true;
1172     int64_t Val = Memory.OffsetImm->getValue();
1173     return Val >= 0 && Val < 256;
1174   }
1175   bool isMemNegImm8Offset() const {
1176     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1177       return false;
1178     // Base reg of PC isn't allowed for these encodings.
1179     if (Memory.BaseRegNum == ARM::PC) return false;
1180     // Immediate offset in range [-255, -1].
1181     if (!Memory.OffsetImm) return false;
1182     int64_t Val = Memory.OffsetImm->getValue();
1183     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1184   }
1185   bool isMemUImm12Offset() const {
1186     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1187       return false;
1188     // Immediate offset in range [0, 4095].
1189     if (!Memory.OffsetImm) return true;
1190     int64_t Val = Memory.OffsetImm->getValue();
1191     return (Val >= 0 && Val < 4096);
1192   }
1193   bool isMemImm12Offset() const {
1194     // If we have an immediate that's not a constant, treat it as a label
1195     // reference needing a fixup. If it is a constant, it's something else
1196     // and we reject it.
1197     if (isImm() && !isa<MCConstantExpr>(getImm()))
1198       return true;
1199 
1200     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1201       return false;
1202     // Immediate offset in range [-4095, 4095].
1203     if (!Memory.OffsetImm) return true;
1204     int64_t Val = Memory.OffsetImm->getValue();
1205     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1206   }
1207   bool isPostIdxImm8() const {
1208     if (!isImm()) return false;
1209     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1210     if (!CE) return false;
1211     int64_t Val = CE->getValue();
1212     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1213   }
1214   bool isPostIdxImm8s4() const {
1215     if (!isImm()) return false;
1216     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1217     if (!CE) return false;
1218     int64_t Val = CE->getValue();
1219     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1220       (Val == INT32_MIN);
1221   }
1222 
1223   bool isMSRMask() const { return Kind == k_MSRMask; }
1224   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1225 
1226   // NEON operands.
1227   bool isSingleSpacedVectorList() const {
1228     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1229   }
1230   bool isDoubleSpacedVectorList() const {
1231     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1232   }
1233   bool isVecListOneD() const {
1234     if (!isSingleSpacedVectorList()) return false;
1235     return VectorList.Count == 1;
1236   }
1237 
1238   bool isVecListDPair() const {
1239     if (!isSingleSpacedVectorList()) return false;
1240     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1241               .contains(VectorList.RegNum));
1242   }
1243 
1244   bool isVecListThreeD() const {
1245     if (!isSingleSpacedVectorList()) return false;
1246     return VectorList.Count == 3;
1247   }
1248 
1249   bool isVecListFourD() const {
1250     if (!isSingleSpacedVectorList()) return false;
1251     return VectorList.Count == 4;
1252   }
1253 
1254   bool isVecListDPairSpaced() const {
1255     if (isSingleSpacedVectorList()) return false;
1256     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1257               .contains(VectorList.RegNum));
1258   }
1259 
1260   bool isVecListThreeQ() const {
1261     if (!isDoubleSpacedVectorList()) return false;
1262     return VectorList.Count == 3;
1263   }
1264 
1265   bool isVecListFourQ() const {
1266     if (!isDoubleSpacedVectorList()) return false;
1267     return VectorList.Count == 4;
1268   }
1269 
1270   bool isSingleSpacedVectorAllLanes() const {
1271     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1272   }
1273   bool isDoubleSpacedVectorAllLanes() const {
1274     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1275   }
1276   bool isVecListOneDAllLanes() const {
1277     if (!isSingleSpacedVectorAllLanes()) return false;
1278     return VectorList.Count == 1;
1279   }
1280 
1281   bool isVecListDPairAllLanes() const {
1282     if (!isSingleSpacedVectorAllLanes()) return false;
1283     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1284               .contains(VectorList.RegNum));
1285   }
1286 
1287   bool isVecListDPairSpacedAllLanes() const {
1288     if (!isDoubleSpacedVectorAllLanes()) return false;
1289     return VectorList.Count == 2;
1290   }
1291 
1292   bool isVecListThreeDAllLanes() const {
1293     if (!isSingleSpacedVectorAllLanes()) return false;
1294     return VectorList.Count == 3;
1295   }
1296 
1297   bool isVecListThreeQAllLanes() const {
1298     if (!isDoubleSpacedVectorAllLanes()) return false;
1299     return VectorList.Count == 3;
1300   }
1301 
1302   bool isVecListFourDAllLanes() const {
1303     if (!isSingleSpacedVectorAllLanes()) return false;
1304     return VectorList.Count == 4;
1305   }
1306 
1307   bool isVecListFourQAllLanes() const {
1308     if (!isDoubleSpacedVectorAllLanes()) return false;
1309     return VectorList.Count == 4;
1310   }
1311 
1312   bool isSingleSpacedVectorIndexed() const {
1313     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1314   }
1315   bool isDoubleSpacedVectorIndexed() const {
1316     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1317   }
1318   bool isVecListOneDByteIndexed() const {
1319     if (!isSingleSpacedVectorIndexed()) return false;
1320     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1321   }
1322 
1323   bool isVecListOneDHWordIndexed() const {
1324     if (!isSingleSpacedVectorIndexed()) return false;
1325     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1326   }
1327 
1328   bool isVecListOneDWordIndexed() const {
1329     if (!isSingleSpacedVectorIndexed()) return false;
1330     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1331   }
1332 
1333   bool isVecListTwoDByteIndexed() const {
1334     if (!isSingleSpacedVectorIndexed()) return false;
1335     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1336   }
1337 
1338   bool isVecListTwoDHWordIndexed() const {
1339     if (!isSingleSpacedVectorIndexed()) return false;
1340     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1341   }
1342 
1343   bool isVecListTwoQWordIndexed() const {
1344     if (!isDoubleSpacedVectorIndexed()) return false;
1345     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1346   }
1347 
1348   bool isVecListTwoQHWordIndexed() const {
1349     if (!isDoubleSpacedVectorIndexed()) return false;
1350     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1351   }
1352 
1353   bool isVecListTwoDWordIndexed() const {
1354     if (!isSingleSpacedVectorIndexed()) return false;
1355     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1356   }
1357 
1358   bool isVecListThreeDByteIndexed() const {
1359     if (!isSingleSpacedVectorIndexed()) return false;
1360     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1361   }
1362 
1363   bool isVecListThreeDHWordIndexed() const {
1364     if (!isSingleSpacedVectorIndexed()) return false;
1365     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1366   }
1367 
1368   bool isVecListThreeQWordIndexed() const {
1369     if (!isDoubleSpacedVectorIndexed()) return false;
1370     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1371   }
1372 
1373   bool isVecListThreeQHWordIndexed() const {
1374     if (!isDoubleSpacedVectorIndexed()) return false;
1375     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1376   }
1377 
1378   bool isVecListThreeDWordIndexed() const {
1379     if (!isSingleSpacedVectorIndexed()) return false;
1380     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1381   }
1382 
1383   bool isVecListFourDByteIndexed() const {
1384     if (!isSingleSpacedVectorIndexed()) return false;
1385     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1386   }
1387 
1388   bool isVecListFourDHWordIndexed() const {
1389     if (!isSingleSpacedVectorIndexed()) return false;
1390     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1391   }
1392 
1393   bool isVecListFourQWordIndexed() const {
1394     if (!isDoubleSpacedVectorIndexed()) return false;
1395     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1396   }
1397 
1398   bool isVecListFourQHWordIndexed() const {
1399     if (!isDoubleSpacedVectorIndexed()) return false;
1400     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1401   }
1402 
1403   bool isVecListFourDWordIndexed() const {
1404     if (!isSingleSpacedVectorIndexed()) return false;
1405     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1406   }
1407 
1408   bool isVectorIndex8() const {
1409     if (Kind != k_VectorIndex) return false;
1410     return VectorIndex.Val < 8;
1411   }
1412   bool isVectorIndex16() const {
1413     if (Kind != k_VectorIndex) return false;
1414     return VectorIndex.Val < 4;
1415   }
1416   bool isVectorIndex32() const {
1417     if (Kind != k_VectorIndex) return false;
1418     return VectorIndex.Val < 2;
1419   }
1420 
1421   bool isNEONi8splat() const {
1422     if (!isImm()) return false;
1423     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1424     // Must be a constant.
1425     if (!CE) return false;
1426     int64_t Value = CE->getValue();
1427     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1428     // value.
1429     return Value >= 0 && Value < 256;
1430   }
1431 
1432   bool isNEONi16splat() const {
1433     if (!isImm()) return false;
1434     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1435     // Must be a constant.
1436     if (!CE) return false;
1437     int64_t Value = CE->getValue();
1438     // i16 value in the range [0,255] or [0x0100, 0xff00]
1439     return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1440   }
1441 
1442   bool isNEONi32splat() const {
1443     if (!isImm()) return false;
1444     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1445     // Must be a constant.
1446     if (!CE) return false;
1447     int64_t Value = CE->getValue();
1448     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1449     return (Value >= 0 && Value < 256) ||
1450       (Value >= 0x0100 && Value <= 0xff00) ||
1451       (Value >= 0x010000 && Value <= 0xff0000) ||
1452       (Value >= 0x01000000 && Value <= 0xff000000);
1453   }
1454 
1455   bool isNEONi32vmov() const {
1456     if (!isImm()) return false;
1457     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1458     // Must be a constant.
1459     if (!CE) return false;
1460     int64_t Value = CE->getValue();
1461     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1462     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1463     return (Value >= 0 && Value < 256) ||
1464       (Value >= 0x0100 && Value <= 0xff00) ||
1465       (Value >= 0x010000 && Value <= 0xff0000) ||
1466       (Value >= 0x01000000 && Value <= 0xff000000) ||
1467       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1468       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1469   }
1470   bool isNEONi32vmovNeg() const {
1471     if (!isImm()) return false;
1472     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1473     // Must be a constant.
1474     if (!CE) return false;
1475     int64_t Value = ~CE->getValue();
1476     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1477     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1478     return (Value >= 0 && Value < 256) ||
1479       (Value >= 0x0100 && Value <= 0xff00) ||
1480       (Value >= 0x010000 && Value <= 0xff0000) ||
1481       (Value >= 0x01000000 && Value <= 0xff000000) ||
1482       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1483       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1484   }
1485 
1486   bool isNEONi64splat() const {
1487     if (!isImm()) return false;
1488     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1489     // Must be a constant.
1490     if (!CE) return false;
1491     uint64_t Value = CE->getValue();
1492     // i64 value with each byte being either 0 or 0xff.
1493     for (unsigned i = 0; i < 8; ++i)
1494       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1495     return true;
1496   }
1497 
1498   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1499     // Add as immediates when possible.  Null MCExpr = 0.
1500     if (Expr == 0)
1501       Inst.addOperand(MCOperand::CreateImm(0));
1502     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1503       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1504     else
1505       Inst.addOperand(MCOperand::CreateExpr(Expr));
1506   }
1507 
1508   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1509     assert(N == 2 && "Invalid number of operands!");
1510     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1511     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1512     Inst.addOperand(MCOperand::CreateReg(RegNum));
1513   }
1514 
1515   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1516     assert(N == 1 && "Invalid number of operands!");
1517     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1518   }
1519 
1520   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1521     assert(N == 1 && "Invalid number of operands!");
1522     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1523   }
1524 
1525   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1526     assert(N == 1 && "Invalid number of operands!");
1527     Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1528   }
1529 
1530   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1531     assert(N == 1 && "Invalid number of operands!");
1532     Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1533   }
1534 
1535   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1536     assert(N == 1 && "Invalid number of operands!");
1537     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1538   }
1539 
1540   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1541     assert(N == 1 && "Invalid number of operands!");
1542     Inst.addOperand(MCOperand::CreateReg(getReg()));
1543   }
1544 
1545   void addRegOperands(MCInst &Inst, unsigned N) const {
1546     assert(N == 1 && "Invalid number of operands!");
1547     Inst.addOperand(MCOperand::CreateReg(getReg()));
1548   }
1549 
1550   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1551     assert(N == 3 && "Invalid number of operands!");
1552     assert(isRegShiftedReg() &&
1553            "addRegShiftedRegOperands() on non RegShiftedReg!");
1554     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1555     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1556     Inst.addOperand(MCOperand::CreateImm(
1557       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1558   }
1559 
1560   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1561     assert(N == 2 && "Invalid number of operands!");
1562     assert(isRegShiftedImm() &&
1563            "addRegShiftedImmOperands() on non RegShiftedImm!");
1564     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1565     // Shift of #32 is encoded as 0 where permitted
1566     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1567     Inst.addOperand(MCOperand::CreateImm(
1568       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1569   }
1570 
1571   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1572     assert(N == 1 && "Invalid number of operands!");
1573     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1574                                          ShifterImm.Imm));
1575   }
1576 
1577   void addRegListOperands(MCInst &Inst, unsigned N) const {
1578     assert(N == 1 && "Invalid number of operands!");
1579     const SmallVectorImpl<unsigned> &RegList = getRegList();
1580     for (SmallVectorImpl<unsigned>::const_iterator
1581            I = RegList.begin(), E = RegList.end(); I != E; ++I)
1582       Inst.addOperand(MCOperand::CreateReg(*I));
1583   }
1584 
1585   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1586     addRegListOperands(Inst, N);
1587   }
1588 
1589   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1590     addRegListOperands(Inst, N);
1591   }
1592 
1593   void addRotImmOperands(MCInst &Inst, unsigned N) const {
1594     assert(N == 1 && "Invalid number of operands!");
1595     // Encoded as val>>3. The printer handles display as 8, 16, 24.
1596     Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1597   }
1598 
1599   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1600     assert(N == 1 && "Invalid number of operands!");
1601     // Munge the lsb/width into a bitfield mask.
1602     unsigned lsb = Bitfield.LSB;
1603     unsigned width = Bitfield.Width;
1604     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1605     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1606                       (32 - (lsb + width)));
1607     Inst.addOperand(MCOperand::CreateImm(Mask));
1608   }
1609 
1610   void addImmOperands(MCInst &Inst, unsigned N) const {
1611     assert(N == 1 && "Invalid number of operands!");
1612     addExpr(Inst, getImm());
1613   }
1614 
1615   void addFBits16Operands(MCInst &Inst, unsigned N) const {
1616     assert(N == 1 && "Invalid number of operands!");
1617     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1619   }
1620 
1621   void addFBits32Operands(MCInst &Inst, unsigned N) const {
1622     assert(N == 1 && "Invalid number of operands!");
1623     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1624     Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1625   }
1626 
1627   void addFPImmOperands(MCInst &Inst, unsigned N) const {
1628     assert(N == 1 && "Invalid number of operands!");
1629     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1630     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1631     Inst.addOperand(MCOperand::CreateImm(Val));
1632   }
1633 
1634   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1635     assert(N == 1 && "Invalid number of operands!");
1636     // FIXME: We really want to scale the value here, but the LDRD/STRD
1637     // instruction don't encode operands that way yet.
1638     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1639     Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1640   }
1641 
1642   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1643     assert(N == 1 && "Invalid number of operands!");
1644     // The immediate is scaled by four in the encoding and is stored
1645     // in the MCInst as such. Lop off the low two bits here.
1646     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1647     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1648   }
1649 
1650   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1651     assert(N == 1 && "Invalid number of operands!");
1652     // The immediate is scaled by four in the encoding and is stored
1653     // in the MCInst as such. Lop off the low two bits here.
1654     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1655     Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1656   }
1657 
1658   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1659     assert(N == 1 && "Invalid number of operands!");
1660     // The immediate is scaled by four in the encoding and is stored
1661     // in the MCInst as such. Lop off the low two bits here.
1662     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1663     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1664   }
1665 
1666   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1667     assert(N == 1 && "Invalid number of operands!");
1668     // The constant encodes as the immediate-1, and we store in the instruction
1669     // the bits as encoded, so subtract off one here.
1670     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1671     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1672   }
1673 
1674   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1675     assert(N == 1 && "Invalid number of operands!");
1676     // The constant encodes as the immediate-1, and we store in the instruction
1677     // the bits as encoded, so subtract off one here.
1678     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1679     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1680   }
1681 
1682   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1683     assert(N == 1 && "Invalid number of operands!");
1684     // The constant encodes as the immediate, except for 32, which encodes as
1685     // zero.
1686     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1687     unsigned Imm = CE->getValue();
1688     Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1689   }
1690 
1691   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1692     assert(N == 1 && "Invalid number of operands!");
1693     // An ASR value of 32 encodes as 0, so that's how we want to add it to
1694     // the instruction as well.
1695     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1696     int Val = CE->getValue();
1697     Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1698   }
1699 
1700   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1701     assert(N == 1 && "Invalid number of operands!");
1702     // The operand is actually a t2_so_imm, but we have its bitwise
1703     // negation in the assembly source, so twiddle it here.
1704     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1705     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1706   }
1707 
1708   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1709     assert(N == 1 && "Invalid number of operands!");
1710     // The operand is actually a t2_so_imm, but we have its
1711     // negation in the assembly source, so twiddle it here.
1712     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1713     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1714   }
1715 
1716   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1717     assert(N == 1 && "Invalid number of operands!");
1718     // The operand is actually an imm0_4095, but we have its
1719     // negation in the assembly source, so twiddle it here.
1720     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1721     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1722   }
1723 
1724   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1725     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1726       Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1727       return;
1728     }
1729 
1730     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1731     assert(SR && "Unknown value type!");
1732     Inst.addOperand(MCOperand::CreateExpr(SR));
1733   }
1734 
1735   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1736     assert(N == 1 && "Invalid number of operands!");
1737     // The operand is actually a so_imm, but we have its bitwise
1738     // negation in the assembly source, so twiddle it here.
1739     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1740     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1741   }
1742 
1743   void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1744     assert(N == 1 && "Invalid number of operands!");
1745     // The operand is actually a so_imm, but we have its
1746     // negation in the assembly source, so twiddle it here.
1747     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1748     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1749   }
1750 
1751   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1752     assert(N == 1 && "Invalid number of operands!");
1753     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1754   }
1755 
1756   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1757     assert(N == 1 && "Invalid number of operands!");
1758     Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1759   }
1760 
1761   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1762     assert(N == 1 && "Invalid number of operands!");
1763     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1764   }
1765 
1766   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1767     assert(N == 1 && "Invalid number of operands!");
1768     int32_t Imm = Memory.OffsetImm->getValue();
1769     // FIXME: Handle #-0
1770     if (Imm == INT32_MIN) Imm = 0;
1771     Inst.addOperand(MCOperand::CreateImm(Imm));
1772   }
1773 
1774   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1775     assert(N == 1 && "Invalid number of operands!");
1776     assert(isImm() && "Not an immediate!");
1777 
1778     // If we have an immediate that's not a constant, treat it as a label
1779     // reference needing a fixup.
1780     if (!isa<MCConstantExpr>(getImm())) {
1781       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1782       return;
1783     }
1784 
1785     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1786     int Val = CE->getValue();
1787     Inst.addOperand(MCOperand::CreateImm(Val));
1788   }
1789 
1790   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1791     assert(N == 2 && "Invalid number of operands!");
1792     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1793     Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1794   }
1795 
1796   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1797     assert(N == 3 && "Invalid number of operands!");
1798     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1799     if (!Memory.OffsetRegNum) {
1800       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1801       // Special case for #-0
1802       if (Val == INT32_MIN) Val = 0;
1803       if (Val < 0) Val = -Val;
1804       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1805     } else {
1806       // For register offset, we encode the shift type and negation flag
1807       // here.
1808       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1809                               Memory.ShiftImm, Memory.ShiftType);
1810     }
1811     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1812     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1813     Inst.addOperand(MCOperand::CreateImm(Val));
1814   }
1815 
1816   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1817     assert(N == 2 && "Invalid number of operands!");
1818     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1819     assert(CE && "non-constant AM2OffsetImm operand!");
1820     int32_t Val = CE->getValue();
1821     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1822     // Special case for #-0
1823     if (Val == INT32_MIN) Val = 0;
1824     if (Val < 0) Val = -Val;
1825     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1826     Inst.addOperand(MCOperand::CreateReg(0));
1827     Inst.addOperand(MCOperand::CreateImm(Val));
1828   }
1829 
1830   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1831     assert(N == 3 && "Invalid number of operands!");
1832     // If we have an immediate that's not a constant, treat it as a label
1833     // reference needing a fixup. If it is a constant, it's something else
1834     // and we reject it.
1835     if (isImm()) {
1836       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1837       Inst.addOperand(MCOperand::CreateReg(0));
1838       Inst.addOperand(MCOperand::CreateImm(0));
1839       return;
1840     }
1841 
1842     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1843     if (!Memory.OffsetRegNum) {
1844       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1845       // Special case for #-0
1846       if (Val == INT32_MIN) Val = 0;
1847       if (Val < 0) Val = -Val;
1848       Val = ARM_AM::getAM3Opc(AddSub, Val);
1849     } else {
1850       // For register offset, we encode the shift type and negation flag
1851       // here.
1852       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1853     }
1854     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1855     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1856     Inst.addOperand(MCOperand::CreateImm(Val));
1857   }
1858 
1859   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1860     assert(N == 2 && "Invalid number of operands!");
1861     if (Kind == k_PostIndexRegister) {
1862       int32_t Val =
1863         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1864       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1865       Inst.addOperand(MCOperand::CreateImm(Val));
1866       return;
1867     }
1868 
1869     // Constant offset.
1870     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1871     int32_t Val = CE->getValue();
1872     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1873     // Special case for #-0
1874     if (Val == INT32_MIN) Val = 0;
1875     if (Val < 0) Val = -Val;
1876     Val = ARM_AM::getAM3Opc(AddSub, Val);
1877     Inst.addOperand(MCOperand::CreateReg(0));
1878     Inst.addOperand(MCOperand::CreateImm(Val));
1879   }
1880 
1881   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1882     assert(N == 2 && "Invalid number of operands!");
1883     // If we have an immediate that's not a constant, treat it as a label
1884     // reference needing a fixup. If it is a constant, it's something else
1885     // and we reject it.
1886     if (isImm()) {
1887       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1888       Inst.addOperand(MCOperand::CreateImm(0));
1889       return;
1890     }
1891 
1892     // The lower two bits are always zero and as such are not encoded.
1893     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1894     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1895     // Special case for #-0
1896     if (Val == INT32_MIN) Val = 0;
1897     if (Val < 0) Val = -Val;
1898     Val = ARM_AM::getAM5Opc(AddSub, Val);
1899     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1900     Inst.addOperand(MCOperand::CreateImm(Val));
1901   }
1902 
1903   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1904     assert(N == 2 && "Invalid number of operands!");
1905     // If we have an immediate that's not a constant, treat it as a label
1906     // reference needing a fixup. If it is a constant, it's something else
1907     // and we reject it.
1908     if (isImm()) {
1909       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1910       Inst.addOperand(MCOperand::CreateImm(0));
1911       return;
1912     }
1913 
1914     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1915     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1916     Inst.addOperand(MCOperand::CreateImm(Val));
1917   }
1918 
1919   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1920     assert(N == 2 && "Invalid number of operands!");
1921     // The lower two bits are always zero and as such are not encoded.
1922     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1923     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1924     Inst.addOperand(MCOperand::CreateImm(Val));
1925   }
1926 
1927   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1928     assert(N == 2 && "Invalid number of operands!");
1929     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1930     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1931     Inst.addOperand(MCOperand::CreateImm(Val));
1932   }
1933 
1934   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1935     addMemImm8OffsetOperands(Inst, N);
1936   }
1937 
1938   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1939     addMemImm8OffsetOperands(Inst, N);
1940   }
1941 
1942   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1943     assert(N == 2 && "Invalid number of operands!");
1944     // If this is an immediate, it's a label reference.
1945     if (isImm()) {
1946       addExpr(Inst, getImm());
1947       Inst.addOperand(MCOperand::CreateImm(0));
1948       return;
1949     }
1950 
1951     // Otherwise, it's a normal memory reg+offset.
1952     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1953     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1954     Inst.addOperand(MCOperand::CreateImm(Val));
1955   }
1956 
1957   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1958     assert(N == 2 && "Invalid number of operands!");
1959     // If this is an immediate, it's a label reference.
1960     if (isImm()) {
1961       addExpr(Inst, getImm());
1962       Inst.addOperand(MCOperand::CreateImm(0));
1963       return;
1964     }
1965 
1966     // Otherwise, it's a normal memory reg+offset.
1967     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1968     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1969     Inst.addOperand(MCOperand::CreateImm(Val));
1970   }
1971 
1972   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1973     assert(N == 2 && "Invalid number of operands!");
1974     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1975     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1976   }
1977 
1978   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1979     assert(N == 2 && "Invalid number of operands!");
1980     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1981     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1982   }
1983 
1984   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1985     assert(N == 3 && "Invalid number of operands!");
1986     unsigned Val =
1987       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1988                         Memory.ShiftImm, Memory.ShiftType);
1989     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1990     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1991     Inst.addOperand(MCOperand::CreateImm(Val));
1992   }
1993 
1994   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1995     assert(N == 3 && "Invalid number of operands!");
1996     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1997     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1998     Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1999   }
2000 
2001   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2002     assert(N == 2 && "Invalid number of operands!");
2003     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2004     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2005   }
2006 
2007   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2008     assert(N == 2 && "Invalid number of operands!");
2009     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2010     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2011     Inst.addOperand(MCOperand::CreateImm(Val));
2012   }
2013 
2014   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2015     assert(N == 2 && "Invalid number of operands!");
2016     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2017     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2018     Inst.addOperand(MCOperand::CreateImm(Val));
2019   }
2020 
2021   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2022     assert(N == 2 && "Invalid number of operands!");
2023     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2024     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2025     Inst.addOperand(MCOperand::CreateImm(Val));
2026   }
2027 
2028   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2029     assert(N == 2 && "Invalid number of operands!");
2030     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2031     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2032     Inst.addOperand(MCOperand::CreateImm(Val));
2033   }
2034 
2035   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2036     assert(N == 1 && "Invalid number of operands!");
2037     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2038     assert(CE && "non-constant post-idx-imm8 operand!");
2039     int Imm = CE->getValue();
2040     bool isAdd = Imm >= 0;
2041     if (Imm == INT32_MIN) Imm = 0;
2042     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2043     Inst.addOperand(MCOperand::CreateImm(Imm));
2044   }
2045 
2046   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2047     assert(N == 1 && "Invalid number of operands!");
2048     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2049     assert(CE && "non-constant post-idx-imm8s4 operand!");
2050     int Imm = CE->getValue();
2051     bool isAdd = Imm >= 0;
2052     if (Imm == INT32_MIN) Imm = 0;
2053     // Immediate is scaled by 4.
2054     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2055     Inst.addOperand(MCOperand::CreateImm(Imm));
2056   }
2057 
2058   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2059     assert(N == 2 && "Invalid number of operands!");
2060     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2061     Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2062   }
2063 
2064   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2065     assert(N == 2 && "Invalid number of operands!");
2066     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2067     // The sign, shift type, and shift amount are encoded in a single operand
2068     // using the AM2 encoding helpers.
2069     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2070     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2071                                      PostIdxReg.ShiftTy);
2072     Inst.addOperand(MCOperand::CreateImm(Imm));
2073   }
2074 
2075   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2076     assert(N == 1 && "Invalid number of operands!");
2077     Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2078   }
2079 
2080   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2081     assert(N == 1 && "Invalid number of operands!");
2082     Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2083   }
2084 
2085   void addVecListOperands(MCInst &Inst, unsigned N) const {
2086     assert(N == 1 && "Invalid number of operands!");
2087     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2088   }
2089 
2090   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2091     assert(N == 2 && "Invalid number of operands!");
2092     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2093     Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2094   }
2095 
2096   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2097     assert(N == 1 && "Invalid number of operands!");
2098     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2099   }
2100 
2101   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2102     assert(N == 1 && "Invalid number of operands!");
2103     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2104   }
2105 
2106   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2107     assert(N == 1 && "Invalid number of operands!");
2108     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2109   }
2110 
2111   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2112     assert(N == 1 && "Invalid number of operands!");
2113     // The immediate encodes the type of constant as well as the value.
2114     // Mask in that this is an i8 splat.
2115     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2116     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2117   }
2118 
2119   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2120     assert(N == 1 && "Invalid number of operands!");
2121     // The immediate encodes the type of constant as well as the value.
2122     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2123     unsigned Value = CE->getValue();
2124     if (Value >= 256)
2125       Value = (Value >> 8) | 0xa00;
2126     else
2127       Value |= 0x800;
2128     Inst.addOperand(MCOperand::CreateImm(Value));
2129   }
2130 
2131   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2132     assert(N == 1 && "Invalid number of operands!");
2133     // The immediate encodes the type of constant as well as the value.
2134     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2135     unsigned Value = CE->getValue();
2136     if (Value >= 256 && Value <= 0xff00)
2137       Value = (Value >> 8) | 0x200;
2138     else if (Value > 0xffff && Value <= 0xff0000)
2139       Value = (Value >> 16) | 0x400;
2140     else if (Value > 0xffffff)
2141       Value = (Value >> 24) | 0x600;
2142     Inst.addOperand(MCOperand::CreateImm(Value));
2143   }
2144 
2145   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2146     assert(N == 1 && "Invalid number of operands!");
2147     // The immediate encodes the type of constant as well as the value.
2148     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2149     unsigned Value = CE->getValue();
2150     if (Value >= 256 && Value <= 0xffff)
2151       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2152     else if (Value > 0xffff && Value <= 0xffffff)
2153       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2154     else if (Value > 0xffffff)
2155       Value = (Value >> 24) | 0x600;
2156     Inst.addOperand(MCOperand::CreateImm(Value));
2157   }
2158 
2159   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2160     assert(N == 1 && "Invalid number of operands!");
2161     // The immediate encodes the type of constant as well as the value.
2162     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2163     unsigned Value = ~CE->getValue();
2164     if (Value >= 256 && Value <= 0xffff)
2165       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2166     else if (Value > 0xffff && Value <= 0xffffff)
2167       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2168     else if (Value > 0xffffff)
2169       Value = (Value >> 24) | 0x600;
2170     Inst.addOperand(MCOperand::CreateImm(Value));
2171   }
2172 
2173   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2174     assert(N == 1 && "Invalid number of operands!");
2175     // The immediate encodes the type of constant as well as the value.
2176     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2177     uint64_t Value = CE->getValue();
2178     unsigned Imm = 0;
2179     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2180       Imm |= (Value & 1) << i;
2181     }
2182     Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2183   }
2184 
2185   virtual void print(raw_ostream &OS) const;
2186 
2187   static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2188     ARMOperand *Op = new ARMOperand(k_ITCondMask);
2189     Op->ITMask.Mask = Mask;
2190     Op->StartLoc = S;
2191     Op->EndLoc = S;
2192     return Op;
2193   }
2194 
2195   static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2196     ARMOperand *Op = new ARMOperand(k_CondCode);
2197     Op->CC.Val = CC;
2198     Op->StartLoc = S;
2199     Op->EndLoc = S;
2200     return Op;
2201   }
2202 
2203   static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2204     ARMOperand *Op = new ARMOperand(k_CoprocNum);
2205     Op->Cop.Val = CopVal;
2206     Op->StartLoc = S;
2207     Op->EndLoc = S;
2208     return Op;
2209   }
2210 
2211   static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2212     ARMOperand *Op = new ARMOperand(k_CoprocReg);
2213     Op->Cop.Val = CopVal;
2214     Op->StartLoc = S;
2215     Op->EndLoc = S;
2216     return Op;
2217   }
2218 
2219   static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2220     ARMOperand *Op = new ARMOperand(k_CoprocOption);
2221     Op->Cop.Val = Val;
2222     Op->StartLoc = S;
2223     Op->EndLoc = E;
2224     return Op;
2225   }
2226 
2227   static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2228     ARMOperand *Op = new ARMOperand(k_CCOut);
2229     Op->Reg.RegNum = RegNum;
2230     Op->StartLoc = S;
2231     Op->EndLoc = S;
2232     return Op;
2233   }
2234 
2235   static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2236     ARMOperand *Op = new ARMOperand(k_Token);
2237     Op->Tok.Data = Str.data();
2238     Op->Tok.Length = Str.size();
2239     Op->StartLoc = S;
2240     Op->EndLoc = S;
2241     return Op;
2242   }
2243 
2244   static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2245     ARMOperand *Op = new ARMOperand(k_Register);
2246     Op->Reg.RegNum = RegNum;
2247     Op->StartLoc = S;
2248     Op->EndLoc = E;
2249     return Op;
2250   }
2251 
2252   static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2253                                            unsigned SrcReg,
2254                                            unsigned ShiftReg,
2255                                            unsigned ShiftImm,
2256                                            SMLoc S, SMLoc E) {
2257     ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2258     Op->RegShiftedReg.ShiftTy = ShTy;
2259     Op->RegShiftedReg.SrcReg = SrcReg;
2260     Op->RegShiftedReg.ShiftReg = ShiftReg;
2261     Op->RegShiftedReg.ShiftImm = ShiftImm;
2262     Op->StartLoc = S;
2263     Op->EndLoc = E;
2264     return Op;
2265   }
2266 
2267   static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2268                                             unsigned SrcReg,
2269                                             unsigned ShiftImm,
2270                                             SMLoc S, SMLoc E) {
2271     ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2272     Op->RegShiftedImm.ShiftTy = ShTy;
2273     Op->RegShiftedImm.SrcReg = SrcReg;
2274     Op->RegShiftedImm.ShiftImm = ShiftImm;
2275     Op->StartLoc = S;
2276     Op->EndLoc = E;
2277     return Op;
2278   }
2279 
2280   static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2281                                    SMLoc S, SMLoc E) {
2282     ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2283     Op->ShifterImm.isASR = isASR;
2284     Op->ShifterImm.Imm = Imm;
2285     Op->StartLoc = S;
2286     Op->EndLoc = E;
2287     return Op;
2288   }
2289 
2290   static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2291     ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2292     Op->RotImm.Imm = Imm;
2293     Op->StartLoc = S;
2294     Op->EndLoc = E;
2295     return Op;
2296   }
2297 
2298   static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2299                                     SMLoc S, SMLoc E) {
2300     ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2301     Op->Bitfield.LSB = LSB;
2302     Op->Bitfield.Width = Width;
2303     Op->StartLoc = S;
2304     Op->EndLoc = E;
2305     return Op;
2306   }
2307 
2308   static ARMOperand *
2309   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2310                 SMLoc StartLoc, SMLoc EndLoc) {
2311     assert (Regs.size() > 0 && "RegList contains no registers?");
2312     KindTy Kind = k_RegisterList;
2313 
2314     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2315       Kind = k_DPRRegisterList;
2316     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2317              contains(Regs.front().second))
2318       Kind = k_SPRRegisterList;
2319 
2320     // Sort based on the register encoding values.
2321     array_pod_sort(Regs.begin(), Regs.end());
2322 
2323     ARMOperand *Op = new ARMOperand(Kind);
2324     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2325            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2326       Op->Registers.push_back(I->second);
2327     Op->StartLoc = StartLoc;
2328     Op->EndLoc = EndLoc;
2329     return Op;
2330   }
2331 
2332   static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2333                                       bool isDoubleSpaced, SMLoc S, SMLoc E) {
2334     ARMOperand *Op = new ARMOperand(k_VectorList);
2335     Op->VectorList.RegNum = RegNum;
2336     Op->VectorList.Count = Count;
2337     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2338     Op->StartLoc = S;
2339     Op->EndLoc = E;
2340     return Op;
2341   }
2342 
2343   static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2344                                               bool isDoubleSpaced,
2345                                               SMLoc S, SMLoc E) {
2346     ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2347     Op->VectorList.RegNum = RegNum;
2348     Op->VectorList.Count = Count;
2349     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2350     Op->StartLoc = S;
2351     Op->EndLoc = E;
2352     return Op;
2353   }
2354 
2355   static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2356                                              unsigned Index,
2357                                              bool isDoubleSpaced,
2358                                              SMLoc S, SMLoc E) {
2359     ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2360     Op->VectorList.RegNum = RegNum;
2361     Op->VectorList.Count = Count;
2362     Op->VectorList.LaneIndex = Index;
2363     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2364     Op->StartLoc = S;
2365     Op->EndLoc = E;
2366     return Op;
2367   }
2368 
2369   static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2370                                        MCContext &Ctx) {
2371     ARMOperand *Op = new ARMOperand(k_VectorIndex);
2372     Op->VectorIndex.Val = Idx;
2373     Op->StartLoc = S;
2374     Op->EndLoc = E;
2375     return Op;
2376   }
2377 
2378   static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2379     ARMOperand *Op = new ARMOperand(k_Immediate);
2380     Op->Imm.Val = Val;
2381     Op->StartLoc = S;
2382     Op->EndLoc = E;
2383     return Op;
2384   }
2385 
2386   static ARMOperand *CreateMem(unsigned BaseRegNum,
2387                                const MCConstantExpr *OffsetImm,
2388                                unsigned OffsetRegNum,
2389                                ARM_AM::ShiftOpc ShiftType,
2390                                unsigned ShiftImm,
2391                                unsigned Alignment,
2392                                bool isNegative,
2393                                SMLoc S, SMLoc E) {
2394     ARMOperand *Op = new ARMOperand(k_Memory);
2395     Op->Memory.BaseRegNum = BaseRegNum;
2396     Op->Memory.OffsetImm = OffsetImm;
2397     Op->Memory.OffsetRegNum = OffsetRegNum;
2398     Op->Memory.ShiftType = ShiftType;
2399     Op->Memory.ShiftImm = ShiftImm;
2400     Op->Memory.Alignment = Alignment;
2401     Op->Memory.isNegative = isNegative;
2402     Op->StartLoc = S;
2403     Op->EndLoc = E;
2404     return Op;
2405   }
2406 
2407   static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2408                                       ARM_AM::ShiftOpc ShiftTy,
2409                                       unsigned ShiftImm,
2410                                       SMLoc S, SMLoc E) {
2411     ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2412     Op->PostIdxReg.RegNum = RegNum;
2413     Op->PostIdxReg.isAdd = isAdd;
2414     Op->PostIdxReg.ShiftTy = ShiftTy;
2415     Op->PostIdxReg.ShiftImm = ShiftImm;
2416     Op->StartLoc = S;
2417     Op->EndLoc = E;
2418     return Op;
2419   }
2420 
2421   static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2422     ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2423     Op->MBOpt.Val = Opt;
2424     Op->StartLoc = S;
2425     Op->EndLoc = S;
2426     return Op;
2427   }
2428 
2429   static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2430                                               SMLoc S) {
2431     ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2432     Op->ISBOpt.Val = Opt;
2433     Op->StartLoc = S;
2434     Op->EndLoc = S;
2435     return Op;
2436   }
2437 
2438   static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2439     ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2440     Op->IFlags.Val = IFlags;
2441     Op->StartLoc = S;
2442     Op->EndLoc = S;
2443     return Op;
2444   }
2445 
2446   static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2447     ARMOperand *Op = new ARMOperand(k_MSRMask);
2448     Op->MMask.Val = MMask;
2449     Op->StartLoc = S;
2450     Op->EndLoc = S;
2451     return Op;
2452   }
2453 };
2454 
2455 } // end anonymous namespace.
2456 
2457 void ARMOperand::print(raw_ostream &OS) const {
2458   switch (Kind) {
2459   case k_CondCode:
2460     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2461     break;
2462   case k_CCOut:
2463     OS << "<ccout " << getReg() << ">";
2464     break;
2465   case k_ITCondMask: {
2466     static const char *const MaskStr[] = {
2467       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2468       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2469     };
2470     assert((ITMask.Mask & 0xf) == ITMask.Mask);
2471     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2472     break;
2473   }
2474   case k_CoprocNum:
2475     OS << "<coprocessor number: " << getCoproc() << ">";
2476     break;
2477   case k_CoprocReg:
2478     OS << "<coprocessor register: " << getCoproc() << ">";
2479     break;
2480   case k_CoprocOption:
2481     OS << "<coprocessor option: " << CoprocOption.Val << ">";
2482     break;
2483   case k_MSRMask:
2484     OS << "<mask: " << getMSRMask() << ">";
2485     break;
2486   case k_Immediate:
2487     getImm()->print(OS);
2488     break;
2489   case k_MemBarrierOpt:
2490     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2491     break;
2492   case k_InstSyncBarrierOpt:
2493     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2494     break;
2495   case k_Memory:
2496     OS << "<memory "
2497        << " base:" << Memory.BaseRegNum;
2498     OS << ">";
2499     break;
2500   case k_PostIndexRegister:
2501     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2502        << PostIdxReg.RegNum;
2503     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2504       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2505          << PostIdxReg.ShiftImm;
2506     OS << ">";
2507     break;
2508   case k_ProcIFlags: {
2509     OS << "<ARM_PROC::";
2510     unsigned IFlags = getProcIFlags();
2511     for (int i=2; i >= 0; --i)
2512       if (IFlags & (1 << i))
2513         OS << ARM_PROC::IFlagsToString(1 << i);
2514     OS << ">";
2515     break;
2516   }
2517   case k_Register:
2518     OS << "<register " << getReg() << ">";
2519     break;
2520   case k_ShifterImmediate:
2521     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2522        << " #" << ShifterImm.Imm << ">";
2523     break;
2524   case k_ShiftedRegister:
2525     OS << "<so_reg_reg "
2526        << RegShiftedReg.SrcReg << " "
2527        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2528        << " " << RegShiftedReg.ShiftReg << ">";
2529     break;
2530   case k_ShiftedImmediate:
2531     OS << "<so_reg_imm "
2532        << RegShiftedImm.SrcReg << " "
2533        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2534        << " #" << RegShiftedImm.ShiftImm << ">";
2535     break;
2536   case k_RotateImmediate:
2537     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2538     break;
2539   case k_BitfieldDescriptor:
2540     OS << "<bitfield " << "lsb: " << Bitfield.LSB
2541        << ", width: " << Bitfield.Width << ">";
2542     break;
2543   case k_RegisterList:
2544   case k_DPRRegisterList:
2545   case k_SPRRegisterList: {
2546     OS << "<register_list ";
2547 
2548     const SmallVectorImpl<unsigned> &RegList = getRegList();
2549     for (SmallVectorImpl<unsigned>::const_iterator
2550            I = RegList.begin(), E = RegList.end(); I != E; ) {
2551       OS << *I;
2552       if (++I < E) OS << ", ";
2553     }
2554 
2555     OS << ">";
2556     break;
2557   }
2558   case k_VectorList:
2559     OS << "<vector_list " << VectorList.Count << " * "
2560        << VectorList.RegNum << ">";
2561     break;
2562   case k_VectorListAllLanes:
2563     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2564        << VectorList.RegNum << ">";
2565     break;
2566   case k_VectorListIndexed:
2567     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2568        << VectorList.Count << " * " << VectorList.RegNum << ">";
2569     break;
2570   case k_Token:
2571     OS << "'" << getToken() << "'";
2572     break;
2573   case k_VectorIndex:
2574     OS << "<vectorindex " << getVectorIndex() << ">";
2575     break;
2576   }
2577 }
2578 
2579 /// @name Auto-generated Match Functions
2580 /// {
2581 
2582 static unsigned MatchRegisterName(StringRef Name);
2583 
2584 /// }
2585 
2586 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2587                                  SMLoc &StartLoc, SMLoc &EndLoc) {
2588   StartLoc = Parser.getTok().getLoc();
2589   EndLoc = Parser.getTok().getEndLoc();
2590   RegNo = tryParseRegister();
2591 
2592   return (RegNo == (unsigned)-1);
2593 }
2594 
2595 /// Try to parse a register name.  The token must be an Identifier when called,
2596 /// and if it is a register name the token is eaten and the register number is
2597 /// returned.  Otherwise return -1.
2598 ///
2599 int ARMAsmParser::tryParseRegister() {
2600   const AsmToken &Tok = Parser.getTok();
2601   if (Tok.isNot(AsmToken::Identifier)) return -1;
2602 
2603   std::string lowerCase = Tok.getString().lower();
2604   unsigned RegNum = MatchRegisterName(lowerCase);
2605   if (!RegNum) {
2606     RegNum = StringSwitch<unsigned>(lowerCase)
2607       .Case("r13", ARM::SP)
2608       .Case("r14", ARM::LR)
2609       .Case("r15", ARM::PC)
2610       .Case("ip", ARM::R12)
2611       // Additional register name aliases for 'gas' compatibility.
2612       .Case("a1", ARM::R0)
2613       .Case("a2", ARM::R1)
2614       .Case("a3", ARM::R2)
2615       .Case("a4", ARM::R3)
2616       .Case("v1", ARM::R4)
2617       .Case("v2", ARM::R5)
2618       .Case("v3", ARM::R6)
2619       .Case("v4", ARM::R7)
2620       .Case("v5", ARM::R8)
2621       .Case("v6", ARM::R9)
2622       .Case("v7", ARM::R10)
2623       .Case("v8", ARM::R11)
2624       .Case("sb", ARM::R9)
2625       .Case("sl", ARM::R10)
2626       .Case("fp", ARM::R11)
2627       .Default(0);
2628   }
2629   if (!RegNum) {
2630     // Check for aliases registered via .req. Canonicalize to lower case.
2631     // That's more consistent since register names are case insensitive, and
2632     // it's how the original entry was passed in from MC/MCParser/AsmParser.
2633     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2634     // If no match, return failure.
2635     if (Entry == RegisterReqs.end())
2636       return -1;
2637     Parser.Lex(); // Eat identifier token.
2638     return Entry->getValue();
2639   }
2640 
2641   Parser.Lex(); // Eat identifier token.
2642 
2643   return RegNum;
2644 }
2645 
2646 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2647 // If a recoverable error occurs, return 1. If an irrecoverable error
2648 // occurs, return -1. An irrecoverable error is one where tokens have been
2649 // consumed in the process of trying to parse the shifter (i.e., when it is
2650 // indeed a shifter operand, but malformed).
2651 int ARMAsmParser::tryParseShiftRegister(
2652                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2653   SMLoc S = Parser.getTok().getLoc();
2654   const AsmToken &Tok = Parser.getTok();
2655   assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2656 
2657   std::string lowerCase = Tok.getString().lower();
2658   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2659       .Case("asl", ARM_AM::lsl)
2660       .Case("lsl", ARM_AM::lsl)
2661       .Case("lsr", ARM_AM::lsr)
2662       .Case("asr", ARM_AM::asr)
2663       .Case("ror", ARM_AM::ror)
2664       .Case("rrx", ARM_AM::rrx)
2665       .Default(ARM_AM::no_shift);
2666 
2667   if (ShiftTy == ARM_AM::no_shift)
2668     return 1;
2669 
2670   Parser.Lex(); // Eat the operator.
2671 
2672   // The source register for the shift has already been added to the
2673   // operand list, so we need to pop it off and combine it into the shifted
2674   // register operand instead.
2675   OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2676   if (!PrevOp->isReg())
2677     return Error(PrevOp->getStartLoc(), "shift must be of a register");
2678   int SrcReg = PrevOp->getReg();
2679 
2680   SMLoc EndLoc;
2681   int64_t Imm = 0;
2682   int ShiftReg = 0;
2683   if (ShiftTy == ARM_AM::rrx) {
2684     // RRX Doesn't have an explicit shift amount. The encoder expects
2685     // the shift register to be the same as the source register. Seems odd,
2686     // but OK.
2687     ShiftReg = SrcReg;
2688   } else {
2689     // Figure out if this is shifted by a constant or a register (for non-RRX).
2690     if (Parser.getTok().is(AsmToken::Hash) ||
2691         Parser.getTok().is(AsmToken::Dollar)) {
2692       Parser.Lex(); // Eat hash.
2693       SMLoc ImmLoc = Parser.getTok().getLoc();
2694       const MCExpr *ShiftExpr = 0;
2695       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2696         Error(ImmLoc, "invalid immediate shift value");
2697         return -1;
2698       }
2699       // The expression must be evaluatable as an immediate.
2700       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2701       if (!CE) {
2702         Error(ImmLoc, "invalid immediate shift value");
2703         return -1;
2704       }
2705       // Range check the immediate.
2706       // lsl, ror: 0 <= imm <= 31
2707       // lsr, asr: 0 <= imm <= 32
2708       Imm = CE->getValue();
2709       if (Imm < 0 ||
2710           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2711           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2712         Error(ImmLoc, "immediate shift value out of range");
2713         return -1;
2714       }
2715       // shift by zero is a nop. Always send it through as lsl.
2716       // ('as' compatibility)
2717       if (Imm == 0)
2718         ShiftTy = ARM_AM::lsl;
2719     } else if (Parser.getTok().is(AsmToken::Identifier)) {
2720       SMLoc L = Parser.getTok().getLoc();
2721       EndLoc = Parser.getTok().getEndLoc();
2722       ShiftReg = tryParseRegister();
2723       if (ShiftReg == -1) {
2724         Error (L, "expected immediate or register in shift operand");
2725         return -1;
2726       }
2727     } else {
2728       Error (Parser.getTok().getLoc(),
2729                     "expected immediate or register in shift operand");
2730       return -1;
2731     }
2732   }
2733 
2734   if (ShiftReg && ShiftTy != ARM_AM::rrx)
2735     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2736                                                          ShiftReg, Imm,
2737                                                          S, EndLoc));
2738   else
2739     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2740                                                           S, EndLoc));
2741 
2742   return 0;
2743 }
2744 
2745 
2746 /// Try to parse a register name.  The token must be an Identifier when called.
2747 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2748 /// if there is a "writeback". 'true' if it's not a register.
2749 ///
2750 /// TODO this is likely to change to allow different register types and or to
2751 /// parse for a specific register type.
2752 bool ARMAsmParser::
2753 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2754   const AsmToken &RegTok = Parser.getTok();
2755   int RegNo = tryParseRegister();
2756   if (RegNo == -1)
2757     return true;
2758 
2759   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2760                                            RegTok.getEndLoc()));
2761 
2762   const AsmToken &ExclaimTok = Parser.getTok();
2763   if (ExclaimTok.is(AsmToken::Exclaim)) {
2764     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2765                                                ExclaimTok.getLoc()));
2766     Parser.Lex(); // Eat exclaim token
2767     return false;
2768   }
2769 
2770   // Also check for an index operand. This is only legal for vector registers,
2771   // but that'll get caught OK in operand matching, so we don't need to
2772   // explicitly filter everything else out here.
2773   if (Parser.getTok().is(AsmToken::LBrac)) {
2774     SMLoc SIdx = Parser.getTok().getLoc();
2775     Parser.Lex(); // Eat left bracket token.
2776 
2777     const MCExpr *ImmVal;
2778     if (getParser().parseExpression(ImmVal))
2779       return true;
2780     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2781     if (!MCE)
2782       return TokError("immediate value expected for vector index");
2783 
2784     if (Parser.getTok().isNot(AsmToken::RBrac))
2785       return Error(Parser.getTok().getLoc(), "']' expected");
2786 
2787     SMLoc E = Parser.getTok().getEndLoc();
2788     Parser.Lex(); // Eat right bracket token.
2789 
2790     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2791                                                      SIdx, E,
2792                                                      getContext()));
2793   }
2794 
2795   return false;
2796 }
2797 
2798 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2799 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2800 /// "c5", ...
2801 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2802   // Use the same layout as the tablegen'erated register name matcher. Ugly,
2803   // but efficient.
2804   switch (Name.size()) {
2805   default: return -1;
2806   case 2:
2807     if (Name[0] != CoprocOp)
2808       return -1;
2809     switch (Name[1]) {
2810     default:  return -1;
2811     case '0': return 0;
2812     case '1': return 1;
2813     case '2': return 2;
2814     case '3': return 3;
2815     case '4': return 4;
2816     case '5': return 5;
2817     case '6': return 6;
2818     case '7': return 7;
2819     case '8': return 8;
2820     case '9': return 9;
2821     }
2822   case 3:
2823     if (Name[0] != CoprocOp || Name[1] != '1')
2824       return -1;
2825     switch (Name[2]) {
2826     default:  return -1;
2827     case '0': return 10;
2828     case '1': return 11;
2829     case '2': return 12;
2830     case '3': return 13;
2831     case '4': return 14;
2832     case '5': return 15;
2833     }
2834   }
2835 }
2836 
2837 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2838 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2839 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2840   SMLoc S = Parser.getTok().getLoc();
2841   const AsmToken &Tok = Parser.getTok();
2842   if (!Tok.is(AsmToken::Identifier))
2843     return MatchOperand_NoMatch;
2844   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2845     .Case("eq", ARMCC::EQ)
2846     .Case("ne", ARMCC::NE)
2847     .Case("hs", ARMCC::HS)
2848     .Case("cs", ARMCC::HS)
2849     .Case("lo", ARMCC::LO)
2850     .Case("cc", ARMCC::LO)
2851     .Case("mi", ARMCC::MI)
2852     .Case("pl", ARMCC::PL)
2853     .Case("vs", ARMCC::VS)
2854     .Case("vc", ARMCC::VC)
2855     .Case("hi", ARMCC::HI)
2856     .Case("ls", ARMCC::LS)
2857     .Case("ge", ARMCC::GE)
2858     .Case("lt", ARMCC::LT)
2859     .Case("gt", ARMCC::GT)
2860     .Case("le", ARMCC::LE)
2861     .Case("al", ARMCC::AL)
2862     .Default(~0U);
2863   if (CC == ~0U)
2864     return MatchOperand_NoMatch;
2865   Parser.Lex(); // Eat the token.
2866 
2867   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2868 
2869   return MatchOperand_Success;
2870 }
2871 
2872 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2873 /// token must be an Identifier when called, and if it is a coprocessor
2874 /// number, the token is eaten and the operand is added to the operand list.
2875 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2876 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2877   SMLoc S = Parser.getTok().getLoc();
2878   const AsmToken &Tok = Parser.getTok();
2879   if (Tok.isNot(AsmToken::Identifier))
2880     return MatchOperand_NoMatch;
2881 
2882   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2883   if (Num == -1)
2884     return MatchOperand_NoMatch;
2885 
2886   Parser.Lex(); // Eat identifier token.
2887   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2888   return MatchOperand_Success;
2889 }
2890 
2891 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2892 /// token must be an Identifier when called, and if it is a coprocessor
2893 /// number, the token is eaten and the operand is added to the operand list.
2894 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2895 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2896   SMLoc S = Parser.getTok().getLoc();
2897   const AsmToken &Tok = Parser.getTok();
2898   if (Tok.isNot(AsmToken::Identifier))
2899     return MatchOperand_NoMatch;
2900 
2901   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2902   if (Reg == -1)
2903     return MatchOperand_NoMatch;
2904 
2905   Parser.Lex(); // Eat identifier token.
2906   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2907   return MatchOperand_Success;
2908 }
2909 
2910 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2911 /// coproc_option : '{' imm0_255 '}'
2912 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2913 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2914   SMLoc S = Parser.getTok().getLoc();
2915 
2916   // If this isn't a '{', this isn't a coprocessor immediate operand.
2917   if (Parser.getTok().isNot(AsmToken::LCurly))
2918     return MatchOperand_NoMatch;
2919   Parser.Lex(); // Eat the '{'
2920 
2921   const MCExpr *Expr;
2922   SMLoc Loc = Parser.getTok().getLoc();
2923   if (getParser().parseExpression(Expr)) {
2924     Error(Loc, "illegal expression");
2925     return MatchOperand_ParseFail;
2926   }
2927   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2928   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2929     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2930     return MatchOperand_ParseFail;
2931   }
2932   int Val = CE->getValue();
2933 
2934   // Check for and consume the closing '}'
2935   if (Parser.getTok().isNot(AsmToken::RCurly))
2936     return MatchOperand_ParseFail;
2937   SMLoc E = Parser.getTok().getEndLoc();
2938   Parser.Lex(); // Eat the '}'
2939 
2940   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2941   return MatchOperand_Success;
2942 }
2943 
2944 // For register list parsing, we need to map from raw GPR register numbering
2945 // to the enumeration values. The enumeration values aren't sorted by
2946 // register number due to our using "sp", "lr" and "pc" as canonical names.
2947 static unsigned getNextRegister(unsigned Reg) {
2948   // If this is a GPR, we need to do it manually, otherwise we can rely
2949   // on the sort ordering of the enumeration since the other reg-classes
2950   // are sane.
2951   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2952     return Reg + 1;
2953   switch(Reg) {
2954   default: llvm_unreachable("Invalid GPR number!");
2955   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2956   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2957   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2958   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2959   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2960   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2961   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2962   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2963   }
2964 }
2965 
2966 // Return the low-subreg of a given Q register.
2967 static unsigned getDRegFromQReg(unsigned QReg) {
2968   switch (QReg) {
2969   default: llvm_unreachable("expected a Q register!");
2970   case ARM::Q0:  return ARM::D0;
2971   case ARM::Q1:  return ARM::D2;
2972   case ARM::Q2:  return ARM::D4;
2973   case ARM::Q3:  return ARM::D6;
2974   case ARM::Q4:  return ARM::D8;
2975   case ARM::Q5:  return ARM::D10;
2976   case ARM::Q6:  return ARM::D12;
2977   case ARM::Q7:  return ARM::D14;
2978   case ARM::Q8:  return ARM::D16;
2979   case ARM::Q9:  return ARM::D18;
2980   case ARM::Q10: return ARM::D20;
2981   case ARM::Q11: return ARM::D22;
2982   case ARM::Q12: return ARM::D24;
2983   case ARM::Q13: return ARM::D26;
2984   case ARM::Q14: return ARM::D28;
2985   case ARM::Q15: return ARM::D30;
2986   }
2987 }
2988 
2989 /// Parse a register list.
2990 bool ARMAsmParser::
2991 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2992   assert(Parser.getTok().is(AsmToken::LCurly) &&
2993          "Token is not a Left Curly Brace");
2994   SMLoc S = Parser.getTok().getLoc();
2995   Parser.Lex(); // Eat '{' token.
2996   SMLoc RegLoc = Parser.getTok().getLoc();
2997 
2998   // Check the first register in the list to see what register class
2999   // this is a list of.
3000   int Reg = tryParseRegister();
3001   if (Reg == -1)
3002     return Error(RegLoc, "register expected");
3003 
3004   // The reglist instructions have at most 16 registers, so reserve
3005   // space for that many.
3006   int EReg = 0;
3007   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3008 
3009   // Allow Q regs and just interpret them as the two D sub-registers.
3010   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3011     Reg = getDRegFromQReg(Reg);
3012     EReg = MRI->getEncodingValue(Reg);
3013     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3014     ++Reg;
3015   }
3016   const MCRegisterClass *RC;
3017   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3018     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3019   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3020     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3021   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3022     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3023   else
3024     return Error(RegLoc, "invalid register in register list");
3025 
3026   // Store the register.
3027   EReg = MRI->getEncodingValue(Reg);
3028   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3029 
3030   // This starts immediately after the first register token in the list,
3031   // so we can see either a comma or a minus (range separator) as a legal
3032   // next token.
3033   while (Parser.getTok().is(AsmToken::Comma) ||
3034          Parser.getTok().is(AsmToken::Minus)) {
3035     if (Parser.getTok().is(AsmToken::Minus)) {
3036       Parser.Lex(); // Eat the minus.
3037       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3038       int EndReg = tryParseRegister();
3039       if (EndReg == -1)
3040         return Error(AfterMinusLoc, "register expected");
3041       // Allow Q regs and just interpret them as the two D sub-registers.
3042       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3043         EndReg = getDRegFromQReg(EndReg) + 1;
3044       // If the register is the same as the start reg, there's nothing
3045       // more to do.
3046       if (Reg == EndReg)
3047         continue;
3048       // The register must be in the same register class as the first.
3049       if (!RC->contains(EndReg))
3050         return Error(AfterMinusLoc, "invalid register in register list");
3051       // Ranges must go from low to high.
3052       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3053         return Error(AfterMinusLoc, "bad range in register list");
3054 
3055       // Add all the registers in the range to the register list.
3056       while (Reg != EndReg) {
3057         Reg = getNextRegister(Reg);
3058         EReg = MRI->getEncodingValue(Reg);
3059         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3060       }
3061       continue;
3062     }
3063     Parser.Lex(); // Eat the comma.
3064     RegLoc = Parser.getTok().getLoc();
3065     int OldReg = Reg;
3066     const AsmToken RegTok = Parser.getTok();
3067     Reg = tryParseRegister();
3068     if (Reg == -1)
3069       return Error(RegLoc, "register expected");
3070     // Allow Q regs and just interpret them as the two D sub-registers.
3071     bool isQReg = false;
3072     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3073       Reg = getDRegFromQReg(Reg);
3074       isQReg = true;
3075     }
3076     // The register must be in the same register class as the first.
3077     if (!RC->contains(Reg))
3078       return Error(RegLoc, "invalid register in register list");
3079     // List must be monotonically increasing.
3080     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3081       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3082         Warning(RegLoc, "register list not in ascending order");
3083       else
3084         return Error(RegLoc, "register list not in ascending order");
3085     }
3086     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3087       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3088               ") in register list");
3089       continue;
3090     }
3091     // VFP register lists must also be contiguous.
3092     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3093         Reg != OldReg + 1)
3094       return Error(RegLoc, "non-contiguous register range");
3095     EReg = MRI->getEncodingValue(Reg);
3096     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3097     if (isQReg) {
3098       EReg = MRI->getEncodingValue(++Reg);
3099       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3100     }
3101   }
3102 
3103   if (Parser.getTok().isNot(AsmToken::RCurly))
3104     return Error(Parser.getTok().getLoc(), "'}' expected");
3105   SMLoc E = Parser.getTok().getEndLoc();
3106   Parser.Lex(); // Eat '}' token.
3107 
3108   // Push the register list operand.
3109   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3110 
3111   // The ARM system instruction variants for LDM/STM have a '^' token here.
3112   if (Parser.getTok().is(AsmToken::Caret)) {
3113     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3114     Parser.Lex(); // Eat '^' token.
3115   }
3116 
3117   return false;
3118 }
3119 
3120 // Helper function to parse the lane index for vector lists.
3121 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3122 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3123   Index = 0; // Always return a defined index value.
3124   if (Parser.getTok().is(AsmToken::LBrac)) {
3125     Parser.Lex(); // Eat the '['.
3126     if (Parser.getTok().is(AsmToken::RBrac)) {
3127       // "Dn[]" is the 'all lanes' syntax.
3128       LaneKind = AllLanes;
3129       EndLoc = Parser.getTok().getEndLoc();
3130       Parser.Lex(); // Eat the ']'.
3131       return MatchOperand_Success;
3132     }
3133 
3134     // There's an optional '#' token here. Normally there wouldn't be, but
3135     // inline assemble puts one in, and it's friendly to accept that.
3136     if (Parser.getTok().is(AsmToken::Hash))
3137       Parser.Lex(); // Eat '#' or '$'.
3138 
3139     const MCExpr *LaneIndex;
3140     SMLoc Loc = Parser.getTok().getLoc();
3141     if (getParser().parseExpression(LaneIndex)) {
3142       Error(Loc, "illegal expression");
3143       return MatchOperand_ParseFail;
3144     }
3145     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3146     if (!CE) {
3147       Error(Loc, "lane index must be empty or an integer");
3148       return MatchOperand_ParseFail;
3149     }
3150     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3151       Error(Parser.getTok().getLoc(), "']' expected");
3152       return MatchOperand_ParseFail;
3153     }
3154     EndLoc = Parser.getTok().getEndLoc();
3155     Parser.Lex(); // Eat the ']'.
3156     int64_t Val = CE->getValue();
3157 
3158     // FIXME: Make this range check context sensitive for .8, .16, .32.
3159     if (Val < 0 || Val > 7) {
3160       Error(Parser.getTok().getLoc(), "lane index out of range");
3161       return MatchOperand_ParseFail;
3162     }
3163     Index = Val;
3164     LaneKind = IndexedLane;
3165     return MatchOperand_Success;
3166   }
3167   LaneKind = NoLanes;
3168   return MatchOperand_Success;
3169 }
3170 
3171 // parse a vector register list
3172 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3173 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3174   VectorLaneTy LaneKind;
3175   unsigned LaneIndex;
3176   SMLoc S = Parser.getTok().getLoc();
3177   // As an extension (to match gas), support a plain D register or Q register
3178   // (without encosing curly braces) as a single or double entry list,
3179   // respectively.
3180   if (Parser.getTok().is(AsmToken::Identifier)) {
3181     SMLoc E = Parser.getTok().getEndLoc();
3182     int Reg = tryParseRegister();
3183     if (Reg == -1)
3184       return MatchOperand_NoMatch;
3185     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3186       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3187       if (Res != MatchOperand_Success)
3188         return Res;
3189       switch (LaneKind) {
3190       case NoLanes:
3191         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3192         break;
3193       case AllLanes:
3194         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3195                                                                 S, E));
3196         break;
3197       case IndexedLane:
3198         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3199                                                                LaneIndex,
3200                                                                false, S, E));
3201         break;
3202       }
3203       return MatchOperand_Success;
3204     }
3205     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3206       Reg = getDRegFromQReg(Reg);
3207       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3208       if (Res != MatchOperand_Success)
3209         return Res;
3210       switch (LaneKind) {
3211       case NoLanes:
3212         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3213                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3214         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3215         break;
3216       case AllLanes:
3217         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3218                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3219         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3220                                                                 S, E));
3221         break;
3222       case IndexedLane:
3223         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3224                                                                LaneIndex,
3225                                                                false, S, E));
3226         break;
3227       }
3228       return MatchOperand_Success;
3229     }
3230     Error(S, "vector register expected");
3231     return MatchOperand_ParseFail;
3232   }
3233 
3234   if (Parser.getTok().isNot(AsmToken::LCurly))
3235     return MatchOperand_NoMatch;
3236 
3237   Parser.Lex(); // Eat '{' token.
3238   SMLoc RegLoc = Parser.getTok().getLoc();
3239 
3240   int Reg = tryParseRegister();
3241   if (Reg == -1) {
3242     Error(RegLoc, "register expected");
3243     return MatchOperand_ParseFail;
3244   }
3245   unsigned Count = 1;
3246   int Spacing = 0;
3247   unsigned FirstReg = Reg;
3248   // The list is of D registers, but we also allow Q regs and just interpret
3249   // them as the two D sub-registers.
3250   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3251     FirstReg = Reg = getDRegFromQReg(Reg);
3252     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3253                  // it's ambiguous with four-register single spaced.
3254     ++Reg;
3255     ++Count;
3256   }
3257 
3258   SMLoc E;
3259   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3260     return MatchOperand_ParseFail;
3261 
3262   while (Parser.getTok().is(AsmToken::Comma) ||
3263          Parser.getTok().is(AsmToken::Minus)) {
3264     if (Parser.getTok().is(AsmToken::Minus)) {
3265       if (!Spacing)
3266         Spacing = 1; // Register range implies a single spaced list.
3267       else if (Spacing == 2) {
3268         Error(Parser.getTok().getLoc(),
3269               "sequential registers in double spaced list");
3270         return MatchOperand_ParseFail;
3271       }
3272       Parser.Lex(); // Eat the minus.
3273       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3274       int EndReg = tryParseRegister();
3275       if (EndReg == -1) {
3276         Error(AfterMinusLoc, "register expected");
3277         return MatchOperand_ParseFail;
3278       }
3279       // Allow Q regs and just interpret them as the two D sub-registers.
3280       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3281         EndReg = getDRegFromQReg(EndReg) + 1;
3282       // If the register is the same as the start reg, there's nothing
3283       // more to do.
3284       if (Reg == EndReg)
3285         continue;
3286       // The register must be in the same register class as the first.
3287       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3288         Error(AfterMinusLoc, "invalid register in register list");
3289         return MatchOperand_ParseFail;
3290       }
3291       // Ranges must go from low to high.
3292       if (Reg > EndReg) {
3293         Error(AfterMinusLoc, "bad range in register list");
3294         return MatchOperand_ParseFail;
3295       }
3296       // Parse the lane specifier if present.
3297       VectorLaneTy NextLaneKind;
3298       unsigned NextLaneIndex;
3299       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3300           MatchOperand_Success)
3301         return MatchOperand_ParseFail;
3302       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3303         Error(AfterMinusLoc, "mismatched lane index in register list");
3304         return MatchOperand_ParseFail;
3305       }
3306 
3307       // Add all the registers in the range to the register list.
3308       Count += EndReg - Reg;
3309       Reg = EndReg;
3310       continue;
3311     }
3312     Parser.Lex(); // Eat the comma.
3313     RegLoc = Parser.getTok().getLoc();
3314     int OldReg = Reg;
3315     Reg = tryParseRegister();
3316     if (Reg == -1) {
3317       Error(RegLoc, "register expected");
3318       return MatchOperand_ParseFail;
3319     }
3320     // vector register lists must be contiguous.
3321     // It's OK to use the enumeration values directly here rather, as the
3322     // VFP register classes have the enum sorted properly.
3323     //
3324     // The list is of D registers, but we also allow Q regs and just interpret
3325     // them as the two D sub-registers.
3326     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3327       if (!Spacing)
3328         Spacing = 1; // Register range implies a single spaced list.
3329       else if (Spacing == 2) {
3330         Error(RegLoc,
3331               "invalid register in double-spaced list (must be 'D' register')");
3332         return MatchOperand_ParseFail;
3333       }
3334       Reg = getDRegFromQReg(Reg);
3335       if (Reg != OldReg + 1) {
3336         Error(RegLoc, "non-contiguous register range");
3337         return MatchOperand_ParseFail;
3338       }
3339       ++Reg;
3340       Count += 2;
3341       // Parse the lane specifier if present.
3342       VectorLaneTy NextLaneKind;
3343       unsigned NextLaneIndex;
3344       SMLoc LaneLoc = Parser.getTok().getLoc();
3345       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3346           MatchOperand_Success)
3347         return MatchOperand_ParseFail;
3348       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3349         Error(LaneLoc, "mismatched lane index in register list");
3350         return MatchOperand_ParseFail;
3351       }
3352       continue;
3353     }
3354     // Normal D register.
3355     // Figure out the register spacing (single or double) of the list if
3356     // we don't know it already.
3357     if (!Spacing)
3358       Spacing = 1 + (Reg == OldReg + 2);
3359 
3360     // Just check that it's contiguous and keep going.
3361     if (Reg != OldReg + Spacing) {
3362       Error(RegLoc, "non-contiguous register range");
3363       return MatchOperand_ParseFail;
3364     }
3365     ++Count;
3366     // Parse the lane specifier if present.
3367     VectorLaneTy NextLaneKind;
3368     unsigned NextLaneIndex;
3369     SMLoc EndLoc = Parser.getTok().getLoc();
3370     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3371       return MatchOperand_ParseFail;
3372     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3373       Error(EndLoc, "mismatched lane index in register list");
3374       return MatchOperand_ParseFail;
3375     }
3376   }
3377 
3378   if (Parser.getTok().isNot(AsmToken::RCurly)) {
3379     Error(Parser.getTok().getLoc(), "'}' expected");
3380     return MatchOperand_ParseFail;
3381   }
3382   E = Parser.getTok().getEndLoc();
3383   Parser.Lex(); // Eat '}' token.
3384 
3385   switch (LaneKind) {
3386   case NoLanes:
3387     // Two-register operands have been converted to the
3388     // composite register classes.
3389     if (Count == 2) {
3390       const MCRegisterClass *RC = (Spacing == 1) ?
3391         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3392         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3393       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3394     }
3395 
3396     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3397                                                     (Spacing == 2), S, E));
3398     break;
3399   case AllLanes:
3400     // Two-register operands have been converted to the
3401     // composite register classes.
3402     if (Count == 2) {
3403       const MCRegisterClass *RC = (Spacing == 1) ?
3404         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3405         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3406       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3407     }
3408     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3409                                                             (Spacing == 2),
3410                                                             S, E));
3411     break;
3412   case IndexedLane:
3413     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3414                                                            LaneIndex,
3415                                                            (Spacing == 2),
3416                                                            S, E));
3417     break;
3418   }
3419   return MatchOperand_Success;
3420 }
3421 
3422 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3423 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3424 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3425   SMLoc S = Parser.getTok().getLoc();
3426   const AsmToken &Tok = Parser.getTok();
3427   unsigned Opt;
3428 
3429   if (Tok.is(AsmToken::Identifier)) {
3430     StringRef OptStr = Tok.getString();
3431 
3432     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3433       .Case("sy",    ARM_MB::SY)
3434       .Case("st",    ARM_MB::ST)
3435       .Case("sh",    ARM_MB::ISH)
3436       .Case("ish",   ARM_MB::ISH)
3437       .Case("shst",  ARM_MB::ISHST)
3438       .Case("ishst", ARM_MB::ISHST)
3439       .Case("nsh",   ARM_MB::NSH)
3440       .Case("un",    ARM_MB::NSH)
3441       .Case("nshst", ARM_MB::NSHST)
3442       .Case("unst",  ARM_MB::NSHST)
3443       .Case("osh",   ARM_MB::OSH)
3444       .Case("oshst", ARM_MB::OSHST)
3445       .Default(~0U);
3446 
3447     if (Opt == ~0U)
3448       return MatchOperand_NoMatch;
3449 
3450     Parser.Lex(); // Eat identifier token.
3451   } else if (Tok.is(AsmToken::Hash) ||
3452              Tok.is(AsmToken::Dollar) ||
3453              Tok.is(AsmToken::Integer)) {
3454     if (Parser.getTok().isNot(AsmToken::Integer))
3455       Parser.Lex(); // Eat '#' or '$'.
3456     SMLoc Loc = Parser.getTok().getLoc();
3457 
3458     const MCExpr *MemBarrierID;
3459     if (getParser().parseExpression(MemBarrierID)) {
3460       Error(Loc, "illegal expression");
3461       return MatchOperand_ParseFail;
3462     }
3463 
3464     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3465     if (!CE) {
3466       Error(Loc, "constant expression expected");
3467       return MatchOperand_ParseFail;
3468     }
3469 
3470     int Val = CE->getValue();
3471     if (Val & ~0xf) {
3472       Error(Loc, "immediate value out of range");
3473       return MatchOperand_ParseFail;
3474     }
3475 
3476     Opt = ARM_MB::RESERVED_0 + Val;
3477   } else
3478     return MatchOperand_ParseFail;
3479 
3480   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3481   return MatchOperand_Success;
3482 }
3483 
3484 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3485 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3486 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3487   SMLoc S = Parser.getTok().getLoc();
3488   const AsmToken &Tok = Parser.getTok();
3489   unsigned Opt;
3490 
3491   if (Tok.is(AsmToken::Identifier)) {
3492     StringRef OptStr = Tok.getString();
3493 
3494     if (OptStr.lower() == "sy")
3495       Opt = ARM_ISB::SY;
3496     else
3497       return MatchOperand_NoMatch;
3498 
3499     Parser.Lex(); // Eat identifier token.
3500   } else if (Tok.is(AsmToken::Hash) ||
3501              Tok.is(AsmToken::Dollar) ||
3502              Tok.is(AsmToken::Integer)) {
3503     if (Parser.getTok().isNot(AsmToken::Integer))
3504       Parser.Lex(); // Eat '#' or '$'.
3505     SMLoc Loc = Parser.getTok().getLoc();
3506 
3507     const MCExpr *ISBarrierID;
3508     if (getParser().parseExpression(ISBarrierID)) {
3509       Error(Loc, "illegal expression");
3510       return MatchOperand_ParseFail;
3511     }
3512 
3513     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3514     if (!CE) {
3515       Error(Loc, "constant expression expected");
3516       return MatchOperand_ParseFail;
3517     }
3518 
3519     int Val = CE->getValue();
3520     if (Val & ~0xf) {
3521       Error(Loc, "immediate value out of range");
3522       return MatchOperand_ParseFail;
3523     }
3524 
3525     Opt = ARM_ISB::RESERVED_0 + Val;
3526   } else
3527     return MatchOperand_ParseFail;
3528 
3529   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3530           (ARM_ISB::InstSyncBOpt)Opt, S));
3531   return MatchOperand_Success;
3532 }
3533 
3534 
3535 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3536 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3537 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3538   SMLoc S = Parser.getTok().getLoc();
3539   const AsmToken &Tok = Parser.getTok();
3540   if (!Tok.is(AsmToken::Identifier))
3541     return MatchOperand_NoMatch;
3542   StringRef IFlagsStr = Tok.getString();
3543 
3544   // An iflags string of "none" is interpreted to mean that none of the AIF
3545   // bits are set.  Not a terribly useful instruction, but a valid encoding.
3546   unsigned IFlags = 0;
3547   if (IFlagsStr != "none") {
3548         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3549       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3550         .Case("a", ARM_PROC::A)
3551         .Case("i", ARM_PROC::I)
3552         .Case("f", ARM_PROC::F)
3553         .Default(~0U);
3554 
3555       // If some specific iflag is already set, it means that some letter is
3556       // present more than once, this is not acceptable.
3557       if (Flag == ~0U || (IFlags & Flag))
3558         return MatchOperand_NoMatch;
3559 
3560       IFlags |= Flag;
3561     }
3562   }
3563 
3564   Parser.Lex(); // Eat identifier token.
3565   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3566   return MatchOperand_Success;
3567 }
3568 
3569 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3570 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3571 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3572   SMLoc S = Parser.getTok().getLoc();
3573   const AsmToken &Tok = Parser.getTok();
3574   if (!Tok.is(AsmToken::Identifier))
3575     return MatchOperand_NoMatch;
3576   StringRef Mask = Tok.getString();
3577 
3578   if (isMClass()) {
3579     // See ARMv6-M 10.1.1
3580     std::string Name = Mask.lower();
3581     unsigned FlagsVal = StringSwitch<unsigned>(Name)
3582       // Note: in the documentation:
3583       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3584       //  for MSR APSR_nzcvq.
3585       // but we do make it an alias here.  This is so to get the "mask encoding"
3586       // bits correct on MSR APSR writes.
3587       //
3588       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3589       // should really only be allowed when writing a special register.  Note
3590       // they get dropped in the MRS instruction reading a special register as
3591       // the SYSm field is only 8 bits.
3592       //
3593       // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3594       // includes the DSP extension but that is not checked.
3595       .Case("apsr", 0x800)
3596       .Case("apsr_nzcvq", 0x800)
3597       .Case("apsr_g", 0x400)
3598       .Case("apsr_nzcvqg", 0xc00)
3599       .Case("iapsr", 0x801)
3600       .Case("iapsr_nzcvq", 0x801)
3601       .Case("iapsr_g", 0x401)
3602       .Case("iapsr_nzcvqg", 0xc01)
3603       .Case("eapsr", 0x802)
3604       .Case("eapsr_nzcvq", 0x802)
3605       .Case("eapsr_g", 0x402)
3606       .Case("eapsr_nzcvqg", 0xc02)
3607       .Case("xpsr", 0x803)
3608       .Case("xpsr_nzcvq", 0x803)
3609       .Case("xpsr_g", 0x403)
3610       .Case("xpsr_nzcvqg", 0xc03)
3611       .Case("ipsr", 0x805)
3612       .Case("epsr", 0x806)
3613       .Case("iepsr", 0x807)
3614       .Case("msp", 0x808)
3615       .Case("psp", 0x809)
3616       .Case("primask", 0x810)
3617       .Case("basepri", 0x811)
3618       .Case("basepri_max", 0x812)
3619       .Case("faultmask", 0x813)
3620       .Case("control", 0x814)
3621       .Default(~0U);
3622 
3623     if (FlagsVal == ~0U)
3624       return MatchOperand_NoMatch;
3625 
3626     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3627       // basepri, basepri_max and faultmask only valid for V7m.
3628       return MatchOperand_NoMatch;
3629 
3630     Parser.Lex(); // Eat identifier token.
3631     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3632     return MatchOperand_Success;
3633   }
3634 
3635   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3636   size_t Start = 0, Next = Mask.find('_');
3637   StringRef Flags = "";
3638   std::string SpecReg = Mask.slice(Start, Next).lower();
3639   if (Next != StringRef::npos)
3640     Flags = Mask.slice(Next+1, Mask.size());
3641 
3642   // FlagsVal contains the complete mask:
3643   // 3-0: Mask
3644   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3645   unsigned FlagsVal = 0;
3646 
3647   if (SpecReg == "apsr") {
3648     FlagsVal = StringSwitch<unsigned>(Flags)
3649     .Case("nzcvq",  0x8) // same as CPSR_f
3650     .Case("g",      0x4) // same as CPSR_s
3651     .Case("nzcvqg", 0xc) // same as CPSR_fs
3652     .Default(~0U);
3653 
3654     if (FlagsVal == ~0U) {
3655       if (!Flags.empty())
3656         return MatchOperand_NoMatch;
3657       else
3658         FlagsVal = 8; // No flag
3659     }
3660   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3661     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3662     if (Flags == "all" || Flags == "")
3663       Flags = "fc";
3664     for (int i = 0, e = Flags.size(); i != e; ++i) {
3665       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3666       .Case("c", 1)
3667       .Case("x", 2)
3668       .Case("s", 4)
3669       .Case("f", 8)
3670       .Default(~0U);
3671 
3672       // If some specific flag is already set, it means that some letter is
3673       // present more than once, this is not acceptable.
3674       if (FlagsVal == ~0U || (FlagsVal & Flag))
3675         return MatchOperand_NoMatch;
3676       FlagsVal |= Flag;
3677     }
3678   } else // No match for special register.
3679     return MatchOperand_NoMatch;
3680 
3681   // Special register without flags is NOT equivalent to "fc" flags.
3682   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3683   // two lines would enable gas compatibility at the expense of breaking
3684   // round-tripping.
3685   //
3686   // if (!FlagsVal)
3687   //  FlagsVal = 0x9;
3688 
3689   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3690   if (SpecReg == "spsr")
3691     FlagsVal |= 16;
3692 
3693   Parser.Lex(); // Eat identifier token.
3694   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3695   return MatchOperand_Success;
3696 }
3697 
3698 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3699 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3700             int Low, int High) {
3701   const AsmToken &Tok = Parser.getTok();
3702   if (Tok.isNot(AsmToken::Identifier)) {
3703     Error(Parser.getTok().getLoc(), Op + " operand expected.");
3704     return MatchOperand_ParseFail;
3705   }
3706   StringRef ShiftName = Tok.getString();
3707   std::string LowerOp = Op.lower();
3708   std::string UpperOp = Op.upper();
3709   if (ShiftName != LowerOp && ShiftName != UpperOp) {
3710     Error(Parser.getTok().getLoc(), Op + " operand expected.");
3711     return MatchOperand_ParseFail;
3712   }
3713   Parser.Lex(); // Eat shift type token.
3714 
3715   // There must be a '#' and a shift amount.
3716   if (Parser.getTok().isNot(AsmToken::Hash) &&
3717       Parser.getTok().isNot(AsmToken::Dollar)) {
3718     Error(Parser.getTok().getLoc(), "'#' expected");
3719     return MatchOperand_ParseFail;
3720   }
3721   Parser.Lex(); // Eat hash token.
3722 
3723   const MCExpr *ShiftAmount;
3724   SMLoc Loc = Parser.getTok().getLoc();
3725   SMLoc EndLoc;
3726   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3727     Error(Loc, "illegal expression");
3728     return MatchOperand_ParseFail;
3729   }
3730   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3731   if (!CE) {
3732     Error(Loc, "constant expression expected");
3733     return MatchOperand_ParseFail;
3734   }
3735   int Val = CE->getValue();
3736   if (Val < Low || Val > High) {
3737     Error(Loc, "immediate value out of range");
3738     return MatchOperand_ParseFail;
3739   }
3740 
3741   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3742 
3743   return MatchOperand_Success;
3744 }
3745 
3746 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3747 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3748   const AsmToken &Tok = Parser.getTok();
3749   SMLoc S = Tok.getLoc();
3750   if (Tok.isNot(AsmToken::Identifier)) {
3751     Error(S, "'be' or 'le' operand expected");
3752     return MatchOperand_ParseFail;
3753   }
3754   int Val = StringSwitch<int>(Tok.getString().lower())
3755     .Case("be", 1)
3756     .Case("le", 0)
3757     .Default(-1);
3758   Parser.Lex(); // Eat the token.
3759 
3760   if (Val == -1) {
3761     Error(S, "'be' or 'le' operand expected");
3762     return MatchOperand_ParseFail;
3763   }
3764   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3765                                                                   getContext()),
3766                                            S, Tok.getEndLoc()));
3767   return MatchOperand_Success;
3768 }
3769 
3770 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3771 /// instructions. Legal values are:
3772 ///     lsl #n  'n' in [0,31]
3773 ///     asr #n  'n' in [1,32]
3774 ///             n == 32 encoded as n == 0.
3775 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3776 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3777   const AsmToken &Tok = Parser.getTok();
3778   SMLoc S = Tok.getLoc();
3779   if (Tok.isNot(AsmToken::Identifier)) {
3780     Error(S, "shift operator 'asr' or 'lsl' expected");
3781     return MatchOperand_ParseFail;
3782   }
3783   StringRef ShiftName = Tok.getString();
3784   bool isASR;
3785   if (ShiftName == "lsl" || ShiftName == "LSL")
3786     isASR = false;
3787   else if (ShiftName == "asr" || ShiftName == "ASR")
3788     isASR = true;
3789   else {
3790     Error(S, "shift operator 'asr' or 'lsl' expected");
3791     return MatchOperand_ParseFail;
3792   }
3793   Parser.Lex(); // Eat the operator.
3794 
3795   // A '#' and a shift amount.
3796   if (Parser.getTok().isNot(AsmToken::Hash) &&
3797       Parser.getTok().isNot(AsmToken::Dollar)) {
3798     Error(Parser.getTok().getLoc(), "'#' expected");
3799     return MatchOperand_ParseFail;
3800   }
3801   Parser.Lex(); // Eat hash token.
3802   SMLoc ExLoc = Parser.getTok().getLoc();
3803 
3804   const MCExpr *ShiftAmount;
3805   SMLoc EndLoc;
3806   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3807     Error(ExLoc, "malformed shift expression");
3808     return MatchOperand_ParseFail;
3809   }
3810   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3811   if (!CE) {
3812     Error(ExLoc, "shift amount must be an immediate");
3813     return MatchOperand_ParseFail;
3814   }
3815 
3816   int64_t Val = CE->getValue();
3817   if (isASR) {
3818     // Shift amount must be in [1,32]
3819     if (Val < 1 || Val > 32) {
3820       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3821       return MatchOperand_ParseFail;
3822     }
3823     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3824     if (isThumb() && Val == 32) {
3825       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3826       return MatchOperand_ParseFail;
3827     }
3828     if (Val == 32) Val = 0;
3829   } else {
3830     // Shift amount must be in [1,32]
3831     if (Val < 0 || Val > 31) {
3832       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3833       return MatchOperand_ParseFail;
3834     }
3835   }
3836 
3837   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3838 
3839   return MatchOperand_Success;
3840 }
3841 
3842 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3843 /// of instructions. Legal values are:
3844 ///     ror #n  'n' in {0, 8, 16, 24}
3845 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3846 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3847   const AsmToken &Tok = Parser.getTok();
3848   SMLoc S = Tok.getLoc();
3849   if (Tok.isNot(AsmToken::Identifier))
3850     return MatchOperand_NoMatch;
3851   StringRef ShiftName = Tok.getString();
3852   if (ShiftName != "ror" && ShiftName != "ROR")
3853     return MatchOperand_NoMatch;
3854   Parser.Lex(); // Eat the operator.
3855 
3856   // A '#' and a rotate amount.
3857   if (Parser.getTok().isNot(AsmToken::Hash) &&
3858       Parser.getTok().isNot(AsmToken::Dollar)) {
3859     Error(Parser.getTok().getLoc(), "'#' expected");
3860     return MatchOperand_ParseFail;
3861   }
3862   Parser.Lex(); // Eat hash token.
3863   SMLoc ExLoc = Parser.getTok().getLoc();
3864 
3865   const MCExpr *ShiftAmount;
3866   SMLoc EndLoc;
3867   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3868     Error(ExLoc, "malformed rotate expression");
3869     return MatchOperand_ParseFail;
3870   }
3871   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3872   if (!CE) {
3873     Error(ExLoc, "rotate amount must be an immediate");
3874     return MatchOperand_ParseFail;
3875   }
3876 
3877   int64_t Val = CE->getValue();
3878   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3879   // normally, zero is represented in asm by omitting the rotate operand
3880   // entirely.
3881   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3882     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3883     return MatchOperand_ParseFail;
3884   }
3885 
3886   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3887 
3888   return MatchOperand_Success;
3889 }
3890 
3891 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3892 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3893   SMLoc S = Parser.getTok().getLoc();
3894   // The bitfield descriptor is really two operands, the LSB and the width.
3895   if (Parser.getTok().isNot(AsmToken::Hash) &&
3896       Parser.getTok().isNot(AsmToken::Dollar)) {
3897     Error(Parser.getTok().getLoc(), "'#' expected");
3898     return MatchOperand_ParseFail;
3899   }
3900   Parser.Lex(); // Eat hash token.
3901 
3902   const MCExpr *LSBExpr;
3903   SMLoc E = Parser.getTok().getLoc();
3904   if (getParser().parseExpression(LSBExpr)) {
3905     Error(E, "malformed immediate expression");
3906     return MatchOperand_ParseFail;
3907   }
3908   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3909   if (!CE) {
3910     Error(E, "'lsb' operand must be an immediate");
3911     return MatchOperand_ParseFail;
3912   }
3913 
3914   int64_t LSB = CE->getValue();
3915   // The LSB must be in the range [0,31]
3916   if (LSB < 0 || LSB > 31) {
3917     Error(E, "'lsb' operand must be in the range [0,31]");
3918     return MatchOperand_ParseFail;
3919   }
3920   E = Parser.getTok().getLoc();
3921 
3922   // Expect another immediate operand.
3923   if (Parser.getTok().isNot(AsmToken::Comma)) {
3924     Error(Parser.getTok().getLoc(), "too few operands");
3925     return MatchOperand_ParseFail;
3926   }
3927   Parser.Lex(); // Eat hash token.
3928   if (Parser.getTok().isNot(AsmToken::Hash) &&
3929       Parser.getTok().isNot(AsmToken::Dollar)) {
3930     Error(Parser.getTok().getLoc(), "'#' expected");
3931     return MatchOperand_ParseFail;
3932   }
3933   Parser.Lex(); // Eat hash token.
3934 
3935   const MCExpr *WidthExpr;
3936   SMLoc EndLoc;
3937   if (getParser().parseExpression(WidthExpr, EndLoc)) {
3938     Error(E, "malformed immediate expression");
3939     return MatchOperand_ParseFail;
3940   }
3941   CE = dyn_cast<MCConstantExpr>(WidthExpr);
3942   if (!CE) {
3943     Error(E, "'width' operand must be an immediate");
3944     return MatchOperand_ParseFail;
3945   }
3946 
3947   int64_t Width = CE->getValue();
3948   // The LSB must be in the range [1,32-lsb]
3949   if (Width < 1 || Width > 32 - LSB) {
3950     Error(E, "'width' operand must be in the range [1,32-lsb]");
3951     return MatchOperand_ParseFail;
3952   }
3953 
3954   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3955 
3956   return MatchOperand_Success;
3957 }
3958 
3959 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3960 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3961   // Check for a post-index addressing register operand. Specifically:
3962   // postidx_reg := '+' register {, shift}
3963   //              | '-' register {, shift}
3964   //              | register {, shift}
3965 
3966   // This method must return MatchOperand_NoMatch without consuming any tokens
3967   // in the case where there is no match, as other alternatives take other
3968   // parse methods.
3969   AsmToken Tok = Parser.getTok();
3970   SMLoc S = Tok.getLoc();
3971   bool haveEaten = false;
3972   bool isAdd = true;
3973   if (Tok.is(AsmToken::Plus)) {
3974     Parser.Lex(); // Eat the '+' token.
3975     haveEaten = true;
3976   } else if (Tok.is(AsmToken::Minus)) {
3977     Parser.Lex(); // Eat the '-' token.
3978     isAdd = false;
3979     haveEaten = true;
3980   }
3981 
3982   SMLoc E = Parser.getTok().getEndLoc();
3983   int Reg = tryParseRegister();
3984   if (Reg == -1) {
3985     if (!haveEaten)
3986       return MatchOperand_NoMatch;
3987     Error(Parser.getTok().getLoc(), "register expected");
3988     return MatchOperand_ParseFail;
3989   }
3990 
3991   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3992   unsigned ShiftImm = 0;
3993   if (Parser.getTok().is(AsmToken::Comma)) {
3994     Parser.Lex(); // Eat the ','.
3995     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3996       return MatchOperand_ParseFail;
3997 
3998     // FIXME: Only approximates end...may include intervening whitespace.
3999     E = Parser.getTok().getLoc();
4000   }
4001 
4002   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4003                                                   ShiftImm, S, E));
4004 
4005   return MatchOperand_Success;
4006 }
4007 
4008 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4009 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4010   // Check for a post-index addressing register operand. Specifically:
4011   // am3offset := '+' register
4012   //              | '-' register
4013   //              | register
4014   //              | # imm
4015   //              | # + imm
4016   //              | # - imm
4017 
4018   // This method must return MatchOperand_NoMatch without consuming any tokens
4019   // in the case where there is no match, as other alternatives take other
4020   // parse methods.
4021   AsmToken Tok = Parser.getTok();
4022   SMLoc S = Tok.getLoc();
4023 
4024   // Do immediates first, as we always parse those if we have a '#'.
4025   if (Parser.getTok().is(AsmToken::Hash) ||
4026       Parser.getTok().is(AsmToken::Dollar)) {
4027     Parser.Lex(); // Eat '#' or '$'.
4028     // Explicitly look for a '-', as we need to encode negative zero
4029     // differently.
4030     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4031     const MCExpr *Offset;
4032     SMLoc E;
4033     if (getParser().parseExpression(Offset, E))
4034       return MatchOperand_ParseFail;
4035     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4036     if (!CE) {
4037       Error(S, "constant expression expected");
4038       return MatchOperand_ParseFail;
4039     }
4040     // Negative zero is encoded as the flag value INT32_MIN.
4041     int32_t Val = CE->getValue();
4042     if (isNegative && Val == 0)
4043       Val = INT32_MIN;
4044 
4045     Operands.push_back(
4046       ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4047 
4048     return MatchOperand_Success;
4049   }
4050 
4051 
4052   bool haveEaten = false;
4053   bool isAdd = true;
4054   if (Tok.is(AsmToken::Plus)) {
4055     Parser.Lex(); // Eat the '+' token.
4056     haveEaten = true;
4057   } else if (Tok.is(AsmToken::Minus)) {
4058     Parser.Lex(); // Eat the '-' token.
4059     isAdd = false;
4060     haveEaten = true;
4061   }
4062 
4063   Tok = Parser.getTok();
4064   int Reg = tryParseRegister();
4065   if (Reg == -1) {
4066     if (!haveEaten)
4067       return MatchOperand_NoMatch;
4068     Error(Tok.getLoc(), "register expected");
4069     return MatchOperand_ParseFail;
4070   }
4071 
4072   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4073                                                   0, S, Tok.getEndLoc()));
4074 
4075   return MatchOperand_Success;
4076 }
4077 
4078 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
4079 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4080 /// when they refer multiple MIOperands inside a single one.
4081 void ARMAsmParser::
4082 cvtT2LdrdPre(MCInst &Inst,
4083              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4084   // Rt, Rt2
4085   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4086   ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4087   // Create a writeback register dummy placeholder.
4088   Inst.addOperand(MCOperand::CreateReg(0));
4089   // addr
4090   ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
4091   // pred
4092   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4093 }
4094 
4095 /// cvtT2StrdPre - Convert parsed operands to MCInst.
4096 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4097 /// when they refer multiple MIOperands inside a single one.
4098 void ARMAsmParser::
4099 cvtT2StrdPre(MCInst &Inst,
4100              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4101   // Create a writeback register dummy placeholder.
4102   Inst.addOperand(MCOperand::CreateReg(0));
4103   // Rt, Rt2
4104   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4105   ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4106   // addr
4107   ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
4108   // pred
4109   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4110 }
4111 
4112 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
4113 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4114 /// when they refer multiple MIOperands inside a single one.
4115 void ARMAsmParser::
4116 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
4117                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4118   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4119 
4120   // Create a writeback register dummy placeholder.
4121   Inst.addOperand(MCOperand::CreateImm(0));
4122 
4123   ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
4124   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4125 }
4126 
4127 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
4128 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4129 /// when they refer multiple MIOperands inside a single one.
4130 void ARMAsmParser::
4131 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
4132                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4133   // Create a writeback register dummy placeholder.
4134   Inst.addOperand(MCOperand::CreateImm(0));
4135   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4136   ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
4137   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4138 }
4139 
4140 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4141 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4142 /// when they refer multiple MIOperands inside a single one.
4143 void ARMAsmParser::
4144 cvtLdWriteBackRegAddrMode2(MCInst &Inst,
4145                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4146   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4147 
4148   // Create a writeback register dummy placeholder.
4149   Inst.addOperand(MCOperand::CreateImm(0));
4150 
4151   ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4152   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4153 }
4154 
4155 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4156 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4157 /// when they refer multiple MIOperands inside a single one.
4158 void ARMAsmParser::
4159 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
4160                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4161   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4162 
4163   // Create a writeback register dummy placeholder.
4164   Inst.addOperand(MCOperand::CreateImm(0));
4165 
4166   ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4167   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4168 }
4169 
4170 
4171 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4172 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4173 /// when they refer multiple MIOperands inside a single one.
4174 void ARMAsmParser::
4175 cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
4176                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4177   // Create a writeback register dummy placeholder.
4178   Inst.addOperand(MCOperand::CreateImm(0));
4179   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4180   ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4181   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4182 }
4183 
4184 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4185 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4186 /// when they refer multiple MIOperands inside a single one.
4187 void ARMAsmParser::
4188 cvtStWriteBackRegAddrMode2(MCInst &Inst,
4189                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4190   // Create a writeback register dummy placeholder.
4191   Inst.addOperand(MCOperand::CreateImm(0));
4192   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4193   ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4194   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4195 }
4196 
4197 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4198 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4199 /// when they refer multiple MIOperands inside a single one.
4200 void ARMAsmParser::
4201 cvtStWriteBackRegAddrMode3(MCInst &Inst,
4202                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4203   // Create a writeback register dummy placeholder.
4204   Inst.addOperand(MCOperand::CreateImm(0));
4205   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4206   ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4207   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4208 }
4209 
4210 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4211 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4212 /// when they refer multiple MIOperands inside a single one.
4213 void ARMAsmParser::
4214 cvtLdExtTWriteBackImm(MCInst &Inst,
4215                       const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4216   // Rt
4217   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4218   // Create a writeback register dummy placeholder.
4219   Inst.addOperand(MCOperand::CreateImm(0));
4220   // addr
4221   ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4222   // offset
4223   ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4224   // pred
4225   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4226 }
4227 
4228 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4229 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4230 /// when they refer multiple MIOperands inside a single one.
4231 void ARMAsmParser::
4232 cvtLdExtTWriteBackReg(MCInst &Inst,
4233                       const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4234   // Rt
4235   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4236   // Create a writeback register dummy placeholder.
4237   Inst.addOperand(MCOperand::CreateImm(0));
4238   // addr
4239   ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4240   // offset
4241   ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4242   // pred
4243   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4244 }
4245 
4246 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4247 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4248 /// when they refer multiple MIOperands inside a single one.
4249 void ARMAsmParser::
4250 cvtStExtTWriteBackImm(MCInst &Inst,
4251                       const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4252   // Create a writeback register dummy placeholder.
4253   Inst.addOperand(MCOperand::CreateImm(0));
4254   // Rt
4255   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4256   // addr
4257   ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4258   // offset
4259   ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4260   // pred
4261   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4262 }
4263 
4264 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4265 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4266 /// when they refer multiple MIOperands inside a single one.
4267 void ARMAsmParser::
4268 cvtStExtTWriteBackReg(MCInst &Inst,
4269                       const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4270   // Create a writeback register dummy placeholder.
4271   Inst.addOperand(MCOperand::CreateImm(0));
4272   // Rt
4273   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4274   // addr
4275   ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4276   // offset
4277   ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4278   // pred
4279   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4280 }
4281 
4282 /// cvtLdrdPre - Convert parsed operands to MCInst.
4283 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4284 /// when they refer multiple MIOperands inside a single one.
4285 void ARMAsmParser::
4286 cvtLdrdPre(MCInst &Inst,
4287            const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4288   // Rt, Rt2
4289   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4290   ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4291   // Create a writeback register dummy placeholder.
4292   Inst.addOperand(MCOperand::CreateImm(0));
4293   // addr
4294   ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4295   // pred
4296   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4297 }
4298 
4299 /// cvtStrdPre - Convert parsed operands to MCInst.
4300 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4301 /// when they refer multiple MIOperands inside a single one.
4302 void ARMAsmParser::
4303 cvtStrdPre(MCInst &Inst,
4304            const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4305   // Create a writeback register dummy placeholder.
4306   Inst.addOperand(MCOperand::CreateImm(0));
4307   // Rt, Rt2
4308   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4309   ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4310   // addr
4311   ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4312   // pred
4313   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4314 }
4315 
4316 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4317 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4318 /// when they refer multiple MIOperands inside a single one.
4319 void ARMAsmParser::
4320 cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4321                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4322   ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4323   // Create a writeback register dummy placeholder.
4324   Inst.addOperand(MCOperand::CreateImm(0));
4325   ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4326   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4327 }
4328 
4329 /// cvtThumbMultiply - Convert parsed operands to MCInst.
4330 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4331 /// when they refer multiple MIOperands inside a single one.
4332 void ARMAsmParser::
4333 cvtThumbMultiply(MCInst &Inst,
4334            const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4335   ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4336   ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4337   // If we have a three-operand form, make sure to set Rn to be the operand
4338   // that isn't the same as Rd.
4339   unsigned RegOp = 4;
4340   if (Operands.size() == 6 &&
4341       ((ARMOperand*)Operands[4])->getReg() ==
4342         ((ARMOperand*)Operands[3])->getReg())
4343     RegOp = 5;
4344   ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4345   Inst.addOperand(Inst.getOperand(0));
4346   ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4347 }
4348 
4349 void ARMAsmParser::
4350 cvtVLDwbFixed(MCInst &Inst,
4351               const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4352   // Vd
4353   ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4354   // Create a writeback register dummy placeholder.
4355   Inst.addOperand(MCOperand::CreateImm(0));
4356   // Vn
4357   ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4358   // pred
4359   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4360 }
4361 
4362 void ARMAsmParser::
4363 cvtVLDwbRegister(MCInst &Inst,
4364                  const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4365   // Vd
4366   ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4367   // Create a writeback register dummy placeholder.
4368   Inst.addOperand(MCOperand::CreateImm(0));
4369   // Vn
4370   ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4371   // Vm
4372   ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4373   // pred
4374   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4375 }
4376 
4377 void ARMAsmParser::
4378 cvtVSTwbFixed(MCInst &Inst,
4379               const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4380   // Create a writeback register dummy placeholder.
4381   Inst.addOperand(MCOperand::CreateImm(0));
4382   // Vn
4383   ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4384   // Vt
4385   ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4386   // pred
4387   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4388 }
4389 
4390 void ARMAsmParser::
4391 cvtVSTwbRegister(MCInst &Inst,
4392                  const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4393   // Create a writeback register dummy placeholder.
4394   Inst.addOperand(MCOperand::CreateImm(0));
4395   // Vn
4396   ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4397   // Vm
4398   ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4399   // Vt
4400   ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4401   // pred
4402   ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4403 }
4404 
4405 /// Parse an ARM memory expression, return false if successful else return true
4406 /// or an error.  The first token must be a '[' when called.
4407 bool ARMAsmParser::
4408 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4409   SMLoc S, E;
4410   assert(Parser.getTok().is(AsmToken::LBrac) &&
4411          "Token is not a Left Bracket");
4412   S = Parser.getTok().getLoc();
4413   Parser.Lex(); // Eat left bracket token.
4414 
4415   const AsmToken &BaseRegTok = Parser.getTok();
4416   int BaseRegNum = tryParseRegister();
4417   if (BaseRegNum == -1)
4418     return Error(BaseRegTok.getLoc(), "register expected");
4419 
4420   // The next token must either be a comma, a colon or a closing bracket.
4421   const AsmToken &Tok = Parser.getTok();
4422   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4423       !Tok.is(AsmToken::RBrac))
4424     return Error(Tok.getLoc(), "malformed memory operand");
4425 
4426   if (Tok.is(AsmToken::RBrac)) {
4427     E = Tok.getEndLoc();
4428     Parser.Lex(); // Eat right bracket token.
4429 
4430     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4431                                              0, 0, false, S, E));
4432 
4433     // If there's a pre-indexing writeback marker, '!', just add it as a token
4434     // operand. It's rather odd, but syntactically valid.
4435     if (Parser.getTok().is(AsmToken::Exclaim)) {
4436       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4437       Parser.Lex(); // Eat the '!'.
4438     }
4439 
4440     return false;
4441   }
4442 
4443   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4444          "Lost colon or comma in memory operand?!");
4445   if (Tok.is(AsmToken::Comma)) {
4446     Parser.Lex(); // Eat the comma.
4447   }
4448 
4449   // If we have a ':', it's an alignment specifier.
4450   if (Parser.getTok().is(AsmToken::Colon)) {
4451     Parser.Lex(); // Eat the ':'.
4452     E = Parser.getTok().getLoc();
4453 
4454     const MCExpr *Expr;
4455     if (getParser().parseExpression(Expr))
4456      return true;
4457 
4458     // The expression has to be a constant. Memory references with relocations
4459     // don't come through here, as they use the <label> forms of the relevant
4460     // instructions.
4461     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4462     if (!CE)
4463       return Error (E, "constant expression expected");
4464 
4465     unsigned Align = 0;
4466     switch (CE->getValue()) {
4467     default:
4468       return Error(E,
4469                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4470     case 16:  Align = 2; break;
4471     case 32:  Align = 4; break;
4472     case 64:  Align = 8; break;
4473     case 128: Align = 16; break;
4474     case 256: Align = 32; break;
4475     }
4476 
4477     // Now we should have the closing ']'
4478     if (Parser.getTok().isNot(AsmToken::RBrac))
4479       return Error(Parser.getTok().getLoc(), "']' expected");
4480     E = Parser.getTok().getEndLoc();
4481     Parser.Lex(); // Eat right bracket token.
4482 
4483     // Don't worry about range checking the value here. That's handled by
4484     // the is*() predicates.
4485     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4486                                              ARM_AM::no_shift, 0, Align,
4487                                              false, S, E));
4488 
4489     // If there's a pre-indexing writeback marker, '!', just add it as a token
4490     // operand.
4491     if (Parser.getTok().is(AsmToken::Exclaim)) {
4492       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4493       Parser.Lex(); // Eat the '!'.
4494     }
4495 
4496     return false;
4497   }
4498 
4499   // If we have a '#', it's an immediate offset, else assume it's a register
4500   // offset. Be friendly and also accept a plain integer (without a leading
4501   // hash) for gas compatibility.
4502   if (Parser.getTok().is(AsmToken::Hash) ||
4503       Parser.getTok().is(AsmToken::Dollar) ||
4504       Parser.getTok().is(AsmToken::Integer)) {
4505     if (Parser.getTok().isNot(AsmToken::Integer))
4506       Parser.Lex(); // Eat '#' or '$'.
4507     E = Parser.getTok().getLoc();
4508 
4509     bool isNegative = getParser().getTok().is(AsmToken::Minus);
4510     const MCExpr *Offset;
4511     if (getParser().parseExpression(Offset))
4512      return true;
4513 
4514     // The expression has to be a constant. Memory references with relocations
4515     // don't come through here, as they use the <label> forms of the relevant
4516     // instructions.
4517     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4518     if (!CE)
4519       return Error (E, "constant expression expected");
4520 
4521     // If the constant was #-0, represent it as INT32_MIN.
4522     int32_t Val = CE->getValue();
4523     if (isNegative && Val == 0)
4524       CE = MCConstantExpr::Create(INT32_MIN, getContext());
4525 
4526     // Now we should have the closing ']'
4527     if (Parser.getTok().isNot(AsmToken::RBrac))
4528       return Error(Parser.getTok().getLoc(), "']' expected");
4529     E = Parser.getTok().getEndLoc();
4530     Parser.Lex(); // Eat right bracket token.
4531 
4532     // Don't worry about range checking the value here. That's handled by
4533     // the is*() predicates.
4534     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4535                                              ARM_AM::no_shift, 0, 0,
4536                                              false, S, E));
4537 
4538     // If there's a pre-indexing writeback marker, '!', just add it as a token
4539     // operand.
4540     if (Parser.getTok().is(AsmToken::Exclaim)) {
4541       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4542       Parser.Lex(); // Eat the '!'.
4543     }
4544 
4545     return false;
4546   }
4547 
4548   // The register offset is optionally preceded by a '+' or '-'
4549   bool isNegative = false;
4550   if (Parser.getTok().is(AsmToken::Minus)) {
4551     isNegative = true;
4552     Parser.Lex(); // Eat the '-'.
4553   } else if (Parser.getTok().is(AsmToken::Plus)) {
4554     // Nothing to do.
4555     Parser.Lex(); // Eat the '+'.
4556   }
4557 
4558   E = Parser.getTok().getLoc();
4559   int OffsetRegNum = tryParseRegister();
4560   if (OffsetRegNum == -1)
4561     return Error(E, "register expected");
4562 
4563   // If there's a shift operator, handle it.
4564   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4565   unsigned ShiftImm = 0;
4566   if (Parser.getTok().is(AsmToken::Comma)) {
4567     Parser.Lex(); // Eat the ','.
4568     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4569       return true;
4570   }
4571 
4572   // Now we should have the closing ']'
4573   if (Parser.getTok().isNot(AsmToken::RBrac))
4574     return Error(Parser.getTok().getLoc(), "']' expected");
4575   E = Parser.getTok().getEndLoc();
4576   Parser.Lex(); // Eat right bracket token.
4577 
4578   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4579                                            ShiftType, ShiftImm, 0, isNegative,
4580                                            S, E));
4581 
4582   // If there's a pre-indexing writeback marker, '!', just add it as a token
4583   // operand.
4584   if (Parser.getTok().is(AsmToken::Exclaim)) {
4585     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4586     Parser.Lex(); // Eat the '!'.
4587   }
4588 
4589   return false;
4590 }
4591 
4592 /// parseMemRegOffsetShift - one of these two:
4593 ///   ( lsl | lsr | asr | ror ) , # shift_amount
4594 ///   rrx
4595 /// return true if it parses a shift otherwise it returns false.
4596 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4597                                           unsigned &Amount) {
4598   SMLoc Loc = Parser.getTok().getLoc();
4599   const AsmToken &Tok = Parser.getTok();
4600   if (Tok.isNot(AsmToken::Identifier))
4601     return true;
4602   StringRef ShiftName = Tok.getString();
4603   if (ShiftName == "lsl" || ShiftName == "LSL" ||
4604       ShiftName == "asl" || ShiftName == "ASL")
4605     St = ARM_AM::lsl;
4606   else if (ShiftName == "lsr" || ShiftName == "LSR")
4607     St = ARM_AM::lsr;
4608   else if (ShiftName == "asr" || ShiftName == "ASR")
4609     St = ARM_AM::asr;
4610   else if (ShiftName == "ror" || ShiftName == "ROR")
4611     St = ARM_AM::ror;
4612   else if (ShiftName == "rrx" || ShiftName == "RRX")
4613     St = ARM_AM::rrx;
4614   else
4615     return Error(Loc, "illegal shift operator");
4616   Parser.Lex(); // Eat shift type token.
4617 
4618   // rrx stands alone.
4619   Amount = 0;
4620   if (St != ARM_AM::rrx) {
4621     Loc = Parser.getTok().getLoc();
4622     // A '#' and a shift amount.
4623     const AsmToken &HashTok = Parser.getTok();
4624     if (HashTok.isNot(AsmToken::Hash) &&
4625         HashTok.isNot(AsmToken::Dollar))
4626       return Error(HashTok.getLoc(), "'#' expected");
4627     Parser.Lex(); // Eat hash token.
4628 
4629     const MCExpr *Expr;
4630     if (getParser().parseExpression(Expr))
4631       return true;
4632     // Range check the immediate.
4633     // lsl, ror: 0 <= imm <= 31
4634     // lsr, asr: 0 <= imm <= 32
4635     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4636     if (!CE)
4637       return Error(Loc, "shift amount must be an immediate");
4638     int64_t Imm = CE->getValue();
4639     if (Imm < 0 ||
4640         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4641         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4642       return Error(Loc, "immediate shift value out of range");
4643     // If <ShiftTy> #0, turn it into a no_shift.
4644     if (Imm == 0)
4645       St = ARM_AM::lsl;
4646     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4647     if (Imm == 32)
4648       Imm = 0;
4649     Amount = Imm;
4650   }
4651 
4652   return false;
4653 }
4654 
4655 /// parseFPImm - A floating point immediate expression operand.
4656 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4657 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4658   // Anything that can accept a floating point constant as an operand
4659   // needs to go through here, as the regular parseExpression is
4660   // integer only.
4661   //
4662   // This routine still creates a generic Immediate operand, containing
4663   // a bitcast of the 64-bit floating point value. The various operands
4664   // that accept floats can check whether the value is valid for them
4665   // via the standard is*() predicates.
4666 
4667   SMLoc S = Parser.getTok().getLoc();
4668 
4669   if (Parser.getTok().isNot(AsmToken::Hash) &&
4670       Parser.getTok().isNot(AsmToken::Dollar))
4671     return MatchOperand_NoMatch;
4672 
4673   // Disambiguate the VMOV forms that can accept an FP immediate.
4674   // vmov.f32 <sreg>, #imm
4675   // vmov.f64 <dreg>, #imm
4676   // vmov.f32 <dreg>, #imm  @ vector f32x2
4677   // vmov.f32 <qreg>, #imm  @ vector f32x4
4678   //
4679   // There are also the NEON VMOV instructions which expect an
4680   // integer constant. Make sure we don't try to parse an FPImm
4681   // for these:
4682   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4683   ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4684   if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4685                            TyOp->getToken() != ".f64"))
4686     return MatchOperand_NoMatch;
4687 
4688   Parser.Lex(); // Eat '#' or '$'.
4689 
4690   // Handle negation, as that still comes through as a separate token.
4691   bool isNegative = false;
4692   if (Parser.getTok().is(AsmToken::Minus)) {
4693     isNegative = true;
4694     Parser.Lex();
4695   }
4696   const AsmToken &Tok = Parser.getTok();
4697   SMLoc Loc = Tok.getLoc();
4698   if (Tok.is(AsmToken::Real)) {
4699     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4700     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4701     // If we had a '-' in front, toggle the sign bit.
4702     IntVal ^= (uint64_t)isNegative << 31;
4703     Parser.Lex(); // Eat the token.
4704     Operands.push_back(ARMOperand::CreateImm(
4705           MCConstantExpr::Create(IntVal, getContext()),
4706           S, Parser.getTok().getLoc()));
4707     return MatchOperand_Success;
4708   }
4709   // Also handle plain integers. Instructions which allow floating point
4710   // immediates also allow a raw encoded 8-bit value.
4711   if (Tok.is(AsmToken::Integer)) {
4712     int64_t Val = Tok.getIntVal();
4713     Parser.Lex(); // Eat the token.
4714     if (Val > 255 || Val < 0) {
4715       Error(Loc, "encoded floating point value out of range");
4716       return MatchOperand_ParseFail;
4717     }
4718     double RealVal = ARM_AM::getFPImmFloat(Val);
4719     Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4720     Operands.push_back(ARMOperand::CreateImm(
4721         MCConstantExpr::Create(Val, getContext()), S,
4722         Parser.getTok().getLoc()));
4723     return MatchOperand_Success;
4724   }
4725 
4726   Error(Loc, "invalid floating point immediate");
4727   return MatchOperand_ParseFail;
4728 }
4729 
4730 /// Parse a arm instruction operand.  For now this parses the operand regardless
4731 /// of the mnemonic.
4732 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4733                                 StringRef Mnemonic) {
4734   SMLoc S, E;
4735 
4736   // Check if the current operand has a custom associated parser, if so, try to
4737   // custom parse the operand, or fallback to the general approach.
4738   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4739   if (ResTy == MatchOperand_Success)
4740     return false;
4741   // If there wasn't a custom match, try the generic matcher below. Otherwise,
4742   // there was a match, but an error occurred, in which case, just return that
4743   // the operand parsing failed.
4744   if (ResTy == MatchOperand_ParseFail)
4745     return true;
4746 
4747   switch (getLexer().getKind()) {
4748   default:
4749     Error(Parser.getTok().getLoc(), "unexpected token in operand");
4750     return true;
4751   case AsmToken::Identifier: {
4752     // If we've seen a branch mnemonic, the next operand must be a label.  This
4753     // is true even if the label is a register name.  So "br r1" means branch to
4754     // label "r1".
4755     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4756     if (!ExpectLabel) {
4757       if (!tryParseRegisterWithWriteBack(Operands))
4758         return false;
4759       int Res = tryParseShiftRegister(Operands);
4760       if (Res == 0) // success
4761         return false;
4762       else if (Res == -1) // irrecoverable error
4763         return true;
4764       // If this is VMRS, check for the apsr_nzcv operand.
4765       if (Mnemonic == "vmrs" &&
4766           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4767         S = Parser.getTok().getLoc();
4768         Parser.Lex();
4769         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4770         return false;
4771       }
4772     }
4773 
4774     // Fall though for the Identifier case that is not a register or a
4775     // special name.
4776   }
4777   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4778   case AsmToken::Integer: // things like 1f and 2b as a branch targets
4779   case AsmToken::String:  // quoted label names.
4780   case AsmToken::Dot: {   // . as a branch target
4781     // This was not a register so parse other operands that start with an
4782     // identifier (like labels) as expressions and create them as immediates.
4783     const MCExpr *IdVal;
4784     S = Parser.getTok().getLoc();
4785     if (getParser().parseExpression(IdVal))
4786       return true;
4787     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4788     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4789     return false;
4790   }
4791   case AsmToken::LBrac:
4792     return parseMemory(Operands);
4793   case AsmToken::LCurly:
4794     return parseRegisterList(Operands);
4795   case AsmToken::Dollar:
4796   case AsmToken::Hash: {
4797     // #42 -> immediate.
4798     S = Parser.getTok().getLoc();
4799     Parser.Lex();
4800 
4801     if (Parser.getTok().isNot(AsmToken::Colon)) {
4802       bool isNegative = Parser.getTok().is(AsmToken::Minus);
4803       const MCExpr *ImmVal;
4804       if (getParser().parseExpression(ImmVal))
4805         return true;
4806       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4807       if (CE) {
4808         int32_t Val = CE->getValue();
4809         if (isNegative && Val == 0)
4810           ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4811       }
4812       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4813       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4814 
4815       // There can be a trailing '!' on operands that we want as a separate
4816       // '!' Token operand. Handle that here. For example, the compatibilty
4817       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4818       if (Parser.getTok().is(AsmToken::Exclaim)) {
4819         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4820                                                    Parser.getTok().getLoc()));
4821         Parser.Lex(); // Eat exclaim token
4822       }
4823       return false;
4824     }
4825     // w/ a ':' after the '#', it's just like a plain ':'.
4826     // FALLTHROUGH
4827   }
4828   case AsmToken::Colon: {
4829     // ":lower16:" and ":upper16:" expression prefixes
4830     // FIXME: Check it's an expression prefix,
4831     // e.g. (FOO - :lower16:BAR) isn't legal.
4832     ARMMCExpr::VariantKind RefKind;
4833     if (parsePrefix(RefKind))
4834       return true;
4835 
4836     const MCExpr *SubExprVal;
4837     if (getParser().parseExpression(SubExprVal))
4838       return true;
4839 
4840     const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4841                                               getContext());
4842     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4843     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4844     return false;
4845   }
4846   }
4847 }
4848 
4849 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4850 //  :lower16: and :upper16:.
4851 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4852   RefKind = ARMMCExpr::VK_ARM_None;
4853 
4854   // :lower16: and :upper16: modifiers
4855   assert(getLexer().is(AsmToken::Colon) && "expected a :");
4856   Parser.Lex(); // Eat ':'
4857 
4858   if (getLexer().isNot(AsmToken::Identifier)) {
4859     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4860     return true;
4861   }
4862 
4863   StringRef IDVal = Parser.getTok().getIdentifier();
4864   if (IDVal == "lower16") {
4865     RefKind = ARMMCExpr::VK_ARM_LO16;
4866   } else if (IDVal == "upper16") {
4867     RefKind = ARMMCExpr::VK_ARM_HI16;
4868   } else {
4869     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4870     return true;
4871   }
4872   Parser.Lex();
4873 
4874   if (getLexer().isNot(AsmToken::Colon)) {
4875     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4876     return true;
4877   }
4878   Parser.Lex(); // Eat the last ':'
4879   return false;
4880 }
4881 
4882 /// \brief Given a mnemonic, split out possible predication code and carry
4883 /// setting letters to form a canonical mnemonic and flags.
4884 //
4885 // FIXME: Would be nice to autogen this.
4886 // FIXME: This is a bit of a maze of special cases.
4887 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4888                                       unsigned &PredicationCode,
4889                                       bool &CarrySetting,
4890                                       unsigned &ProcessorIMod,
4891                                       StringRef &ITMask) {
4892   PredicationCode = ARMCC::AL;
4893   CarrySetting = false;
4894   ProcessorIMod = 0;
4895 
4896   // Ignore some mnemonics we know aren't predicated forms.
4897   //
4898   // FIXME: Would be nice to autogen this.
4899   if ((Mnemonic == "movs" && isThumb()) ||
4900       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4901       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4902       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4903       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4904       Mnemonic == "vaclt" || Mnemonic == "vacle"  ||
4905       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4906       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4907       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4908       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4909       Mnemonic.startswith("vsel"))
4910     return Mnemonic;
4911 
4912   // First, split out any predication code. Ignore mnemonics we know aren't
4913   // predicated but do have a carry-set and so weren't caught above.
4914   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4915       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4916       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4917       Mnemonic != "sbcs" && Mnemonic != "rscs") {
4918     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4919       .Case("eq", ARMCC::EQ)
4920       .Case("ne", ARMCC::NE)
4921       .Case("hs", ARMCC::HS)
4922       .Case("cs", ARMCC::HS)
4923       .Case("lo", ARMCC::LO)
4924       .Case("cc", ARMCC::LO)
4925       .Case("mi", ARMCC::MI)
4926       .Case("pl", ARMCC::PL)
4927       .Case("vs", ARMCC::VS)
4928       .Case("vc", ARMCC::VC)
4929       .Case("hi", ARMCC::HI)
4930       .Case("ls", ARMCC::LS)
4931       .Case("ge", ARMCC::GE)
4932       .Case("lt", ARMCC::LT)
4933       .Case("gt", ARMCC::GT)
4934       .Case("le", ARMCC::LE)
4935       .Case("al", ARMCC::AL)
4936       .Default(~0U);
4937     if (CC != ~0U) {
4938       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4939       PredicationCode = CC;
4940     }
4941   }
4942 
4943   // Next, determine if we have a carry setting bit. We explicitly ignore all
4944   // the instructions we know end in 's'.
4945   if (Mnemonic.endswith("s") &&
4946       !(Mnemonic == "cps" || Mnemonic == "mls" ||
4947         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4948         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4949         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4950         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4951         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4952         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4953         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4954         Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4955         (Mnemonic == "movs" && isThumb()))) {
4956     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4957     CarrySetting = true;
4958   }
4959 
4960   // The "cps" instruction can have a interrupt mode operand which is glued into
4961   // the mnemonic. Check if this is the case, split it and parse the imod op
4962   if (Mnemonic.startswith("cps")) {
4963     // Split out any imod code.
4964     unsigned IMod =
4965       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4966       .Case("ie", ARM_PROC::IE)
4967       .Case("id", ARM_PROC::ID)
4968       .Default(~0U);
4969     if (IMod != ~0U) {
4970       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4971       ProcessorIMod = IMod;
4972     }
4973   }
4974 
4975   // The "it" instruction has the condition mask on the end of the mnemonic.
4976   if (Mnemonic.startswith("it")) {
4977     ITMask = Mnemonic.slice(2, Mnemonic.size());
4978     Mnemonic = Mnemonic.slice(0, 2);
4979   }
4980 
4981   return Mnemonic;
4982 }
4983 
4984 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4985 /// inclusion of carry set or predication code operands.
4986 //
4987 // FIXME: It would be nice to autogen this.
4988 void ARMAsmParser::
4989 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4990                       bool &CanAcceptPredicationCode) {
4991   if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4992       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4993       Mnemonic == "add" || Mnemonic == "adc" ||
4994       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4995       Mnemonic == "orr" || Mnemonic == "mvn" ||
4996       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4997       Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4998       Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4999       (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5000                       Mnemonic == "mla" || Mnemonic == "smlal" ||
5001                       Mnemonic == "umlal" || Mnemonic == "umull"))) {
5002     CanAcceptCarrySet = true;
5003   } else
5004     CanAcceptCarrySet = false;
5005 
5006   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5007       Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
5008       Mnemonic == "trap" || Mnemonic == "setend" ||
5009       Mnemonic.startswith("cps") || Mnemonic == "vmaxnm" ||
5010 			Mnemonic == "vminnm" || Mnemonic.startswith("vsel")) {
5011     // These mnemonics are never predicable
5012     CanAcceptPredicationCode = false;
5013   } else if (!isThumb()) {
5014     // Some instructions are only predicable in Thumb mode
5015     CanAcceptPredicationCode
5016       = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5017         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5018         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5019         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5020         Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5021         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5022         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5023   } else if (isThumbOne()) {
5024     CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5025   } else
5026     CanAcceptPredicationCode = true;
5027 }
5028 
5029 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5030                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5031   // FIXME: This is all horribly hacky. We really need a better way to deal
5032   // with optional operands like this in the matcher table.
5033 
5034   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5035   // another does not. Specifically, the MOVW instruction does not. So we
5036   // special case it here and remove the defaulted (non-setting) cc_out
5037   // operand if that's the instruction we're trying to match.
5038   //
5039   // We do this as post-processing of the explicit operands rather than just
5040   // conditionally adding the cc_out in the first place because we need
5041   // to check the type of the parsed immediate operand.
5042   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5043       !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5044       static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5045       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5046     return true;
5047 
5048   // Register-register 'add' for thumb does not have a cc_out operand
5049   // when there are only two register operands.
5050   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5051       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5052       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5053       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5054     return true;
5055   // Register-register 'add' for thumb does not have a cc_out operand
5056   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5057   // have to check the immediate range here since Thumb2 has a variant
5058   // that can handle a different range and has a cc_out operand.
5059   if (((isThumb() && Mnemonic == "add") ||
5060        (isThumbTwo() && Mnemonic == "sub")) &&
5061       Operands.size() == 6 &&
5062       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5063       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5064       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5065       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5066       ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5067        static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5068     return true;
5069   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5070   // imm0_4095 variant. That's the least-preferred variant when
5071   // selecting via the generic "add" mnemonic, so to know that we
5072   // should remove the cc_out operand, we have to explicitly check that
5073   // it's not one of the other variants. Ugh.
5074   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5075       Operands.size() == 6 &&
5076       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5077       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5078       static_cast<ARMOperand*>(Operands[5])->isImm()) {
5079     // Nest conditions rather than one big 'if' statement for readability.
5080     //
5081     // If both registers are low, we're in an IT block, and the immediate is
5082     // in range, we should use encoding T1 instead, which has a cc_out.
5083     if (inITBlock() &&
5084         isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5085         isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5086         static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5087       return false;
5088     // Check against T3. If the second register is the PC, this is an
5089     // alternate form of ADR, which uses encoding T4, so check for that too.
5090     if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5091         static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5092       return false;
5093 
5094     // Otherwise, we use encoding T4, which does not have a cc_out
5095     // operand.
5096     return true;
5097   }
5098 
5099   // The thumb2 multiply instruction doesn't have a CCOut register, so
5100   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5101   // use the 16-bit encoding or not.
5102   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5103       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5104       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5105       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5106       static_cast<ARMOperand*>(Operands[5])->isReg() &&
5107       // If the registers aren't low regs, the destination reg isn't the
5108       // same as one of the source regs, or the cc_out operand is zero
5109       // outside of an IT block, we have to use the 32-bit encoding, so
5110       // remove the cc_out operand.
5111       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5112        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5113        !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5114        !inITBlock() ||
5115        (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5116         static_cast<ARMOperand*>(Operands[5])->getReg() &&
5117         static_cast<ARMOperand*>(Operands[3])->getReg() !=
5118         static_cast<ARMOperand*>(Operands[4])->getReg())))
5119     return true;
5120 
5121   // Also check the 'mul' syntax variant that doesn't specify an explicit
5122   // destination register.
5123   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5124       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5125       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5126       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5127       // If the registers aren't low regs  or the cc_out operand is zero
5128       // outside of an IT block, we have to use the 32-bit encoding, so
5129       // remove the cc_out operand.
5130       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5131        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5132        !inITBlock()))
5133     return true;
5134 
5135 
5136 
5137   // Register-register 'add/sub' for thumb does not have a cc_out operand
5138   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5139   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5140   // right, this will result in better diagnostics (which operand is off)
5141   // anyway.
5142   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5143       (Operands.size() == 5 || Operands.size() == 6) &&
5144       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5145       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5146       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5147       (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5148        (Operands.size() == 6 &&
5149         static_cast<ARMOperand*>(Operands[5])->isImm())))
5150     return true;
5151 
5152   return false;
5153 }
5154 
5155 static bool isDataTypeToken(StringRef Tok) {
5156   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5157     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5158     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5159     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5160     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5161     Tok == ".f" || Tok == ".d";
5162 }
5163 
5164 // FIXME: This bit should probably be handled via an explicit match class
5165 // in the .td files that matches the suffix instead of having it be
5166 // a literal string token the way it is now.
5167 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5168   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5169 }
5170 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5171                                  unsigned VariantID);
5172 /// Parse an arm instruction mnemonic followed by its operands.
5173 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5174                                     SMLoc NameLoc,
5175                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5176   // Apply mnemonic aliases before doing anything else, as the destination
5177   // mnemnonic may include suffices and we want to handle them normally.
5178   // The generic tblgen'erated code does this later, at the start of
5179   // MatchInstructionImpl(), but that's too late for aliases that include
5180   // any sort of suffix.
5181   unsigned AvailableFeatures = getAvailableFeatures();
5182   unsigned AssemblerDialect = getParser().getAssemblerDialect();
5183   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5184 
5185   // First check for the ARM-specific .req directive.
5186   if (Parser.getTok().is(AsmToken::Identifier) &&
5187       Parser.getTok().getIdentifier() == ".req") {
5188     parseDirectiveReq(Name, NameLoc);
5189     // We always return 'error' for this, as we're done with this
5190     // statement and don't need to match the 'instruction."
5191     return true;
5192   }
5193 
5194   // Create the leading tokens for the mnemonic, split by '.' characters.
5195   size_t Start = 0, Next = Name.find('.');
5196   StringRef Mnemonic = Name.slice(Start, Next);
5197 
5198   // Split out the predication code and carry setting flag from the mnemonic.
5199   unsigned PredicationCode;
5200   unsigned ProcessorIMod;
5201   bool CarrySetting;
5202   StringRef ITMask;
5203   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5204                            ProcessorIMod, ITMask);
5205 
5206   // In Thumb1, only the branch (B) instruction can be predicated.
5207   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5208     Parser.eatToEndOfStatement();
5209     return Error(NameLoc, "conditional execution not supported in Thumb1");
5210   }
5211 
5212   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5213 
5214   // Handle the IT instruction ITMask. Convert it to a bitmask. This
5215   // is the mask as it will be for the IT encoding if the conditional
5216   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5217   // where the conditional bit0 is zero, the instruction post-processing
5218   // will adjust the mask accordingly.
5219   if (Mnemonic == "it") {
5220     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5221     if (ITMask.size() > 3) {
5222       Parser.eatToEndOfStatement();
5223       return Error(Loc, "too many conditions on IT instruction");
5224     }
5225     unsigned Mask = 8;
5226     for (unsigned i = ITMask.size(); i != 0; --i) {
5227       char pos = ITMask[i - 1];
5228       if (pos != 't' && pos != 'e') {
5229         Parser.eatToEndOfStatement();
5230         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5231       }
5232       Mask >>= 1;
5233       if (ITMask[i - 1] == 't')
5234         Mask |= 8;
5235     }
5236     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5237   }
5238 
5239   // FIXME: This is all a pretty gross hack. We should automatically handle
5240   // optional operands like this via tblgen.
5241 
5242   // Next, add the CCOut and ConditionCode operands, if needed.
5243   //
5244   // For mnemonics which can ever incorporate a carry setting bit or predication
5245   // code, our matching model involves us always generating CCOut and
5246   // ConditionCode operands to match the mnemonic "as written" and then we let
5247   // the matcher deal with finding the right instruction or generating an
5248   // appropriate error.
5249   bool CanAcceptCarrySet, CanAcceptPredicationCode;
5250   getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5251 
5252   // If we had a carry-set on an instruction that can't do that, issue an
5253   // error.
5254   if (!CanAcceptCarrySet && CarrySetting) {
5255     Parser.eatToEndOfStatement();
5256     return Error(NameLoc, "instruction '" + Mnemonic +
5257                  "' can not set flags, but 's' suffix specified");
5258   }
5259   // If we had a predication code on an instruction that can't do that, issue an
5260   // error.
5261   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5262     Parser.eatToEndOfStatement();
5263     return Error(NameLoc, "instruction '" + Mnemonic +
5264                  "' is not predicable, but condition code specified");
5265   }
5266 
5267   // Add the carry setting operand, if necessary.
5268   if (CanAcceptCarrySet) {
5269     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5270     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5271                                                Loc));
5272   }
5273 
5274   // Add the predication code operand, if necessary.
5275   if (CanAcceptPredicationCode) {
5276     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5277                                       CarrySetting);
5278     Operands.push_back(ARMOperand::CreateCondCode(
5279                          ARMCC::CondCodes(PredicationCode), Loc));
5280   }
5281 
5282   // Add the processor imod operand, if necessary.
5283   if (ProcessorIMod) {
5284     Operands.push_back(ARMOperand::CreateImm(
5285           MCConstantExpr::Create(ProcessorIMod, getContext()),
5286                                  NameLoc, NameLoc));
5287   }
5288 
5289   // Add the remaining tokens in the mnemonic.
5290   while (Next != StringRef::npos) {
5291     Start = Next;
5292     Next = Name.find('.', Start + 1);
5293     StringRef ExtraToken = Name.slice(Start, Next);
5294 
5295     // Some NEON instructions have an optional datatype suffix that is
5296     // completely ignored. Check for that.
5297     if (isDataTypeToken(ExtraToken) &&
5298         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5299       continue;
5300 
5301     // For for ARM mode generate an error if the .n qualifier is used.
5302     if (ExtraToken == ".n" && !isThumb()) {
5303       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5304       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5305                    "arm mode");
5306     }
5307 
5308     // The .n qualifier is always discarded as that is what the tables
5309     // and matcher expect.  In ARM mode the .w qualifier has no effect,
5310     // so discard it to avoid errors that can be caused by the matcher.
5311     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5312       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5313       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5314     }
5315   }
5316 
5317   // Read the remaining operands.
5318   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5319     // Read the first operand.
5320     if (parseOperand(Operands, Mnemonic)) {
5321       Parser.eatToEndOfStatement();
5322       return true;
5323     }
5324 
5325     while (getLexer().is(AsmToken::Comma)) {
5326       Parser.Lex();  // Eat the comma.
5327 
5328       // Parse and remember the operand.
5329       if (parseOperand(Operands, Mnemonic)) {
5330         Parser.eatToEndOfStatement();
5331         return true;
5332       }
5333     }
5334   }
5335 
5336   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5337     SMLoc Loc = getLexer().getLoc();
5338     Parser.eatToEndOfStatement();
5339     return Error(Loc, "unexpected token in argument list");
5340   }
5341 
5342   Parser.Lex(); // Consume the EndOfStatement
5343 
5344   // Some instructions, mostly Thumb, have forms for the same mnemonic that
5345   // do and don't have a cc_out optional-def operand. With some spot-checks
5346   // of the operand list, we can figure out which variant we're trying to
5347   // parse and adjust accordingly before actually matching. We shouldn't ever
5348   // try to remove a cc_out operand that was explicitly set on the the
5349   // mnemonic, of course (CarrySetting == true). Reason number #317 the
5350   // table driven matcher doesn't fit well with the ARM instruction set.
5351   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5352     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5353     Operands.erase(Operands.begin() + 1);
5354     delete Op;
5355   }
5356 
5357   // ARM mode 'blx' need special handling, as the register operand version
5358   // is predicable, but the label operand version is not. So, we can't rely
5359   // on the Mnemonic based checking to correctly figure out when to put
5360   // a k_CondCode operand in the list. If we're trying to match the label
5361   // version, remove the k_CondCode operand here.
5362   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5363       static_cast<ARMOperand*>(Operands[2])->isImm()) {
5364     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5365     Operands.erase(Operands.begin() + 1);
5366     delete Op;
5367   }
5368 
5369   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5370   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5371   // a single GPRPair reg operand is used in the .td file to replace the two
5372   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5373   // expressed as a GPRPair, so we have to manually merge them.
5374   // FIXME: We would really like to be able to tablegen'erate this.
5375   if (!isThumb() && Operands.size() > 4 &&
5376       (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5377     bool isLoad = (Mnemonic == "ldrexd");
5378     unsigned Idx = isLoad ? 2 : 3;
5379     ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5380     ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5381 
5382     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5383     // Adjust only if Op1 and Op2 are GPRs.
5384     if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5385         MRC.contains(Op2->getReg())) {
5386       unsigned Reg1 = Op1->getReg();
5387       unsigned Reg2 = Op2->getReg();
5388       unsigned Rt = MRI->getEncodingValue(Reg1);
5389       unsigned Rt2 = MRI->getEncodingValue(Reg2);
5390 
5391       // Rt2 must be Rt + 1 and Rt must be even.
5392       if (Rt + 1 != Rt2 || (Rt & 1)) {
5393         Error(Op2->getStartLoc(), isLoad ?
5394             "destination operands must be sequential" :
5395             "source operands must be sequential");
5396         return true;
5397       }
5398       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5399           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5400       Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5401       Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5402             NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5403       delete Op1;
5404       delete Op2;
5405     }
5406   }
5407 
5408   return false;
5409 }
5410 
5411 // Validate context-sensitive operand constraints.
5412 
5413 // return 'true' if register list contains non-low GPR registers,
5414 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5415 // 'containsReg' to true.
5416 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5417                                  unsigned HiReg, bool &containsReg) {
5418   containsReg = false;
5419   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5420     unsigned OpReg = Inst.getOperand(i).getReg();
5421     if (OpReg == Reg)
5422       containsReg = true;
5423     // Anything other than a low register isn't legal here.
5424     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5425       return true;
5426   }
5427   return false;
5428 }
5429 
5430 // Check if the specified regisgter is in the register list of the inst,
5431 // starting at the indicated operand number.
5432 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5433   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5434     unsigned OpReg = Inst.getOperand(i).getReg();
5435     if (OpReg == Reg)
5436       return true;
5437   }
5438   return false;
5439 }
5440 
5441 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5442 // the ARMInsts array) instead. Getting that here requires awkward
5443 // API changes, though. Better way?
5444 namespace llvm {
5445 extern const MCInstrDesc ARMInsts[];
5446 }
5447 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5448   return ARMInsts[Opcode];
5449 }
5450 
5451 // FIXME: We would really like to be able to tablegen'erate this.
5452 bool ARMAsmParser::
5453 validateInstruction(MCInst &Inst,
5454                     const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5455   const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5456   SMLoc Loc = Operands[0]->getStartLoc();
5457   // Check the IT block state first.
5458   // NOTE: BKPT instruction has the interesting property of being
5459   // allowed in IT blocks, but not being predicable.  It just always
5460   // executes.
5461   if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5462       Inst.getOpcode() != ARM::BKPT) {
5463     unsigned bit = 1;
5464     if (ITState.FirstCond)
5465       ITState.FirstCond = false;
5466     else
5467       bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5468     // The instruction must be predicable.
5469     if (!MCID.isPredicable())
5470       return Error(Loc, "instructions in IT block must be predicable");
5471     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5472     unsigned ITCond = bit ? ITState.Cond :
5473       ARMCC::getOppositeCondition(ITState.Cond);
5474     if (Cond != ITCond) {
5475       // Find the condition code Operand to get its SMLoc information.
5476       SMLoc CondLoc;
5477       for (unsigned i = 1; i < Operands.size(); ++i)
5478         if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5479           CondLoc = Operands[i]->getStartLoc();
5480       return Error(CondLoc, "incorrect condition in IT block; got '" +
5481                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5482                    "', but expected '" +
5483                    ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5484     }
5485   // Check for non-'al' condition codes outside of the IT block.
5486   } else if (isThumbTwo() && MCID.isPredicable() &&
5487              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5488              ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5489              Inst.getOpcode() != ARM::t2B)
5490     return Error(Loc, "predicated instructions must be in IT block");
5491 
5492   switch (Inst.getOpcode()) {
5493   case ARM::LDRD:
5494   case ARM::LDRD_PRE:
5495   case ARM::LDRD_POST: {
5496     // Rt2 must be Rt + 1.
5497     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5498     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5499     if (Rt2 != Rt + 1)
5500       return Error(Operands[3]->getStartLoc(),
5501                    "destination operands must be sequential");
5502     return false;
5503   }
5504   case ARM::STRD: {
5505     // Rt2 must be Rt + 1.
5506     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5507     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5508     if (Rt2 != Rt + 1)
5509       return Error(Operands[3]->getStartLoc(),
5510                    "source operands must be sequential");
5511     return false;
5512   }
5513   case ARM::STRD_PRE:
5514   case ARM::STRD_POST: {
5515     // Rt2 must be Rt + 1.
5516     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5517     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5518     if (Rt2 != Rt + 1)
5519       return Error(Operands[3]->getStartLoc(),
5520                    "source operands must be sequential");
5521     return false;
5522   }
5523   case ARM::SBFX:
5524   case ARM::UBFX: {
5525     // width must be in range [1, 32-lsb]
5526     unsigned lsb = Inst.getOperand(2).getImm();
5527     unsigned widthm1 = Inst.getOperand(3).getImm();
5528     if (widthm1 >= 32 - lsb)
5529       return Error(Operands[5]->getStartLoc(),
5530                    "bitfield width must be in range [1,32-lsb]");
5531     return false;
5532   }
5533   case ARM::tLDMIA: {
5534     // If we're parsing Thumb2, the .w variant is available and handles
5535     // most cases that are normally illegal for a Thumb1 LDM
5536     // instruction. We'll make the transformation in processInstruction()
5537     // if necessary.
5538     //
5539     // Thumb LDM instructions are writeback iff the base register is not
5540     // in the register list.
5541     unsigned Rn = Inst.getOperand(0).getReg();
5542     bool hasWritebackToken =
5543       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5544        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5545     bool listContainsBase;
5546     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5547       return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5548                    "registers must be in range r0-r7");
5549     // If we should have writeback, then there should be a '!' token.
5550     if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5551       return Error(Operands[2]->getStartLoc(),
5552                    "writeback operator '!' expected");
5553     // If we should not have writeback, there must not be a '!'. This is
5554     // true even for the 32-bit wide encodings.
5555     if (listContainsBase && hasWritebackToken)
5556       return Error(Operands[3]->getStartLoc(),
5557                    "writeback operator '!' not allowed when base register "
5558                    "in register list");
5559 
5560     break;
5561   }
5562   case ARM::t2LDMIA_UPD: {
5563     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5564       return Error(Operands[4]->getStartLoc(),
5565                    "writeback operator '!' not allowed when base register "
5566                    "in register list");
5567     break;
5568   }
5569   case ARM::tMUL: {
5570     // The second source operand must be the same register as the destination
5571     // operand.
5572     //
5573     // In this case, we must directly check the parsed operands because the
5574     // cvtThumbMultiply() function is written in such a way that it guarantees
5575     // this first statement is always true for the new Inst.  Essentially, the
5576     // destination is unconditionally copied into the second source operand
5577     // without checking to see if it matches what we actually parsed.
5578     if (Operands.size() == 6 &&
5579         (((ARMOperand*)Operands[3])->getReg() !=
5580          ((ARMOperand*)Operands[5])->getReg()) &&
5581         (((ARMOperand*)Operands[3])->getReg() !=
5582          ((ARMOperand*)Operands[4])->getReg())) {
5583       return Error(Operands[3]->getStartLoc(),
5584                    "destination register must match source register");
5585     }
5586     break;
5587   }
5588   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5589   // so only issue a diagnostic for thumb1. The instructions will be
5590   // switched to the t2 encodings in processInstruction() if necessary.
5591   case ARM::tPOP: {
5592     bool listContainsBase;
5593     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5594         !isThumbTwo())
5595       return Error(Operands[2]->getStartLoc(),
5596                    "registers must be in range r0-r7 or pc");
5597     break;
5598   }
5599   case ARM::tPUSH: {
5600     bool listContainsBase;
5601     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5602         !isThumbTwo())
5603       return Error(Operands[2]->getStartLoc(),
5604                    "registers must be in range r0-r7 or lr");
5605     break;
5606   }
5607   case ARM::tSTMIA_UPD: {
5608     bool listContainsBase;
5609     if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5610       return Error(Operands[4]->getStartLoc(),
5611                    "registers must be in range r0-r7");
5612     break;
5613   }
5614   case ARM::tADDrSP: {
5615     // If the non-SP source operand and the destination operand are not the
5616     // same, we need thumb2 (for the wide encoding), or we have an error.
5617     if (!isThumbTwo() &&
5618         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5619       return Error(Operands[4]->getStartLoc(),
5620                    "source register must be the same as destination");
5621     }
5622     break;
5623   }
5624   }
5625 
5626   return false;
5627 }
5628 
5629 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5630   switch(Opc) {
5631   default: llvm_unreachable("unexpected opcode!");
5632   // VST1LN
5633   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5634   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5635   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5636   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5637   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5638   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5639   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5640   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5641   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5642 
5643   // VST2LN
5644   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5645   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5646   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5647   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5648   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5649 
5650   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5651   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5652   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5653   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5654   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5655 
5656   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5657   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5658   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5659   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5660   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5661 
5662   // VST3LN
5663   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5664   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5665   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5666   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5667   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5668   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5669   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5670   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5671   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5672   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5673   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5674   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5675   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5676   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5677   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5678 
5679   // VST3
5680   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5681   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5682   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5683   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5684   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5685   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5686   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5687   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5688   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5689   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5690   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5691   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5692   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5693   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5694   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5695   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5696   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5697   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5698 
5699   // VST4LN
5700   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5701   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5702   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5703   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5704   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5705   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5706   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5707   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5708   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5709   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5710   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5711   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5712   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5713   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5714   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5715 
5716   // VST4
5717   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5718   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5719   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5720   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5721   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5722   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5723   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5724   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5725   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5726   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5727   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5728   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5729   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5730   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5731   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5732   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5733   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5734   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5735   }
5736 }
5737 
5738 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5739   switch(Opc) {
5740   default: llvm_unreachable("unexpected opcode!");
5741   // VLD1LN
5742   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5743   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5744   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5745   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5746   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5747   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5748   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5749   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5750   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5751 
5752   // VLD2LN
5753   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5754   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5755   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5756   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5757   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5758   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5759   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5760   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5761   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5762   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5763   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5764   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5765   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5766   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5767   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5768 
5769   // VLD3DUP
5770   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5771   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5772   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5773   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5774   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5775   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5776   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5777   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5778   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5779   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5780   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5781   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5782   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5783   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5784   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5785   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5786   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5787   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5788 
5789   // VLD3LN
5790   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5791   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5792   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5793   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5794   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5795   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5796   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5797   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5798   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5799   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5800   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5801   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5802   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5803   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5804   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5805 
5806   // VLD3
5807   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5808   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5809   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5810   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5811   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5812   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5813   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5814   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5815   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5816   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5817   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5818   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5819   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5820   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5821   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5822   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5823   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5824   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5825 
5826   // VLD4LN
5827   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5828   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5829   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5830   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5831   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5832   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5833   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5834   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5835   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5836   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5837   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5838   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5839   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5840   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5841   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5842 
5843   // VLD4DUP
5844   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5845   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5846   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5847   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5848   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5849   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5850   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5851   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5852   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5853   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5854   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5855   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5856   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5857   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5858   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5859   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5860   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5861   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5862 
5863   // VLD4
5864   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5865   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5866   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5867   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5868   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5869   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5870   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5871   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5872   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5873   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5874   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5875   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5876   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5877   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5878   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5879   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5880   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5881   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5882   }
5883 }
5884 
5885 bool ARMAsmParser::
5886 processInstruction(MCInst &Inst,
5887                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5888   switch (Inst.getOpcode()) {
5889   // Alias for alternate form of 'ADR Rd, #imm' instruction.
5890   case ARM::ADDri: {
5891     if (Inst.getOperand(1).getReg() != ARM::PC ||
5892         Inst.getOperand(5).getReg() != 0)
5893       return false;
5894     MCInst TmpInst;
5895     TmpInst.setOpcode(ARM::ADR);
5896     TmpInst.addOperand(Inst.getOperand(0));
5897     TmpInst.addOperand(Inst.getOperand(2));
5898     TmpInst.addOperand(Inst.getOperand(3));
5899     TmpInst.addOperand(Inst.getOperand(4));
5900     Inst = TmpInst;
5901     return true;
5902   }
5903   // Aliases for alternate PC+imm syntax of LDR instructions.
5904   case ARM::t2LDRpcrel:
5905     // Select the narrow version if the immediate will fit.
5906     if (Inst.getOperand(1).getImm() > 0 &&
5907         Inst.getOperand(1).getImm() <= 0xff &&
5908         !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5909          static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5910       Inst.setOpcode(ARM::tLDRpci);
5911     else
5912       Inst.setOpcode(ARM::t2LDRpci);
5913     return true;
5914   case ARM::t2LDRBpcrel:
5915     Inst.setOpcode(ARM::t2LDRBpci);
5916     return true;
5917   case ARM::t2LDRHpcrel:
5918     Inst.setOpcode(ARM::t2LDRHpci);
5919     return true;
5920   case ARM::t2LDRSBpcrel:
5921     Inst.setOpcode(ARM::t2LDRSBpci);
5922     return true;
5923   case ARM::t2LDRSHpcrel:
5924     Inst.setOpcode(ARM::t2LDRSHpci);
5925     return true;
5926   // Handle NEON VST complex aliases.
5927   case ARM::VST1LNdWB_register_Asm_8:
5928   case ARM::VST1LNdWB_register_Asm_16:
5929   case ARM::VST1LNdWB_register_Asm_32: {
5930     MCInst TmpInst;
5931     // Shuffle the operands around so the lane index operand is in the
5932     // right place.
5933     unsigned Spacing;
5934     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5935     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5936     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5937     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5938     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5939     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5940     TmpInst.addOperand(Inst.getOperand(1)); // lane
5941     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5942     TmpInst.addOperand(Inst.getOperand(6));
5943     Inst = TmpInst;
5944     return true;
5945   }
5946 
5947   case ARM::VST2LNdWB_register_Asm_8:
5948   case ARM::VST2LNdWB_register_Asm_16:
5949   case ARM::VST2LNdWB_register_Asm_32:
5950   case ARM::VST2LNqWB_register_Asm_16:
5951   case ARM::VST2LNqWB_register_Asm_32: {
5952     MCInst TmpInst;
5953     // Shuffle the operands around so the lane index operand is in the
5954     // right place.
5955     unsigned Spacing;
5956     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5957     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5958     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5959     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5960     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5961     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5962     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5963                                             Spacing));
5964     TmpInst.addOperand(Inst.getOperand(1)); // lane
5965     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5966     TmpInst.addOperand(Inst.getOperand(6));
5967     Inst = TmpInst;
5968     return true;
5969   }
5970 
5971   case ARM::VST3LNdWB_register_Asm_8:
5972   case ARM::VST3LNdWB_register_Asm_16:
5973   case ARM::VST3LNdWB_register_Asm_32:
5974   case ARM::VST3LNqWB_register_Asm_16:
5975   case ARM::VST3LNqWB_register_Asm_32: {
5976     MCInst TmpInst;
5977     // Shuffle the operands around so the lane index operand is in the
5978     // right place.
5979     unsigned Spacing;
5980     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5981     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5982     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5983     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5984     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5985     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5986     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5987                                             Spacing));
5988     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5989                                             Spacing * 2));
5990     TmpInst.addOperand(Inst.getOperand(1)); // lane
5991     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5992     TmpInst.addOperand(Inst.getOperand(6));
5993     Inst = TmpInst;
5994     return true;
5995   }
5996 
5997   case ARM::VST4LNdWB_register_Asm_8:
5998   case ARM::VST4LNdWB_register_Asm_16:
5999   case ARM::VST4LNdWB_register_Asm_32:
6000   case ARM::VST4LNqWB_register_Asm_16:
6001   case ARM::VST4LNqWB_register_Asm_32: {
6002     MCInst TmpInst;
6003     // Shuffle the operands around so the lane index operand is in the
6004     // right place.
6005     unsigned Spacing;
6006     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6007     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6008     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6009     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6010     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6011     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6012     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6013                                             Spacing));
6014     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6015                                             Spacing * 2));
6016     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6017                                             Spacing * 3));
6018     TmpInst.addOperand(Inst.getOperand(1)); // lane
6019     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6020     TmpInst.addOperand(Inst.getOperand(6));
6021     Inst = TmpInst;
6022     return true;
6023   }
6024 
6025   case ARM::VST1LNdWB_fixed_Asm_8:
6026   case ARM::VST1LNdWB_fixed_Asm_16:
6027   case ARM::VST1LNdWB_fixed_Asm_32: {
6028     MCInst TmpInst;
6029     // Shuffle the operands around so the lane index operand is in the
6030     // right place.
6031     unsigned Spacing;
6032     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6033     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6034     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6035     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6036     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6037     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6038     TmpInst.addOperand(Inst.getOperand(1)); // lane
6039     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6040     TmpInst.addOperand(Inst.getOperand(5));
6041     Inst = TmpInst;
6042     return true;
6043   }
6044 
6045   case ARM::VST2LNdWB_fixed_Asm_8:
6046   case ARM::VST2LNdWB_fixed_Asm_16:
6047   case ARM::VST2LNdWB_fixed_Asm_32:
6048   case ARM::VST2LNqWB_fixed_Asm_16:
6049   case ARM::VST2LNqWB_fixed_Asm_32: {
6050     MCInst TmpInst;
6051     // Shuffle the operands around so the lane index operand is in the
6052     // right place.
6053     unsigned Spacing;
6054     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6055     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6056     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6057     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6058     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6059     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6060     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6061                                             Spacing));
6062     TmpInst.addOperand(Inst.getOperand(1)); // lane
6063     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6064     TmpInst.addOperand(Inst.getOperand(5));
6065     Inst = TmpInst;
6066     return true;
6067   }
6068 
6069   case ARM::VST3LNdWB_fixed_Asm_8:
6070   case ARM::VST3LNdWB_fixed_Asm_16:
6071   case ARM::VST3LNdWB_fixed_Asm_32:
6072   case ARM::VST3LNqWB_fixed_Asm_16:
6073   case ARM::VST3LNqWB_fixed_Asm_32: {
6074     MCInst TmpInst;
6075     // Shuffle the operands around so the lane index operand is in the
6076     // right place.
6077     unsigned Spacing;
6078     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6079     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6080     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6081     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6082     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6083     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6084     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6085                                             Spacing));
6086     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6087                                             Spacing * 2));
6088     TmpInst.addOperand(Inst.getOperand(1)); // lane
6089     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6090     TmpInst.addOperand(Inst.getOperand(5));
6091     Inst = TmpInst;
6092     return true;
6093   }
6094 
6095   case ARM::VST4LNdWB_fixed_Asm_8:
6096   case ARM::VST4LNdWB_fixed_Asm_16:
6097   case ARM::VST4LNdWB_fixed_Asm_32:
6098   case ARM::VST4LNqWB_fixed_Asm_16:
6099   case ARM::VST4LNqWB_fixed_Asm_32: {
6100     MCInst TmpInst;
6101     // Shuffle the operands around so the lane index operand is in the
6102     // right place.
6103     unsigned Spacing;
6104     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6105     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6106     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6107     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6108     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6109     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6110     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6111                                             Spacing));
6112     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6113                                             Spacing * 2));
6114     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6115                                             Spacing * 3));
6116     TmpInst.addOperand(Inst.getOperand(1)); // lane
6117     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6118     TmpInst.addOperand(Inst.getOperand(5));
6119     Inst = TmpInst;
6120     return true;
6121   }
6122 
6123   case ARM::VST1LNdAsm_8:
6124   case ARM::VST1LNdAsm_16:
6125   case ARM::VST1LNdAsm_32: {
6126     MCInst TmpInst;
6127     // Shuffle the operands around so the lane index operand is in the
6128     // right place.
6129     unsigned Spacing;
6130     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6131     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6132     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6133     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6134     TmpInst.addOperand(Inst.getOperand(1)); // lane
6135     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6136     TmpInst.addOperand(Inst.getOperand(5));
6137     Inst = TmpInst;
6138     return true;
6139   }
6140 
6141   case ARM::VST2LNdAsm_8:
6142   case ARM::VST2LNdAsm_16:
6143   case ARM::VST2LNdAsm_32:
6144   case ARM::VST2LNqAsm_16:
6145   case ARM::VST2LNqAsm_32: {
6146     MCInst TmpInst;
6147     // Shuffle the operands around so the lane index operand is in the
6148     // right place.
6149     unsigned Spacing;
6150     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6151     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6152     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6153     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6154     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6155                                             Spacing));
6156     TmpInst.addOperand(Inst.getOperand(1)); // lane
6157     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6158     TmpInst.addOperand(Inst.getOperand(5));
6159     Inst = TmpInst;
6160     return true;
6161   }
6162 
6163   case ARM::VST3LNdAsm_8:
6164   case ARM::VST3LNdAsm_16:
6165   case ARM::VST3LNdAsm_32:
6166   case ARM::VST3LNqAsm_16:
6167   case ARM::VST3LNqAsm_32: {
6168     MCInst TmpInst;
6169     // Shuffle the operands around so the lane index operand is in the
6170     // right place.
6171     unsigned Spacing;
6172     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6173     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6174     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6175     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6176     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6177                                             Spacing));
6178     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6179                                             Spacing * 2));
6180     TmpInst.addOperand(Inst.getOperand(1)); // lane
6181     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6182     TmpInst.addOperand(Inst.getOperand(5));
6183     Inst = TmpInst;
6184     return true;
6185   }
6186 
6187   case ARM::VST4LNdAsm_8:
6188   case ARM::VST4LNdAsm_16:
6189   case ARM::VST4LNdAsm_32:
6190   case ARM::VST4LNqAsm_16:
6191   case ARM::VST4LNqAsm_32: {
6192     MCInst TmpInst;
6193     // Shuffle the operands around so the lane index operand is in the
6194     // right place.
6195     unsigned Spacing;
6196     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6197     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6198     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6199     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6200     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6201                                             Spacing));
6202     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6203                                             Spacing * 2));
6204     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6205                                             Spacing * 3));
6206     TmpInst.addOperand(Inst.getOperand(1)); // lane
6207     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6208     TmpInst.addOperand(Inst.getOperand(5));
6209     Inst = TmpInst;
6210     return true;
6211   }
6212 
6213   // Handle NEON VLD complex aliases.
6214   case ARM::VLD1LNdWB_register_Asm_8:
6215   case ARM::VLD1LNdWB_register_Asm_16:
6216   case ARM::VLD1LNdWB_register_Asm_32: {
6217     MCInst TmpInst;
6218     // Shuffle the operands around so the lane index operand is in the
6219     // right place.
6220     unsigned Spacing;
6221     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6222     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6223     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6224     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6225     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6226     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6227     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6228     TmpInst.addOperand(Inst.getOperand(1)); // lane
6229     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6230     TmpInst.addOperand(Inst.getOperand(6));
6231     Inst = TmpInst;
6232     return true;
6233   }
6234 
6235   case ARM::VLD2LNdWB_register_Asm_8:
6236   case ARM::VLD2LNdWB_register_Asm_16:
6237   case ARM::VLD2LNdWB_register_Asm_32:
6238   case ARM::VLD2LNqWB_register_Asm_16:
6239   case ARM::VLD2LNqWB_register_Asm_32: {
6240     MCInst TmpInst;
6241     // Shuffle the operands around so the lane index operand is in the
6242     // right place.
6243     unsigned Spacing;
6244     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6245     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6246     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6247                                             Spacing));
6248     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6249     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6250     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6251     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6252     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6253     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6254                                             Spacing));
6255     TmpInst.addOperand(Inst.getOperand(1)); // lane
6256     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6257     TmpInst.addOperand(Inst.getOperand(6));
6258     Inst = TmpInst;
6259     return true;
6260   }
6261 
6262   case ARM::VLD3LNdWB_register_Asm_8:
6263   case ARM::VLD3LNdWB_register_Asm_16:
6264   case ARM::VLD3LNdWB_register_Asm_32:
6265   case ARM::VLD3LNqWB_register_Asm_16:
6266   case ARM::VLD3LNqWB_register_Asm_32: {
6267     MCInst TmpInst;
6268     // Shuffle the operands around so the lane index operand is in the
6269     // right place.
6270     unsigned Spacing;
6271     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6272     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6273     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6274                                             Spacing));
6275     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6276                                             Spacing * 2));
6277     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6278     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6279     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6280     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6281     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6282     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6283                                             Spacing));
6284     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6285                                             Spacing * 2));
6286     TmpInst.addOperand(Inst.getOperand(1)); // lane
6287     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6288     TmpInst.addOperand(Inst.getOperand(6));
6289     Inst = TmpInst;
6290     return true;
6291   }
6292 
6293   case ARM::VLD4LNdWB_register_Asm_8:
6294   case ARM::VLD4LNdWB_register_Asm_16:
6295   case ARM::VLD4LNdWB_register_Asm_32:
6296   case ARM::VLD4LNqWB_register_Asm_16:
6297   case ARM::VLD4LNqWB_register_Asm_32: {
6298     MCInst TmpInst;
6299     // Shuffle the operands around so the lane index operand is in the
6300     // right place.
6301     unsigned Spacing;
6302     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6303     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6304     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6305                                             Spacing));
6306     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6307                                             Spacing * 2));
6308     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6309                                             Spacing * 3));
6310     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6311     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6312     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6313     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6314     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6315     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6316                                             Spacing));
6317     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6318                                             Spacing * 2));
6319     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6320                                             Spacing * 3));
6321     TmpInst.addOperand(Inst.getOperand(1)); // lane
6322     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6323     TmpInst.addOperand(Inst.getOperand(6));
6324     Inst = TmpInst;
6325     return true;
6326   }
6327 
6328   case ARM::VLD1LNdWB_fixed_Asm_8:
6329   case ARM::VLD1LNdWB_fixed_Asm_16:
6330   case ARM::VLD1LNdWB_fixed_Asm_32: {
6331     MCInst TmpInst;
6332     // Shuffle the operands around so the lane index operand is in the
6333     // right place.
6334     unsigned Spacing;
6335     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6336     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6337     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6338     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6339     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6340     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6341     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6342     TmpInst.addOperand(Inst.getOperand(1)); // lane
6343     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6344     TmpInst.addOperand(Inst.getOperand(5));
6345     Inst = TmpInst;
6346     return true;
6347   }
6348 
6349   case ARM::VLD2LNdWB_fixed_Asm_8:
6350   case ARM::VLD2LNdWB_fixed_Asm_16:
6351   case ARM::VLD2LNdWB_fixed_Asm_32:
6352   case ARM::VLD2LNqWB_fixed_Asm_16:
6353   case ARM::VLD2LNqWB_fixed_Asm_32: {
6354     MCInst TmpInst;
6355     // Shuffle the operands around so the lane index operand is in the
6356     // right place.
6357     unsigned Spacing;
6358     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6359     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6360     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6361                                             Spacing));
6362     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6363     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6364     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6365     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6366     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6367     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6368                                             Spacing));
6369     TmpInst.addOperand(Inst.getOperand(1)); // lane
6370     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6371     TmpInst.addOperand(Inst.getOperand(5));
6372     Inst = TmpInst;
6373     return true;
6374   }
6375 
6376   case ARM::VLD3LNdWB_fixed_Asm_8:
6377   case ARM::VLD3LNdWB_fixed_Asm_16:
6378   case ARM::VLD3LNdWB_fixed_Asm_32:
6379   case ARM::VLD3LNqWB_fixed_Asm_16:
6380   case ARM::VLD3LNqWB_fixed_Asm_32: {
6381     MCInst TmpInst;
6382     // Shuffle the operands around so the lane index operand is in the
6383     // right place.
6384     unsigned Spacing;
6385     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6386     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6387     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6388                                             Spacing));
6389     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6390                                             Spacing * 2));
6391     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6392     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6393     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6394     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6395     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6396     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6397                                             Spacing));
6398     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6399                                             Spacing * 2));
6400     TmpInst.addOperand(Inst.getOperand(1)); // lane
6401     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6402     TmpInst.addOperand(Inst.getOperand(5));
6403     Inst = TmpInst;
6404     return true;
6405   }
6406 
6407   case ARM::VLD4LNdWB_fixed_Asm_8:
6408   case ARM::VLD4LNdWB_fixed_Asm_16:
6409   case ARM::VLD4LNdWB_fixed_Asm_32:
6410   case ARM::VLD4LNqWB_fixed_Asm_16:
6411   case ARM::VLD4LNqWB_fixed_Asm_32: {
6412     MCInst TmpInst;
6413     // Shuffle the operands around so the lane index operand is in the
6414     // right place.
6415     unsigned Spacing;
6416     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6417     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6418     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6419                                             Spacing));
6420     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6421                                             Spacing * 2));
6422     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6423                                             Spacing * 3));
6424     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6425     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6426     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6427     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6428     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6429     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6430                                             Spacing));
6431     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6432                                             Spacing * 2));
6433     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6434                                             Spacing * 3));
6435     TmpInst.addOperand(Inst.getOperand(1)); // lane
6436     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6437     TmpInst.addOperand(Inst.getOperand(5));
6438     Inst = TmpInst;
6439     return true;
6440   }
6441 
6442   case ARM::VLD1LNdAsm_8:
6443   case ARM::VLD1LNdAsm_16:
6444   case ARM::VLD1LNdAsm_32: {
6445     MCInst TmpInst;
6446     // Shuffle the operands around so the lane index operand is in the
6447     // right place.
6448     unsigned Spacing;
6449     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6450     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6451     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6452     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6453     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6454     TmpInst.addOperand(Inst.getOperand(1)); // lane
6455     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6456     TmpInst.addOperand(Inst.getOperand(5));
6457     Inst = TmpInst;
6458     return true;
6459   }
6460 
6461   case ARM::VLD2LNdAsm_8:
6462   case ARM::VLD2LNdAsm_16:
6463   case ARM::VLD2LNdAsm_32:
6464   case ARM::VLD2LNqAsm_16:
6465   case ARM::VLD2LNqAsm_32: {
6466     MCInst TmpInst;
6467     // Shuffle the operands around so the lane index operand is in the
6468     // right place.
6469     unsigned Spacing;
6470     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6471     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6472     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6473                                             Spacing));
6474     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6475     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6476     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6477     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6478                                             Spacing));
6479     TmpInst.addOperand(Inst.getOperand(1)); // lane
6480     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6481     TmpInst.addOperand(Inst.getOperand(5));
6482     Inst = TmpInst;
6483     return true;
6484   }
6485 
6486   case ARM::VLD3LNdAsm_8:
6487   case ARM::VLD3LNdAsm_16:
6488   case ARM::VLD3LNdAsm_32:
6489   case ARM::VLD3LNqAsm_16:
6490   case ARM::VLD3LNqAsm_32: {
6491     MCInst TmpInst;
6492     // Shuffle the operands around so the lane index operand is in the
6493     // right place.
6494     unsigned Spacing;
6495     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6496     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6497     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6498                                             Spacing));
6499     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6500                                             Spacing * 2));
6501     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6502     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6503     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6504     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6505                                             Spacing));
6506     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6507                                             Spacing * 2));
6508     TmpInst.addOperand(Inst.getOperand(1)); // lane
6509     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6510     TmpInst.addOperand(Inst.getOperand(5));
6511     Inst = TmpInst;
6512     return true;
6513   }
6514 
6515   case ARM::VLD4LNdAsm_8:
6516   case ARM::VLD4LNdAsm_16:
6517   case ARM::VLD4LNdAsm_32:
6518   case ARM::VLD4LNqAsm_16:
6519   case ARM::VLD4LNqAsm_32: {
6520     MCInst TmpInst;
6521     // Shuffle the operands around so the lane index operand is in the
6522     // right place.
6523     unsigned Spacing;
6524     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6525     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6526     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6527                                             Spacing));
6528     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6529                                             Spacing * 2));
6530     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6531                                             Spacing * 3));
6532     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6533     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6534     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6535     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6536                                             Spacing));
6537     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6538                                             Spacing * 2));
6539     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6540                                             Spacing * 3));
6541     TmpInst.addOperand(Inst.getOperand(1)); // lane
6542     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6543     TmpInst.addOperand(Inst.getOperand(5));
6544     Inst = TmpInst;
6545     return true;
6546   }
6547 
6548   // VLD3DUP single 3-element structure to all lanes instructions.
6549   case ARM::VLD3DUPdAsm_8:
6550   case ARM::VLD3DUPdAsm_16:
6551   case ARM::VLD3DUPdAsm_32:
6552   case ARM::VLD3DUPqAsm_8:
6553   case ARM::VLD3DUPqAsm_16:
6554   case ARM::VLD3DUPqAsm_32: {
6555     MCInst TmpInst;
6556     unsigned Spacing;
6557     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6558     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6559     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6560                                             Spacing));
6561     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6562                                             Spacing * 2));
6563     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6564     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6565     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6566     TmpInst.addOperand(Inst.getOperand(4));
6567     Inst = TmpInst;
6568     return true;
6569   }
6570 
6571   case ARM::VLD3DUPdWB_fixed_Asm_8:
6572   case ARM::VLD3DUPdWB_fixed_Asm_16:
6573   case ARM::VLD3DUPdWB_fixed_Asm_32:
6574   case ARM::VLD3DUPqWB_fixed_Asm_8:
6575   case ARM::VLD3DUPqWB_fixed_Asm_16:
6576   case ARM::VLD3DUPqWB_fixed_Asm_32: {
6577     MCInst TmpInst;
6578     unsigned Spacing;
6579     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6580     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6581     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6582                                             Spacing));
6583     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6584                                             Spacing * 2));
6585     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6586     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6587     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6588     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6589     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6590     TmpInst.addOperand(Inst.getOperand(4));
6591     Inst = TmpInst;
6592     return true;
6593   }
6594 
6595   case ARM::VLD3DUPdWB_register_Asm_8:
6596   case ARM::VLD3DUPdWB_register_Asm_16:
6597   case ARM::VLD3DUPdWB_register_Asm_32:
6598   case ARM::VLD3DUPqWB_register_Asm_8:
6599   case ARM::VLD3DUPqWB_register_Asm_16:
6600   case ARM::VLD3DUPqWB_register_Asm_32: {
6601     MCInst TmpInst;
6602     unsigned Spacing;
6603     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6604     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6605     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6606                                             Spacing));
6607     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6608                                             Spacing * 2));
6609     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6610     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6611     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6612     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6613     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6614     TmpInst.addOperand(Inst.getOperand(5));
6615     Inst = TmpInst;
6616     return true;
6617   }
6618 
6619   // VLD3 multiple 3-element structure instructions.
6620   case ARM::VLD3dAsm_8:
6621   case ARM::VLD3dAsm_16:
6622   case ARM::VLD3dAsm_32:
6623   case ARM::VLD3qAsm_8:
6624   case ARM::VLD3qAsm_16:
6625   case ARM::VLD3qAsm_32: {
6626     MCInst TmpInst;
6627     unsigned Spacing;
6628     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6629     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6630     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6631                                             Spacing));
6632     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6633                                             Spacing * 2));
6634     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6635     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6636     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6637     TmpInst.addOperand(Inst.getOperand(4));
6638     Inst = TmpInst;
6639     return true;
6640   }
6641 
6642   case ARM::VLD3dWB_fixed_Asm_8:
6643   case ARM::VLD3dWB_fixed_Asm_16:
6644   case ARM::VLD3dWB_fixed_Asm_32:
6645   case ARM::VLD3qWB_fixed_Asm_8:
6646   case ARM::VLD3qWB_fixed_Asm_16:
6647   case ARM::VLD3qWB_fixed_Asm_32: {
6648     MCInst TmpInst;
6649     unsigned Spacing;
6650     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6651     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6652     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6653                                             Spacing));
6654     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6655                                             Spacing * 2));
6656     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6657     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6658     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6659     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6660     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6661     TmpInst.addOperand(Inst.getOperand(4));
6662     Inst = TmpInst;
6663     return true;
6664   }
6665 
6666   case ARM::VLD3dWB_register_Asm_8:
6667   case ARM::VLD3dWB_register_Asm_16:
6668   case ARM::VLD3dWB_register_Asm_32:
6669   case ARM::VLD3qWB_register_Asm_8:
6670   case ARM::VLD3qWB_register_Asm_16:
6671   case ARM::VLD3qWB_register_Asm_32: {
6672     MCInst TmpInst;
6673     unsigned Spacing;
6674     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6675     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6676     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6677                                             Spacing));
6678     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6679                                             Spacing * 2));
6680     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6681     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6682     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6683     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6684     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6685     TmpInst.addOperand(Inst.getOperand(5));
6686     Inst = TmpInst;
6687     return true;
6688   }
6689 
6690   // VLD4DUP single 3-element structure to all lanes instructions.
6691   case ARM::VLD4DUPdAsm_8:
6692   case ARM::VLD4DUPdAsm_16:
6693   case ARM::VLD4DUPdAsm_32:
6694   case ARM::VLD4DUPqAsm_8:
6695   case ARM::VLD4DUPqAsm_16:
6696   case ARM::VLD4DUPqAsm_32: {
6697     MCInst TmpInst;
6698     unsigned Spacing;
6699     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6700     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6701     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6702                                             Spacing));
6703     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6704                                             Spacing * 2));
6705     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6706                                             Spacing * 3));
6707     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6708     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6709     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6710     TmpInst.addOperand(Inst.getOperand(4));
6711     Inst = TmpInst;
6712     return true;
6713   }
6714 
6715   case ARM::VLD4DUPdWB_fixed_Asm_8:
6716   case ARM::VLD4DUPdWB_fixed_Asm_16:
6717   case ARM::VLD4DUPdWB_fixed_Asm_32:
6718   case ARM::VLD4DUPqWB_fixed_Asm_8:
6719   case ARM::VLD4DUPqWB_fixed_Asm_16:
6720   case ARM::VLD4DUPqWB_fixed_Asm_32: {
6721     MCInst TmpInst;
6722     unsigned Spacing;
6723     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6724     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6725     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6726                                             Spacing));
6727     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6728                                             Spacing * 2));
6729     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6730                                             Spacing * 3));
6731     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6732     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6733     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6734     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6735     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6736     TmpInst.addOperand(Inst.getOperand(4));
6737     Inst = TmpInst;
6738     return true;
6739   }
6740 
6741   case ARM::VLD4DUPdWB_register_Asm_8:
6742   case ARM::VLD4DUPdWB_register_Asm_16:
6743   case ARM::VLD4DUPdWB_register_Asm_32:
6744   case ARM::VLD4DUPqWB_register_Asm_8:
6745   case ARM::VLD4DUPqWB_register_Asm_16:
6746   case ARM::VLD4DUPqWB_register_Asm_32: {
6747     MCInst TmpInst;
6748     unsigned Spacing;
6749     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6750     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6751     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6752                                             Spacing));
6753     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6754                                             Spacing * 2));
6755     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6756                                             Spacing * 3));
6757     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6758     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6759     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6760     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6761     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6762     TmpInst.addOperand(Inst.getOperand(5));
6763     Inst = TmpInst;
6764     return true;
6765   }
6766 
6767   // VLD4 multiple 4-element structure instructions.
6768   case ARM::VLD4dAsm_8:
6769   case ARM::VLD4dAsm_16:
6770   case ARM::VLD4dAsm_32:
6771   case ARM::VLD4qAsm_8:
6772   case ARM::VLD4qAsm_16:
6773   case ARM::VLD4qAsm_32: {
6774     MCInst TmpInst;
6775     unsigned Spacing;
6776     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6777     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6778     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6779                                             Spacing));
6780     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6781                                             Spacing * 2));
6782     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6783                                             Spacing * 3));
6784     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6785     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6786     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6787     TmpInst.addOperand(Inst.getOperand(4));
6788     Inst = TmpInst;
6789     return true;
6790   }
6791 
6792   case ARM::VLD4dWB_fixed_Asm_8:
6793   case ARM::VLD4dWB_fixed_Asm_16:
6794   case ARM::VLD4dWB_fixed_Asm_32:
6795   case ARM::VLD4qWB_fixed_Asm_8:
6796   case ARM::VLD4qWB_fixed_Asm_16:
6797   case ARM::VLD4qWB_fixed_Asm_32: {
6798     MCInst TmpInst;
6799     unsigned Spacing;
6800     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6801     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6802     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6803                                             Spacing));
6804     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6805                                             Spacing * 2));
6806     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6807                                             Spacing * 3));
6808     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6809     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6810     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6811     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6812     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6813     TmpInst.addOperand(Inst.getOperand(4));
6814     Inst = TmpInst;
6815     return true;
6816   }
6817 
6818   case ARM::VLD4dWB_register_Asm_8:
6819   case ARM::VLD4dWB_register_Asm_16:
6820   case ARM::VLD4dWB_register_Asm_32:
6821   case ARM::VLD4qWB_register_Asm_8:
6822   case ARM::VLD4qWB_register_Asm_16:
6823   case ARM::VLD4qWB_register_Asm_32: {
6824     MCInst TmpInst;
6825     unsigned Spacing;
6826     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6827     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6828     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6829                                             Spacing));
6830     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6831                                             Spacing * 2));
6832     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6833                                             Spacing * 3));
6834     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6835     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6836     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6837     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6838     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6839     TmpInst.addOperand(Inst.getOperand(5));
6840     Inst = TmpInst;
6841     return true;
6842   }
6843 
6844   // VST3 multiple 3-element structure instructions.
6845   case ARM::VST3dAsm_8:
6846   case ARM::VST3dAsm_16:
6847   case ARM::VST3dAsm_32:
6848   case ARM::VST3qAsm_8:
6849   case ARM::VST3qAsm_16:
6850   case ARM::VST3qAsm_32: {
6851     MCInst TmpInst;
6852     unsigned Spacing;
6853     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6854     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6855     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6856     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6857     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6858                                             Spacing));
6859     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6860                                             Spacing * 2));
6861     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6862     TmpInst.addOperand(Inst.getOperand(4));
6863     Inst = TmpInst;
6864     return true;
6865   }
6866 
6867   case ARM::VST3dWB_fixed_Asm_8:
6868   case ARM::VST3dWB_fixed_Asm_16:
6869   case ARM::VST3dWB_fixed_Asm_32:
6870   case ARM::VST3qWB_fixed_Asm_8:
6871   case ARM::VST3qWB_fixed_Asm_16:
6872   case ARM::VST3qWB_fixed_Asm_32: {
6873     MCInst TmpInst;
6874     unsigned Spacing;
6875     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6876     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6877     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6878     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6879     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6880     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6881     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6882                                             Spacing));
6883     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6884                                             Spacing * 2));
6885     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6886     TmpInst.addOperand(Inst.getOperand(4));
6887     Inst = TmpInst;
6888     return true;
6889   }
6890 
6891   case ARM::VST3dWB_register_Asm_8:
6892   case ARM::VST3dWB_register_Asm_16:
6893   case ARM::VST3dWB_register_Asm_32:
6894   case ARM::VST3qWB_register_Asm_8:
6895   case ARM::VST3qWB_register_Asm_16:
6896   case ARM::VST3qWB_register_Asm_32: {
6897     MCInst TmpInst;
6898     unsigned Spacing;
6899     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6900     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6901     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6902     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6903     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6904     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6905     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6906                                             Spacing));
6907     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6908                                             Spacing * 2));
6909     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6910     TmpInst.addOperand(Inst.getOperand(5));
6911     Inst = TmpInst;
6912     return true;
6913   }
6914 
6915   // VST4 multiple 3-element structure instructions.
6916   case ARM::VST4dAsm_8:
6917   case ARM::VST4dAsm_16:
6918   case ARM::VST4dAsm_32:
6919   case ARM::VST4qAsm_8:
6920   case ARM::VST4qAsm_16:
6921   case ARM::VST4qAsm_32: {
6922     MCInst TmpInst;
6923     unsigned Spacing;
6924     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6925     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6926     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6927     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6928     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6929                                             Spacing));
6930     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6931                                             Spacing * 2));
6932     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6933                                             Spacing * 3));
6934     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6935     TmpInst.addOperand(Inst.getOperand(4));
6936     Inst = TmpInst;
6937     return true;
6938   }
6939 
6940   case ARM::VST4dWB_fixed_Asm_8:
6941   case ARM::VST4dWB_fixed_Asm_16:
6942   case ARM::VST4dWB_fixed_Asm_32:
6943   case ARM::VST4qWB_fixed_Asm_8:
6944   case ARM::VST4qWB_fixed_Asm_16:
6945   case ARM::VST4qWB_fixed_Asm_32: {
6946     MCInst TmpInst;
6947     unsigned Spacing;
6948     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6949     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6950     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6951     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6952     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6953     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6954     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6955                                             Spacing));
6956     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6957                                             Spacing * 2));
6958     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6959                                             Spacing * 3));
6960     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6961     TmpInst.addOperand(Inst.getOperand(4));
6962     Inst = TmpInst;
6963     return true;
6964   }
6965 
6966   case ARM::VST4dWB_register_Asm_8:
6967   case ARM::VST4dWB_register_Asm_16:
6968   case ARM::VST4dWB_register_Asm_32:
6969   case ARM::VST4qWB_register_Asm_8:
6970   case ARM::VST4qWB_register_Asm_16:
6971   case ARM::VST4qWB_register_Asm_32: {
6972     MCInst TmpInst;
6973     unsigned Spacing;
6974     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6975     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6976     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6977     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6978     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6979     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6980     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6981                                             Spacing));
6982     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6983                                             Spacing * 2));
6984     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6985                                             Spacing * 3));
6986     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6987     TmpInst.addOperand(Inst.getOperand(5));
6988     Inst = TmpInst;
6989     return true;
6990   }
6991 
6992   // Handle encoding choice for the shift-immediate instructions.
6993   case ARM::t2LSLri:
6994   case ARM::t2LSRri:
6995   case ARM::t2ASRri: {
6996     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6997         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6998         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6999         !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7000          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7001       unsigned NewOpc;
7002       switch (Inst.getOpcode()) {
7003       default: llvm_unreachable("unexpected opcode");
7004       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7005       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7006       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7007       }
7008       // The Thumb1 operands aren't in the same order. Awesome, eh?
7009       MCInst TmpInst;
7010       TmpInst.setOpcode(NewOpc);
7011       TmpInst.addOperand(Inst.getOperand(0));
7012       TmpInst.addOperand(Inst.getOperand(5));
7013       TmpInst.addOperand(Inst.getOperand(1));
7014       TmpInst.addOperand(Inst.getOperand(2));
7015       TmpInst.addOperand(Inst.getOperand(3));
7016       TmpInst.addOperand(Inst.getOperand(4));
7017       Inst = TmpInst;
7018       return true;
7019     }
7020     return false;
7021   }
7022 
7023   // Handle the Thumb2 mode MOV complex aliases.
7024   case ARM::t2MOVsr:
7025   case ARM::t2MOVSsr: {
7026     // Which instruction to expand to depends on the CCOut operand and
7027     // whether we're in an IT block if the register operands are low
7028     // registers.
7029     bool isNarrow = false;
7030     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7031         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7032         isARMLowRegister(Inst.getOperand(2).getReg()) &&
7033         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7034         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7035       isNarrow = true;
7036     MCInst TmpInst;
7037     unsigned newOpc;
7038     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7039     default: llvm_unreachable("unexpected opcode!");
7040     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7041     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7042     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7043     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7044     }
7045     TmpInst.setOpcode(newOpc);
7046     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7047     if (isNarrow)
7048       TmpInst.addOperand(MCOperand::CreateReg(
7049           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7050     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7051     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7052     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7053     TmpInst.addOperand(Inst.getOperand(5));
7054     if (!isNarrow)
7055       TmpInst.addOperand(MCOperand::CreateReg(
7056           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7057     Inst = TmpInst;
7058     return true;
7059   }
7060   case ARM::t2MOVsi:
7061   case ARM::t2MOVSsi: {
7062     // Which instruction to expand to depends on the CCOut operand and
7063     // whether we're in an IT block if the register operands are low
7064     // registers.
7065     bool isNarrow = false;
7066     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7067         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7068         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7069       isNarrow = true;
7070     MCInst TmpInst;
7071     unsigned newOpc;
7072     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7073     default: llvm_unreachable("unexpected opcode!");
7074     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7075     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7076     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7077     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7078     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7079     }
7080     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7081     if (Amount == 32) Amount = 0;
7082     TmpInst.setOpcode(newOpc);
7083     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7084     if (isNarrow)
7085       TmpInst.addOperand(MCOperand::CreateReg(
7086           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7087     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7088     if (newOpc != ARM::t2RRX)
7089       TmpInst.addOperand(MCOperand::CreateImm(Amount));
7090     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7091     TmpInst.addOperand(Inst.getOperand(4));
7092     if (!isNarrow)
7093       TmpInst.addOperand(MCOperand::CreateReg(
7094           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7095     Inst = TmpInst;
7096     return true;
7097   }
7098   // Handle the ARM mode MOV complex aliases.
7099   case ARM::ASRr:
7100   case ARM::LSRr:
7101   case ARM::LSLr:
7102   case ARM::RORr: {
7103     ARM_AM::ShiftOpc ShiftTy;
7104     switch(Inst.getOpcode()) {
7105     default: llvm_unreachable("unexpected opcode!");
7106     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7107     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7108     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7109     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7110     }
7111     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7112     MCInst TmpInst;
7113     TmpInst.setOpcode(ARM::MOVsr);
7114     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7115     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7116     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7117     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7118     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7119     TmpInst.addOperand(Inst.getOperand(4));
7120     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7121     Inst = TmpInst;
7122     return true;
7123   }
7124   case ARM::ASRi:
7125   case ARM::LSRi:
7126   case ARM::LSLi:
7127   case ARM::RORi: {
7128     ARM_AM::ShiftOpc ShiftTy;
7129     switch(Inst.getOpcode()) {
7130     default: llvm_unreachable("unexpected opcode!");
7131     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7132     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7133     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7134     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7135     }
7136     // A shift by zero is a plain MOVr, not a MOVsi.
7137     unsigned Amt = Inst.getOperand(2).getImm();
7138     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7139     // A shift by 32 should be encoded as 0 when permitted
7140     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7141       Amt = 0;
7142     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7143     MCInst TmpInst;
7144     TmpInst.setOpcode(Opc);
7145     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7146     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7147     if (Opc == ARM::MOVsi)
7148       TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7149     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7150     TmpInst.addOperand(Inst.getOperand(4));
7151     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7152     Inst = TmpInst;
7153     return true;
7154   }
7155   case ARM::RRXi: {
7156     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7157     MCInst TmpInst;
7158     TmpInst.setOpcode(ARM::MOVsi);
7159     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7160     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7161     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7162     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7163     TmpInst.addOperand(Inst.getOperand(3));
7164     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7165     Inst = TmpInst;
7166     return true;
7167   }
7168   case ARM::t2LDMIA_UPD: {
7169     // If this is a load of a single register, then we should use
7170     // a post-indexed LDR instruction instead, per the ARM ARM.
7171     if (Inst.getNumOperands() != 5)
7172       return false;
7173     MCInst TmpInst;
7174     TmpInst.setOpcode(ARM::t2LDR_POST);
7175     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7176     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7177     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7178     TmpInst.addOperand(MCOperand::CreateImm(4));
7179     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7180     TmpInst.addOperand(Inst.getOperand(3));
7181     Inst = TmpInst;
7182     return true;
7183   }
7184   case ARM::t2STMDB_UPD: {
7185     // If this is a store of a single register, then we should use
7186     // a pre-indexed STR instruction instead, per the ARM ARM.
7187     if (Inst.getNumOperands() != 5)
7188       return false;
7189     MCInst TmpInst;
7190     TmpInst.setOpcode(ARM::t2STR_PRE);
7191     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7192     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7193     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7194     TmpInst.addOperand(MCOperand::CreateImm(-4));
7195     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7196     TmpInst.addOperand(Inst.getOperand(3));
7197     Inst = TmpInst;
7198     return true;
7199   }
7200   case ARM::LDMIA_UPD:
7201     // If this is a load of a single register via a 'pop', then we should use
7202     // a post-indexed LDR instruction instead, per the ARM ARM.
7203     if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7204         Inst.getNumOperands() == 5) {
7205       MCInst TmpInst;
7206       TmpInst.setOpcode(ARM::LDR_POST_IMM);
7207       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7208       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7209       TmpInst.addOperand(Inst.getOperand(1)); // Rn
7210       TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7211       TmpInst.addOperand(MCOperand::CreateImm(4));
7212       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7213       TmpInst.addOperand(Inst.getOperand(3));
7214       Inst = TmpInst;
7215       return true;
7216     }
7217     break;
7218   case ARM::STMDB_UPD:
7219     // If this is a store of a single register via a 'push', then we should use
7220     // a pre-indexed STR instruction instead, per the ARM ARM.
7221     if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7222         Inst.getNumOperands() == 5) {
7223       MCInst TmpInst;
7224       TmpInst.setOpcode(ARM::STR_PRE_IMM);
7225       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7226       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7227       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7228       TmpInst.addOperand(MCOperand::CreateImm(-4));
7229       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7230       TmpInst.addOperand(Inst.getOperand(3));
7231       Inst = TmpInst;
7232     }
7233     break;
7234   case ARM::t2ADDri12:
7235     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7236     // mnemonic was used (not "addw"), encoding T3 is preferred.
7237     if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7238         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7239       break;
7240     Inst.setOpcode(ARM::t2ADDri);
7241     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7242     break;
7243   case ARM::t2SUBri12:
7244     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7245     // mnemonic was used (not "subw"), encoding T3 is preferred.
7246     if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7247         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7248       break;
7249     Inst.setOpcode(ARM::t2SUBri);
7250     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7251     break;
7252   case ARM::tADDi8:
7253     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7254     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7255     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7256     // to encoding T1 if <Rd> is omitted."
7257     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7258       Inst.setOpcode(ARM::tADDi3);
7259       return true;
7260     }
7261     break;
7262   case ARM::tSUBi8:
7263     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7264     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7265     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7266     // to encoding T1 if <Rd> is omitted."
7267     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7268       Inst.setOpcode(ARM::tSUBi3);
7269       return true;
7270     }
7271     break;
7272   case ARM::t2ADDri:
7273   case ARM::t2SUBri: {
7274     // If the destination and first source operand are the same, and
7275     // the flags are compatible with the current IT status, use encoding T2
7276     // instead of T3. For compatibility with the system 'as'. Make sure the
7277     // wide encoding wasn't explicit.
7278     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7279         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7280         (unsigned)Inst.getOperand(2).getImm() > 255 ||
7281         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7282         (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7283         (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7284          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7285       break;
7286     MCInst TmpInst;
7287     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7288                       ARM::tADDi8 : ARM::tSUBi8);
7289     TmpInst.addOperand(Inst.getOperand(0));
7290     TmpInst.addOperand(Inst.getOperand(5));
7291     TmpInst.addOperand(Inst.getOperand(0));
7292     TmpInst.addOperand(Inst.getOperand(2));
7293     TmpInst.addOperand(Inst.getOperand(3));
7294     TmpInst.addOperand(Inst.getOperand(4));
7295     Inst = TmpInst;
7296     return true;
7297   }
7298   case ARM::t2ADDrr: {
7299     // If the destination and first source operand are the same, and
7300     // there's no setting of the flags, use encoding T2 instead of T3.
7301     // Note that this is only for ADD, not SUB. This mirrors the system
7302     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7303     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7304         Inst.getOperand(5).getReg() != 0 ||
7305         (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7306          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7307       break;
7308     MCInst TmpInst;
7309     TmpInst.setOpcode(ARM::tADDhirr);
7310     TmpInst.addOperand(Inst.getOperand(0));
7311     TmpInst.addOperand(Inst.getOperand(0));
7312     TmpInst.addOperand(Inst.getOperand(2));
7313     TmpInst.addOperand(Inst.getOperand(3));
7314     TmpInst.addOperand(Inst.getOperand(4));
7315     Inst = TmpInst;
7316     return true;
7317   }
7318   case ARM::tADDrSP: {
7319     // If the non-SP source operand and the destination operand are not the
7320     // same, we need to use the 32-bit encoding if it's available.
7321     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7322       Inst.setOpcode(ARM::t2ADDrr);
7323       Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7324       return true;
7325     }
7326     break;
7327   }
7328   case ARM::tB:
7329     // A Thumb conditional branch outside of an IT block is a tBcc.
7330     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7331       Inst.setOpcode(ARM::tBcc);
7332       return true;
7333     }
7334     break;
7335   case ARM::t2B:
7336     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7337     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7338       Inst.setOpcode(ARM::t2Bcc);
7339       return true;
7340     }
7341     break;
7342   case ARM::t2Bcc:
7343     // If the conditional is AL or we're in an IT block, we really want t2B.
7344     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7345       Inst.setOpcode(ARM::t2B);
7346       return true;
7347     }
7348     break;
7349   case ARM::tBcc:
7350     // If the conditional is AL, we really want tB.
7351     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7352       Inst.setOpcode(ARM::tB);
7353       return true;
7354     }
7355     break;
7356   case ARM::tLDMIA: {
7357     // If the register list contains any high registers, or if the writeback
7358     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7359     // instead if we're in Thumb2. Otherwise, this should have generated
7360     // an error in validateInstruction().
7361     unsigned Rn = Inst.getOperand(0).getReg();
7362     bool hasWritebackToken =
7363       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7364        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7365     bool listContainsBase;
7366     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7367         (!listContainsBase && !hasWritebackToken) ||
7368         (listContainsBase && hasWritebackToken)) {
7369       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7370       assert (isThumbTwo());
7371       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7372       // If we're switching to the updating version, we need to insert
7373       // the writeback tied operand.
7374       if (hasWritebackToken)
7375         Inst.insert(Inst.begin(),
7376                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7377       return true;
7378     }
7379     break;
7380   }
7381   case ARM::tSTMIA_UPD: {
7382     // If the register list contains any high registers, we need to use
7383     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7384     // should have generated an error in validateInstruction().
7385     unsigned Rn = Inst.getOperand(0).getReg();
7386     bool listContainsBase;
7387     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7388       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7389       assert (isThumbTwo());
7390       Inst.setOpcode(ARM::t2STMIA_UPD);
7391       return true;
7392     }
7393     break;
7394   }
7395   case ARM::tPOP: {
7396     bool listContainsBase;
7397     // If the register list contains any high registers, we need to use
7398     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7399     // should have generated an error in validateInstruction().
7400     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7401       return false;
7402     assert (isThumbTwo());
7403     Inst.setOpcode(ARM::t2LDMIA_UPD);
7404     // Add the base register and writeback operands.
7405     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7406     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7407     return true;
7408   }
7409   case ARM::tPUSH: {
7410     bool listContainsBase;
7411     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7412       return false;
7413     assert (isThumbTwo());
7414     Inst.setOpcode(ARM::t2STMDB_UPD);
7415     // Add the base register and writeback operands.
7416     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7417     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7418     return true;
7419   }
7420   case ARM::t2MOVi: {
7421     // If we can use the 16-bit encoding and the user didn't explicitly
7422     // request the 32-bit variant, transform it here.
7423     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7424         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7425         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7426          Inst.getOperand(4).getReg() == ARM::CPSR) ||
7427         (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7428         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7429          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7430       // The operands aren't in the same order for tMOVi8...
7431       MCInst TmpInst;
7432       TmpInst.setOpcode(ARM::tMOVi8);
7433       TmpInst.addOperand(Inst.getOperand(0));
7434       TmpInst.addOperand(Inst.getOperand(4));
7435       TmpInst.addOperand(Inst.getOperand(1));
7436       TmpInst.addOperand(Inst.getOperand(2));
7437       TmpInst.addOperand(Inst.getOperand(3));
7438       Inst = TmpInst;
7439       return true;
7440     }
7441     break;
7442   }
7443   case ARM::t2MOVr: {
7444     // If we can use the 16-bit encoding and the user didn't explicitly
7445     // request the 32-bit variant, transform it here.
7446     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7447         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7448         Inst.getOperand(2).getImm() == ARMCC::AL &&
7449         Inst.getOperand(4).getReg() == ARM::CPSR &&
7450         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7451          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7452       // The operands aren't the same for tMOV[S]r... (no cc_out)
7453       MCInst TmpInst;
7454       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7455       TmpInst.addOperand(Inst.getOperand(0));
7456       TmpInst.addOperand(Inst.getOperand(1));
7457       TmpInst.addOperand(Inst.getOperand(2));
7458       TmpInst.addOperand(Inst.getOperand(3));
7459       Inst = TmpInst;
7460       return true;
7461     }
7462     break;
7463   }
7464   case ARM::t2SXTH:
7465   case ARM::t2SXTB:
7466   case ARM::t2UXTH:
7467   case ARM::t2UXTB: {
7468     // If we can use the 16-bit encoding and the user didn't explicitly
7469     // request the 32-bit variant, transform it here.
7470     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7471         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7472         Inst.getOperand(2).getImm() == 0 &&
7473         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7474          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7475       unsigned NewOpc;
7476       switch (Inst.getOpcode()) {
7477       default: llvm_unreachable("Illegal opcode!");
7478       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7479       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7480       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7481       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7482       }
7483       // The operands aren't the same for thumb1 (no rotate operand).
7484       MCInst TmpInst;
7485       TmpInst.setOpcode(NewOpc);
7486       TmpInst.addOperand(Inst.getOperand(0));
7487       TmpInst.addOperand(Inst.getOperand(1));
7488       TmpInst.addOperand(Inst.getOperand(3));
7489       TmpInst.addOperand(Inst.getOperand(4));
7490       Inst = TmpInst;
7491       return true;
7492     }
7493     break;
7494   }
7495   case ARM::MOVsi: {
7496     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7497     // rrx shifts and asr/lsr of #32 is encoded as 0
7498     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7499       return false;
7500     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7501       // Shifting by zero is accepted as a vanilla 'MOVr'
7502       MCInst TmpInst;
7503       TmpInst.setOpcode(ARM::MOVr);
7504       TmpInst.addOperand(Inst.getOperand(0));
7505       TmpInst.addOperand(Inst.getOperand(1));
7506       TmpInst.addOperand(Inst.getOperand(3));
7507       TmpInst.addOperand(Inst.getOperand(4));
7508       TmpInst.addOperand(Inst.getOperand(5));
7509       Inst = TmpInst;
7510       return true;
7511     }
7512     return false;
7513   }
7514   case ARM::ANDrsi:
7515   case ARM::ORRrsi:
7516   case ARM::EORrsi:
7517   case ARM::BICrsi:
7518   case ARM::SUBrsi:
7519   case ARM::ADDrsi: {
7520     unsigned newOpc;
7521     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7522     if (SOpc == ARM_AM::rrx) return false;
7523     switch (Inst.getOpcode()) {
7524     default: llvm_unreachable("unexpected opcode!");
7525     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7526     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7527     case ARM::EORrsi: newOpc = ARM::EORrr; break;
7528     case ARM::BICrsi: newOpc = ARM::BICrr; break;
7529     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7530     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7531     }
7532     // If the shift is by zero, use the non-shifted instruction definition.
7533     // The exception is for right shifts, where 0 == 32
7534     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7535         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7536       MCInst TmpInst;
7537       TmpInst.setOpcode(newOpc);
7538       TmpInst.addOperand(Inst.getOperand(0));
7539       TmpInst.addOperand(Inst.getOperand(1));
7540       TmpInst.addOperand(Inst.getOperand(2));
7541       TmpInst.addOperand(Inst.getOperand(4));
7542       TmpInst.addOperand(Inst.getOperand(5));
7543       TmpInst.addOperand(Inst.getOperand(6));
7544       Inst = TmpInst;
7545       return true;
7546     }
7547     return false;
7548   }
7549   case ARM::ITasm:
7550   case ARM::t2IT: {
7551     // The mask bits for all but the first condition are represented as
7552     // the low bit of the condition code value implies 't'. We currently
7553     // always have 1 implies 't', so XOR toggle the bits if the low bit
7554     // of the condition code is zero.
7555     MCOperand &MO = Inst.getOperand(1);
7556     unsigned Mask = MO.getImm();
7557     unsigned OrigMask = Mask;
7558     unsigned TZ = countTrailingZeros(Mask);
7559     if ((Inst.getOperand(0).getImm() & 1) == 0) {
7560       assert(Mask && TZ <= 3 && "illegal IT mask value!");
7561       Mask ^= (0xE << TZ) & 0xF;
7562     }
7563     MO.setImm(Mask);
7564 
7565     // Set up the IT block state according to the IT instruction we just
7566     // matched.
7567     assert(!inITBlock() && "nested IT blocks?!");
7568     ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7569     ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7570     ITState.CurPosition = 0;
7571     ITState.FirstCond = true;
7572     break;
7573   }
7574   case ARM::t2LSLrr:
7575   case ARM::t2LSRrr:
7576   case ARM::t2ASRrr:
7577   case ARM::t2SBCrr:
7578   case ARM::t2RORrr:
7579   case ARM::t2BICrr:
7580   {
7581     // Assemblers should use the narrow encodings of these instructions when permissible.
7582     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7583          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7584         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7585         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7586          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7587         (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7588          !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7589       unsigned NewOpc;
7590       switch (Inst.getOpcode()) {
7591         default: llvm_unreachable("unexpected opcode");
7592         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7593         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7594         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7595         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7596         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7597         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7598       }
7599       MCInst TmpInst;
7600       TmpInst.setOpcode(NewOpc);
7601       TmpInst.addOperand(Inst.getOperand(0));
7602       TmpInst.addOperand(Inst.getOperand(5));
7603       TmpInst.addOperand(Inst.getOperand(1));
7604       TmpInst.addOperand(Inst.getOperand(2));
7605       TmpInst.addOperand(Inst.getOperand(3));
7606       TmpInst.addOperand(Inst.getOperand(4));
7607       Inst = TmpInst;
7608       return true;
7609     }
7610     return false;
7611   }
7612   case ARM::t2ANDrr:
7613   case ARM::t2EORrr:
7614   case ARM::t2ADCrr:
7615   case ARM::t2ORRrr:
7616   {
7617     // Assemblers should use the narrow encodings of these instructions when permissible.
7618     // These instructions are special in that they are commutable, so shorter encodings
7619     // are available more often.
7620     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7621          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7622         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7623          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7624         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7625          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7626         (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7627          !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7628       unsigned NewOpc;
7629       switch (Inst.getOpcode()) {
7630         default: llvm_unreachable("unexpected opcode");
7631         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7632         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7633         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7634         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7635       }
7636       MCInst TmpInst;
7637       TmpInst.setOpcode(NewOpc);
7638       TmpInst.addOperand(Inst.getOperand(0));
7639       TmpInst.addOperand(Inst.getOperand(5));
7640       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7641         TmpInst.addOperand(Inst.getOperand(1));
7642         TmpInst.addOperand(Inst.getOperand(2));
7643       } else {
7644         TmpInst.addOperand(Inst.getOperand(2));
7645         TmpInst.addOperand(Inst.getOperand(1));
7646       }
7647       TmpInst.addOperand(Inst.getOperand(3));
7648       TmpInst.addOperand(Inst.getOperand(4));
7649       Inst = TmpInst;
7650       return true;
7651     }
7652     return false;
7653   }
7654   }
7655   return false;
7656 }
7657 
7658 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7659   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7660   // suffix depending on whether they're in an IT block or not.
7661   unsigned Opc = Inst.getOpcode();
7662   const MCInstrDesc &MCID = getInstDesc(Opc);
7663   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7664     assert(MCID.hasOptionalDef() &&
7665            "optionally flag setting instruction missing optional def operand");
7666     assert(MCID.NumOperands == Inst.getNumOperands() &&
7667            "operand count mismatch!");
7668     // Find the optional-def operand (cc_out).
7669     unsigned OpNo;
7670     for (OpNo = 0;
7671          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7672          ++OpNo)
7673       ;
7674     // If we're parsing Thumb1, reject it completely.
7675     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7676       return Match_MnemonicFail;
7677     // If we're parsing Thumb2, which form is legal depends on whether we're
7678     // in an IT block.
7679     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7680         !inITBlock())
7681       return Match_RequiresITBlock;
7682     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7683         inITBlock())
7684       return Match_RequiresNotITBlock;
7685   }
7686   // Some high-register supporting Thumb1 encodings only allow both registers
7687   // to be from r0-r7 when in Thumb2.
7688   else if (Opc == ARM::tADDhirr && isThumbOne() &&
7689            isARMLowRegister(Inst.getOperand(1).getReg()) &&
7690            isARMLowRegister(Inst.getOperand(2).getReg()))
7691     return Match_RequiresThumb2;
7692   // Others only require ARMv6 or later.
7693   else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7694            isARMLowRegister(Inst.getOperand(0).getReg()) &&
7695            isARMLowRegister(Inst.getOperand(1).getReg()))
7696     return Match_RequiresV6;
7697   return Match_Success;
7698 }
7699 
7700 static const char *getSubtargetFeatureName(unsigned Val);
7701 bool ARMAsmParser::
7702 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7703                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7704                         MCStreamer &Out, unsigned &ErrorInfo,
7705                         bool MatchingInlineAsm) {
7706   MCInst Inst;
7707   unsigned MatchResult;
7708 
7709   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7710                                      MatchingInlineAsm);
7711   switch (MatchResult) {
7712   default: break;
7713   case Match_Success:
7714     // Context sensitive operand constraints aren't handled by the matcher,
7715     // so check them here.
7716     if (validateInstruction(Inst, Operands)) {
7717       // Still progress the IT block, otherwise one wrong condition causes
7718       // nasty cascading errors.
7719       forwardITPosition();
7720       return true;
7721     }
7722 
7723     // Some instructions need post-processing to, for example, tweak which
7724     // encoding is selected. Loop on it while changes happen so the
7725     // individual transformations can chain off each other. E.g.,
7726     // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7727     while (processInstruction(Inst, Operands))
7728       ;
7729 
7730     // Only move forward at the very end so that everything in validate
7731     // and process gets a consistent answer about whether we're in an IT
7732     // block.
7733     forwardITPosition();
7734 
7735     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7736     // doesn't actually encode.
7737     if (Inst.getOpcode() == ARM::ITasm)
7738       return false;
7739 
7740     Inst.setLoc(IDLoc);
7741     Out.EmitInstruction(Inst);
7742     return false;
7743   case Match_MissingFeature: {
7744     assert(ErrorInfo && "Unknown missing feature!");
7745     // Special case the error message for the very common case where only
7746     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7747     std::string Msg = "instruction requires:";
7748     unsigned Mask = 1;
7749     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7750       if (ErrorInfo & Mask) {
7751         Msg += " ";
7752         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7753       }
7754       Mask <<= 1;
7755     }
7756     return Error(IDLoc, Msg);
7757   }
7758   case Match_InvalidOperand: {
7759     SMLoc ErrorLoc = IDLoc;
7760     if (ErrorInfo != ~0U) {
7761       if (ErrorInfo >= Operands.size())
7762         return Error(IDLoc, "too few operands for instruction");
7763 
7764       ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7765       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7766     }
7767 
7768     return Error(ErrorLoc, "invalid operand for instruction");
7769   }
7770   case Match_MnemonicFail:
7771     return Error(IDLoc, "invalid instruction",
7772                  ((ARMOperand*)Operands[0])->getLocRange());
7773   case Match_RequiresNotITBlock:
7774     return Error(IDLoc, "flag setting instruction only valid outside IT block");
7775   case Match_RequiresITBlock:
7776     return Error(IDLoc, "instruction only valid inside IT block");
7777   case Match_RequiresV6:
7778     return Error(IDLoc, "instruction variant requires ARMv6 or later");
7779   case Match_RequiresThumb2:
7780     return Error(IDLoc, "instruction variant requires Thumb2");
7781   case Match_ImmRange0_4: {
7782     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7783     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7784     return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7785   }
7786   case Match_ImmRange0_15: {
7787     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7788     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7789     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7790   }
7791   }
7792 
7793   llvm_unreachable("Implement any new match types added!");
7794 }
7795 
7796 /// parseDirective parses the arm specific directives
7797 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7798   StringRef IDVal = DirectiveID.getIdentifier();
7799   if (IDVal == ".word")
7800     return parseDirectiveWord(4, DirectiveID.getLoc());
7801   else if (IDVal == ".thumb")
7802     return parseDirectiveThumb(DirectiveID.getLoc());
7803   else if (IDVal == ".arm")
7804     return parseDirectiveARM(DirectiveID.getLoc());
7805   else if (IDVal == ".thumb_func")
7806     return parseDirectiveThumbFunc(DirectiveID.getLoc());
7807   else if (IDVal == ".code")
7808     return parseDirectiveCode(DirectiveID.getLoc());
7809   else if (IDVal == ".syntax")
7810     return parseDirectiveSyntax(DirectiveID.getLoc());
7811   else if (IDVal == ".unreq")
7812     return parseDirectiveUnreq(DirectiveID.getLoc());
7813   else if (IDVal == ".arch")
7814     return parseDirectiveArch(DirectiveID.getLoc());
7815   else if (IDVal == ".eabi_attribute")
7816     return parseDirectiveEabiAttr(DirectiveID.getLoc());
7817   else if (IDVal == ".fnstart")
7818     return parseDirectiveFnStart(DirectiveID.getLoc());
7819   else if (IDVal == ".fnend")
7820     return parseDirectiveFnEnd(DirectiveID.getLoc());
7821   else if (IDVal == ".cantunwind")
7822     return parseDirectiveCantUnwind(DirectiveID.getLoc());
7823   else if (IDVal == ".personality")
7824     return parseDirectivePersonality(DirectiveID.getLoc());
7825   else if (IDVal == ".handlerdata")
7826     return parseDirectiveHandlerData(DirectiveID.getLoc());
7827   else if (IDVal == ".setfp")
7828     return parseDirectiveSetFP(DirectiveID.getLoc());
7829   else if (IDVal == ".pad")
7830     return parseDirectivePad(DirectiveID.getLoc());
7831   else if (IDVal == ".save")
7832     return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7833   else if (IDVal == ".vsave")
7834     return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7835   return true;
7836 }
7837 
7838 /// parseDirectiveWord
7839 ///  ::= .word [ expression (, expression)* ]
7840 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7841   if (getLexer().isNot(AsmToken::EndOfStatement)) {
7842     for (;;) {
7843       const MCExpr *Value;
7844       if (getParser().parseExpression(Value))
7845         return true;
7846 
7847       getParser().getStreamer().EmitValue(Value, Size);
7848 
7849       if (getLexer().is(AsmToken::EndOfStatement))
7850         break;
7851 
7852       // FIXME: Improve diagnostic.
7853       if (getLexer().isNot(AsmToken::Comma))
7854         return Error(L, "unexpected token in directive");
7855       Parser.Lex();
7856     }
7857   }
7858 
7859   Parser.Lex();
7860   return false;
7861 }
7862 
7863 /// parseDirectiveThumb
7864 ///  ::= .thumb
7865 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7866   if (getLexer().isNot(AsmToken::EndOfStatement))
7867     return Error(L, "unexpected token in directive");
7868   Parser.Lex();
7869 
7870   if (!hasThumb())
7871     return Error(L, "target does not support Thumb mode");
7872 
7873   if (!isThumb())
7874     SwitchMode();
7875   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7876   return false;
7877 }
7878 
7879 /// parseDirectiveARM
7880 ///  ::= .arm
7881 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7882   if (getLexer().isNot(AsmToken::EndOfStatement))
7883     return Error(L, "unexpected token in directive");
7884   Parser.Lex();
7885 
7886   if (!hasARM())
7887     return Error(L, "target does not support ARM mode");
7888 
7889   if (isThumb())
7890     SwitchMode();
7891   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7892   return false;
7893 }
7894 
7895 /// parseDirectiveThumbFunc
7896 ///  ::= .thumbfunc symbol_name
7897 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7898   const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7899   bool isMachO = MAI->hasSubsectionsViaSymbols();
7900   StringRef Name;
7901   bool needFuncName = true;
7902 
7903   // Darwin asm has (optionally) function name after .thumb_func direction
7904   // ELF doesn't
7905   if (isMachO) {
7906     const AsmToken &Tok = Parser.getTok();
7907     if (Tok.isNot(AsmToken::EndOfStatement)) {
7908       if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7909         return Error(L, "unexpected token in .thumb_func directive");
7910       Name = Tok.getIdentifier();
7911       Parser.Lex(); // Consume the identifier token.
7912       needFuncName = false;
7913     }
7914   }
7915 
7916   if (getLexer().isNot(AsmToken::EndOfStatement))
7917     return Error(L, "unexpected token in directive");
7918 
7919   // Eat the end of statement and any blank lines that follow.
7920   while (getLexer().is(AsmToken::EndOfStatement))
7921     Parser.Lex();
7922 
7923   // FIXME: assuming function name will be the line following .thumb_func
7924   // We really should be checking the next symbol definition even if there's
7925   // stuff in between.
7926   if (needFuncName) {
7927     Name = Parser.getTok().getIdentifier();
7928   }
7929 
7930   // Mark symbol as a thumb symbol.
7931   MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7932   getParser().getStreamer().EmitThumbFunc(Func);
7933   return false;
7934 }
7935 
7936 /// parseDirectiveSyntax
7937 ///  ::= .syntax unified | divided
7938 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7939   const AsmToken &Tok = Parser.getTok();
7940   if (Tok.isNot(AsmToken::Identifier))
7941     return Error(L, "unexpected token in .syntax directive");
7942   StringRef Mode = Tok.getString();
7943   if (Mode == "unified" || Mode == "UNIFIED")
7944     Parser.Lex();
7945   else if (Mode == "divided" || Mode == "DIVIDED")
7946     return Error(L, "'.syntax divided' arm asssembly not supported");
7947   else
7948     return Error(L, "unrecognized syntax mode in .syntax directive");
7949 
7950   if (getLexer().isNot(AsmToken::EndOfStatement))
7951     return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7952   Parser.Lex();
7953 
7954   // TODO tell the MC streamer the mode
7955   // getParser().getStreamer().Emit???();
7956   return false;
7957 }
7958 
7959 /// parseDirectiveCode
7960 ///  ::= .code 16 | 32
7961 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7962   const AsmToken &Tok = Parser.getTok();
7963   if (Tok.isNot(AsmToken::Integer))
7964     return Error(L, "unexpected token in .code directive");
7965   int64_t Val = Parser.getTok().getIntVal();
7966   if (Val == 16)
7967     Parser.Lex();
7968   else if (Val == 32)
7969     Parser.Lex();
7970   else
7971     return Error(L, "invalid operand to .code directive");
7972 
7973   if (getLexer().isNot(AsmToken::EndOfStatement))
7974     return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7975   Parser.Lex();
7976 
7977   if (Val == 16) {
7978     if (!hasThumb())
7979       return Error(L, "target does not support Thumb mode");
7980 
7981     if (!isThumb())
7982       SwitchMode();
7983     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7984   } else {
7985     if (!hasARM())
7986       return Error(L, "target does not support ARM mode");
7987 
7988     if (isThumb())
7989       SwitchMode();
7990     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7991   }
7992 
7993   return false;
7994 }
7995 
7996 /// parseDirectiveReq
7997 ///  ::= name .req registername
7998 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7999   Parser.Lex(); // Eat the '.req' token.
8000   unsigned Reg;
8001   SMLoc SRegLoc, ERegLoc;
8002   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8003     Parser.eatToEndOfStatement();
8004     return Error(SRegLoc, "register name expected");
8005   }
8006 
8007   // Shouldn't be anything else.
8008   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8009     Parser.eatToEndOfStatement();
8010     return Error(Parser.getTok().getLoc(),
8011                  "unexpected input in .req directive.");
8012   }
8013 
8014   Parser.Lex(); // Consume the EndOfStatement
8015 
8016   if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
8017     return Error(SRegLoc, "redefinition of '" + Name +
8018                           "' does not match original.");
8019 
8020   return false;
8021 }
8022 
8023 /// parseDirectiveUneq
8024 ///  ::= .unreq registername
8025 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8026   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8027     Parser.eatToEndOfStatement();
8028     return Error(L, "unexpected input in .unreq directive.");
8029   }
8030   RegisterReqs.erase(Parser.getTok().getIdentifier());
8031   Parser.Lex(); // Eat the identifier.
8032   return false;
8033 }
8034 
8035 /// parseDirectiveArch
8036 ///  ::= .arch token
8037 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8038   return true;
8039 }
8040 
8041 /// parseDirectiveEabiAttr
8042 ///  ::= .eabi_attribute int, int
8043 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8044   return true;
8045 }
8046 
8047 /// parseDirectiveFnStart
8048 ///  ::= .fnstart
8049 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8050   if (FnStartLoc.isValid()) {
8051     Error(L, ".fnstart starts before the end of previous one");
8052     Error(FnStartLoc, "previous .fnstart starts here");
8053     return true;
8054   }
8055 
8056   FnStartLoc = L;
8057   getParser().getStreamer().EmitFnStart();
8058   return false;
8059 }
8060 
8061 /// parseDirectiveFnEnd
8062 ///  ::= .fnend
8063 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8064   // Check the ordering of unwind directives
8065   if (!FnStartLoc.isValid())
8066     return Error(L, ".fnstart must precede .fnend directive");
8067 
8068   // Reset the unwind directives parser state
8069   resetUnwindDirectiveParserState();
8070 
8071   getParser().getStreamer().EmitFnEnd();
8072   return false;
8073 }
8074 
8075 /// parseDirectiveCantUnwind
8076 ///  ::= .cantunwind
8077 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8078   // Check the ordering of unwind directives
8079   CantUnwindLoc = L;
8080   if (!FnStartLoc.isValid())
8081     return Error(L, ".fnstart must precede .cantunwind directive");
8082   if (HandlerDataLoc.isValid()) {
8083     Error(L, ".cantunwind can't be used with .handlerdata directive");
8084     Error(HandlerDataLoc, ".handlerdata was specified here");
8085     return true;
8086   }
8087   if (PersonalityLoc.isValid()) {
8088     Error(L, ".cantunwind can't be used with .personality directive");
8089     Error(PersonalityLoc, ".personality was specified here");
8090     return true;
8091   }
8092 
8093   getParser().getStreamer().EmitCantUnwind();
8094   return false;
8095 }
8096 
8097 /// parseDirectivePersonality
8098 ///  ::= .personality name
8099 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8100   // Check the ordering of unwind directives
8101   PersonalityLoc = L;
8102   if (!FnStartLoc.isValid())
8103     return Error(L, ".fnstart must precede .personality directive");
8104   if (CantUnwindLoc.isValid()) {
8105     Error(L, ".personality can't be used with .cantunwind directive");
8106     Error(CantUnwindLoc, ".cantunwind was specified here");
8107     return true;
8108   }
8109   if (HandlerDataLoc.isValid()) {
8110     Error(L, ".personality must precede .handlerdata directive");
8111     Error(HandlerDataLoc, ".handlerdata was specified here");
8112     return true;
8113   }
8114 
8115   // Parse the name of the personality routine
8116   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8117     Parser.eatToEndOfStatement();
8118     return Error(L, "unexpected input in .personality directive.");
8119   }
8120   StringRef Name(Parser.getTok().getIdentifier());
8121   Parser.Lex();
8122 
8123   MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8124   getParser().getStreamer().EmitPersonality(PR);
8125   return false;
8126 }
8127 
8128 /// parseDirectiveHandlerData
8129 ///  ::= .handlerdata
8130 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8131   // Check the ordering of unwind directives
8132   HandlerDataLoc = L;
8133   if (!FnStartLoc.isValid())
8134     return Error(L, ".fnstart must precede .personality directive");
8135   if (CantUnwindLoc.isValid()) {
8136     Error(L, ".handlerdata can't be used with .cantunwind directive");
8137     Error(CantUnwindLoc, ".cantunwind was specified here");
8138     return true;
8139   }
8140 
8141   getParser().getStreamer().EmitHandlerData();
8142   return false;
8143 }
8144 
8145 /// parseDirectiveSetFP
8146 ///  ::= .setfp fpreg, spreg [, offset]
8147 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8148   // Check the ordering of unwind directives
8149   if (!FnStartLoc.isValid())
8150     return Error(L, ".fnstart must precede .setfp directive");
8151   if (HandlerDataLoc.isValid())
8152     return Error(L, ".setfp must precede .handlerdata directive");
8153 
8154   // Parse fpreg
8155   SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8156   int NewFPReg = tryParseRegister();
8157   if (NewFPReg == -1)
8158     return Error(NewFPRegLoc, "frame pointer register expected");
8159 
8160   // Consume comma
8161   if (!Parser.getTok().is(AsmToken::Comma))
8162     return Error(Parser.getTok().getLoc(), "comma expected");
8163   Parser.Lex(); // skip comma
8164 
8165   // Parse spreg
8166   SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8167   int NewSPReg = tryParseRegister();
8168   if (NewSPReg == -1)
8169     return Error(NewSPRegLoc, "stack pointer register expected");
8170 
8171   if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8172     return Error(NewSPRegLoc,
8173                  "register should be either $sp or the latest fp register");
8174 
8175   // Update the frame pointer register
8176   FPReg = NewFPReg;
8177 
8178   // Parse offset
8179   int64_t Offset = 0;
8180   if (Parser.getTok().is(AsmToken::Comma)) {
8181     Parser.Lex(); // skip comma
8182 
8183     if (Parser.getTok().isNot(AsmToken::Hash) &&
8184         Parser.getTok().isNot(AsmToken::Dollar)) {
8185       return Error(Parser.getTok().getLoc(), "'#' expected");
8186     }
8187     Parser.Lex(); // skip hash token.
8188 
8189     const MCExpr *OffsetExpr;
8190     SMLoc ExLoc = Parser.getTok().getLoc();
8191     SMLoc EndLoc;
8192     if (getParser().parseExpression(OffsetExpr, EndLoc))
8193       return Error(ExLoc, "malformed setfp offset");
8194     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8195     if (!CE)
8196       return Error(ExLoc, "setfp offset must be an immediate");
8197 
8198     Offset = CE->getValue();
8199   }
8200 
8201   getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8202                                       static_cast<unsigned>(NewSPReg),
8203                                       Offset);
8204   return false;
8205 }
8206 
8207 /// parseDirective
8208 ///  ::= .pad offset
8209 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8210   // Check the ordering of unwind directives
8211   if (!FnStartLoc.isValid())
8212     return Error(L, ".fnstart must precede .pad directive");
8213   if (HandlerDataLoc.isValid())
8214     return Error(L, ".pad must precede .handlerdata directive");
8215 
8216   // Parse the offset
8217   if (Parser.getTok().isNot(AsmToken::Hash) &&
8218       Parser.getTok().isNot(AsmToken::Dollar)) {
8219     return Error(Parser.getTok().getLoc(), "'#' expected");
8220   }
8221   Parser.Lex(); // skip hash token.
8222 
8223   const MCExpr *OffsetExpr;
8224   SMLoc ExLoc = Parser.getTok().getLoc();
8225   SMLoc EndLoc;
8226   if (getParser().parseExpression(OffsetExpr, EndLoc))
8227     return Error(ExLoc, "malformed pad offset");
8228   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8229   if (!CE)
8230     return Error(ExLoc, "pad offset must be an immediate");
8231 
8232   getParser().getStreamer().EmitPad(CE->getValue());
8233   return false;
8234 }
8235 
8236 /// parseDirectiveRegSave
8237 ///  ::= .save  { registers }
8238 ///  ::= .vsave { registers }
8239 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8240   // Check the ordering of unwind directives
8241   if (!FnStartLoc.isValid())
8242     return Error(L, ".fnstart must precede .save or .vsave directives");
8243   if (HandlerDataLoc.isValid())
8244     return Error(L, ".save or .vsave must precede .handlerdata directive");
8245 
8246   // Parse the register list
8247   SmallVector<MCParsedAsmOperand*, 1> Operands;
8248   if (parseRegisterList(Operands))
8249     return true;
8250   ARMOperand *Op = (ARMOperand*)Operands[0];
8251   if (!IsVector && !Op->isRegList())
8252     return Error(L, ".save expects GPR registers");
8253   if (IsVector && !Op->isDPRRegList())
8254     return Error(L, ".vsave expects DPR registers");
8255 
8256   getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8257   return false;
8258 }
8259 
8260 /// Force static initialization.
8261 extern "C" void LLVMInitializeARMAsmParser() {
8262   RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8263   RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8264 }
8265 
8266 #define GET_REGISTER_MATCHER
8267 #define GET_SUBTARGET_FEATURE_NAME
8268 #define GET_MATCHER_IMPLEMENTATION
8269 #include "ARMGenAsmMatcher.inc"
8270 
8271 // Define this matcher function after the auto-generated include so we
8272 // have the match class enum definitions.
8273 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8274                                                   unsigned Kind) {
8275   ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8276   // If the kind is a token for a literal immediate, check if our asm
8277   // operand matches. This is for InstAliases which have a fixed-value
8278   // immediate in the syntax.
8279   if (Kind == MCK__35_0 && Op->isImm()) {
8280     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8281     if (!CE)
8282       return Match_InvalidOperand;
8283     if (CE->getValue() == 0)
8284       return Match_Success;
8285   }
8286   return Match_InvalidOperand;
8287 }
8288