1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMBaseInfo.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMMCExpr.h" 13 #include "llvm/MC/MCParser/MCAsmLexer.h" 14 #include "llvm/MC/MCParser/MCAsmParser.h" 15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCStreamer.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCInstrDesc.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/MC/MCTargetAsmParser.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/SourceMgr.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/ADT/BitVector.h" 30 #include "llvm/ADT/OwningPtr.h" 31 #include "llvm/ADT/STLExtras.h" 32 #include "llvm/ADT/SmallVector.h" 33 #include "llvm/ADT/StringSwitch.h" 34 #include "llvm/ADT/Twine.h" 35 36 using namespace llvm; 37 38 namespace { 39 40 class ARMOperand; 41 42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 43 44 class ARMAsmParser : public MCTargetAsmParser { 45 MCSubtargetInfo &STI; 46 MCAsmParser &Parser; 47 48 struct { 49 ARMCC::CondCodes Cond; // Condition for IT block. 50 unsigned Mask:4; // Condition mask for instructions. 51 // Starting at first 1 (from lsb). 52 // '1' condition as indicated in IT. 53 // '0' inverse of condition (else). 54 // Count of instructions in IT block is 55 // 4 - trailingzeroes(mask) 56 57 bool FirstCond; // Explicit flag for when we're parsing the 58 // First instruction in the IT block. It's 59 // implied in the mask, so needs special 60 // handling. 61 62 unsigned CurPosition; // Current position in parsing of IT 63 // block. In range [0,3]. Initialized 64 // according to count of instructions in block. 65 // ~0U if no active IT block. 66 } ITState; 67 bool inITBlock() { return ITState.CurPosition != ~0U;} 68 void forwardITPosition() { 69 if (!inITBlock()) return; 70 // Move to the next instruction in the IT block, if there is one. If not, 71 // mark the block as done. 72 unsigned TZ = CountTrailingZeros_32(ITState.Mask); 73 if (++ITState.CurPosition == 5 - TZ) 74 ITState.CurPosition = ~0U; // Done with the IT block after this. 75 } 76 77 78 MCAsmParser &getParser() const { return Parser; } 79 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 80 81 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 82 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 83 84 int tryParseRegister(); 85 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 86 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 87 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 88 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 89 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 90 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 91 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 92 unsigned &ShiftAmount); 93 bool parseDirectiveWord(unsigned Size, SMLoc L); 94 bool parseDirectiveThumb(SMLoc L); 95 bool parseDirectiveThumbFunc(SMLoc L); 96 bool parseDirectiveCode(SMLoc L); 97 bool parseDirectiveSyntax(SMLoc L); 98 99 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 100 bool &CarrySetting, unsigned &ProcessorIMod, 101 StringRef &ITMask); 102 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 103 bool &CanAcceptPredicationCode); 104 105 bool isThumb() const { 106 // FIXME: Can tablegen auto-generate this? 107 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 108 } 109 bool isThumbOne() const { 110 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 111 } 112 bool isThumbTwo() const { 113 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 114 } 115 bool hasV6Ops() const { 116 return STI.getFeatureBits() & ARM::HasV6Ops; 117 } 118 bool hasV7Ops() const { 119 return STI.getFeatureBits() & ARM::HasV7Ops; 120 } 121 void SwitchMode() { 122 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 123 setAvailableFeatures(FB); 124 } 125 bool isMClass() const { 126 return STI.getFeatureBits() & ARM::FeatureMClass; 127 } 128 129 /// @name Auto-generated Match Functions 130 /// { 131 132 #define GET_ASSEMBLER_HEADER 133 #include "ARMGenAsmMatcher.inc" 134 135 /// } 136 137 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 138 OperandMatchResultTy parseCoprocNumOperand( 139 SmallVectorImpl<MCParsedAsmOperand*>&); 140 OperandMatchResultTy parseCoprocRegOperand( 141 SmallVectorImpl<MCParsedAsmOperand*>&); 142 OperandMatchResultTy parseCoprocOptionOperand( 143 SmallVectorImpl<MCParsedAsmOperand*>&); 144 OperandMatchResultTy parseMemBarrierOptOperand( 145 SmallVectorImpl<MCParsedAsmOperand*>&); 146 OperandMatchResultTy parseProcIFlagsOperand( 147 SmallVectorImpl<MCParsedAsmOperand*>&); 148 OperandMatchResultTy parseMSRMaskOperand( 149 SmallVectorImpl<MCParsedAsmOperand*>&); 150 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 151 StringRef Op, int Low, int High); 152 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 153 return parsePKHImm(O, "lsl", 0, 31); 154 } 155 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 156 return parsePKHImm(O, "asr", 1, 32); 157 } 158 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 159 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 160 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 161 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 162 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 163 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 164 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 165 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 166 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); 167 168 // Asm Match Converter Methods 169 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 170 const SmallVectorImpl<MCParsedAsmOperand*> &); 171 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 172 const SmallVectorImpl<MCParsedAsmOperand*> &); 173 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 174 const SmallVectorImpl<MCParsedAsmOperand*> &); 175 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 176 const SmallVectorImpl<MCParsedAsmOperand*> &); 177 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 178 const SmallVectorImpl<MCParsedAsmOperand*> &); 179 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 180 const SmallVectorImpl<MCParsedAsmOperand*> &); 181 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 182 const SmallVectorImpl<MCParsedAsmOperand*> &); 183 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 184 const SmallVectorImpl<MCParsedAsmOperand*> &); 185 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 186 const SmallVectorImpl<MCParsedAsmOperand*> &); 187 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 188 const SmallVectorImpl<MCParsedAsmOperand*> &); 189 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 190 const SmallVectorImpl<MCParsedAsmOperand*> &); 191 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 192 const SmallVectorImpl<MCParsedAsmOperand*> &); 193 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 194 const SmallVectorImpl<MCParsedAsmOperand*> &); 195 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 196 const SmallVectorImpl<MCParsedAsmOperand*> &); 197 bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 198 const SmallVectorImpl<MCParsedAsmOperand*> &); 199 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 200 const SmallVectorImpl<MCParsedAsmOperand*> &); 201 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 202 const SmallVectorImpl<MCParsedAsmOperand*> &); 203 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 204 const SmallVectorImpl<MCParsedAsmOperand*> &); 205 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 206 const SmallVectorImpl<MCParsedAsmOperand*> &); 207 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 208 const SmallVectorImpl<MCParsedAsmOperand*> &); 209 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 210 const SmallVectorImpl<MCParsedAsmOperand*> &); 211 212 bool validateInstruction(MCInst &Inst, 213 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 214 bool processInstruction(MCInst &Inst, 215 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 216 bool shouldOmitCCOutOperand(StringRef Mnemonic, 217 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 218 219 public: 220 enum ARMMatchResultTy { 221 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 222 Match_RequiresNotITBlock, 223 Match_RequiresV6, 224 Match_RequiresThumb2 225 }; 226 227 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 228 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 229 MCAsmParserExtension::Initialize(_Parser); 230 231 // Initialize the set of available features. 232 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 233 234 // Not in an ITBlock to start with. 235 ITState.CurPosition = ~0U; 236 } 237 238 // Implementation of the MCTargetAsmParser interface: 239 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 240 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 241 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 242 bool ParseDirective(AsmToken DirectiveID); 243 244 unsigned checkTargetMatchPredicate(MCInst &Inst); 245 246 bool MatchAndEmitInstruction(SMLoc IDLoc, 247 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 248 MCStreamer &Out); 249 }; 250 } // end anonymous namespace 251 252 namespace { 253 254 /// ARMOperand - Instances of this class represent a parsed ARM machine 255 /// instruction. 256 class ARMOperand : public MCParsedAsmOperand { 257 enum KindTy { 258 k_CondCode, 259 k_CCOut, 260 k_ITCondMask, 261 k_CoprocNum, 262 k_CoprocReg, 263 k_CoprocOption, 264 k_Immediate, 265 k_FPImmediate, 266 k_MemBarrierOpt, 267 k_Memory, 268 k_PostIndexRegister, 269 k_MSRMask, 270 k_ProcIFlags, 271 k_VectorIndex, 272 k_Register, 273 k_RegisterList, 274 k_DPRRegisterList, 275 k_SPRRegisterList, 276 k_VectorList, 277 k_VectorListAllLanes, 278 k_VectorListIndexed, 279 k_ShiftedRegister, 280 k_ShiftedImmediate, 281 k_ShifterImmediate, 282 k_RotateImmediate, 283 k_BitfieldDescriptor, 284 k_Token 285 } Kind; 286 287 SMLoc StartLoc, EndLoc; 288 SmallVector<unsigned, 8> Registers; 289 290 union { 291 struct { 292 ARMCC::CondCodes Val; 293 } CC; 294 295 struct { 296 unsigned Val; 297 } Cop; 298 299 struct { 300 unsigned Val; 301 } CoprocOption; 302 303 struct { 304 unsigned Mask:4; 305 } ITMask; 306 307 struct { 308 ARM_MB::MemBOpt Val; 309 } MBOpt; 310 311 struct { 312 ARM_PROC::IFlags Val; 313 } IFlags; 314 315 struct { 316 unsigned Val; 317 } MMask; 318 319 struct { 320 const char *Data; 321 unsigned Length; 322 } Tok; 323 324 struct { 325 unsigned RegNum; 326 } Reg; 327 328 // A vector register list is a sequential list of 1 to 4 registers. 329 struct { 330 unsigned RegNum; 331 unsigned Count; 332 unsigned LaneIndex; 333 } VectorList; 334 335 struct { 336 unsigned Val; 337 } VectorIndex; 338 339 struct { 340 const MCExpr *Val; 341 } Imm; 342 343 struct { 344 unsigned Val; // encoded 8-bit representation 345 } FPImm; 346 347 /// Combined record for all forms of ARM address expressions. 348 struct { 349 unsigned BaseRegNum; 350 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 351 // was specified. 352 const MCConstantExpr *OffsetImm; // Offset immediate value 353 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 354 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 355 unsigned ShiftImm; // shift for OffsetReg. 356 unsigned Alignment; // 0 = no alignment specified 357 // n = alignment in bytes (8, 16, or 32) 358 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 359 } Memory; 360 361 struct { 362 unsigned RegNum; 363 bool isAdd; 364 ARM_AM::ShiftOpc ShiftTy; 365 unsigned ShiftImm; 366 } PostIdxReg; 367 368 struct { 369 bool isASR; 370 unsigned Imm; 371 } ShifterImm; 372 struct { 373 ARM_AM::ShiftOpc ShiftTy; 374 unsigned SrcReg; 375 unsigned ShiftReg; 376 unsigned ShiftImm; 377 } RegShiftedReg; 378 struct { 379 ARM_AM::ShiftOpc ShiftTy; 380 unsigned SrcReg; 381 unsigned ShiftImm; 382 } RegShiftedImm; 383 struct { 384 unsigned Imm; 385 } RotImm; 386 struct { 387 unsigned LSB; 388 unsigned Width; 389 } Bitfield; 390 }; 391 392 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 393 public: 394 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 395 Kind = o.Kind; 396 StartLoc = o.StartLoc; 397 EndLoc = o.EndLoc; 398 switch (Kind) { 399 case k_CondCode: 400 CC = o.CC; 401 break; 402 case k_ITCondMask: 403 ITMask = o.ITMask; 404 break; 405 case k_Token: 406 Tok = o.Tok; 407 break; 408 case k_CCOut: 409 case k_Register: 410 Reg = o.Reg; 411 break; 412 case k_RegisterList: 413 case k_DPRRegisterList: 414 case k_SPRRegisterList: 415 Registers = o.Registers; 416 break; 417 case k_VectorList: 418 case k_VectorListAllLanes: 419 case k_VectorListIndexed: 420 VectorList = o.VectorList; 421 break; 422 case k_CoprocNum: 423 case k_CoprocReg: 424 Cop = o.Cop; 425 break; 426 case k_CoprocOption: 427 CoprocOption = o.CoprocOption; 428 break; 429 case k_Immediate: 430 Imm = o.Imm; 431 break; 432 case k_FPImmediate: 433 FPImm = o.FPImm; 434 break; 435 case k_MemBarrierOpt: 436 MBOpt = o.MBOpt; 437 break; 438 case k_Memory: 439 Memory = o.Memory; 440 break; 441 case k_PostIndexRegister: 442 PostIdxReg = o.PostIdxReg; 443 break; 444 case k_MSRMask: 445 MMask = o.MMask; 446 break; 447 case k_ProcIFlags: 448 IFlags = o.IFlags; 449 break; 450 case k_ShifterImmediate: 451 ShifterImm = o.ShifterImm; 452 break; 453 case k_ShiftedRegister: 454 RegShiftedReg = o.RegShiftedReg; 455 break; 456 case k_ShiftedImmediate: 457 RegShiftedImm = o.RegShiftedImm; 458 break; 459 case k_RotateImmediate: 460 RotImm = o.RotImm; 461 break; 462 case k_BitfieldDescriptor: 463 Bitfield = o.Bitfield; 464 break; 465 case k_VectorIndex: 466 VectorIndex = o.VectorIndex; 467 break; 468 } 469 } 470 471 /// getStartLoc - Get the location of the first token of this operand. 472 SMLoc getStartLoc() const { return StartLoc; } 473 /// getEndLoc - Get the location of the last token of this operand. 474 SMLoc getEndLoc() const { return EndLoc; } 475 476 ARMCC::CondCodes getCondCode() const { 477 assert(Kind == k_CondCode && "Invalid access!"); 478 return CC.Val; 479 } 480 481 unsigned getCoproc() const { 482 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 483 return Cop.Val; 484 } 485 486 StringRef getToken() const { 487 assert(Kind == k_Token && "Invalid access!"); 488 return StringRef(Tok.Data, Tok.Length); 489 } 490 491 unsigned getReg() const { 492 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 493 return Reg.RegNum; 494 } 495 496 const SmallVectorImpl<unsigned> &getRegList() const { 497 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 498 Kind == k_SPRRegisterList) && "Invalid access!"); 499 return Registers; 500 } 501 502 const MCExpr *getImm() const { 503 assert(Kind == k_Immediate && "Invalid access!"); 504 return Imm.Val; 505 } 506 507 unsigned getFPImm() const { 508 assert(Kind == k_FPImmediate && "Invalid access!"); 509 return FPImm.Val; 510 } 511 512 unsigned getVectorIndex() const { 513 assert(Kind == k_VectorIndex && "Invalid access!"); 514 return VectorIndex.Val; 515 } 516 517 ARM_MB::MemBOpt getMemBarrierOpt() const { 518 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 519 return MBOpt.Val; 520 } 521 522 ARM_PROC::IFlags getProcIFlags() const { 523 assert(Kind == k_ProcIFlags && "Invalid access!"); 524 return IFlags.Val; 525 } 526 527 unsigned getMSRMask() const { 528 assert(Kind == k_MSRMask && "Invalid access!"); 529 return MMask.Val; 530 } 531 532 bool isCoprocNum() const { return Kind == k_CoprocNum; } 533 bool isCoprocReg() const { return Kind == k_CoprocReg; } 534 bool isCoprocOption() const { return Kind == k_CoprocOption; } 535 bool isCondCode() const { return Kind == k_CondCode; } 536 bool isCCOut() const { return Kind == k_CCOut; } 537 bool isITMask() const { return Kind == k_ITCondMask; } 538 bool isITCondCode() const { return Kind == k_CondCode; } 539 bool isImm() const { return Kind == k_Immediate; } 540 bool isFPImm() const { return Kind == k_FPImmediate; } 541 bool isImm8s4() const { 542 if (Kind != k_Immediate) 543 return false; 544 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 545 if (!CE) return false; 546 int64_t Value = CE->getValue(); 547 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 548 } 549 bool isImm0_1020s4() const { 550 if (Kind != k_Immediate) 551 return false; 552 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 553 if (!CE) return false; 554 int64_t Value = CE->getValue(); 555 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 556 } 557 bool isImm0_508s4() const { 558 if (Kind != k_Immediate) 559 return false; 560 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 561 if (!CE) return false; 562 int64_t Value = CE->getValue(); 563 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 564 } 565 bool isImm0_255() const { 566 if (Kind != k_Immediate) 567 return false; 568 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 569 if (!CE) return false; 570 int64_t Value = CE->getValue(); 571 return Value >= 0 && Value < 256; 572 } 573 bool isImm0_1() const { 574 if (Kind != k_Immediate) 575 return false; 576 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 577 if (!CE) return false; 578 int64_t Value = CE->getValue(); 579 return Value >= 0 && Value < 2; 580 } 581 bool isImm0_3() const { 582 if (Kind != k_Immediate) 583 return false; 584 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 585 if (!CE) return false; 586 int64_t Value = CE->getValue(); 587 return Value >= 0 && Value < 4; 588 } 589 bool isImm0_7() const { 590 if (Kind != k_Immediate) 591 return false; 592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 593 if (!CE) return false; 594 int64_t Value = CE->getValue(); 595 return Value >= 0 && Value < 8; 596 } 597 bool isImm0_15() const { 598 if (Kind != k_Immediate) 599 return false; 600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 601 if (!CE) return false; 602 int64_t Value = CE->getValue(); 603 return Value >= 0 && Value < 16; 604 } 605 bool isImm0_31() const { 606 if (Kind != k_Immediate) 607 return false; 608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 609 if (!CE) return false; 610 int64_t Value = CE->getValue(); 611 return Value >= 0 && Value < 32; 612 } 613 bool isImm8() const { 614 if (Kind != k_Immediate) 615 return false; 616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 617 if (!CE) return false; 618 int64_t Value = CE->getValue(); 619 return Value == 8; 620 } 621 bool isImm16() const { 622 if (Kind != k_Immediate) 623 return false; 624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 625 if (!CE) return false; 626 int64_t Value = CE->getValue(); 627 return Value == 16; 628 } 629 bool isImm32() const { 630 if (Kind != k_Immediate) 631 return false; 632 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 633 if (!CE) return false; 634 int64_t Value = CE->getValue(); 635 return Value == 32; 636 } 637 bool isImm1_7() const { 638 if (Kind != k_Immediate) 639 return false; 640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 641 if (!CE) return false; 642 int64_t Value = CE->getValue(); 643 return Value > 0 && Value < 8; 644 } 645 bool isImm1_15() const { 646 if (Kind != k_Immediate) 647 return false; 648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 649 if (!CE) return false; 650 int64_t Value = CE->getValue(); 651 return Value > 0 && Value < 16; 652 } 653 bool isImm1_31() const { 654 if (Kind != k_Immediate) 655 return false; 656 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 657 if (!CE) return false; 658 int64_t Value = CE->getValue(); 659 return Value > 0 && Value < 32; 660 } 661 bool isImm1_16() const { 662 if (Kind != k_Immediate) 663 return false; 664 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 665 if (!CE) return false; 666 int64_t Value = CE->getValue(); 667 return Value > 0 && Value < 17; 668 } 669 bool isImm1_32() const { 670 if (Kind != k_Immediate) 671 return false; 672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 673 if (!CE) return false; 674 int64_t Value = CE->getValue(); 675 return Value > 0 && Value < 33; 676 } 677 bool isImm0_32() const { 678 if (Kind != k_Immediate) 679 return false; 680 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 681 if (!CE) return false; 682 int64_t Value = CE->getValue(); 683 return Value >= 0 && Value < 33; 684 } 685 bool isImm0_65535() const { 686 if (Kind != k_Immediate) 687 return false; 688 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 689 if (!CE) return false; 690 int64_t Value = CE->getValue(); 691 return Value >= 0 && Value < 65536; 692 } 693 bool isImm0_65535Expr() const { 694 if (Kind != k_Immediate) 695 return false; 696 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 697 // If it's not a constant expression, it'll generate a fixup and be 698 // handled later. 699 if (!CE) return true; 700 int64_t Value = CE->getValue(); 701 return Value >= 0 && Value < 65536; 702 } 703 bool isImm24bit() const { 704 if (Kind != k_Immediate) 705 return false; 706 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 707 if (!CE) return false; 708 int64_t Value = CE->getValue(); 709 return Value >= 0 && Value <= 0xffffff; 710 } 711 bool isImmThumbSR() const { 712 if (Kind != k_Immediate) 713 return false; 714 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 715 if (!CE) return false; 716 int64_t Value = CE->getValue(); 717 return Value > 0 && Value < 33; 718 } 719 bool isPKHLSLImm() const { 720 if (Kind != k_Immediate) 721 return false; 722 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 723 if (!CE) return false; 724 int64_t Value = CE->getValue(); 725 return Value >= 0 && Value < 32; 726 } 727 bool isPKHASRImm() const { 728 if (Kind != k_Immediate) 729 return false; 730 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 731 if (!CE) return false; 732 int64_t Value = CE->getValue(); 733 return Value > 0 && Value <= 32; 734 } 735 bool isARMSOImm() const { 736 if (Kind != k_Immediate) 737 return false; 738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 739 if (!CE) return false; 740 int64_t Value = CE->getValue(); 741 return ARM_AM::getSOImmVal(Value) != -1; 742 } 743 bool isARMSOImmNot() const { 744 if (Kind != k_Immediate) 745 return false; 746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 747 if (!CE) return false; 748 int64_t Value = CE->getValue(); 749 return ARM_AM::getSOImmVal(~Value) != -1; 750 } 751 bool isT2SOImm() const { 752 if (Kind != k_Immediate) 753 return false; 754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 755 if (!CE) return false; 756 int64_t Value = CE->getValue(); 757 return ARM_AM::getT2SOImmVal(Value) != -1; 758 } 759 bool isT2SOImmNot() const { 760 if (Kind != k_Immediate) 761 return false; 762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 763 if (!CE) return false; 764 int64_t Value = CE->getValue(); 765 return ARM_AM::getT2SOImmVal(~Value) != -1; 766 } 767 bool isSetEndImm() const { 768 if (Kind != k_Immediate) 769 return false; 770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 771 if (!CE) return false; 772 int64_t Value = CE->getValue(); 773 return Value == 1 || Value == 0; 774 } 775 bool isReg() const { return Kind == k_Register; } 776 bool isRegList() const { return Kind == k_RegisterList; } 777 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 778 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 779 bool isToken() const { return Kind == k_Token; } 780 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 781 bool isMemory() const { return Kind == k_Memory; } 782 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 783 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 784 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 785 bool isRotImm() const { return Kind == k_RotateImmediate; } 786 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 787 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 788 bool isPostIdxReg() const { 789 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 790 } 791 bool isMemNoOffset(bool alignOK = false) const { 792 if (!isMemory()) 793 return false; 794 // No offset of any kind. 795 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 796 (alignOK || Memory.Alignment == 0); 797 } 798 bool isAlignedMemory() const { 799 return isMemNoOffset(true); 800 } 801 bool isAddrMode2() const { 802 if (!isMemory() || Memory.Alignment != 0) return false; 803 // Check for register offset. 804 if (Memory.OffsetRegNum) return true; 805 // Immediate offset in range [-4095, 4095]. 806 if (!Memory.OffsetImm) return true; 807 int64_t Val = Memory.OffsetImm->getValue(); 808 return Val > -4096 && Val < 4096; 809 } 810 bool isAM2OffsetImm() const { 811 if (Kind != k_Immediate) 812 return false; 813 // Immediate offset in range [-4095, 4095]. 814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 815 if (!CE) return false; 816 int64_t Val = CE->getValue(); 817 return Val > -4096 && Val < 4096; 818 } 819 bool isAddrMode3() const { 820 if (!isMemory() || Memory.Alignment != 0) return false; 821 // No shifts are legal for AM3. 822 if (Memory.ShiftType != ARM_AM::no_shift) return false; 823 // Check for register offset. 824 if (Memory.OffsetRegNum) return true; 825 // Immediate offset in range [-255, 255]. 826 if (!Memory.OffsetImm) return true; 827 int64_t Val = Memory.OffsetImm->getValue(); 828 return Val > -256 && Val < 256; 829 } 830 bool isAM3Offset() const { 831 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 832 return false; 833 if (Kind == k_PostIndexRegister) 834 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 835 // Immediate offset in range [-255, 255]. 836 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 837 if (!CE) return false; 838 int64_t Val = CE->getValue(); 839 // Special case, #-0 is INT32_MIN. 840 return (Val > -256 && Val < 256) || Val == INT32_MIN; 841 } 842 bool isAddrMode5() const { 843 // If we have an immediate that's not a constant, treat it as a label 844 // reference needing a fixup. If it is a constant, it's something else 845 // and we reject it. 846 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm())) 847 return true; 848 if (!isMemory() || Memory.Alignment != 0) return false; 849 // Check for register offset. 850 if (Memory.OffsetRegNum) return false; 851 // Immediate offset in range [-1020, 1020] and a multiple of 4. 852 if (!Memory.OffsetImm) return true; 853 int64_t Val = Memory.OffsetImm->getValue(); 854 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 855 Val == INT32_MIN; 856 } 857 bool isMemTBB() const { 858 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 859 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 860 return false; 861 return true; 862 } 863 bool isMemTBH() const { 864 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 865 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 866 Memory.Alignment != 0 ) 867 return false; 868 return true; 869 } 870 bool isMemRegOffset() const { 871 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 872 return false; 873 return true; 874 } 875 bool isT2MemRegOffset() const { 876 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 877 Memory.Alignment != 0) 878 return false; 879 // Only lsl #{0, 1, 2, 3} allowed. 880 if (Memory.ShiftType == ARM_AM::no_shift) 881 return true; 882 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 883 return false; 884 return true; 885 } 886 bool isMemThumbRR() const { 887 // Thumb reg+reg addressing is simple. Just two registers, a base and 888 // an offset. No shifts, negations or any other complicating factors. 889 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 890 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 891 return false; 892 return isARMLowRegister(Memory.BaseRegNum) && 893 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 894 } 895 bool isMemThumbRIs4() const { 896 if (!isMemory() || Memory.OffsetRegNum != 0 || 897 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 898 return false; 899 // Immediate offset, multiple of 4 in range [0, 124]. 900 if (!Memory.OffsetImm) return true; 901 int64_t Val = Memory.OffsetImm->getValue(); 902 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 903 } 904 bool isMemThumbRIs2() const { 905 if (!isMemory() || Memory.OffsetRegNum != 0 || 906 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 907 return false; 908 // Immediate offset, multiple of 4 in range [0, 62]. 909 if (!Memory.OffsetImm) return true; 910 int64_t Val = Memory.OffsetImm->getValue(); 911 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 912 } 913 bool isMemThumbRIs1() const { 914 if (!isMemory() || Memory.OffsetRegNum != 0 || 915 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 916 return false; 917 // Immediate offset in range [0, 31]. 918 if (!Memory.OffsetImm) return true; 919 int64_t Val = Memory.OffsetImm->getValue(); 920 return Val >= 0 && Val <= 31; 921 } 922 bool isMemThumbSPI() const { 923 if (!isMemory() || Memory.OffsetRegNum != 0 || 924 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 925 return false; 926 // Immediate offset, multiple of 4 in range [0, 1020]. 927 if (!Memory.OffsetImm) return true; 928 int64_t Val = Memory.OffsetImm->getValue(); 929 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 930 } 931 bool isMemImm8s4Offset() const { 932 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 933 return false; 934 // Immediate offset a multiple of 4 in range [-1020, 1020]. 935 if (!Memory.OffsetImm) return true; 936 int64_t Val = Memory.OffsetImm->getValue(); 937 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; 938 } 939 bool isMemImm0_1020s4Offset() const { 940 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 941 return false; 942 // Immediate offset a multiple of 4 in range [0, 1020]. 943 if (!Memory.OffsetImm) return true; 944 int64_t Val = Memory.OffsetImm->getValue(); 945 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 946 } 947 bool isMemImm8Offset() const { 948 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 949 return false; 950 // Immediate offset in range [-255, 255]. 951 if (!Memory.OffsetImm) return true; 952 int64_t Val = Memory.OffsetImm->getValue(); 953 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 954 } 955 bool isMemPosImm8Offset() const { 956 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 957 return false; 958 // Immediate offset in range [0, 255]. 959 if (!Memory.OffsetImm) return true; 960 int64_t Val = Memory.OffsetImm->getValue(); 961 return Val >= 0 && Val < 256; 962 } 963 bool isMemNegImm8Offset() const { 964 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 965 return false; 966 // Immediate offset in range [-255, -1]. 967 if (!Memory.OffsetImm) return false; 968 int64_t Val = Memory.OffsetImm->getValue(); 969 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 970 } 971 bool isMemUImm12Offset() const { 972 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 973 return false; 974 // Immediate offset in range [0, 4095]. 975 if (!Memory.OffsetImm) return true; 976 int64_t Val = Memory.OffsetImm->getValue(); 977 return (Val >= 0 && Val < 4096); 978 } 979 bool isMemImm12Offset() const { 980 // If we have an immediate that's not a constant, treat it as a label 981 // reference needing a fixup. If it is a constant, it's something else 982 // and we reject it. 983 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm())) 984 return true; 985 986 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 987 return false; 988 // Immediate offset in range [-4095, 4095]. 989 if (!Memory.OffsetImm) return true; 990 int64_t Val = Memory.OffsetImm->getValue(); 991 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 992 } 993 bool isPostIdxImm8() const { 994 if (Kind != k_Immediate) 995 return false; 996 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 997 if (!CE) return false; 998 int64_t Val = CE->getValue(); 999 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1000 } 1001 bool isPostIdxImm8s4() const { 1002 if (Kind != k_Immediate) 1003 return false; 1004 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1005 if (!CE) return false; 1006 int64_t Val = CE->getValue(); 1007 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1008 (Val == INT32_MIN); 1009 } 1010 1011 bool isMSRMask() const { return Kind == k_MSRMask; } 1012 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1013 1014 // NEON operands. 1015 bool isVecListOneD() const { 1016 if (Kind != k_VectorList) return false; 1017 return VectorList.Count == 1; 1018 } 1019 1020 bool isVecListTwoD() const { 1021 if (Kind != k_VectorList) return false; 1022 return VectorList.Count == 2; 1023 } 1024 1025 bool isVecListThreeD() const { 1026 if (Kind != k_VectorList) return false; 1027 return VectorList.Count == 3; 1028 } 1029 1030 bool isVecListFourD() const { 1031 if (Kind != k_VectorList) return false; 1032 return VectorList.Count == 4; 1033 } 1034 1035 bool isVecListTwoQ() const { 1036 if (Kind != k_VectorList) return false; 1037 //FIXME: We haven't taught the parser to handle by-two register lists 1038 // yet, so don't pretend to know one. 1039 return VectorList.Count == 2 && false; 1040 } 1041 1042 bool isVecListOneDAllLanes() const { 1043 if (Kind != k_VectorListAllLanes) return false; 1044 return VectorList.Count == 1; 1045 } 1046 1047 bool isVecListTwoDAllLanes() const { 1048 if (Kind != k_VectorListAllLanes) return false; 1049 return VectorList.Count == 2; 1050 } 1051 1052 bool isVecListOneDByteIndexed() const { 1053 if (Kind != k_VectorListIndexed) return false; 1054 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1055 } 1056 1057 bool isVectorIndex8() const { 1058 if (Kind != k_VectorIndex) return false; 1059 return VectorIndex.Val < 8; 1060 } 1061 bool isVectorIndex16() const { 1062 if (Kind != k_VectorIndex) return false; 1063 return VectorIndex.Val < 4; 1064 } 1065 bool isVectorIndex32() const { 1066 if (Kind != k_VectorIndex) return false; 1067 return VectorIndex.Val < 2; 1068 } 1069 1070 bool isNEONi8splat() const { 1071 if (Kind != k_Immediate) 1072 return false; 1073 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1074 // Must be a constant. 1075 if (!CE) return false; 1076 int64_t Value = CE->getValue(); 1077 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1078 // value. 1079 return Value >= 0 && Value < 256; 1080 } 1081 1082 bool isNEONi16splat() const { 1083 if (Kind != k_Immediate) 1084 return false; 1085 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1086 // Must be a constant. 1087 if (!CE) return false; 1088 int64_t Value = CE->getValue(); 1089 // i16 value in the range [0,255] or [0x0100, 0xff00] 1090 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1091 } 1092 1093 bool isNEONi32splat() const { 1094 if (Kind != k_Immediate) 1095 return false; 1096 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1097 // Must be a constant. 1098 if (!CE) return false; 1099 int64_t Value = CE->getValue(); 1100 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1101 return (Value >= 0 && Value < 256) || 1102 (Value >= 0x0100 && Value <= 0xff00) || 1103 (Value >= 0x010000 && Value <= 0xff0000) || 1104 (Value >= 0x01000000 && Value <= 0xff000000); 1105 } 1106 1107 bool isNEONi32vmov() const { 1108 if (Kind != k_Immediate) 1109 return false; 1110 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1111 // Must be a constant. 1112 if (!CE) return false; 1113 int64_t Value = CE->getValue(); 1114 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1115 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1116 return (Value >= 0 && Value < 256) || 1117 (Value >= 0x0100 && Value <= 0xff00) || 1118 (Value >= 0x010000 && Value <= 0xff0000) || 1119 (Value >= 0x01000000 && Value <= 0xff000000) || 1120 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1121 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1122 } 1123 1124 bool isNEONi64splat() const { 1125 if (Kind != k_Immediate) 1126 return false; 1127 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1128 // Must be a constant. 1129 if (!CE) return false; 1130 uint64_t Value = CE->getValue(); 1131 // i64 value with each byte being either 0 or 0xff. 1132 for (unsigned i = 0; i < 8; ++i) 1133 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1134 return true; 1135 } 1136 1137 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1138 // Add as immediates when possible. Null MCExpr = 0. 1139 if (Expr == 0) 1140 Inst.addOperand(MCOperand::CreateImm(0)); 1141 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1142 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1143 else 1144 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1145 } 1146 1147 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1148 assert(N == 2 && "Invalid number of operands!"); 1149 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1150 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1151 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1152 } 1153 1154 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1155 assert(N == 1 && "Invalid number of operands!"); 1156 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1157 } 1158 1159 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1160 assert(N == 1 && "Invalid number of operands!"); 1161 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1162 } 1163 1164 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1165 assert(N == 1 && "Invalid number of operands!"); 1166 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1167 } 1168 1169 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1170 assert(N == 1 && "Invalid number of operands!"); 1171 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1172 } 1173 1174 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1175 assert(N == 1 && "Invalid number of operands!"); 1176 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1177 } 1178 1179 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1180 assert(N == 1 && "Invalid number of operands!"); 1181 Inst.addOperand(MCOperand::CreateReg(getReg())); 1182 } 1183 1184 void addRegOperands(MCInst &Inst, unsigned N) const { 1185 assert(N == 1 && "Invalid number of operands!"); 1186 Inst.addOperand(MCOperand::CreateReg(getReg())); 1187 } 1188 1189 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1190 assert(N == 3 && "Invalid number of operands!"); 1191 assert(isRegShiftedReg() && 1192 "addRegShiftedRegOperands() on non RegShiftedReg!"); 1193 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1194 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1195 Inst.addOperand(MCOperand::CreateImm( 1196 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1197 } 1198 1199 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1200 assert(N == 2 && "Invalid number of operands!"); 1201 assert(isRegShiftedImm() && 1202 "addRegShiftedImmOperands() on non RegShiftedImm!"); 1203 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1204 Inst.addOperand(MCOperand::CreateImm( 1205 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); 1206 } 1207 1208 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1209 assert(N == 1 && "Invalid number of operands!"); 1210 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1211 ShifterImm.Imm)); 1212 } 1213 1214 void addRegListOperands(MCInst &Inst, unsigned N) const { 1215 assert(N == 1 && "Invalid number of operands!"); 1216 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1217 for (SmallVectorImpl<unsigned>::const_iterator 1218 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1219 Inst.addOperand(MCOperand::CreateReg(*I)); 1220 } 1221 1222 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1223 addRegListOperands(Inst, N); 1224 } 1225 1226 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1227 addRegListOperands(Inst, N); 1228 } 1229 1230 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1231 assert(N == 1 && "Invalid number of operands!"); 1232 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1233 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1234 } 1235 1236 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1237 assert(N == 1 && "Invalid number of operands!"); 1238 // Munge the lsb/width into a bitfield mask. 1239 unsigned lsb = Bitfield.LSB; 1240 unsigned width = Bitfield.Width; 1241 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1242 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1243 (32 - (lsb + width))); 1244 Inst.addOperand(MCOperand::CreateImm(Mask)); 1245 } 1246 1247 void addImmOperands(MCInst &Inst, unsigned N) const { 1248 assert(N == 1 && "Invalid number of operands!"); 1249 addExpr(Inst, getImm()); 1250 } 1251 1252 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1253 assert(N == 1 && "Invalid number of operands!"); 1254 Inst.addOperand(MCOperand::CreateImm(getFPImm())); 1255 } 1256 1257 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1258 assert(N == 1 && "Invalid number of operands!"); 1259 // FIXME: We really want to scale the value here, but the LDRD/STRD 1260 // instruction don't encode operands that way yet. 1261 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1262 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1263 } 1264 1265 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1266 assert(N == 1 && "Invalid number of operands!"); 1267 // The immediate is scaled by four in the encoding and is stored 1268 // in the MCInst as such. Lop off the low two bits here. 1269 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1270 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1271 } 1272 1273 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1274 assert(N == 1 && "Invalid number of operands!"); 1275 // The immediate is scaled by four in the encoding and is stored 1276 // in the MCInst as such. Lop off the low two bits here. 1277 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1278 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1279 } 1280 1281 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1282 assert(N == 1 && "Invalid number of operands!"); 1283 // The constant encodes as the immediate-1, and we store in the instruction 1284 // the bits as encoded, so subtract off one here. 1285 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1286 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1287 } 1288 1289 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1290 assert(N == 1 && "Invalid number of operands!"); 1291 // The constant encodes as the immediate-1, and we store in the instruction 1292 // the bits as encoded, so subtract off one here. 1293 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1294 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1295 } 1296 1297 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1298 assert(N == 1 && "Invalid number of operands!"); 1299 // The constant encodes as the immediate, except for 32, which encodes as 1300 // zero. 1301 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1302 unsigned Imm = CE->getValue(); 1303 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1304 } 1305 1306 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1307 assert(N == 1 && "Invalid number of operands!"); 1308 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1309 // the instruction as well. 1310 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1311 int Val = CE->getValue(); 1312 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1313 } 1314 1315 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1316 assert(N == 1 && "Invalid number of operands!"); 1317 // The operand is actually a t2_so_imm, but we have its bitwise 1318 // negation in the assembly source, so twiddle it here. 1319 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1320 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1321 } 1322 1323 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1324 assert(N == 1 && "Invalid number of operands!"); 1325 // The operand is actually a so_imm, but we have its bitwise 1326 // negation in the assembly source, so twiddle it here. 1327 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1328 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1329 } 1330 1331 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1332 assert(N == 1 && "Invalid number of operands!"); 1333 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1334 } 1335 1336 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1337 assert(N == 1 && "Invalid number of operands!"); 1338 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1339 } 1340 1341 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1342 assert(N == 2 && "Invalid number of operands!"); 1343 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1344 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1345 } 1346 1347 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1348 assert(N == 3 && "Invalid number of operands!"); 1349 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1350 if (!Memory.OffsetRegNum) { 1351 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1352 // Special case for #-0 1353 if (Val == INT32_MIN) Val = 0; 1354 if (Val < 0) Val = -Val; 1355 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1356 } else { 1357 // For register offset, we encode the shift type and negation flag 1358 // here. 1359 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1360 Memory.ShiftImm, Memory.ShiftType); 1361 } 1362 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1363 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1364 Inst.addOperand(MCOperand::CreateImm(Val)); 1365 } 1366 1367 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1368 assert(N == 2 && "Invalid number of operands!"); 1369 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1370 assert(CE && "non-constant AM2OffsetImm operand!"); 1371 int32_t Val = CE->getValue(); 1372 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1373 // Special case for #-0 1374 if (Val == INT32_MIN) Val = 0; 1375 if (Val < 0) Val = -Val; 1376 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1377 Inst.addOperand(MCOperand::CreateReg(0)); 1378 Inst.addOperand(MCOperand::CreateImm(Val)); 1379 } 1380 1381 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1382 assert(N == 3 && "Invalid number of operands!"); 1383 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1384 if (!Memory.OffsetRegNum) { 1385 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1386 // Special case for #-0 1387 if (Val == INT32_MIN) Val = 0; 1388 if (Val < 0) Val = -Val; 1389 Val = ARM_AM::getAM3Opc(AddSub, Val); 1390 } else { 1391 // For register offset, we encode the shift type and negation flag 1392 // here. 1393 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1394 } 1395 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1396 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1397 Inst.addOperand(MCOperand::CreateImm(Val)); 1398 } 1399 1400 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1401 assert(N == 2 && "Invalid number of operands!"); 1402 if (Kind == k_PostIndexRegister) { 1403 int32_t Val = 1404 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1405 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1406 Inst.addOperand(MCOperand::CreateImm(Val)); 1407 return; 1408 } 1409 1410 // Constant offset. 1411 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1412 int32_t Val = CE->getValue(); 1413 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1414 // Special case for #-0 1415 if (Val == INT32_MIN) Val = 0; 1416 if (Val < 0) Val = -Val; 1417 Val = ARM_AM::getAM3Opc(AddSub, Val); 1418 Inst.addOperand(MCOperand::CreateReg(0)); 1419 Inst.addOperand(MCOperand::CreateImm(Val)); 1420 } 1421 1422 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1423 assert(N == 2 && "Invalid number of operands!"); 1424 // If we have an immediate that's not a constant, treat it as a label 1425 // reference needing a fixup. If it is a constant, it's something else 1426 // and we reject it. 1427 if (isImm()) { 1428 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1429 Inst.addOperand(MCOperand::CreateImm(0)); 1430 return; 1431 } 1432 1433 // The lower two bits are always zero and as such are not encoded. 1434 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1435 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1436 // Special case for #-0 1437 if (Val == INT32_MIN) Val = 0; 1438 if (Val < 0) Val = -Val; 1439 Val = ARM_AM::getAM5Opc(AddSub, Val); 1440 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1441 Inst.addOperand(MCOperand::CreateImm(Val)); 1442 } 1443 1444 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1445 assert(N == 2 && "Invalid number of operands!"); 1446 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1447 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1448 Inst.addOperand(MCOperand::CreateImm(Val)); 1449 } 1450 1451 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1452 assert(N == 2 && "Invalid number of operands!"); 1453 // The lower two bits are always zero and as such are not encoded. 1454 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1455 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1456 Inst.addOperand(MCOperand::CreateImm(Val)); 1457 } 1458 1459 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1460 assert(N == 2 && "Invalid number of operands!"); 1461 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1462 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1463 Inst.addOperand(MCOperand::CreateImm(Val)); 1464 } 1465 1466 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1467 addMemImm8OffsetOperands(Inst, N); 1468 } 1469 1470 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1471 addMemImm8OffsetOperands(Inst, N); 1472 } 1473 1474 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1475 assert(N == 2 && "Invalid number of operands!"); 1476 // If this is an immediate, it's a label reference. 1477 if (Kind == k_Immediate) { 1478 addExpr(Inst, getImm()); 1479 Inst.addOperand(MCOperand::CreateImm(0)); 1480 return; 1481 } 1482 1483 // Otherwise, it's a normal memory reg+offset. 1484 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1485 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1486 Inst.addOperand(MCOperand::CreateImm(Val)); 1487 } 1488 1489 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1490 assert(N == 2 && "Invalid number of operands!"); 1491 // If this is an immediate, it's a label reference. 1492 if (Kind == k_Immediate) { 1493 addExpr(Inst, getImm()); 1494 Inst.addOperand(MCOperand::CreateImm(0)); 1495 return; 1496 } 1497 1498 // Otherwise, it's a normal memory reg+offset. 1499 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1500 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1501 Inst.addOperand(MCOperand::CreateImm(Val)); 1502 } 1503 1504 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 1505 assert(N == 2 && "Invalid number of operands!"); 1506 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1507 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1508 } 1509 1510 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 1511 assert(N == 2 && "Invalid number of operands!"); 1512 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1513 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1514 } 1515 1516 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1517 assert(N == 3 && "Invalid number of operands!"); 1518 unsigned Val = 1519 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1520 Memory.ShiftImm, Memory.ShiftType); 1521 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1522 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1523 Inst.addOperand(MCOperand::CreateImm(Val)); 1524 } 1525 1526 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1527 assert(N == 3 && "Invalid number of operands!"); 1528 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1529 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1530 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1531 } 1532 1533 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1534 assert(N == 2 && "Invalid number of operands!"); 1535 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1536 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1537 } 1538 1539 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1540 assert(N == 2 && "Invalid number of operands!"); 1541 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1542 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1543 Inst.addOperand(MCOperand::CreateImm(Val)); 1544 } 1545 1546 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1547 assert(N == 2 && "Invalid number of operands!"); 1548 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1549 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1550 Inst.addOperand(MCOperand::CreateImm(Val)); 1551 } 1552 1553 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1554 assert(N == 2 && "Invalid number of operands!"); 1555 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1556 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1557 Inst.addOperand(MCOperand::CreateImm(Val)); 1558 } 1559 1560 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1561 assert(N == 2 && "Invalid number of operands!"); 1562 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1563 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1564 Inst.addOperand(MCOperand::CreateImm(Val)); 1565 } 1566 1567 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 1568 assert(N == 1 && "Invalid number of operands!"); 1569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1570 assert(CE && "non-constant post-idx-imm8 operand!"); 1571 int Imm = CE->getValue(); 1572 bool isAdd = Imm >= 0; 1573 if (Imm == INT32_MIN) Imm = 0; 1574 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 1575 Inst.addOperand(MCOperand::CreateImm(Imm)); 1576 } 1577 1578 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 1579 assert(N == 1 && "Invalid number of operands!"); 1580 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1581 assert(CE && "non-constant post-idx-imm8s4 operand!"); 1582 int Imm = CE->getValue(); 1583 bool isAdd = Imm >= 0; 1584 if (Imm == INT32_MIN) Imm = 0; 1585 // Immediate is scaled by 4. 1586 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 1587 Inst.addOperand(MCOperand::CreateImm(Imm)); 1588 } 1589 1590 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 1591 assert(N == 2 && "Invalid number of operands!"); 1592 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1593 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1594 } 1595 1596 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1597 assert(N == 2 && "Invalid number of operands!"); 1598 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1599 // The sign, shift type, and shift amount are encoded in a single operand 1600 // using the AM2 encoding helpers. 1601 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1602 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1603 PostIdxReg.ShiftTy); 1604 Inst.addOperand(MCOperand::CreateImm(Imm)); 1605 } 1606 1607 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1608 assert(N == 1 && "Invalid number of operands!"); 1609 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1610 } 1611 1612 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1613 assert(N == 1 && "Invalid number of operands!"); 1614 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1615 } 1616 1617 void addVecListOperands(MCInst &Inst, unsigned N) const { 1618 assert(N == 1 && "Invalid number of operands!"); 1619 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1620 } 1621 1622 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 1623 assert(N == 2 && "Invalid number of operands!"); 1624 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1625 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 1626 } 1627 1628 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1629 assert(N == 1 && "Invalid number of operands!"); 1630 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1631 } 1632 1633 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1634 assert(N == 1 && "Invalid number of operands!"); 1635 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1636 } 1637 1638 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1639 assert(N == 1 && "Invalid number of operands!"); 1640 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1641 } 1642 1643 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 1644 assert(N == 1 && "Invalid number of operands!"); 1645 // The immediate encodes the type of constant as well as the value. 1646 // Mask in that this is an i8 splat. 1647 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1648 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 1649 } 1650 1651 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 1652 assert(N == 1 && "Invalid number of operands!"); 1653 // The immediate encodes the type of constant as well as the value. 1654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1655 unsigned Value = CE->getValue(); 1656 if (Value >= 256) 1657 Value = (Value >> 8) | 0xa00; 1658 else 1659 Value |= 0x800; 1660 Inst.addOperand(MCOperand::CreateImm(Value)); 1661 } 1662 1663 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 1664 assert(N == 1 && "Invalid number of operands!"); 1665 // The immediate encodes the type of constant as well as the value. 1666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1667 unsigned Value = CE->getValue(); 1668 if (Value >= 256 && Value <= 0xff00) 1669 Value = (Value >> 8) | 0x200; 1670 else if (Value > 0xffff && Value <= 0xff0000) 1671 Value = (Value >> 16) | 0x400; 1672 else if (Value > 0xffffff) 1673 Value = (Value >> 24) | 0x600; 1674 Inst.addOperand(MCOperand::CreateImm(Value)); 1675 } 1676 1677 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 1678 assert(N == 1 && "Invalid number of operands!"); 1679 // The immediate encodes the type of constant as well as the value. 1680 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1681 unsigned Value = CE->getValue(); 1682 if (Value >= 256 && Value <= 0xffff) 1683 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 1684 else if (Value > 0xffff && Value <= 0xffffff) 1685 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 1686 else if (Value > 0xffffff) 1687 Value = (Value >> 24) | 0x600; 1688 Inst.addOperand(MCOperand::CreateImm(Value)); 1689 } 1690 1691 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 1692 assert(N == 1 && "Invalid number of operands!"); 1693 // The immediate encodes the type of constant as well as the value. 1694 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1695 uint64_t Value = CE->getValue(); 1696 unsigned Imm = 0; 1697 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 1698 Imm |= (Value & 1) << i; 1699 } 1700 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 1701 } 1702 1703 virtual void print(raw_ostream &OS) const; 1704 1705 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 1706 ARMOperand *Op = new ARMOperand(k_ITCondMask); 1707 Op->ITMask.Mask = Mask; 1708 Op->StartLoc = S; 1709 Op->EndLoc = S; 1710 return Op; 1711 } 1712 1713 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 1714 ARMOperand *Op = new ARMOperand(k_CondCode); 1715 Op->CC.Val = CC; 1716 Op->StartLoc = S; 1717 Op->EndLoc = S; 1718 return Op; 1719 } 1720 1721 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 1722 ARMOperand *Op = new ARMOperand(k_CoprocNum); 1723 Op->Cop.Val = CopVal; 1724 Op->StartLoc = S; 1725 Op->EndLoc = S; 1726 return Op; 1727 } 1728 1729 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 1730 ARMOperand *Op = new ARMOperand(k_CoprocReg); 1731 Op->Cop.Val = CopVal; 1732 Op->StartLoc = S; 1733 Op->EndLoc = S; 1734 return Op; 1735 } 1736 1737 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 1738 ARMOperand *Op = new ARMOperand(k_CoprocOption); 1739 Op->Cop.Val = Val; 1740 Op->StartLoc = S; 1741 Op->EndLoc = E; 1742 return Op; 1743 } 1744 1745 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 1746 ARMOperand *Op = new ARMOperand(k_CCOut); 1747 Op->Reg.RegNum = RegNum; 1748 Op->StartLoc = S; 1749 Op->EndLoc = S; 1750 return Op; 1751 } 1752 1753 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 1754 ARMOperand *Op = new ARMOperand(k_Token); 1755 Op->Tok.Data = Str.data(); 1756 Op->Tok.Length = Str.size(); 1757 Op->StartLoc = S; 1758 Op->EndLoc = S; 1759 return Op; 1760 } 1761 1762 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 1763 ARMOperand *Op = new ARMOperand(k_Register); 1764 Op->Reg.RegNum = RegNum; 1765 Op->StartLoc = S; 1766 Op->EndLoc = E; 1767 return Op; 1768 } 1769 1770 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 1771 unsigned SrcReg, 1772 unsigned ShiftReg, 1773 unsigned ShiftImm, 1774 SMLoc S, SMLoc E) { 1775 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 1776 Op->RegShiftedReg.ShiftTy = ShTy; 1777 Op->RegShiftedReg.SrcReg = SrcReg; 1778 Op->RegShiftedReg.ShiftReg = ShiftReg; 1779 Op->RegShiftedReg.ShiftImm = ShiftImm; 1780 Op->StartLoc = S; 1781 Op->EndLoc = E; 1782 return Op; 1783 } 1784 1785 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 1786 unsigned SrcReg, 1787 unsigned ShiftImm, 1788 SMLoc S, SMLoc E) { 1789 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 1790 Op->RegShiftedImm.ShiftTy = ShTy; 1791 Op->RegShiftedImm.SrcReg = SrcReg; 1792 Op->RegShiftedImm.ShiftImm = ShiftImm; 1793 Op->StartLoc = S; 1794 Op->EndLoc = E; 1795 return Op; 1796 } 1797 1798 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 1799 SMLoc S, SMLoc E) { 1800 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 1801 Op->ShifterImm.isASR = isASR; 1802 Op->ShifterImm.Imm = Imm; 1803 Op->StartLoc = S; 1804 Op->EndLoc = E; 1805 return Op; 1806 } 1807 1808 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 1809 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 1810 Op->RotImm.Imm = Imm; 1811 Op->StartLoc = S; 1812 Op->EndLoc = E; 1813 return Op; 1814 } 1815 1816 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 1817 SMLoc S, SMLoc E) { 1818 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 1819 Op->Bitfield.LSB = LSB; 1820 Op->Bitfield.Width = Width; 1821 Op->StartLoc = S; 1822 Op->EndLoc = E; 1823 return Op; 1824 } 1825 1826 static ARMOperand * 1827 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 1828 SMLoc StartLoc, SMLoc EndLoc) { 1829 KindTy Kind = k_RegisterList; 1830 1831 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 1832 Kind = k_DPRRegisterList; 1833 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 1834 contains(Regs.front().first)) 1835 Kind = k_SPRRegisterList; 1836 1837 ARMOperand *Op = new ARMOperand(Kind); 1838 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 1839 I = Regs.begin(), E = Regs.end(); I != E; ++I) 1840 Op->Registers.push_back(I->first); 1841 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 1842 Op->StartLoc = StartLoc; 1843 Op->EndLoc = EndLoc; 1844 return Op; 1845 } 1846 1847 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 1848 SMLoc S, SMLoc E) { 1849 ARMOperand *Op = new ARMOperand(k_VectorList); 1850 Op->VectorList.RegNum = RegNum; 1851 Op->VectorList.Count = Count; 1852 Op->StartLoc = S; 1853 Op->EndLoc = E; 1854 return Op; 1855 } 1856 1857 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 1858 SMLoc S, SMLoc E) { 1859 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 1860 Op->VectorList.RegNum = RegNum; 1861 Op->VectorList.Count = Count; 1862 Op->StartLoc = S; 1863 Op->EndLoc = E; 1864 return Op; 1865 } 1866 1867 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 1868 unsigned Index, SMLoc S, SMLoc E) { 1869 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 1870 Op->VectorList.RegNum = RegNum; 1871 Op->VectorList.Count = Count; 1872 Op->VectorList.LaneIndex = Index; 1873 Op->StartLoc = S; 1874 Op->EndLoc = E; 1875 return Op; 1876 } 1877 1878 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 1879 MCContext &Ctx) { 1880 ARMOperand *Op = new ARMOperand(k_VectorIndex); 1881 Op->VectorIndex.Val = Idx; 1882 Op->StartLoc = S; 1883 Op->EndLoc = E; 1884 return Op; 1885 } 1886 1887 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 1888 ARMOperand *Op = new ARMOperand(k_Immediate); 1889 Op->Imm.Val = Val; 1890 Op->StartLoc = S; 1891 Op->EndLoc = E; 1892 return Op; 1893 } 1894 1895 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) { 1896 ARMOperand *Op = new ARMOperand(k_FPImmediate); 1897 Op->FPImm.Val = Val; 1898 Op->StartLoc = S; 1899 Op->EndLoc = S; 1900 return Op; 1901 } 1902 1903 static ARMOperand *CreateMem(unsigned BaseRegNum, 1904 const MCConstantExpr *OffsetImm, 1905 unsigned OffsetRegNum, 1906 ARM_AM::ShiftOpc ShiftType, 1907 unsigned ShiftImm, 1908 unsigned Alignment, 1909 bool isNegative, 1910 SMLoc S, SMLoc E) { 1911 ARMOperand *Op = new ARMOperand(k_Memory); 1912 Op->Memory.BaseRegNum = BaseRegNum; 1913 Op->Memory.OffsetImm = OffsetImm; 1914 Op->Memory.OffsetRegNum = OffsetRegNum; 1915 Op->Memory.ShiftType = ShiftType; 1916 Op->Memory.ShiftImm = ShiftImm; 1917 Op->Memory.Alignment = Alignment; 1918 Op->Memory.isNegative = isNegative; 1919 Op->StartLoc = S; 1920 Op->EndLoc = E; 1921 return Op; 1922 } 1923 1924 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 1925 ARM_AM::ShiftOpc ShiftTy, 1926 unsigned ShiftImm, 1927 SMLoc S, SMLoc E) { 1928 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 1929 Op->PostIdxReg.RegNum = RegNum; 1930 Op->PostIdxReg.isAdd = isAdd; 1931 Op->PostIdxReg.ShiftTy = ShiftTy; 1932 Op->PostIdxReg.ShiftImm = ShiftImm; 1933 Op->StartLoc = S; 1934 Op->EndLoc = E; 1935 return Op; 1936 } 1937 1938 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 1939 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 1940 Op->MBOpt.Val = Opt; 1941 Op->StartLoc = S; 1942 Op->EndLoc = S; 1943 return Op; 1944 } 1945 1946 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 1947 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 1948 Op->IFlags.Val = IFlags; 1949 Op->StartLoc = S; 1950 Op->EndLoc = S; 1951 return Op; 1952 } 1953 1954 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 1955 ARMOperand *Op = new ARMOperand(k_MSRMask); 1956 Op->MMask.Val = MMask; 1957 Op->StartLoc = S; 1958 Op->EndLoc = S; 1959 return Op; 1960 } 1961 }; 1962 1963 } // end anonymous namespace. 1964 1965 void ARMOperand::print(raw_ostream &OS) const { 1966 switch (Kind) { 1967 case k_FPImmediate: 1968 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm()) 1969 << ") >"; 1970 break; 1971 case k_CondCode: 1972 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 1973 break; 1974 case k_CCOut: 1975 OS << "<ccout " << getReg() << ">"; 1976 break; 1977 case k_ITCondMask: { 1978 static const char *MaskStr[] = { 1979 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 1980 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 1981 }; 1982 assert((ITMask.Mask & 0xf) == ITMask.Mask); 1983 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 1984 break; 1985 } 1986 case k_CoprocNum: 1987 OS << "<coprocessor number: " << getCoproc() << ">"; 1988 break; 1989 case k_CoprocReg: 1990 OS << "<coprocessor register: " << getCoproc() << ">"; 1991 break; 1992 case k_CoprocOption: 1993 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 1994 break; 1995 case k_MSRMask: 1996 OS << "<mask: " << getMSRMask() << ">"; 1997 break; 1998 case k_Immediate: 1999 getImm()->print(OS); 2000 break; 2001 case k_MemBarrierOpt: 2002 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2003 break; 2004 case k_Memory: 2005 OS << "<memory " 2006 << " base:" << Memory.BaseRegNum; 2007 OS << ">"; 2008 break; 2009 case k_PostIndexRegister: 2010 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2011 << PostIdxReg.RegNum; 2012 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2013 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2014 << PostIdxReg.ShiftImm; 2015 OS << ">"; 2016 break; 2017 case k_ProcIFlags: { 2018 OS << "<ARM_PROC::"; 2019 unsigned IFlags = getProcIFlags(); 2020 for (int i=2; i >= 0; --i) 2021 if (IFlags & (1 << i)) 2022 OS << ARM_PROC::IFlagsToString(1 << i); 2023 OS << ">"; 2024 break; 2025 } 2026 case k_Register: 2027 OS << "<register " << getReg() << ">"; 2028 break; 2029 case k_ShifterImmediate: 2030 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2031 << " #" << ShifterImm.Imm << ">"; 2032 break; 2033 case k_ShiftedRegister: 2034 OS << "<so_reg_reg " 2035 << RegShiftedReg.SrcReg << " " 2036 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2037 << " " << RegShiftedReg.ShiftReg << ">"; 2038 break; 2039 case k_ShiftedImmediate: 2040 OS << "<so_reg_imm " 2041 << RegShiftedImm.SrcReg << " " 2042 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2043 << " #" << RegShiftedImm.ShiftImm << ">"; 2044 break; 2045 case k_RotateImmediate: 2046 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2047 break; 2048 case k_BitfieldDescriptor: 2049 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2050 << ", width: " << Bitfield.Width << ">"; 2051 break; 2052 case k_RegisterList: 2053 case k_DPRRegisterList: 2054 case k_SPRRegisterList: { 2055 OS << "<register_list "; 2056 2057 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2058 for (SmallVectorImpl<unsigned>::const_iterator 2059 I = RegList.begin(), E = RegList.end(); I != E; ) { 2060 OS << *I; 2061 if (++I < E) OS << ", "; 2062 } 2063 2064 OS << ">"; 2065 break; 2066 } 2067 case k_VectorList: 2068 OS << "<vector_list " << VectorList.Count << " * " 2069 << VectorList.RegNum << ">"; 2070 break; 2071 case k_VectorListAllLanes: 2072 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2073 << VectorList.RegNum << ">"; 2074 break; 2075 case k_VectorListIndexed: 2076 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2077 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2078 break; 2079 case k_Token: 2080 OS << "'" << getToken() << "'"; 2081 break; 2082 case k_VectorIndex: 2083 OS << "<vectorindex " << getVectorIndex() << ">"; 2084 break; 2085 } 2086 } 2087 2088 /// @name Auto-generated Match Functions 2089 /// { 2090 2091 static unsigned MatchRegisterName(StringRef Name); 2092 2093 /// } 2094 2095 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2096 SMLoc &StartLoc, SMLoc &EndLoc) { 2097 RegNo = tryParseRegister(); 2098 2099 return (RegNo == (unsigned)-1); 2100 } 2101 2102 /// Try to parse a register name. The token must be an Identifier when called, 2103 /// and if it is a register name the token is eaten and the register number is 2104 /// returned. Otherwise return -1. 2105 /// 2106 int ARMAsmParser::tryParseRegister() { 2107 const AsmToken &Tok = Parser.getTok(); 2108 if (Tok.isNot(AsmToken::Identifier)) return -1; 2109 2110 // FIXME: Validate register for the current architecture; we have to do 2111 // validation later, so maybe there is no need for this here. 2112 std::string lowerCase = Tok.getString().lower(); 2113 unsigned RegNum = MatchRegisterName(lowerCase); 2114 if (!RegNum) { 2115 RegNum = StringSwitch<unsigned>(lowerCase) 2116 .Case("r13", ARM::SP) 2117 .Case("r14", ARM::LR) 2118 .Case("r15", ARM::PC) 2119 .Case("ip", ARM::R12) 2120 .Default(0); 2121 } 2122 if (!RegNum) return -1; 2123 2124 Parser.Lex(); // Eat identifier token. 2125 2126 return RegNum; 2127 } 2128 2129 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2130 // If a recoverable error occurs, return 1. If an irrecoverable error 2131 // occurs, return -1. An irrecoverable error is one where tokens have been 2132 // consumed in the process of trying to parse the shifter (i.e., when it is 2133 // indeed a shifter operand, but malformed). 2134 int ARMAsmParser::tryParseShiftRegister( 2135 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2136 SMLoc S = Parser.getTok().getLoc(); 2137 const AsmToken &Tok = Parser.getTok(); 2138 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2139 2140 std::string lowerCase = Tok.getString().lower(); 2141 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2142 .Case("lsl", ARM_AM::lsl) 2143 .Case("lsr", ARM_AM::lsr) 2144 .Case("asr", ARM_AM::asr) 2145 .Case("ror", ARM_AM::ror) 2146 .Case("rrx", ARM_AM::rrx) 2147 .Default(ARM_AM::no_shift); 2148 2149 if (ShiftTy == ARM_AM::no_shift) 2150 return 1; 2151 2152 Parser.Lex(); // Eat the operator. 2153 2154 // The source register for the shift has already been added to the 2155 // operand list, so we need to pop it off and combine it into the shifted 2156 // register operand instead. 2157 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2158 if (!PrevOp->isReg()) 2159 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2160 int SrcReg = PrevOp->getReg(); 2161 int64_t Imm = 0; 2162 int ShiftReg = 0; 2163 if (ShiftTy == ARM_AM::rrx) { 2164 // RRX Doesn't have an explicit shift amount. The encoder expects 2165 // the shift register to be the same as the source register. Seems odd, 2166 // but OK. 2167 ShiftReg = SrcReg; 2168 } else { 2169 // Figure out if this is shifted by a constant or a register (for non-RRX). 2170 if (Parser.getTok().is(AsmToken::Hash)) { 2171 Parser.Lex(); // Eat hash. 2172 SMLoc ImmLoc = Parser.getTok().getLoc(); 2173 const MCExpr *ShiftExpr = 0; 2174 if (getParser().ParseExpression(ShiftExpr)) { 2175 Error(ImmLoc, "invalid immediate shift value"); 2176 return -1; 2177 } 2178 // The expression must be evaluatable as an immediate. 2179 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2180 if (!CE) { 2181 Error(ImmLoc, "invalid immediate shift value"); 2182 return -1; 2183 } 2184 // Range check the immediate. 2185 // lsl, ror: 0 <= imm <= 31 2186 // lsr, asr: 0 <= imm <= 32 2187 Imm = CE->getValue(); 2188 if (Imm < 0 || 2189 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2190 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2191 Error(ImmLoc, "immediate shift value out of range"); 2192 return -1; 2193 } 2194 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2195 ShiftReg = tryParseRegister(); 2196 SMLoc L = Parser.getTok().getLoc(); 2197 if (ShiftReg == -1) { 2198 Error (L, "expected immediate or register in shift operand"); 2199 return -1; 2200 } 2201 } else { 2202 Error (Parser.getTok().getLoc(), 2203 "expected immediate or register in shift operand"); 2204 return -1; 2205 } 2206 } 2207 2208 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2209 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2210 ShiftReg, Imm, 2211 S, Parser.getTok().getLoc())); 2212 else 2213 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2214 S, Parser.getTok().getLoc())); 2215 2216 return 0; 2217 } 2218 2219 2220 /// Try to parse a register name. The token must be an Identifier when called. 2221 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 2222 /// if there is a "writeback". 'true' if it's not a register. 2223 /// 2224 /// TODO this is likely to change to allow different register types and or to 2225 /// parse for a specific register type. 2226 bool ARMAsmParser:: 2227 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2228 SMLoc S = Parser.getTok().getLoc(); 2229 int RegNo = tryParseRegister(); 2230 if (RegNo == -1) 2231 return true; 2232 2233 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2234 2235 const AsmToken &ExclaimTok = Parser.getTok(); 2236 if (ExclaimTok.is(AsmToken::Exclaim)) { 2237 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2238 ExclaimTok.getLoc())); 2239 Parser.Lex(); // Eat exclaim token 2240 return false; 2241 } 2242 2243 // Also check for an index operand. This is only legal for vector registers, 2244 // but that'll get caught OK in operand matching, so we don't need to 2245 // explicitly filter everything else out here. 2246 if (Parser.getTok().is(AsmToken::LBrac)) { 2247 SMLoc SIdx = Parser.getTok().getLoc(); 2248 Parser.Lex(); // Eat left bracket token. 2249 2250 const MCExpr *ImmVal; 2251 if (getParser().ParseExpression(ImmVal)) 2252 return MatchOperand_ParseFail; 2253 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2254 if (!MCE) { 2255 TokError("immediate value expected for vector index"); 2256 return MatchOperand_ParseFail; 2257 } 2258 2259 SMLoc E = Parser.getTok().getLoc(); 2260 if (Parser.getTok().isNot(AsmToken::RBrac)) { 2261 Error(E, "']' expected"); 2262 return MatchOperand_ParseFail; 2263 } 2264 2265 Parser.Lex(); // Eat right bracket token. 2266 2267 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2268 SIdx, E, 2269 getContext())); 2270 } 2271 2272 return false; 2273 } 2274 2275 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 2276 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2277 /// "c5", ... 2278 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2279 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2280 // but efficient. 2281 switch (Name.size()) { 2282 default: break; 2283 case 2: 2284 if (Name[0] != CoprocOp) 2285 return -1; 2286 switch (Name[1]) { 2287 default: return -1; 2288 case '0': return 0; 2289 case '1': return 1; 2290 case '2': return 2; 2291 case '3': return 3; 2292 case '4': return 4; 2293 case '5': return 5; 2294 case '6': return 6; 2295 case '7': return 7; 2296 case '8': return 8; 2297 case '9': return 9; 2298 } 2299 break; 2300 case 3: 2301 if (Name[0] != CoprocOp || Name[1] != '1') 2302 return -1; 2303 switch (Name[2]) { 2304 default: return -1; 2305 case '0': return 10; 2306 case '1': return 11; 2307 case '2': return 12; 2308 case '3': return 13; 2309 case '4': return 14; 2310 case '5': return 15; 2311 } 2312 break; 2313 } 2314 2315 return -1; 2316 } 2317 2318 /// parseITCondCode - Try to parse a condition code for an IT instruction. 2319 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2320 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2321 SMLoc S = Parser.getTok().getLoc(); 2322 const AsmToken &Tok = Parser.getTok(); 2323 if (!Tok.is(AsmToken::Identifier)) 2324 return MatchOperand_NoMatch; 2325 unsigned CC = StringSwitch<unsigned>(Tok.getString()) 2326 .Case("eq", ARMCC::EQ) 2327 .Case("ne", ARMCC::NE) 2328 .Case("hs", ARMCC::HS) 2329 .Case("cs", ARMCC::HS) 2330 .Case("lo", ARMCC::LO) 2331 .Case("cc", ARMCC::LO) 2332 .Case("mi", ARMCC::MI) 2333 .Case("pl", ARMCC::PL) 2334 .Case("vs", ARMCC::VS) 2335 .Case("vc", ARMCC::VC) 2336 .Case("hi", ARMCC::HI) 2337 .Case("ls", ARMCC::LS) 2338 .Case("ge", ARMCC::GE) 2339 .Case("lt", ARMCC::LT) 2340 .Case("gt", ARMCC::GT) 2341 .Case("le", ARMCC::LE) 2342 .Case("al", ARMCC::AL) 2343 .Default(~0U); 2344 if (CC == ~0U) 2345 return MatchOperand_NoMatch; 2346 Parser.Lex(); // Eat the token. 2347 2348 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2349 2350 return MatchOperand_Success; 2351 } 2352 2353 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2354 /// token must be an Identifier when called, and if it is a coprocessor 2355 /// number, the token is eaten and the operand is added to the operand list. 2356 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2357 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2358 SMLoc S = Parser.getTok().getLoc(); 2359 const AsmToken &Tok = Parser.getTok(); 2360 if (Tok.isNot(AsmToken::Identifier)) 2361 return MatchOperand_NoMatch; 2362 2363 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2364 if (Num == -1) 2365 return MatchOperand_NoMatch; 2366 2367 Parser.Lex(); // Eat identifier token. 2368 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2369 return MatchOperand_Success; 2370 } 2371 2372 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2373 /// token must be an Identifier when called, and if it is a coprocessor 2374 /// number, the token is eaten and the operand is added to the operand list. 2375 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2376 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2377 SMLoc S = Parser.getTok().getLoc(); 2378 const AsmToken &Tok = Parser.getTok(); 2379 if (Tok.isNot(AsmToken::Identifier)) 2380 return MatchOperand_NoMatch; 2381 2382 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2383 if (Reg == -1) 2384 return MatchOperand_NoMatch; 2385 2386 Parser.Lex(); // Eat identifier token. 2387 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2388 return MatchOperand_Success; 2389 } 2390 2391 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2392 /// coproc_option : '{' imm0_255 '}' 2393 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2394 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2395 SMLoc S = Parser.getTok().getLoc(); 2396 2397 // If this isn't a '{', this isn't a coprocessor immediate operand. 2398 if (Parser.getTok().isNot(AsmToken::LCurly)) 2399 return MatchOperand_NoMatch; 2400 Parser.Lex(); // Eat the '{' 2401 2402 const MCExpr *Expr; 2403 SMLoc Loc = Parser.getTok().getLoc(); 2404 if (getParser().ParseExpression(Expr)) { 2405 Error(Loc, "illegal expression"); 2406 return MatchOperand_ParseFail; 2407 } 2408 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2409 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2410 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2411 return MatchOperand_ParseFail; 2412 } 2413 int Val = CE->getValue(); 2414 2415 // Check for and consume the closing '}' 2416 if (Parser.getTok().isNot(AsmToken::RCurly)) 2417 return MatchOperand_ParseFail; 2418 SMLoc E = Parser.getTok().getLoc(); 2419 Parser.Lex(); // Eat the '}' 2420 2421 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2422 return MatchOperand_Success; 2423 } 2424 2425 // For register list parsing, we need to map from raw GPR register numbering 2426 // to the enumeration values. The enumeration values aren't sorted by 2427 // register number due to our using "sp", "lr" and "pc" as canonical names. 2428 static unsigned getNextRegister(unsigned Reg) { 2429 // If this is a GPR, we need to do it manually, otherwise we can rely 2430 // on the sort ordering of the enumeration since the other reg-classes 2431 // are sane. 2432 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2433 return Reg + 1; 2434 switch(Reg) { 2435 default: assert(0 && "Invalid GPR number!"); 2436 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2437 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2438 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2439 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2440 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2441 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2442 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2443 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2444 } 2445 } 2446 2447 // Return the low-subreg of a given Q register. 2448 static unsigned getDRegFromQReg(unsigned QReg) { 2449 switch (QReg) { 2450 default: llvm_unreachable("expected a Q register!"); 2451 case ARM::Q0: return ARM::D0; 2452 case ARM::Q1: return ARM::D2; 2453 case ARM::Q2: return ARM::D4; 2454 case ARM::Q3: return ARM::D6; 2455 case ARM::Q4: return ARM::D8; 2456 case ARM::Q5: return ARM::D10; 2457 case ARM::Q6: return ARM::D12; 2458 case ARM::Q7: return ARM::D14; 2459 case ARM::Q8: return ARM::D16; 2460 case ARM::Q9: return ARM::D18; 2461 case ARM::Q10: return ARM::D20; 2462 case ARM::Q11: return ARM::D22; 2463 case ARM::Q12: return ARM::D24; 2464 case ARM::Q13: return ARM::D26; 2465 case ARM::Q14: return ARM::D28; 2466 case ARM::Q15: return ARM::D30; 2467 } 2468 } 2469 2470 /// Parse a register list. 2471 bool ARMAsmParser:: 2472 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2473 assert(Parser.getTok().is(AsmToken::LCurly) && 2474 "Token is not a Left Curly Brace"); 2475 SMLoc S = Parser.getTok().getLoc(); 2476 Parser.Lex(); // Eat '{' token. 2477 SMLoc RegLoc = Parser.getTok().getLoc(); 2478 2479 // Check the first register in the list to see what register class 2480 // this is a list of. 2481 int Reg = tryParseRegister(); 2482 if (Reg == -1) 2483 return Error(RegLoc, "register expected"); 2484 2485 // The reglist instructions have at most 16 registers, so reserve 2486 // space for that many. 2487 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2488 2489 // Allow Q regs and just interpret them as the two D sub-registers. 2490 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2491 Reg = getDRegFromQReg(Reg); 2492 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2493 ++Reg; 2494 } 2495 const MCRegisterClass *RC; 2496 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2497 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2498 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2499 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2500 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2501 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2502 else 2503 return Error(RegLoc, "invalid register in register list"); 2504 2505 // Store the register. 2506 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2507 2508 // This starts immediately after the first register token in the list, 2509 // so we can see either a comma or a minus (range separator) as a legal 2510 // next token. 2511 while (Parser.getTok().is(AsmToken::Comma) || 2512 Parser.getTok().is(AsmToken::Minus)) { 2513 if (Parser.getTok().is(AsmToken::Minus)) { 2514 Parser.Lex(); // Eat the minus. 2515 SMLoc EndLoc = Parser.getTok().getLoc(); 2516 int EndReg = tryParseRegister(); 2517 if (EndReg == -1) 2518 return Error(EndLoc, "register expected"); 2519 // Allow Q regs and just interpret them as the two D sub-registers. 2520 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2521 EndReg = getDRegFromQReg(EndReg) + 1; 2522 // If the register is the same as the start reg, there's nothing 2523 // more to do. 2524 if (Reg == EndReg) 2525 continue; 2526 // The register must be in the same register class as the first. 2527 if (!RC->contains(EndReg)) 2528 return Error(EndLoc, "invalid register in register list"); 2529 // Ranges must go from low to high. 2530 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 2531 return Error(EndLoc, "bad range in register list"); 2532 2533 // Add all the registers in the range to the register list. 2534 while (Reg != EndReg) { 2535 Reg = getNextRegister(Reg); 2536 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2537 } 2538 continue; 2539 } 2540 Parser.Lex(); // Eat the comma. 2541 RegLoc = Parser.getTok().getLoc(); 2542 int OldReg = Reg; 2543 Reg = tryParseRegister(); 2544 if (Reg == -1) 2545 return Error(RegLoc, "register expected"); 2546 // Allow Q regs and just interpret them as the two D sub-registers. 2547 bool isQReg = false; 2548 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2549 Reg = getDRegFromQReg(Reg); 2550 isQReg = true; 2551 } 2552 // The register must be in the same register class as the first. 2553 if (!RC->contains(Reg)) 2554 return Error(RegLoc, "invalid register in register list"); 2555 // List must be monotonically increasing. 2556 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg)) 2557 return Error(RegLoc, "register list not in ascending order"); 2558 // VFP register lists must also be contiguous. 2559 // It's OK to use the enumeration values directly here rather, as the 2560 // VFP register classes have the enum sorted properly. 2561 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2562 Reg != OldReg + 1) 2563 return Error(RegLoc, "non-contiguous register range"); 2564 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2565 if (isQReg) 2566 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 2567 } 2568 2569 SMLoc E = Parser.getTok().getLoc(); 2570 if (Parser.getTok().isNot(AsmToken::RCurly)) 2571 return Error(E, "'}' expected"); 2572 Parser.Lex(); // Eat '}' token. 2573 2574 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 2575 return false; 2576 } 2577 2578 // Helper function to parse the lane index for vector lists. 2579 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2580 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) { 2581 Index = 0; // Always return a defined index value. 2582 if (Parser.getTok().is(AsmToken::LBrac)) { 2583 Parser.Lex(); // Eat the '['. 2584 if (Parser.getTok().is(AsmToken::RBrac)) { 2585 // "Dn[]" is the 'all lanes' syntax. 2586 LaneKind = AllLanes; 2587 Parser.Lex(); // Eat the ']'. 2588 return MatchOperand_Success; 2589 } 2590 if (Parser.getTok().is(AsmToken::Integer)) { 2591 int64_t Val = Parser.getTok().getIntVal(); 2592 // Make this range check context sensitive for .8, .16, .32. 2593 if (Val < 0 && Val > 7) 2594 Error(Parser.getTok().getLoc(), "lane index out of range"); 2595 Index = Val; 2596 LaneKind = IndexedLane; 2597 Parser.Lex(); // Eat the token; 2598 if (Parser.getTok().isNot(AsmToken::RBrac)) 2599 Error(Parser.getTok().getLoc(), "']' expected"); 2600 Parser.Lex(); // Eat the ']'. 2601 return MatchOperand_Success; 2602 } 2603 Error(Parser.getTok().getLoc(), "lane index must be empty or an integer"); 2604 return MatchOperand_ParseFail; 2605 } 2606 LaneKind = NoLanes; 2607 return MatchOperand_Success; 2608 } 2609 2610 // parse a vector register list 2611 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2612 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2613 VectorLaneTy LaneKind; 2614 unsigned LaneIndex; 2615 SMLoc S = Parser.getTok().getLoc(); 2616 // As an extension (to match gas), support a plain D register or Q register 2617 // (without encosing curly braces) as a single or double entry list, 2618 // respectively. 2619 if (Parser.getTok().is(AsmToken::Identifier)) { 2620 int Reg = tryParseRegister(); 2621 if (Reg == -1) 2622 return MatchOperand_NoMatch; 2623 SMLoc E = Parser.getTok().getLoc(); 2624 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 2625 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 2626 if (Res != MatchOperand_Success) 2627 return Res; 2628 switch (LaneKind) { 2629 default: 2630 assert(0 && "unexpected lane kind!"); 2631 case NoLanes: 2632 E = Parser.getTok().getLoc(); 2633 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, S, E)); 2634 break; 2635 case AllLanes: 2636 E = Parser.getTok().getLoc(); 2637 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, S, E)); 2638 break; 2639 case IndexedLane: 2640 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 2641 LaneIndex, S,E)); 2642 break; 2643 } 2644 return MatchOperand_Success; 2645 } 2646 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2647 Reg = getDRegFromQReg(Reg); 2648 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 2649 if (Res != MatchOperand_Success) 2650 return Res; 2651 switch (LaneKind) { 2652 default: 2653 assert(0 && "unexpected lane kind!"); 2654 case NoLanes: 2655 E = Parser.getTok().getLoc(); 2656 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, S, E)); 2657 break; 2658 case AllLanes: 2659 E = Parser.getTok().getLoc(); 2660 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, S, E)); 2661 break; 2662 case IndexedLane: 2663 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 2664 LaneIndex, S,E)); 2665 break; 2666 } 2667 return MatchOperand_Success; 2668 } 2669 Error(S, "vector register expected"); 2670 return MatchOperand_ParseFail; 2671 } 2672 2673 if (Parser.getTok().isNot(AsmToken::LCurly)) 2674 return MatchOperand_NoMatch; 2675 2676 Parser.Lex(); // Eat '{' token. 2677 SMLoc RegLoc = Parser.getTok().getLoc(); 2678 2679 int Reg = tryParseRegister(); 2680 if (Reg == -1) { 2681 Error(RegLoc, "register expected"); 2682 return MatchOperand_ParseFail; 2683 } 2684 unsigned Count = 1; 2685 unsigned FirstReg = Reg; 2686 // The list is of D registers, but we also allow Q regs and just interpret 2687 // them as the two D sub-registers. 2688 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2689 FirstReg = Reg = getDRegFromQReg(Reg); 2690 ++Reg; 2691 ++Count; 2692 } 2693 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success) 2694 return MatchOperand_ParseFail; 2695 2696 while (Parser.getTok().is(AsmToken::Comma) || 2697 Parser.getTok().is(AsmToken::Minus)) { 2698 if (Parser.getTok().is(AsmToken::Minus)) { 2699 Parser.Lex(); // Eat the minus. 2700 SMLoc EndLoc = Parser.getTok().getLoc(); 2701 int EndReg = tryParseRegister(); 2702 if (EndReg == -1) { 2703 Error(EndLoc, "register expected"); 2704 return MatchOperand_ParseFail; 2705 } 2706 // Allow Q regs and just interpret them as the two D sub-registers. 2707 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2708 EndReg = getDRegFromQReg(EndReg) + 1; 2709 // If the register is the same as the start reg, there's nothing 2710 // more to do. 2711 if (Reg == EndReg) 2712 continue; 2713 // The register must be in the same register class as the first. 2714 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 2715 Error(EndLoc, "invalid register in register list"); 2716 return MatchOperand_ParseFail; 2717 } 2718 // Ranges must go from low to high. 2719 if (Reg > EndReg) { 2720 Error(EndLoc, "bad range in register list"); 2721 return MatchOperand_ParseFail; 2722 } 2723 // Parse the lane specifier if present. 2724 VectorLaneTy NextLaneKind; 2725 unsigned NextLaneIndex; 2726 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 2727 return MatchOperand_ParseFail; 2728 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 2729 Error(EndLoc, "mismatched lane index in register list"); 2730 return MatchOperand_ParseFail; 2731 } 2732 EndLoc = Parser.getTok().getLoc(); 2733 2734 // Add all the registers in the range to the register list. 2735 Count += EndReg - Reg; 2736 Reg = EndReg; 2737 continue; 2738 } 2739 Parser.Lex(); // Eat the comma. 2740 RegLoc = Parser.getTok().getLoc(); 2741 int OldReg = Reg; 2742 Reg = tryParseRegister(); 2743 if (Reg == -1) { 2744 Error(RegLoc, "register expected"); 2745 return MatchOperand_ParseFail; 2746 } 2747 // vector register lists must be contiguous. 2748 // It's OK to use the enumeration values directly here rather, as the 2749 // VFP register classes have the enum sorted properly. 2750 // 2751 // The list is of D registers, but we also allow Q regs and just interpret 2752 // them as the two D sub-registers. 2753 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2754 Reg = getDRegFromQReg(Reg); 2755 if (Reg != OldReg + 1) { 2756 Error(RegLoc, "non-contiguous register range"); 2757 return MatchOperand_ParseFail; 2758 } 2759 ++Reg; 2760 Count += 2; 2761 // Parse the lane specifier if present. 2762 VectorLaneTy NextLaneKind; 2763 unsigned NextLaneIndex; 2764 SMLoc EndLoc = Parser.getTok().getLoc(); 2765 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 2766 return MatchOperand_ParseFail; 2767 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 2768 Error(EndLoc, "mismatched lane index in register list"); 2769 return MatchOperand_ParseFail; 2770 } 2771 continue; 2772 } 2773 // Normal D register. Just check that it's contiguous and keep going. 2774 if (Reg != OldReg + 1) { 2775 Error(RegLoc, "non-contiguous register range"); 2776 return MatchOperand_ParseFail; 2777 } 2778 ++Count; 2779 // Parse the lane specifier if present. 2780 VectorLaneTy NextLaneKind; 2781 unsigned NextLaneIndex; 2782 SMLoc EndLoc = Parser.getTok().getLoc(); 2783 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 2784 return MatchOperand_ParseFail; 2785 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 2786 Error(EndLoc, "mismatched lane index in register list"); 2787 return MatchOperand_ParseFail; 2788 } 2789 } 2790 2791 SMLoc E = Parser.getTok().getLoc(); 2792 if (Parser.getTok().isNot(AsmToken::RCurly)) { 2793 Error(E, "'}' expected"); 2794 return MatchOperand_ParseFail; 2795 } 2796 Parser.Lex(); // Eat '}' token. 2797 2798 switch (LaneKind) { 2799 default: 2800 assert(0 && "unexpected lane kind in register list."); 2801 case NoLanes: 2802 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E)); 2803 break; 2804 case AllLanes: 2805 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 2806 S, E)); 2807 break; 2808 case IndexedLane: 2809 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 2810 LaneIndex, S, E)); 2811 break; 2812 } 2813 return MatchOperand_Success; 2814 } 2815 2816 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 2817 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2818 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2819 SMLoc S = Parser.getTok().getLoc(); 2820 const AsmToken &Tok = Parser.getTok(); 2821 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2822 StringRef OptStr = Tok.getString(); 2823 2824 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 2825 .Case("sy", ARM_MB::SY) 2826 .Case("st", ARM_MB::ST) 2827 .Case("sh", ARM_MB::ISH) 2828 .Case("ish", ARM_MB::ISH) 2829 .Case("shst", ARM_MB::ISHST) 2830 .Case("ishst", ARM_MB::ISHST) 2831 .Case("nsh", ARM_MB::NSH) 2832 .Case("un", ARM_MB::NSH) 2833 .Case("nshst", ARM_MB::NSHST) 2834 .Case("unst", ARM_MB::NSHST) 2835 .Case("osh", ARM_MB::OSH) 2836 .Case("oshst", ARM_MB::OSHST) 2837 .Default(~0U); 2838 2839 if (Opt == ~0U) 2840 return MatchOperand_NoMatch; 2841 2842 Parser.Lex(); // Eat identifier token. 2843 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 2844 return MatchOperand_Success; 2845 } 2846 2847 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 2848 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2849 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2850 SMLoc S = Parser.getTok().getLoc(); 2851 const AsmToken &Tok = Parser.getTok(); 2852 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2853 StringRef IFlagsStr = Tok.getString(); 2854 2855 // An iflags string of "none" is interpreted to mean that none of the AIF 2856 // bits are set. Not a terribly useful instruction, but a valid encoding. 2857 unsigned IFlags = 0; 2858 if (IFlagsStr != "none") { 2859 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 2860 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 2861 .Case("a", ARM_PROC::A) 2862 .Case("i", ARM_PROC::I) 2863 .Case("f", ARM_PROC::F) 2864 .Default(~0U); 2865 2866 // If some specific iflag is already set, it means that some letter is 2867 // present more than once, this is not acceptable. 2868 if (Flag == ~0U || (IFlags & Flag)) 2869 return MatchOperand_NoMatch; 2870 2871 IFlags |= Flag; 2872 } 2873 } 2874 2875 Parser.Lex(); // Eat identifier token. 2876 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 2877 return MatchOperand_Success; 2878 } 2879 2880 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 2881 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2882 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2883 SMLoc S = Parser.getTok().getLoc(); 2884 const AsmToken &Tok = Parser.getTok(); 2885 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2886 StringRef Mask = Tok.getString(); 2887 2888 if (isMClass()) { 2889 // See ARMv6-M 10.1.1 2890 unsigned FlagsVal = StringSwitch<unsigned>(Mask) 2891 .Case("apsr", 0) 2892 .Case("iapsr", 1) 2893 .Case("eapsr", 2) 2894 .Case("xpsr", 3) 2895 .Case("ipsr", 5) 2896 .Case("epsr", 6) 2897 .Case("iepsr", 7) 2898 .Case("msp", 8) 2899 .Case("psp", 9) 2900 .Case("primask", 16) 2901 .Case("basepri", 17) 2902 .Case("basepri_max", 18) 2903 .Case("faultmask", 19) 2904 .Case("control", 20) 2905 .Default(~0U); 2906 2907 if (FlagsVal == ~0U) 2908 return MatchOperand_NoMatch; 2909 2910 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19) 2911 // basepri, basepri_max and faultmask only valid for V7m. 2912 return MatchOperand_NoMatch; 2913 2914 Parser.Lex(); // Eat identifier token. 2915 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 2916 return MatchOperand_Success; 2917 } 2918 2919 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 2920 size_t Start = 0, Next = Mask.find('_'); 2921 StringRef Flags = ""; 2922 std::string SpecReg = Mask.slice(Start, Next).lower(); 2923 if (Next != StringRef::npos) 2924 Flags = Mask.slice(Next+1, Mask.size()); 2925 2926 // FlagsVal contains the complete mask: 2927 // 3-0: Mask 2928 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 2929 unsigned FlagsVal = 0; 2930 2931 if (SpecReg == "apsr") { 2932 FlagsVal = StringSwitch<unsigned>(Flags) 2933 .Case("nzcvq", 0x8) // same as CPSR_f 2934 .Case("g", 0x4) // same as CPSR_s 2935 .Case("nzcvqg", 0xc) // same as CPSR_fs 2936 .Default(~0U); 2937 2938 if (FlagsVal == ~0U) { 2939 if (!Flags.empty()) 2940 return MatchOperand_NoMatch; 2941 else 2942 FlagsVal = 8; // No flag 2943 } 2944 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 2945 if (Flags == "all") // cpsr_all is an alias for cpsr_fc 2946 Flags = "fc"; 2947 for (int i = 0, e = Flags.size(); i != e; ++i) { 2948 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 2949 .Case("c", 1) 2950 .Case("x", 2) 2951 .Case("s", 4) 2952 .Case("f", 8) 2953 .Default(~0U); 2954 2955 // If some specific flag is already set, it means that some letter is 2956 // present more than once, this is not acceptable. 2957 if (FlagsVal == ~0U || (FlagsVal & Flag)) 2958 return MatchOperand_NoMatch; 2959 FlagsVal |= Flag; 2960 } 2961 } else // No match for special register. 2962 return MatchOperand_NoMatch; 2963 2964 // Special register without flags is NOT equivalent to "fc" flags. 2965 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 2966 // two lines would enable gas compatibility at the expense of breaking 2967 // round-tripping. 2968 // 2969 // if (!FlagsVal) 2970 // FlagsVal = 0x9; 2971 2972 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 2973 if (SpecReg == "spsr") 2974 FlagsVal |= 16; 2975 2976 Parser.Lex(); // Eat identifier token. 2977 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 2978 return MatchOperand_Success; 2979 } 2980 2981 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2982 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 2983 int Low, int High) { 2984 const AsmToken &Tok = Parser.getTok(); 2985 if (Tok.isNot(AsmToken::Identifier)) { 2986 Error(Parser.getTok().getLoc(), Op + " operand expected."); 2987 return MatchOperand_ParseFail; 2988 } 2989 StringRef ShiftName = Tok.getString(); 2990 std::string LowerOp = Op.lower(); 2991 std::string UpperOp = Op.upper(); 2992 if (ShiftName != LowerOp && ShiftName != UpperOp) { 2993 Error(Parser.getTok().getLoc(), Op + " operand expected."); 2994 return MatchOperand_ParseFail; 2995 } 2996 Parser.Lex(); // Eat shift type token. 2997 2998 // There must be a '#' and a shift amount. 2999 if (Parser.getTok().isNot(AsmToken::Hash)) { 3000 Error(Parser.getTok().getLoc(), "'#' expected"); 3001 return MatchOperand_ParseFail; 3002 } 3003 Parser.Lex(); // Eat hash token. 3004 3005 const MCExpr *ShiftAmount; 3006 SMLoc Loc = Parser.getTok().getLoc(); 3007 if (getParser().ParseExpression(ShiftAmount)) { 3008 Error(Loc, "illegal expression"); 3009 return MatchOperand_ParseFail; 3010 } 3011 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3012 if (!CE) { 3013 Error(Loc, "constant expression expected"); 3014 return MatchOperand_ParseFail; 3015 } 3016 int Val = CE->getValue(); 3017 if (Val < Low || Val > High) { 3018 Error(Loc, "immediate value out of range"); 3019 return MatchOperand_ParseFail; 3020 } 3021 3022 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 3023 3024 return MatchOperand_Success; 3025 } 3026 3027 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3028 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3029 const AsmToken &Tok = Parser.getTok(); 3030 SMLoc S = Tok.getLoc(); 3031 if (Tok.isNot(AsmToken::Identifier)) { 3032 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3033 return MatchOperand_ParseFail; 3034 } 3035 int Val = StringSwitch<int>(Tok.getString()) 3036 .Case("be", 1) 3037 .Case("le", 0) 3038 .Default(-1); 3039 Parser.Lex(); // Eat the token. 3040 3041 if (Val == -1) { 3042 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3043 return MatchOperand_ParseFail; 3044 } 3045 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3046 getContext()), 3047 S, Parser.getTok().getLoc())); 3048 return MatchOperand_Success; 3049 } 3050 3051 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3052 /// instructions. Legal values are: 3053 /// lsl #n 'n' in [0,31] 3054 /// asr #n 'n' in [1,32] 3055 /// n == 32 encoded as n == 0. 3056 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3057 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3058 const AsmToken &Tok = Parser.getTok(); 3059 SMLoc S = Tok.getLoc(); 3060 if (Tok.isNot(AsmToken::Identifier)) { 3061 Error(S, "shift operator 'asr' or 'lsl' expected"); 3062 return MatchOperand_ParseFail; 3063 } 3064 StringRef ShiftName = Tok.getString(); 3065 bool isASR; 3066 if (ShiftName == "lsl" || ShiftName == "LSL") 3067 isASR = false; 3068 else if (ShiftName == "asr" || ShiftName == "ASR") 3069 isASR = true; 3070 else { 3071 Error(S, "shift operator 'asr' or 'lsl' expected"); 3072 return MatchOperand_ParseFail; 3073 } 3074 Parser.Lex(); // Eat the operator. 3075 3076 // A '#' and a shift amount. 3077 if (Parser.getTok().isNot(AsmToken::Hash)) { 3078 Error(Parser.getTok().getLoc(), "'#' expected"); 3079 return MatchOperand_ParseFail; 3080 } 3081 Parser.Lex(); // Eat hash token. 3082 3083 const MCExpr *ShiftAmount; 3084 SMLoc E = Parser.getTok().getLoc(); 3085 if (getParser().ParseExpression(ShiftAmount)) { 3086 Error(E, "malformed shift expression"); 3087 return MatchOperand_ParseFail; 3088 } 3089 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3090 if (!CE) { 3091 Error(E, "shift amount must be an immediate"); 3092 return MatchOperand_ParseFail; 3093 } 3094 3095 int64_t Val = CE->getValue(); 3096 if (isASR) { 3097 // Shift amount must be in [1,32] 3098 if (Val < 1 || Val > 32) { 3099 Error(E, "'asr' shift amount must be in range [1,32]"); 3100 return MatchOperand_ParseFail; 3101 } 3102 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3103 if (isThumb() && Val == 32) { 3104 Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 3105 return MatchOperand_ParseFail; 3106 } 3107 if (Val == 32) Val = 0; 3108 } else { 3109 // Shift amount must be in [1,32] 3110 if (Val < 0 || Val > 31) { 3111 Error(E, "'lsr' shift amount must be in range [0,31]"); 3112 return MatchOperand_ParseFail; 3113 } 3114 } 3115 3116 E = Parser.getTok().getLoc(); 3117 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 3118 3119 return MatchOperand_Success; 3120 } 3121 3122 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3123 /// of instructions. Legal values are: 3124 /// ror #n 'n' in {0, 8, 16, 24} 3125 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3126 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3127 const AsmToken &Tok = Parser.getTok(); 3128 SMLoc S = Tok.getLoc(); 3129 if (Tok.isNot(AsmToken::Identifier)) 3130 return MatchOperand_NoMatch; 3131 StringRef ShiftName = Tok.getString(); 3132 if (ShiftName != "ror" && ShiftName != "ROR") 3133 return MatchOperand_NoMatch; 3134 Parser.Lex(); // Eat the operator. 3135 3136 // A '#' and a rotate amount. 3137 if (Parser.getTok().isNot(AsmToken::Hash)) { 3138 Error(Parser.getTok().getLoc(), "'#' expected"); 3139 return MatchOperand_ParseFail; 3140 } 3141 Parser.Lex(); // Eat hash token. 3142 3143 const MCExpr *ShiftAmount; 3144 SMLoc E = Parser.getTok().getLoc(); 3145 if (getParser().ParseExpression(ShiftAmount)) { 3146 Error(E, "malformed rotate expression"); 3147 return MatchOperand_ParseFail; 3148 } 3149 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3150 if (!CE) { 3151 Error(E, "rotate amount must be an immediate"); 3152 return MatchOperand_ParseFail; 3153 } 3154 3155 int64_t Val = CE->getValue(); 3156 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 3157 // normally, zero is represented in asm by omitting the rotate operand 3158 // entirely. 3159 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 3160 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 3161 return MatchOperand_ParseFail; 3162 } 3163 3164 E = Parser.getTok().getLoc(); 3165 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 3166 3167 return MatchOperand_Success; 3168 } 3169 3170 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3171 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3172 SMLoc S = Parser.getTok().getLoc(); 3173 // The bitfield descriptor is really two operands, the LSB and the width. 3174 if (Parser.getTok().isNot(AsmToken::Hash)) { 3175 Error(Parser.getTok().getLoc(), "'#' expected"); 3176 return MatchOperand_ParseFail; 3177 } 3178 Parser.Lex(); // Eat hash token. 3179 3180 const MCExpr *LSBExpr; 3181 SMLoc E = Parser.getTok().getLoc(); 3182 if (getParser().ParseExpression(LSBExpr)) { 3183 Error(E, "malformed immediate expression"); 3184 return MatchOperand_ParseFail; 3185 } 3186 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3187 if (!CE) { 3188 Error(E, "'lsb' operand must be an immediate"); 3189 return MatchOperand_ParseFail; 3190 } 3191 3192 int64_t LSB = CE->getValue(); 3193 // The LSB must be in the range [0,31] 3194 if (LSB < 0 || LSB > 31) { 3195 Error(E, "'lsb' operand must be in the range [0,31]"); 3196 return MatchOperand_ParseFail; 3197 } 3198 E = Parser.getTok().getLoc(); 3199 3200 // Expect another immediate operand. 3201 if (Parser.getTok().isNot(AsmToken::Comma)) { 3202 Error(Parser.getTok().getLoc(), "too few operands"); 3203 return MatchOperand_ParseFail; 3204 } 3205 Parser.Lex(); // Eat hash token. 3206 if (Parser.getTok().isNot(AsmToken::Hash)) { 3207 Error(Parser.getTok().getLoc(), "'#' expected"); 3208 return MatchOperand_ParseFail; 3209 } 3210 Parser.Lex(); // Eat hash token. 3211 3212 const MCExpr *WidthExpr; 3213 if (getParser().ParseExpression(WidthExpr)) { 3214 Error(E, "malformed immediate expression"); 3215 return MatchOperand_ParseFail; 3216 } 3217 CE = dyn_cast<MCConstantExpr>(WidthExpr); 3218 if (!CE) { 3219 Error(E, "'width' operand must be an immediate"); 3220 return MatchOperand_ParseFail; 3221 } 3222 3223 int64_t Width = CE->getValue(); 3224 // The LSB must be in the range [1,32-lsb] 3225 if (Width < 1 || Width > 32 - LSB) { 3226 Error(E, "'width' operand must be in the range [1,32-lsb]"); 3227 return MatchOperand_ParseFail; 3228 } 3229 E = Parser.getTok().getLoc(); 3230 3231 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3232 3233 return MatchOperand_Success; 3234 } 3235 3236 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3237 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3238 // Check for a post-index addressing register operand. Specifically: 3239 // postidx_reg := '+' register {, shift} 3240 // | '-' register {, shift} 3241 // | register {, shift} 3242 3243 // This method must return MatchOperand_NoMatch without consuming any tokens 3244 // in the case where there is no match, as other alternatives take other 3245 // parse methods. 3246 AsmToken Tok = Parser.getTok(); 3247 SMLoc S = Tok.getLoc(); 3248 bool haveEaten = false; 3249 bool isAdd = true; 3250 int Reg = -1; 3251 if (Tok.is(AsmToken::Plus)) { 3252 Parser.Lex(); // Eat the '+' token. 3253 haveEaten = true; 3254 } else if (Tok.is(AsmToken::Minus)) { 3255 Parser.Lex(); // Eat the '-' token. 3256 isAdd = false; 3257 haveEaten = true; 3258 } 3259 if (Parser.getTok().is(AsmToken::Identifier)) 3260 Reg = tryParseRegister(); 3261 if (Reg == -1) { 3262 if (!haveEaten) 3263 return MatchOperand_NoMatch; 3264 Error(Parser.getTok().getLoc(), "register expected"); 3265 return MatchOperand_ParseFail; 3266 } 3267 SMLoc E = Parser.getTok().getLoc(); 3268 3269 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3270 unsigned ShiftImm = 0; 3271 if (Parser.getTok().is(AsmToken::Comma)) { 3272 Parser.Lex(); // Eat the ','. 3273 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 3274 return MatchOperand_ParseFail; 3275 } 3276 3277 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3278 ShiftImm, S, E)); 3279 3280 return MatchOperand_Success; 3281 } 3282 3283 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3284 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3285 // Check for a post-index addressing register operand. Specifically: 3286 // am3offset := '+' register 3287 // | '-' register 3288 // | register 3289 // | # imm 3290 // | # + imm 3291 // | # - imm 3292 3293 // This method must return MatchOperand_NoMatch without consuming any tokens 3294 // in the case where there is no match, as other alternatives take other 3295 // parse methods. 3296 AsmToken Tok = Parser.getTok(); 3297 SMLoc S = Tok.getLoc(); 3298 3299 // Do immediates first, as we always parse those if we have a '#'. 3300 if (Parser.getTok().is(AsmToken::Hash)) { 3301 Parser.Lex(); // Eat the '#'. 3302 // Explicitly look for a '-', as we need to encode negative zero 3303 // differently. 3304 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3305 const MCExpr *Offset; 3306 if (getParser().ParseExpression(Offset)) 3307 return MatchOperand_ParseFail; 3308 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3309 if (!CE) { 3310 Error(S, "constant expression expected"); 3311 return MatchOperand_ParseFail; 3312 } 3313 SMLoc E = Tok.getLoc(); 3314 // Negative zero is encoded as the flag value INT32_MIN. 3315 int32_t Val = CE->getValue(); 3316 if (isNegative && Val == 0) 3317 Val = INT32_MIN; 3318 3319 Operands.push_back( 3320 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3321 3322 return MatchOperand_Success; 3323 } 3324 3325 3326 bool haveEaten = false; 3327 bool isAdd = true; 3328 int Reg = -1; 3329 if (Tok.is(AsmToken::Plus)) { 3330 Parser.Lex(); // Eat the '+' token. 3331 haveEaten = true; 3332 } else if (Tok.is(AsmToken::Minus)) { 3333 Parser.Lex(); // Eat the '-' token. 3334 isAdd = false; 3335 haveEaten = true; 3336 } 3337 if (Parser.getTok().is(AsmToken::Identifier)) 3338 Reg = tryParseRegister(); 3339 if (Reg == -1) { 3340 if (!haveEaten) 3341 return MatchOperand_NoMatch; 3342 Error(Parser.getTok().getLoc(), "register expected"); 3343 return MatchOperand_ParseFail; 3344 } 3345 SMLoc E = Parser.getTok().getLoc(); 3346 3347 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3348 0, S, E)); 3349 3350 return MatchOperand_Success; 3351 } 3352 3353 /// cvtT2LdrdPre - Convert parsed operands to MCInst. 3354 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3355 /// when they refer multiple MIOperands inside a single one. 3356 bool ARMAsmParser:: 3357 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 3358 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3359 // Rt, Rt2 3360 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3361 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3362 // Create a writeback register dummy placeholder. 3363 Inst.addOperand(MCOperand::CreateReg(0)); 3364 // addr 3365 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3366 // pred 3367 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3368 return true; 3369 } 3370 3371 /// cvtT2StrdPre - Convert parsed operands to MCInst. 3372 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3373 /// when they refer multiple MIOperands inside a single one. 3374 bool ARMAsmParser:: 3375 cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 3376 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3377 // Create a writeback register dummy placeholder. 3378 Inst.addOperand(MCOperand::CreateReg(0)); 3379 // Rt, Rt2 3380 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3381 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3382 // addr 3383 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3384 // pred 3385 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3386 return true; 3387 } 3388 3389 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3390 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3391 /// when they refer multiple MIOperands inside a single one. 3392 bool ARMAsmParser:: 3393 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3394 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3395 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3396 3397 // Create a writeback register dummy placeholder. 3398 Inst.addOperand(MCOperand::CreateImm(0)); 3399 3400 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3401 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3402 return true; 3403 } 3404 3405 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3406 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3407 /// when they refer multiple MIOperands inside a single one. 3408 bool ARMAsmParser:: 3409 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3410 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3411 // Create a writeback register dummy placeholder. 3412 Inst.addOperand(MCOperand::CreateImm(0)); 3413 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3414 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3415 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3416 return true; 3417 } 3418 3419 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3420 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3421 /// when they refer multiple MIOperands inside a single one. 3422 bool ARMAsmParser:: 3423 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3424 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3425 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3426 3427 // Create a writeback register dummy placeholder. 3428 Inst.addOperand(MCOperand::CreateImm(0)); 3429 3430 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3431 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3432 return true; 3433 } 3434 3435 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3436 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3437 /// when they refer multiple MIOperands inside a single one. 3438 bool ARMAsmParser:: 3439 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3440 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3441 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3442 3443 // Create a writeback register dummy placeholder. 3444 Inst.addOperand(MCOperand::CreateImm(0)); 3445 3446 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3447 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3448 return true; 3449 } 3450 3451 3452 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3453 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3454 /// when they refer multiple MIOperands inside a single one. 3455 bool ARMAsmParser:: 3456 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3457 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3458 // Create a writeback register dummy placeholder. 3459 Inst.addOperand(MCOperand::CreateImm(0)); 3460 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3461 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3462 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3463 return true; 3464 } 3465 3466 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3467 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3468 /// when they refer multiple MIOperands inside a single one. 3469 bool ARMAsmParser:: 3470 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3471 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3472 // Create a writeback register dummy placeholder. 3473 Inst.addOperand(MCOperand::CreateImm(0)); 3474 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3475 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3476 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3477 return true; 3478 } 3479 3480 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 3481 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3482 /// when they refer multiple MIOperands inside a single one. 3483 bool ARMAsmParser:: 3484 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 3485 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3486 // Create a writeback register dummy placeholder. 3487 Inst.addOperand(MCOperand::CreateImm(0)); 3488 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3489 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 3490 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3491 return true; 3492 } 3493 3494 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 3495 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3496 /// when they refer multiple MIOperands inside a single one. 3497 bool ARMAsmParser:: 3498 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 3499 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3500 // Rt 3501 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3502 // Create a writeback register dummy placeholder. 3503 Inst.addOperand(MCOperand::CreateImm(0)); 3504 // addr 3505 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3506 // offset 3507 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 3508 // pred 3509 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3510 return true; 3511 } 3512 3513 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 3514 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3515 /// when they refer multiple MIOperands inside a single one. 3516 bool ARMAsmParser:: 3517 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 3518 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3519 // Rt 3520 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3521 // Create a writeback register dummy placeholder. 3522 Inst.addOperand(MCOperand::CreateImm(0)); 3523 // addr 3524 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3525 // offset 3526 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 3527 // pred 3528 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3529 return true; 3530 } 3531 3532 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 3533 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3534 /// when they refer multiple MIOperands inside a single one. 3535 bool ARMAsmParser:: 3536 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 3537 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3538 // Create a writeback register dummy placeholder. 3539 Inst.addOperand(MCOperand::CreateImm(0)); 3540 // Rt 3541 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3542 // addr 3543 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3544 // offset 3545 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 3546 // pred 3547 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3548 return true; 3549 } 3550 3551 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 3552 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3553 /// when they refer multiple MIOperands inside a single one. 3554 bool ARMAsmParser:: 3555 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 3556 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3557 // Create a writeback register dummy placeholder. 3558 Inst.addOperand(MCOperand::CreateImm(0)); 3559 // Rt 3560 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3561 // addr 3562 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3563 // offset 3564 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 3565 // pred 3566 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3567 return true; 3568 } 3569 3570 /// cvtLdrdPre - Convert parsed operands to MCInst. 3571 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3572 /// when they refer multiple MIOperands inside a single one. 3573 bool ARMAsmParser:: 3574 cvtLdrdPre(MCInst &Inst, unsigned Opcode, 3575 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3576 // Rt, Rt2 3577 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3578 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3579 // Create a writeback register dummy placeholder. 3580 Inst.addOperand(MCOperand::CreateImm(0)); 3581 // addr 3582 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 3583 // pred 3584 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3585 return true; 3586 } 3587 3588 /// cvtStrdPre - Convert parsed operands to MCInst. 3589 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3590 /// when they refer multiple MIOperands inside a single one. 3591 bool ARMAsmParser:: 3592 cvtStrdPre(MCInst &Inst, unsigned Opcode, 3593 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3594 // Create a writeback register dummy placeholder. 3595 Inst.addOperand(MCOperand::CreateImm(0)); 3596 // Rt, Rt2 3597 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3598 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3599 // addr 3600 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 3601 // pred 3602 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3603 return true; 3604 } 3605 3606 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 3607 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3608 /// when they refer multiple MIOperands inside a single one. 3609 bool ARMAsmParser:: 3610 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 3611 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3612 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3613 // Create a writeback register dummy placeholder. 3614 Inst.addOperand(MCOperand::CreateImm(0)); 3615 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 3616 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3617 return true; 3618 } 3619 3620 /// cvtThumbMultiple- Convert parsed operands to MCInst. 3621 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3622 /// when they refer multiple MIOperands inside a single one. 3623 bool ARMAsmParser:: 3624 cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 3625 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3626 // The second source operand must be the same register as the destination 3627 // operand. 3628 if (Operands.size() == 6 && 3629 (((ARMOperand*)Operands[3])->getReg() != 3630 ((ARMOperand*)Operands[5])->getReg()) && 3631 (((ARMOperand*)Operands[3])->getReg() != 3632 ((ARMOperand*)Operands[4])->getReg())) { 3633 Error(Operands[3]->getStartLoc(), 3634 "destination register must match source register"); 3635 return false; 3636 } 3637 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3638 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 3639 // If we have a three-operand form, make sure to set Rn to be the operand 3640 // that isn't the same as Rd. 3641 unsigned RegOp = 4; 3642 if (Operands.size() == 6 && 3643 ((ARMOperand*)Operands[4])->getReg() == 3644 ((ARMOperand*)Operands[3])->getReg()) 3645 RegOp = 5; 3646 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 3647 Inst.addOperand(Inst.getOperand(0)); 3648 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 3649 3650 return true; 3651 } 3652 3653 bool ARMAsmParser:: 3654 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 3655 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3656 // Vd 3657 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 3658 // Create a writeback register dummy placeholder. 3659 Inst.addOperand(MCOperand::CreateImm(0)); 3660 // Vn 3661 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 3662 // pred 3663 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3664 return true; 3665 } 3666 3667 bool ARMAsmParser:: 3668 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 3669 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3670 // Vd 3671 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 3672 // Create a writeback register dummy placeholder. 3673 Inst.addOperand(MCOperand::CreateImm(0)); 3674 // Vn 3675 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 3676 // Vm 3677 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 3678 // pred 3679 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3680 return true; 3681 } 3682 3683 bool ARMAsmParser:: 3684 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 3685 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3686 // Create a writeback register dummy placeholder. 3687 Inst.addOperand(MCOperand::CreateImm(0)); 3688 // Vn 3689 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 3690 // Vt 3691 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 3692 // pred 3693 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3694 return true; 3695 } 3696 3697 bool ARMAsmParser:: 3698 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 3699 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3700 // Create a writeback register dummy placeholder. 3701 Inst.addOperand(MCOperand::CreateImm(0)); 3702 // Vn 3703 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 3704 // Vm 3705 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 3706 // Vt 3707 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 3708 // pred 3709 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3710 return true; 3711 } 3712 3713 /// Parse an ARM memory expression, return false if successful else return true 3714 /// or an error. The first token must be a '[' when called. 3715 bool ARMAsmParser:: 3716 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3717 SMLoc S, E; 3718 assert(Parser.getTok().is(AsmToken::LBrac) && 3719 "Token is not a Left Bracket"); 3720 S = Parser.getTok().getLoc(); 3721 Parser.Lex(); // Eat left bracket token. 3722 3723 const AsmToken &BaseRegTok = Parser.getTok(); 3724 int BaseRegNum = tryParseRegister(); 3725 if (BaseRegNum == -1) 3726 return Error(BaseRegTok.getLoc(), "register expected"); 3727 3728 // The next token must either be a comma or a closing bracket. 3729 const AsmToken &Tok = Parser.getTok(); 3730 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 3731 return Error(Tok.getLoc(), "malformed memory operand"); 3732 3733 if (Tok.is(AsmToken::RBrac)) { 3734 E = Tok.getLoc(); 3735 Parser.Lex(); // Eat right bracket token. 3736 3737 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 3738 0, 0, false, S, E)); 3739 3740 // If there's a pre-indexing writeback marker, '!', just add it as a token 3741 // operand. It's rather odd, but syntactically valid. 3742 if (Parser.getTok().is(AsmToken::Exclaim)) { 3743 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 3744 Parser.Lex(); // Eat the '!'. 3745 } 3746 3747 return false; 3748 } 3749 3750 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 3751 Parser.Lex(); // Eat the comma. 3752 3753 // If we have a ':', it's an alignment specifier. 3754 if (Parser.getTok().is(AsmToken::Colon)) { 3755 Parser.Lex(); // Eat the ':'. 3756 E = Parser.getTok().getLoc(); 3757 3758 const MCExpr *Expr; 3759 if (getParser().ParseExpression(Expr)) 3760 return true; 3761 3762 // The expression has to be a constant. Memory references with relocations 3763 // don't come through here, as they use the <label> forms of the relevant 3764 // instructions. 3765 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3766 if (!CE) 3767 return Error (E, "constant expression expected"); 3768 3769 unsigned Align = 0; 3770 switch (CE->getValue()) { 3771 default: 3772 return Error(E, "alignment specifier must be 64, 128, or 256 bits"); 3773 case 64: Align = 8; break; 3774 case 128: Align = 16; break; 3775 case 256: Align = 32; break; 3776 } 3777 3778 // Now we should have the closing ']' 3779 E = Parser.getTok().getLoc(); 3780 if (Parser.getTok().isNot(AsmToken::RBrac)) 3781 return Error(E, "']' expected"); 3782 Parser.Lex(); // Eat right bracket token. 3783 3784 // Don't worry about range checking the value here. That's handled by 3785 // the is*() predicates. 3786 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 3787 ARM_AM::no_shift, 0, Align, 3788 false, S, E)); 3789 3790 // If there's a pre-indexing writeback marker, '!', just add it as a token 3791 // operand. 3792 if (Parser.getTok().is(AsmToken::Exclaim)) { 3793 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 3794 Parser.Lex(); // Eat the '!'. 3795 } 3796 3797 return false; 3798 } 3799 3800 // If we have a '#', it's an immediate offset, else assume it's a register 3801 // offset. Be friendly and also accept a plain integer (without a leading 3802 // hash) for gas compatibility. 3803 if (Parser.getTok().is(AsmToken::Hash) || 3804 Parser.getTok().is(AsmToken::Integer)) { 3805 if (Parser.getTok().is(AsmToken::Hash)) 3806 Parser.Lex(); // Eat the '#'. 3807 E = Parser.getTok().getLoc(); 3808 3809 bool isNegative = getParser().getTok().is(AsmToken::Minus); 3810 const MCExpr *Offset; 3811 if (getParser().ParseExpression(Offset)) 3812 return true; 3813 3814 // The expression has to be a constant. Memory references with relocations 3815 // don't come through here, as they use the <label> forms of the relevant 3816 // instructions. 3817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3818 if (!CE) 3819 return Error (E, "constant expression expected"); 3820 3821 // If the constant was #-0, represent it as INT32_MIN. 3822 int32_t Val = CE->getValue(); 3823 if (isNegative && Val == 0) 3824 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 3825 3826 // Now we should have the closing ']' 3827 E = Parser.getTok().getLoc(); 3828 if (Parser.getTok().isNot(AsmToken::RBrac)) 3829 return Error(E, "']' expected"); 3830 Parser.Lex(); // Eat right bracket token. 3831 3832 // Don't worry about range checking the value here. That's handled by 3833 // the is*() predicates. 3834 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 3835 ARM_AM::no_shift, 0, 0, 3836 false, S, E)); 3837 3838 // If there's a pre-indexing writeback marker, '!', just add it as a token 3839 // operand. 3840 if (Parser.getTok().is(AsmToken::Exclaim)) { 3841 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 3842 Parser.Lex(); // Eat the '!'. 3843 } 3844 3845 return false; 3846 } 3847 3848 // The register offset is optionally preceded by a '+' or '-' 3849 bool isNegative = false; 3850 if (Parser.getTok().is(AsmToken::Minus)) { 3851 isNegative = true; 3852 Parser.Lex(); // Eat the '-'. 3853 } else if (Parser.getTok().is(AsmToken::Plus)) { 3854 // Nothing to do. 3855 Parser.Lex(); // Eat the '+'. 3856 } 3857 3858 E = Parser.getTok().getLoc(); 3859 int OffsetRegNum = tryParseRegister(); 3860 if (OffsetRegNum == -1) 3861 return Error(E, "register expected"); 3862 3863 // If there's a shift operator, handle it. 3864 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 3865 unsigned ShiftImm = 0; 3866 if (Parser.getTok().is(AsmToken::Comma)) { 3867 Parser.Lex(); // Eat the ','. 3868 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 3869 return true; 3870 } 3871 3872 // Now we should have the closing ']' 3873 E = Parser.getTok().getLoc(); 3874 if (Parser.getTok().isNot(AsmToken::RBrac)) 3875 return Error(E, "']' expected"); 3876 Parser.Lex(); // Eat right bracket token. 3877 3878 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 3879 ShiftType, ShiftImm, 0, isNegative, 3880 S, E)); 3881 3882 // If there's a pre-indexing writeback marker, '!', just add it as a token 3883 // operand. 3884 if (Parser.getTok().is(AsmToken::Exclaim)) { 3885 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 3886 Parser.Lex(); // Eat the '!'. 3887 } 3888 3889 return false; 3890 } 3891 3892 /// parseMemRegOffsetShift - one of these two: 3893 /// ( lsl | lsr | asr | ror ) , # shift_amount 3894 /// rrx 3895 /// return true if it parses a shift otherwise it returns false. 3896 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 3897 unsigned &Amount) { 3898 SMLoc Loc = Parser.getTok().getLoc(); 3899 const AsmToken &Tok = Parser.getTok(); 3900 if (Tok.isNot(AsmToken::Identifier)) 3901 return true; 3902 StringRef ShiftName = Tok.getString(); 3903 if (ShiftName == "lsl" || ShiftName == "LSL") 3904 St = ARM_AM::lsl; 3905 else if (ShiftName == "lsr" || ShiftName == "LSR") 3906 St = ARM_AM::lsr; 3907 else if (ShiftName == "asr" || ShiftName == "ASR") 3908 St = ARM_AM::asr; 3909 else if (ShiftName == "ror" || ShiftName == "ROR") 3910 St = ARM_AM::ror; 3911 else if (ShiftName == "rrx" || ShiftName == "RRX") 3912 St = ARM_AM::rrx; 3913 else 3914 return Error(Loc, "illegal shift operator"); 3915 Parser.Lex(); // Eat shift type token. 3916 3917 // rrx stands alone. 3918 Amount = 0; 3919 if (St != ARM_AM::rrx) { 3920 Loc = Parser.getTok().getLoc(); 3921 // A '#' and a shift amount. 3922 const AsmToken &HashTok = Parser.getTok(); 3923 if (HashTok.isNot(AsmToken::Hash)) 3924 return Error(HashTok.getLoc(), "'#' expected"); 3925 Parser.Lex(); // Eat hash token. 3926 3927 const MCExpr *Expr; 3928 if (getParser().ParseExpression(Expr)) 3929 return true; 3930 // Range check the immediate. 3931 // lsl, ror: 0 <= imm <= 31 3932 // lsr, asr: 0 <= imm <= 32 3933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3934 if (!CE) 3935 return Error(Loc, "shift amount must be an immediate"); 3936 int64_t Imm = CE->getValue(); 3937 if (Imm < 0 || 3938 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 3939 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 3940 return Error(Loc, "immediate shift value out of range"); 3941 Amount = Imm; 3942 } 3943 3944 return false; 3945 } 3946 3947 /// parseFPImm - A floating point immediate expression operand. 3948 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3949 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3950 SMLoc S = Parser.getTok().getLoc(); 3951 3952 if (Parser.getTok().isNot(AsmToken::Hash)) 3953 return MatchOperand_NoMatch; 3954 3955 // Disambiguate the VMOV forms that can accept an FP immediate. 3956 // vmov.f32 <sreg>, #imm 3957 // vmov.f64 <dreg>, #imm 3958 // vmov.f32 <dreg>, #imm @ vector f32x2 3959 // vmov.f32 <qreg>, #imm @ vector f32x4 3960 // 3961 // There are also the NEON VMOV instructions which expect an 3962 // integer constant. Make sure we don't try to parse an FPImm 3963 // for these: 3964 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 3965 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 3966 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 3967 TyOp->getToken() != ".f64")) 3968 return MatchOperand_NoMatch; 3969 3970 Parser.Lex(); // Eat the '#'. 3971 3972 // Handle negation, as that still comes through as a separate token. 3973 bool isNegative = false; 3974 if (Parser.getTok().is(AsmToken::Minus)) { 3975 isNegative = true; 3976 Parser.Lex(); 3977 } 3978 const AsmToken &Tok = Parser.getTok(); 3979 if (Tok.is(AsmToken::Real)) { 3980 APFloat RealVal(APFloat::IEEEdouble, Tok.getString()); 3981 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 3982 // If we had a '-' in front, toggle the sign bit. 3983 IntVal ^= (uint64_t)isNegative << 63; 3984 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal)); 3985 Parser.Lex(); // Eat the token. 3986 if (Val == -1) { 3987 TokError("floating point value out of range"); 3988 return MatchOperand_ParseFail; 3989 } 3990 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext())); 3991 return MatchOperand_Success; 3992 } 3993 if (Tok.is(AsmToken::Integer)) { 3994 int64_t Val = Tok.getIntVal(); 3995 Parser.Lex(); // Eat the token. 3996 if (Val > 255 || Val < 0) { 3997 TokError("encoded floating point value out of range"); 3998 return MatchOperand_ParseFail; 3999 } 4000 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext())); 4001 return MatchOperand_Success; 4002 } 4003 4004 TokError("invalid floating point immediate"); 4005 return MatchOperand_ParseFail; 4006 } 4007 /// Parse a arm instruction operand. For now this parses the operand regardless 4008 /// of the mnemonic. 4009 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4010 StringRef Mnemonic) { 4011 SMLoc S, E; 4012 4013 // Check if the current operand has a custom associated parser, if so, try to 4014 // custom parse the operand, or fallback to the general approach. 4015 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4016 if (ResTy == MatchOperand_Success) 4017 return false; 4018 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4019 // there was a match, but an error occurred, in which case, just return that 4020 // the operand parsing failed. 4021 if (ResTy == MatchOperand_ParseFail) 4022 return true; 4023 4024 switch (getLexer().getKind()) { 4025 default: 4026 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4027 return true; 4028 case AsmToken::Identifier: { 4029 // If this is VMRS, check for the apsr_nzcv operand. 4030 if (!tryParseRegisterWithWriteBack(Operands)) 4031 return false; 4032 int Res = tryParseShiftRegister(Operands); 4033 if (Res == 0) // success 4034 return false; 4035 else if (Res == -1) // irrecoverable error 4036 return true; 4037 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") { 4038 S = Parser.getTok().getLoc(); 4039 Parser.Lex(); 4040 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S)); 4041 return false; 4042 } 4043 4044 // Fall though for the Identifier case that is not a register or a 4045 // special name. 4046 } 4047 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4048 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4049 case AsmToken::String: // quoted label names. 4050 case AsmToken::Dot: { // . as a branch target 4051 // This was not a register so parse other operands that start with an 4052 // identifier (like labels) as expressions and create them as immediates. 4053 const MCExpr *IdVal; 4054 S = Parser.getTok().getLoc(); 4055 if (getParser().ParseExpression(IdVal)) 4056 return true; 4057 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4058 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4059 return false; 4060 } 4061 case AsmToken::LBrac: 4062 return parseMemory(Operands); 4063 case AsmToken::LCurly: 4064 return parseRegisterList(Operands); 4065 case AsmToken::Hash: { 4066 // #42 -> immediate. 4067 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 4068 S = Parser.getTok().getLoc(); 4069 Parser.Lex(); 4070 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4071 const MCExpr *ImmVal; 4072 if (getParser().ParseExpression(ImmVal)) 4073 return true; 4074 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4075 if (CE) { 4076 int32_t Val = CE->getValue(); 4077 if (isNegative && Val == 0) 4078 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4079 } 4080 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4081 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4082 return false; 4083 } 4084 case AsmToken::Colon: { 4085 // ":lower16:" and ":upper16:" expression prefixes 4086 // FIXME: Check it's an expression prefix, 4087 // e.g. (FOO - :lower16:BAR) isn't legal. 4088 ARMMCExpr::VariantKind RefKind; 4089 if (parsePrefix(RefKind)) 4090 return true; 4091 4092 const MCExpr *SubExprVal; 4093 if (getParser().ParseExpression(SubExprVal)) 4094 return true; 4095 4096 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4097 getContext()); 4098 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4099 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4100 return false; 4101 } 4102 } 4103 } 4104 4105 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4106 // :lower16: and :upper16:. 4107 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4108 RefKind = ARMMCExpr::VK_ARM_None; 4109 4110 // :lower16: and :upper16: modifiers 4111 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4112 Parser.Lex(); // Eat ':' 4113 4114 if (getLexer().isNot(AsmToken::Identifier)) { 4115 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4116 return true; 4117 } 4118 4119 StringRef IDVal = Parser.getTok().getIdentifier(); 4120 if (IDVal == "lower16") { 4121 RefKind = ARMMCExpr::VK_ARM_LO16; 4122 } else if (IDVal == "upper16") { 4123 RefKind = ARMMCExpr::VK_ARM_HI16; 4124 } else { 4125 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4126 return true; 4127 } 4128 Parser.Lex(); 4129 4130 if (getLexer().isNot(AsmToken::Colon)) { 4131 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4132 return true; 4133 } 4134 Parser.Lex(); // Eat the last ':' 4135 return false; 4136 } 4137 4138 /// \brief Given a mnemonic, split out possible predication code and carry 4139 /// setting letters to form a canonical mnemonic and flags. 4140 // 4141 // FIXME: Would be nice to autogen this. 4142 // FIXME: This is a bit of a maze of special cases. 4143 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4144 unsigned &PredicationCode, 4145 bool &CarrySetting, 4146 unsigned &ProcessorIMod, 4147 StringRef &ITMask) { 4148 PredicationCode = ARMCC::AL; 4149 CarrySetting = false; 4150 ProcessorIMod = 0; 4151 4152 // Ignore some mnemonics we know aren't predicated forms. 4153 // 4154 // FIXME: Would be nice to autogen this. 4155 if ((Mnemonic == "movs" && isThumb()) || 4156 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4157 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4158 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4159 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4160 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4161 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4162 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal") 4163 return Mnemonic; 4164 4165 // First, split out any predication code. Ignore mnemonics we know aren't 4166 // predicated but do have a carry-set and so weren't caught above. 4167 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4168 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4169 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4170 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4171 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4172 .Case("eq", ARMCC::EQ) 4173 .Case("ne", ARMCC::NE) 4174 .Case("hs", ARMCC::HS) 4175 .Case("cs", ARMCC::HS) 4176 .Case("lo", ARMCC::LO) 4177 .Case("cc", ARMCC::LO) 4178 .Case("mi", ARMCC::MI) 4179 .Case("pl", ARMCC::PL) 4180 .Case("vs", ARMCC::VS) 4181 .Case("vc", ARMCC::VC) 4182 .Case("hi", ARMCC::HI) 4183 .Case("ls", ARMCC::LS) 4184 .Case("ge", ARMCC::GE) 4185 .Case("lt", ARMCC::LT) 4186 .Case("gt", ARMCC::GT) 4187 .Case("le", ARMCC::LE) 4188 .Case("al", ARMCC::AL) 4189 .Default(~0U); 4190 if (CC != ~0U) { 4191 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4192 PredicationCode = CC; 4193 } 4194 } 4195 4196 // Next, determine if we have a carry setting bit. We explicitly ignore all 4197 // the instructions we know end in 's'. 4198 if (Mnemonic.endswith("s") && 4199 !(Mnemonic == "cps" || Mnemonic == "mls" || 4200 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4201 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4202 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4203 Mnemonic == "vrsqrts" || Mnemonic == "srs" || 4204 (Mnemonic == "movs" && isThumb()))) { 4205 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4206 CarrySetting = true; 4207 } 4208 4209 // The "cps" instruction can have a interrupt mode operand which is glued into 4210 // the mnemonic. Check if this is the case, split it and parse the imod op 4211 if (Mnemonic.startswith("cps")) { 4212 // Split out any imod code. 4213 unsigned IMod = 4214 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4215 .Case("ie", ARM_PROC::IE) 4216 .Case("id", ARM_PROC::ID) 4217 .Default(~0U); 4218 if (IMod != ~0U) { 4219 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4220 ProcessorIMod = IMod; 4221 } 4222 } 4223 4224 // The "it" instruction has the condition mask on the end of the mnemonic. 4225 if (Mnemonic.startswith("it")) { 4226 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4227 Mnemonic = Mnemonic.slice(0, 2); 4228 } 4229 4230 return Mnemonic; 4231 } 4232 4233 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 4234 /// inclusion of carry set or predication code operands. 4235 // 4236 // FIXME: It would be nice to autogen this. 4237 void ARMAsmParser:: 4238 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4239 bool &CanAcceptPredicationCode) { 4240 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4241 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4242 Mnemonic == "add" || Mnemonic == "adc" || 4243 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4244 Mnemonic == "orr" || Mnemonic == "mvn" || 4245 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4246 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4247 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4248 Mnemonic == "mla" || Mnemonic == "smlal" || 4249 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4250 CanAcceptCarrySet = true; 4251 } else 4252 CanAcceptCarrySet = false; 4253 4254 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4255 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4256 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4257 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4258 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4259 (Mnemonic == "clrex" && !isThumb()) || 4260 (Mnemonic == "nop" && isThumbOne()) || 4261 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 4262 Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 4263 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 4264 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 4265 !isThumb()) || 4266 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 4267 CanAcceptPredicationCode = false; 4268 } else 4269 CanAcceptPredicationCode = true; 4270 4271 if (isThumb()) { 4272 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 4273 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4274 CanAcceptPredicationCode = false; 4275 } 4276 } 4277 4278 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4279 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4280 // FIXME: This is all horribly hacky. We really need a better way to deal 4281 // with optional operands like this in the matcher table. 4282 4283 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4284 // another does not. Specifically, the MOVW instruction does not. So we 4285 // special case it here and remove the defaulted (non-setting) cc_out 4286 // operand if that's the instruction we're trying to match. 4287 // 4288 // We do this as post-processing of the explicit operands rather than just 4289 // conditionally adding the cc_out in the first place because we need 4290 // to check the type of the parsed immediate operand. 4291 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4292 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4293 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4294 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4295 return true; 4296 4297 // Register-register 'add' for thumb does not have a cc_out operand 4298 // when there are only two register operands. 4299 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4300 static_cast<ARMOperand*>(Operands[3])->isReg() && 4301 static_cast<ARMOperand*>(Operands[4])->isReg() && 4302 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4303 return true; 4304 // Register-register 'add' for thumb does not have a cc_out operand 4305 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4306 // have to check the immediate range here since Thumb2 has a variant 4307 // that can handle a different range and has a cc_out operand. 4308 if (((isThumb() && Mnemonic == "add") || 4309 (isThumbTwo() && Mnemonic == "sub")) && 4310 Operands.size() == 6 && 4311 static_cast<ARMOperand*>(Operands[3])->isReg() && 4312 static_cast<ARMOperand*>(Operands[4])->isReg() && 4313 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4314 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4315 (static_cast<ARMOperand*>(Operands[5])->isReg() || 4316 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4317 return true; 4318 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4319 // imm0_4095 variant. That's the least-preferred variant when 4320 // selecting via the generic "add" mnemonic, so to know that we 4321 // should remove the cc_out operand, we have to explicitly check that 4322 // it's not one of the other variants. Ugh. 4323 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4324 Operands.size() == 6 && 4325 static_cast<ARMOperand*>(Operands[3])->isReg() && 4326 static_cast<ARMOperand*>(Operands[4])->isReg() && 4327 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4328 // Nest conditions rather than one big 'if' statement for readability. 4329 // 4330 // If either register is a high reg, it's either one of the SP 4331 // variants (handled above) or a 32-bit encoding, so we just 4332 // check against T3. 4333 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4334 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 4335 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 4336 return false; 4337 // If both registers are low, we're in an IT block, and the immediate is 4338 // in range, we should use encoding T1 instead, which has a cc_out. 4339 if (inITBlock() && 4340 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4341 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 4342 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 4343 return false; 4344 4345 // Otherwise, we use encoding T4, which does not have a cc_out 4346 // operand. 4347 return true; 4348 } 4349 4350 // The thumb2 multiply instruction doesn't have a CCOut register, so 4351 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 4352 // use the 16-bit encoding or not. 4353 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 4354 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4355 static_cast<ARMOperand*>(Operands[3])->isReg() && 4356 static_cast<ARMOperand*>(Operands[4])->isReg() && 4357 static_cast<ARMOperand*>(Operands[5])->isReg() && 4358 // If the registers aren't low regs, the destination reg isn't the 4359 // same as one of the source regs, or the cc_out operand is zero 4360 // outside of an IT block, we have to use the 32-bit encoding, so 4361 // remove the cc_out operand. 4362 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4363 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4364 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 4365 !inITBlock() || 4366 (static_cast<ARMOperand*>(Operands[3])->getReg() != 4367 static_cast<ARMOperand*>(Operands[5])->getReg() && 4368 static_cast<ARMOperand*>(Operands[3])->getReg() != 4369 static_cast<ARMOperand*>(Operands[4])->getReg()))) 4370 return true; 4371 4372 // Also check the 'mul' syntax variant that doesn't specify an explicit 4373 // destination register. 4374 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 4375 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4376 static_cast<ARMOperand*>(Operands[3])->isReg() && 4377 static_cast<ARMOperand*>(Operands[4])->isReg() && 4378 // If the registers aren't low regs or the cc_out operand is zero 4379 // outside of an IT block, we have to use the 32-bit encoding, so 4380 // remove the cc_out operand. 4381 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4382 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4383 !inITBlock())) 4384 return true; 4385 4386 4387 4388 // Register-register 'add/sub' for thumb does not have a cc_out operand 4389 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4390 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4391 // right, this will result in better diagnostics (which operand is off) 4392 // anyway. 4393 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4394 (Operands.size() == 5 || Operands.size() == 6) && 4395 static_cast<ARMOperand*>(Operands[3])->isReg() && 4396 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 4397 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4398 return true; 4399 4400 return false; 4401 } 4402 4403 static bool isDataTypeToken(StringRef Tok) { 4404 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 4405 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 4406 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 4407 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 4408 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 4409 Tok == ".f" || Tok == ".d"; 4410 } 4411 4412 // FIXME: This bit should probably be handled via an explicit match class 4413 // in the .td files that matches the suffix instead of having it be 4414 // a literal string token the way it is now. 4415 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 4416 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 4417 } 4418 4419 /// Parse an arm instruction mnemonic followed by its operands. 4420 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4421 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4422 // Create the leading tokens for the mnemonic, split by '.' characters. 4423 size_t Start = 0, Next = Name.find('.'); 4424 StringRef Mnemonic = Name.slice(Start, Next); 4425 4426 // Split out the predication code and carry setting flag from the mnemonic. 4427 unsigned PredicationCode; 4428 unsigned ProcessorIMod; 4429 bool CarrySetting; 4430 StringRef ITMask; 4431 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 4432 ProcessorIMod, ITMask); 4433 4434 // In Thumb1, only the branch (B) instruction can be predicated. 4435 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 4436 Parser.EatToEndOfStatement(); 4437 return Error(NameLoc, "conditional execution not supported in Thumb1"); 4438 } 4439 4440 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4441 4442 // Handle the IT instruction ITMask. Convert it to a bitmask. This 4443 // is the mask as it will be for the IT encoding if the conditional 4444 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 4445 // where the conditional bit0 is zero, the instruction post-processing 4446 // will adjust the mask accordingly. 4447 if (Mnemonic == "it") { 4448 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 4449 if (ITMask.size() > 3) { 4450 Parser.EatToEndOfStatement(); 4451 return Error(Loc, "too many conditions on IT instruction"); 4452 } 4453 unsigned Mask = 8; 4454 for (unsigned i = ITMask.size(); i != 0; --i) { 4455 char pos = ITMask[i - 1]; 4456 if (pos != 't' && pos != 'e') { 4457 Parser.EatToEndOfStatement(); 4458 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 4459 } 4460 Mask >>= 1; 4461 if (ITMask[i - 1] == 't') 4462 Mask |= 8; 4463 } 4464 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 4465 } 4466 4467 // FIXME: This is all a pretty gross hack. We should automatically handle 4468 // optional operands like this via tblgen. 4469 4470 // Next, add the CCOut and ConditionCode operands, if needed. 4471 // 4472 // For mnemonics which can ever incorporate a carry setting bit or predication 4473 // code, our matching model involves us always generating CCOut and 4474 // ConditionCode operands to match the mnemonic "as written" and then we let 4475 // the matcher deal with finding the right instruction or generating an 4476 // appropriate error. 4477 bool CanAcceptCarrySet, CanAcceptPredicationCode; 4478 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 4479 4480 // If we had a carry-set on an instruction that can't do that, issue an 4481 // error. 4482 if (!CanAcceptCarrySet && CarrySetting) { 4483 Parser.EatToEndOfStatement(); 4484 return Error(NameLoc, "instruction '" + Mnemonic + 4485 "' can not set flags, but 's' suffix specified"); 4486 } 4487 // If we had a predication code on an instruction that can't do that, issue an 4488 // error. 4489 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 4490 Parser.EatToEndOfStatement(); 4491 return Error(NameLoc, "instruction '" + Mnemonic + 4492 "' is not predicable, but condition code specified"); 4493 } 4494 4495 // Add the carry setting operand, if necessary. 4496 if (CanAcceptCarrySet) { 4497 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 4498 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 4499 Loc)); 4500 } 4501 4502 // Add the predication code operand, if necessary. 4503 if (CanAcceptPredicationCode) { 4504 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 4505 CarrySetting); 4506 Operands.push_back(ARMOperand::CreateCondCode( 4507 ARMCC::CondCodes(PredicationCode), Loc)); 4508 } 4509 4510 // Add the processor imod operand, if necessary. 4511 if (ProcessorIMod) { 4512 Operands.push_back(ARMOperand::CreateImm( 4513 MCConstantExpr::Create(ProcessorIMod, getContext()), 4514 NameLoc, NameLoc)); 4515 } 4516 4517 // Add the remaining tokens in the mnemonic. 4518 while (Next != StringRef::npos) { 4519 Start = Next; 4520 Next = Name.find('.', Start + 1); 4521 StringRef ExtraToken = Name.slice(Start, Next); 4522 4523 // Some NEON instructions have an optional datatype suffix that is 4524 // completely ignored. Check for that. 4525 if (isDataTypeToken(ExtraToken) && 4526 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 4527 continue; 4528 4529 if (ExtraToken != ".n") { 4530 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 4531 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 4532 } 4533 } 4534 4535 // Read the remaining operands. 4536 if (getLexer().isNot(AsmToken::EndOfStatement)) { 4537 // Read the first operand. 4538 if (parseOperand(Operands, Mnemonic)) { 4539 Parser.EatToEndOfStatement(); 4540 return true; 4541 } 4542 4543 while (getLexer().is(AsmToken::Comma)) { 4544 Parser.Lex(); // Eat the comma. 4545 4546 // Parse and remember the operand. 4547 if (parseOperand(Operands, Mnemonic)) { 4548 Parser.EatToEndOfStatement(); 4549 return true; 4550 } 4551 } 4552 } 4553 4554 if (getLexer().isNot(AsmToken::EndOfStatement)) { 4555 SMLoc Loc = getLexer().getLoc(); 4556 Parser.EatToEndOfStatement(); 4557 return Error(Loc, "unexpected token in argument list"); 4558 } 4559 4560 Parser.Lex(); // Consume the EndOfStatement 4561 4562 // Some instructions, mostly Thumb, have forms for the same mnemonic that 4563 // do and don't have a cc_out optional-def operand. With some spot-checks 4564 // of the operand list, we can figure out which variant we're trying to 4565 // parse and adjust accordingly before actually matching. We shouldn't ever 4566 // try to remove a cc_out operand that was explicitly set on the the 4567 // mnemonic, of course (CarrySetting == true). Reason number #317 the 4568 // table driven matcher doesn't fit well with the ARM instruction set. 4569 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 4570 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4571 Operands.erase(Operands.begin() + 1); 4572 delete Op; 4573 } 4574 4575 // ARM mode 'blx' need special handling, as the register operand version 4576 // is predicable, but the label operand version is not. So, we can't rely 4577 // on the Mnemonic based checking to correctly figure out when to put 4578 // a k_CondCode operand in the list. If we're trying to match the label 4579 // version, remove the k_CondCode operand here. 4580 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 4581 static_cast<ARMOperand*>(Operands[2])->isImm()) { 4582 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4583 Operands.erase(Operands.begin() + 1); 4584 delete Op; 4585 } 4586 4587 // The vector-compare-to-zero instructions have a literal token "#0" at 4588 // the end that comes to here as an immediate operand. Convert it to a 4589 // token to play nicely with the matcher. 4590 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 4591 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 4592 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4593 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4594 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 4595 if (CE && CE->getValue() == 0) { 4596 Operands.erase(Operands.begin() + 5); 4597 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4598 delete Op; 4599 } 4600 } 4601 // VCMP{E} does the same thing, but with a different operand count. 4602 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 4603 static_cast<ARMOperand*>(Operands[4])->isImm()) { 4604 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 4605 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 4606 if (CE && CE->getValue() == 0) { 4607 Operands.erase(Operands.begin() + 4); 4608 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4609 delete Op; 4610 } 4611 } 4612 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 4613 // end. Convert it to a token here. 4614 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 4615 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4616 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 4618 if (CE && CE->getValue() == 0) { 4619 Operands.erase(Operands.begin() + 5); 4620 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4621 delete Op; 4622 } 4623 } 4624 4625 return false; 4626 } 4627 4628 // Validate context-sensitive operand constraints. 4629 4630 // return 'true' if register list contains non-low GPR registers, 4631 // 'false' otherwise. If Reg is in the register list or is HiReg, set 4632 // 'containsReg' to true. 4633 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 4634 unsigned HiReg, bool &containsReg) { 4635 containsReg = false; 4636 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 4637 unsigned OpReg = Inst.getOperand(i).getReg(); 4638 if (OpReg == Reg) 4639 containsReg = true; 4640 // Anything other than a low register isn't legal here. 4641 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 4642 return true; 4643 } 4644 return false; 4645 } 4646 4647 // Check if the specified regisgter is in the register list of the inst, 4648 // starting at the indicated operand number. 4649 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 4650 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 4651 unsigned OpReg = Inst.getOperand(i).getReg(); 4652 if (OpReg == Reg) 4653 return true; 4654 } 4655 return false; 4656 } 4657 4658 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around 4659 // the ARMInsts array) instead. Getting that here requires awkward 4660 // API changes, though. Better way? 4661 namespace llvm { 4662 extern const MCInstrDesc ARMInsts[]; 4663 } 4664 static const MCInstrDesc &getInstDesc(unsigned Opcode) { 4665 return ARMInsts[Opcode]; 4666 } 4667 4668 // FIXME: We would really like to be able to tablegen'erate this. 4669 bool ARMAsmParser:: 4670 validateInstruction(MCInst &Inst, 4671 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4672 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 4673 SMLoc Loc = Operands[0]->getStartLoc(); 4674 // Check the IT block state first. 4675 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of 4676 // being allowed in IT blocks, but not being predicable. It just always 4677 // executes. 4678 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) { 4679 unsigned bit = 1; 4680 if (ITState.FirstCond) 4681 ITState.FirstCond = false; 4682 else 4683 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 4684 // The instruction must be predicable. 4685 if (!MCID.isPredicable()) 4686 return Error(Loc, "instructions in IT block must be predicable"); 4687 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 4688 unsigned ITCond = bit ? ITState.Cond : 4689 ARMCC::getOppositeCondition(ITState.Cond); 4690 if (Cond != ITCond) { 4691 // Find the condition code Operand to get its SMLoc information. 4692 SMLoc CondLoc; 4693 for (unsigned i = 1; i < Operands.size(); ++i) 4694 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 4695 CondLoc = Operands[i]->getStartLoc(); 4696 return Error(CondLoc, "incorrect condition in IT block; got '" + 4697 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 4698 "', but expected '" + 4699 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 4700 } 4701 // Check for non-'al' condition codes outside of the IT block. 4702 } else if (isThumbTwo() && MCID.isPredicable() && 4703 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 4704 ARMCC::AL && Inst.getOpcode() != ARM::tB && 4705 Inst.getOpcode() != ARM::t2B) 4706 return Error(Loc, "predicated instructions must be in IT block"); 4707 4708 switch (Inst.getOpcode()) { 4709 case ARM::LDRD: 4710 case ARM::LDRD_PRE: 4711 case ARM::LDRD_POST: 4712 case ARM::LDREXD: { 4713 // Rt2 must be Rt + 1. 4714 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 4715 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 4716 if (Rt2 != Rt + 1) 4717 return Error(Operands[3]->getStartLoc(), 4718 "destination operands must be sequential"); 4719 return false; 4720 } 4721 case ARM::STRD: { 4722 // Rt2 must be Rt + 1. 4723 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 4724 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 4725 if (Rt2 != Rt + 1) 4726 return Error(Operands[3]->getStartLoc(), 4727 "source operands must be sequential"); 4728 return false; 4729 } 4730 case ARM::STRD_PRE: 4731 case ARM::STRD_POST: 4732 case ARM::STREXD: { 4733 // Rt2 must be Rt + 1. 4734 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 4735 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 4736 if (Rt2 != Rt + 1) 4737 return Error(Operands[3]->getStartLoc(), 4738 "source operands must be sequential"); 4739 return false; 4740 } 4741 case ARM::SBFX: 4742 case ARM::UBFX: { 4743 // width must be in range [1, 32-lsb] 4744 unsigned lsb = Inst.getOperand(2).getImm(); 4745 unsigned widthm1 = Inst.getOperand(3).getImm(); 4746 if (widthm1 >= 32 - lsb) 4747 return Error(Operands[5]->getStartLoc(), 4748 "bitfield width must be in range [1,32-lsb]"); 4749 return false; 4750 } 4751 case ARM::tLDMIA: { 4752 // If we're parsing Thumb2, the .w variant is available and handles 4753 // most cases that are normally illegal for a Thumb1 LDM 4754 // instruction. We'll make the transformation in processInstruction() 4755 // if necessary. 4756 // 4757 // Thumb LDM instructions are writeback iff the base register is not 4758 // in the register list. 4759 unsigned Rn = Inst.getOperand(0).getReg(); 4760 bool hasWritebackToken = 4761 (static_cast<ARMOperand*>(Operands[3])->isToken() && 4762 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 4763 bool listContainsBase; 4764 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 4765 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 4766 "registers must be in range r0-r7"); 4767 // If we should have writeback, then there should be a '!' token. 4768 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 4769 return Error(Operands[2]->getStartLoc(), 4770 "writeback operator '!' expected"); 4771 // If we should not have writeback, there must not be a '!'. This is 4772 // true even for the 32-bit wide encodings. 4773 if (listContainsBase && hasWritebackToken) 4774 return Error(Operands[3]->getStartLoc(), 4775 "writeback operator '!' not allowed when base register " 4776 "in register list"); 4777 4778 break; 4779 } 4780 case ARM::t2LDMIA_UPD: { 4781 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 4782 return Error(Operands[4]->getStartLoc(), 4783 "writeback operator '!' not allowed when base register " 4784 "in register list"); 4785 break; 4786 } 4787 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 4788 // so only issue a diagnostic for thumb1. The instructions will be 4789 // switched to the t2 encodings in processInstruction() if necessary. 4790 case ARM::tPOP: { 4791 bool listContainsBase; 4792 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 4793 !isThumbTwo()) 4794 return Error(Operands[2]->getStartLoc(), 4795 "registers must be in range r0-r7 or pc"); 4796 break; 4797 } 4798 case ARM::tPUSH: { 4799 bool listContainsBase; 4800 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 4801 !isThumbTwo()) 4802 return Error(Operands[2]->getStartLoc(), 4803 "registers must be in range r0-r7 or lr"); 4804 break; 4805 } 4806 case ARM::tSTMIA_UPD: { 4807 bool listContainsBase; 4808 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 4809 return Error(Operands[4]->getStartLoc(), 4810 "registers must be in range r0-r7"); 4811 break; 4812 } 4813 } 4814 4815 return false; 4816 } 4817 4818 static unsigned getRealVSTLNOpcode(unsigned Opc) { 4819 switch(Opc) { 4820 default: assert(0 && "unexpected opcode!"); 4821 case ARM::VST1LNdWB_fixed_Asm_8: return ARM::VST1LNd8_UPD; 4822 case ARM::VST1LNdWB_fixed_Asm_P8: return ARM::VST1LNd8_UPD; 4823 case ARM::VST1LNdWB_fixed_Asm_I8: return ARM::VST1LNd8_UPD; 4824 case ARM::VST1LNdWB_fixed_Asm_S8: return ARM::VST1LNd8_UPD; 4825 case ARM::VST1LNdWB_fixed_Asm_U8: return ARM::VST1LNd8_UPD; 4826 case ARM::VST1LNdWB_fixed_Asm_16: return ARM::VST1LNd16_UPD; 4827 case ARM::VST1LNdWB_fixed_Asm_P16: return ARM::VST1LNd16_UPD; 4828 case ARM::VST1LNdWB_fixed_Asm_I16: return ARM::VST1LNd16_UPD; 4829 case ARM::VST1LNdWB_fixed_Asm_S16: return ARM::VST1LNd16_UPD; 4830 case ARM::VST1LNdWB_fixed_Asm_U16: return ARM::VST1LNd16_UPD; 4831 case ARM::VST1LNdWB_fixed_Asm_32: return ARM::VST1LNd32_UPD; 4832 case ARM::VST1LNdWB_fixed_Asm_F: return ARM::VST1LNd32_UPD; 4833 case ARM::VST1LNdWB_fixed_Asm_F32: return ARM::VST1LNd32_UPD; 4834 case ARM::VST1LNdWB_fixed_Asm_I32: return ARM::VST1LNd32_UPD; 4835 case ARM::VST1LNdWB_fixed_Asm_S32: return ARM::VST1LNd32_UPD; 4836 case ARM::VST1LNdWB_fixed_Asm_U32: return ARM::VST1LNd32_UPD; 4837 case ARM::VST1LNdWB_register_Asm_8: return ARM::VST1LNd8_UPD; 4838 case ARM::VST1LNdWB_register_Asm_P8: return ARM::VST1LNd8_UPD; 4839 case ARM::VST1LNdWB_register_Asm_I8: return ARM::VST1LNd8_UPD; 4840 case ARM::VST1LNdWB_register_Asm_S8: return ARM::VST1LNd8_UPD; 4841 case ARM::VST1LNdWB_register_Asm_U8: return ARM::VST1LNd8_UPD; 4842 case ARM::VST1LNdWB_register_Asm_16: return ARM::VST1LNd16_UPD; 4843 case ARM::VST1LNdWB_register_Asm_P16: return ARM::VST1LNd16_UPD; 4844 case ARM::VST1LNdWB_register_Asm_I16: return ARM::VST1LNd16_UPD; 4845 case ARM::VST1LNdWB_register_Asm_S16: return ARM::VST1LNd16_UPD; 4846 case ARM::VST1LNdWB_register_Asm_U16: return ARM::VST1LNd16_UPD; 4847 case ARM::VST1LNdWB_register_Asm_32: return ARM::VST1LNd32_UPD; 4848 case ARM::VST1LNdWB_register_Asm_F: return ARM::VST1LNd32_UPD; 4849 case ARM::VST1LNdWB_register_Asm_F32: return ARM::VST1LNd32_UPD; 4850 case ARM::VST1LNdWB_register_Asm_I32: return ARM::VST1LNd32_UPD; 4851 case ARM::VST1LNdWB_register_Asm_S32: return ARM::VST1LNd32_UPD; 4852 case ARM::VST1LNdWB_register_Asm_U32: return ARM::VST1LNd32_UPD; 4853 case ARM::VST1LNdAsm_8: return ARM::VST1LNd8; 4854 case ARM::VST1LNdAsm_P8: return ARM::VST1LNd8; 4855 case ARM::VST1LNdAsm_I8: return ARM::VST1LNd8; 4856 case ARM::VST1LNdAsm_S8: return ARM::VST1LNd8; 4857 case ARM::VST1LNdAsm_U8: return ARM::VST1LNd8; 4858 case ARM::VST1LNdAsm_16: return ARM::VST1LNd16; 4859 case ARM::VST1LNdAsm_P16: return ARM::VST1LNd16; 4860 case ARM::VST1LNdAsm_I16: return ARM::VST1LNd16; 4861 case ARM::VST1LNdAsm_S16: return ARM::VST1LNd16; 4862 case ARM::VST1LNdAsm_U16: return ARM::VST1LNd16; 4863 case ARM::VST1LNdAsm_32: return ARM::VST1LNd32; 4864 case ARM::VST1LNdAsm_F: return ARM::VST1LNd32; 4865 case ARM::VST1LNdAsm_F32: return ARM::VST1LNd32; 4866 case ARM::VST1LNdAsm_I32: return ARM::VST1LNd32; 4867 case ARM::VST1LNdAsm_S32: return ARM::VST1LNd32; 4868 case ARM::VST1LNdAsm_U32: return ARM::VST1LNd32; 4869 } 4870 } 4871 4872 static unsigned getRealVLDLNOpcode(unsigned Opc) { 4873 switch(Opc) { 4874 default: assert(0 && "unexpected opcode!"); 4875 case ARM::VLD1LNdWB_fixed_Asm_8: return ARM::VLD1LNd8_UPD; 4876 case ARM::VLD1LNdWB_fixed_Asm_P8: return ARM::VLD1LNd8_UPD; 4877 case ARM::VLD1LNdWB_fixed_Asm_I8: return ARM::VLD1LNd8_UPD; 4878 case ARM::VLD1LNdWB_fixed_Asm_S8: return ARM::VLD1LNd8_UPD; 4879 case ARM::VLD1LNdWB_fixed_Asm_U8: return ARM::VLD1LNd8_UPD; 4880 case ARM::VLD1LNdWB_fixed_Asm_16: return ARM::VLD1LNd16_UPD; 4881 case ARM::VLD1LNdWB_fixed_Asm_P16: return ARM::VLD1LNd16_UPD; 4882 case ARM::VLD1LNdWB_fixed_Asm_I16: return ARM::VLD1LNd16_UPD; 4883 case ARM::VLD1LNdWB_fixed_Asm_S16: return ARM::VLD1LNd16_UPD; 4884 case ARM::VLD1LNdWB_fixed_Asm_U16: return ARM::VLD1LNd16_UPD; 4885 case ARM::VLD1LNdWB_fixed_Asm_32: return ARM::VLD1LNd32_UPD; 4886 case ARM::VLD1LNdWB_fixed_Asm_F: return ARM::VLD1LNd32_UPD; 4887 case ARM::VLD1LNdWB_fixed_Asm_F32: return ARM::VLD1LNd32_UPD; 4888 case ARM::VLD1LNdWB_fixed_Asm_I32: return ARM::VLD1LNd32_UPD; 4889 case ARM::VLD1LNdWB_fixed_Asm_S32: return ARM::VLD1LNd32_UPD; 4890 case ARM::VLD1LNdWB_fixed_Asm_U32: return ARM::VLD1LNd32_UPD; 4891 case ARM::VLD1LNdWB_register_Asm_8: return ARM::VLD1LNd8_UPD; 4892 case ARM::VLD1LNdWB_register_Asm_P8: return ARM::VLD1LNd8_UPD; 4893 case ARM::VLD1LNdWB_register_Asm_I8: return ARM::VLD1LNd8_UPD; 4894 case ARM::VLD1LNdWB_register_Asm_S8: return ARM::VLD1LNd8_UPD; 4895 case ARM::VLD1LNdWB_register_Asm_U8: return ARM::VLD1LNd8_UPD; 4896 case ARM::VLD1LNdWB_register_Asm_16: return ARM::VLD1LNd16_UPD; 4897 case ARM::VLD1LNdWB_register_Asm_P16: return ARM::VLD1LNd16_UPD; 4898 case ARM::VLD1LNdWB_register_Asm_I16: return ARM::VLD1LNd16_UPD; 4899 case ARM::VLD1LNdWB_register_Asm_S16: return ARM::VLD1LNd16_UPD; 4900 case ARM::VLD1LNdWB_register_Asm_U16: return ARM::VLD1LNd16_UPD; 4901 case ARM::VLD1LNdWB_register_Asm_32: return ARM::VLD1LNd32_UPD; 4902 case ARM::VLD1LNdWB_register_Asm_F: return ARM::VLD1LNd32_UPD; 4903 case ARM::VLD1LNdWB_register_Asm_F32: return ARM::VLD1LNd32_UPD; 4904 case ARM::VLD1LNdWB_register_Asm_I32: return ARM::VLD1LNd32_UPD; 4905 case ARM::VLD1LNdWB_register_Asm_S32: return ARM::VLD1LNd32_UPD; 4906 case ARM::VLD1LNdWB_register_Asm_U32: return ARM::VLD1LNd32_UPD; 4907 case ARM::VLD1LNdAsm_8: return ARM::VLD1LNd8; 4908 case ARM::VLD1LNdAsm_P8: return ARM::VLD1LNd8; 4909 case ARM::VLD1LNdAsm_I8: return ARM::VLD1LNd8; 4910 case ARM::VLD1LNdAsm_S8: return ARM::VLD1LNd8; 4911 case ARM::VLD1LNdAsm_U8: return ARM::VLD1LNd8; 4912 case ARM::VLD1LNdAsm_16: return ARM::VLD1LNd16; 4913 case ARM::VLD1LNdAsm_P16: return ARM::VLD1LNd16; 4914 case ARM::VLD1LNdAsm_I16: return ARM::VLD1LNd16; 4915 case ARM::VLD1LNdAsm_S16: return ARM::VLD1LNd16; 4916 case ARM::VLD1LNdAsm_U16: return ARM::VLD1LNd16; 4917 case ARM::VLD1LNdAsm_32: return ARM::VLD1LNd32; 4918 case ARM::VLD1LNdAsm_F: return ARM::VLD1LNd32; 4919 case ARM::VLD1LNdAsm_F32: return ARM::VLD1LNd32; 4920 case ARM::VLD1LNdAsm_I32: return ARM::VLD1LNd32; 4921 case ARM::VLD1LNdAsm_S32: return ARM::VLD1LNd32; 4922 case ARM::VLD1LNdAsm_U32: return ARM::VLD1LNd32; 4923 } 4924 } 4925 4926 bool ARMAsmParser:: 4927 processInstruction(MCInst &Inst, 4928 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4929 switch (Inst.getOpcode()) { 4930 // Handle NEON VST1 complex aliases. 4931 case ARM::VST1LNdWB_register_Asm_8: 4932 case ARM::VST1LNdWB_register_Asm_P8: 4933 case ARM::VST1LNdWB_register_Asm_I8: 4934 case ARM::VST1LNdWB_register_Asm_S8: 4935 case ARM::VST1LNdWB_register_Asm_U8: 4936 case ARM::VST1LNdWB_register_Asm_16: 4937 case ARM::VST1LNdWB_register_Asm_P16: 4938 case ARM::VST1LNdWB_register_Asm_I16: 4939 case ARM::VST1LNdWB_register_Asm_S16: 4940 case ARM::VST1LNdWB_register_Asm_U16: 4941 case ARM::VST1LNdWB_register_Asm_32: 4942 case ARM::VST1LNdWB_register_Asm_F: 4943 case ARM::VST1LNdWB_register_Asm_F32: 4944 case ARM::VST1LNdWB_register_Asm_I32: 4945 case ARM::VST1LNdWB_register_Asm_S32: 4946 case ARM::VST1LNdWB_register_Asm_U32: { 4947 MCInst TmpInst; 4948 // Shuffle the operands around so the lane index operand is in the 4949 // right place. 4950 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); 4951 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 4952 TmpInst.addOperand(Inst.getOperand(2)); // Rn 4953 TmpInst.addOperand(Inst.getOperand(3)); // alignment 4954 TmpInst.addOperand(Inst.getOperand(4)); // Rm 4955 TmpInst.addOperand(Inst.getOperand(0)); // Vd 4956 TmpInst.addOperand(Inst.getOperand(1)); // lane 4957 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 4958 TmpInst.addOperand(Inst.getOperand(6)); 4959 Inst = TmpInst; 4960 return true; 4961 } 4962 case ARM::VST1LNdWB_fixed_Asm_8: 4963 case ARM::VST1LNdWB_fixed_Asm_P8: 4964 case ARM::VST1LNdWB_fixed_Asm_I8: 4965 case ARM::VST1LNdWB_fixed_Asm_S8: 4966 case ARM::VST1LNdWB_fixed_Asm_U8: 4967 case ARM::VST1LNdWB_fixed_Asm_16: 4968 case ARM::VST1LNdWB_fixed_Asm_P16: 4969 case ARM::VST1LNdWB_fixed_Asm_I16: 4970 case ARM::VST1LNdWB_fixed_Asm_S16: 4971 case ARM::VST1LNdWB_fixed_Asm_U16: 4972 case ARM::VST1LNdWB_fixed_Asm_32: 4973 case ARM::VST1LNdWB_fixed_Asm_F: 4974 case ARM::VST1LNdWB_fixed_Asm_F32: 4975 case ARM::VST1LNdWB_fixed_Asm_I32: 4976 case ARM::VST1LNdWB_fixed_Asm_S32: 4977 case ARM::VST1LNdWB_fixed_Asm_U32: { 4978 MCInst TmpInst; 4979 // Shuffle the operands around so the lane index operand is in the 4980 // right place. 4981 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); 4982 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 4983 TmpInst.addOperand(Inst.getOperand(2)); // Rn 4984 TmpInst.addOperand(Inst.getOperand(3)); // alignment 4985 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 4986 TmpInst.addOperand(Inst.getOperand(0)); // Vd 4987 TmpInst.addOperand(Inst.getOperand(1)); // lane 4988 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 4989 TmpInst.addOperand(Inst.getOperand(5)); 4990 Inst = TmpInst; 4991 return true; 4992 } 4993 case ARM::VST1LNdAsm_8: 4994 case ARM::VST1LNdAsm_P8: 4995 case ARM::VST1LNdAsm_I8: 4996 case ARM::VST1LNdAsm_S8: 4997 case ARM::VST1LNdAsm_U8: 4998 case ARM::VST1LNdAsm_16: 4999 case ARM::VST1LNdAsm_P16: 5000 case ARM::VST1LNdAsm_I16: 5001 case ARM::VST1LNdAsm_S16: 5002 case ARM::VST1LNdAsm_U16: 5003 case ARM::VST1LNdAsm_32: 5004 case ARM::VST1LNdAsm_F: 5005 case ARM::VST1LNdAsm_F32: 5006 case ARM::VST1LNdAsm_I32: 5007 case ARM::VST1LNdAsm_S32: 5008 case ARM::VST1LNdAsm_U32: { 5009 MCInst TmpInst; 5010 // Shuffle the operands around so the lane index operand is in the 5011 // right place. 5012 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode())); 5013 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5014 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5015 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5016 TmpInst.addOperand(Inst.getOperand(1)); // lane 5017 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5018 TmpInst.addOperand(Inst.getOperand(5)); 5019 Inst = TmpInst; 5020 return true; 5021 } 5022 // Handle NEON VLD1 complex aliases. 5023 case ARM::VLD1LNdWB_register_Asm_8: 5024 case ARM::VLD1LNdWB_register_Asm_P8: 5025 case ARM::VLD1LNdWB_register_Asm_I8: 5026 case ARM::VLD1LNdWB_register_Asm_S8: 5027 case ARM::VLD1LNdWB_register_Asm_U8: 5028 case ARM::VLD1LNdWB_register_Asm_16: 5029 case ARM::VLD1LNdWB_register_Asm_P16: 5030 case ARM::VLD1LNdWB_register_Asm_I16: 5031 case ARM::VLD1LNdWB_register_Asm_S16: 5032 case ARM::VLD1LNdWB_register_Asm_U16: 5033 case ARM::VLD1LNdWB_register_Asm_32: 5034 case ARM::VLD1LNdWB_register_Asm_F: 5035 case ARM::VLD1LNdWB_register_Asm_F32: 5036 case ARM::VLD1LNdWB_register_Asm_I32: 5037 case ARM::VLD1LNdWB_register_Asm_S32: 5038 case ARM::VLD1LNdWB_register_Asm_U32: { 5039 MCInst TmpInst; 5040 // Shuffle the operands around so the lane index operand is in the 5041 // right place. 5042 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); 5043 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5044 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5045 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5046 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5047 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5048 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5049 TmpInst.addOperand(Inst.getOperand(1)); // lane 5050 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5051 TmpInst.addOperand(Inst.getOperand(6)); 5052 Inst = TmpInst; 5053 return true; 5054 } 5055 case ARM::VLD1LNdWB_fixed_Asm_8: 5056 case ARM::VLD1LNdWB_fixed_Asm_P8: 5057 case ARM::VLD1LNdWB_fixed_Asm_I8: 5058 case ARM::VLD1LNdWB_fixed_Asm_S8: 5059 case ARM::VLD1LNdWB_fixed_Asm_U8: 5060 case ARM::VLD1LNdWB_fixed_Asm_16: 5061 case ARM::VLD1LNdWB_fixed_Asm_P16: 5062 case ARM::VLD1LNdWB_fixed_Asm_I16: 5063 case ARM::VLD1LNdWB_fixed_Asm_S16: 5064 case ARM::VLD1LNdWB_fixed_Asm_U16: 5065 case ARM::VLD1LNdWB_fixed_Asm_32: 5066 case ARM::VLD1LNdWB_fixed_Asm_F: 5067 case ARM::VLD1LNdWB_fixed_Asm_F32: 5068 case ARM::VLD1LNdWB_fixed_Asm_I32: 5069 case ARM::VLD1LNdWB_fixed_Asm_S32: 5070 case ARM::VLD1LNdWB_fixed_Asm_U32: { 5071 MCInst TmpInst; 5072 // Shuffle the operands around so the lane index operand is in the 5073 // right place. 5074 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); 5075 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5076 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5077 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5078 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5079 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5080 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5081 TmpInst.addOperand(Inst.getOperand(1)); // lane 5082 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5083 TmpInst.addOperand(Inst.getOperand(5)); 5084 Inst = TmpInst; 5085 return true; 5086 } 5087 case ARM::VLD1LNdAsm_8: 5088 case ARM::VLD1LNdAsm_P8: 5089 case ARM::VLD1LNdAsm_I8: 5090 case ARM::VLD1LNdAsm_S8: 5091 case ARM::VLD1LNdAsm_U8: 5092 case ARM::VLD1LNdAsm_16: 5093 case ARM::VLD1LNdAsm_P16: 5094 case ARM::VLD1LNdAsm_I16: 5095 case ARM::VLD1LNdAsm_S16: 5096 case ARM::VLD1LNdAsm_U16: 5097 case ARM::VLD1LNdAsm_32: 5098 case ARM::VLD1LNdAsm_F: 5099 case ARM::VLD1LNdAsm_F32: 5100 case ARM::VLD1LNdAsm_I32: 5101 case ARM::VLD1LNdAsm_S32: 5102 case ARM::VLD1LNdAsm_U32: { 5103 MCInst TmpInst; 5104 // Shuffle the operands around so the lane index operand is in the 5105 // right place. 5106 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode())); 5107 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5108 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5109 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5110 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5111 TmpInst.addOperand(Inst.getOperand(1)); // lane 5112 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5113 TmpInst.addOperand(Inst.getOperand(5)); 5114 Inst = TmpInst; 5115 return true; 5116 } 5117 // Handle the MOV complex aliases. 5118 case ARM::ASRr: 5119 case ARM::LSRr: 5120 case ARM::LSLr: 5121 case ARM::RORr: { 5122 ARM_AM::ShiftOpc ShiftTy; 5123 switch(Inst.getOpcode()) { 5124 default: llvm_unreachable("unexpected opcode!"); 5125 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 5126 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 5127 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 5128 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 5129 } 5130 // A shift by zero is a plain MOVr, not a MOVsi. 5131 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 5132 MCInst TmpInst; 5133 TmpInst.setOpcode(ARM::MOVsr); 5134 TmpInst.addOperand(Inst.getOperand(0)); // Rd 5135 TmpInst.addOperand(Inst.getOperand(1)); // Rn 5136 TmpInst.addOperand(Inst.getOperand(2)); // Rm 5137 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 5138 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 5139 TmpInst.addOperand(Inst.getOperand(4)); 5140 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 5141 Inst = TmpInst; 5142 return true; 5143 } 5144 case ARM::ASRi: 5145 case ARM::LSRi: 5146 case ARM::LSLi: 5147 case ARM::RORi: { 5148 ARM_AM::ShiftOpc ShiftTy; 5149 switch(Inst.getOpcode()) { 5150 default: llvm_unreachable("unexpected opcode!"); 5151 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 5152 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 5153 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 5154 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 5155 } 5156 // A shift by zero is a plain MOVr, not a MOVsi. 5157 unsigned Amt = Inst.getOperand(2).getImm(); 5158 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 5159 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 5160 MCInst TmpInst; 5161 TmpInst.setOpcode(Opc); 5162 TmpInst.addOperand(Inst.getOperand(0)); // Rd 5163 TmpInst.addOperand(Inst.getOperand(1)); // Rn 5164 if (Opc == ARM::MOVsi) 5165 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 5166 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 5167 TmpInst.addOperand(Inst.getOperand(4)); 5168 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 5169 Inst = TmpInst; 5170 return true; 5171 } 5172 case ARM::RRXi: { 5173 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 5174 MCInst TmpInst; 5175 TmpInst.setOpcode(ARM::MOVsi); 5176 TmpInst.addOperand(Inst.getOperand(0)); // Rd 5177 TmpInst.addOperand(Inst.getOperand(1)); // Rn 5178 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 5179 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 5180 TmpInst.addOperand(Inst.getOperand(3)); 5181 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 5182 Inst = TmpInst; 5183 return true; 5184 } 5185 case ARM::t2LDMIA_UPD: { 5186 // If this is a load of a single register, then we should use 5187 // a post-indexed LDR instruction instead, per the ARM ARM. 5188 if (Inst.getNumOperands() != 5) 5189 return false; 5190 MCInst TmpInst; 5191 TmpInst.setOpcode(ARM::t2LDR_POST); 5192 TmpInst.addOperand(Inst.getOperand(4)); // Rt 5193 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 5194 TmpInst.addOperand(Inst.getOperand(1)); // Rn 5195 TmpInst.addOperand(MCOperand::CreateImm(4)); 5196 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 5197 TmpInst.addOperand(Inst.getOperand(3)); 5198 Inst = TmpInst; 5199 return true; 5200 } 5201 case ARM::t2STMDB_UPD: { 5202 // If this is a store of a single register, then we should use 5203 // a pre-indexed STR instruction instead, per the ARM ARM. 5204 if (Inst.getNumOperands() != 5) 5205 return false; 5206 MCInst TmpInst; 5207 TmpInst.setOpcode(ARM::t2STR_PRE); 5208 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 5209 TmpInst.addOperand(Inst.getOperand(4)); // Rt 5210 TmpInst.addOperand(Inst.getOperand(1)); // Rn 5211 TmpInst.addOperand(MCOperand::CreateImm(-4)); 5212 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 5213 TmpInst.addOperand(Inst.getOperand(3)); 5214 Inst = TmpInst; 5215 return true; 5216 } 5217 case ARM::LDMIA_UPD: 5218 // If this is a load of a single register via a 'pop', then we should use 5219 // a post-indexed LDR instruction instead, per the ARM ARM. 5220 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 5221 Inst.getNumOperands() == 5) { 5222 MCInst TmpInst; 5223 TmpInst.setOpcode(ARM::LDR_POST_IMM); 5224 TmpInst.addOperand(Inst.getOperand(4)); // Rt 5225 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 5226 TmpInst.addOperand(Inst.getOperand(1)); // Rn 5227 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 5228 TmpInst.addOperand(MCOperand::CreateImm(4)); 5229 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 5230 TmpInst.addOperand(Inst.getOperand(3)); 5231 Inst = TmpInst; 5232 return true; 5233 } 5234 break; 5235 case ARM::STMDB_UPD: 5236 // If this is a store of a single register via a 'push', then we should use 5237 // a pre-indexed STR instruction instead, per the ARM ARM. 5238 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 5239 Inst.getNumOperands() == 5) { 5240 MCInst TmpInst; 5241 TmpInst.setOpcode(ARM::STR_PRE_IMM); 5242 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 5243 TmpInst.addOperand(Inst.getOperand(4)); // Rt 5244 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 5245 TmpInst.addOperand(MCOperand::CreateImm(-4)); 5246 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 5247 TmpInst.addOperand(Inst.getOperand(3)); 5248 Inst = TmpInst; 5249 } 5250 break; 5251 case ARM::t2ADDri12: 5252 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 5253 // mnemonic was used (not "addw"), encoding T3 is preferred. 5254 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 5255 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 5256 break; 5257 Inst.setOpcode(ARM::t2ADDri); 5258 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 5259 break; 5260 case ARM::t2SUBri12: 5261 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 5262 // mnemonic was used (not "subw"), encoding T3 is preferred. 5263 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 5264 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 5265 break; 5266 Inst.setOpcode(ARM::t2SUBri); 5267 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 5268 break; 5269 case ARM::tADDi8: 5270 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 5271 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 5272 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 5273 // to encoding T1 if <Rd> is omitted." 5274 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 5275 Inst.setOpcode(ARM::tADDi3); 5276 return true; 5277 } 5278 break; 5279 case ARM::tSUBi8: 5280 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 5281 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 5282 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 5283 // to encoding T1 if <Rd> is omitted." 5284 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 5285 Inst.setOpcode(ARM::tSUBi3); 5286 return true; 5287 } 5288 break; 5289 case ARM::t2ADDrr: { 5290 // If the destination and first source operand are the same, and 5291 // there's no setting of the flags, use encoding T2 instead of T3. 5292 // Note that this is only for ADD, not SUB. This mirrors the system 5293 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 5294 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 5295 Inst.getOperand(5).getReg() != 0 || 5296 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5297 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 5298 break; 5299 MCInst TmpInst; 5300 TmpInst.setOpcode(ARM::tADDhirr); 5301 TmpInst.addOperand(Inst.getOperand(0)); 5302 TmpInst.addOperand(Inst.getOperand(0)); 5303 TmpInst.addOperand(Inst.getOperand(2)); 5304 TmpInst.addOperand(Inst.getOperand(3)); 5305 TmpInst.addOperand(Inst.getOperand(4)); 5306 Inst = TmpInst; 5307 return true; 5308 } 5309 case ARM::tB: 5310 // A Thumb conditional branch outside of an IT block is a tBcc. 5311 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 5312 Inst.setOpcode(ARM::tBcc); 5313 return true; 5314 } 5315 break; 5316 case ARM::t2B: 5317 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 5318 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 5319 Inst.setOpcode(ARM::t2Bcc); 5320 return true; 5321 } 5322 break; 5323 case ARM::t2Bcc: 5324 // If the conditional is AL or we're in an IT block, we really want t2B. 5325 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 5326 Inst.setOpcode(ARM::t2B); 5327 return true; 5328 } 5329 break; 5330 case ARM::tBcc: 5331 // If the conditional is AL, we really want tB. 5332 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 5333 Inst.setOpcode(ARM::tB); 5334 return true; 5335 } 5336 break; 5337 case ARM::tLDMIA: { 5338 // If the register list contains any high registers, or if the writeback 5339 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 5340 // instead if we're in Thumb2. Otherwise, this should have generated 5341 // an error in validateInstruction(). 5342 unsigned Rn = Inst.getOperand(0).getReg(); 5343 bool hasWritebackToken = 5344 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5345 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5346 bool listContainsBase; 5347 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 5348 (!listContainsBase && !hasWritebackToken) || 5349 (listContainsBase && hasWritebackToken)) { 5350 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 5351 assert (isThumbTwo()); 5352 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 5353 // If we're switching to the updating version, we need to insert 5354 // the writeback tied operand. 5355 if (hasWritebackToken) 5356 Inst.insert(Inst.begin(), 5357 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 5358 return true; 5359 } 5360 break; 5361 } 5362 case ARM::tSTMIA_UPD: { 5363 // If the register list contains any high registers, we need to use 5364 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 5365 // should have generated an error in validateInstruction(). 5366 unsigned Rn = Inst.getOperand(0).getReg(); 5367 bool listContainsBase; 5368 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 5369 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 5370 assert (isThumbTwo()); 5371 Inst.setOpcode(ARM::t2STMIA_UPD); 5372 return true; 5373 } 5374 break; 5375 } 5376 case ARM::tPOP: { 5377 bool listContainsBase; 5378 // If the register list contains any high registers, we need to use 5379 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 5380 // should have generated an error in validateInstruction(). 5381 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 5382 return false; 5383 assert (isThumbTwo()); 5384 Inst.setOpcode(ARM::t2LDMIA_UPD); 5385 // Add the base register and writeback operands. 5386 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 5387 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 5388 return true; 5389 } 5390 case ARM::tPUSH: { 5391 bool listContainsBase; 5392 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 5393 return false; 5394 assert (isThumbTwo()); 5395 Inst.setOpcode(ARM::t2STMDB_UPD); 5396 // Add the base register and writeback operands. 5397 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 5398 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 5399 return true; 5400 } 5401 case ARM::t2MOVi: { 5402 // If we can use the 16-bit encoding and the user didn't explicitly 5403 // request the 32-bit variant, transform it here. 5404 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 5405 Inst.getOperand(1).getImm() <= 255 && 5406 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 5407 Inst.getOperand(4).getReg() == ARM::CPSR) || 5408 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 5409 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 5410 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 5411 // The operands aren't in the same order for tMOVi8... 5412 MCInst TmpInst; 5413 TmpInst.setOpcode(ARM::tMOVi8); 5414 TmpInst.addOperand(Inst.getOperand(0)); 5415 TmpInst.addOperand(Inst.getOperand(4)); 5416 TmpInst.addOperand(Inst.getOperand(1)); 5417 TmpInst.addOperand(Inst.getOperand(2)); 5418 TmpInst.addOperand(Inst.getOperand(3)); 5419 Inst = TmpInst; 5420 return true; 5421 } 5422 break; 5423 } 5424 case ARM::t2MOVr: { 5425 // If we can use the 16-bit encoding and the user didn't explicitly 5426 // request the 32-bit variant, transform it here. 5427 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 5428 isARMLowRegister(Inst.getOperand(1).getReg()) && 5429 Inst.getOperand(2).getImm() == ARMCC::AL && 5430 Inst.getOperand(4).getReg() == ARM::CPSR && 5431 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 5432 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 5433 // The operands aren't the same for tMOV[S]r... (no cc_out) 5434 MCInst TmpInst; 5435 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 5436 TmpInst.addOperand(Inst.getOperand(0)); 5437 TmpInst.addOperand(Inst.getOperand(1)); 5438 TmpInst.addOperand(Inst.getOperand(2)); 5439 TmpInst.addOperand(Inst.getOperand(3)); 5440 Inst = TmpInst; 5441 return true; 5442 } 5443 break; 5444 } 5445 case ARM::t2SXTH: 5446 case ARM::t2SXTB: 5447 case ARM::t2UXTH: 5448 case ARM::t2UXTB: { 5449 // If we can use the 16-bit encoding and the user didn't explicitly 5450 // request the 32-bit variant, transform it here. 5451 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 5452 isARMLowRegister(Inst.getOperand(1).getReg()) && 5453 Inst.getOperand(2).getImm() == 0 && 5454 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 5455 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 5456 unsigned NewOpc; 5457 switch (Inst.getOpcode()) { 5458 default: llvm_unreachable("Illegal opcode!"); 5459 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 5460 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 5461 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 5462 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 5463 } 5464 // The operands aren't the same for thumb1 (no rotate operand). 5465 MCInst TmpInst; 5466 TmpInst.setOpcode(NewOpc); 5467 TmpInst.addOperand(Inst.getOperand(0)); 5468 TmpInst.addOperand(Inst.getOperand(1)); 5469 TmpInst.addOperand(Inst.getOperand(3)); 5470 TmpInst.addOperand(Inst.getOperand(4)); 5471 Inst = TmpInst; 5472 return true; 5473 } 5474 break; 5475 } 5476 case ARM::t2IT: { 5477 // The mask bits for all but the first condition are represented as 5478 // the low bit of the condition code value implies 't'. We currently 5479 // always have 1 implies 't', so XOR toggle the bits if the low bit 5480 // of the condition code is zero. The encoding also expects the low 5481 // bit of the condition to be encoded as bit 4 of the mask operand, 5482 // so mask that in if needed 5483 MCOperand &MO = Inst.getOperand(1); 5484 unsigned Mask = MO.getImm(); 5485 unsigned OrigMask = Mask; 5486 unsigned TZ = CountTrailingZeros_32(Mask); 5487 if ((Inst.getOperand(0).getImm() & 1) == 0) { 5488 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 5489 for (unsigned i = 3; i != TZ; --i) 5490 Mask ^= 1 << i; 5491 } else 5492 Mask |= 0x10; 5493 MO.setImm(Mask); 5494 5495 // Set up the IT block state according to the IT instruction we just 5496 // matched. 5497 assert(!inITBlock() && "nested IT blocks?!"); 5498 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 5499 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 5500 ITState.CurPosition = 0; 5501 ITState.FirstCond = true; 5502 break; 5503 } 5504 } 5505 return false; 5506 } 5507 5508 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 5509 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 5510 // suffix depending on whether they're in an IT block or not. 5511 unsigned Opc = Inst.getOpcode(); 5512 const MCInstrDesc &MCID = getInstDesc(Opc); 5513 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 5514 assert(MCID.hasOptionalDef() && 5515 "optionally flag setting instruction missing optional def operand"); 5516 assert(MCID.NumOperands == Inst.getNumOperands() && 5517 "operand count mismatch!"); 5518 // Find the optional-def operand (cc_out). 5519 unsigned OpNo; 5520 for (OpNo = 0; 5521 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 5522 ++OpNo) 5523 ; 5524 // If we're parsing Thumb1, reject it completely. 5525 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 5526 return Match_MnemonicFail; 5527 // If we're parsing Thumb2, which form is legal depends on whether we're 5528 // in an IT block. 5529 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 5530 !inITBlock()) 5531 return Match_RequiresITBlock; 5532 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 5533 inITBlock()) 5534 return Match_RequiresNotITBlock; 5535 } 5536 // Some high-register supporting Thumb1 encodings only allow both registers 5537 // to be from r0-r7 when in Thumb2. 5538 else if (Opc == ARM::tADDhirr && isThumbOne() && 5539 isARMLowRegister(Inst.getOperand(1).getReg()) && 5540 isARMLowRegister(Inst.getOperand(2).getReg())) 5541 return Match_RequiresThumb2; 5542 // Others only require ARMv6 or later. 5543 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 5544 isARMLowRegister(Inst.getOperand(0).getReg()) && 5545 isARMLowRegister(Inst.getOperand(1).getReg())) 5546 return Match_RequiresV6; 5547 return Match_Success; 5548 } 5549 5550 bool ARMAsmParser:: 5551 MatchAndEmitInstruction(SMLoc IDLoc, 5552 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 5553 MCStreamer &Out) { 5554 MCInst Inst; 5555 unsigned ErrorInfo; 5556 unsigned MatchResult; 5557 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 5558 switch (MatchResult) { 5559 default: break; 5560 case Match_Success: 5561 // Context sensitive operand constraints aren't handled by the matcher, 5562 // so check them here. 5563 if (validateInstruction(Inst, Operands)) { 5564 // Still progress the IT block, otherwise one wrong condition causes 5565 // nasty cascading errors. 5566 forwardITPosition(); 5567 return true; 5568 } 5569 5570 // Some instructions need post-processing to, for example, tweak which 5571 // encoding is selected. Loop on it while changes happen so the 5572 // individual transformations can chain off each other. E.g., 5573 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 5574 while (processInstruction(Inst, Operands)) 5575 ; 5576 5577 // Only move forward at the very end so that everything in validate 5578 // and process gets a consistent answer about whether we're in an IT 5579 // block. 5580 forwardITPosition(); 5581 5582 Out.EmitInstruction(Inst); 5583 return false; 5584 case Match_MissingFeature: 5585 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 5586 return true; 5587 case Match_InvalidOperand: { 5588 SMLoc ErrorLoc = IDLoc; 5589 if (ErrorInfo != ~0U) { 5590 if (ErrorInfo >= Operands.size()) 5591 return Error(IDLoc, "too few operands for instruction"); 5592 5593 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 5594 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 5595 } 5596 5597 return Error(ErrorLoc, "invalid operand for instruction"); 5598 } 5599 case Match_MnemonicFail: 5600 return Error(IDLoc, "invalid instruction"); 5601 case Match_ConversionFail: 5602 // The converter function will have already emited a diagnostic. 5603 return true; 5604 case Match_RequiresNotITBlock: 5605 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 5606 case Match_RequiresITBlock: 5607 return Error(IDLoc, "instruction only valid inside IT block"); 5608 case Match_RequiresV6: 5609 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 5610 case Match_RequiresThumb2: 5611 return Error(IDLoc, "instruction variant requires Thumb2"); 5612 } 5613 5614 llvm_unreachable("Implement any new match types added!"); 5615 return true; 5616 } 5617 5618 /// parseDirective parses the arm specific directives 5619 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 5620 StringRef IDVal = DirectiveID.getIdentifier(); 5621 if (IDVal == ".word") 5622 return parseDirectiveWord(4, DirectiveID.getLoc()); 5623 else if (IDVal == ".thumb") 5624 return parseDirectiveThumb(DirectiveID.getLoc()); 5625 else if (IDVal == ".thumb_func") 5626 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 5627 else if (IDVal == ".code") 5628 return parseDirectiveCode(DirectiveID.getLoc()); 5629 else if (IDVal == ".syntax") 5630 return parseDirectiveSyntax(DirectiveID.getLoc()); 5631 return true; 5632 } 5633 5634 /// parseDirectiveWord 5635 /// ::= .word [ expression (, expression)* ] 5636 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 5637 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5638 for (;;) { 5639 const MCExpr *Value; 5640 if (getParser().ParseExpression(Value)) 5641 return true; 5642 5643 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 5644 5645 if (getLexer().is(AsmToken::EndOfStatement)) 5646 break; 5647 5648 // FIXME: Improve diagnostic. 5649 if (getLexer().isNot(AsmToken::Comma)) 5650 return Error(L, "unexpected token in directive"); 5651 Parser.Lex(); 5652 } 5653 } 5654 5655 Parser.Lex(); 5656 return false; 5657 } 5658 5659 /// parseDirectiveThumb 5660 /// ::= .thumb 5661 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 5662 if (getLexer().isNot(AsmToken::EndOfStatement)) 5663 return Error(L, "unexpected token in directive"); 5664 Parser.Lex(); 5665 5666 // TODO: set thumb mode 5667 // TODO: tell the MC streamer the mode 5668 // getParser().getStreamer().Emit???(); 5669 return false; 5670 } 5671 5672 /// parseDirectiveThumbFunc 5673 /// ::= .thumbfunc symbol_name 5674 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 5675 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 5676 bool isMachO = MAI.hasSubsectionsViaSymbols(); 5677 StringRef Name; 5678 5679 // Darwin asm has function name after .thumb_func direction 5680 // ELF doesn't 5681 if (isMachO) { 5682 const AsmToken &Tok = Parser.getTok(); 5683 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 5684 return Error(L, "unexpected token in .thumb_func directive"); 5685 Name = Tok.getIdentifier(); 5686 Parser.Lex(); // Consume the identifier token. 5687 } 5688 5689 if (getLexer().isNot(AsmToken::EndOfStatement)) 5690 return Error(L, "unexpected token in directive"); 5691 Parser.Lex(); 5692 5693 // FIXME: assuming function name will be the line following .thumb_func 5694 if (!isMachO) { 5695 Name = Parser.getTok().getIdentifier(); 5696 } 5697 5698 // Mark symbol as a thumb symbol. 5699 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 5700 getParser().getStreamer().EmitThumbFunc(Func); 5701 return false; 5702 } 5703 5704 /// parseDirectiveSyntax 5705 /// ::= .syntax unified | divided 5706 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 5707 const AsmToken &Tok = Parser.getTok(); 5708 if (Tok.isNot(AsmToken::Identifier)) 5709 return Error(L, "unexpected token in .syntax directive"); 5710 StringRef Mode = Tok.getString(); 5711 if (Mode == "unified" || Mode == "UNIFIED") 5712 Parser.Lex(); 5713 else if (Mode == "divided" || Mode == "DIVIDED") 5714 return Error(L, "'.syntax divided' arm asssembly not supported"); 5715 else 5716 return Error(L, "unrecognized syntax mode in .syntax directive"); 5717 5718 if (getLexer().isNot(AsmToken::EndOfStatement)) 5719 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 5720 Parser.Lex(); 5721 5722 // TODO tell the MC streamer the mode 5723 // getParser().getStreamer().Emit???(); 5724 return false; 5725 } 5726 5727 /// parseDirectiveCode 5728 /// ::= .code 16 | 32 5729 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 5730 const AsmToken &Tok = Parser.getTok(); 5731 if (Tok.isNot(AsmToken::Integer)) 5732 return Error(L, "unexpected token in .code directive"); 5733 int64_t Val = Parser.getTok().getIntVal(); 5734 if (Val == 16) 5735 Parser.Lex(); 5736 else if (Val == 32) 5737 Parser.Lex(); 5738 else 5739 return Error(L, "invalid operand to .code directive"); 5740 5741 if (getLexer().isNot(AsmToken::EndOfStatement)) 5742 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 5743 Parser.Lex(); 5744 5745 if (Val == 16) { 5746 if (!isThumb()) 5747 SwitchMode(); 5748 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 5749 } else { 5750 if (isThumb()) 5751 SwitchMode(); 5752 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 5753 } 5754 5755 return false; 5756 } 5757 5758 extern "C" void LLVMInitializeARMAsmLexer(); 5759 5760 /// Force static initialization. 5761 extern "C" void LLVMInitializeARMAsmParser() { 5762 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 5763 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 5764 LLVMInitializeARMAsmLexer(); 5765 } 5766 5767 #define GET_REGISTER_MATCHER 5768 #define GET_MATCHER_IMPLEMENTATION 5769 #include "ARMGenAsmMatcher.inc" 5770