1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMFeatures.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
24 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCExpr.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCObjectFileInfo.h"
30 #include "llvm/MC/MCParser/MCAsmLexer.h"
31 #include "llvm/MC/MCParser/MCAsmParser.h"
32 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/MC/MCSection.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSubtargetInfo.h"
39 #include "llvm/MC/MCSymbol.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SourceMgr.h"
48 #include "llvm/Support/TargetParser.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
51 
52 using namespace llvm;
53 
54 namespace {
55 
56 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
57 
58 static cl::opt<ImplicitItModeTy> ImplicitItMode(
59     "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
60     cl::desc("Allow conditional instructions outdside of an IT block"),
61     cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
62                           "Accept in both ISAs, emit implicit ITs in Thumb"),
63                clEnumValN(ImplicitItModeTy::Never, "never",
64                           "Warn in ARM, reject in Thumb"),
65                clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
66                           "Accept in ARM, reject in Thumb"),
67                clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
68                           "Warn in ARM, emit implicit ITs in Thumb")));
69 
70 class ARMOperand;
71 
72 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
73 
74 class UnwindContext {
75   MCAsmParser &Parser;
76 
77   typedef SmallVector<SMLoc, 4> Locs;
78 
79   Locs FnStartLocs;
80   Locs CantUnwindLocs;
81   Locs PersonalityLocs;
82   Locs PersonalityIndexLocs;
83   Locs HandlerDataLocs;
84   int FPReg;
85 
86 public:
87   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
88 
89   bool hasFnStart() const { return !FnStartLocs.empty(); }
90   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
91   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
92   bool hasPersonality() const {
93     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
94   }
95 
96   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
97   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
98   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
99   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
100   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
101 
102   void saveFPReg(int Reg) { FPReg = Reg; }
103   int getFPReg() const { return FPReg; }
104 
105   void emitFnStartLocNotes() const {
106     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
107          FI != FE; ++FI)
108       Parser.Note(*FI, ".fnstart was specified here");
109   }
110   void emitCantUnwindLocNotes() const {
111     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
112                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
113       Parser.Note(*UI, ".cantunwind was specified here");
114   }
115   void emitHandlerDataLocNotes() const {
116     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
117                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
118       Parser.Note(*HI, ".handlerdata was specified here");
119   }
120   void emitPersonalityLocNotes() const {
121     for (Locs::const_iterator PI = PersonalityLocs.begin(),
122                               PE = PersonalityLocs.end(),
123                               PII = PersonalityIndexLocs.begin(),
124                               PIE = PersonalityIndexLocs.end();
125          PI != PE || PII != PIE;) {
126       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
127         Parser.Note(*PI++, ".personality was specified here");
128       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
129         Parser.Note(*PII++, ".personalityindex was specified here");
130       else
131         llvm_unreachable(".personality and .personalityindex cannot be "
132                          "at the same location");
133     }
134   }
135 
136   void reset() {
137     FnStartLocs = Locs();
138     CantUnwindLocs = Locs();
139     PersonalityLocs = Locs();
140     HandlerDataLocs = Locs();
141     PersonalityIndexLocs = Locs();
142     FPReg = ARM::SP;
143   }
144 };
145 
146 class ARMAsmParser : public MCTargetAsmParser {
147   const MCInstrInfo &MII;
148   const MCRegisterInfo *MRI;
149   UnwindContext UC;
150 
151   ARMTargetStreamer &getTargetStreamer() {
152     assert(getParser().getStreamer().getTargetStreamer() &&
153            "do not have a target streamer");
154     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
155     return static_cast<ARMTargetStreamer &>(TS);
156   }
157 
158   // Map of register aliases registers via the .req directive.
159   StringMap<unsigned> RegisterReqs;
160 
161   bool NextSymbolIsThumb;
162 
163   bool useImplicitITThumb() const {
164     return ImplicitItMode == ImplicitItModeTy::Always ||
165            ImplicitItMode == ImplicitItModeTy::ThumbOnly;
166   }
167 
168   bool useImplicitITARM() const {
169     return ImplicitItMode == ImplicitItModeTy::Always ||
170            ImplicitItMode == ImplicitItModeTy::ARMOnly;
171   }
172 
173   struct {
174     ARMCC::CondCodes Cond;    // Condition for IT block.
175     unsigned Mask:4;          // Condition mask for instructions.
176                               // Starting at first 1 (from lsb).
177                               //   '1'  condition as indicated in IT.
178                               //   '0'  inverse of condition (else).
179                               // Count of instructions in IT block is
180                               // 4 - trailingzeroes(mask)
181                               // Note that this does not have the same encoding
182                               // as in the IT instruction, which also depends
183                               // on the low bit of the condition code.
184 
185     unsigned CurPosition;     // Current position in parsing of IT
186                               // block. In range [0,4], with 0 being the IT
187                               // instruction itself. Initialized according to
188                               // count of instructions in block.  ~0U if no
189                               // active IT block.
190 
191     bool IsExplicit;          // true  - The IT instruction was present in the
192                               //         input, we should not modify it.
193                               // false - The IT instruction was added
194                               //         implicitly, we can extend it if that
195                               //         would be legal.
196   } ITState;
197 
198   llvm::SmallVector<MCInst, 4> PendingConditionalInsts;
199 
200   void flushPendingInstructions(MCStreamer &Out) override {
201     if (!inImplicitITBlock()) {
202       assert(PendingConditionalInsts.size() == 0);
203       return;
204     }
205 
206     // Emit the IT instruction
207     unsigned Mask = getITMaskEncoding();
208     MCInst ITInst;
209     ITInst.setOpcode(ARM::t2IT);
210     ITInst.addOperand(MCOperand::createImm(ITState.Cond));
211     ITInst.addOperand(MCOperand::createImm(Mask));
212     Out.EmitInstruction(ITInst, getSTI());
213 
214     // Emit the conditonal instructions
215     assert(PendingConditionalInsts.size() <= 4);
216     for (const MCInst &Inst : PendingConditionalInsts) {
217       Out.EmitInstruction(Inst, getSTI());
218     }
219     PendingConditionalInsts.clear();
220 
221     // Clear the IT state
222     ITState.Mask = 0;
223     ITState.CurPosition = ~0U;
224   }
225 
226   bool inITBlock() { return ITState.CurPosition != ~0U; }
227   bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
228   bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
229   bool lastInITBlock() {
230     return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
231   }
232   void forwardITPosition() {
233     if (!inITBlock()) return;
234     // Move to the next instruction in the IT block, if there is one. If not,
235     // mark the block as done, except for implicit IT blocks, which we leave
236     // open until we find an instruction that can't be added to it.
237     unsigned TZ = countTrailingZeros(ITState.Mask);
238     if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
239       ITState.CurPosition = ~0U; // Done with the IT block after this.
240   }
241 
242   // Rewind the state of the current IT block, removing the last slot from it.
243   void rewindImplicitITPosition() {
244     assert(inImplicitITBlock());
245     assert(ITState.CurPosition > 1);
246     ITState.CurPosition--;
247     unsigned TZ = countTrailingZeros(ITState.Mask);
248     unsigned NewMask = 0;
249     NewMask |= ITState.Mask & (0xC << TZ);
250     NewMask |= 0x2 << TZ;
251     ITState.Mask = NewMask;
252   }
253 
254   // Rewind the state of the current IT block, removing the last slot from it.
255   // If we were at the first slot, this closes the IT block.
256   void discardImplicitITBlock() {
257     assert(inImplicitITBlock());
258     assert(ITState.CurPosition == 1);
259     ITState.CurPosition = ~0U;
260     return;
261   }
262 
263   // Get the encoding of the IT mask, as it will appear in an IT instruction.
264   unsigned getITMaskEncoding() {
265     assert(inITBlock());
266     unsigned Mask = ITState.Mask;
267     unsigned TZ = countTrailingZeros(Mask);
268     if ((ITState.Cond & 1) == 0) {
269       assert(Mask && TZ <= 3 && "illegal IT mask value!");
270       Mask ^= (0xE << TZ) & 0xF;
271     }
272     return Mask;
273   }
274 
275   // Get the condition code corresponding to the current IT block slot.
276   ARMCC::CondCodes currentITCond() {
277     unsigned MaskBit;
278     if (ITState.CurPosition == 1)
279       MaskBit = 1;
280     else
281       MaskBit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
282 
283     return MaskBit ? ITState.Cond : ARMCC::getOppositeCondition(ITState.Cond);
284   }
285 
286   // Invert the condition of the current IT block slot without changing any
287   // other slots in the same block.
288   void invertCurrentITCondition() {
289     if (ITState.CurPosition == 1) {
290       ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
291     } else {
292       ITState.Mask ^= 1 << (5 - ITState.CurPosition);
293     }
294   }
295 
296   // Returns true if the current IT block is full (all 4 slots used).
297   bool isITBlockFull() {
298     return inITBlock() && (ITState.Mask & 1);
299   }
300 
301   // Extend the current implicit IT block to have one more slot with the given
302   // condition code.
303   void extendImplicitITBlock(ARMCC::CondCodes Cond) {
304     assert(inImplicitITBlock());
305     assert(!isITBlockFull());
306     assert(Cond == ITState.Cond ||
307            Cond == ARMCC::getOppositeCondition(ITState.Cond));
308     unsigned TZ = countTrailingZeros(ITState.Mask);
309     unsigned NewMask = 0;
310     // Keep any existing condition bits.
311     NewMask |= ITState.Mask & (0xE << TZ);
312     // Insert the new condition bit.
313     NewMask |= (Cond == ITState.Cond) << TZ;
314     // Move the trailing 1 down one bit.
315     NewMask |= 1 << (TZ - 1);
316     ITState.Mask = NewMask;
317   }
318 
319   // Create a new implicit IT block with a dummy condition code.
320   void startImplicitITBlock() {
321     assert(!inITBlock());
322     ITState.Cond = ARMCC::AL;
323     ITState.Mask = 8;
324     ITState.CurPosition = 1;
325     ITState.IsExplicit = false;
326     return;
327   }
328 
329   // Create a new explicit IT block with the given condition and mask. The mask
330   // should be in the parsed format, with a 1 implying 't', regardless of the
331   // low bit of the condition.
332   void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
333     assert(!inITBlock());
334     ITState.Cond = Cond;
335     ITState.Mask = Mask;
336     ITState.CurPosition = 0;
337     ITState.IsExplicit = true;
338     return;
339   }
340 
341   void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
342     return getParser().Note(L, Msg, Range);
343   }
344   bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
345     return getParser().Warning(L, Msg, Range);
346   }
347   bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
348     return getParser().Error(L, Msg, Range);
349   }
350 
351   bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
352                            unsigned ListNo, bool IsARPop = false);
353   bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
354                            unsigned ListNo);
355 
356   int tryParseRegister();
357   bool tryParseRegisterWithWriteBack(OperandVector &);
358   int tryParseShiftRegister(OperandVector &);
359   bool parseRegisterList(OperandVector &);
360   bool parseMemory(OperandVector &);
361   bool parseOperand(OperandVector &, StringRef Mnemonic);
362   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
363   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
364                               unsigned &ShiftAmount);
365   bool parseLiteralValues(unsigned Size, SMLoc L);
366   bool parseDirectiveThumb(SMLoc L);
367   bool parseDirectiveARM(SMLoc L);
368   bool parseDirectiveThumbFunc(SMLoc L);
369   bool parseDirectiveCode(SMLoc L);
370   bool parseDirectiveSyntax(SMLoc L);
371   bool parseDirectiveReq(StringRef Name, SMLoc L);
372   bool parseDirectiveUnreq(SMLoc L);
373   bool parseDirectiveArch(SMLoc L);
374   bool parseDirectiveEabiAttr(SMLoc L);
375   bool parseDirectiveCPU(SMLoc L);
376   bool parseDirectiveFPU(SMLoc L);
377   bool parseDirectiveFnStart(SMLoc L);
378   bool parseDirectiveFnEnd(SMLoc L);
379   bool parseDirectiveCantUnwind(SMLoc L);
380   bool parseDirectivePersonality(SMLoc L);
381   bool parseDirectiveHandlerData(SMLoc L);
382   bool parseDirectiveSetFP(SMLoc L);
383   bool parseDirectivePad(SMLoc L);
384   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
385   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
386   bool parseDirectiveLtorg(SMLoc L);
387   bool parseDirectiveEven(SMLoc L);
388   bool parseDirectivePersonalityIndex(SMLoc L);
389   bool parseDirectiveUnwindRaw(SMLoc L);
390   bool parseDirectiveTLSDescSeq(SMLoc L);
391   bool parseDirectiveMovSP(SMLoc L);
392   bool parseDirectiveObjectArch(SMLoc L);
393   bool parseDirectiveArchExtension(SMLoc L);
394   bool parseDirectiveAlign(SMLoc L);
395   bool parseDirectiveThumbSet(SMLoc L);
396 
397   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
398                           bool &CarrySetting, unsigned &ProcessorIMod,
399                           StringRef &ITMask);
400   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
401                              bool &CanAcceptCarrySet,
402                              bool &CanAcceptPredicationCode);
403 
404   void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
405                                      OperandVector &Operands);
406   bool isThumb() const {
407     // FIXME: Can tablegen auto-generate this?
408     return getSTI().getFeatureBits()[ARM::ModeThumb];
409   }
410   bool isThumbOne() const {
411     return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
412   }
413   bool isThumbTwo() const {
414     return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
415   }
416   bool hasThumb() const {
417     return getSTI().getFeatureBits()[ARM::HasV4TOps];
418   }
419   bool hasThumb2() const {
420     return getSTI().getFeatureBits()[ARM::FeatureThumb2];
421   }
422   bool hasV6Ops() const {
423     return getSTI().getFeatureBits()[ARM::HasV6Ops];
424   }
425   bool hasV6T2Ops() const {
426     return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
427   }
428   bool hasV6MOps() const {
429     return getSTI().getFeatureBits()[ARM::HasV6MOps];
430   }
431   bool hasV7Ops() const {
432     return getSTI().getFeatureBits()[ARM::HasV7Ops];
433   }
434   bool hasV8Ops() const {
435     return getSTI().getFeatureBits()[ARM::HasV8Ops];
436   }
437   bool hasV8MBaseline() const {
438     return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
439   }
440   bool hasV8MMainline() const {
441     return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
442   }
443   bool has8MSecExt() const {
444     return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
445   }
446   bool hasARM() const {
447     return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
448   }
449   bool hasDSP() const {
450     return getSTI().getFeatureBits()[ARM::FeatureDSP];
451   }
452   bool hasD16() const {
453     return getSTI().getFeatureBits()[ARM::FeatureD16];
454   }
455   bool hasV8_1aOps() const {
456     return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
457   }
458   bool hasRAS() const {
459     return getSTI().getFeatureBits()[ARM::FeatureRAS];
460   }
461 
462   void SwitchMode() {
463     MCSubtargetInfo &STI = copySTI();
464     uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
465     setAvailableFeatures(FB);
466   }
467   void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
468   bool isMClass() const {
469     return getSTI().getFeatureBits()[ARM::FeatureMClass];
470   }
471 
472   /// @name Auto-generated Match Functions
473   /// {
474 
475 #define GET_ASSEMBLER_HEADER
476 #include "ARMGenAsmMatcher.inc"
477 
478   /// }
479 
480   OperandMatchResultTy parseITCondCode(OperandVector &);
481   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
482   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
483   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
484   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
485   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
486   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
487   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
488   OperandMatchResultTy parseBankedRegOperand(OperandVector &);
489   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
490                                    int High);
491   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
492     return parsePKHImm(O, "lsl", 0, 31);
493   }
494   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
495     return parsePKHImm(O, "asr", 1, 32);
496   }
497   OperandMatchResultTy parseSetEndImm(OperandVector &);
498   OperandMatchResultTy parseShifterImm(OperandVector &);
499   OperandMatchResultTy parseRotImm(OperandVector &);
500   OperandMatchResultTy parseModImm(OperandVector &);
501   OperandMatchResultTy parseBitfield(OperandVector &);
502   OperandMatchResultTy parsePostIdxReg(OperandVector &);
503   OperandMatchResultTy parseAM3Offset(OperandVector &);
504   OperandMatchResultTy parseFPImm(OperandVector &);
505   OperandMatchResultTy parseVectorList(OperandVector &);
506   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
507                                        SMLoc &EndLoc);
508 
509   // Asm Match Converter Methods
510   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
511   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
512 
513   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
514   bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
515   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
516   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
517   bool isITBlockTerminator(MCInst &Inst) const;
518 
519 public:
520   enum ARMMatchResultTy {
521     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
522     Match_RequiresNotITBlock,
523     Match_RequiresV6,
524     Match_RequiresThumb2,
525     Match_RequiresV8,
526 #define GET_OPERAND_DIAGNOSTIC_TYPES
527 #include "ARMGenAsmMatcher.inc"
528 
529   };
530 
531   ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
532                const MCInstrInfo &MII, const MCTargetOptions &Options)
533     : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
534     MCAsmParserExtension::Initialize(Parser);
535 
536     // Cache the MCRegisterInfo.
537     MRI = getContext().getRegisterInfo();
538 
539     // Initialize the set of available features.
540     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
541 
542     // Not in an ITBlock to start with.
543     ITState.CurPosition = ~0U;
544 
545     NextSymbolIsThumb = false;
546   }
547 
548   // Implementation of the MCTargetAsmParser interface:
549   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
550   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
551                         SMLoc NameLoc, OperandVector &Operands) override;
552   bool ParseDirective(AsmToken DirectiveID) override;
553 
554   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
555                                       unsigned Kind) override;
556   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
557 
558   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
559                                OperandVector &Operands, MCStreamer &Out,
560                                uint64_t &ErrorInfo,
561                                bool MatchingInlineAsm) override;
562   unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
563                             uint64_t &ErrorInfo, bool MatchingInlineAsm,
564                             bool &EmitInITBlock, MCStreamer &Out);
565   void onLabelParsed(MCSymbol *Symbol) override;
566 };
567 } // end anonymous namespace
568 
569 namespace {
570 
571 /// ARMOperand - Instances of this class represent a parsed ARM machine
572 /// operand.
573 class ARMOperand : public MCParsedAsmOperand {
574   enum KindTy {
575     k_CondCode,
576     k_CCOut,
577     k_ITCondMask,
578     k_CoprocNum,
579     k_CoprocReg,
580     k_CoprocOption,
581     k_Immediate,
582     k_MemBarrierOpt,
583     k_InstSyncBarrierOpt,
584     k_Memory,
585     k_PostIndexRegister,
586     k_MSRMask,
587     k_BankedReg,
588     k_ProcIFlags,
589     k_VectorIndex,
590     k_Register,
591     k_RegisterList,
592     k_DPRRegisterList,
593     k_SPRRegisterList,
594     k_VectorList,
595     k_VectorListAllLanes,
596     k_VectorListIndexed,
597     k_ShiftedRegister,
598     k_ShiftedImmediate,
599     k_ShifterImmediate,
600     k_RotateImmediate,
601     k_ModifiedImmediate,
602     k_ConstantPoolImmediate,
603     k_BitfieldDescriptor,
604     k_Token,
605   } Kind;
606 
607   SMLoc StartLoc, EndLoc, AlignmentLoc;
608   SmallVector<unsigned, 8> Registers;
609 
610   struct CCOp {
611     ARMCC::CondCodes Val;
612   };
613 
614   struct CopOp {
615     unsigned Val;
616   };
617 
618   struct CoprocOptionOp {
619     unsigned Val;
620   };
621 
622   struct ITMaskOp {
623     unsigned Mask:4;
624   };
625 
626   struct MBOptOp {
627     ARM_MB::MemBOpt Val;
628   };
629 
630   struct ISBOptOp {
631     ARM_ISB::InstSyncBOpt Val;
632   };
633 
634   struct IFlagsOp {
635     ARM_PROC::IFlags Val;
636   };
637 
638   struct MMaskOp {
639     unsigned Val;
640   };
641 
642   struct BankedRegOp {
643     unsigned Val;
644   };
645 
646   struct TokOp {
647     const char *Data;
648     unsigned Length;
649   };
650 
651   struct RegOp {
652     unsigned RegNum;
653   };
654 
655   // A vector register list is a sequential list of 1 to 4 registers.
656   struct VectorListOp {
657     unsigned RegNum;
658     unsigned Count;
659     unsigned LaneIndex;
660     bool isDoubleSpaced;
661   };
662 
663   struct VectorIndexOp {
664     unsigned Val;
665   };
666 
667   struct ImmOp {
668     const MCExpr *Val;
669   };
670 
671   /// Combined record for all forms of ARM address expressions.
672   struct MemoryOp {
673     unsigned BaseRegNum;
674     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
675     // was specified.
676     const MCConstantExpr *OffsetImm;  // Offset immediate value
677     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
678     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
679     unsigned ShiftImm;        // shift for OffsetReg.
680     unsigned Alignment;       // 0 = no alignment specified
681     // n = alignment in bytes (2, 4, 8, 16, or 32)
682     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
683   };
684 
685   struct PostIdxRegOp {
686     unsigned RegNum;
687     bool isAdd;
688     ARM_AM::ShiftOpc ShiftTy;
689     unsigned ShiftImm;
690   };
691 
692   struct ShifterImmOp {
693     bool isASR;
694     unsigned Imm;
695   };
696 
697   struct RegShiftedRegOp {
698     ARM_AM::ShiftOpc ShiftTy;
699     unsigned SrcReg;
700     unsigned ShiftReg;
701     unsigned ShiftImm;
702   };
703 
704   struct RegShiftedImmOp {
705     ARM_AM::ShiftOpc ShiftTy;
706     unsigned SrcReg;
707     unsigned ShiftImm;
708   };
709 
710   struct RotImmOp {
711     unsigned Imm;
712   };
713 
714   struct ModImmOp {
715     unsigned Bits;
716     unsigned Rot;
717   };
718 
719   struct BitfieldOp {
720     unsigned LSB;
721     unsigned Width;
722   };
723 
724   union {
725     struct CCOp CC;
726     struct CopOp Cop;
727     struct CoprocOptionOp CoprocOption;
728     struct MBOptOp MBOpt;
729     struct ISBOptOp ISBOpt;
730     struct ITMaskOp ITMask;
731     struct IFlagsOp IFlags;
732     struct MMaskOp MMask;
733     struct BankedRegOp BankedReg;
734     struct TokOp Tok;
735     struct RegOp Reg;
736     struct VectorListOp VectorList;
737     struct VectorIndexOp VectorIndex;
738     struct ImmOp Imm;
739     struct MemoryOp Memory;
740     struct PostIdxRegOp PostIdxReg;
741     struct ShifterImmOp ShifterImm;
742     struct RegShiftedRegOp RegShiftedReg;
743     struct RegShiftedImmOp RegShiftedImm;
744     struct RotImmOp RotImm;
745     struct ModImmOp ModImm;
746     struct BitfieldOp Bitfield;
747   };
748 
749 public:
750   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
751 
752   /// getStartLoc - Get the location of the first token of this operand.
753   SMLoc getStartLoc() const override { return StartLoc; }
754   /// getEndLoc - Get the location of the last token of this operand.
755   SMLoc getEndLoc() const override { return EndLoc; }
756   /// getLocRange - Get the range between the first and last token of this
757   /// operand.
758   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
759 
760   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
761   SMLoc getAlignmentLoc() const {
762     assert(Kind == k_Memory && "Invalid access!");
763     return AlignmentLoc;
764   }
765 
766   ARMCC::CondCodes getCondCode() const {
767     assert(Kind == k_CondCode && "Invalid access!");
768     return CC.Val;
769   }
770 
771   unsigned getCoproc() const {
772     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
773     return Cop.Val;
774   }
775 
776   StringRef getToken() const {
777     assert(Kind == k_Token && "Invalid access!");
778     return StringRef(Tok.Data, Tok.Length);
779   }
780 
781   unsigned getReg() const override {
782     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
783     return Reg.RegNum;
784   }
785 
786   const SmallVectorImpl<unsigned> &getRegList() const {
787     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
788             Kind == k_SPRRegisterList) && "Invalid access!");
789     return Registers;
790   }
791 
792   const MCExpr *getImm() const {
793     assert(isImm() && "Invalid access!");
794     return Imm.Val;
795   }
796 
797   const MCExpr *getConstantPoolImm() const {
798     assert(isConstantPoolImm() && "Invalid access!");
799     return Imm.Val;
800   }
801 
802   unsigned getVectorIndex() const {
803     assert(Kind == k_VectorIndex && "Invalid access!");
804     return VectorIndex.Val;
805   }
806 
807   ARM_MB::MemBOpt getMemBarrierOpt() const {
808     assert(Kind == k_MemBarrierOpt && "Invalid access!");
809     return MBOpt.Val;
810   }
811 
812   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
813     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
814     return ISBOpt.Val;
815   }
816 
817   ARM_PROC::IFlags getProcIFlags() const {
818     assert(Kind == k_ProcIFlags && "Invalid access!");
819     return IFlags.Val;
820   }
821 
822   unsigned getMSRMask() const {
823     assert(Kind == k_MSRMask && "Invalid access!");
824     return MMask.Val;
825   }
826 
827   unsigned getBankedReg() const {
828     assert(Kind == k_BankedReg && "Invalid access!");
829     return BankedReg.Val;
830   }
831 
832   bool isCoprocNum() const { return Kind == k_CoprocNum; }
833   bool isCoprocReg() const { return Kind == k_CoprocReg; }
834   bool isCoprocOption() const { return Kind == k_CoprocOption; }
835   bool isCondCode() const { return Kind == k_CondCode; }
836   bool isCCOut() const { return Kind == k_CCOut; }
837   bool isITMask() const { return Kind == k_ITCondMask; }
838   bool isITCondCode() const { return Kind == k_CondCode; }
839   bool isImm() const override {
840     return Kind == k_Immediate;
841   }
842 
843   bool isARMBranchTarget() const {
844     if (!isImm()) return false;
845 
846     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
847       return CE->getValue() % 4 == 0;
848     return true;
849   }
850 
851 
852   bool isThumbBranchTarget() const {
853     if (!isImm()) return false;
854 
855     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
856       return CE->getValue() % 2 == 0;
857     return true;
858   }
859 
860   // checks whether this operand is an unsigned offset which fits is a field
861   // of specified width and scaled by a specific number of bits
862   template<unsigned width, unsigned scale>
863   bool isUnsignedOffset() const {
864     if (!isImm()) return false;
865     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
866     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
867       int64_t Val = CE->getValue();
868       int64_t Align = 1LL << scale;
869       int64_t Max = Align * ((1LL << width) - 1);
870       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
871     }
872     return false;
873   }
874   // checks whether this operand is an signed offset which fits is a field
875   // of specified width and scaled by a specific number of bits
876   template<unsigned width, unsigned scale>
877   bool isSignedOffset() const {
878     if (!isImm()) return false;
879     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
880     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
881       int64_t Val = CE->getValue();
882       int64_t Align = 1LL << scale;
883       int64_t Max = Align * ((1LL << (width-1)) - 1);
884       int64_t Min = -Align * (1LL << (width-1));
885       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
886     }
887     return false;
888   }
889 
890   // checks whether this operand is a memory operand computed as an offset
891   // applied to PC. the offset may have 8 bits of magnitude and is represented
892   // with two bits of shift. textually it may be either [pc, #imm], #imm or
893   // relocable expression...
894   bool isThumbMemPC() const {
895     int64_t Val = 0;
896     if (isImm()) {
897       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
898       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
899       if (!CE) return false;
900       Val = CE->getValue();
901     }
902     else if (isMem()) {
903       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
904       if(Memory.BaseRegNum != ARM::PC) return false;
905       Val = Memory.OffsetImm->getValue();
906     }
907     else return false;
908     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
909   }
910   bool isFPImm() const {
911     if (!isImm()) return false;
912     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913     if (!CE) return false;
914     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
915     return Val != -1;
916   }
917   bool isFBits16() const {
918     if (!isImm()) return false;
919     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
920     if (!CE) return false;
921     int64_t Value = CE->getValue();
922     return Value >= 0 && Value <= 16;
923   }
924   bool isFBits32() const {
925     if (!isImm()) return false;
926     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927     if (!CE) return false;
928     int64_t Value = CE->getValue();
929     return Value >= 1 && Value <= 32;
930   }
931   bool isImm8s4() const {
932     if (!isImm()) return false;
933     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934     if (!CE) return false;
935     int64_t Value = CE->getValue();
936     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
937   }
938   bool isImm0_1020s4() const {
939     if (!isImm()) return false;
940     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941     if (!CE) return false;
942     int64_t Value = CE->getValue();
943     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
944   }
945   bool isImm0_508s4() const {
946     if (!isImm()) return false;
947     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948     if (!CE) return false;
949     int64_t Value = CE->getValue();
950     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
951   }
952   bool isImm0_508s4Neg() const {
953     if (!isImm()) return false;
954     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955     if (!CE) return false;
956     int64_t Value = -CE->getValue();
957     // explicitly exclude zero. we want that to use the normal 0_508 version.
958     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
959   }
960   bool isImm0_239() const {
961     if (!isImm()) return false;
962     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
963     if (!CE) return false;
964     int64_t Value = CE->getValue();
965     return Value >= 0 && Value < 240;
966   }
967   bool isImm0_255() const {
968     if (!isImm()) return false;
969     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
970     if (!CE) return false;
971     int64_t Value = CE->getValue();
972     return Value >= 0 && Value < 256;
973   }
974   bool isImm0_4095() const {
975     if (!isImm()) return false;
976     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
977     if (!CE) return false;
978     int64_t Value = CE->getValue();
979     return Value >= 0 && Value < 4096;
980   }
981   bool isImm0_4095Neg() const {
982     if (!isImm()) return false;
983     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984     if (!CE) return false;
985     int64_t Value = -CE->getValue();
986     return Value > 0 && Value < 4096;
987   }
988   bool isImm0_1() const {
989     if (!isImm()) return false;
990     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
991     if (!CE) return false;
992     int64_t Value = CE->getValue();
993     return Value >= 0 && Value < 2;
994   }
995   bool isImm0_3() const {
996     if (!isImm()) return false;
997     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
998     if (!CE) return false;
999     int64_t Value = CE->getValue();
1000     return Value >= 0 && Value < 4;
1001   }
1002   bool isImm0_7() const {
1003     if (!isImm()) return false;
1004     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1005     if (!CE) return false;
1006     int64_t Value = CE->getValue();
1007     return Value >= 0 && Value < 8;
1008   }
1009   bool isImm0_15() const {
1010     if (!isImm()) return false;
1011     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1012     if (!CE) return false;
1013     int64_t Value = CE->getValue();
1014     return Value >= 0 && Value < 16;
1015   }
1016   bool isImm0_31() const {
1017     if (!isImm()) return false;
1018     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1019     if (!CE) return false;
1020     int64_t Value = CE->getValue();
1021     return Value >= 0 && Value < 32;
1022   }
1023   bool isImm0_63() const {
1024     if (!isImm()) return false;
1025     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1026     if (!CE) return false;
1027     int64_t Value = CE->getValue();
1028     return Value >= 0 && Value < 64;
1029   }
1030   bool isImm8() const {
1031     if (!isImm()) return false;
1032     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1033     if (!CE) return false;
1034     int64_t Value = CE->getValue();
1035     return Value == 8;
1036   }
1037   bool isImm16() const {
1038     if (!isImm()) return false;
1039     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1040     if (!CE) return false;
1041     int64_t Value = CE->getValue();
1042     return Value == 16;
1043   }
1044   bool isImm32() const {
1045     if (!isImm()) return false;
1046     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1047     if (!CE) return false;
1048     int64_t Value = CE->getValue();
1049     return Value == 32;
1050   }
1051   bool isShrImm8() const {
1052     if (!isImm()) return false;
1053     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1054     if (!CE) return false;
1055     int64_t Value = CE->getValue();
1056     return Value > 0 && Value <= 8;
1057   }
1058   bool isShrImm16() const {
1059     if (!isImm()) return false;
1060     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1061     if (!CE) return false;
1062     int64_t Value = CE->getValue();
1063     return Value > 0 && Value <= 16;
1064   }
1065   bool isShrImm32() const {
1066     if (!isImm()) return false;
1067     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1068     if (!CE) return false;
1069     int64_t Value = CE->getValue();
1070     return Value > 0 && Value <= 32;
1071   }
1072   bool isShrImm64() const {
1073     if (!isImm()) return false;
1074     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1075     if (!CE) return false;
1076     int64_t Value = CE->getValue();
1077     return Value > 0 && Value <= 64;
1078   }
1079   bool isImm1_7() const {
1080     if (!isImm()) return false;
1081     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1082     if (!CE) return false;
1083     int64_t Value = CE->getValue();
1084     return Value > 0 && Value < 8;
1085   }
1086   bool isImm1_15() const {
1087     if (!isImm()) return false;
1088     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1089     if (!CE) return false;
1090     int64_t Value = CE->getValue();
1091     return Value > 0 && Value < 16;
1092   }
1093   bool isImm1_31() const {
1094     if (!isImm()) return false;
1095     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1096     if (!CE) return false;
1097     int64_t Value = CE->getValue();
1098     return Value > 0 && Value < 32;
1099   }
1100   bool isImm1_16() const {
1101     if (!isImm()) return false;
1102     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1103     if (!CE) return false;
1104     int64_t Value = CE->getValue();
1105     return Value > 0 && Value < 17;
1106   }
1107   bool isImm1_32() const {
1108     if (!isImm()) return false;
1109     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1110     if (!CE) return false;
1111     int64_t Value = CE->getValue();
1112     return Value > 0 && Value < 33;
1113   }
1114   bool isImm0_32() const {
1115     if (!isImm()) return false;
1116     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1117     if (!CE) return false;
1118     int64_t Value = CE->getValue();
1119     return Value >= 0 && Value < 33;
1120   }
1121   bool isImm0_65535() const {
1122     if (!isImm()) return false;
1123     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1124     if (!CE) return false;
1125     int64_t Value = CE->getValue();
1126     return Value >= 0 && Value < 65536;
1127   }
1128   bool isImm256_65535Expr() const {
1129     if (!isImm()) return false;
1130     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1131     // If it's not a constant expression, it'll generate a fixup and be
1132     // handled later.
1133     if (!CE) return true;
1134     int64_t Value = CE->getValue();
1135     return Value >= 256 && Value < 65536;
1136   }
1137   bool isImm0_65535Expr() const {
1138     if (!isImm()) return false;
1139     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1140     // If it's not a constant expression, it'll generate a fixup and be
1141     // handled later.
1142     if (!CE) return true;
1143     int64_t Value = CE->getValue();
1144     return Value >= 0 && Value < 65536;
1145   }
1146   bool isImm24bit() const {
1147     if (!isImm()) return false;
1148     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1149     if (!CE) return false;
1150     int64_t Value = CE->getValue();
1151     return Value >= 0 && Value <= 0xffffff;
1152   }
1153   bool isImmThumbSR() const {
1154     if (!isImm()) return false;
1155     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1156     if (!CE) return false;
1157     int64_t Value = CE->getValue();
1158     return Value > 0 && Value < 33;
1159   }
1160   bool isPKHLSLImm() const {
1161     if (!isImm()) return false;
1162     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1163     if (!CE) return false;
1164     int64_t Value = CE->getValue();
1165     return Value >= 0 && Value < 32;
1166   }
1167   bool isPKHASRImm() const {
1168     if (!isImm()) return false;
1169     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1170     if (!CE) return false;
1171     int64_t Value = CE->getValue();
1172     return Value > 0 && Value <= 32;
1173   }
1174   bool isAdrLabel() const {
1175     // If we have an immediate that's not a constant, treat it as a label
1176     // reference needing a fixup.
1177     if (isImm() && !isa<MCConstantExpr>(getImm()))
1178       return true;
1179 
1180     // If it is a constant, it must fit into a modified immediate encoding.
1181     if (!isImm()) return false;
1182     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1183     if (!CE) return false;
1184     int64_t Value = CE->getValue();
1185     return (ARM_AM::getSOImmVal(Value) != -1 ||
1186             ARM_AM::getSOImmVal(-Value) != -1);
1187   }
1188   bool isT2SOImm() const {
1189     if (!isImm()) return false;
1190     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1191     if (!CE) return false;
1192     int64_t Value = CE->getValue();
1193     return ARM_AM::getT2SOImmVal(Value) != -1;
1194   }
1195   bool isT2SOImmNot() const {
1196     if (!isImm()) return false;
1197     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1198     if (!CE) return false;
1199     int64_t Value = CE->getValue();
1200     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1201       ARM_AM::getT2SOImmVal(~Value) != -1;
1202   }
1203   bool isT2SOImmNeg() const {
1204     if (!isImm()) return false;
1205     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1206     if (!CE) return false;
1207     int64_t Value = CE->getValue();
1208     // Only use this when not representable as a plain so_imm.
1209     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1210       ARM_AM::getT2SOImmVal(-Value) != -1;
1211   }
1212   bool isSetEndImm() const {
1213     if (!isImm()) return false;
1214     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1215     if (!CE) return false;
1216     int64_t Value = CE->getValue();
1217     return Value == 1 || Value == 0;
1218   }
1219   bool isReg() const override { return Kind == k_Register; }
1220   bool isRegList() const { return Kind == k_RegisterList; }
1221   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1222   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1223   bool isToken() const override { return Kind == k_Token; }
1224   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1225   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1226   bool isMem() const override { return Kind == k_Memory; }
1227   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1228   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1229   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1230   bool isRotImm() const { return Kind == k_RotateImmediate; }
1231   bool isModImm() const { return Kind == k_ModifiedImmediate; }
1232   bool isModImmNot() const {
1233     if (!isImm()) return false;
1234     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1235     if (!CE) return false;
1236     int64_t Value = CE->getValue();
1237     return ARM_AM::getSOImmVal(~Value) != -1;
1238   }
1239   bool isModImmNeg() const {
1240     if (!isImm()) return false;
1241     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1242     if (!CE) return false;
1243     int64_t Value = CE->getValue();
1244     return ARM_AM::getSOImmVal(Value) == -1 &&
1245       ARM_AM::getSOImmVal(-Value) != -1;
1246   }
1247   bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1248   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1249   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1250   bool isPostIdxReg() const {
1251     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1252   }
1253   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1254     if (!isMem())
1255       return false;
1256     // No offset of any kind.
1257     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1258      (alignOK || Memory.Alignment == Alignment);
1259   }
1260   bool isMemPCRelImm12() const {
1261     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1262       return false;
1263     // Base register must be PC.
1264     if (Memory.BaseRegNum != ARM::PC)
1265       return false;
1266     // Immediate offset in range [-4095, 4095].
1267     if (!Memory.OffsetImm) return true;
1268     int64_t Val = Memory.OffsetImm->getValue();
1269     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1270   }
1271   bool isAlignedMemory() const {
1272     return isMemNoOffset(true);
1273   }
1274   bool isAlignedMemoryNone() const {
1275     return isMemNoOffset(false, 0);
1276   }
1277   bool isDupAlignedMemoryNone() const {
1278     return isMemNoOffset(false, 0);
1279   }
1280   bool isAlignedMemory16() const {
1281     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1282       return true;
1283     return isMemNoOffset(false, 0);
1284   }
1285   bool isDupAlignedMemory16() const {
1286     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1287       return true;
1288     return isMemNoOffset(false, 0);
1289   }
1290   bool isAlignedMemory32() const {
1291     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1292       return true;
1293     return isMemNoOffset(false, 0);
1294   }
1295   bool isDupAlignedMemory32() const {
1296     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1297       return true;
1298     return isMemNoOffset(false, 0);
1299   }
1300   bool isAlignedMemory64() const {
1301     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1302       return true;
1303     return isMemNoOffset(false, 0);
1304   }
1305   bool isDupAlignedMemory64() const {
1306     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1307       return true;
1308     return isMemNoOffset(false, 0);
1309   }
1310   bool isAlignedMemory64or128() const {
1311     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1312       return true;
1313     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1314       return true;
1315     return isMemNoOffset(false, 0);
1316   }
1317   bool isDupAlignedMemory64or128() const {
1318     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1319       return true;
1320     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1321       return true;
1322     return isMemNoOffset(false, 0);
1323   }
1324   bool isAlignedMemory64or128or256() const {
1325     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1326       return true;
1327     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1328       return true;
1329     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1330       return true;
1331     return isMemNoOffset(false, 0);
1332   }
1333   bool isAddrMode2() const {
1334     if (!isMem() || Memory.Alignment != 0) return false;
1335     // Check for register offset.
1336     if (Memory.OffsetRegNum) return true;
1337     // Immediate offset in range [-4095, 4095].
1338     if (!Memory.OffsetImm) return true;
1339     int64_t Val = Memory.OffsetImm->getValue();
1340     return Val > -4096 && Val < 4096;
1341   }
1342   bool isAM2OffsetImm() const {
1343     if (!isImm()) return false;
1344     // Immediate offset in range [-4095, 4095].
1345     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1346     if (!CE) return false;
1347     int64_t Val = CE->getValue();
1348     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1349   }
1350   bool isAddrMode3() const {
1351     // If we have an immediate that's not a constant, treat it as a label
1352     // reference needing a fixup. If it is a constant, it's something else
1353     // and we reject it.
1354     if (isImm() && !isa<MCConstantExpr>(getImm()))
1355       return true;
1356     if (!isMem() || Memory.Alignment != 0) return false;
1357     // No shifts are legal for AM3.
1358     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1359     // Check for register offset.
1360     if (Memory.OffsetRegNum) return true;
1361     // Immediate offset in range [-255, 255].
1362     if (!Memory.OffsetImm) return true;
1363     int64_t Val = Memory.OffsetImm->getValue();
1364     // The #-0 offset is encoded as INT32_MIN, and we have to check
1365     // for this too.
1366     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1367   }
1368   bool isAM3Offset() const {
1369     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1370       return false;
1371     if (Kind == k_PostIndexRegister)
1372       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1373     // Immediate offset in range [-255, 255].
1374     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1375     if (!CE) return false;
1376     int64_t Val = CE->getValue();
1377     // Special case, #-0 is INT32_MIN.
1378     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1379   }
1380   bool isAddrMode5() const {
1381     // If we have an immediate that's not a constant, treat it as a label
1382     // reference needing a fixup. If it is a constant, it's something else
1383     // and we reject it.
1384     if (isImm() && !isa<MCConstantExpr>(getImm()))
1385       return true;
1386     if (!isMem() || Memory.Alignment != 0) return false;
1387     // Check for register offset.
1388     if (Memory.OffsetRegNum) return false;
1389     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1390     if (!Memory.OffsetImm) return true;
1391     int64_t Val = Memory.OffsetImm->getValue();
1392     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1393       Val == INT32_MIN;
1394   }
1395   bool isAddrMode5FP16() const {
1396     // If we have an immediate that's not a constant, treat it as a label
1397     // reference needing a fixup. If it is a constant, it's something else
1398     // and we reject it.
1399     if (isImm() && !isa<MCConstantExpr>(getImm()))
1400       return true;
1401     if (!isMem() || Memory.Alignment != 0) return false;
1402     // Check for register offset.
1403     if (Memory.OffsetRegNum) return false;
1404     // Immediate offset in range [-510, 510] and a multiple of 2.
1405     if (!Memory.OffsetImm) return true;
1406     int64_t Val = Memory.OffsetImm->getValue();
1407     return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == INT32_MIN;
1408   }
1409   bool isMemTBB() const {
1410     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1411         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1412       return false;
1413     return true;
1414   }
1415   bool isMemTBH() const {
1416     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1417         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1418         Memory.Alignment != 0 )
1419       return false;
1420     return true;
1421   }
1422   bool isMemRegOffset() const {
1423     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1424       return false;
1425     return true;
1426   }
1427   bool isT2MemRegOffset() const {
1428     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1429         Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1430       return false;
1431     // Only lsl #{0, 1, 2, 3} allowed.
1432     if (Memory.ShiftType == ARM_AM::no_shift)
1433       return true;
1434     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1435       return false;
1436     return true;
1437   }
1438   bool isMemThumbRR() const {
1439     // Thumb reg+reg addressing is simple. Just two registers, a base and
1440     // an offset. No shifts, negations or any other complicating factors.
1441     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1442         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1443       return false;
1444     return isARMLowRegister(Memory.BaseRegNum) &&
1445       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1446   }
1447   bool isMemThumbRIs4() const {
1448     if (!isMem() || Memory.OffsetRegNum != 0 ||
1449         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1450       return false;
1451     // Immediate offset, multiple of 4 in range [0, 124].
1452     if (!Memory.OffsetImm) return true;
1453     int64_t Val = Memory.OffsetImm->getValue();
1454     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1455   }
1456   bool isMemThumbRIs2() const {
1457     if (!isMem() || Memory.OffsetRegNum != 0 ||
1458         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1459       return false;
1460     // Immediate offset, multiple of 4 in range [0, 62].
1461     if (!Memory.OffsetImm) return true;
1462     int64_t Val = Memory.OffsetImm->getValue();
1463     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1464   }
1465   bool isMemThumbRIs1() const {
1466     if (!isMem() || Memory.OffsetRegNum != 0 ||
1467         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1468       return false;
1469     // Immediate offset in range [0, 31].
1470     if (!Memory.OffsetImm) return true;
1471     int64_t Val = Memory.OffsetImm->getValue();
1472     return Val >= 0 && Val <= 31;
1473   }
1474   bool isMemThumbSPI() const {
1475     if (!isMem() || Memory.OffsetRegNum != 0 ||
1476         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1477       return false;
1478     // Immediate offset, multiple of 4 in range [0, 1020].
1479     if (!Memory.OffsetImm) return true;
1480     int64_t Val = Memory.OffsetImm->getValue();
1481     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1482   }
1483   bool isMemImm8s4Offset() const {
1484     // If we have an immediate that's not a constant, treat it as a label
1485     // reference needing a fixup. If it is a constant, it's something else
1486     // and we reject it.
1487     if (isImm() && !isa<MCConstantExpr>(getImm()))
1488       return true;
1489     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1490       return false;
1491     // Immediate offset a multiple of 4 in range [-1020, 1020].
1492     if (!Memory.OffsetImm) return true;
1493     int64_t Val = Memory.OffsetImm->getValue();
1494     // Special case, #-0 is INT32_MIN.
1495     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1496   }
1497   bool isMemImm0_1020s4Offset() const {
1498     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1499       return false;
1500     // Immediate offset a multiple of 4 in range [0, 1020].
1501     if (!Memory.OffsetImm) return true;
1502     int64_t Val = Memory.OffsetImm->getValue();
1503     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1504   }
1505   bool isMemImm8Offset() const {
1506     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1507       return false;
1508     // Base reg of PC isn't allowed for these encodings.
1509     if (Memory.BaseRegNum == ARM::PC) return false;
1510     // Immediate offset in range [-255, 255].
1511     if (!Memory.OffsetImm) return true;
1512     int64_t Val = Memory.OffsetImm->getValue();
1513     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1514   }
1515   bool isMemPosImm8Offset() const {
1516     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1517       return false;
1518     // Immediate offset in range [0, 255].
1519     if (!Memory.OffsetImm) return true;
1520     int64_t Val = Memory.OffsetImm->getValue();
1521     return Val >= 0 && Val < 256;
1522   }
1523   bool isMemNegImm8Offset() const {
1524     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1525       return false;
1526     // Base reg of PC isn't allowed for these encodings.
1527     if (Memory.BaseRegNum == ARM::PC) return false;
1528     // Immediate offset in range [-255, -1].
1529     if (!Memory.OffsetImm) return false;
1530     int64_t Val = Memory.OffsetImm->getValue();
1531     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1532   }
1533   bool isMemUImm12Offset() const {
1534     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1535       return false;
1536     // Immediate offset in range [0, 4095].
1537     if (!Memory.OffsetImm) return true;
1538     int64_t Val = Memory.OffsetImm->getValue();
1539     return (Val >= 0 && Val < 4096);
1540   }
1541   bool isMemImm12Offset() const {
1542     // If we have an immediate that's not a constant, treat it as a label
1543     // reference needing a fixup. If it is a constant, it's something else
1544     // and we reject it.
1545 
1546     if (isImm() && !isa<MCConstantExpr>(getImm()))
1547       return true;
1548 
1549     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1550       return false;
1551     // Immediate offset in range [-4095, 4095].
1552     if (!Memory.OffsetImm) return true;
1553     int64_t Val = Memory.OffsetImm->getValue();
1554     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1555   }
1556   bool isConstPoolAsmImm() const {
1557     // Delay processing of Constant Pool Immediate, this will turn into
1558     // a constant. Match no other operand
1559     return (isConstantPoolImm());
1560   }
1561   bool isPostIdxImm8() const {
1562     if (!isImm()) return false;
1563     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1564     if (!CE) return false;
1565     int64_t Val = CE->getValue();
1566     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1567   }
1568   bool isPostIdxImm8s4() const {
1569     if (!isImm()) return false;
1570     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1571     if (!CE) return false;
1572     int64_t Val = CE->getValue();
1573     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1574       (Val == INT32_MIN);
1575   }
1576 
1577   bool isMSRMask() const { return Kind == k_MSRMask; }
1578   bool isBankedReg() const { return Kind == k_BankedReg; }
1579   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1580 
1581   // NEON operands.
1582   bool isSingleSpacedVectorList() const {
1583     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1584   }
1585   bool isDoubleSpacedVectorList() const {
1586     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1587   }
1588   bool isVecListOneD() const {
1589     if (!isSingleSpacedVectorList()) return false;
1590     return VectorList.Count == 1;
1591   }
1592 
1593   bool isVecListDPair() const {
1594     if (!isSingleSpacedVectorList()) return false;
1595     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1596               .contains(VectorList.RegNum));
1597   }
1598 
1599   bool isVecListThreeD() const {
1600     if (!isSingleSpacedVectorList()) return false;
1601     return VectorList.Count == 3;
1602   }
1603 
1604   bool isVecListFourD() const {
1605     if (!isSingleSpacedVectorList()) return false;
1606     return VectorList.Count == 4;
1607   }
1608 
1609   bool isVecListDPairSpaced() const {
1610     if (Kind != k_VectorList) return false;
1611     if (isSingleSpacedVectorList()) return false;
1612     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1613               .contains(VectorList.RegNum));
1614   }
1615 
1616   bool isVecListThreeQ() const {
1617     if (!isDoubleSpacedVectorList()) return false;
1618     return VectorList.Count == 3;
1619   }
1620 
1621   bool isVecListFourQ() const {
1622     if (!isDoubleSpacedVectorList()) return false;
1623     return VectorList.Count == 4;
1624   }
1625 
1626   bool isSingleSpacedVectorAllLanes() const {
1627     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1628   }
1629   bool isDoubleSpacedVectorAllLanes() const {
1630     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1631   }
1632   bool isVecListOneDAllLanes() const {
1633     if (!isSingleSpacedVectorAllLanes()) return false;
1634     return VectorList.Count == 1;
1635   }
1636 
1637   bool isVecListDPairAllLanes() const {
1638     if (!isSingleSpacedVectorAllLanes()) return false;
1639     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1640               .contains(VectorList.RegNum));
1641   }
1642 
1643   bool isVecListDPairSpacedAllLanes() const {
1644     if (!isDoubleSpacedVectorAllLanes()) return false;
1645     return VectorList.Count == 2;
1646   }
1647 
1648   bool isVecListThreeDAllLanes() const {
1649     if (!isSingleSpacedVectorAllLanes()) return false;
1650     return VectorList.Count == 3;
1651   }
1652 
1653   bool isVecListThreeQAllLanes() const {
1654     if (!isDoubleSpacedVectorAllLanes()) return false;
1655     return VectorList.Count == 3;
1656   }
1657 
1658   bool isVecListFourDAllLanes() const {
1659     if (!isSingleSpacedVectorAllLanes()) return false;
1660     return VectorList.Count == 4;
1661   }
1662 
1663   bool isVecListFourQAllLanes() const {
1664     if (!isDoubleSpacedVectorAllLanes()) return false;
1665     return VectorList.Count == 4;
1666   }
1667 
1668   bool isSingleSpacedVectorIndexed() const {
1669     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1670   }
1671   bool isDoubleSpacedVectorIndexed() const {
1672     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1673   }
1674   bool isVecListOneDByteIndexed() const {
1675     if (!isSingleSpacedVectorIndexed()) return false;
1676     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1677   }
1678 
1679   bool isVecListOneDHWordIndexed() const {
1680     if (!isSingleSpacedVectorIndexed()) return false;
1681     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1682   }
1683 
1684   bool isVecListOneDWordIndexed() const {
1685     if (!isSingleSpacedVectorIndexed()) return false;
1686     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1687   }
1688 
1689   bool isVecListTwoDByteIndexed() const {
1690     if (!isSingleSpacedVectorIndexed()) return false;
1691     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1692   }
1693 
1694   bool isVecListTwoDHWordIndexed() const {
1695     if (!isSingleSpacedVectorIndexed()) return false;
1696     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1697   }
1698 
1699   bool isVecListTwoQWordIndexed() const {
1700     if (!isDoubleSpacedVectorIndexed()) return false;
1701     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1702   }
1703 
1704   bool isVecListTwoQHWordIndexed() const {
1705     if (!isDoubleSpacedVectorIndexed()) return false;
1706     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1707   }
1708 
1709   bool isVecListTwoDWordIndexed() const {
1710     if (!isSingleSpacedVectorIndexed()) return false;
1711     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1712   }
1713 
1714   bool isVecListThreeDByteIndexed() const {
1715     if (!isSingleSpacedVectorIndexed()) return false;
1716     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1717   }
1718 
1719   bool isVecListThreeDHWordIndexed() const {
1720     if (!isSingleSpacedVectorIndexed()) return false;
1721     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1722   }
1723 
1724   bool isVecListThreeQWordIndexed() const {
1725     if (!isDoubleSpacedVectorIndexed()) return false;
1726     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1727   }
1728 
1729   bool isVecListThreeQHWordIndexed() const {
1730     if (!isDoubleSpacedVectorIndexed()) return false;
1731     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1732   }
1733 
1734   bool isVecListThreeDWordIndexed() const {
1735     if (!isSingleSpacedVectorIndexed()) return false;
1736     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1737   }
1738 
1739   bool isVecListFourDByteIndexed() const {
1740     if (!isSingleSpacedVectorIndexed()) return false;
1741     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1742   }
1743 
1744   bool isVecListFourDHWordIndexed() const {
1745     if (!isSingleSpacedVectorIndexed()) return false;
1746     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1747   }
1748 
1749   bool isVecListFourQWordIndexed() const {
1750     if (!isDoubleSpacedVectorIndexed()) return false;
1751     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1752   }
1753 
1754   bool isVecListFourQHWordIndexed() const {
1755     if (!isDoubleSpacedVectorIndexed()) return false;
1756     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1757   }
1758 
1759   bool isVecListFourDWordIndexed() const {
1760     if (!isSingleSpacedVectorIndexed()) return false;
1761     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1762   }
1763 
1764   bool isVectorIndex8() const {
1765     if (Kind != k_VectorIndex) return false;
1766     return VectorIndex.Val < 8;
1767   }
1768   bool isVectorIndex16() const {
1769     if (Kind != k_VectorIndex) return false;
1770     return VectorIndex.Val < 4;
1771   }
1772   bool isVectorIndex32() const {
1773     if (Kind != k_VectorIndex) return false;
1774     return VectorIndex.Val < 2;
1775   }
1776 
1777   bool isNEONi8splat() const {
1778     if (!isImm()) return false;
1779     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1780     // Must be a constant.
1781     if (!CE) return false;
1782     int64_t Value = CE->getValue();
1783     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1784     // value.
1785     return Value >= 0 && Value < 256;
1786   }
1787 
1788   bool isNEONi16splat() const {
1789     if (isNEONByteReplicate(2))
1790       return false; // Leave that for bytes replication and forbid by default.
1791     if (!isImm())
1792       return false;
1793     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1794     // Must be a constant.
1795     if (!CE) return false;
1796     unsigned Value = CE->getValue();
1797     return ARM_AM::isNEONi16splat(Value);
1798   }
1799 
1800   bool isNEONi16splatNot() const {
1801     if (!isImm())
1802       return false;
1803     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1804     // Must be a constant.
1805     if (!CE) return false;
1806     unsigned Value = CE->getValue();
1807     return ARM_AM::isNEONi16splat(~Value & 0xffff);
1808   }
1809 
1810   bool isNEONi32splat() const {
1811     if (isNEONByteReplicate(4))
1812       return false; // Leave that for bytes replication and forbid by default.
1813     if (!isImm())
1814       return false;
1815     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1816     // Must be a constant.
1817     if (!CE) return false;
1818     unsigned Value = CE->getValue();
1819     return ARM_AM::isNEONi32splat(Value);
1820   }
1821 
1822   bool isNEONi32splatNot() const {
1823     if (!isImm())
1824       return false;
1825     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1826     // Must be a constant.
1827     if (!CE) return false;
1828     unsigned Value = CE->getValue();
1829     return ARM_AM::isNEONi32splat(~Value);
1830   }
1831 
1832   bool isNEONByteReplicate(unsigned NumBytes) const {
1833     if (!isImm())
1834       return false;
1835     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1836     // Must be a constant.
1837     if (!CE)
1838       return false;
1839     int64_t Value = CE->getValue();
1840     if (!Value)
1841       return false; // Don't bother with zero.
1842 
1843     unsigned char B = Value & 0xff;
1844     for (unsigned i = 1; i < NumBytes; ++i) {
1845       Value >>= 8;
1846       if ((Value & 0xff) != B)
1847         return false;
1848     }
1849     return true;
1850   }
1851   bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1852   bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1853   bool isNEONi32vmov() const {
1854     if (isNEONByteReplicate(4))
1855       return false; // Let it to be classified as byte-replicate case.
1856     if (!isImm())
1857       return false;
1858     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1859     // Must be a constant.
1860     if (!CE)
1861       return false;
1862     int64_t Value = CE->getValue();
1863     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1864     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1865     // FIXME: This is probably wrong and a copy and paste from previous example
1866     return (Value >= 0 && Value < 256) ||
1867       (Value >= 0x0100 && Value <= 0xff00) ||
1868       (Value >= 0x010000 && Value <= 0xff0000) ||
1869       (Value >= 0x01000000 && Value <= 0xff000000) ||
1870       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1871       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1872   }
1873   bool isNEONi32vmovNeg() const {
1874     if (!isImm()) return false;
1875     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1876     // Must be a constant.
1877     if (!CE) return false;
1878     int64_t Value = ~CE->getValue();
1879     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1880     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1881     // FIXME: This is probably wrong and a copy and paste from previous example
1882     return (Value >= 0 && Value < 256) ||
1883       (Value >= 0x0100 && Value <= 0xff00) ||
1884       (Value >= 0x010000 && Value <= 0xff0000) ||
1885       (Value >= 0x01000000 && Value <= 0xff000000) ||
1886       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1887       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1888   }
1889 
1890   bool isNEONi64splat() const {
1891     if (!isImm()) return false;
1892     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1893     // Must be a constant.
1894     if (!CE) return false;
1895     uint64_t Value = CE->getValue();
1896     // i64 value with each byte being either 0 or 0xff.
1897     for (unsigned i = 0; i < 8; ++i, Value >>= 8)
1898       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1899     return true;
1900   }
1901 
1902   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1903     // Add as immediates when possible.  Null MCExpr = 0.
1904     if (!Expr)
1905       Inst.addOperand(MCOperand::createImm(0));
1906     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1907       Inst.addOperand(MCOperand::createImm(CE->getValue()));
1908     else
1909       Inst.addOperand(MCOperand::createExpr(Expr));
1910   }
1911 
1912   void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
1913     assert(N == 1 && "Invalid number of operands!");
1914     addExpr(Inst, getImm());
1915   }
1916 
1917   void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
1918     assert(N == 1 && "Invalid number of operands!");
1919     addExpr(Inst, getImm());
1920   }
1921 
1922   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1923     assert(N == 2 && "Invalid number of operands!");
1924     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1925     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1926     Inst.addOperand(MCOperand::createReg(RegNum));
1927   }
1928 
1929   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1930     assert(N == 1 && "Invalid number of operands!");
1931     Inst.addOperand(MCOperand::createImm(getCoproc()));
1932   }
1933 
1934   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1935     assert(N == 1 && "Invalid number of operands!");
1936     Inst.addOperand(MCOperand::createImm(getCoproc()));
1937   }
1938 
1939   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1940     assert(N == 1 && "Invalid number of operands!");
1941     Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
1942   }
1943 
1944   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1945     assert(N == 1 && "Invalid number of operands!");
1946     Inst.addOperand(MCOperand::createImm(ITMask.Mask));
1947   }
1948 
1949   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1950     assert(N == 1 && "Invalid number of operands!");
1951     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1952   }
1953 
1954   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1955     assert(N == 1 && "Invalid number of operands!");
1956     Inst.addOperand(MCOperand::createReg(getReg()));
1957   }
1958 
1959   void addRegOperands(MCInst &Inst, unsigned N) const {
1960     assert(N == 1 && "Invalid number of operands!");
1961     Inst.addOperand(MCOperand::createReg(getReg()));
1962   }
1963 
1964   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1965     assert(N == 3 && "Invalid number of operands!");
1966     assert(isRegShiftedReg() &&
1967            "addRegShiftedRegOperands() on non-RegShiftedReg!");
1968     Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
1969     Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
1970     Inst.addOperand(MCOperand::createImm(
1971       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1972   }
1973 
1974   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1975     assert(N == 2 && "Invalid number of operands!");
1976     assert(isRegShiftedImm() &&
1977            "addRegShiftedImmOperands() on non-RegShiftedImm!");
1978     Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
1979     // Shift of #32 is encoded as 0 where permitted
1980     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1981     Inst.addOperand(MCOperand::createImm(
1982       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1983   }
1984 
1985   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1986     assert(N == 1 && "Invalid number of operands!");
1987     Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
1988                                          ShifterImm.Imm));
1989   }
1990 
1991   void addRegListOperands(MCInst &Inst, unsigned N) const {
1992     assert(N == 1 && "Invalid number of operands!");
1993     const SmallVectorImpl<unsigned> &RegList = getRegList();
1994     for (SmallVectorImpl<unsigned>::const_iterator
1995            I = RegList.begin(), E = RegList.end(); I != E; ++I)
1996       Inst.addOperand(MCOperand::createReg(*I));
1997   }
1998 
1999   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2000     addRegListOperands(Inst, N);
2001   }
2002 
2003   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2004     addRegListOperands(Inst, N);
2005   }
2006 
2007   void addRotImmOperands(MCInst &Inst, unsigned N) const {
2008     assert(N == 1 && "Invalid number of operands!");
2009     // Encoded as val>>3. The printer handles display as 8, 16, 24.
2010     Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2011   }
2012 
2013   void addModImmOperands(MCInst &Inst, unsigned N) const {
2014     assert(N == 1 && "Invalid number of operands!");
2015 
2016     // Support for fixups (MCFixup)
2017     if (isImm())
2018       return addImmOperands(Inst, N);
2019 
2020     Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2021   }
2022 
2023   void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2024     assert(N == 1 && "Invalid number of operands!");
2025     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2026     uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2027     Inst.addOperand(MCOperand::createImm(Enc));
2028   }
2029 
2030   void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2031     assert(N == 1 && "Invalid number of operands!");
2032     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2033     uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2034     Inst.addOperand(MCOperand::createImm(Enc));
2035   }
2036 
2037   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2038     assert(N == 1 && "Invalid number of operands!");
2039     // Munge the lsb/width into a bitfield mask.
2040     unsigned lsb = Bitfield.LSB;
2041     unsigned width = Bitfield.Width;
2042     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2043     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2044                       (32 - (lsb + width)));
2045     Inst.addOperand(MCOperand::createImm(Mask));
2046   }
2047 
2048   void addImmOperands(MCInst &Inst, unsigned N) const {
2049     assert(N == 1 && "Invalid number of operands!");
2050     addExpr(Inst, getImm());
2051   }
2052 
2053   void addFBits16Operands(MCInst &Inst, unsigned N) const {
2054     assert(N == 1 && "Invalid number of operands!");
2055     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2056     Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2057   }
2058 
2059   void addFBits32Operands(MCInst &Inst, unsigned N) const {
2060     assert(N == 1 && "Invalid number of operands!");
2061     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2062     Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2063   }
2064 
2065   void addFPImmOperands(MCInst &Inst, unsigned N) const {
2066     assert(N == 1 && "Invalid number of operands!");
2067     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2068     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2069     Inst.addOperand(MCOperand::createImm(Val));
2070   }
2071 
2072   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2073     assert(N == 1 && "Invalid number of operands!");
2074     // FIXME: We really want to scale the value here, but the LDRD/STRD
2075     // instruction don't encode operands that way yet.
2076     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2077     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2078   }
2079 
2080   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2081     assert(N == 1 && "Invalid number of operands!");
2082     // The immediate is scaled by four in the encoding and is stored
2083     // in the MCInst as such. Lop off the low two bits here.
2084     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2085     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2086   }
2087 
2088   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2089     assert(N == 1 && "Invalid number of operands!");
2090     // The immediate is scaled by four in the encoding and is stored
2091     // in the MCInst as such. Lop off the low two bits here.
2092     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2093     Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2094   }
2095 
2096   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2097     assert(N == 1 && "Invalid number of operands!");
2098     // The immediate is scaled by four in the encoding and is stored
2099     // in the MCInst as such. Lop off the low two bits here.
2100     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2101     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2102   }
2103 
2104   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2105     assert(N == 1 && "Invalid number of operands!");
2106     // The constant encodes as the immediate-1, and we store in the instruction
2107     // the bits as encoded, so subtract off one here.
2108     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2109     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2110   }
2111 
2112   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2113     assert(N == 1 && "Invalid number of operands!");
2114     // The constant encodes as the immediate-1, and we store in the instruction
2115     // the bits as encoded, so subtract off one here.
2116     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2117     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2118   }
2119 
2120   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2121     assert(N == 1 && "Invalid number of operands!");
2122     // The constant encodes as the immediate, except for 32, which encodes as
2123     // zero.
2124     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2125     unsigned Imm = CE->getValue();
2126     Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2127   }
2128 
2129   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2130     assert(N == 1 && "Invalid number of operands!");
2131     // An ASR value of 32 encodes as 0, so that's how we want to add it to
2132     // the instruction as well.
2133     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2134     int Val = CE->getValue();
2135     Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2136   }
2137 
2138   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2139     assert(N == 1 && "Invalid number of operands!");
2140     // The operand is actually a t2_so_imm, but we have its bitwise
2141     // negation in the assembly source, so twiddle it here.
2142     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2143     Inst.addOperand(MCOperand::createImm(~CE->getValue()));
2144   }
2145 
2146   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2147     assert(N == 1 && "Invalid number of operands!");
2148     // The operand is actually a t2_so_imm, but we have its
2149     // negation in the assembly source, so twiddle it here.
2150     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2151     Inst.addOperand(MCOperand::createImm(-CE->getValue()));
2152   }
2153 
2154   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2155     assert(N == 1 && "Invalid number of operands!");
2156     // The operand is actually an imm0_4095, but we have its
2157     // negation in the assembly source, so twiddle it here.
2158     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2159     Inst.addOperand(MCOperand::createImm(-CE->getValue()));
2160   }
2161 
2162   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2163     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2164       Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2165       return;
2166     }
2167 
2168     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2169     assert(SR && "Unknown value type!");
2170     Inst.addOperand(MCOperand::createExpr(SR));
2171   }
2172 
2173   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2174     assert(N == 1 && "Invalid number of operands!");
2175     if (isImm()) {
2176       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2177       if (CE) {
2178         Inst.addOperand(MCOperand::createImm(CE->getValue()));
2179         return;
2180       }
2181 
2182       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2183 
2184       assert(SR && "Unknown value type!");
2185       Inst.addOperand(MCOperand::createExpr(SR));
2186       return;
2187     }
2188 
2189     assert(isMem()  && "Unknown value type!");
2190     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2191     Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2192   }
2193 
2194   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2195     assert(N == 1 && "Invalid number of operands!");
2196     Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2197   }
2198 
2199   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2200     assert(N == 1 && "Invalid number of operands!");
2201     Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2202   }
2203 
2204   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2205     assert(N == 1 && "Invalid number of operands!");
2206     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2207   }
2208 
2209   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2210     assert(N == 1 && "Invalid number of operands!");
2211     int32_t Imm = Memory.OffsetImm->getValue();
2212     Inst.addOperand(MCOperand::createImm(Imm));
2213   }
2214 
2215   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2216     assert(N == 1 && "Invalid number of operands!");
2217     assert(isImm() && "Not an immediate!");
2218 
2219     // If we have an immediate that's not a constant, treat it as a label
2220     // reference needing a fixup.
2221     if (!isa<MCConstantExpr>(getImm())) {
2222       Inst.addOperand(MCOperand::createExpr(getImm()));
2223       return;
2224     }
2225 
2226     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2227     int Val = CE->getValue();
2228     Inst.addOperand(MCOperand::createImm(Val));
2229   }
2230 
2231   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2232     assert(N == 2 && "Invalid number of operands!");
2233     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2234     Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2235   }
2236 
2237   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2238     addAlignedMemoryOperands(Inst, N);
2239   }
2240 
2241   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2242     addAlignedMemoryOperands(Inst, N);
2243   }
2244 
2245   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2246     addAlignedMemoryOperands(Inst, N);
2247   }
2248 
2249   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2250     addAlignedMemoryOperands(Inst, N);
2251   }
2252 
2253   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2254     addAlignedMemoryOperands(Inst, N);
2255   }
2256 
2257   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2258     addAlignedMemoryOperands(Inst, N);
2259   }
2260 
2261   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2262     addAlignedMemoryOperands(Inst, N);
2263   }
2264 
2265   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2266     addAlignedMemoryOperands(Inst, N);
2267   }
2268 
2269   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2270     addAlignedMemoryOperands(Inst, N);
2271   }
2272 
2273   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2274     addAlignedMemoryOperands(Inst, N);
2275   }
2276 
2277   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2278     addAlignedMemoryOperands(Inst, N);
2279   }
2280 
2281   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2282     assert(N == 3 && "Invalid number of operands!");
2283     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2284     if (!Memory.OffsetRegNum) {
2285       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2286       // Special case for #-0
2287       if (Val == INT32_MIN) Val = 0;
2288       if (Val < 0) Val = -Val;
2289       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2290     } else {
2291       // For register offset, we encode the shift type and negation flag
2292       // here.
2293       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2294                               Memory.ShiftImm, Memory.ShiftType);
2295     }
2296     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2297     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2298     Inst.addOperand(MCOperand::createImm(Val));
2299   }
2300 
2301   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2302     assert(N == 2 && "Invalid number of operands!");
2303     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2304     assert(CE && "non-constant AM2OffsetImm operand!");
2305     int32_t Val = CE->getValue();
2306     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2307     // Special case for #-0
2308     if (Val == INT32_MIN) Val = 0;
2309     if (Val < 0) Val = -Val;
2310     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2311     Inst.addOperand(MCOperand::createReg(0));
2312     Inst.addOperand(MCOperand::createImm(Val));
2313   }
2314 
2315   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2316     assert(N == 3 && "Invalid number of operands!");
2317     // If we have an immediate that's not a constant, treat it as a label
2318     // reference needing a fixup. If it is a constant, it's something else
2319     // and we reject it.
2320     if (isImm()) {
2321       Inst.addOperand(MCOperand::createExpr(getImm()));
2322       Inst.addOperand(MCOperand::createReg(0));
2323       Inst.addOperand(MCOperand::createImm(0));
2324       return;
2325     }
2326 
2327     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2328     if (!Memory.OffsetRegNum) {
2329       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2330       // Special case for #-0
2331       if (Val == INT32_MIN) Val = 0;
2332       if (Val < 0) Val = -Val;
2333       Val = ARM_AM::getAM3Opc(AddSub, Val);
2334     } else {
2335       // For register offset, we encode the shift type and negation flag
2336       // here.
2337       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2338     }
2339     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2340     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2341     Inst.addOperand(MCOperand::createImm(Val));
2342   }
2343 
2344   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2345     assert(N == 2 && "Invalid number of operands!");
2346     if (Kind == k_PostIndexRegister) {
2347       int32_t Val =
2348         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2349       Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2350       Inst.addOperand(MCOperand::createImm(Val));
2351       return;
2352     }
2353 
2354     // Constant offset.
2355     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2356     int32_t Val = CE->getValue();
2357     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2358     // Special case for #-0
2359     if (Val == INT32_MIN) Val = 0;
2360     if (Val < 0) Val = -Val;
2361     Val = ARM_AM::getAM3Opc(AddSub, Val);
2362     Inst.addOperand(MCOperand::createReg(0));
2363     Inst.addOperand(MCOperand::createImm(Val));
2364   }
2365 
2366   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2367     assert(N == 2 && "Invalid number of operands!");
2368     // If we have an immediate that's not a constant, treat it as a label
2369     // reference needing a fixup. If it is a constant, it's something else
2370     // and we reject it.
2371     if (isImm()) {
2372       Inst.addOperand(MCOperand::createExpr(getImm()));
2373       Inst.addOperand(MCOperand::createImm(0));
2374       return;
2375     }
2376 
2377     // The lower two bits are always zero and as such are not encoded.
2378     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2379     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2380     // Special case for #-0
2381     if (Val == INT32_MIN) Val = 0;
2382     if (Val < 0) Val = -Val;
2383     Val = ARM_AM::getAM5Opc(AddSub, Val);
2384     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2385     Inst.addOperand(MCOperand::createImm(Val));
2386   }
2387 
2388   void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2389     assert(N == 2 && "Invalid number of operands!");
2390     // If we have an immediate that's not a constant, treat it as a label
2391     // reference needing a fixup. If it is a constant, it's something else
2392     // and we reject it.
2393     if (isImm()) {
2394       Inst.addOperand(MCOperand::createExpr(getImm()));
2395       Inst.addOperand(MCOperand::createImm(0));
2396       return;
2397     }
2398 
2399     // The lower bit is always zero and as such is not encoded.
2400     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2401     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2402     // Special case for #-0
2403     if (Val == INT32_MIN) Val = 0;
2404     if (Val < 0) Val = -Val;
2405     Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2406     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2407     Inst.addOperand(MCOperand::createImm(Val));
2408   }
2409 
2410   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2411     assert(N == 2 && "Invalid number of operands!");
2412     // If we have an immediate that's not a constant, treat it as a label
2413     // reference needing a fixup. If it is a constant, it's something else
2414     // and we reject it.
2415     if (isImm()) {
2416       Inst.addOperand(MCOperand::createExpr(getImm()));
2417       Inst.addOperand(MCOperand::createImm(0));
2418       return;
2419     }
2420 
2421     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2422     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2423     Inst.addOperand(MCOperand::createImm(Val));
2424   }
2425 
2426   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2427     assert(N == 2 && "Invalid number of operands!");
2428     // The lower two bits are always zero and as such are not encoded.
2429     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2430     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2431     Inst.addOperand(MCOperand::createImm(Val));
2432   }
2433 
2434   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2435     assert(N == 2 && "Invalid number of operands!");
2436     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2437     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2438     Inst.addOperand(MCOperand::createImm(Val));
2439   }
2440 
2441   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2442     addMemImm8OffsetOperands(Inst, N);
2443   }
2444 
2445   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2446     addMemImm8OffsetOperands(Inst, N);
2447   }
2448 
2449   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2450     assert(N == 2 && "Invalid number of operands!");
2451     // If this is an immediate, it's a label reference.
2452     if (isImm()) {
2453       addExpr(Inst, getImm());
2454       Inst.addOperand(MCOperand::createImm(0));
2455       return;
2456     }
2457 
2458     // Otherwise, it's a normal memory reg+offset.
2459     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2460     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2461     Inst.addOperand(MCOperand::createImm(Val));
2462   }
2463 
2464   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2465     assert(N == 2 && "Invalid number of operands!");
2466     // If this is an immediate, it's a label reference.
2467     if (isImm()) {
2468       addExpr(Inst, getImm());
2469       Inst.addOperand(MCOperand::createImm(0));
2470       return;
2471     }
2472 
2473     // Otherwise, it's a normal memory reg+offset.
2474     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2475     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2476     Inst.addOperand(MCOperand::createImm(Val));
2477   }
2478 
2479   void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
2480     assert(N == 1 && "Invalid number of operands!");
2481     // This is container for the immediate that we will create the constant
2482     // pool from
2483     addExpr(Inst, getConstantPoolImm());
2484     return;
2485   }
2486 
2487   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2488     assert(N == 2 && "Invalid number of operands!");
2489     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2490     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2491   }
2492 
2493   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2494     assert(N == 2 && "Invalid number of operands!");
2495     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2496     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2497   }
2498 
2499   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2500     assert(N == 3 && "Invalid number of operands!");
2501     unsigned Val =
2502       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2503                         Memory.ShiftImm, Memory.ShiftType);
2504     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2505     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2506     Inst.addOperand(MCOperand::createImm(Val));
2507   }
2508 
2509   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2510     assert(N == 3 && "Invalid number of operands!");
2511     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2512     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2513     Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2514   }
2515 
2516   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2517     assert(N == 2 && "Invalid number of operands!");
2518     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2519     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2520   }
2521 
2522   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2523     assert(N == 2 && "Invalid number of operands!");
2524     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2525     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2526     Inst.addOperand(MCOperand::createImm(Val));
2527   }
2528 
2529   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2530     assert(N == 2 && "Invalid number of operands!");
2531     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2532     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2533     Inst.addOperand(MCOperand::createImm(Val));
2534   }
2535 
2536   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2537     assert(N == 2 && "Invalid number of operands!");
2538     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2539     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2540     Inst.addOperand(MCOperand::createImm(Val));
2541   }
2542 
2543   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2544     assert(N == 2 && "Invalid number of operands!");
2545     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2546     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2547     Inst.addOperand(MCOperand::createImm(Val));
2548   }
2549 
2550   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2551     assert(N == 1 && "Invalid number of operands!");
2552     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2553     assert(CE && "non-constant post-idx-imm8 operand!");
2554     int Imm = CE->getValue();
2555     bool isAdd = Imm >= 0;
2556     if (Imm == INT32_MIN) Imm = 0;
2557     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2558     Inst.addOperand(MCOperand::createImm(Imm));
2559   }
2560 
2561   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2562     assert(N == 1 && "Invalid number of operands!");
2563     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2564     assert(CE && "non-constant post-idx-imm8s4 operand!");
2565     int Imm = CE->getValue();
2566     bool isAdd = Imm >= 0;
2567     if (Imm == INT32_MIN) Imm = 0;
2568     // Immediate is scaled by 4.
2569     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2570     Inst.addOperand(MCOperand::createImm(Imm));
2571   }
2572 
2573   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2574     assert(N == 2 && "Invalid number of operands!");
2575     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2576     Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2577   }
2578 
2579   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2580     assert(N == 2 && "Invalid number of operands!");
2581     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2582     // The sign, shift type, and shift amount are encoded in a single operand
2583     // using the AM2 encoding helpers.
2584     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2585     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2586                                      PostIdxReg.ShiftTy);
2587     Inst.addOperand(MCOperand::createImm(Imm));
2588   }
2589 
2590   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2591     assert(N == 1 && "Invalid number of operands!");
2592     Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2593   }
2594 
2595   void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2596     assert(N == 1 && "Invalid number of operands!");
2597     Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2598   }
2599 
2600   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2601     assert(N == 1 && "Invalid number of operands!");
2602     Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2603   }
2604 
2605   void addVecListOperands(MCInst &Inst, unsigned N) const {
2606     assert(N == 1 && "Invalid number of operands!");
2607     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2608   }
2609 
2610   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2611     assert(N == 2 && "Invalid number of operands!");
2612     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2613     Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2614   }
2615 
2616   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2617     assert(N == 1 && "Invalid number of operands!");
2618     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2619   }
2620 
2621   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2622     assert(N == 1 && "Invalid number of operands!");
2623     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2624   }
2625 
2626   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2627     assert(N == 1 && "Invalid number of operands!");
2628     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2629   }
2630 
2631   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2632     assert(N == 1 && "Invalid number of operands!");
2633     // The immediate encodes the type of constant as well as the value.
2634     // Mask in that this is an i8 splat.
2635     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2636     Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2637   }
2638 
2639   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2640     assert(N == 1 && "Invalid number of operands!");
2641     // The immediate encodes the type of constant as well as the value.
2642     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2643     unsigned Value = CE->getValue();
2644     Value = ARM_AM::encodeNEONi16splat(Value);
2645     Inst.addOperand(MCOperand::createImm(Value));
2646   }
2647 
2648   void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2649     assert(N == 1 && "Invalid number of operands!");
2650     // The immediate encodes the type of constant as well as the value.
2651     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2652     unsigned Value = CE->getValue();
2653     Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2654     Inst.addOperand(MCOperand::createImm(Value));
2655   }
2656 
2657   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2658     assert(N == 1 && "Invalid number of operands!");
2659     // The immediate encodes the type of constant as well as the value.
2660     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2661     unsigned Value = CE->getValue();
2662     Value = ARM_AM::encodeNEONi32splat(Value);
2663     Inst.addOperand(MCOperand::createImm(Value));
2664   }
2665 
2666   void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2667     assert(N == 1 && "Invalid number of operands!");
2668     // The immediate encodes the type of constant as well as the value.
2669     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2670     unsigned Value = CE->getValue();
2671     Value = ARM_AM::encodeNEONi32splat(~Value);
2672     Inst.addOperand(MCOperand::createImm(Value));
2673   }
2674 
2675   void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2676     assert(N == 1 && "Invalid number of operands!");
2677     // The immediate encodes the type of constant as well as the value.
2678     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2679     unsigned Value = CE->getValue();
2680     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2681             Inst.getOpcode() == ARM::VMOVv16i8) &&
2682            "All vmvn instructions that wants to replicate non-zero byte "
2683            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2684     unsigned B = ((~Value) & 0xff);
2685     B |= 0xe00; // cmode = 0b1110
2686     Inst.addOperand(MCOperand::createImm(B));
2687   }
2688   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2689     assert(N == 1 && "Invalid number of operands!");
2690     // The immediate encodes the type of constant as well as the value.
2691     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2692     unsigned Value = CE->getValue();
2693     if (Value >= 256 && Value <= 0xffff)
2694       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2695     else if (Value > 0xffff && Value <= 0xffffff)
2696       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2697     else if (Value > 0xffffff)
2698       Value = (Value >> 24) | 0x600;
2699     Inst.addOperand(MCOperand::createImm(Value));
2700   }
2701 
2702   void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2703     assert(N == 1 && "Invalid number of operands!");
2704     // The immediate encodes the type of constant as well as the value.
2705     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2706     unsigned Value = CE->getValue();
2707     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2708             Inst.getOpcode() == ARM::VMOVv16i8) &&
2709            "All instructions that wants to replicate non-zero byte "
2710            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2711     unsigned B = Value & 0xff;
2712     B |= 0xe00; // cmode = 0b1110
2713     Inst.addOperand(MCOperand::createImm(B));
2714   }
2715   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2716     assert(N == 1 && "Invalid number of operands!");
2717     // The immediate encodes the type of constant as well as the value.
2718     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2719     unsigned Value = ~CE->getValue();
2720     if (Value >= 256 && Value <= 0xffff)
2721       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2722     else if (Value > 0xffff && Value <= 0xffffff)
2723       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2724     else if (Value > 0xffffff)
2725       Value = (Value >> 24) | 0x600;
2726     Inst.addOperand(MCOperand::createImm(Value));
2727   }
2728 
2729   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2730     assert(N == 1 && "Invalid number of operands!");
2731     // The immediate encodes the type of constant as well as the value.
2732     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2733     uint64_t Value = CE->getValue();
2734     unsigned Imm = 0;
2735     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2736       Imm |= (Value & 1) << i;
2737     }
2738     Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2739   }
2740 
2741   void print(raw_ostream &OS) const override;
2742 
2743   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2744     auto Op = make_unique<ARMOperand>(k_ITCondMask);
2745     Op->ITMask.Mask = Mask;
2746     Op->StartLoc = S;
2747     Op->EndLoc = S;
2748     return Op;
2749   }
2750 
2751   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2752                                                     SMLoc S) {
2753     auto Op = make_unique<ARMOperand>(k_CondCode);
2754     Op->CC.Val = CC;
2755     Op->StartLoc = S;
2756     Op->EndLoc = S;
2757     return Op;
2758   }
2759 
2760   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2761     auto Op = make_unique<ARMOperand>(k_CoprocNum);
2762     Op->Cop.Val = CopVal;
2763     Op->StartLoc = S;
2764     Op->EndLoc = S;
2765     return Op;
2766   }
2767 
2768   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2769     auto Op = make_unique<ARMOperand>(k_CoprocReg);
2770     Op->Cop.Val = CopVal;
2771     Op->StartLoc = S;
2772     Op->EndLoc = S;
2773     return Op;
2774   }
2775 
2776   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2777                                                         SMLoc E) {
2778     auto Op = make_unique<ARMOperand>(k_CoprocOption);
2779     Op->Cop.Val = Val;
2780     Op->StartLoc = S;
2781     Op->EndLoc = E;
2782     return Op;
2783   }
2784 
2785   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2786     auto Op = make_unique<ARMOperand>(k_CCOut);
2787     Op->Reg.RegNum = RegNum;
2788     Op->StartLoc = S;
2789     Op->EndLoc = S;
2790     return Op;
2791   }
2792 
2793   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2794     auto Op = make_unique<ARMOperand>(k_Token);
2795     Op->Tok.Data = Str.data();
2796     Op->Tok.Length = Str.size();
2797     Op->StartLoc = S;
2798     Op->EndLoc = S;
2799     return Op;
2800   }
2801 
2802   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2803                                                SMLoc E) {
2804     auto Op = make_unique<ARMOperand>(k_Register);
2805     Op->Reg.RegNum = RegNum;
2806     Op->StartLoc = S;
2807     Op->EndLoc = E;
2808     return Op;
2809   }
2810 
2811   static std::unique_ptr<ARMOperand>
2812   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2813                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2814                         SMLoc E) {
2815     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2816     Op->RegShiftedReg.ShiftTy = ShTy;
2817     Op->RegShiftedReg.SrcReg = SrcReg;
2818     Op->RegShiftedReg.ShiftReg = ShiftReg;
2819     Op->RegShiftedReg.ShiftImm = ShiftImm;
2820     Op->StartLoc = S;
2821     Op->EndLoc = E;
2822     return Op;
2823   }
2824 
2825   static std::unique_ptr<ARMOperand>
2826   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2827                          unsigned ShiftImm, SMLoc S, SMLoc E) {
2828     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2829     Op->RegShiftedImm.ShiftTy = ShTy;
2830     Op->RegShiftedImm.SrcReg = SrcReg;
2831     Op->RegShiftedImm.ShiftImm = ShiftImm;
2832     Op->StartLoc = S;
2833     Op->EndLoc = E;
2834     return Op;
2835   }
2836 
2837   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2838                                                       SMLoc S, SMLoc E) {
2839     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2840     Op->ShifterImm.isASR = isASR;
2841     Op->ShifterImm.Imm = Imm;
2842     Op->StartLoc = S;
2843     Op->EndLoc = E;
2844     return Op;
2845   }
2846 
2847   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2848                                                   SMLoc E) {
2849     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2850     Op->RotImm.Imm = Imm;
2851     Op->StartLoc = S;
2852     Op->EndLoc = E;
2853     return Op;
2854   }
2855 
2856   static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2857                                                   SMLoc S, SMLoc E) {
2858     auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2859     Op->ModImm.Bits = Bits;
2860     Op->ModImm.Rot = Rot;
2861     Op->StartLoc = S;
2862     Op->EndLoc = E;
2863     return Op;
2864   }
2865 
2866   static std::unique_ptr<ARMOperand>
2867   CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2868     auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate);
2869     Op->Imm.Val = Val;
2870     Op->StartLoc = S;
2871     Op->EndLoc = E;
2872     return Op;
2873   }
2874 
2875   static std::unique_ptr<ARMOperand>
2876   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2877     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2878     Op->Bitfield.LSB = LSB;
2879     Op->Bitfield.Width = Width;
2880     Op->StartLoc = S;
2881     Op->EndLoc = E;
2882     return Op;
2883   }
2884 
2885   static std::unique_ptr<ARMOperand>
2886   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2887                 SMLoc StartLoc, SMLoc EndLoc) {
2888     assert (Regs.size() > 0 && "RegList contains no registers?");
2889     KindTy Kind = k_RegisterList;
2890 
2891     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2892       Kind = k_DPRRegisterList;
2893     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2894              contains(Regs.front().second))
2895       Kind = k_SPRRegisterList;
2896 
2897     // Sort based on the register encoding values.
2898     array_pod_sort(Regs.begin(), Regs.end());
2899 
2900     auto Op = make_unique<ARMOperand>(Kind);
2901     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2902            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2903       Op->Registers.push_back(I->second);
2904     Op->StartLoc = StartLoc;
2905     Op->EndLoc = EndLoc;
2906     return Op;
2907   }
2908 
2909   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2910                                                       unsigned Count,
2911                                                       bool isDoubleSpaced,
2912                                                       SMLoc S, SMLoc E) {
2913     auto Op = make_unique<ARMOperand>(k_VectorList);
2914     Op->VectorList.RegNum = RegNum;
2915     Op->VectorList.Count = Count;
2916     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2917     Op->StartLoc = S;
2918     Op->EndLoc = E;
2919     return Op;
2920   }
2921 
2922   static std::unique_ptr<ARMOperand>
2923   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2924                            SMLoc S, SMLoc E) {
2925     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2926     Op->VectorList.RegNum = RegNum;
2927     Op->VectorList.Count = Count;
2928     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2929     Op->StartLoc = S;
2930     Op->EndLoc = E;
2931     return Op;
2932   }
2933 
2934   static std::unique_ptr<ARMOperand>
2935   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2936                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
2937     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2938     Op->VectorList.RegNum = RegNum;
2939     Op->VectorList.Count = Count;
2940     Op->VectorList.LaneIndex = Index;
2941     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2942     Op->StartLoc = S;
2943     Op->EndLoc = E;
2944     return Op;
2945   }
2946 
2947   static std::unique_ptr<ARMOperand>
2948   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2949     auto Op = make_unique<ARMOperand>(k_VectorIndex);
2950     Op->VectorIndex.Val = Idx;
2951     Op->StartLoc = S;
2952     Op->EndLoc = E;
2953     return Op;
2954   }
2955 
2956   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2957                                                SMLoc E) {
2958     auto Op = make_unique<ARMOperand>(k_Immediate);
2959     Op->Imm.Val = Val;
2960     Op->StartLoc = S;
2961     Op->EndLoc = E;
2962     return Op;
2963   }
2964 
2965   static std::unique_ptr<ARMOperand>
2966   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2967             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2968             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2969             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2970     auto Op = make_unique<ARMOperand>(k_Memory);
2971     Op->Memory.BaseRegNum = BaseRegNum;
2972     Op->Memory.OffsetImm = OffsetImm;
2973     Op->Memory.OffsetRegNum = OffsetRegNum;
2974     Op->Memory.ShiftType = ShiftType;
2975     Op->Memory.ShiftImm = ShiftImm;
2976     Op->Memory.Alignment = Alignment;
2977     Op->Memory.isNegative = isNegative;
2978     Op->StartLoc = S;
2979     Op->EndLoc = E;
2980     Op->AlignmentLoc = AlignmentLoc;
2981     return Op;
2982   }
2983 
2984   static std::unique_ptr<ARMOperand>
2985   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2986                    unsigned ShiftImm, SMLoc S, SMLoc E) {
2987     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2988     Op->PostIdxReg.RegNum = RegNum;
2989     Op->PostIdxReg.isAdd = isAdd;
2990     Op->PostIdxReg.ShiftTy = ShiftTy;
2991     Op->PostIdxReg.ShiftImm = ShiftImm;
2992     Op->StartLoc = S;
2993     Op->EndLoc = E;
2994     return Op;
2995   }
2996 
2997   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2998                                                          SMLoc S) {
2999     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
3000     Op->MBOpt.Val = Opt;
3001     Op->StartLoc = S;
3002     Op->EndLoc = S;
3003     return Op;
3004   }
3005 
3006   static std::unique_ptr<ARMOperand>
3007   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3008     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3009     Op->ISBOpt.Val = Opt;
3010     Op->StartLoc = S;
3011     Op->EndLoc = S;
3012     return Op;
3013   }
3014 
3015   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3016                                                       SMLoc S) {
3017     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
3018     Op->IFlags.Val = IFlags;
3019     Op->StartLoc = S;
3020     Op->EndLoc = S;
3021     return Op;
3022   }
3023 
3024   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3025     auto Op = make_unique<ARMOperand>(k_MSRMask);
3026     Op->MMask.Val = MMask;
3027     Op->StartLoc = S;
3028     Op->EndLoc = S;
3029     return Op;
3030   }
3031 
3032   static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3033     auto Op = make_unique<ARMOperand>(k_BankedReg);
3034     Op->BankedReg.Val = Reg;
3035     Op->StartLoc = S;
3036     Op->EndLoc = S;
3037     return Op;
3038   }
3039 };
3040 
3041 } // end anonymous namespace.
3042 
3043 void ARMOperand::print(raw_ostream &OS) const {
3044   switch (Kind) {
3045   case k_CondCode:
3046     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3047     break;
3048   case k_CCOut:
3049     OS << "<ccout " << getReg() << ">";
3050     break;
3051   case k_ITCondMask: {
3052     static const char *const MaskStr[] = {
3053       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
3054       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
3055     };
3056     assert((ITMask.Mask & 0xf) == ITMask.Mask);
3057     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3058     break;
3059   }
3060   case k_CoprocNum:
3061     OS << "<coprocessor number: " << getCoproc() << ">";
3062     break;
3063   case k_CoprocReg:
3064     OS << "<coprocessor register: " << getCoproc() << ">";
3065     break;
3066   case k_CoprocOption:
3067     OS << "<coprocessor option: " << CoprocOption.Val << ">";
3068     break;
3069   case k_MSRMask:
3070     OS << "<mask: " << getMSRMask() << ">";
3071     break;
3072   case k_BankedReg:
3073     OS << "<banked reg: " << getBankedReg() << ">";
3074     break;
3075   case k_Immediate:
3076     OS << *getImm();
3077     break;
3078   case k_MemBarrierOpt:
3079     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3080     break;
3081   case k_InstSyncBarrierOpt:
3082     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3083     break;
3084   case k_Memory:
3085     OS << "<memory "
3086        << " base:" << Memory.BaseRegNum;
3087     OS << ">";
3088     break;
3089   case k_PostIndexRegister:
3090     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3091        << PostIdxReg.RegNum;
3092     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3093       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3094          << PostIdxReg.ShiftImm;
3095     OS << ">";
3096     break;
3097   case k_ProcIFlags: {
3098     OS << "<ARM_PROC::";
3099     unsigned IFlags = getProcIFlags();
3100     for (int i=2; i >= 0; --i)
3101       if (IFlags & (1 << i))
3102         OS << ARM_PROC::IFlagsToString(1 << i);
3103     OS << ">";
3104     break;
3105   }
3106   case k_Register:
3107     OS << "<register " << getReg() << ">";
3108     break;
3109   case k_ShifterImmediate:
3110     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3111        << " #" << ShifterImm.Imm << ">";
3112     break;
3113   case k_ShiftedRegister:
3114     OS << "<so_reg_reg "
3115        << RegShiftedReg.SrcReg << " "
3116        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
3117        << " " << RegShiftedReg.ShiftReg << ">";
3118     break;
3119   case k_ShiftedImmediate:
3120     OS << "<so_reg_imm "
3121        << RegShiftedImm.SrcReg << " "
3122        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
3123        << " #" << RegShiftedImm.ShiftImm << ">";
3124     break;
3125   case k_RotateImmediate:
3126     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3127     break;
3128   case k_ModifiedImmediate:
3129     OS << "<mod_imm #" << ModImm.Bits << ", #"
3130        <<  ModImm.Rot << ")>";
3131     break;
3132   case k_ConstantPoolImmediate:
3133     OS << "<constant_pool_imm #" << *getConstantPoolImm();
3134     break;
3135   case k_BitfieldDescriptor:
3136     OS << "<bitfield " << "lsb: " << Bitfield.LSB
3137        << ", width: " << Bitfield.Width << ">";
3138     break;
3139   case k_RegisterList:
3140   case k_DPRRegisterList:
3141   case k_SPRRegisterList: {
3142     OS << "<register_list ";
3143 
3144     const SmallVectorImpl<unsigned> &RegList = getRegList();
3145     for (SmallVectorImpl<unsigned>::const_iterator
3146            I = RegList.begin(), E = RegList.end(); I != E; ) {
3147       OS << *I;
3148       if (++I < E) OS << ", ";
3149     }
3150 
3151     OS << ">";
3152     break;
3153   }
3154   case k_VectorList:
3155     OS << "<vector_list " << VectorList.Count << " * "
3156        << VectorList.RegNum << ">";
3157     break;
3158   case k_VectorListAllLanes:
3159     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3160        << VectorList.RegNum << ">";
3161     break;
3162   case k_VectorListIndexed:
3163     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3164        << VectorList.Count << " * " << VectorList.RegNum << ">";
3165     break;
3166   case k_Token:
3167     OS << "'" << getToken() << "'";
3168     break;
3169   case k_VectorIndex:
3170     OS << "<vectorindex " << getVectorIndex() << ">";
3171     break;
3172   }
3173 }
3174 
3175 /// @name Auto-generated Match Functions
3176 /// {
3177 
3178 static unsigned MatchRegisterName(StringRef Name);
3179 
3180 /// }
3181 
3182 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3183                                  SMLoc &StartLoc, SMLoc &EndLoc) {
3184   const AsmToken &Tok = getParser().getTok();
3185   StartLoc = Tok.getLoc();
3186   EndLoc = Tok.getEndLoc();
3187   RegNo = tryParseRegister();
3188 
3189   return (RegNo == (unsigned)-1);
3190 }
3191 
3192 /// Try to parse a register name.  The token must be an Identifier when called,
3193 /// and if it is a register name the token is eaten and the register number is
3194 /// returned.  Otherwise return -1.
3195 ///
3196 int ARMAsmParser::tryParseRegister() {
3197   MCAsmParser &Parser = getParser();
3198   const AsmToken &Tok = Parser.getTok();
3199   if (Tok.isNot(AsmToken::Identifier)) return -1;
3200 
3201   std::string lowerCase = Tok.getString().lower();
3202   unsigned RegNum = MatchRegisterName(lowerCase);
3203   if (!RegNum) {
3204     RegNum = StringSwitch<unsigned>(lowerCase)
3205       .Case("r13", ARM::SP)
3206       .Case("r14", ARM::LR)
3207       .Case("r15", ARM::PC)
3208       .Case("ip", ARM::R12)
3209       // Additional register name aliases for 'gas' compatibility.
3210       .Case("a1", ARM::R0)
3211       .Case("a2", ARM::R1)
3212       .Case("a3", ARM::R2)
3213       .Case("a4", ARM::R3)
3214       .Case("v1", ARM::R4)
3215       .Case("v2", ARM::R5)
3216       .Case("v3", ARM::R6)
3217       .Case("v4", ARM::R7)
3218       .Case("v5", ARM::R8)
3219       .Case("v6", ARM::R9)
3220       .Case("v7", ARM::R10)
3221       .Case("v8", ARM::R11)
3222       .Case("sb", ARM::R9)
3223       .Case("sl", ARM::R10)
3224       .Case("fp", ARM::R11)
3225       .Default(0);
3226   }
3227   if (!RegNum) {
3228     // Check for aliases registered via .req. Canonicalize to lower case.
3229     // That's more consistent since register names are case insensitive, and
3230     // it's how the original entry was passed in from MC/MCParser/AsmParser.
3231     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3232     // If no match, return failure.
3233     if (Entry == RegisterReqs.end())
3234       return -1;
3235     Parser.Lex(); // Eat identifier token.
3236     return Entry->getValue();
3237   }
3238 
3239   // Some FPUs only have 16 D registers, so D16-D31 are invalid
3240   if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3241     return -1;
3242 
3243   Parser.Lex(); // Eat identifier token.
3244 
3245   return RegNum;
3246 }
3247 
3248 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
3249 // If a recoverable error occurs, return 1. If an irrecoverable error
3250 // occurs, return -1. An irrecoverable error is one where tokens have been
3251 // consumed in the process of trying to parse the shifter (i.e., when it is
3252 // indeed a shifter operand, but malformed).
3253 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3254   MCAsmParser &Parser = getParser();
3255   SMLoc S = Parser.getTok().getLoc();
3256   const AsmToken &Tok = Parser.getTok();
3257   if (Tok.isNot(AsmToken::Identifier))
3258     return -1;
3259 
3260   std::string lowerCase = Tok.getString().lower();
3261   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3262       .Case("asl", ARM_AM::lsl)
3263       .Case("lsl", ARM_AM::lsl)
3264       .Case("lsr", ARM_AM::lsr)
3265       .Case("asr", ARM_AM::asr)
3266       .Case("ror", ARM_AM::ror)
3267       .Case("rrx", ARM_AM::rrx)
3268       .Default(ARM_AM::no_shift);
3269 
3270   if (ShiftTy == ARM_AM::no_shift)
3271     return 1;
3272 
3273   Parser.Lex(); // Eat the operator.
3274 
3275   // The source register for the shift has already been added to the
3276   // operand list, so we need to pop it off and combine it into the shifted
3277   // register operand instead.
3278   std::unique_ptr<ARMOperand> PrevOp(
3279       (ARMOperand *)Operands.pop_back_val().release());
3280   if (!PrevOp->isReg())
3281     return Error(PrevOp->getStartLoc(), "shift must be of a register");
3282   int SrcReg = PrevOp->getReg();
3283 
3284   SMLoc EndLoc;
3285   int64_t Imm = 0;
3286   int ShiftReg = 0;
3287   if (ShiftTy == ARM_AM::rrx) {
3288     // RRX Doesn't have an explicit shift amount. The encoder expects
3289     // the shift register to be the same as the source register. Seems odd,
3290     // but OK.
3291     ShiftReg = SrcReg;
3292   } else {
3293     // Figure out if this is shifted by a constant or a register (for non-RRX).
3294     if (Parser.getTok().is(AsmToken::Hash) ||
3295         Parser.getTok().is(AsmToken::Dollar)) {
3296       Parser.Lex(); // Eat hash.
3297       SMLoc ImmLoc = Parser.getTok().getLoc();
3298       const MCExpr *ShiftExpr = nullptr;
3299       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3300         Error(ImmLoc, "invalid immediate shift value");
3301         return -1;
3302       }
3303       // The expression must be evaluatable as an immediate.
3304       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3305       if (!CE) {
3306         Error(ImmLoc, "invalid immediate shift value");
3307         return -1;
3308       }
3309       // Range check the immediate.
3310       // lsl, ror: 0 <= imm <= 31
3311       // lsr, asr: 0 <= imm <= 32
3312       Imm = CE->getValue();
3313       if (Imm < 0 ||
3314           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3315           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3316         Error(ImmLoc, "immediate shift value out of range");
3317         return -1;
3318       }
3319       // shift by zero is a nop. Always send it through as lsl.
3320       // ('as' compatibility)
3321       if (Imm == 0)
3322         ShiftTy = ARM_AM::lsl;
3323     } else if (Parser.getTok().is(AsmToken::Identifier)) {
3324       SMLoc L = Parser.getTok().getLoc();
3325       EndLoc = Parser.getTok().getEndLoc();
3326       ShiftReg = tryParseRegister();
3327       if (ShiftReg == -1) {
3328         Error(L, "expected immediate or register in shift operand");
3329         return -1;
3330       }
3331     } else {
3332       Error(Parser.getTok().getLoc(),
3333             "expected immediate or register in shift operand");
3334       return -1;
3335     }
3336   }
3337 
3338   if (ShiftReg && ShiftTy != ARM_AM::rrx)
3339     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3340                                                          ShiftReg, Imm,
3341                                                          S, EndLoc));
3342   else
3343     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3344                                                           S, EndLoc));
3345 
3346   return 0;
3347 }
3348 
3349 
3350 /// Try to parse a register name.  The token must be an Identifier when called.
3351 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3352 /// if there is a "writeback". 'true' if it's not a register.
3353 ///
3354 /// TODO this is likely to change to allow different register types and or to
3355 /// parse for a specific register type.
3356 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3357   MCAsmParser &Parser = getParser();
3358   const AsmToken &RegTok = Parser.getTok();
3359   int RegNo = tryParseRegister();
3360   if (RegNo == -1)
3361     return true;
3362 
3363   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3364                                            RegTok.getEndLoc()));
3365 
3366   const AsmToken &ExclaimTok = Parser.getTok();
3367   if (ExclaimTok.is(AsmToken::Exclaim)) {
3368     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3369                                                ExclaimTok.getLoc()));
3370     Parser.Lex(); // Eat exclaim token
3371     return false;
3372   }
3373 
3374   // Also check for an index operand. This is only legal for vector registers,
3375   // but that'll get caught OK in operand matching, so we don't need to
3376   // explicitly filter everything else out here.
3377   if (Parser.getTok().is(AsmToken::LBrac)) {
3378     SMLoc SIdx = Parser.getTok().getLoc();
3379     Parser.Lex(); // Eat left bracket token.
3380 
3381     const MCExpr *ImmVal;
3382     if (getParser().parseExpression(ImmVal))
3383       return true;
3384     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3385     if (!MCE)
3386       return TokError("immediate value expected for vector index");
3387 
3388     if (Parser.getTok().isNot(AsmToken::RBrac))
3389       return Error(Parser.getTok().getLoc(), "']' expected");
3390 
3391     SMLoc E = Parser.getTok().getEndLoc();
3392     Parser.Lex(); // Eat right bracket token.
3393 
3394     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3395                                                      SIdx, E,
3396                                                      getContext()));
3397   }
3398 
3399   return false;
3400 }
3401 
3402 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3403 /// instruction with a symbolic operand name.
3404 /// We accept "crN" syntax for GAS compatibility.
3405 /// <operand-name> ::= <prefix><number>
3406 /// If CoprocOp is 'c', then:
3407 ///   <prefix> ::= c | cr
3408 /// If CoprocOp is 'p', then :
3409 ///   <prefix> ::= p
3410 /// <number> ::= integer in range [0, 15]
3411 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3412   // Use the same layout as the tablegen'erated register name matcher. Ugly,
3413   // but efficient.
3414   if (Name.size() < 2 || Name[0] != CoprocOp)
3415     return -1;
3416   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3417 
3418   switch (Name.size()) {
3419   default: return -1;
3420   case 1:
3421     switch (Name[0]) {
3422     default:  return -1;
3423     case '0': return 0;
3424     case '1': return 1;
3425     case '2': return 2;
3426     case '3': return 3;
3427     case '4': return 4;
3428     case '5': return 5;
3429     case '6': return 6;
3430     case '7': return 7;
3431     case '8': return 8;
3432     case '9': return 9;
3433     }
3434   case 2:
3435     if (Name[0] != '1')
3436       return -1;
3437     switch (Name[1]) {
3438     default:  return -1;
3439     // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3440     // However, old cores (v5/v6) did use them in that way.
3441     case '0': return 10;
3442     case '1': return 11;
3443     case '2': return 12;
3444     case '3': return 13;
3445     case '4': return 14;
3446     case '5': return 15;
3447     }
3448   }
3449 }
3450 
3451 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3452 OperandMatchResultTy
3453 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3454   MCAsmParser &Parser = getParser();
3455   SMLoc S = Parser.getTok().getLoc();
3456   const AsmToken &Tok = Parser.getTok();
3457   if (!Tok.is(AsmToken::Identifier))
3458     return MatchOperand_NoMatch;
3459   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3460     .Case("eq", ARMCC::EQ)
3461     .Case("ne", ARMCC::NE)
3462     .Case("hs", ARMCC::HS)
3463     .Case("cs", ARMCC::HS)
3464     .Case("lo", ARMCC::LO)
3465     .Case("cc", ARMCC::LO)
3466     .Case("mi", ARMCC::MI)
3467     .Case("pl", ARMCC::PL)
3468     .Case("vs", ARMCC::VS)
3469     .Case("vc", ARMCC::VC)
3470     .Case("hi", ARMCC::HI)
3471     .Case("ls", ARMCC::LS)
3472     .Case("ge", ARMCC::GE)
3473     .Case("lt", ARMCC::LT)
3474     .Case("gt", ARMCC::GT)
3475     .Case("le", ARMCC::LE)
3476     .Case("al", ARMCC::AL)
3477     .Default(~0U);
3478   if (CC == ~0U)
3479     return MatchOperand_NoMatch;
3480   Parser.Lex(); // Eat the token.
3481 
3482   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3483 
3484   return MatchOperand_Success;
3485 }
3486 
3487 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3488 /// token must be an Identifier when called, and if it is a coprocessor
3489 /// number, the token is eaten and the operand is added to the operand list.
3490 OperandMatchResultTy
3491 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3492   MCAsmParser &Parser = getParser();
3493   SMLoc S = Parser.getTok().getLoc();
3494   const AsmToken &Tok = Parser.getTok();
3495   if (Tok.isNot(AsmToken::Identifier))
3496     return MatchOperand_NoMatch;
3497 
3498   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3499   if (Num == -1)
3500     return MatchOperand_NoMatch;
3501   // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3502   if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3503     return MatchOperand_NoMatch;
3504 
3505   Parser.Lex(); // Eat identifier token.
3506   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3507   return MatchOperand_Success;
3508 }
3509 
3510 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3511 /// token must be an Identifier when called, and if it is a coprocessor
3512 /// number, the token is eaten and the operand is added to the operand list.
3513 OperandMatchResultTy
3514 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3515   MCAsmParser &Parser = getParser();
3516   SMLoc S = Parser.getTok().getLoc();
3517   const AsmToken &Tok = Parser.getTok();
3518   if (Tok.isNot(AsmToken::Identifier))
3519     return MatchOperand_NoMatch;
3520 
3521   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3522   if (Reg == -1)
3523     return MatchOperand_NoMatch;
3524 
3525   Parser.Lex(); // Eat identifier token.
3526   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3527   return MatchOperand_Success;
3528 }
3529 
3530 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3531 /// coproc_option : '{' imm0_255 '}'
3532 OperandMatchResultTy
3533 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3534   MCAsmParser &Parser = getParser();
3535   SMLoc S = Parser.getTok().getLoc();
3536 
3537   // If this isn't a '{', this isn't a coprocessor immediate operand.
3538   if (Parser.getTok().isNot(AsmToken::LCurly))
3539     return MatchOperand_NoMatch;
3540   Parser.Lex(); // Eat the '{'
3541 
3542   const MCExpr *Expr;
3543   SMLoc Loc = Parser.getTok().getLoc();
3544   if (getParser().parseExpression(Expr)) {
3545     Error(Loc, "illegal expression");
3546     return MatchOperand_ParseFail;
3547   }
3548   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3549   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3550     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3551     return MatchOperand_ParseFail;
3552   }
3553   int Val = CE->getValue();
3554 
3555   // Check for and consume the closing '}'
3556   if (Parser.getTok().isNot(AsmToken::RCurly))
3557     return MatchOperand_ParseFail;
3558   SMLoc E = Parser.getTok().getEndLoc();
3559   Parser.Lex(); // Eat the '}'
3560 
3561   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3562   return MatchOperand_Success;
3563 }
3564 
3565 // For register list parsing, we need to map from raw GPR register numbering
3566 // to the enumeration values. The enumeration values aren't sorted by
3567 // register number due to our using "sp", "lr" and "pc" as canonical names.
3568 static unsigned getNextRegister(unsigned Reg) {
3569   // If this is a GPR, we need to do it manually, otherwise we can rely
3570   // on the sort ordering of the enumeration since the other reg-classes
3571   // are sane.
3572   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3573     return Reg + 1;
3574   switch(Reg) {
3575   default: llvm_unreachable("Invalid GPR number!");
3576   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3577   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3578   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3579   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3580   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3581   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3582   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3583   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3584   }
3585 }
3586 
3587 // Return the low-subreg of a given Q register.
3588 static unsigned getDRegFromQReg(unsigned QReg) {
3589   switch (QReg) {
3590   default: llvm_unreachable("expected a Q register!");
3591   case ARM::Q0:  return ARM::D0;
3592   case ARM::Q1:  return ARM::D2;
3593   case ARM::Q2:  return ARM::D4;
3594   case ARM::Q3:  return ARM::D6;
3595   case ARM::Q4:  return ARM::D8;
3596   case ARM::Q5:  return ARM::D10;
3597   case ARM::Q6:  return ARM::D12;
3598   case ARM::Q7:  return ARM::D14;
3599   case ARM::Q8:  return ARM::D16;
3600   case ARM::Q9:  return ARM::D18;
3601   case ARM::Q10: return ARM::D20;
3602   case ARM::Q11: return ARM::D22;
3603   case ARM::Q12: return ARM::D24;
3604   case ARM::Q13: return ARM::D26;
3605   case ARM::Q14: return ARM::D28;
3606   case ARM::Q15: return ARM::D30;
3607   }
3608 }
3609 
3610 /// Parse a register list.
3611 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3612   MCAsmParser &Parser = getParser();
3613   if (Parser.getTok().isNot(AsmToken::LCurly))
3614     return TokError("Token is not a Left Curly Brace");
3615   SMLoc S = Parser.getTok().getLoc();
3616   Parser.Lex(); // Eat '{' token.
3617   SMLoc RegLoc = Parser.getTok().getLoc();
3618 
3619   // Check the first register in the list to see what register class
3620   // this is a list of.
3621   int Reg = tryParseRegister();
3622   if (Reg == -1)
3623     return Error(RegLoc, "register expected");
3624 
3625   // The reglist instructions have at most 16 registers, so reserve
3626   // space for that many.
3627   int EReg = 0;
3628   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3629 
3630   // Allow Q regs and just interpret them as the two D sub-registers.
3631   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3632     Reg = getDRegFromQReg(Reg);
3633     EReg = MRI->getEncodingValue(Reg);
3634     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3635     ++Reg;
3636   }
3637   const MCRegisterClass *RC;
3638   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3639     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3640   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3641     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3642   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3643     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3644   else
3645     return Error(RegLoc, "invalid register in register list");
3646 
3647   // Store the register.
3648   EReg = MRI->getEncodingValue(Reg);
3649   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3650 
3651   // This starts immediately after the first register token in the list,
3652   // so we can see either a comma or a minus (range separator) as a legal
3653   // next token.
3654   while (Parser.getTok().is(AsmToken::Comma) ||
3655          Parser.getTok().is(AsmToken::Minus)) {
3656     if (Parser.getTok().is(AsmToken::Minus)) {
3657       Parser.Lex(); // Eat the minus.
3658       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3659       int EndReg = tryParseRegister();
3660       if (EndReg == -1)
3661         return Error(AfterMinusLoc, "register expected");
3662       // Allow Q regs and just interpret them as the two D sub-registers.
3663       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3664         EndReg = getDRegFromQReg(EndReg) + 1;
3665       // If the register is the same as the start reg, there's nothing
3666       // more to do.
3667       if (Reg == EndReg)
3668         continue;
3669       // The register must be in the same register class as the first.
3670       if (!RC->contains(EndReg))
3671         return Error(AfterMinusLoc, "invalid register in register list");
3672       // Ranges must go from low to high.
3673       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3674         return Error(AfterMinusLoc, "bad range in register list");
3675 
3676       // Add all the registers in the range to the register list.
3677       while (Reg != EndReg) {
3678         Reg = getNextRegister(Reg);
3679         EReg = MRI->getEncodingValue(Reg);
3680         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3681       }
3682       continue;
3683     }
3684     Parser.Lex(); // Eat the comma.
3685     RegLoc = Parser.getTok().getLoc();
3686     int OldReg = Reg;
3687     const AsmToken RegTok = Parser.getTok();
3688     Reg = tryParseRegister();
3689     if (Reg == -1)
3690       return Error(RegLoc, "register expected");
3691     // Allow Q regs and just interpret them as the two D sub-registers.
3692     bool isQReg = false;
3693     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3694       Reg = getDRegFromQReg(Reg);
3695       isQReg = true;
3696     }
3697     // The register must be in the same register class as the first.
3698     if (!RC->contains(Reg))
3699       return Error(RegLoc, "invalid register in register list");
3700     // List must be monotonically increasing.
3701     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3702       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3703         Warning(RegLoc, "register list not in ascending order");
3704       else
3705         return Error(RegLoc, "register list not in ascending order");
3706     }
3707     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3708       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3709               ") in register list");
3710       continue;
3711     }
3712     // VFP register lists must also be contiguous.
3713     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3714         Reg != OldReg + 1)
3715       return Error(RegLoc, "non-contiguous register range");
3716     EReg = MRI->getEncodingValue(Reg);
3717     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3718     if (isQReg) {
3719       EReg = MRI->getEncodingValue(++Reg);
3720       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3721     }
3722   }
3723 
3724   if (Parser.getTok().isNot(AsmToken::RCurly))
3725     return Error(Parser.getTok().getLoc(), "'}' expected");
3726   SMLoc E = Parser.getTok().getEndLoc();
3727   Parser.Lex(); // Eat '}' token.
3728 
3729   // Push the register list operand.
3730   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3731 
3732   // The ARM system instruction variants for LDM/STM have a '^' token here.
3733   if (Parser.getTok().is(AsmToken::Caret)) {
3734     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3735     Parser.Lex(); // Eat '^' token.
3736   }
3737 
3738   return false;
3739 }
3740 
3741 // Helper function to parse the lane index for vector lists.
3742 OperandMatchResultTy ARMAsmParser::
3743 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3744   MCAsmParser &Parser = getParser();
3745   Index = 0; // Always return a defined index value.
3746   if (Parser.getTok().is(AsmToken::LBrac)) {
3747     Parser.Lex(); // Eat the '['.
3748     if (Parser.getTok().is(AsmToken::RBrac)) {
3749       // "Dn[]" is the 'all lanes' syntax.
3750       LaneKind = AllLanes;
3751       EndLoc = Parser.getTok().getEndLoc();
3752       Parser.Lex(); // Eat the ']'.
3753       return MatchOperand_Success;
3754     }
3755 
3756     // There's an optional '#' token here. Normally there wouldn't be, but
3757     // inline assemble puts one in, and it's friendly to accept that.
3758     if (Parser.getTok().is(AsmToken::Hash))
3759       Parser.Lex(); // Eat '#' or '$'.
3760 
3761     const MCExpr *LaneIndex;
3762     SMLoc Loc = Parser.getTok().getLoc();
3763     if (getParser().parseExpression(LaneIndex)) {
3764       Error(Loc, "illegal expression");
3765       return MatchOperand_ParseFail;
3766     }
3767     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3768     if (!CE) {
3769       Error(Loc, "lane index must be empty or an integer");
3770       return MatchOperand_ParseFail;
3771     }
3772     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3773       Error(Parser.getTok().getLoc(), "']' expected");
3774       return MatchOperand_ParseFail;
3775     }
3776     EndLoc = Parser.getTok().getEndLoc();
3777     Parser.Lex(); // Eat the ']'.
3778     int64_t Val = CE->getValue();
3779 
3780     // FIXME: Make this range check context sensitive for .8, .16, .32.
3781     if (Val < 0 || Val > 7) {
3782       Error(Parser.getTok().getLoc(), "lane index out of range");
3783       return MatchOperand_ParseFail;
3784     }
3785     Index = Val;
3786     LaneKind = IndexedLane;
3787     return MatchOperand_Success;
3788   }
3789   LaneKind = NoLanes;
3790   return MatchOperand_Success;
3791 }
3792 
3793 // parse a vector register list
3794 OperandMatchResultTy
3795 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3796   MCAsmParser &Parser = getParser();
3797   VectorLaneTy LaneKind;
3798   unsigned LaneIndex;
3799   SMLoc S = Parser.getTok().getLoc();
3800   // As an extension (to match gas), support a plain D register or Q register
3801   // (without encosing curly braces) as a single or double entry list,
3802   // respectively.
3803   if (Parser.getTok().is(AsmToken::Identifier)) {
3804     SMLoc E = Parser.getTok().getEndLoc();
3805     int Reg = tryParseRegister();
3806     if (Reg == -1)
3807       return MatchOperand_NoMatch;
3808     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3809       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3810       if (Res != MatchOperand_Success)
3811         return Res;
3812       switch (LaneKind) {
3813       case NoLanes:
3814         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3815         break;
3816       case AllLanes:
3817         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3818                                                                 S, E));
3819         break;
3820       case IndexedLane:
3821         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3822                                                                LaneIndex,
3823                                                                false, S, E));
3824         break;
3825       }
3826       return MatchOperand_Success;
3827     }
3828     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3829       Reg = getDRegFromQReg(Reg);
3830       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3831       if (Res != MatchOperand_Success)
3832         return Res;
3833       switch (LaneKind) {
3834       case NoLanes:
3835         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3836                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3837         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3838         break;
3839       case AllLanes:
3840         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3841                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3842         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3843                                                                 S, E));
3844         break;
3845       case IndexedLane:
3846         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3847                                                                LaneIndex,
3848                                                                false, S, E));
3849         break;
3850       }
3851       return MatchOperand_Success;
3852     }
3853     Error(S, "vector register expected");
3854     return MatchOperand_ParseFail;
3855   }
3856 
3857   if (Parser.getTok().isNot(AsmToken::LCurly))
3858     return MatchOperand_NoMatch;
3859 
3860   Parser.Lex(); // Eat '{' token.
3861   SMLoc RegLoc = Parser.getTok().getLoc();
3862 
3863   int Reg = tryParseRegister();
3864   if (Reg == -1) {
3865     Error(RegLoc, "register expected");
3866     return MatchOperand_ParseFail;
3867   }
3868   unsigned Count = 1;
3869   int Spacing = 0;
3870   unsigned FirstReg = Reg;
3871   // The list is of D registers, but we also allow Q regs and just interpret
3872   // them as the two D sub-registers.
3873   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3874     FirstReg = Reg = getDRegFromQReg(Reg);
3875     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3876                  // it's ambiguous with four-register single spaced.
3877     ++Reg;
3878     ++Count;
3879   }
3880 
3881   SMLoc E;
3882   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3883     return MatchOperand_ParseFail;
3884 
3885   while (Parser.getTok().is(AsmToken::Comma) ||
3886          Parser.getTok().is(AsmToken::Minus)) {
3887     if (Parser.getTok().is(AsmToken::Minus)) {
3888       if (!Spacing)
3889         Spacing = 1; // Register range implies a single spaced list.
3890       else if (Spacing == 2) {
3891         Error(Parser.getTok().getLoc(),
3892               "sequential registers in double spaced list");
3893         return MatchOperand_ParseFail;
3894       }
3895       Parser.Lex(); // Eat the minus.
3896       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3897       int EndReg = tryParseRegister();
3898       if (EndReg == -1) {
3899         Error(AfterMinusLoc, "register expected");
3900         return MatchOperand_ParseFail;
3901       }
3902       // Allow Q regs and just interpret them as the two D sub-registers.
3903       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3904         EndReg = getDRegFromQReg(EndReg) + 1;
3905       // If the register is the same as the start reg, there's nothing
3906       // more to do.
3907       if (Reg == EndReg)
3908         continue;
3909       // The register must be in the same register class as the first.
3910       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3911         Error(AfterMinusLoc, "invalid register in register list");
3912         return MatchOperand_ParseFail;
3913       }
3914       // Ranges must go from low to high.
3915       if (Reg > EndReg) {
3916         Error(AfterMinusLoc, "bad range in register list");
3917         return MatchOperand_ParseFail;
3918       }
3919       // Parse the lane specifier if present.
3920       VectorLaneTy NextLaneKind;
3921       unsigned NextLaneIndex;
3922       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3923           MatchOperand_Success)
3924         return MatchOperand_ParseFail;
3925       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3926         Error(AfterMinusLoc, "mismatched lane index in register list");
3927         return MatchOperand_ParseFail;
3928       }
3929 
3930       // Add all the registers in the range to the register list.
3931       Count += EndReg - Reg;
3932       Reg = EndReg;
3933       continue;
3934     }
3935     Parser.Lex(); // Eat the comma.
3936     RegLoc = Parser.getTok().getLoc();
3937     int OldReg = Reg;
3938     Reg = tryParseRegister();
3939     if (Reg == -1) {
3940       Error(RegLoc, "register expected");
3941       return MatchOperand_ParseFail;
3942     }
3943     // vector register lists must be contiguous.
3944     // It's OK to use the enumeration values directly here rather, as the
3945     // VFP register classes have the enum sorted properly.
3946     //
3947     // The list is of D registers, but we also allow Q regs and just interpret
3948     // them as the two D sub-registers.
3949     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3950       if (!Spacing)
3951         Spacing = 1; // Register range implies a single spaced list.
3952       else if (Spacing == 2) {
3953         Error(RegLoc,
3954               "invalid register in double-spaced list (must be 'D' register')");
3955         return MatchOperand_ParseFail;
3956       }
3957       Reg = getDRegFromQReg(Reg);
3958       if (Reg != OldReg + 1) {
3959         Error(RegLoc, "non-contiguous register range");
3960         return MatchOperand_ParseFail;
3961       }
3962       ++Reg;
3963       Count += 2;
3964       // Parse the lane specifier if present.
3965       VectorLaneTy NextLaneKind;
3966       unsigned NextLaneIndex;
3967       SMLoc LaneLoc = Parser.getTok().getLoc();
3968       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3969           MatchOperand_Success)
3970         return MatchOperand_ParseFail;
3971       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3972         Error(LaneLoc, "mismatched lane index in register list");
3973         return MatchOperand_ParseFail;
3974       }
3975       continue;
3976     }
3977     // Normal D register.
3978     // Figure out the register spacing (single or double) of the list if
3979     // we don't know it already.
3980     if (!Spacing)
3981       Spacing = 1 + (Reg == OldReg + 2);
3982 
3983     // Just check that it's contiguous and keep going.
3984     if (Reg != OldReg + Spacing) {
3985       Error(RegLoc, "non-contiguous register range");
3986       return MatchOperand_ParseFail;
3987     }
3988     ++Count;
3989     // Parse the lane specifier if present.
3990     VectorLaneTy NextLaneKind;
3991     unsigned NextLaneIndex;
3992     SMLoc EndLoc = Parser.getTok().getLoc();
3993     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3994       return MatchOperand_ParseFail;
3995     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3996       Error(EndLoc, "mismatched lane index in register list");
3997       return MatchOperand_ParseFail;
3998     }
3999   }
4000 
4001   if (Parser.getTok().isNot(AsmToken::RCurly)) {
4002     Error(Parser.getTok().getLoc(), "'}' expected");
4003     return MatchOperand_ParseFail;
4004   }
4005   E = Parser.getTok().getEndLoc();
4006   Parser.Lex(); // Eat '}' token.
4007 
4008   switch (LaneKind) {
4009   case NoLanes:
4010     // Two-register operands have been converted to the
4011     // composite register classes.
4012     if (Count == 2) {
4013       const MCRegisterClass *RC = (Spacing == 1) ?
4014         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4015         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4016       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4017     }
4018 
4019     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
4020                                                     (Spacing == 2), S, E));
4021     break;
4022   case AllLanes:
4023     // Two-register operands have been converted to the
4024     // composite register classes.
4025     if (Count == 2) {
4026       const MCRegisterClass *RC = (Spacing == 1) ?
4027         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4028         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4029       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4030     }
4031     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
4032                                                             (Spacing == 2),
4033                                                             S, E));
4034     break;
4035   case IndexedLane:
4036     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4037                                                            LaneIndex,
4038                                                            (Spacing == 2),
4039                                                            S, E));
4040     break;
4041   }
4042   return MatchOperand_Success;
4043 }
4044 
4045 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4046 OperandMatchResultTy
4047 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4048   MCAsmParser &Parser = getParser();
4049   SMLoc S = Parser.getTok().getLoc();
4050   const AsmToken &Tok = Parser.getTok();
4051   unsigned Opt;
4052 
4053   if (Tok.is(AsmToken::Identifier)) {
4054     StringRef OptStr = Tok.getString();
4055 
4056     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4057       .Case("sy",    ARM_MB::SY)
4058       .Case("st",    ARM_MB::ST)
4059       .Case("ld",    ARM_MB::LD)
4060       .Case("sh",    ARM_MB::ISH)
4061       .Case("ish",   ARM_MB::ISH)
4062       .Case("shst",  ARM_MB::ISHST)
4063       .Case("ishst", ARM_MB::ISHST)
4064       .Case("ishld", ARM_MB::ISHLD)
4065       .Case("nsh",   ARM_MB::NSH)
4066       .Case("un",    ARM_MB::NSH)
4067       .Case("nshst", ARM_MB::NSHST)
4068       .Case("nshld", ARM_MB::NSHLD)
4069       .Case("unst",  ARM_MB::NSHST)
4070       .Case("osh",   ARM_MB::OSH)
4071       .Case("oshst", ARM_MB::OSHST)
4072       .Case("oshld", ARM_MB::OSHLD)
4073       .Default(~0U);
4074 
4075     // ishld, oshld, nshld and ld are only available from ARMv8.
4076     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4077                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4078       Opt = ~0U;
4079 
4080     if (Opt == ~0U)
4081       return MatchOperand_NoMatch;
4082 
4083     Parser.Lex(); // Eat identifier token.
4084   } else if (Tok.is(AsmToken::Hash) ||
4085              Tok.is(AsmToken::Dollar) ||
4086              Tok.is(AsmToken::Integer)) {
4087     if (Parser.getTok().isNot(AsmToken::Integer))
4088       Parser.Lex(); // Eat '#' or '$'.
4089     SMLoc Loc = Parser.getTok().getLoc();
4090 
4091     const MCExpr *MemBarrierID;
4092     if (getParser().parseExpression(MemBarrierID)) {
4093       Error(Loc, "illegal expression");
4094       return MatchOperand_ParseFail;
4095     }
4096 
4097     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4098     if (!CE) {
4099       Error(Loc, "constant expression expected");
4100       return MatchOperand_ParseFail;
4101     }
4102 
4103     int Val = CE->getValue();
4104     if (Val & ~0xf) {
4105       Error(Loc, "immediate value out of range");
4106       return MatchOperand_ParseFail;
4107     }
4108 
4109     Opt = ARM_MB::RESERVED_0 + Val;
4110   } else
4111     return MatchOperand_ParseFail;
4112 
4113   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4114   return MatchOperand_Success;
4115 }
4116 
4117 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4118 OperandMatchResultTy
4119 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4120   MCAsmParser &Parser = getParser();
4121   SMLoc S = Parser.getTok().getLoc();
4122   const AsmToken &Tok = Parser.getTok();
4123   unsigned Opt;
4124 
4125   if (Tok.is(AsmToken::Identifier)) {
4126     StringRef OptStr = Tok.getString();
4127 
4128     if (OptStr.equals_lower("sy"))
4129       Opt = ARM_ISB::SY;
4130     else
4131       return MatchOperand_NoMatch;
4132 
4133     Parser.Lex(); // Eat identifier token.
4134   } else if (Tok.is(AsmToken::Hash) ||
4135              Tok.is(AsmToken::Dollar) ||
4136              Tok.is(AsmToken::Integer)) {
4137     if (Parser.getTok().isNot(AsmToken::Integer))
4138       Parser.Lex(); // Eat '#' or '$'.
4139     SMLoc Loc = Parser.getTok().getLoc();
4140 
4141     const MCExpr *ISBarrierID;
4142     if (getParser().parseExpression(ISBarrierID)) {
4143       Error(Loc, "illegal expression");
4144       return MatchOperand_ParseFail;
4145     }
4146 
4147     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4148     if (!CE) {
4149       Error(Loc, "constant expression expected");
4150       return MatchOperand_ParseFail;
4151     }
4152 
4153     int Val = CE->getValue();
4154     if (Val & ~0xf) {
4155       Error(Loc, "immediate value out of range");
4156       return MatchOperand_ParseFail;
4157     }
4158 
4159     Opt = ARM_ISB::RESERVED_0 + Val;
4160   } else
4161     return MatchOperand_ParseFail;
4162 
4163   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4164           (ARM_ISB::InstSyncBOpt)Opt, S));
4165   return MatchOperand_Success;
4166 }
4167 
4168 
4169 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4170 OperandMatchResultTy
4171 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4172   MCAsmParser &Parser = getParser();
4173   SMLoc S = Parser.getTok().getLoc();
4174   const AsmToken &Tok = Parser.getTok();
4175   if (!Tok.is(AsmToken::Identifier))
4176     return MatchOperand_NoMatch;
4177   StringRef IFlagsStr = Tok.getString();
4178 
4179   // An iflags string of "none" is interpreted to mean that none of the AIF
4180   // bits are set.  Not a terribly useful instruction, but a valid encoding.
4181   unsigned IFlags = 0;
4182   if (IFlagsStr != "none") {
4183         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4184       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
4185         .Case("a", ARM_PROC::A)
4186         .Case("i", ARM_PROC::I)
4187         .Case("f", ARM_PROC::F)
4188         .Default(~0U);
4189 
4190       // If some specific iflag is already set, it means that some letter is
4191       // present more than once, this is not acceptable.
4192       if (Flag == ~0U || (IFlags & Flag))
4193         return MatchOperand_NoMatch;
4194 
4195       IFlags |= Flag;
4196     }
4197   }
4198 
4199   Parser.Lex(); // Eat identifier token.
4200   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4201   return MatchOperand_Success;
4202 }
4203 
4204 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4205 OperandMatchResultTy
4206 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4207   MCAsmParser &Parser = getParser();
4208   SMLoc S = Parser.getTok().getLoc();
4209   const AsmToken &Tok = Parser.getTok();
4210   if (!Tok.is(AsmToken::Identifier))
4211     return MatchOperand_NoMatch;
4212   StringRef Mask = Tok.getString();
4213 
4214   if (isMClass()) {
4215     // See ARMv6-M 10.1.1
4216     std::string Name = Mask.lower();
4217     unsigned FlagsVal = StringSwitch<unsigned>(Name)
4218       // Note: in the documentation:
4219       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
4220       //  for MSR APSR_nzcvq.
4221       // but we do make it an alias here.  This is so to get the "mask encoding"
4222       // bits correct on MSR APSR writes.
4223       //
4224       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
4225       // should really only be allowed when writing a special register.  Note
4226       // they get dropped in the MRS instruction reading a special register as
4227       // the SYSm field is only 8 bits.
4228       .Case("apsr", 0x800)
4229       .Case("apsr_nzcvq", 0x800)
4230       .Case("apsr_g", 0x400)
4231       .Case("apsr_nzcvqg", 0xc00)
4232       .Case("iapsr", 0x801)
4233       .Case("iapsr_nzcvq", 0x801)
4234       .Case("iapsr_g", 0x401)
4235       .Case("iapsr_nzcvqg", 0xc01)
4236       .Case("eapsr", 0x802)
4237       .Case("eapsr_nzcvq", 0x802)
4238       .Case("eapsr_g", 0x402)
4239       .Case("eapsr_nzcvqg", 0xc02)
4240       .Case("xpsr", 0x803)
4241       .Case("xpsr_nzcvq", 0x803)
4242       .Case("xpsr_g", 0x403)
4243       .Case("xpsr_nzcvqg", 0xc03)
4244       .Case("ipsr", 0x805)
4245       .Case("epsr", 0x806)
4246       .Case("iepsr", 0x807)
4247       .Case("msp", 0x808)
4248       .Case("psp", 0x809)
4249       .Case("primask", 0x810)
4250       .Case("basepri", 0x811)
4251       .Case("basepri_max", 0x812)
4252       .Case("faultmask", 0x813)
4253       .Case("control", 0x814)
4254       .Case("msplim", 0x80a)
4255       .Case("psplim", 0x80b)
4256       .Case("msp_ns", 0x888)
4257       .Case("psp_ns", 0x889)
4258       .Case("msplim_ns", 0x88a)
4259       .Case("psplim_ns", 0x88b)
4260       .Case("primask_ns", 0x890)
4261       .Case("basepri_ns", 0x891)
4262       .Case("basepri_max_ns", 0x892)
4263       .Case("faultmask_ns", 0x893)
4264       .Case("control_ns", 0x894)
4265       .Case("sp_ns", 0x898)
4266       .Default(~0U);
4267 
4268     if (FlagsVal == ~0U)
4269       return MatchOperand_NoMatch;
4270 
4271     if (!hasDSP() && (FlagsVal & 0x400))
4272       // The _g and _nzcvqg versions are only valid if the DSP extension is
4273       // available.
4274       return MatchOperand_NoMatch;
4275 
4276     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4277       // basepri, basepri_max and faultmask only valid for V7m.
4278       return MatchOperand_NoMatch;
4279 
4280     if (!has8MSecExt() && (FlagsVal == 0x80a || FlagsVal == 0x80b ||
4281                              (FlagsVal > 0x814 && FlagsVal < 0xc00)))
4282       return MatchOperand_NoMatch;
4283 
4284     if (!hasV8MMainline() && (FlagsVal == 0x88a || FlagsVal == 0x88b ||
4285                               (FlagsVal > 0x890 && FlagsVal <= 0x893)))
4286       return MatchOperand_NoMatch;
4287 
4288     Parser.Lex(); // Eat identifier token.
4289     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4290     return MatchOperand_Success;
4291   }
4292 
4293   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4294   size_t Start = 0, Next = Mask.find('_');
4295   StringRef Flags = "";
4296   std::string SpecReg = Mask.slice(Start, Next).lower();
4297   if (Next != StringRef::npos)
4298     Flags = Mask.slice(Next+1, Mask.size());
4299 
4300   // FlagsVal contains the complete mask:
4301   // 3-0: Mask
4302   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4303   unsigned FlagsVal = 0;
4304 
4305   if (SpecReg == "apsr") {
4306     FlagsVal = StringSwitch<unsigned>(Flags)
4307     .Case("nzcvq",  0x8) // same as CPSR_f
4308     .Case("g",      0x4) // same as CPSR_s
4309     .Case("nzcvqg", 0xc) // same as CPSR_fs
4310     .Default(~0U);
4311 
4312     if (FlagsVal == ~0U) {
4313       if (!Flags.empty())
4314         return MatchOperand_NoMatch;
4315       else
4316         FlagsVal = 8; // No flag
4317     }
4318   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4319     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4320     if (Flags == "all" || Flags == "")
4321       Flags = "fc";
4322     for (int i = 0, e = Flags.size(); i != e; ++i) {
4323       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4324       .Case("c", 1)
4325       .Case("x", 2)
4326       .Case("s", 4)
4327       .Case("f", 8)
4328       .Default(~0U);
4329 
4330       // If some specific flag is already set, it means that some letter is
4331       // present more than once, this is not acceptable.
4332       if (FlagsVal == ~0U || (FlagsVal & Flag))
4333         return MatchOperand_NoMatch;
4334       FlagsVal |= Flag;
4335     }
4336   } else // No match for special register.
4337     return MatchOperand_NoMatch;
4338 
4339   // Special register without flags is NOT equivalent to "fc" flags.
4340   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
4341   // two lines would enable gas compatibility at the expense of breaking
4342   // round-tripping.
4343   //
4344   // if (!FlagsVal)
4345   //  FlagsVal = 0x9;
4346 
4347   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4348   if (SpecReg == "spsr")
4349     FlagsVal |= 16;
4350 
4351   Parser.Lex(); // Eat identifier token.
4352   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4353   return MatchOperand_Success;
4354 }
4355 
4356 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4357 /// use in the MRS/MSR instructions added to support virtualization.
4358 OperandMatchResultTy
4359 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4360   MCAsmParser &Parser = getParser();
4361   SMLoc S = Parser.getTok().getLoc();
4362   const AsmToken &Tok = Parser.getTok();
4363   if (!Tok.is(AsmToken::Identifier))
4364     return MatchOperand_NoMatch;
4365   StringRef RegName = Tok.getString();
4366 
4367   // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4368   // and bit 5 is R.
4369   unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4370                           .Case("r8_usr", 0x00)
4371                           .Case("r9_usr", 0x01)
4372                           .Case("r10_usr", 0x02)
4373                           .Case("r11_usr", 0x03)
4374                           .Case("r12_usr", 0x04)
4375                           .Case("sp_usr", 0x05)
4376                           .Case("lr_usr", 0x06)
4377                           .Case("r8_fiq", 0x08)
4378                           .Case("r9_fiq", 0x09)
4379                           .Case("r10_fiq", 0x0a)
4380                           .Case("r11_fiq", 0x0b)
4381                           .Case("r12_fiq", 0x0c)
4382                           .Case("sp_fiq", 0x0d)
4383                           .Case("lr_fiq", 0x0e)
4384                           .Case("lr_irq", 0x10)
4385                           .Case("sp_irq", 0x11)
4386                           .Case("lr_svc", 0x12)
4387                           .Case("sp_svc", 0x13)
4388                           .Case("lr_abt", 0x14)
4389                           .Case("sp_abt", 0x15)
4390                           .Case("lr_und", 0x16)
4391                           .Case("sp_und", 0x17)
4392                           .Case("lr_mon", 0x1c)
4393                           .Case("sp_mon", 0x1d)
4394                           .Case("elr_hyp", 0x1e)
4395                           .Case("sp_hyp", 0x1f)
4396                           .Case("spsr_fiq", 0x2e)
4397                           .Case("spsr_irq", 0x30)
4398                           .Case("spsr_svc", 0x32)
4399                           .Case("spsr_abt", 0x34)
4400                           .Case("spsr_und", 0x36)
4401                           .Case("spsr_mon", 0x3c)
4402                           .Case("spsr_hyp", 0x3e)
4403                           .Default(~0U);
4404 
4405   if (Encoding == ~0U)
4406     return MatchOperand_NoMatch;
4407 
4408   Parser.Lex(); // Eat identifier token.
4409   Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4410   return MatchOperand_Success;
4411 }
4412 
4413 OperandMatchResultTy
4414 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4415                           int High) {
4416   MCAsmParser &Parser = getParser();
4417   const AsmToken &Tok = Parser.getTok();
4418   if (Tok.isNot(AsmToken::Identifier)) {
4419     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4420     return MatchOperand_ParseFail;
4421   }
4422   StringRef ShiftName = Tok.getString();
4423   std::string LowerOp = Op.lower();
4424   std::string UpperOp = Op.upper();
4425   if (ShiftName != LowerOp && ShiftName != UpperOp) {
4426     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4427     return MatchOperand_ParseFail;
4428   }
4429   Parser.Lex(); // Eat shift type token.
4430 
4431   // There must be a '#' and a shift amount.
4432   if (Parser.getTok().isNot(AsmToken::Hash) &&
4433       Parser.getTok().isNot(AsmToken::Dollar)) {
4434     Error(Parser.getTok().getLoc(), "'#' expected");
4435     return MatchOperand_ParseFail;
4436   }
4437   Parser.Lex(); // Eat hash token.
4438 
4439   const MCExpr *ShiftAmount;
4440   SMLoc Loc = Parser.getTok().getLoc();
4441   SMLoc EndLoc;
4442   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4443     Error(Loc, "illegal expression");
4444     return MatchOperand_ParseFail;
4445   }
4446   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4447   if (!CE) {
4448     Error(Loc, "constant expression expected");
4449     return MatchOperand_ParseFail;
4450   }
4451   int Val = CE->getValue();
4452   if (Val < Low || Val > High) {
4453     Error(Loc, "immediate value out of range");
4454     return MatchOperand_ParseFail;
4455   }
4456 
4457   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4458 
4459   return MatchOperand_Success;
4460 }
4461 
4462 OperandMatchResultTy
4463 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4464   MCAsmParser &Parser = getParser();
4465   const AsmToken &Tok = Parser.getTok();
4466   SMLoc S = Tok.getLoc();
4467   if (Tok.isNot(AsmToken::Identifier)) {
4468     Error(S, "'be' or 'le' operand expected");
4469     return MatchOperand_ParseFail;
4470   }
4471   int Val = StringSwitch<int>(Tok.getString().lower())
4472     .Case("be", 1)
4473     .Case("le", 0)
4474     .Default(-1);
4475   Parser.Lex(); // Eat the token.
4476 
4477   if (Val == -1) {
4478     Error(S, "'be' or 'le' operand expected");
4479     return MatchOperand_ParseFail;
4480   }
4481   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4482                                                                   getContext()),
4483                                            S, Tok.getEndLoc()));
4484   return MatchOperand_Success;
4485 }
4486 
4487 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4488 /// instructions. Legal values are:
4489 ///     lsl #n  'n' in [0,31]
4490 ///     asr #n  'n' in [1,32]
4491 ///             n == 32 encoded as n == 0.
4492 OperandMatchResultTy
4493 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4494   MCAsmParser &Parser = getParser();
4495   const AsmToken &Tok = Parser.getTok();
4496   SMLoc S = Tok.getLoc();
4497   if (Tok.isNot(AsmToken::Identifier)) {
4498     Error(S, "shift operator 'asr' or 'lsl' expected");
4499     return MatchOperand_ParseFail;
4500   }
4501   StringRef ShiftName = Tok.getString();
4502   bool isASR;
4503   if (ShiftName == "lsl" || ShiftName == "LSL")
4504     isASR = false;
4505   else if (ShiftName == "asr" || ShiftName == "ASR")
4506     isASR = true;
4507   else {
4508     Error(S, "shift operator 'asr' or 'lsl' expected");
4509     return MatchOperand_ParseFail;
4510   }
4511   Parser.Lex(); // Eat the operator.
4512 
4513   // A '#' and a shift amount.
4514   if (Parser.getTok().isNot(AsmToken::Hash) &&
4515       Parser.getTok().isNot(AsmToken::Dollar)) {
4516     Error(Parser.getTok().getLoc(), "'#' expected");
4517     return MatchOperand_ParseFail;
4518   }
4519   Parser.Lex(); // Eat hash token.
4520   SMLoc ExLoc = Parser.getTok().getLoc();
4521 
4522   const MCExpr *ShiftAmount;
4523   SMLoc EndLoc;
4524   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4525     Error(ExLoc, "malformed shift expression");
4526     return MatchOperand_ParseFail;
4527   }
4528   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4529   if (!CE) {
4530     Error(ExLoc, "shift amount must be an immediate");
4531     return MatchOperand_ParseFail;
4532   }
4533 
4534   int64_t Val = CE->getValue();
4535   if (isASR) {
4536     // Shift amount must be in [1,32]
4537     if (Val < 1 || Val > 32) {
4538       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4539       return MatchOperand_ParseFail;
4540     }
4541     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4542     if (isThumb() && Val == 32) {
4543       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4544       return MatchOperand_ParseFail;
4545     }
4546     if (Val == 32) Val = 0;
4547   } else {
4548     // Shift amount must be in [1,32]
4549     if (Val < 0 || Val > 31) {
4550       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4551       return MatchOperand_ParseFail;
4552     }
4553   }
4554 
4555   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4556 
4557   return MatchOperand_Success;
4558 }
4559 
4560 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4561 /// of instructions. Legal values are:
4562 ///     ror #n  'n' in {0, 8, 16, 24}
4563 OperandMatchResultTy
4564 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4565   MCAsmParser &Parser = getParser();
4566   const AsmToken &Tok = Parser.getTok();
4567   SMLoc S = Tok.getLoc();
4568   if (Tok.isNot(AsmToken::Identifier))
4569     return MatchOperand_NoMatch;
4570   StringRef ShiftName = Tok.getString();
4571   if (ShiftName != "ror" && ShiftName != "ROR")
4572     return MatchOperand_NoMatch;
4573   Parser.Lex(); // Eat the operator.
4574 
4575   // A '#' and a rotate amount.
4576   if (Parser.getTok().isNot(AsmToken::Hash) &&
4577       Parser.getTok().isNot(AsmToken::Dollar)) {
4578     Error(Parser.getTok().getLoc(), "'#' expected");
4579     return MatchOperand_ParseFail;
4580   }
4581   Parser.Lex(); // Eat hash token.
4582   SMLoc ExLoc = Parser.getTok().getLoc();
4583 
4584   const MCExpr *ShiftAmount;
4585   SMLoc EndLoc;
4586   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4587     Error(ExLoc, "malformed rotate expression");
4588     return MatchOperand_ParseFail;
4589   }
4590   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4591   if (!CE) {
4592     Error(ExLoc, "rotate amount must be an immediate");
4593     return MatchOperand_ParseFail;
4594   }
4595 
4596   int64_t Val = CE->getValue();
4597   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4598   // normally, zero is represented in asm by omitting the rotate operand
4599   // entirely.
4600   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4601     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4602     return MatchOperand_ParseFail;
4603   }
4604 
4605   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4606 
4607   return MatchOperand_Success;
4608 }
4609 
4610 OperandMatchResultTy
4611 ARMAsmParser::parseModImm(OperandVector &Operands) {
4612   MCAsmParser &Parser = getParser();
4613   MCAsmLexer &Lexer = getLexer();
4614   int64_t Imm1, Imm2;
4615 
4616   SMLoc S = Parser.getTok().getLoc();
4617 
4618   // 1) A mod_imm operand can appear in the place of a register name:
4619   //   add r0, #mod_imm
4620   //   add r0, r0, #mod_imm
4621   // to correctly handle the latter, we bail out as soon as we see an
4622   // identifier.
4623   //
4624   // 2) Similarly, we do not want to parse into complex operands:
4625   //   mov r0, #mod_imm
4626   //   mov r0, :lower16:(_foo)
4627   if (Parser.getTok().is(AsmToken::Identifier) ||
4628       Parser.getTok().is(AsmToken::Colon))
4629     return MatchOperand_NoMatch;
4630 
4631   // Hash (dollar) is optional as per the ARMARM
4632   if (Parser.getTok().is(AsmToken::Hash) ||
4633       Parser.getTok().is(AsmToken::Dollar)) {
4634     // Avoid parsing into complex operands (#:)
4635     if (Lexer.peekTok().is(AsmToken::Colon))
4636       return MatchOperand_NoMatch;
4637 
4638     // Eat the hash (dollar)
4639     Parser.Lex();
4640   }
4641 
4642   SMLoc Sx1, Ex1;
4643   Sx1 = Parser.getTok().getLoc();
4644   const MCExpr *Imm1Exp;
4645   if (getParser().parseExpression(Imm1Exp, Ex1)) {
4646     Error(Sx1, "malformed expression");
4647     return MatchOperand_ParseFail;
4648   }
4649 
4650   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4651 
4652   if (CE) {
4653     // Immediate must fit within 32-bits
4654     Imm1 = CE->getValue();
4655     int Enc = ARM_AM::getSOImmVal(Imm1);
4656     if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4657       // We have a match!
4658       Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4659                                                   (Enc & 0xF00) >> 7,
4660                                                   Sx1, Ex1));
4661       return MatchOperand_Success;
4662     }
4663 
4664     // We have parsed an immediate which is not for us, fallback to a plain
4665     // immediate. This can happen for instruction aliases. For an example,
4666     // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4667     // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4668     // instruction with a mod_imm operand. The alias is defined such that the
4669     // parser method is shared, that's why we have to do this here.
4670     if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4671       Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4672       return MatchOperand_Success;
4673     }
4674   } else {
4675     // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4676     // MCFixup). Fallback to a plain immediate.
4677     Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4678     return MatchOperand_Success;
4679   }
4680 
4681   // From this point onward, we expect the input to be a (#bits, #rot) pair
4682   if (Parser.getTok().isNot(AsmToken::Comma)) {
4683     Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4684     return MatchOperand_ParseFail;
4685   }
4686 
4687   if (Imm1 & ~0xFF) {
4688     Error(Sx1, "immediate operand must a number in the range [0, 255]");
4689     return MatchOperand_ParseFail;
4690   }
4691 
4692   // Eat the comma
4693   Parser.Lex();
4694 
4695   // Repeat for #rot
4696   SMLoc Sx2, Ex2;
4697   Sx2 = Parser.getTok().getLoc();
4698 
4699   // Eat the optional hash (dollar)
4700   if (Parser.getTok().is(AsmToken::Hash) ||
4701       Parser.getTok().is(AsmToken::Dollar))
4702     Parser.Lex();
4703 
4704   const MCExpr *Imm2Exp;
4705   if (getParser().parseExpression(Imm2Exp, Ex2)) {
4706     Error(Sx2, "malformed expression");
4707     return MatchOperand_ParseFail;
4708   }
4709 
4710   CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4711 
4712   if (CE) {
4713     Imm2 = CE->getValue();
4714     if (!(Imm2 & ~0x1E)) {
4715       // We have a match!
4716       Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4717       return MatchOperand_Success;
4718     }
4719     Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4720     return MatchOperand_ParseFail;
4721   } else {
4722     Error(Sx2, "constant expression expected");
4723     return MatchOperand_ParseFail;
4724   }
4725 }
4726 
4727 OperandMatchResultTy
4728 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4729   MCAsmParser &Parser = getParser();
4730   SMLoc S = Parser.getTok().getLoc();
4731   // The bitfield descriptor is really two operands, the LSB and the width.
4732   if (Parser.getTok().isNot(AsmToken::Hash) &&
4733       Parser.getTok().isNot(AsmToken::Dollar)) {
4734     Error(Parser.getTok().getLoc(), "'#' expected");
4735     return MatchOperand_ParseFail;
4736   }
4737   Parser.Lex(); // Eat hash token.
4738 
4739   const MCExpr *LSBExpr;
4740   SMLoc E = Parser.getTok().getLoc();
4741   if (getParser().parseExpression(LSBExpr)) {
4742     Error(E, "malformed immediate expression");
4743     return MatchOperand_ParseFail;
4744   }
4745   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4746   if (!CE) {
4747     Error(E, "'lsb' operand must be an immediate");
4748     return MatchOperand_ParseFail;
4749   }
4750 
4751   int64_t LSB = CE->getValue();
4752   // The LSB must be in the range [0,31]
4753   if (LSB < 0 || LSB > 31) {
4754     Error(E, "'lsb' operand must be in the range [0,31]");
4755     return MatchOperand_ParseFail;
4756   }
4757   E = Parser.getTok().getLoc();
4758 
4759   // Expect another immediate operand.
4760   if (Parser.getTok().isNot(AsmToken::Comma)) {
4761     Error(Parser.getTok().getLoc(), "too few operands");
4762     return MatchOperand_ParseFail;
4763   }
4764   Parser.Lex(); // Eat hash token.
4765   if (Parser.getTok().isNot(AsmToken::Hash) &&
4766       Parser.getTok().isNot(AsmToken::Dollar)) {
4767     Error(Parser.getTok().getLoc(), "'#' expected");
4768     return MatchOperand_ParseFail;
4769   }
4770   Parser.Lex(); // Eat hash token.
4771 
4772   const MCExpr *WidthExpr;
4773   SMLoc EndLoc;
4774   if (getParser().parseExpression(WidthExpr, EndLoc)) {
4775     Error(E, "malformed immediate expression");
4776     return MatchOperand_ParseFail;
4777   }
4778   CE = dyn_cast<MCConstantExpr>(WidthExpr);
4779   if (!CE) {
4780     Error(E, "'width' operand must be an immediate");
4781     return MatchOperand_ParseFail;
4782   }
4783 
4784   int64_t Width = CE->getValue();
4785   // The LSB must be in the range [1,32-lsb]
4786   if (Width < 1 || Width > 32 - LSB) {
4787     Error(E, "'width' operand must be in the range [1,32-lsb]");
4788     return MatchOperand_ParseFail;
4789   }
4790 
4791   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4792 
4793   return MatchOperand_Success;
4794 }
4795 
4796 OperandMatchResultTy
4797 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4798   // Check for a post-index addressing register operand. Specifically:
4799   // postidx_reg := '+' register {, shift}
4800   //              | '-' register {, shift}
4801   //              | register {, shift}
4802 
4803   // This method must return MatchOperand_NoMatch without consuming any tokens
4804   // in the case where there is no match, as other alternatives take other
4805   // parse methods.
4806   MCAsmParser &Parser = getParser();
4807   AsmToken Tok = Parser.getTok();
4808   SMLoc S = Tok.getLoc();
4809   bool haveEaten = false;
4810   bool isAdd = true;
4811   if (Tok.is(AsmToken::Plus)) {
4812     Parser.Lex(); // Eat the '+' token.
4813     haveEaten = true;
4814   } else if (Tok.is(AsmToken::Minus)) {
4815     Parser.Lex(); // Eat the '-' token.
4816     isAdd = false;
4817     haveEaten = true;
4818   }
4819 
4820   SMLoc E = Parser.getTok().getEndLoc();
4821   int Reg = tryParseRegister();
4822   if (Reg == -1) {
4823     if (!haveEaten)
4824       return MatchOperand_NoMatch;
4825     Error(Parser.getTok().getLoc(), "register expected");
4826     return MatchOperand_ParseFail;
4827   }
4828 
4829   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4830   unsigned ShiftImm = 0;
4831   if (Parser.getTok().is(AsmToken::Comma)) {
4832     Parser.Lex(); // Eat the ','.
4833     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4834       return MatchOperand_ParseFail;
4835 
4836     // FIXME: Only approximates end...may include intervening whitespace.
4837     E = Parser.getTok().getLoc();
4838   }
4839 
4840   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4841                                                   ShiftImm, S, E));
4842 
4843   return MatchOperand_Success;
4844 }
4845 
4846 OperandMatchResultTy
4847 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4848   // Check for a post-index addressing register operand. Specifically:
4849   // am3offset := '+' register
4850   //              | '-' register
4851   //              | register
4852   //              | # imm
4853   //              | # + imm
4854   //              | # - imm
4855 
4856   // This method must return MatchOperand_NoMatch without consuming any tokens
4857   // in the case where there is no match, as other alternatives take other
4858   // parse methods.
4859   MCAsmParser &Parser = getParser();
4860   AsmToken Tok = Parser.getTok();
4861   SMLoc S = Tok.getLoc();
4862 
4863   // Do immediates first, as we always parse those if we have a '#'.
4864   if (Parser.getTok().is(AsmToken::Hash) ||
4865       Parser.getTok().is(AsmToken::Dollar)) {
4866     Parser.Lex(); // Eat '#' or '$'.
4867     // Explicitly look for a '-', as we need to encode negative zero
4868     // differently.
4869     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4870     const MCExpr *Offset;
4871     SMLoc E;
4872     if (getParser().parseExpression(Offset, E))
4873       return MatchOperand_ParseFail;
4874     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4875     if (!CE) {
4876       Error(S, "constant expression expected");
4877       return MatchOperand_ParseFail;
4878     }
4879     // Negative zero is encoded as the flag value INT32_MIN.
4880     int32_t Val = CE->getValue();
4881     if (isNegative && Val == 0)
4882       Val = INT32_MIN;
4883 
4884     Operands.push_back(
4885       ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4886 
4887     return MatchOperand_Success;
4888   }
4889 
4890 
4891   bool haveEaten = false;
4892   bool isAdd = true;
4893   if (Tok.is(AsmToken::Plus)) {
4894     Parser.Lex(); // Eat the '+' token.
4895     haveEaten = true;
4896   } else if (Tok.is(AsmToken::Minus)) {
4897     Parser.Lex(); // Eat the '-' token.
4898     isAdd = false;
4899     haveEaten = true;
4900   }
4901 
4902   Tok = Parser.getTok();
4903   int Reg = tryParseRegister();
4904   if (Reg == -1) {
4905     if (!haveEaten)
4906       return MatchOperand_NoMatch;
4907     Error(Tok.getLoc(), "register expected");
4908     return MatchOperand_ParseFail;
4909   }
4910 
4911   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4912                                                   0, S, Tok.getEndLoc()));
4913 
4914   return MatchOperand_Success;
4915 }
4916 
4917 /// Convert parsed operands to MCInst.  Needed here because this instruction
4918 /// only has two register operands, but multiplication is commutative so
4919 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4920 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4921                                     const OperandVector &Operands) {
4922   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4923   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4924   // If we have a three-operand form, make sure to set Rn to be the operand
4925   // that isn't the same as Rd.
4926   unsigned RegOp = 4;
4927   if (Operands.size() == 6 &&
4928       ((ARMOperand &)*Operands[4]).getReg() ==
4929           ((ARMOperand &)*Operands[3]).getReg())
4930     RegOp = 5;
4931   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4932   Inst.addOperand(Inst.getOperand(0));
4933   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4934 }
4935 
4936 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4937                                     const OperandVector &Operands) {
4938   int CondOp = -1, ImmOp = -1;
4939   switch(Inst.getOpcode()) {
4940     case ARM::tB:
4941     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4942 
4943     case ARM::t2B:
4944     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4945 
4946     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4947   }
4948   // first decide whether or not the branch should be conditional
4949   // by looking at it's location relative to an IT block
4950   if(inITBlock()) {
4951     // inside an IT block we cannot have any conditional branches. any
4952     // such instructions needs to be converted to unconditional form
4953     switch(Inst.getOpcode()) {
4954       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4955       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4956     }
4957   } else {
4958     // outside IT blocks we can only have unconditional branches with AL
4959     // condition code or conditional branches with non-AL condition code
4960     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4961     switch(Inst.getOpcode()) {
4962       case ARM::tB:
4963       case ARM::tBcc:
4964         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4965         break;
4966       case ARM::t2B:
4967       case ARM::t2Bcc:
4968         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4969         break;
4970     }
4971   }
4972 
4973   // now decide on encoding size based on branch target range
4974   switch(Inst.getOpcode()) {
4975     // classify tB as either t2B or t1B based on range of immediate operand
4976     case ARM::tB: {
4977       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4978       if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
4979         Inst.setOpcode(ARM::t2B);
4980       break;
4981     }
4982     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4983     case ARM::tBcc: {
4984       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4985       if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
4986         Inst.setOpcode(ARM::t2Bcc);
4987       break;
4988     }
4989   }
4990   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4991   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4992 }
4993 
4994 /// Parse an ARM memory expression, return false if successful else return true
4995 /// or an error.  The first token must be a '[' when called.
4996 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4997   MCAsmParser &Parser = getParser();
4998   SMLoc S, E;
4999   if (Parser.getTok().isNot(AsmToken::LBrac))
5000     return TokError("Token is not a Left Bracket");
5001   S = Parser.getTok().getLoc();
5002   Parser.Lex(); // Eat left bracket token.
5003 
5004   const AsmToken &BaseRegTok = Parser.getTok();
5005   int BaseRegNum = tryParseRegister();
5006   if (BaseRegNum == -1)
5007     return Error(BaseRegTok.getLoc(), "register expected");
5008 
5009   // The next token must either be a comma, a colon or a closing bracket.
5010   const AsmToken &Tok = Parser.getTok();
5011   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5012       !Tok.is(AsmToken::RBrac))
5013     return Error(Tok.getLoc(), "malformed memory operand");
5014 
5015   if (Tok.is(AsmToken::RBrac)) {
5016     E = Tok.getEndLoc();
5017     Parser.Lex(); // Eat right bracket token.
5018 
5019     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5020                                              ARM_AM::no_shift, 0, 0, false,
5021                                              S, E));
5022 
5023     // If there's a pre-indexing writeback marker, '!', just add it as a token
5024     // operand. It's rather odd, but syntactically valid.
5025     if (Parser.getTok().is(AsmToken::Exclaim)) {
5026       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5027       Parser.Lex(); // Eat the '!'.
5028     }
5029 
5030     return false;
5031   }
5032 
5033   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
5034          "Lost colon or comma in memory operand?!");
5035   if (Tok.is(AsmToken::Comma)) {
5036     Parser.Lex(); // Eat the comma.
5037   }
5038 
5039   // If we have a ':', it's an alignment specifier.
5040   if (Parser.getTok().is(AsmToken::Colon)) {
5041     Parser.Lex(); // Eat the ':'.
5042     E = Parser.getTok().getLoc();
5043     SMLoc AlignmentLoc = Tok.getLoc();
5044 
5045     const MCExpr *Expr;
5046     if (getParser().parseExpression(Expr))
5047      return true;
5048 
5049     // The expression has to be a constant. Memory references with relocations
5050     // don't come through here, as they use the <label> forms of the relevant
5051     // instructions.
5052     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5053     if (!CE)
5054       return Error (E, "constant expression expected");
5055 
5056     unsigned Align = 0;
5057     switch (CE->getValue()) {
5058     default:
5059       return Error(E,
5060                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5061     case 16:  Align = 2; break;
5062     case 32:  Align = 4; break;
5063     case 64:  Align = 8; break;
5064     case 128: Align = 16; break;
5065     case 256: Align = 32; break;
5066     }
5067 
5068     // Now we should have the closing ']'
5069     if (Parser.getTok().isNot(AsmToken::RBrac))
5070       return Error(Parser.getTok().getLoc(), "']' expected");
5071     E = Parser.getTok().getEndLoc();
5072     Parser.Lex(); // Eat right bracket token.
5073 
5074     // Don't worry about range checking the value here. That's handled by
5075     // the is*() predicates.
5076     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5077                                              ARM_AM::no_shift, 0, Align,
5078                                              false, S, E, AlignmentLoc));
5079 
5080     // If there's a pre-indexing writeback marker, '!', just add it as a token
5081     // operand.
5082     if (Parser.getTok().is(AsmToken::Exclaim)) {
5083       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5084       Parser.Lex(); // Eat the '!'.
5085     }
5086 
5087     return false;
5088   }
5089 
5090   // If we have a '#', it's an immediate offset, else assume it's a register
5091   // offset. Be friendly and also accept a plain integer (without a leading
5092   // hash) for gas compatibility.
5093   if (Parser.getTok().is(AsmToken::Hash) ||
5094       Parser.getTok().is(AsmToken::Dollar) ||
5095       Parser.getTok().is(AsmToken::Integer)) {
5096     if (Parser.getTok().isNot(AsmToken::Integer))
5097       Parser.Lex(); // Eat '#' or '$'.
5098     E = Parser.getTok().getLoc();
5099 
5100     bool isNegative = getParser().getTok().is(AsmToken::Minus);
5101     const MCExpr *Offset;
5102     if (getParser().parseExpression(Offset))
5103      return true;
5104 
5105     // The expression has to be a constant. Memory references with relocations
5106     // don't come through here, as they use the <label> forms of the relevant
5107     // instructions.
5108     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5109     if (!CE)
5110       return Error (E, "constant expression expected");
5111 
5112     // If the constant was #-0, represent it as INT32_MIN.
5113     int32_t Val = CE->getValue();
5114     if (isNegative && Val == 0)
5115       CE = MCConstantExpr::create(INT32_MIN, getContext());
5116 
5117     // Now we should have the closing ']'
5118     if (Parser.getTok().isNot(AsmToken::RBrac))
5119       return Error(Parser.getTok().getLoc(), "']' expected");
5120     E = Parser.getTok().getEndLoc();
5121     Parser.Lex(); // Eat right bracket token.
5122 
5123     // Don't worry about range checking the value here. That's handled by
5124     // the is*() predicates.
5125     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
5126                                              ARM_AM::no_shift, 0, 0,
5127                                              false, S, E));
5128 
5129     // If there's a pre-indexing writeback marker, '!', just add it as a token
5130     // operand.
5131     if (Parser.getTok().is(AsmToken::Exclaim)) {
5132       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5133       Parser.Lex(); // Eat the '!'.
5134     }
5135 
5136     return false;
5137   }
5138 
5139   // The register offset is optionally preceded by a '+' or '-'
5140   bool isNegative = false;
5141   if (Parser.getTok().is(AsmToken::Minus)) {
5142     isNegative = true;
5143     Parser.Lex(); // Eat the '-'.
5144   } else if (Parser.getTok().is(AsmToken::Plus)) {
5145     // Nothing to do.
5146     Parser.Lex(); // Eat the '+'.
5147   }
5148 
5149   E = Parser.getTok().getLoc();
5150   int OffsetRegNum = tryParseRegister();
5151   if (OffsetRegNum == -1)
5152     return Error(E, "register expected");
5153 
5154   // If there's a shift operator, handle it.
5155   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5156   unsigned ShiftImm = 0;
5157   if (Parser.getTok().is(AsmToken::Comma)) {
5158     Parser.Lex(); // Eat the ','.
5159     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5160       return true;
5161   }
5162 
5163   // Now we should have the closing ']'
5164   if (Parser.getTok().isNot(AsmToken::RBrac))
5165     return Error(Parser.getTok().getLoc(), "']' expected");
5166   E = Parser.getTok().getEndLoc();
5167   Parser.Lex(); // Eat right bracket token.
5168 
5169   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
5170                                            ShiftType, ShiftImm, 0, isNegative,
5171                                            S, E));
5172 
5173   // If there's a pre-indexing writeback marker, '!', just add it as a token
5174   // operand.
5175   if (Parser.getTok().is(AsmToken::Exclaim)) {
5176     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5177     Parser.Lex(); // Eat the '!'.
5178   }
5179 
5180   return false;
5181 }
5182 
5183 /// parseMemRegOffsetShift - one of these two:
5184 ///   ( lsl | lsr | asr | ror ) , # shift_amount
5185 ///   rrx
5186 /// return true if it parses a shift otherwise it returns false.
5187 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5188                                           unsigned &Amount) {
5189   MCAsmParser &Parser = getParser();
5190   SMLoc Loc = Parser.getTok().getLoc();
5191   const AsmToken &Tok = Parser.getTok();
5192   if (Tok.isNot(AsmToken::Identifier))
5193     return true;
5194   StringRef ShiftName = Tok.getString();
5195   if (ShiftName == "lsl" || ShiftName == "LSL" ||
5196       ShiftName == "asl" || ShiftName == "ASL")
5197     St = ARM_AM::lsl;
5198   else if (ShiftName == "lsr" || ShiftName == "LSR")
5199     St = ARM_AM::lsr;
5200   else if (ShiftName == "asr" || ShiftName == "ASR")
5201     St = ARM_AM::asr;
5202   else if (ShiftName == "ror" || ShiftName == "ROR")
5203     St = ARM_AM::ror;
5204   else if (ShiftName == "rrx" || ShiftName == "RRX")
5205     St = ARM_AM::rrx;
5206   else
5207     return Error(Loc, "illegal shift operator");
5208   Parser.Lex(); // Eat shift type token.
5209 
5210   // rrx stands alone.
5211   Amount = 0;
5212   if (St != ARM_AM::rrx) {
5213     Loc = Parser.getTok().getLoc();
5214     // A '#' and a shift amount.
5215     const AsmToken &HashTok = Parser.getTok();
5216     if (HashTok.isNot(AsmToken::Hash) &&
5217         HashTok.isNot(AsmToken::Dollar))
5218       return Error(HashTok.getLoc(), "'#' expected");
5219     Parser.Lex(); // Eat hash token.
5220 
5221     const MCExpr *Expr;
5222     if (getParser().parseExpression(Expr))
5223       return true;
5224     // Range check the immediate.
5225     // lsl, ror: 0 <= imm <= 31
5226     // lsr, asr: 0 <= imm <= 32
5227     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5228     if (!CE)
5229       return Error(Loc, "shift amount must be an immediate");
5230     int64_t Imm = CE->getValue();
5231     if (Imm < 0 ||
5232         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5233         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5234       return Error(Loc, "immediate shift value out of range");
5235     // If <ShiftTy> #0, turn it into a no_shift.
5236     if (Imm == 0)
5237       St = ARM_AM::lsl;
5238     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5239     if (Imm == 32)
5240       Imm = 0;
5241     Amount = Imm;
5242   }
5243 
5244   return false;
5245 }
5246 
5247 /// parseFPImm - A floating point immediate expression operand.
5248 OperandMatchResultTy
5249 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5250   MCAsmParser &Parser = getParser();
5251   // Anything that can accept a floating point constant as an operand
5252   // needs to go through here, as the regular parseExpression is
5253   // integer only.
5254   //
5255   // This routine still creates a generic Immediate operand, containing
5256   // a bitcast of the 64-bit floating point value. The various operands
5257   // that accept floats can check whether the value is valid for them
5258   // via the standard is*() predicates.
5259 
5260   SMLoc S = Parser.getTok().getLoc();
5261 
5262   if (Parser.getTok().isNot(AsmToken::Hash) &&
5263       Parser.getTok().isNot(AsmToken::Dollar))
5264     return MatchOperand_NoMatch;
5265 
5266   // Disambiguate the VMOV forms that can accept an FP immediate.
5267   // vmov.f32 <sreg>, #imm
5268   // vmov.f64 <dreg>, #imm
5269   // vmov.f32 <dreg>, #imm  @ vector f32x2
5270   // vmov.f32 <qreg>, #imm  @ vector f32x4
5271   //
5272   // There are also the NEON VMOV instructions which expect an
5273   // integer constant. Make sure we don't try to parse an FPImm
5274   // for these:
5275   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5276   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5277   bool isVmovf = TyOp.isToken() &&
5278                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5279                   TyOp.getToken() == ".f16");
5280   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5281   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5282                                          Mnemonic.getToken() == "fconsts");
5283   if (!(isVmovf || isFconst))
5284     return MatchOperand_NoMatch;
5285 
5286   Parser.Lex(); // Eat '#' or '$'.
5287 
5288   // Handle negation, as that still comes through as a separate token.
5289   bool isNegative = false;
5290   if (Parser.getTok().is(AsmToken::Minus)) {
5291     isNegative = true;
5292     Parser.Lex();
5293   }
5294   const AsmToken &Tok = Parser.getTok();
5295   SMLoc Loc = Tok.getLoc();
5296   if (Tok.is(AsmToken::Real) && isVmovf) {
5297     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
5298     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5299     // If we had a '-' in front, toggle the sign bit.
5300     IntVal ^= (uint64_t)isNegative << 31;
5301     Parser.Lex(); // Eat the token.
5302     Operands.push_back(ARMOperand::CreateImm(
5303           MCConstantExpr::create(IntVal, getContext()),
5304           S, Parser.getTok().getLoc()));
5305     return MatchOperand_Success;
5306   }
5307   // Also handle plain integers. Instructions which allow floating point
5308   // immediates also allow a raw encoded 8-bit value.
5309   if (Tok.is(AsmToken::Integer) && isFconst) {
5310     int64_t Val = Tok.getIntVal();
5311     Parser.Lex(); // Eat the token.
5312     if (Val > 255 || Val < 0) {
5313       Error(Loc, "encoded floating point value out of range");
5314       return MatchOperand_ParseFail;
5315     }
5316     float RealVal = ARM_AM::getFPImmFloat(Val);
5317     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5318 
5319     Operands.push_back(ARMOperand::CreateImm(
5320         MCConstantExpr::create(Val, getContext()), S,
5321         Parser.getTok().getLoc()));
5322     return MatchOperand_Success;
5323   }
5324 
5325   Error(Loc, "invalid floating point immediate");
5326   return MatchOperand_ParseFail;
5327 }
5328 
5329 /// Parse a arm instruction operand.  For now this parses the operand regardless
5330 /// of the mnemonic.
5331 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5332   MCAsmParser &Parser = getParser();
5333   SMLoc S, E;
5334 
5335   // Check if the current operand has a custom associated parser, if so, try to
5336   // custom parse the operand, or fallback to the general approach.
5337   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5338   if (ResTy == MatchOperand_Success)
5339     return false;
5340   // If there wasn't a custom match, try the generic matcher below. Otherwise,
5341   // there was a match, but an error occurred, in which case, just return that
5342   // the operand parsing failed.
5343   if (ResTy == MatchOperand_ParseFail)
5344     return true;
5345 
5346   switch (getLexer().getKind()) {
5347   default:
5348     Error(Parser.getTok().getLoc(), "unexpected token in operand");
5349     return true;
5350   case AsmToken::Identifier: {
5351     // If we've seen a branch mnemonic, the next operand must be a label.  This
5352     // is true even if the label is a register name.  So "br r1" means branch to
5353     // label "r1".
5354     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5355     if (!ExpectLabel) {
5356       if (!tryParseRegisterWithWriteBack(Operands))
5357         return false;
5358       int Res = tryParseShiftRegister(Operands);
5359       if (Res == 0) // success
5360         return false;
5361       else if (Res == -1) // irrecoverable error
5362         return true;
5363       // If this is VMRS, check for the apsr_nzcv operand.
5364       if (Mnemonic == "vmrs" &&
5365           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5366         S = Parser.getTok().getLoc();
5367         Parser.Lex();
5368         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5369         return false;
5370       }
5371     }
5372 
5373     // Fall though for the Identifier case that is not a register or a
5374     // special name.
5375   }
5376   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
5377   case AsmToken::Integer: // things like 1f and 2b as a branch targets
5378   case AsmToken::String:  // quoted label names.
5379   case AsmToken::Dot: {   // . as a branch target
5380     // This was not a register so parse other operands that start with an
5381     // identifier (like labels) as expressions and create them as immediates.
5382     const MCExpr *IdVal;
5383     S = Parser.getTok().getLoc();
5384     if (getParser().parseExpression(IdVal))
5385       return true;
5386     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5387     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5388     return false;
5389   }
5390   case AsmToken::LBrac:
5391     return parseMemory(Operands);
5392   case AsmToken::LCurly:
5393     return parseRegisterList(Operands);
5394   case AsmToken::Dollar:
5395   case AsmToken::Hash: {
5396     // #42 -> immediate.
5397     S = Parser.getTok().getLoc();
5398     Parser.Lex();
5399 
5400     if (Parser.getTok().isNot(AsmToken::Colon)) {
5401       bool isNegative = Parser.getTok().is(AsmToken::Minus);
5402       const MCExpr *ImmVal;
5403       if (getParser().parseExpression(ImmVal))
5404         return true;
5405       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5406       if (CE) {
5407         int32_t Val = CE->getValue();
5408         if (isNegative && Val == 0)
5409           ImmVal = MCConstantExpr::create(INT32_MIN, getContext());
5410       }
5411       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5412       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5413 
5414       // There can be a trailing '!' on operands that we want as a separate
5415       // '!' Token operand. Handle that here. For example, the compatibility
5416       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5417       if (Parser.getTok().is(AsmToken::Exclaim)) {
5418         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5419                                                    Parser.getTok().getLoc()));
5420         Parser.Lex(); // Eat exclaim token
5421       }
5422       return false;
5423     }
5424     // w/ a ':' after the '#', it's just like a plain ':'.
5425     LLVM_FALLTHROUGH;
5426   }
5427   case AsmToken::Colon: {
5428     S = Parser.getTok().getLoc();
5429     // ":lower16:" and ":upper16:" expression prefixes
5430     // FIXME: Check it's an expression prefix,
5431     // e.g. (FOO - :lower16:BAR) isn't legal.
5432     ARMMCExpr::VariantKind RefKind;
5433     if (parsePrefix(RefKind))
5434       return true;
5435 
5436     const MCExpr *SubExprVal;
5437     if (getParser().parseExpression(SubExprVal))
5438       return true;
5439 
5440     const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
5441                                               getContext());
5442     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5443     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5444     return false;
5445   }
5446   case AsmToken::Equal: {
5447     S = Parser.getTok().getLoc();
5448     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5449       return Error(S, "unexpected token in operand");
5450     Parser.Lex(); // Eat '='
5451     const MCExpr *SubExprVal;
5452     if (getParser().parseExpression(SubExprVal))
5453       return true;
5454     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5455     Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
5456     return false;
5457   }
5458   }
5459 }
5460 
5461 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5462 //  :lower16: and :upper16:.
5463 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5464   MCAsmParser &Parser = getParser();
5465   RefKind = ARMMCExpr::VK_ARM_None;
5466 
5467   // consume an optional '#' (GNU compatibility)
5468   if (getLexer().is(AsmToken::Hash))
5469     Parser.Lex();
5470 
5471   // :lower16: and :upper16: modifiers
5472   assert(getLexer().is(AsmToken::Colon) && "expected a :");
5473   Parser.Lex(); // Eat ':'
5474 
5475   if (getLexer().isNot(AsmToken::Identifier)) {
5476     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5477     return true;
5478   }
5479 
5480   enum {
5481     COFF = (1 << MCObjectFileInfo::IsCOFF),
5482     ELF = (1 << MCObjectFileInfo::IsELF),
5483     MACHO = (1 << MCObjectFileInfo::IsMachO)
5484   };
5485   static const struct PrefixEntry {
5486     const char *Spelling;
5487     ARMMCExpr::VariantKind VariantKind;
5488     uint8_t SupportedFormats;
5489   } PrefixEntries[] = {
5490     { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5491     { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5492   };
5493 
5494   StringRef IDVal = Parser.getTok().getIdentifier();
5495 
5496   const auto &Prefix =
5497       std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5498                    [&IDVal](const PrefixEntry &PE) {
5499                       return PE.Spelling == IDVal;
5500                    });
5501   if (Prefix == std::end(PrefixEntries)) {
5502     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5503     return true;
5504   }
5505 
5506   uint8_t CurrentFormat;
5507   switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5508   case MCObjectFileInfo::IsMachO:
5509     CurrentFormat = MACHO;
5510     break;
5511   case MCObjectFileInfo::IsELF:
5512     CurrentFormat = ELF;
5513     break;
5514   case MCObjectFileInfo::IsCOFF:
5515     CurrentFormat = COFF;
5516     break;
5517   }
5518 
5519   if (~Prefix->SupportedFormats & CurrentFormat) {
5520     Error(Parser.getTok().getLoc(),
5521           "cannot represent relocation in the current file format");
5522     return true;
5523   }
5524 
5525   RefKind = Prefix->VariantKind;
5526   Parser.Lex();
5527 
5528   if (getLexer().isNot(AsmToken::Colon)) {
5529     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5530     return true;
5531   }
5532   Parser.Lex(); // Eat the last ':'
5533 
5534   return false;
5535 }
5536 
5537 /// \brief Given a mnemonic, split out possible predication code and carry
5538 /// setting letters to form a canonical mnemonic and flags.
5539 //
5540 // FIXME: Would be nice to autogen this.
5541 // FIXME: This is a bit of a maze of special cases.
5542 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5543                                       unsigned &PredicationCode,
5544                                       bool &CarrySetting,
5545                                       unsigned &ProcessorIMod,
5546                                       StringRef &ITMask) {
5547   PredicationCode = ARMCC::AL;
5548   CarrySetting = false;
5549   ProcessorIMod = 0;
5550 
5551   // Ignore some mnemonics we know aren't predicated forms.
5552   //
5553   // FIXME: Would be nice to autogen this.
5554   if ((Mnemonic == "movs" && isThumb()) ||
5555       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
5556       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
5557       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
5558       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
5559       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
5560       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
5561       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
5562       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5563       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5564       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
5565       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5566       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5567       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
5568       Mnemonic == "bxns"  || Mnemonic == "blxns")
5569     return Mnemonic;
5570 
5571   // First, split out any predication code. Ignore mnemonics we know aren't
5572   // predicated but do have a carry-set and so weren't caught above.
5573   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5574       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5575       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5576       Mnemonic != "sbcs" && Mnemonic != "rscs") {
5577     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5578       .Case("eq", ARMCC::EQ)
5579       .Case("ne", ARMCC::NE)
5580       .Case("hs", ARMCC::HS)
5581       .Case("cs", ARMCC::HS)
5582       .Case("lo", ARMCC::LO)
5583       .Case("cc", ARMCC::LO)
5584       .Case("mi", ARMCC::MI)
5585       .Case("pl", ARMCC::PL)
5586       .Case("vs", ARMCC::VS)
5587       .Case("vc", ARMCC::VC)
5588       .Case("hi", ARMCC::HI)
5589       .Case("ls", ARMCC::LS)
5590       .Case("ge", ARMCC::GE)
5591       .Case("lt", ARMCC::LT)
5592       .Case("gt", ARMCC::GT)
5593       .Case("le", ARMCC::LE)
5594       .Case("al", ARMCC::AL)
5595       .Default(~0U);
5596     if (CC != ~0U) {
5597       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5598       PredicationCode = CC;
5599     }
5600   }
5601 
5602   // Next, determine if we have a carry setting bit. We explicitly ignore all
5603   // the instructions we know end in 's'.
5604   if (Mnemonic.endswith("s") &&
5605       !(Mnemonic == "cps" || Mnemonic == "mls" ||
5606         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5607         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5608         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5609         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5610         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5611         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5612         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5613         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5614         Mnemonic == "bxns" || Mnemonic == "blxns" ||
5615         (Mnemonic == "movs" && isThumb()))) {
5616     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5617     CarrySetting = true;
5618   }
5619 
5620   // The "cps" instruction can have a interrupt mode operand which is glued into
5621   // the mnemonic. Check if this is the case, split it and parse the imod op
5622   if (Mnemonic.startswith("cps")) {
5623     // Split out any imod code.
5624     unsigned IMod =
5625       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5626       .Case("ie", ARM_PROC::IE)
5627       .Case("id", ARM_PROC::ID)
5628       .Default(~0U);
5629     if (IMod != ~0U) {
5630       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5631       ProcessorIMod = IMod;
5632     }
5633   }
5634 
5635   // The "it" instruction has the condition mask on the end of the mnemonic.
5636   if (Mnemonic.startswith("it")) {
5637     ITMask = Mnemonic.slice(2, Mnemonic.size());
5638     Mnemonic = Mnemonic.slice(0, 2);
5639   }
5640 
5641   return Mnemonic;
5642 }
5643 
5644 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5645 /// inclusion of carry set or predication code operands.
5646 //
5647 // FIXME: It would be nice to autogen this.
5648 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5649                                          bool &CanAcceptCarrySet,
5650                                          bool &CanAcceptPredicationCode) {
5651   CanAcceptCarrySet =
5652       Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5653       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5654       Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
5655       Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
5656       Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
5657       Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
5658       Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5659       (!isThumb() &&
5660        (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
5661         Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
5662 
5663   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5664       Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5665       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5666       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5667       Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
5668       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
5669       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
5670       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
5671       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
5672       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5673       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
5674       Mnemonic == "vmovx" || Mnemonic == "vins") {
5675     // These mnemonics are never predicable
5676     CanAcceptPredicationCode = false;
5677   } else if (!isThumb()) {
5678     // Some instructions are only predicable in Thumb mode
5679     CanAcceptPredicationCode =
5680         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5681         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5682         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5683         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5684         Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" &&
5685         Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") &&
5686         !Mnemonic.startswith("srs");
5687   } else if (isThumbOne()) {
5688     if (hasV6MOps())
5689       CanAcceptPredicationCode = Mnemonic != "movs";
5690     else
5691       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5692   } else
5693     CanAcceptPredicationCode = true;
5694 }
5695 
5696 // \brief Some Thumb instructions have two operand forms that are not
5697 // available as three operand, convert to two operand form if possible.
5698 //
5699 // FIXME: We would really like to be able to tablegen'erate this.
5700 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
5701                                                  bool CarrySetting,
5702                                                  OperandVector &Operands) {
5703   if (Operands.size() != 6)
5704     return;
5705 
5706   const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5707         auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5708   if (!Op3.isReg() || !Op4.isReg())
5709     return;
5710 
5711   auto Op3Reg = Op3.getReg();
5712   auto Op4Reg = Op4.getReg();
5713 
5714   // For most Thumb2 cases we just generate the 3 operand form and reduce
5715   // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
5716   // won't accept SP or PC so we do the transformation here taking care
5717   // with immediate range in the 'add sp, sp #imm' case.
5718   auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5719   if (isThumbTwo()) {
5720     if (Mnemonic != "add")
5721       return;
5722     bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
5723                         (Op5.isReg() && Op5.getReg() == ARM::PC);
5724     if (!TryTransform) {
5725       TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
5726                       (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
5727                      !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
5728                        Op5.isImm() && !Op5.isImm0_508s4());
5729     }
5730     if (!TryTransform)
5731       return;
5732   } else if (!isThumbOne())
5733     return;
5734 
5735   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5736         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5737         Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5738         Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
5739     return;
5740 
5741   // If first 2 operands of a 3 operand instruction are the same
5742   // then transform to 2 operand version of the same instruction
5743   // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5744   bool Transform = Op3Reg == Op4Reg;
5745 
5746   // For communtative operations, we might be able to transform if we swap
5747   // Op4 and Op5.  The 'ADD Rdm, SP, Rdm' form is already handled specially
5748   // as tADDrsp.
5749   const ARMOperand *LastOp = &Op5;
5750   bool Swap = false;
5751   if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
5752       ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
5753        Mnemonic == "and" || Mnemonic == "eor" ||
5754        Mnemonic == "adc" || Mnemonic == "orr")) {
5755     Swap = true;
5756     LastOp = &Op4;
5757     Transform = true;
5758   }
5759 
5760   // If both registers are the same then remove one of them from
5761   // the operand list, with certain exceptions.
5762   if (Transform) {
5763     // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
5764     // 2 operand forms don't exist.
5765     if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
5766         LastOp->isReg())
5767       Transform = false;
5768 
5769     // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
5770     // 3-bits because the ARMARM says not to.
5771     if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
5772       Transform = false;
5773   }
5774 
5775   if (Transform) {
5776     if (Swap)
5777       std::swap(Op4, Op5);
5778     Operands.erase(Operands.begin() + 3);
5779   }
5780 }
5781 
5782 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5783                                           OperandVector &Operands) {
5784   // FIXME: This is all horribly hacky. We really need a better way to deal
5785   // with optional operands like this in the matcher table.
5786 
5787   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5788   // another does not. Specifically, the MOVW instruction does not. So we
5789   // special case it here and remove the defaulted (non-setting) cc_out
5790   // operand if that's the instruction we're trying to match.
5791   //
5792   // We do this as post-processing of the explicit operands rather than just
5793   // conditionally adding the cc_out in the first place because we need
5794   // to check the type of the parsed immediate operand.
5795   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5796       !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5797       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5798       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5799     return true;
5800 
5801   // Register-register 'add' for thumb does not have a cc_out operand
5802   // when there are only two register operands.
5803   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5804       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5805       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5806       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5807     return true;
5808   // Register-register 'add' for thumb does not have a cc_out operand
5809   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5810   // have to check the immediate range here since Thumb2 has a variant
5811   // that can handle a different range and has a cc_out operand.
5812   if (((isThumb() && Mnemonic == "add") ||
5813        (isThumbTwo() && Mnemonic == "sub")) &&
5814       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5815       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5816       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5817       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5818       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5819        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5820     return true;
5821   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5822   // imm0_4095 variant. That's the least-preferred variant when
5823   // selecting via the generic "add" mnemonic, so to know that we
5824   // should remove the cc_out operand, we have to explicitly check that
5825   // it's not one of the other variants. Ugh.
5826   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5827       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5828       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5829       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5830     // Nest conditions rather than one big 'if' statement for readability.
5831     //
5832     // If both registers are low, we're in an IT block, and the immediate is
5833     // in range, we should use encoding T1 instead, which has a cc_out.
5834     if (inITBlock() &&
5835         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5836         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5837         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5838       return false;
5839     // Check against T3. If the second register is the PC, this is an
5840     // alternate form of ADR, which uses encoding T4, so check for that too.
5841     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5842         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5843       return false;
5844 
5845     // Otherwise, we use encoding T4, which does not have a cc_out
5846     // operand.
5847     return true;
5848   }
5849 
5850   // The thumb2 multiply instruction doesn't have a CCOut register, so
5851   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5852   // use the 16-bit encoding or not.
5853   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5854       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5855       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5856       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5857       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5858       // If the registers aren't low regs, the destination reg isn't the
5859       // same as one of the source regs, or the cc_out operand is zero
5860       // outside of an IT block, we have to use the 32-bit encoding, so
5861       // remove the cc_out operand.
5862       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5863        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5864        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5865        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5866                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5867                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5868                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
5869     return true;
5870 
5871   // Also check the 'mul' syntax variant that doesn't specify an explicit
5872   // destination register.
5873   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5874       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5875       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5876       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5877       // If the registers aren't low regs  or the cc_out operand is zero
5878       // outside of an IT block, we have to use the 32-bit encoding, so
5879       // remove the cc_out operand.
5880       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5881        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5882        !inITBlock()))
5883     return true;
5884 
5885 
5886 
5887   // Register-register 'add/sub' for thumb does not have a cc_out operand
5888   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5889   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5890   // right, this will result in better diagnostics (which operand is off)
5891   // anyway.
5892   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5893       (Operands.size() == 5 || Operands.size() == 6) &&
5894       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5895       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5896       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5897       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5898        (Operands.size() == 6 &&
5899         static_cast<ARMOperand &>(*Operands[5]).isImm())))
5900     return true;
5901 
5902   return false;
5903 }
5904 
5905 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5906                                               OperandVector &Operands) {
5907   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5908   unsigned RegIdx = 3;
5909   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5910       (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
5911        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
5912     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5913         (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
5914          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
5915       RegIdx = 4;
5916 
5917     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5918         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5919              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5920          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5921              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5922       return true;
5923   }
5924   return false;
5925 }
5926 
5927 static bool isDataTypeToken(StringRef Tok) {
5928   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5929     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5930     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5931     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5932     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5933     Tok == ".f" || Tok == ".d";
5934 }
5935 
5936 // FIXME: This bit should probably be handled via an explicit match class
5937 // in the .td files that matches the suffix instead of having it be
5938 // a literal string token the way it is now.
5939 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5940   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5941 }
5942 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5943                                  unsigned VariantID);
5944 
5945 static bool RequiresVFPRegListValidation(StringRef Inst,
5946                                          bool &AcceptSinglePrecisionOnly,
5947                                          bool &AcceptDoublePrecisionOnly) {
5948   if (Inst.size() < 7)
5949     return false;
5950 
5951   if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5952     StringRef AddressingMode = Inst.substr(4, 2);
5953     if (AddressingMode == "ia" || AddressingMode == "db" ||
5954         AddressingMode == "ea" || AddressingMode == "fd") {
5955       AcceptSinglePrecisionOnly = Inst[6] == 's';
5956       AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5957       return true;
5958     }
5959   }
5960 
5961   return false;
5962 }
5963 
5964 /// Parse an arm instruction mnemonic followed by its operands.
5965 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5966                                     SMLoc NameLoc, OperandVector &Operands) {
5967   MCAsmParser &Parser = getParser();
5968   // FIXME: Can this be done via tablegen in some fashion?
5969   bool RequireVFPRegisterListCheck;
5970   bool AcceptSinglePrecisionOnly;
5971   bool AcceptDoublePrecisionOnly;
5972   RequireVFPRegisterListCheck =
5973     RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5974                                  AcceptDoublePrecisionOnly);
5975 
5976   // Apply mnemonic aliases before doing anything else, as the destination
5977   // mnemonic may include suffices and we want to handle them normally.
5978   // The generic tblgen'erated code does this later, at the start of
5979   // MatchInstructionImpl(), but that's too late for aliases that include
5980   // any sort of suffix.
5981   uint64_t AvailableFeatures = getAvailableFeatures();
5982   unsigned AssemblerDialect = getParser().getAssemblerDialect();
5983   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5984 
5985   // First check for the ARM-specific .req directive.
5986   if (Parser.getTok().is(AsmToken::Identifier) &&
5987       Parser.getTok().getIdentifier() == ".req") {
5988     parseDirectiveReq(Name, NameLoc);
5989     // We always return 'error' for this, as we're done with this
5990     // statement and don't need to match the 'instruction."
5991     return true;
5992   }
5993 
5994   // Create the leading tokens for the mnemonic, split by '.' characters.
5995   size_t Start = 0, Next = Name.find('.');
5996   StringRef Mnemonic = Name.slice(Start, Next);
5997 
5998   // Split out the predication code and carry setting flag from the mnemonic.
5999   unsigned PredicationCode;
6000   unsigned ProcessorIMod;
6001   bool CarrySetting;
6002   StringRef ITMask;
6003   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
6004                            ProcessorIMod, ITMask);
6005 
6006   // In Thumb1, only the branch (B) instruction can be predicated.
6007   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
6008     return Error(NameLoc, "conditional execution not supported in Thumb1");
6009   }
6010 
6011   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
6012 
6013   // Handle the IT instruction ITMask. Convert it to a bitmask. This
6014   // is the mask as it will be for the IT encoding if the conditional
6015   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
6016   // where the conditional bit0 is zero, the instruction post-processing
6017   // will adjust the mask accordingly.
6018   if (Mnemonic == "it") {
6019     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
6020     if (ITMask.size() > 3) {
6021       return Error(Loc, "too many conditions on IT instruction");
6022     }
6023     unsigned Mask = 8;
6024     for (unsigned i = ITMask.size(); i != 0; --i) {
6025       char pos = ITMask[i - 1];
6026       if (pos != 't' && pos != 'e') {
6027         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
6028       }
6029       Mask >>= 1;
6030       if (ITMask[i - 1] == 't')
6031         Mask |= 8;
6032     }
6033     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
6034   }
6035 
6036   // FIXME: This is all a pretty gross hack. We should automatically handle
6037   // optional operands like this via tblgen.
6038 
6039   // Next, add the CCOut and ConditionCode operands, if needed.
6040   //
6041   // For mnemonics which can ever incorporate a carry setting bit or predication
6042   // code, our matching model involves us always generating CCOut and
6043   // ConditionCode operands to match the mnemonic "as written" and then we let
6044   // the matcher deal with finding the right instruction or generating an
6045   // appropriate error.
6046   bool CanAcceptCarrySet, CanAcceptPredicationCode;
6047   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
6048 
6049   // If we had a carry-set on an instruction that can't do that, issue an
6050   // error.
6051   if (!CanAcceptCarrySet && CarrySetting) {
6052     return Error(NameLoc, "instruction '" + Mnemonic +
6053                  "' can not set flags, but 's' suffix specified");
6054   }
6055   // If we had a predication code on an instruction that can't do that, issue an
6056   // error.
6057   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
6058     return Error(NameLoc, "instruction '" + Mnemonic +
6059                  "' is not predicable, but condition code specified");
6060   }
6061 
6062   // Add the carry setting operand, if necessary.
6063   if (CanAcceptCarrySet) {
6064     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
6065     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
6066                                                Loc));
6067   }
6068 
6069   // Add the predication code operand, if necessary.
6070   if (CanAcceptPredicationCode) {
6071     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
6072                                       CarrySetting);
6073     Operands.push_back(ARMOperand::CreateCondCode(
6074                          ARMCC::CondCodes(PredicationCode), Loc));
6075   }
6076 
6077   // Add the processor imod operand, if necessary.
6078   if (ProcessorIMod) {
6079     Operands.push_back(ARMOperand::CreateImm(
6080           MCConstantExpr::create(ProcessorIMod, getContext()),
6081                                  NameLoc, NameLoc));
6082   } else if (Mnemonic == "cps" && isMClass()) {
6083     return Error(NameLoc, "instruction 'cps' requires effect for M-class");
6084   }
6085 
6086   // Add the remaining tokens in the mnemonic.
6087   while (Next != StringRef::npos) {
6088     Start = Next;
6089     Next = Name.find('.', Start + 1);
6090     StringRef ExtraToken = Name.slice(Start, Next);
6091 
6092     // Some NEON instructions have an optional datatype suffix that is
6093     // completely ignored. Check for that.
6094     if (isDataTypeToken(ExtraToken) &&
6095         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
6096       continue;
6097 
6098     // For for ARM mode generate an error if the .n qualifier is used.
6099     if (ExtraToken == ".n" && !isThumb()) {
6100       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6101       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
6102                    "arm mode");
6103     }
6104 
6105     // The .n qualifier is always discarded as that is what the tables
6106     // and matcher expect.  In ARM mode the .w qualifier has no effect,
6107     // so discard it to avoid errors that can be caused by the matcher.
6108     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
6109       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6110       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
6111     }
6112   }
6113 
6114   // Read the remaining operands.
6115   if (getLexer().isNot(AsmToken::EndOfStatement)) {
6116     // Read the first operand.
6117     if (parseOperand(Operands, Mnemonic)) {
6118       return true;
6119     }
6120 
6121     while (parseOptionalToken(AsmToken::Comma)) {
6122       // Parse and remember the operand.
6123       if (parseOperand(Operands, Mnemonic)) {
6124         return true;
6125       }
6126     }
6127   }
6128 
6129   if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
6130     return true;
6131 
6132   if (RequireVFPRegisterListCheck) {
6133     ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
6134     if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
6135       return Error(Op.getStartLoc(),
6136                    "VFP/Neon single precision register expected");
6137     if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
6138       return Error(Op.getStartLoc(),
6139                    "VFP/Neon double precision register expected");
6140   }
6141 
6142   tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
6143 
6144   // Some instructions, mostly Thumb, have forms for the same mnemonic that
6145   // do and don't have a cc_out optional-def operand. With some spot-checks
6146   // of the operand list, we can figure out which variant we're trying to
6147   // parse and adjust accordingly before actually matching. We shouldn't ever
6148   // try to remove a cc_out operand that was explicitly set on the
6149   // mnemonic, of course (CarrySetting == true). Reason number #317 the
6150   // table driven matcher doesn't fit well with the ARM instruction set.
6151   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
6152     Operands.erase(Operands.begin() + 1);
6153 
6154   // Some instructions have the same mnemonic, but don't always
6155   // have a predicate. Distinguish them here and delete the
6156   // predicate if needed.
6157   if (shouldOmitPredicateOperand(Mnemonic, Operands))
6158     Operands.erase(Operands.begin() + 1);
6159 
6160   // ARM mode 'blx' need special handling, as the register operand version
6161   // is predicable, but the label operand version is not. So, we can't rely
6162   // on the Mnemonic based checking to correctly figure out when to put
6163   // a k_CondCode operand in the list. If we're trying to match the label
6164   // version, remove the k_CondCode operand here.
6165   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
6166       static_cast<ARMOperand &>(*Operands[2]).isImm())
6167     Operands.erase(Operands.begin() + 1);
6168 
6169   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
6170   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
6171   // a single GPRPair reg operand is used in the .td file to replace the two
6172   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
6173   // expressed as a GPRPair, so we have to manually merge them.
6174   // FIXME: We would really like to be able to tablegen'erate this.
6175   if (!isThumb() && Operands.size() > 4 &&
6176       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
6177        Mnemonic == "stlexd")) {
6178     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
6179     unsigned Idx = isLoad ? 2 : 3;
6180     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
6181     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
6182 
6183     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
6184     // Adjust only if Op1 and Op2 are GPRs.
6185     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
6186         MRC.contains(Op2.getReg())) {
6187       unsigned Reg1 = Op1.getReg();
6188       unsigned Reg2 = Op2.getReg();
6189       unsigned Rt = MRI->getEncodingValue(Reg1);
6190       unsigned Rt2 = MRI->getEncodingValue(Reg2);
6191 
6192       // Rt2 must be Rt + 1 and Rt must be even.
6193       if (Rt + 1 != Rt2 || (Rt & 1)) {
6194         return Error(Op2.getStartLoc(),
6195                      isLoad ? "destination operands must be sequential"
6196                             : "source operands must be sequential");
6197       }
6198       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
6199           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
6200       Operands[Idx] =
6201           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
6202       Operands.erase(Operands.begin() + Idx + 1);
6203     }
6204   }
6205 
6206   // GNU Assembler extension (compatibility)
6207   if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
6208     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
6209     ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6210     if (Op3.isMem()) {
6211       assert(Op2.isReg() && "expected register argument");
6212 
6213       unsigned SuperReg = MRI->getMatchingSuperReg(
6214           Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
6215 
6216       assert(SuperReg && "expected register pair");
6217 
6218       unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
6219 
6220       Operands.insert(
6221           Operands.begin() + 3,
6222           ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
6223     }
6224   }
6225 
6226   // FIXME: As said above, this is all a pretty gross hack.  This instruction
6227   // does not fit with other "subs" and tblgen.
6228   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
6229   // so the Mnemonic is the original name "subs" and delete the predicate
6230   // operand so it will match the table entry.
6231   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
6232       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6233       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
6234       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6235       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
6236       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6237     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
6238     Operands.erase(Operands.begin() + 1);
6239   }
6240   return false;
6241 }
6242 
6243 // Validate context-sensitive operand constraints.
6244 
6245 // return 'true' if register list contains non-low GPR registers,
6246 // 'false' otherwise. If Reg is in the register list or is HiReg, set
6247 // 'containsReg' to true.
6248 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
6249                                  unsigned Reg, unsigned HiReg,
6250                                  bool &containsReg) {
6251   containsReg = false;
6252   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6253     unsigned OpReg = Inst.getOperand(i).getReg();
6254     if (OpReg == Reg)
6255       containsReg = true;
6256     // Anything other than a low register isn't legal here.
6257     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6258       return true;
6259   }
6260   return false;
6261 }
6262 
6263 // Check if the specified regisgter is in the register list of the inst,
6264 // starting at the indicated operand number.
6265 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
6266   for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
6267     unsigned OpReg = Inst.getOperand(i).getReg();
6268     if (OpReg == Reg)
6269       return true;
6270   }
6271   return false;
6272 }
6273 
6274 // Return true if instruction has the interesting property of being
6275 // allowed in IT blocks, but not being predicable.
6276 static bool instIsBreakpoint(const MCInst &Inst) {
6277     return Inst.getOpcode() == ARM::tBKPT ||
6278            Inst.getOpcode() == ARM::BKPT ||
6279            Inst.getOpcode() == ARM::tHLT ||
6280            Inst.getOpcode() == ARM::HLT;
6281 
6282 }
6283 
6284 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
6285                                        const OperandVector &Operands,
6286                                        unsigned ListNo, bool IsARPop) {
6287   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6288   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6289 
6290   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6291   bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6292   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6293 
6294   if (!IsARPop && ListContainsSP)
6295     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6296                  "SP may not be in the register list");
6297   else if (ListContainsPC && ListContainsLR)
6298     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6299                  "PC and LR may not be in the register list simultaneously");
6300   else if (inITBlock() && !lastInITBlock() && ListContainsPC)
6301     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6302                  "instruction must be outside of IT block or the last "
6303                  "instruction in an IT block");
6304   return false;
6305 }
6306 
6307 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
6308                                        const OperandVector &Operands,
6309                                        unsigned ListNo) {
6310   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6311   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6312 
6313   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6314   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6315 
6316   if (ListContainsSP && ListContainsPC)
6317     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6318                  "SP and PC may not be in the register list");
6319   else if (ListContainsSP)
6320     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6321                  "SP may not be in the register list");
6322   else if (ListContainsPC)
6323     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6324                  "PC may not be in the register list");
6325   return false;
6326 }
6327 
6328 // FIXME: We would really like to be able to tablegen'erate this.
6329 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6330                                        const OperandVector &Operands) {
6331   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6332   SMLoc Loc = Operands[0]->getStartLoc();
6333 
6334   // Check the IT block state first.
6335   // NOTE: BKPT and HLT instructions have the interesting property of being
6336   // allowed in IT blocks, but not being predicable. They just always execute.
6337   if (inITBlock() && !instIsBreakpoint(Inst)) {
6338     // The instruction must be predicable.
6339     if (!MCID.isPredicable())
6340       return Error(Loc, "instructions in IT block must be predicable");
6341     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6342     if (Cond != currentITCond()) {
6343       // Find the condition code Operand to get its SMLoc information.
6344       SMLoc CondLoc;
6345       for (unsigned I = 1; I < Operands.size(); ++I)
6346         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6347           CondLoc = Operands[I]->getStartLoc();
6348       return Error(CondLoc, "incorrect condition in IT block; got '" +
6349                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
6350                    "', but expected '" +
6351                    ARMCondCodeToString(ARMCC::CondCodes(currentITCond())) + "'");
6352     }
6353   // Check for non-'al' condition codes outside of the IT block.
6354   } else if (isThumbTwo() && MCID.isPredicable() &&
6355              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6356              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6357              Inst.getOpcode() != ARM::t2Bcc) {
6358     return Error(Loc, "predicated instructions must be in IT block");
6359   } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
6360              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6361                  ARMCC::AL) {
6362     return Warning(Loc, "predicated instructions should be in IT block");
6363   }
6364 
6365   const unsigned Opcode = Inst.getOpcode();
6366   switch (Opcode) {
6367   case ARM::LDRD:
6368   case ARM::LDRD_PRE:
6369   case ARM::LDRD_POST: {
6370     const unsigned RtReg = Inst.getOperand(0).getReg();
6371 
6372     // Rt can't be R14.
6373     if (RtReg == ARM::LR)
6374       return Error(Operands[3]->getStartLoc(),
6375                    "Rt can't be R14");
6376 
6377     const unsigned Rt = MRI->getEncodingValue(RtReg);
6378     // Rt must be even-numbered.
6379     if ((Rt & 1) == 1)
6380       return Error(Operands[3]->getStartLoc(),
6381                    "Rt must be even-numbered");
6382 
6383     // Rt2 must be Rt + 1.
6384     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6385     if (Rt2 != Rt + 1)
6386       return Error(Operands[3]->getStartLoc(),
6387                    "destination operands must be sequential");
6388 
6389     if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
6390       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6391       // For addressing modes with writeback, the base register needs to be
6392       // different from the destination registers.
6393       if (Rn == Rt || Rn == Rt2)
6394         return Error(Operands[3]->getStartLoc(),
6395                      "base register needs to be different from destination "
6396                      "registers");
6397     }
6398 
6399     return false;
6400   }
6401   case ARM::t2LDRDi8:
6402   case ARM::t2LDRD_PRE:
6403   case ARM::t2LDRD_POST: {
6404     // Rt2 must be different from Rt.
6405     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6406     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6407     if (Rt2 == Rt)
6408       return Error(Operands[3]->getStartLoc(),
6409                    "destination operands can't be identical");
6410     return false;
6411   }
6412   case ARM::t2BXJ: {
6413     const unsigned RmReg = Inst.getOperand(0).getReg();
6414     // Rm = SP is no longer unpredictable in v8-A
6415     if (RmReg == ARM::SP && !hasV8Ops())
6416       return Error(Operands[2]->getStartLoc(),
6417                    "r13 (SP) is an unpredictable operand to BXJ");
6418     return false;
6419   }
6420   case ARM::STRD: {
6421     // Rt2 must be Rt + 1.
6422     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6423     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6424     if (Rt2 != Rt + 1)
6425       return Error(Operands[3]->getStartLoc(),
6426                    "source operands must be sequential");
6427     return false;
6428   }
6429   case ARM::STRD_PRE:
6430   case ARM::STRD_POST: {
6431     // Rt2 must be Rt + 1.
6432     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6433     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6434     if (Rt2 != Rt + 1)
6435       return Error(Operands[3]->getStartLoc(),
6436                    "source operands must be sequential");
6437     return false;
6438   }
6439   case ARM::STR_PRE_IMM:
6440   case ARM::STR_PRE_REG:
6441   case ARM::STR_POST_IMM:
6442   case ARM::STR_POST_REG:
6443   case ARM::STRH_PRE:
6444   case ARM::STRH_POST:
6445   case ARM::STRB_PRE_IMM:
6446   case ARM::STRB_PRE_REG:
6447   case ARM::STRB_POST_IMM:
6448   case ARM::STRB_POST_REG: {
6449     // Rt must be different from Rn.
6450     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6451     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6452 
6453     if (Rt == Rn)
6454       return Error(Operands[3]->getStartLoc(),
6455                    "source register and base register can't be identical");
6456     return false;
6457   }
6458   case ARM::LDR_PRE_IMM:
6459   case ARM::LDR_PRE_REG:
6460   case ARM::LDR_POST_IMM:
6461   case ARM::LDR_POST_REG:
6462   case ARM::LDRH_PRE:
6463   case ARM::LDRH_POST:
6464   case ARM::LDRSH_PRE:
6465   case ARM::LDRSH_POST:
6466   case ARM::LDRB_PRE_IMM:
6467   case ARM::LDRB_PRE_REG:
6468   case ARM::LDRB_POST_IMM:
6469   case ARM::LDRB_POST_REG:
6470   case ARM::LDRSB_PRE:
6471   case ARM::LDRSB_POST: {
6472     // Rt must be different from Rn.
6473     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6474     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6475 
6476     if (Rt == Rn)
6477       return Error(Operands[3]->getStartLoc(),
6478                    "destination register and base register can't be identical");
6479     return false;
6480   }
6481   case ARM::SBFX:
6482   case ARM::UBFX: {
6483     // Width must be in range [1, 32-lsb].
6484     unsigned LSB = Inst.getOperand(2).getImm();
6485     unsigned Widthm1 = Inst.getOperand(3).getImm();
6486     if (Widthm1 >= 32 - LSB)
6487       return Error(Operands[5]->getStartLoc(),
6488                    "bitfield width must be in range [1,32-lsb]");
6489     return false;
6490   }
6491   // Notionally handles ARM::tLDMIA_UPD too.
6492   case ARM::tLDMIA: {
6493     // If we're parsing Thumb2, the .w variant is available and handles
6494     // most cases that are normally illegal for a Thumb1 LDM instruction.
6495     // We'll make the transformation in processInstruction() if necessary.
6496     //
6497     // Thumb LDM instructions are writeback iff the base register is not
6498     // in the register list.
6499     unsigned Rn = Inst.getOperand(0).getReg();
6500     bool HasWritebackToken =
6501         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6502          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6503     bool ListContainsBase;
6504     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6505       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6506                    "registers must be in range r0-r7");
6507     // If we should have writeback, then there should be a '!' token.
6508     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6509       return Error(Operands[2]->getStartLoc(),
6510                    "writeback operator '!' expected");
6511     // If we should not have writeback, there must not be a '!'. This is
6512     // true even for the 32-bit wide encodings.
6513     if (ListContainsBase && HasWritebackToken)
6514       return Error(Operands[3]->getStartLoc(),
6515                    "writeback operator '!' not allowed when base register "
6516                    "in register list");
6517 
6518     if (validatetLDMRegList(Inst, Operands, 3))
6519       return true;
6520     break;
6521   }
6522   case ARM::LDMIA_UPD:
6523   case ARM::LDMDB_UPD:
6524   case ARM::LDMIB_UPD:
6525   case ARM::LDMDA_UPD:
6526     // ARM variants loading and updating the same register are only officially
6527     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6528     if (!hasV7Ops())
6529       break;
6530     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6531       return Error(Operands.back()->getStartLoc(),
6532                    "writeback register not allowed in register list");
6533     break;
6534   case ARM::t2LDMIA:
6535   case ARM::t2LDMDB:
6536     if (validatetLDMRegList(Inst, Operands, 3))
6537       return true;
6538     break;
6539   case ARM::t2STMIA:
6540   case ARM::t2STMDB:
6541     if (validatetSTMRegList(Inst, Operands, 3))
6542       return true;
6543     break;
6544   case ARM::t2LDMIA_UPD:
6545   case ARM::t2LDMDB_UPD:
6546   case ARM::t2STMIA_UPD:
6547   case ARM::t2STMDB_UPD: {
6548     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6549       return Error(Operands.back()->getStartLoc(),
6550                    "writeback register not allowed in register list");
6551 
6552     if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6553       if (validatetLDMRegList(Inst, Operands, 3))
6554         return true;
6555     } else {
6556       if (validatetSTMRegList(Inst, Operands, 3))
6557         return true;
6558     }
6559     break;
6560   }
6561   case ARM::sysLDMIA_UPD:
6562   case ARM::sysLDMDA_UPD:
6563   case ARM::sysLDMDB_UPD:
6564   case ARM::sysLDMIB_UPD:
6565     if (!listContainsReg(Inst, 3, ARM::PC))
6566       return Error(Operands[4]->getStartLoc(),
6567                    "writeback register only allowed on system LDM "
6568                    "if PC in register-list");
6569     break;
6570   case ARM::sysSTMIA_UPD:
6571   case ARM::sysSTMDA_UPD:
6572   case ARM::sysSTMDB_UPD:
6573   case ARM::sysSTMIB_UPD:
6574     return Error(Operands[2]->getStartLoc(),
6575                  "system STM cannot have writeback register");
6576   case ARM::tMUL: {
6577     // The second source operand must be the same register as the destination
6578     // operand.
6579     //
6580     // In this case, we must directly check the parsed operands because the
6581     // cvtThumbMultiply() function is written in such a way that it guarantees
6582     // this first statement is always true for the new Inst.  Essentially, the
6583     // destination is unconditionally copied into the second source operand
6584     // without checking to see if it matches what we actually parsed.
6585     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6586                                  ((ARMOperand &)*Operands[5]).getReg()) &&
6587         (((ARMOperand &)*Operands[3]).getReg() !=
6588          ((ARMOperand &)*Operands[4]).getReg())) {
6589       return Error(Operands[3]->getStartLoc(),
6590                    "destination register must match source register");
6591     }
6592     break;
6593   }
6594   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6595   // so only issue a diagnostic for thumb1. The instructions will be
6596   // switched to the t2 encodings in processInstruction() if necessary.
6597   case ARM::tPOP: {
6598     bool ListContainsBase;
6599     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6600         !isThumbTwo())
6601       return Error(Operands[2]->getStartLoc(),
6602                    "registers must be in range r0-r7 or pc");
6603     if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6604       return true;
6605     break;
6606   }
6607   case ARM::tPUSH: {
6608     bool ListContainsBase;
6609     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6610         !isThumbTwo())
6611       return Error(Operands[2]->getStartLoc(),
6612                    "registers must be in range r0-r7 or lr");
6613     if (validatetSTMRegList(Inst, Operands, 2))
6614       return true;
6615     break;
6616   }
6617   case ARM::tSTMIA_UPD: {
6618     bool ListContainsBase, InvalidLowList;
6619     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6620                                           0, ListContainsBase);
6621     if (InvalidLowList && !isThumbTwo())
6622       return Error(Operands[4]->getStartLoc(),
6623                    "registers must be in range r0-r7");
6624 
6625     // This would be converted to a 32-bit stm, but that's not valid if the
6626     // writeback register is in the list.
6627     if (InvalidLowList && ListContainsBase)
6628       return Error(Operands[4]->getStartLoc(),
6629                    "writeback operator '!' not allowed when base register "
6630                    "in register list");
6631 
6632     if (validatetSTMRegList(Inst, Operands, 4))
6633       return true;
6634     break;
6635   }
6636   case ARM::tADDrSP: {
6637     // If the non-SP source operand and the destination operand are not the
6638     // same, we need thumb2 (for the wide encoding), or we have an error.
6639     if (!isThumbTwo() &&
6640         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6641       return Error(Operands[4]->getStartLoc(),
6642                    "source register must be the same as destination");
6643     }
6644     break;
6645   }
6646   // Final range checking for Thumb unconditional branch instructions.
6647   case ARM::tB:
6648     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6649       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6650     break;
6651   case ARM::t2B: {
6652     int op = (Operands[2]->isImm()) ? 2 : 3;
6653     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6654       return Error(Operands[op]->getStartLoc(), "branch target out of range");
6655     break;
6656   }
6657   // Final range checking for Thumb conditional branch instructions.
6658   case ARM::tBcc:
6659     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6660       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6661     break;
6662   case ARM::t2Bcc: {
6663     int Op = (Operands[2]->isImm()) ? 2 : 3;
6664     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6665       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6666     break;
6667   }
6668   case ARM::tCBZ:
6669   case ARM::tCBNZ: {
6670     if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
6671       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6672     break;
6673   }
6674   case ARM::MOVi16:
6675   case ARM::t2MOVi16:
6676   case ARM::t2MOVTi16:
6677     {
6678     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6679     // especially when we turn it into a movw and the expression <symbol> does
6680     // not have a :lower16: or :upper16 as part of the expression.  We don't
6681     // want the behavior of silently truncating, which can be unexpected and
6682     // lead to bugs that are difficult to find since this is an easy mistake
6683     // to make.
6684     int i = (Operands[3]->isImm()) ? 3 : 4;
6685     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6686     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6687     if (CE) break;
6688     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6689     if (!E) break;
6690     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6691     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6692                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6693       return Error(
6694           Op.getStartLoc(),
6695           "immediate expression for mov requires :lower16: or :upper16");
6696     break;
6697   }
6698   case ARM::HINT:
6699   case ARM::t2HINT: {
6700     if (hasRAS()) {
6701       // ESB is not predicable (pred must be AL)
6702       unsigned Imm8 = Inst.getOperand(0).getImm();
6703       unsigned Pred = Inst.getOperand(1).getImm();
6704       if (Imm8 == 0x10 && Pred != ARMCC::AL)
6705         return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
6706                                                  "predicable, but condition "
6707                                                  "code specified");
6708     }
6709     // Without the RAS extension, this behaves as any other unallocated hint.
6710     break;
6711   }
6712   }
6713 
6714   return false;
6715 }
6716 
6717 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6718   switch(Opc) {
6719   default: llvm_unreachable("unexpected opcode!");
6720   // VST1LN
6721   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6722   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6723   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6724   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6725   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6726   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6727   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
6728   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6729   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6730 
6731   // VST2LN
6732   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6733   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6734   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6735   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6736   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6737 
6738   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6739   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6740   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6741   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6742   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6743 
6744   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
6745   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6746   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6747   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6748   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6749 
6750   // VST3LN
6751   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6752   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6753   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6754   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6755   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6756   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6757   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6758   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6759   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6760   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6761   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
6762   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6763   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6764   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6765   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6766 
6767   // VST3
6768   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6769   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6770   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6771   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6772   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6773   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6774   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6775   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6776   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6777   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6778   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6779   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6780   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
6781   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6782   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6783   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
6784   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6785   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6786 
6787   // VST4LN
6788   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6789   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6790   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6791   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6792   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6793   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6794   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6795   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6796   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6797   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6798   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
6799   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6800   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6801   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6802   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6803 
6804   // VST4
6805   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6806   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6807   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6808   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6809   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6810   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6811   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6812   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6813   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6814   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6815   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6816   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6817   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
6818   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6819   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6820   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
6821   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6822   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6823   }
6824 }
6825 
6826 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6827   switch(Opc) {
6828   default: llvm_unreachable("unexpected opcode!");
6829   // VLD1LN
6830   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6831   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6832   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6833   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6834   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6835   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6836   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
6837   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6838   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6839 
6840   // VLD2LN
6841   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6842   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6843   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6844   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6845   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6846   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6847   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6848   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6849   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6850   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6851   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
6852   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6853   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6854   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6855   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6856 
6857   // VLD3DUP
6858   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6859   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6860   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6861   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6862   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6863   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6864   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6865   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6866   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6867   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6868   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6869   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6870   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
6871   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6872   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6873   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6874   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6875   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6876 
6877   // VLD3LN
6878   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6879   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6880   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6881   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6882   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6883   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6884   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6885   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6886   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6887   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6888   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
6889   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6890   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6891   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6892   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6893 
6894   // VLD3
6895   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6896   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6897   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6898   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6899   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6900   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6901   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6902   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6903   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6904   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6905   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6906   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6907   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
6908   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6909   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6910   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
6911   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6912   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6913 
6914   // VLD4LN
6915   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6916   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6917   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6918   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6919   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6920   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6921   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6922   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6923   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6924   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6925   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
6926   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6927   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6928   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6929   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6930 
6931   // VLD4DUP
6932   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6933   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6934   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6935   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6936   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6937   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6938   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6939   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6940   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6941   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6942   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6943   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6944   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
6945   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6946   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6947   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6948   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6949   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6950 
6951   // VLD4
6952   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6953   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6954   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6955   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6956   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6957   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6958   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6959   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6960   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6961   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6962   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6963   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6964   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
6965   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6966   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6967   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
6968   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6969   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6970   }
6971 }
6972 
6973 bool ARMAsmParser::processInstruction(MCInst &Inst,
6974                                       const OperandVector &Operands,
6975                                       MCStreamer &Out) {
6976   switch (Inst.getOpcode()) {
6977   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6978   case ARM::LDRT_POST:
6979   case ARM::LDRBT_POST: {
6980     const unsigned Opcode =
6981       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6982                                            : ARM::LDRBT_POST_IMM;
6983     MCInst TmpInst;
6984     TmpInst.setOpcode(Opcode);
6985     TmpInst.addOperand(Inst.getOperand(0));
6986     TmpInst.addOperand(Inst.getOperand(1));
6987     TmpInst.addOperand(Inst.getOperand(1));
6988     TmpInst.addOperand(MCOperand::createReg(0));
6989     TmpInst.addOperand(MCOperand::createImm(0));
6990     TmpInst.addOperand(Inst.getOperand(2));
6991     TmpInst.addOperand(Inst.getOperand(3));
6992     Inst = TmpInst;
6993     return true;
6994   }
6995   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6996   case ARM::STRT_POST:
6997   case ARM::STRBT_POST: {
6998     const unsigned Opcode =
6999       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
7000                                            : ARM::STRBT_POST_IMM;
7001     MCInst TmpInst;
7002     TmpInst.setOpcode(Opcode);
7003     TmpInst.addOperand(Inst.getOperand(1));
7004     TmpInst.addOperand(Inst.getOperand(0));
7005     TmpInst.addOperand(Inst.getOperand(1));
7006     TmpInst.addOperand(MCOperand::createReg(0));
7007     TmpInst.addOperand(MCOperand::createImm(0));
7008     TmpInst.addOperand(Inst.getOperand(2));
7009     TmpInst.addOperand(Inst.getOperand(3));
7010     Inst = TmpInst;
7011     return true;
7012   }
7013   // Alias for alternate form of 'ADR Rd, #imm' instruction.
7014   case ARM::ADDri: {
7015     if (Inst.getOperand(1).getReg() != ARM::PC ||
7016         Inst.getOperand(5).getReg() != 0 ||
7017         !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
7018       return false;
7019     MCInst TmpInst;
7020     TmpInst.setOpcode(ARM::ADR);
7021     TmpInst.addOperand(Inst.getOperand(0));
7022     if (Inst.getOperand(2).isImm()) {
7023       // Immediate (mod_imm) will be in its encoded form, we must unencode it
7024       // before passing it to the ADR instruction.
7025       unsigned Enc = Inst.getOperand(2).getImm();
7026       TmpInst.addOperand(MCOperand::createImm(
7027         ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
7028     } else {
7029       // Turn PC-relative expression into absolute expression.
7030       // Reading PC provides the start of the current instruction + 8 and
7031       // the transform to adr is biased by that.
7032       MCSymbol *Dot = getContext().createTempSymbol();
7033       Out.EmitLabel(Dot);
7034       const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
7035       const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
7036                                                      MCSymbolRefExpr::VK_None,
7037                                                      getContext());
7038       const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
7039       const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
7040                                                      getContext());
7041       const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
7042                                                         getContext());
7043       TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
7044     }
7045     TmpInst.addOperand(Inst.getOperand(3));
7046     TmpInst.addOperand(Inst.getOperand(4));
7047     Inst = TmpInst;
7048     return true;
7049   }
7050   // Aliases for alternate PC+imm syntax of LDR instructions.
7051   case ARM::t2LDRpcrel:
7052     // Select the narrow version if the immediate will fit.
7053     if (Inst.getOperand(1).getImm() > 0 &&
7054         Inst.getOperand(1).getImm() <= 0xff &&
7055         !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
7056           static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
7057       Inst.setOpcode(ARM::tLDRpci);
7058     else
7059       Inst.setOpcode(ARM::t2LDRpci);
7060     return true;
7061   case ARM::t2LDRBpcrel:
7062     Inst.setOpcode(ARM::t2LDRBpci);
7063     return true;
7064   case ARM::t2LDRHpcrel:
7065     Inst.setOpcode(ARM::t2LDRHpci);
7066     return true;
7067   case ARM::t2LDRSBpcrel:
7068     Inst.setOpcode(ARM::t2LDRSBpci);
7069     return true;
7070   case ARM::t2LDRSHpcrel:
7071     Inst.setOpcode(ARM::t2LDRSHpci);
7072     return true;
7073   case ARM::LDRConstPool:
7074   case ARM::tLDRConstPool:
7075   case ARM::t2LDRConstPool: {
7076     // Pseudo instruction ldr rt, =immediate is converted to a
7077     // MOV rt, immediate if immediate is known and representable
7078     // otherwise we create a constant pool entry that we load from.
7079     MCInst TmpInst;
7080     if (Inst.getOpcode() == ARM::LDRConstPool)
7081       TmpInst.setOpcode(ARM::LDRi12);
7082     else if (Inst.getOpcode() == ARM::tLDRConstPool)
7083       TmpInst.setOpcode(ARM::tLDRpci);
7084     else if (Inst.getOpcode() == ARM::t2LDRConstPool)
7085       TmpInst.setOpcode(ARM::t2LDRpci);
7086     const ARMOperand &PoolOperand =
7087       (static_cast<ARMOperand &>(*Operands[2]).isToken() &&
7088        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w") ?
7089       static_cast<ARMOperand &>(*Operands[4]) :
7090       static_cast<ARMOperand &>(*Operands[3]);
7091     const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
7092     // If SubExprVal is a constant we may be able to use a MOV
7093     if (isa<MCConstantExpr>(SubExprVal) &&
7094         Inst.getOperand(0).getReg() != ARM::PC &&
7095         Inst.getOperand(0).getReg() != ARM::SP) {
7096       int64_t Value =
7097         (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
7098       bool UseMov  = true;
7099       bool MovHasS = true;
7100       if (Inst.getOpcode() == ARM::LDRConstPool) {
7101         // ARM Constant
7102         if (ARM_AM::getSOImmVal(Value) != -1) {
7103           Value = ARM_AM::getSOImmVal(Value);
7104           TmpInst.setOpcode(ARM::MOVi);
7105         }
7106         else if (ARM_AM::getSOImmVal(~Value) != -1) {
7107           Value = ARM_AM::getSOImmVal(~Value);
7108           TmpInst.setOpcode(ARM::MVNi);
7109         }
7110         else if (hasV6T2Ops() &&
7111                  Value >=0 && Value < 65536) {
7112           TmpInst.setOpcode(ARM::MOVi16);
7113           MovHasS = false;
7114         }
7115         else
7116           UseMov = false;
7117       }
7118       else {
7119         // Thumb/Thumb2 Constant
7120         if (hasThumb2() &&
7121             ARM_AM::getT2SOImmVal(Value) != -1)
7122           TmpInst.setOpcode(ARM::t2MOVi);
7123         else if (hasThumb2() &&
7124                  ARM_AM::getT2SOImmVal(~Value) != -1) {
7125           TmpInst.setOpcode(ARM::t2MVNi);
7126           Value = ~Value;
7127         }
7128         else if (hasV8MBaseline() &&
7129                  Value >=0 && Value < 65536) {
7130           TmpInst.setOpcode(ARM::t2MOVi16);
7131           MovHasS = false;
7132         }
7133         else
7134           UseMov = false;
7135       }
7136       if (UseMov) {
7137         TmpInst.addOperand(Inst.getOperand(0));           // Rt
7138         TmpInst.addOperand(MCOperand::createImm(Value));  // Immediate
7139         TmpInst.addOperand(Inst.getOperand(2));           // CondCode
7140         TmpInst.addOperand(Inst.getOperand(3));           // CondCode
7141         if (MovHasS)
7142           TmpInst.addOperand(MCOperand::createReg(0));    // S
7143         Inst = TmpInst;
7144         return true;
7145       }
7146     }
7147     // No opportunity to use MOV/MVN create constant pool
7148     const MCExpr *CPLoc =
7149       getTargetStreamer().addConstantPoolEntry(SubExprVal,
7150                                                PoolOperand.getStartLoc());
7151     TmpInst.addOperand(Inst.getOperand(0));           // Rt
7152     TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
7153     if (TmpInst.getOpcode() == ARM::LDRi12)
7154       TmpInst.addOperand(MCOperand::createImm(0));    // unused offset
7155     TmpInst.addOperand(Inst.getOperand(2));           // CondCode
7156     TmpInst.addOperand(Inst.getOperand(3));           // CondCode
7157     Inst = TmpInst;
7158     return true;
7159   }
7160   // Handle NEON VST complex aliases.
7161   case ARM::VST1LNdWB_register_Asm_8:
7162   case ARM::VST1LNdWB_register_Asm_16:
7163   case ARM::VST1LNdWB_register_Asm_32: {
7164     MCInst TmpInst;
7165     // Shuffle the operands around so the lane index operand is in the
7166     // right place.
7167     unsigned Spacing;
7168     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7169     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7170     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7171     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7172     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7173     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7174     TmpInst.addOperand(Inst.getOperand(1)); // lane
7175     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7176     TmpInst.addOperand(Inst.getOperand(6));
7177     Inst = TmpInst;
7178     return true;
7179   }
7180 
7181   case ARM::VST2LNdWB_register_Asm_8:
7182   case ARM::VST2LNdWB_register_Asm_16:
7183   case ARM::VST2LNdWB_register_Asm_32:
7184   case ARM::VST2LNqWB_register_Asm_16:
7185   case ARM::VST2LNqWB_register_Asm_32: {
7186     MCInst TmpInst;
7187     // Shuffle the operands around so the lane index operand is in the
7188     // right place.
7189     unsigned Spacing;
7190     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7191     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7192     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7193     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7194     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7195     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7196     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7197                                             Spacing));
7198     TmpInst.addOperand(Inst.getOperand(1)); // lane
7199     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7200     TmpInst.addOperand(Inst.getOperand(6));
7201     Inst = TmpInst;
7202     return true;
7203   }
7204 
7205   case ARM::VST3LNdWB_register_Asm_8:
7206   case ARM::VST3LNdWB_register_Asm_16:
7207   case ARM::VST3LNdWB_register_Asm_32:
7208   case ARM::VST3LNqWB_register_Asm_16:
7209   case ARM::VST3LNqWB_register_Asm_32: {
7210     MCInst TmpInst;
7211     // Shuffle the operands around so the lane index operand is in the
7212     // right place.
7213     unsigned Spacing;
7214     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7215     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7216     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7217     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7218     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7219     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7220     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7221                                             Spacing));
7222     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7223                                             Spacing * 2));
7224     TmpInst.addOperand(Inst.getOperand(1)); // lane
7225     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7226     TmpInst.addOperand(Inst.getOperand(6));
7227     Inst = TmpInst;
7228     return true;
7229   }
7230 
7231   case ARM::VST4LNdWB_register_Asm_8:
7232   case ARM::VST4LNdWB_register_Asm_16:
7233   case ARM::VST4LNdWB_register_Asm_32:
7234   case ARM::VST4LNqWB_register_Asm_16:
7235   case ARM::VST4LNqWB_register_Asm_32: {
7236     MCInst TmpInst;
7237     // Shuffle the operands around so the lane index operand is in the
7238     // right place.
7239     unsigned Spacing;
7240     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7241     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7242     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7243     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7244     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7245     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7246     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7247                                             Spacing));
7248     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7249                                             Spacing * 2));
7250     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7251                                             Spacing * 3));
7252     TmpInst.addOperand(Inst.getOperand(1)); // lane
7253     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7254     TmpInst.addOperand(Inst.getOperand(6));
7255     Inst = TmpInst;
7256     return true;
7257   }
7258 
7259   case ARM::VST1LNdWB_fixed_Asm_8:
7260   case ARM::VST1LNdWB_fixed_Asm_16:
7261   case ARM::VST1LNdWB_fixed_Asm_32: {
7262     MCInst TmpInst;
7263     // Shuffle the operands around so the lane index operand is in the
7264     // right place.
7265     unsigned Spacing;
7266     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7267     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7268     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7269     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7270     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7271     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7272     TmpInst.addOperand(Inst.getOperand(1)); // lane
7273     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7274     TmpInst.addOperand(Inst.getOperand(5));
7275     Inst = TmpInst;
7276     return true;
7277   }
7278 
7279   case ARM::VST2LNdWB_fixed_Asm_8:
7280   case ARM::VST2LNdWB_fixed_Asm_16:
7281   case ARM::VST2LNdWB_fixed_Asm_32:
7282   case ARM::VST2LNqWB_fixed_Asm_16:
7283   case ARM::VST2LNqWB_fixed_Asm_32: {
7284     MCInst TmpInst;
7285     // Shuffle the operands around so the lane index operand is in the
7286     // right place.
7287     unsigned Spacing;
7288     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7289     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7290     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7291     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7292     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7293     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7294     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7295                                             Spacing));
7296     TmpInst.addOperand(Inst.getOperand(1)); // lane
7297     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7298     TmpInst.addOperand(Inst.getOperand(5));
7299     Inst = TmpInst;
7300     return true;
7301   }
7302 
7303   case ARM::VST3LNdWB_fixed_Asm_8:
7304   case ARM::VST3LNdWB_fixed_Asm_16:
7305   case ARM::VST3LNdWB_fixed_Asm_32:
7306   case ARM::VST3LNqWB_fixed_Asm_16:
7307   case ARM::VST3LNqWB_fixed_Asm_32: {
7308     MCInst TmpInst;
7309     // Shuffle the operands around so the lane index operand is in the
7310     // right place.
7311     unsigned Spacing;
7312     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7313     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7314     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7315     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7316     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7317     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7318     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7319                                             Spacing));
7320     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7321                                             Spacing * 2));
7322     TmpInst.addOperand(Inst.getOperand(1)); // lane
7323     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7324     TmpInst.addOperand(Inst.getOperand(5));
7325     Inst = TmpInst;
7326     return true;
7327   }
7328 
7329   case ARM::VST4LNdWB_fixed_Asm_8:
7330   case ARM::VST4LNdWB_fixed_Asm_16:
7331   case ARM::VST4LNdWB_fixed_Asm_32:
7332   case ARM::VST4LNqWB_fixed_Asm_16:
7333   case ARM::VST4LNqWB_fixed_Asm_32: {
7334     MCInst TmpInst;
7335     // Shuffle the operands around so the lane index operand is in the
7336     // right place.
7337     unsigned Spacing;
7338     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7339     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7340     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7341     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7342     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7343     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7344     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7345                                             Spacing));
7346     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7347                                             Spacing * 2));
7348     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7349                                             Spacing * 3));
7350     TmpInst.addOperand(Inst.getOperand(1)); // lane
7351     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7352     TmpInst.addOperand(Inst.getOperand(5));
7353     Inst = TmpInst;
7354     return true;
7355   }
7356 
7357   case ARM::VST1LNdAsm_8:
7358   case ARM::VST1LNdAsm_16:
7359   case ARM::VST1LNdAsm_32: {
7360     MCInst TmpInst;
7361     // Shuffle the operands around so the lane index operand is in the
7362     // right place.
7363     unsigned Spacing;
7364     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7365     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7366     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7367     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7368     TmpInst.addOperand(Inst.getOperand(1)); // lane
7369     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7370     TmpInst.addOperand(Inst.getOperand(5));
7371     Inst = TmpInst;
7372     return true;
7373   }
7374 
7375   case ARM::VST2LNdAsm_8:
7376   case ARM::VST2LNdAsm_16:
7377   case ARM::VST2LNdAsm_32:
7378   case ARM::VST2LNqAsm_16:
7379   case ARM::VST2LNqAsm_32: {
7380     MCInst TmpInst;
7381     // Shuffle the operands around so the lane index operand is in the
7382     // right place.
7383     unsigned Spacing;
7384     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7385     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7386     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7387     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7388     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7389                                             Spacing));
7390     TmpInst.addOperand(Inst.getOperand(1)); // lane
7391     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7392     TmpInst.addOperand(Inst.getOperand(5));
7393     Inst = TmpInst;
7394     return true;
7395   }
7396 
7397   case ARM::VST3LNdAsm_8:
7398   case ARM::VST3LNdAsm_16:
7399   case ARM::VST3LNdAsm_32:
7400   case ARM::VST3LNqAsm_16:
7401   case ARM::VST3LNqAsm_32: {
7402     MCInst TmpInst;
7403     // Shuffle the operands around so the lane index operand is in the
7404     // right place.
7405     unsigned Spacing;
7406     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7407     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7408     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7409     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7410     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7411                                             Spacing));
7412     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7413                                             Spacing * 2));
7414     TmpInst.addOperand(Inst.getOperand(1)); // lane
7415     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7416     TmpInst.addOperand(Inst.getOperand(5));
7417     Inst = TmpInst;
7418     return true;
7419   }
7420 
7421   case ARM::VST4LNdAsm_8:
7422   case ARM::VST4LNdAsm_16:
7423   case ARM::VST4LNdAsm_32:
7424   case ARM::VST4LNqAsm_16:
7425   case ARM::VST4LNqAsm_32: {
7426     MCInst TmpInst;
7427     // Shuffle the operands around so the lane index operand is in the
7428     // right place.
7429     unsigned Spacing;
7430     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7431     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7432     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7433     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7434     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7435                                             Spacing));
7436     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7437                                             Spacing * 2));
7438     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7439                                             Spacing * 3));
7440     TmpInst.addOperand(Inst.getOperand(1)); // lane
7441     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7442     TmpInst.addOperand(Inst.getOperand(5));
7443     Inst = TmpInst;
7444     return true;
7445   }
7446 
7447   // Handle NEON VLD complex aliases.
7448   case ARM::VLD1LNdWB_register_Asm_8:
7449   case ARM::VLD1LNdWB_register_Asm_16:
7450   case ARM::VLD1LNdWB_register_Asm_32: {
7451     MCInst TmpInst;
7452     // Shuffle the operands around so the lane index operand is in the
7453     // right place.
7454     unsigned Spacing;
7455     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7456     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7457     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7458     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7459     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7460     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7461     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7462     TmpInst.addOperand(Inst.getOperand(1)); // lane
7463     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7464     TmpInst.addOperand(Inst.getOperand(6));
7465     Inst = TmpInst;
7466     return true;
7467   }
7468 
7469   case ARM::VLD2LNdWB_register_Asm_8:
7470   case ARM::VLD2LNdWB_register_Asm_16:
7471   case ARM::VLD2LNdWB_register_Asm_32:
7472   case ARM::VLD2LNqWB_register_Asm_16:
7473   case ARM::VLD2LNqWB_register_Asm_32: {
7474     MCInst TmpInst;
7475     // Shuffle the operands around so the lane index operand is in the
7476     // right place.
7477     unsigned Spacing;
7478     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7479     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7480     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7481                                             Spacing));
7482     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7483     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7484     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7485     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7486     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7487     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7488                                             Spacing));
7489     TmpInst.addOperand(Inst.getOperand(1)); // lane
7490     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7491     TmpInst.addOperand(Inst.getOperand(6));
7492     Inst = TmpInst;
7493     return true;
7494   }
7495 
7496   case ARM::VLD3LNdWB_register_Asm_8:
7497   case ARM::VLD3LNdWB_register_Asm_16:
7498   case ARM::VLD3LNdWB_register_Asm_32:
7499   case ARM::VLD3LNqWB_register_Asm_16:
7500   case ARM::VLD3LNqWB_register_Asm_32: {
7501     MCInst TmpInst;
7502     // Shuffle the operands around so the lane index operand is in the
7503     // right place.
7504     unsigned Spacing;
7505     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7506     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7507     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7508                                             Spacing));
7509     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7510                                             Spacing * 2));
7511     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7512     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7513     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7514     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7515     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7516     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7517                                             Spacing));
7518     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7519                                             Spacing * 2));
7520     TmpInst.addOperand(Inst.getOperand(1)); // lane
7521     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7522     TmpInst.addOperand(Inst.getOperand(6));
7523     Inst = TmpInst;
7524     return true;
7525   }
7526 
7527   case ARM::VLD4LNdWB_register_Asm_8:
7528   case ARM::VLD4LNdWB_register_Asm_16:
7529   case ARM::VLD4LNdWB_register_Asm_32:
7530   case ARM::VLD4LNqWB_register_Asm_16:
7531   case ARM::VLD4LNqWB_register_Asm_32: {
7532     MCInst TmpInst;
7533     // Shuffle the operands around so the lane index operand is in the
7534     // right place.
7535     unsigned Spacing;
7536     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7537     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7538     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7539                                             Spacing));
7540     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7541                                             Spacing * 2));
7542     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7543                                             Spacing * 3));
7544     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7545     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7546     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7547     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7548     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7549     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7550                                             Spacing));
7551     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7552                                             Spacing * 2));
7553     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7554                                             Spacing * 3));
7555     TmpInst.addOperand(Inst.getOperand(1)); // lane
7556     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7557     TmpInst.addOperand(Inst.getOperand(6));
7558     Inst = TmpInst;
7559     return true;
7560   }
7561 
7562   case ARM::VLD1LNdWB_fixed_Asm_8:
7563   case ARM::VLD1LNdWB_fixed_Asm_16:
7564   case ARM::VLD1LNdWB_fixed_Asm_32: {
7565     MCInst TmpInst;
7566     // Shuffle the operands around so the lane index operand is in the
7567     // right place.
7568     unsigned Spacing;
7569     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7570     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7571     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7572     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7573     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7574     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7575     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7576     TmpInst.addOperand(Inst.getOperand(1)); // lane
7577     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7578     TmpInst.addOperand(Inst.getOperand(5));
7579     Inst = TmpInst;
7580     return true;
7581   }
7582 
7583   case ARM::VLD2LNdWB_fixed_Asm_8:
7584   case ARM::VLD2LNdWB_fixed_Asm_16:
7585   case ARM::VLD2LNdWB_fixed_Asm_32:
7586   case ARM::VLD2LNqWB_fixed_Asm_16:
7587   case ARM::VLD2LNqWB_fixed_Asm_32: {
7588     MCInst TmpInst;
7589     // Shuffle the operands around so the lane index operand is in the
7590     // right place.
7591     unsigned Spacing;
7592     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7593     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7594     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7595                                             Spacing));
7596     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7597     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7598     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7599     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7600     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7601     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7602                                             Spacing));
7603     TmpInst.addOperand(Inst.getOperand(1)); // lane
7604     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7605     TmpInst.addOperand(Inst.getOperand(5));
7606     Inst = TmpInst;
7607     return true;
7608   }
7609 
7610   case ARM::VLD3LNdWB_fixed_Asm_8:
7611   case ARM::VLD3LNdWB_fixed_Asm_16:
7612   case ARM::VLD3LNdWB_fixed_Asm_32:
7613   case ARM::VLD3LNqWB_fixed_Asm_16:
7614   case ARM::VLD3LNqWB_fixed_Asm_32: {
7615     MCInst TmpInst;
7616     // Shuffle the operands around so the lane index operand is in the
7617     // right place.
7618     unsigned Spacing;
7619     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7620     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7621     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7622                                             Spacing));
7623     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7624                                             Spacing * 2));
7625     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7626     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7627     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7628     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7629     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7630     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7631                                             Spacing));
7632     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7633                                             Spacing * 2));
7634     TmpInst.addOperand(Inst.getOperand(1)); // lane
7635     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7636     TmpInst.addOperand(Inst.getOperand(5));
7637     Inst = TmpInst;
7638     return true;
7639   }
7640 
7641   case ARM::VLD4LNdWB_fixed_Asm_8:
7642   case ARM::VLD4LNdWB_fixed_Asm_16:
7643   case ARM::VLD4LNdWB_fixed_Asm_32:
7644   case ARM::VLD4LNqWB_fixed_Asm_16:
7645   case ARM::VLD4LNqWB_fixed_Asm_32: {
7646     MCInst TmpInst;
7647     // Shuffle the operands around so the lane index operand is in the
7648     // right place.
7649     unsigned Spacing;
7650     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7651     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7652     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7653                                             Spacing));
7654     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7655                                             Spacing * 2));
7656     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7657                                             Spacing * 3));
7658     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7659     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7660     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7661     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7662     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7663     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7664                                             Spacing));
7665     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7666                                             Spacing * 2));
7667     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7668                                             Spacing * 3));
7669     TmpInst.addOperand(Inst.getOperand(1)); // lane
7670     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7671     TmpInst.addOperand(Inst.getOperand(5));
7672     Inst = TmpInst;
7673     return true;
7674   }
7675 
7676   case ARM::VLD1LNdAsm_8:
7677   case ARM::VLD1LNdAsm_16:
7678   case ARM::VLD1LNdAsm_32: {
7679     MCInst TmpInst;
7680     // Shuffle the operands around so the lane index operand is in the
7681     // right place.
7682     unsigned Spacing;
7683     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7684     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7685     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7686     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7687     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7688     TmpInst.addOperand(Inst.getOperand(1)); // lane
7689     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7690     TmpInst.addOperand(Inst.getOperand(5));
7691     Inst = TmpInst;
7692     return true;
7693   }
7694 
7695   case ARM::VLD2LNdAsm_8:
7696   case ARM::VLD2LNdAsm_16:
7697   case ARM::VLD2LNdAsm_32:
7698   case ARM::VLD2LNqAsm_16:
7699   case ARM::VLD2LNqAsm_32: {
7700     MCInst TmpInst;
7701     // Shuffle the operands around so the lane index operand is in the
7702     // right place.
7703     unsigned Spacing;
7704     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7705     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7706     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7707                                             Spacing));
7708     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7709     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7710     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7711     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7712                                             Spacing));
7713     TmpInst.addOperand(Inst.getOperand(1)); // lane
7714     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7715     TmpInst.addOperand(Inst.getOperand(5));
7716     Inst = TmpInst;
7717     return true;
7718   }
7719 
7720   case ARM::VLD3LNdAsm_8:
7721   case ARM::VLD3LNdAsm_16:
7722   case ARM::VLD3LNdAsm_32:
7723   case ARM::VLD3LNqAsm_16:
7724   case ARM::VLD3LNqAsm_32: {
7725     MCInst TmpInst;
7726     // Shuffle the operands around so the lane index operand is in the
7727     // right place.
7728     unsigned Spacing;
7729     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7730     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7731     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7732                                             Spacing));
7733     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7734                                             Spacing * 2));
7735     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7736     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7737     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7738     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7739                                             Spacing));
7740     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7741                                             Spacing * 2));
7742     TmpInst.addOperand(Inst.getOperand(1)); // lane
7743     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7744     TmpInst.addOperand(Inst.getOperand(5));
7745     Inst = TmpInst;
7746     return true;
7747   }
7748 
7749   case ARM::VLD4LNdAsm_8:
7750   case ARM::VLD4LNdAsm_16:
7751   case ARM::VLD4LNdAsm_32:
7752   case ARM::VLD4LNqAsm_16:
7753   case ARM::VLD4LNqAsm_32: {
7754     MCInst TmpInst;
7755     // Shuffle the operands around so the lane index operand is in the
7756     // right place.
7757     unsigned Spacing;
7758     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7759     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7760     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7761                                             Spacing));
7762     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7763                                             Spacing * 2));
7764     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7765                                             Spacing * 3));
7766     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7767     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7768     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7769     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7770                                             Spacing));
7771     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7772                                             Spacing * 2));
7773     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7774                                             Spacing * 3));
7775     TmpInst.addOperand(Inst.getOperand(1)); // lane
7776     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7777     TmpInst.addOperand(Inst.getOperand(5));
7778     Inst = TmpInst;
7779     return true;
7780   }
7781 
7782   // VLD3DUP single 3-element structure to all lanes instructions.
7783   case ARM::VLD3DUPdAsm_8:
7784   case ARM::VLD3DUPdAsm_16:
7785   case ARM::VLD3DUPdAsm_32:
7786   case ARM::VLD3DUPqAsm_8:
7787   case ARM::VLD3DUPqAsm_16:
7788   case ARM::VLD3DUPqAsm_32: {
7789     MCInst TmpInst;
7790     unsigned Spacing;
7791     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7792     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7793     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7794                                             Spacing));
7795     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7796                                             Spacing * 2));
7797     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7798     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7799     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7800     TmpInst.addOperand(Inst.getOperand(4));
7801     Inst = TmpInst;
7802     return true;
7803   }
7804 
7805   case ARM::VLD3DUPdWB_fixed_Asm_8:
7806   case ARM::VLD3DUPdWB_fixed_Asm_16:
7807   case ARM::VLD3DUPdWB_fixed_Asm_32:
7808   case ARM::VLD3DUPqWB_fixed_Asm_8:
7809   case ARM::VLD3DUPqWB_fixed_Asm_16:
7810   case ARM::VLD3DUPqWB_fixed_Asm_32: {
7811     MCInst TmpInst;
7812     unsigned Spacing;
7813     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7814     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7815     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7816                                             Spacing));
7817     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7818                                             Spacing * 2));
7819     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7820     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7821     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7822     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7823     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7824     TmpInst.addOperand(Inst.getOperand(4));
7825     Inst = TmpInst;
7826     return true;
7827   }
7828 
7829   case ARM::VLD3DUPdWB_register_Asm_8:
7830   case ARM::VLD3DUPdWB_register_Asm_16:
7831   case ARM::VLD3DUPdWB_register_Asm_32:
7832   case ARM::VLD3DUPqWB_register_Asm_8:
7833   case ARM::VLD3DUPqWB_register_Asm_16:
7834   case ARM::VLD3DUPqWB_register_Asm_32: {
7835     MCInst TmpInst;
7836     unsigned Spacing;
7837     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7838     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7839     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7840                                             Spacing));
7841     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7842                                             Spacing * 2));
7843     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7844     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7845     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7846     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7847     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7848     TmpInst.addOperand(Inst.getOperand(5));
7849     Inst = TmpInst;
7850     return true;
7851   }
7852 
7853   // VLD3 multiple 3-element structure instructions.
7854   case ARM::VLD3dAsm_8:
7855   case ARM::VLD3dAsm_16:
7856   case ARM::VLD3dAsm_32:
7857   case ARM::VLD3qAsm_8:
7858   case ARM::VLD3qAsm_16:
7859   case ARM::VLD3qAsm_32: {
7860     MCInst TmpInst;
7861     unsigned Spacing;
7862     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7863     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7864     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7865                                             Spacing));
7866     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7867                                             Spacing * 2));
7868     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7869     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7870     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7871     TmpInst.addOperand(Inst.getOperand(4));
7872     Inst = TmpInst;
7873     return true;
7874   }
7875 
7876   case ARM::VLD3dWB_fixed_Asm_8:
7877   case ARM::VLD3dWB_fixed_Asm_16:
7878   case ARM::VLD3dWB_fixed_Asm_32:
7879   case ARM::VLD3qWB_fixed_Asm_8:
7880   case ARM::VLD3qWB_fixed_Asm_16:
7881   case ARM::VLD3qWB_fixed_Asm_32: {
7882     MCInst TmpInst;
7883     unsigned Spacing;
7884     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7885     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7886     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7887                                             Spacing));
7888     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7889                                             Spacing * 2));
7890     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7891     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7892     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7893     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7894     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7895     TmpInst.addOperand(Inst.getOperand(4));
7896     Inst = TmpInst;
7897     return true;
7898   }
7899 
7900   case ARM::VLD3dWB_register_Asm_8:
7901   case ARM::VLD3dWB_register_Asm_16:
7902   case ARM::VLD3dWB_register_Asm_32:
7903   case ARM::VLD3qWB_register_Asm_8:
7904   case ARM::VLD3qWB_register_Asm_16:
7905   case ARM::VLD3qWB_register_Asm_32: {
7906     MCInst TmpInst;
7907     unsigned Spacing;
7908     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7909     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7910     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7911                                             Spacing));
7912     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7913                                             Spacing * 2));
7914     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7915     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7916     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7917     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7918     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7919     TmpInst.addOperand(Inst.getOperand(5));
7920     Inst = TmpInst;
7921     return true;
7922   }
7923 
7924   // VLD4DUP single 3-element structure to all lanes instructions.
7925   case ARM::VLD4DUPdAsm_8:
7926   case ARM::VLD4DUPdAsm_16:
7927   case ARM::VLD4DUPdAsm_32:
7928   case ARM::VLD4DUPqAsm_8:
7929   case ARM::VLD4DUPqAsm_16:
7930   case ARM::VLD4DUPqAsm_32: {
7931     MCInst TmpInst;
7932     unsigned Spacing;
7933     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7934     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7935     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7936                                             Spacing));
7937     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7938                                             Spacing * 2));
7939     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7940                                             Spacing * 3));
7941     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7942     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7943     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7944     TmpInst.addOperand(Inst.getOperand(4));
7945     Inst = TmpInst;
7946     return true;
7947   }
7948 
7949   case ARM::VLD4DUPdWB_fixed_Asm_8:
7950   case ARM::VLD4DUPdWB_fixed_Asm_16:
7951   case ARM::VLD4DUPdWB_fixed_Asm_32:
7952   case ARM::VLD4DUPqWB_fixed_Asm_8:
7953   case ARM::VLD4DUPqWB_fixed_Asm_16:
7954   case ARM::VLD4DUPqWB_fixed_Asm_32: {
7955     MCInst TmpInst;
7956     unsigned Spacing;
7957     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7958     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7959     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7960                                             Spacing));
7961     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7962                                             Spacing * 2));
7963     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7964                                             Spacing * 3));
7965     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7966     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7967     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7968     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7969     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7970     TmpInst.addOperand(Inst.getOperand(4));
7971     Inst = TmpInst;
7972     return true;
7973   }
7974 
7975   case ARM::VLD4DUPdWB_register_Asm_8:
7976   case ARM::VLD4DUPdWB_register_Asm_16:
7977   case ARM::VLD4DUPdWB_register_Asm_32:
7978   case ARM::VLD4DUPqWB_register_Asm_8:
7979   case ARM::VLD4DUPqWB_register_Asm_16:
7980   case ARM::VLD4DUPqWB_register_Asm_32: {
7981     MCInst TmpInst;
7982     unsigned Spacing;
7983     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7984     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7985     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7986                                             Spacing));
7987     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7988                                             Spacing * 2));
7989     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7990                                             Spacing * 3));
7991     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7992     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7993     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7994     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7995     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7996     TmpInst.addOperand(Inst.getOperand(5));
7997     Inst = TmpInst;
7998     return true;
7999   }
8000 
8001   // VLD4 multiple 4-element structure instructions.
8002   case ARM::VLD4dAsm_8:
8003   case ARM::VLD4dAsm_16:
8004   case ARM::VLD4dAsm_32:
8005   case ARM::VLD4qAsm_8:
8006   case ARM::VLD4qAsm_16:
8007   case ARM::VLD4qAsm_32: {
8008     MCInst TmpInst;
8009     unsigned Spacing;
8010     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8011     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8012     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8013                                             Spacing));
8014     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8015                                             Spacing * 2));
8016     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8017                                             Spacing * 3));
8018     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8019     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8020     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8021     TmpInst.addOperand(Inst.getOperand(4));
8022     Inst = TmpInst;
8023     return true;
8024   }
8025 
8026   case ARM::VLD4dWB_fixed_Asm_8:
8027   case ARM::VLD4dWB_fixed_Asm_16:
8028   case ARM::VLD4dWB_fixed_Asm_32:
8029   case ARM::VLD4qWB_fixed_Asm_8:
8030   case ARM::VLD4qWB_fixed_Asm_16:
8031   case ARM::VLD4qWB_fixed_Asm_32: {
8032     MCInst TmpInst;
8033     unsigned Spacing;
8034     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8035     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8036     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8037                                             Spacing));
8038     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8039                                             Spacing * 2));
8040     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8041                                             Spacing * 3));
8042     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8043     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8044     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8045     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8046     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8047     TmpInst.addOperand(Inst.getOperand(4));
8048     Inst = TmpInst;
8049     return true;
8050   }
8051 
8052   case ARM::VLD4dWB_register_Asm_8:
8053   case ARM::VLD4dWB_register_Asm_16:
8054   case ARM::VLD4dWB_register_Asm_32:
8055   case ARM::VLD4qWB_register_Asm_8:
8056   case ARM::VLD4qWB_register_Asm_16:
8057   case ARM::VLD4qWB_register_Asm_32: {
8058     MCInst TmpInst;
8059     unsigned Spacing;
8060     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8061     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8062     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8063                                             Spacing));
8064     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8065                                             Spacing * 2));
8066     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8067                                             Spacing * 3));
8068     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8069     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8070     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8071     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8072     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8073     TmpInst.addOperand(Inst.getOperand(5));
8074     Inst = TmpInst;
8075     return true;
8076   }
8077 
8078   // VST3 multiple 3-element structure instructions.
8079   case ARM::VST3dAsm_8:
8080   case ARM::VST3dAsm_16:
8081   case ARM::VST3dAsm_32:
8082   case ARM::VST3qAsm_8:
8083   case ARM::VST3qAsm_16:
8084   case ARM::VST3qAsm_32: {
8085     MCInst TmpInst;
8086     unsigned Spacing;
8087     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8088     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8089     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8090     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8091     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8092                                             Spacing));
8093     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8094                                             Spacing * 2));
8095     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8096     TmpInst.addOperand(Inst.getOperand(4));
8097     Inst = TmpInst;
8098     return true;
8099   }
8100 
8101   case ARM::VST3dWB_fixed_Asm_8:
8102   case ARM::VST3dWB_fixed_Asm_16:
8103   case ARM::VST3dWB_fixed_Asm_32:
8104   case ARM::VST3qWB_fixed_Asm_8:
8105   case ARM::VST3qWB_fixed_Asm_16:
8106   case ARM::VST3qWB_fixed_Asm_32: {
8107     MCInst TmpInst;
8108     unsigned Spacing;
8109     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8110     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8111     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8112     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8113     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8114     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8115     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8116                                             Spacing));
8117     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8118                                             Spacing * 2));
8119     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8120     TmpInst.addOperand(Inst.getOperand(4));
8121     Inst = TmpInst;
8122     return true;
8123   }
8124 
8125   case ARM::VST3dWB_register_Asm_8:
8126   case ARM::VST3dWB_register_Asm_16:
8127   case ARM::VST3dWB_register_Asm_32:
8128   case ARM::VST3qWB_register_Asm_8:
8129   case ARM::VST3qWB_register_Asm_16:
8130   case ARM::VST3qWB_register_Asm_32: {
8131     MCInst TmpInst;
8132     unsigned Spacing;
8133     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8134     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8135     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8136     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8137     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8138     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8139     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8140                                             Spacing));
8141     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8142                                             Spacing * 2));
8143     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8144     TmpInst.addOperand(Inst.getOperand(5));
8145     Inst = TmpInst;
8146     return true;
8147   }
8148 
8149   // VST4 multiple 3-element structure instructions.
8150   case ARM::VST4dAsm_8:
8151   case ARM::VST4dAsm_16:
8152   case ARM::VST4dAsm_32:
8153   case ARM::VST4qAsm_8:
8154   case ARM::VST4qAsm_16:
8155   case ARM::VST4qAsm_32: {
8156     MCInst TmpInst;
8157     unsigned Spacing;
8158     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8159     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8160     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8161     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8162     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8163                                             Spacing));
8164     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8165                                             Spacing * 2));
8166     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8167                                             Spacing * 3));
8168     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8169     TmpInst.addOperand(Inst.getOperand(4));
8170     Inst = TmpInst;
8171     return true;
8172   }
8173 
8174   case ARM::VST4dWB_fixed_Asm_8:
8175   case ARM::VST4dWB_fixed_Asm_16:
8176   case ARM::VST4dWB_fixed_Asm_32:
8177   case ARM::VST4qWB_fixed_Asm_8:
8178   case ARM::VST4qWB_fixed_Asm_16:
8179   case ARM::VST4qWB_fixed_Asm_32: {
8180     MCInst TmpInst;
8181     unsigned Spacing;
8182     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8183     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8184     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8185     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8186     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8187     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8188     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8189                                             Spacing));
8190     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8191                                             Spacing * 2));
8192     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8193                                             Spacing * 3));
8194     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8195     TmpInst.addOperand(Inst.getOperand(4));
8196     Inst = TmpInst;
8197     return true;
8198   }
8199 
8200   case ARM::VST4dWB_register_Asm_8:
8201   case ARM::VST4dWB_register_Asm_16:
8202   case ARM::VST4dWB_register_Asm_32:
8203   case ARM::VST4qWB_register_Asm_8:
8204   case ARM::VST4qWB_register_Asm_16:
8205   case ARM::VST4qWB_register_Asm_32: {
8206     MCInst TmpInst;
8207     unsigned Spacing;
8208     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8209     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8210     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8211     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8212     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8213     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8214     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8215                                             Spacing));
8216     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8217                                             Spacing * 2));
8218     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8219                                             Spacing * 3));
8220     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8221     TmpInst.addOperand(Inst.getOperand(5));
8222     Inst = TmpInst;
8223     return true;
8224   }
8225 
8226   // Handle encoding choice for the shift-immediate instructions.
8227   case ARM::t2LSLri:
8228   case ARM::t2LSRri:
8229   case ARM::t2ASRri: {
8230     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8231         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8232         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8233         !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8234           static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
8235       unsigned NewOpc;
8236       switch (Inst.getOpcode()) {
8237       default: llvm_unreachable("unexpected opcode");
8238       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
8239       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
8240       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
8241       }
8242       // The Thumb1 operands aren't in the same order. Awesome, eh?
8243       MCInst TmpInst;
8244       TmpInst.setOpcode(NewOpc);
8245       TmpInst.addOperand(Inst.getOperand(0));
8246       TmpInst.addOperand(Inst.getOperand(5));
8247       TmpInst.addOperand(Inst.getOperand(1));
8248       TmpInst.addOperand(Inst.getOperand(2));
8249       TmpInst.addOperand(Inst.getOperand(3));
8250       TmpInst.addOperand(Inst.getOperand(4));
8251       Inst = TmpInst;
8252       return true;
8253     }
8254     return false;
8255   }
8256 
8257   // Handle the Thumb2 mode MOV complex aliases.
8258   case ARM::t2MOVsr:
8259   case ARM::t2MOVSsr: {
8260     // Which instruction to expand to depends on the CCOut operand and
8261     // whether we're in an IT block if the register operands are low
8262     // registers.
8263     bool isNarrow = false;
8264     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8265         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8266         isARMLowRegister(Inst.getOperand(2).getReg()) &&
8267         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8268         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
8269       isNarrow = true;
8270     MCInst TmpInst;
8271     unsigned newOpc;
8272     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
8273     default: llvm_unreachable("unexpected opcode!");
8274     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
8275     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
8276     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
8277     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
8278     }
8279     TmpInst.setOpcode(newOpc);
8280     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8281     if (isNarrow)
8282       TmpInst.addOperand(MCOperand::createReg(
8283           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8284     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8285     TmpInst.addOperand(Inst.getOperand(2)); // Rm
8286     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8287     TmpInst.addOperand(Inst.getOperand(5));
8288     if (!isNarrow)
8289       TmpInst.addOperand(MCOperand::createReg(
8290           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8291     Inst = TmpInst;
8292     return true;
8293   }
8294   case ARM::t2MOVsi:
8295   case ARM::t2MOVSsi: {
8296     // Which instruction to expand to depends on the CCOut operand and
8297     // whether we're in an IT block if the register operands are low
8298     // registers.
8299     bool isNarrow = false;
8300     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8301         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8302         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
8303       isNarrow = true;
8304     MCInst TmpInst;
8305     unsigned newOpc;
8306     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
8307     default: llvm_unreachable("unexpected opcode!");
8308     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
8309     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
8310     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
8311     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
8312     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
8313     }
8314     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
8315     if (Amount == 32) Amount = 0;
8316     TmpInst.setOpcode(newOpc);
8317     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8318     if (isNarrow)
8319       TmpInst.addOperand(MCOperand::createReg(
8320           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8321     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8322     if (newOpc != ARM::t2RRX)
8323       TmpInst.addOperand(MCOperand::createImm(Amount));
8324     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8325     TmpInst.addOperand(Inst.getOperand(4));
8326     if (!isNarrow)
8327       TmpInst.addOperand(MCOperand::createReg(
8328           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8329     Inst = TmpInst;
8330     return true;
8331   }
8332   // Handle the ARM mode MOV complex aliases.
8333   case ARM::ASRr:
8334   case ARM::LSRr:
8335   case ARM::LSLr:
8336   case ARM::RORr: {
8337     ARM_AM::ShiftOpc ShiftTy;
8338     switch(Inst.getOpcode()) {
8339     default: llvm_unreachable("unexpected opcode!");
8340     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
8341     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
8342     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
8343     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
8344     }
8345     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
8346     MCInst TmpInst;
8347     TmpInst.setOpcode(ARM::MOVsr);
8348     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8349     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8350     TmpInst.addOperand(Inst.getOperand(2)); // Rm
8351     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8352     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8353     TmpInst.addOperand(Inst.getOperand(4));
8354     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8355     Inst = TmpInst;
8356     return true;
8357   }
8358   case ARM::ASRi:
8359   case ARM::LSRi:
8360   case ARM::LSLi:
8361   case ARM::RORi: {
8362     ARM_AM::ShiftOpc ShiftTy;
8363     switch(Inst.getOpcode()) {
8364     default: llvm_unreachable("unexpected opcode!");
8365     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
8366     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
8367     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
8368     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
8369     }
8370     // A shift by zero is a plain MOVr, not a MOVsi.
8371     unsigned Amt = Inst.getOperand(2).getImm();
8372     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
8373     // A shift by 32 should be encoded as 0 when permitted
8374     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
8375       Amt = 0;
8376     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
8377     MCInst TmpInst;
8378     TmpInst.setOpcode(Opc);
8379     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8380     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8381     if (Opc == ARM::MOVsi)
8382       TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8383     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8384     TmpInst.addOperand(Inst.getOperand(4));
8385     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8386     Inst = TmpInst;
8387     return true;
8388   }
8389   case ARM::RRXi: {
8390     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8391     MCInst TmpInst;
8392     TmpInst.setOpcode(ARM::MOVsi);
8393     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8394     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8395     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8396     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8397     TmpInst.addOperand(Inst.getOperand(3));
8398     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8399     Inst = TmpInst;
8400     return true;
8401   }
8402   case ARM::t2LDMIA_UPD: {
8403     // If this is a load of a single register, then we should use
8404     // a post-indexed LDR instruction instead, per the ARM ARM.
8405     if (Inst.getNumOperands() != 5)
8406       return false;
8407     MCInst TmpInst;
8408     TmpInst.setOpcode(ARM::t2LDR_POST);
8409     TmpInst.addOperand(Inst.getOperand(4)); // Rt
8410     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8411     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8412     TmpInst.addOperand(MCOperand::createImm(4));
8413     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8414     TmpInst.addOperand(Inst.getOperand(3));
8415     Inst = TmpInst;
8416     return true;
8417   }
8418   case ARM::t2STMDB_UPD: {
8419     // If this is a store of a single register, then we should use
8420     // a pre-indexed STR instruction instead, per the ARM ARM.
8421     if (Inst.getNumOperands() != 5)
8422       return false;
8423     MCInst TmpInst;
8424     TmpInst.setOpcode(ARM::t2STR_PRE);
8425     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8426     TmpInst.addOperand(Inst.getOperand(4)); // Rt
8427     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8428     TmpInst.addOperand(MCOperand::createImm(-4));
8429     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8430     TmpInst.addOperand(Inst.getOperand(3));
8431     Inst = TmpInst;
8432     return true;
8433   }
8434   case ARM::LDMIA_UPD:
8435     // If this is a load of a single register via a 'pop', then we should use
8436     // a post-indexed LDR instruction instead, per the ARM ARM.
8437     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8438         Inst.getNumOperands() == 5) {
8439       MCInst TmpInst;
8440       TmpInst.setOpcode(ARM::LDR_POST_IMM);
8441       TmpInst.addOperand(Inst.getOperand(4)); // Rt
8442       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8443       TmpInst.addOperand(Inst.getOperand(1)); // Rn
8444       TmpInst.addOperand(MCOperand::createReg(0));  // am2offset
8445       TmpInst.addOperand(MCOperand::createImm(4));
8446       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8447       TmpInst.addOperand(Inst.getOperand(3));
8448       Inst = TmpInst;
8449       return true;
8450     }
8451     break;
8452   case ARM::STMDB_UPD:
8453     // If this is a store of a single register via a 'push', then we should use
8454     // a pre-indexed STR instruction instead, per the ARM ARM.
8455     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8456         Inst.getNumOperands() == 5) {
8457       MCInst TmpInst;
8458       TmpInst.setOpcode(ARM::STR_PRE_IMM);
8459       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8460       TmpInst.addOperand(Inst.getOperand(4)); // Rt
8461       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8462       TmpInst.addOperand(MCOperand::createImm(-4));
8463       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8464       TmpInst.addOperand(Inst.getOperand(3));
8465       Inst = TmpInst;
8466     }
8467     break;
8468   case ARM::t2ADDri12:
8469     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8470     // mnemonic was used (not "addw"), encoding T3 is preferred.
8471     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8472         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8473       break;
8474     Inst.setOpcode(ARM::t2ADDri);
8475     Inst.addOperand(MCOperand::createReg(0)); // cc_out
8476     break;
8477   case ARM::t2SUBri12:
8478     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8479     // mnemonic was used (not "subw"), encoding T3 is preferred.
8480     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8481         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8482       break;
8483     Inst.setOpcode(ARM::t2SUBri);
8484     Inst.addOperand(MCOperand::createReg(0)); // cc_out
8485     break;
8486   case ARM::tADDi8:
8487     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8488     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8489     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8490     // to encoding T1 if <Rd> is omitted."
8491     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8492       Inst.setOpcode(ARM::tADDi3);
8493       return true;
8494     }
8495     break;
8496   case ARM::tSUBi8:
8497     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8498     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8499     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8500     // to encoding T1 if <Rd> is omitted."
8501     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8502       Inst.setOpcode(ARM::tSUBi3);
8503       return true;
8504     }
8505     break;
8506   case ARM::t2ADDri:
8507   case ARM::t2SUBri: {
8508     // If the destination and first source operand are the same, and
8509     // the flags are compatible with the current IT status, use encoding T2
8510     // instead of T3. For compatibility with the system 'as'. Make sure the
8511     // wide encoding wasn't explicit.
8512     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8513         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8514         (unsigned)Inst.getOperand(2).getImm() > 255 ||
8515         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8516          (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8517         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8518          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8519       break;
8520     MCInst TmpInst;
8521     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8522                       ARM::tADDi8 : ARM::tSUBi8);
8523     TmpInst.addOperand(Inst.getOperand(0));
8524     TmpInst.addOperand(Inst.getOperand(5));
8525     TmpInst.addOperand(Inst.getOperand(0));
8526     TmpInst.addOperand(Inst.getOperand(2));
8527     TmpInst.addOperand(Inst.getOperand(3));
8528     TmpInst.addOperand(Inst.getOperand(4));
8529     Inst = TmpInst;
8530     return true;
8531   }
8532   case ARM::t2ADDrr: {
8533     // If the destination and first source operand are the same, and
8534     // there's no setting of the flags, use encoding T2 instead of T3.
8535     // Note that this is only for ADD, not SUB. This mirrors the system
8536     // 'as' behaviour.  Also take advantage of ADD being commutative.
8537     // Make sure the wide encoding wasn't explicit.
8538     bool Swap = false;
8539     auto DestReg = Inst.getOperand(0).getReg();
8540     bool Transform = DestReg == Inst.getOperand(1).getReg();
8541     if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
8542       Transform = true;
8543       Swap = true;
8544     }
8545     if (!Transform ||
8546         Inst.getOperand(5).getReg() != 0 ||
8547         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8548          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8549       break;
8550     MCInst TmpInst;
8551     TmpInst.setOpcode(ARM::tADDhirr);
8552     TmpInst.addOperand(Inst.getOperand(0));
8553     TmpInst.addOperand(Inst.getOperand(0));
8554     TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
8555     TmpInst.addOperand(Inst.getOperand(3));
8556     TmpInst.addOperand(Inst.getOperand(4));
8557     Inst = TmpInst;
8558     return true;
8559   }
8560   case ARM::tADDrSP: {
8561     // If the non-SP source operand and the destination operand are not the
8562     // same, we need to use the 32-bit encoding if it's available.
8563     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8564       Inst.setOpcode(ARM::t2ADDrr);
8565       Inst.addOperand(MCOperand::createReg(0)); // cc_out
8566       return true;
8567     }
8568     break;
8569   }
8570   case ARM::tB:
8571     // A Thumb conditional branch outside of an IT block is a tBcc.
8572     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8573       Inst.setOpcode(ARM::tBcc);
8574       return true;
8575     }
8576     break;
8577   case ARM::t2B:
8578     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8579     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8580       Inst.setOpcode(ARM::t2Bcc);
8581       return true;
8582     }
8583     break;
8584   case ARM::t2Bcc:
8585     // If the conditional is AL or we're in an IT block, we really want t2B.
8586     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8587       Inst.setOpcode(ARM::t2B);
8588       return true;
8589     }
8590     break;
8591   case ARM::tBcc:
8592     // If the conditional is AL, we really want tB.
8593     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8594       Inst.setOpcode(ARM::tB);
8595       return true;
8596     }
8597     break;
8598   case ARM::tLDMIA: {
8599     // If the register list contains any high registers, or if the writeback
8600     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8601     // instead if we're in Thumb2. Otherwise, this should have generated
8602     // an error in validateInstruction().
8603     unsigned Rn = Inst.getOperand(0).getReg();
8604     bool hasWritebackToken =
8605         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8606          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8607     bool listContainsBase;
8608     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8609         (!listContainsBase && !hasWritebackToken) ||
8610         (listContainsBase && hasWritebackToken)) {
8611       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8612       assert (isThumbTwo());
8613       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8614       // If we're switching to the updating version, we need to insert
8615       // the writeback tied operand.
8616       if (hasWritebackToken)
8617         Inst.insert(Inst.begin(),
8618                     MCOperand::createReg(Inst.getOperand(0).getReg()));
8619       return true;
8620     }
8621     break;
8622   }
8623   case ARM::tSTMIA_UPD: {
8624     // If the register list contains any high registers, we need to use
8625     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8626     // should have generated an error in validateInstruction().
8627     unsigned Rn = Inst.getOperand(0).getReg();
8628     bool listContainsBase;
8629     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8630       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8631       assert (isThumbTwo());
8632       Inst.setOpcode(ARM::t2STMIA_UPD);
8633       return true;
8634     }
8635     break;
8636   }
8637   case ARM::tPOP: {
8638     bool listContainsBase;
8639     // If the register list contains any high registers, we need to use
8640     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8641     // should have generated an error in validateInstruction().
8642     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8643       return false;
8644     assert (isThumbTwo());
8645     Inst.setOpcode(ARM::t2LDMIA_UPD);
8646     // Add the base register and writeback operands.
8647     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8648     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8649     return true;
8650   }
8651   case ARM::tPUSH: {
8652     bool listContainsBase;
8653     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8654       return false;
8655     assert (isThumbTwo());
8656     Inst.setOpcode(ARM::t2STMDB_UPD);
8657     // Add the base register and writeback operands.
8658     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8659     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8660     return true;
8661   }
8662   case ARM::t2MOVi: {
8663     // If we can use the 16-bit encoding and the user didn't explicitly
8664     // request the 32-bit variant, transform it here.
8665     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8666         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8667         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8668           Inst.getOperand(4).getReg() == ARM::CPSR) ||
8669          (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8670         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8671          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8672       // The operands aren't in the same order for tMOVi8...
8673       MCInst TmpInst;
8674       TmpInst.setOpcode(ARM::tMOVi8);
8675       TmpInst.addOperand(Inst.getOperand(0));
8676       TmpInst.addOperand(Inst.getOperand(4));
8677       TmpInst.addOperand(Inst.getOperand(1));
8678       TmpInst.addOperand(Inst.getOperand(2));
8679       TmpInst.addOperand(Inst.getOperand(3));
8680       Inst = TmpInst;
8681       return true;
8682     }
8683     break;
8684   }
8685   case ARM::t2MOVr: {
8686     // If we can use the 16-bit encoding and the user didn't explicitly
8687     // request the 32-bit variant, transform it here.
8688     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8689         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8690         Inst.getOperand(2).getImm() == ARMCC::AL &&
8691         Inst.getOperand(4).getReg() == ARM::CPSR &&
8692         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8693          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8694       // The operands aren't the same for tMOV[S]r... (no cc_out)
8695       MCInst TmpInst;
8696       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8697       TmpInst.addOperand(Inst.getOperand(0));
8698       TmpInst.addOperand(Inst.getOperand(1));
8699       TmpInst.addOperand(Inst.getOperand(2));
8700       TmpInst.addOperand(Inst.getOperand(3));
8701       Inst = TmpInst;
8702       return true;
8703     }
8704     break;
8705   }
8706   case ARM::t2SXTH:
8707   case ARM::t2SXTB:
8708   case ARM::t2UXTH:
8709   case ARM::t2UXTB: {
8710     // If we can use the 16-bit encoding and the user didn't explicitly
8711     // request the 32-bit variant, transform it here.
8712     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8713         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8714         Inst.getOperand(2).getImm() == 0 &&
8715         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8716          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8717       unsigned NewOpc;
8718       switch (Inst.getOpcode()) {
8719       default: llvm_unreachable("Illegal opcode!");
8720       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8721       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8722       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8723       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8724       }
8725       // The operands aren't the same for thumb1 (no rotate operand).
8726       MCInst TmpInst;
8727       TmpInst.setOpcode(NewOpc);
8728       TmpInst.addOperand(Inst.getOperand(0));
8729       TmpInst.addOperand(Inst.getOperand(1));
8730       TmpInst.addOperand(Inst.getOperand(3));
8731       TmpInst.addOperand(Inst.getOperand(4));
8732       Inst = TmpInst;
8733       return true;
8734     }
8735     break;
8736   }
8737   case ARM::MOVsi: {
8738     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8739     // rrx shifts and asr/lsr of #32 is encoded as 0
8740     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8741       return false;
8742     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8743       // Shifting by zero is accepted as a vanilla 'MOVr'
8744       MCInst TmpInst;
8745       TmpInst.setOpcode(ARM::MOVr);
8746       TmpInst.addOperand(Inst.getOperand(0));
8747       TmpInst.addOperand(Inst.getOperand(1));
8748       TmpInst.addOperand(Inst.getOperand(3));
8749       TmpInst.addOperand(Inst.getOperand(4));
8750       TmpInst.addOperand(Inst.getOperand(5));
8751       Inst = TmpInst;
8752       return true;
8753     }
8754     return false;
8755   }
8756   case ARM::ANDrsi:
8757   case ARM::ORRrsi:
8758   case ARM::EORrsi:
8759   case ARM::BICrsi:
8760   case ARM::SUBrsi:
8761   case ARM::ADDrsi: {
8762     unsigned newOpc;
8763     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8764     if (SOpc == ARM_AM::rrx) return false;
8765     switch (Inst.getOpcode()) {
8766     default: llvm_unreachable("unexpected opcode!");
8767     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8768     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8769     case ARM::EORrsi: newOpc = ARM::EORrr; break;
8770     case ARM::BICrsi: newOpc = ARM::BICrr; break;
8771     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8772     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8773     }
8774     // If the shift is by zero, use the non-shifted instruction definition.
8775     // The exception is for right shifts, where 0 == 32
8776     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8777         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8778       MCInst TmpInst;
8779       TmpInst.setOpcode(newOpc);
8780       TmpInst.addOperand(Inst.getOperand(0));
8781       TmpInst.addOperand(Inst.getOperand(1));
8782       TmpInst.addOperand(Inst.getOperand(2));
8783       TmpInst.addOperand(Inst.getOperand(4));
8784       TmpInst.addOperand(Inst.getOperand(5));
8785       TmpInst.addOperand(Inst.getOperand(6));
8786       Inst = TmpInst;
8787       return true;
8788     }
8789     return false;
8790   }
8791   case ARM::ITasm:
8792   case ARM::t2IT: {
8793     MCOperand &MO = Inst.getOperand(1);
8794     unsigned Mask = MO.getImm();
8795     ARMCC::CondCodes Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8796 
8797     // Set up the IT block state according to the IT instruction we just
8798     // matched.
8799     assert(!inITBlock() && "nested IT blocks?!");
8800     startExplicitITBlock(Cond, Mask);
8801     MO.setImm(getITMaskEncoding());
8802     break;
8803   }
8804   case ARM::t2LSLrr:
8805   case ARM::t2LSRrr:
8806   case ARM::t2ASRrr:
8807   case ARM::t2SBCrr:
8808   case ARM::t2RORrr:
8809   case ARM::t2BICrr:
8810   {
8811     // Assemblers should use the narrow encodings of these instructions when permissible.
8812     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8813          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8814         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8815         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8816          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8817         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8818          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8819              ".w"))) {
8820       unsigned NewOpc;
8821       switch (Inst.getOpcode()) {
8822         default: llvm_unreachable("unexpected opcode");
8823         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8824         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8825         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8826         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8827         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8828         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8829       }
8830       MCInst TmpInst;
8831       TmpInst.setOpcode(NewOpc);
8832       TmpInst.addOperand(Inst.getOperand(0));
8833       TmpInst.addOperand(Inst.getOperand(5));
8834       TmpInst.addOperand(Inst.getOperand(1));
8835       TmpInst.addOperand(Inst.getOperand(2));
8836       TmpInst.addOperand(Inst.getOperand(3));
8837       TmpInst.addOperand(Inst.getOperand(4));
8838       Inst = TmpInst;
8839       return true;
8840     }
8841     return false;
8842   }
8843   case ARM::t2ANDrr:
8844   case ARM::t2EORrr:
8845   case ARM::t2ADCrr:
8846   case ARM::t2ORRrr:
8847   {
8848     // Assemblers should use the narrow encodings of these instructions when permissible.
8849     // These instructions are special in that they are commutable, so shorter encodings
8850     // are available more often.
8851     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8852          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8853         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8854          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8855         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8856          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8857         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8858          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8859              ".w"))) {
8860       unsigned NewOpc;
8861       switch (Inst.getOpcode()) {
8862         default: llvm_unreachable("unexpected opcode");
8863         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8864         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8865         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8866         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8867       }
8868       MCInst TmpInst;
8869       TmpInst.setOpcode(NewOpc);
8870       TmpInst.addOperand(Inst.getOperand(0));
8871       TmpInst.addOperand(Inst.getOperand(5));
8872       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8873         TmpInst.addOperand(Inst.getOperand(1));
8874         TmpInst.addOperand(Inst.getOperand(2));
8875       } else {
8876         TmpInst.addOperand(Inst.getOperand(2));
8877         TmpInst.addOperand(Inst.getOperand(1));
8878       }
8879       TmpInst.addOperand(Inst.getOperand(3));
8880       TmpInst.addOperand(Inst.getOperand(4));
8881       Inst = TmpInst;
8882       return true;
8883     }
8884     return false;
8885   }
8886   }
8887   return false;
8888 }
8889 
8890 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8891   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8892   // suffix depending on whether they're in an IT block or not.
8893   unsigned Opc = Inst.getOpcode();
8894   const MCInstrDesc &MCID = MII.get(Opc);
8895   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8896     assert(MCID.hasOptionalDef() &&
8897            "optionally flag setting instruction missing optional def operand");
8898     assert(MCID.NumOperands == Inst.getNumOperands() &&
8899            "operand count mismatch!");
8900     // Find the optional-def operand (cc_out).
8901     unsigned OpNo;
8902     for (OpNo = 0;
8903          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8904          ++OpNo)
8905       ;
8906     // If we're parsing Thumb1, reject it completely.
8907     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8908       return Match_MnemonicFail;
8909     // If we're parsing Thumb2, which form is legal depends on whether we're
8910     // in an IT block.
8911     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8912         !inITBlock())
8913       return Match_RequiresITBlock;
8914     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8915         inITBlock())
8916       return Match_RequiresNotITBlock;
8917   } else if (isThumbOne()) {
8918     // Some high-register supporting Thumb1 encodings only allow both registers
8919     // to be from r0-r7 when in Thumb2.
8920     if (Opc == ARM::tADDhirr && !hasV6MOps() &&
8921         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8922         isARMLowRegister(Inst.getOperand(2).getReg()))
8923       return Match_RequiresThumb2;
8924     // Others only require ARMv6 or later.
8925     else if (Opc == ARM::tMOVr && !hasV6Ops() &&
8926              isARMLowRegister(Inst.getOperand(0).getReg()) &&
8927              isARMLowRegister(Inst.getOperand(1).getReg()))
8928       return Match_RequiresV6;
8929   }
8930 
8931   for (unsigned I = 0; I < MCID.NumOperands; ++I)
8932     if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
8933       // rGPRRegClass excludes PC, and also excluded SP before ARMv8
8934       if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
8935         return Match_RequiresV8;
8936       else if (Inst.getOperand(I).getReg() == ARM::PC)
8937         return Match_InvalidOperand;
8938     }
8939 
8940   return Match_Success;
8941 }
8942 
8943 namespace llvm {
8944 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8945   return true; // In an assembly source, no need to second-guess
8946 }
8947 }
8948 
8949 // Returns true if Inst is unpredictable if it is in and IT block, but is not
8950 // the last instruction in the block.
8951 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
8952   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
8953 
8954   // All branch & call instructions terminate IT blocks.
8955   if (MCID.isTerminator() || MCID.isCall() || MCID.isReturn() ||
8956       MCID.isBranch() || MCID.isIndirectBranch())
8957     return true;
8958 
8959   // Any arithmetic instruction which writes to the PC also terminates the IT
8960   // block.
8961   for (unsigned OpIdx = 0; OpIdx < MCID.getNumDefs(); ++OpIdx) {
8962     MCOperand &Op = Inst.getOperand(OpIdx);
8963     if (Op.isReg() && Op.getReg() == ARM::PC)
8964       return true;
8965   }
8966 
8967   if (MCID.hasImplicitDefOfPhysReg(ARM::PC, MRI))
8968     return true;
8969 
8970   // Instructions with variable operand lists, which write to the variable
8971   // operands. We only care about Thumb instructions here, as ARM instructions
8972   // obviously can't be in an IT block.
8973   switch (Inst.getOpcode()) {
8974   case ARM::t2LDMIA:
8975   case ARM::t2LDMIA_UPD:
8976   case ARM::t2LDMDB:
8977   case ARM::t2LDMDB_UPD:
8978     if (listContainsReg(Inst, 3, ARM::PC))
8979       return true;
8980     break;
8981   case ARM::tPOP:
8982     if (listContainsReg(Inst, 2, ARM::PC))
8983       return true;
8984     break;
8985   }
8986 
8987   return false;
8988 }
8989 
8990 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
8991                                           uint64_t &ErrorInfo,
8992                                           bool MatchingInlineAsm,
8993                                           bool &EmitInITBlock,
8994                                           MCStreamer &Out) {
8995   // If we can't use an implicit IT block here, just match as normal.
8996   if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
8997     return MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
8998 
8999   // Try to match the instruction in an extension of the current IT block (if
9000   // there is one).
9001   if (inImplicitITBlock()) {
9002     extendImplicitITBlock(ITState.Cond);
9003     if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) ==
9004             Match_Success) {
9005       // The match succeded, but we still have to check that the instruction is
9006       // valid in this implicit IT block.
9007       const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9008       if (MCID.isPredicable()) {
9009         ARMCC::CondCodes InstCond =
9010             (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9011                 .getImm();
9012         ARMCC::CondCodes ITCond = currentITCond();
9013         if (InstCond == ITCond) {
9014           EmitInITBlock = true;
9015           return Match_Success;
9016         } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
9017           invertCurrentITCondition();
9018           EmitInITBlock = true;
9019           return Match_Success;
9020         }
9021       }
9022     }
9023     rewindImplicitITPosition();
9024   }
9025 
9026   // Finish the current IT block, and try to match outside any IT block.
9027   flushPendingInstructions(Out);
9028   unsigned PlainMatchResult =
9029       MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
9030   if (PlainMatchResult == Match_Success) {
9031     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9032     if (MCID.isPredicable()) {
9033       ARMCC::CondCodes InstCond =
9034           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9035               .getImm();
9036       // Some forms of the branch instruction have their own condition code
9037       // fields, so can be conditionally executed without an IT block.
9038       if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
9039         EmitInITBlock = false;
9040         return Match_Success;
9041       }
9042       if (InstCond == ARMCC::AL) {
9043         EmitInITBlock = false;
9044         return Match_Success;
9045       }
9046     } else {
9047       EmitInITBlock = false;
9048       return Match_Success;
9049     }
9050   }
9051 
9052   // Try to match in a new IT block. The matcher doesn't check the actual
9053   // condition, so we create an IT block with a dummy condition, and fix it up
9054   // once we know the actual condition.
9055   startImplicitITBlock();
9056   if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) ==
9057       Match_Success) {
9058     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9059     if (MCID.isPredicable()) {
9060       ITState.Cond =
9061           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9062               .getImm();
9063       EmitInITBlock = true;
9064       return Match_Success;
9065     }
9066   }
9067   discardImplicitITBlock();
9068 
9069   // If none of these succeed, return the error we got when trying to match
9070   // outside any IT blocks.
9071   EmitInITBlock = false;
9072   return PlainMatchResult;
9073 }
9074 
9075 static const char *getSubtargetFeatureName(uint64_t Val);
9076 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
9077                                            OperandVector &Operands,
9078                                            MCStreamer &Out, uint64_t &ErrorInfo,
9079                                            bool MatchingInlineAsm) {
9080   MCInst Inst;
9081   unsigned MatchResult;
9082   bool PendConditionalInstruction = false;
9083 
9084   MatchResult = MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm,
9085                                  PendConditionalInstruction, Out);
9086 
9087   switch (MatchResult) {
9088   case Match_Success:
9089     // Context sensitive operand constraints aren't handled by the matcher,
9090     // so check them here.
9091     if (validateInstruction(Inst, Operands)) {
9092       // Still progress the IT block, otherwise one wrong condition causes
9093       // nasty cascading errors.
9094       forwardITPosition();
9095       return true;
9096     }
9097 
9098     { // processInstruction() updates inITBlock state, we need to save it away
9099       bool wasInITBlock = inITBlock();
9100 
9101       // Some instructions need post-processing to, for example, tweak which
9102       // encoding is selected. Loop on it while changes happen so the
9103       // individual transformations can chain off each other. E.g.,
9104       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
9105       while (processInstruction(Inst, Operands, Out))
9106         ;
9107 
9108       // Only after the instruction is fully processed, we can validate it
9109       if (wasInITBlock && hasV8Ops() && isThumb() &&
9110           !isV8EligibleForIT(&Inst)) {
9111         Warning(IDLoc, "deprecated instruction in IT block");
9112       }
9113     }
9114 
9115     // Only move forward at the very end so that everything in validate
9116     // and process gets a consistent answer about whether we're in an IT
9117     // block.
9118     forwardITPosition();
9119 
9120     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
9121     // doesn't actually encode.
9122     if (Inst.getOpcode() == ARM::ITasm)
9123       return false;
9124 
9125     Inst.setLoc(IDLoc);
9126     if (PendConditionalInstruction) {
9127       PendingConditionalInsts.push_back(Inst);
9128       if (isITBlockFull() || isITBlockTerminator(Inst))
9129         flushPendingInstructions(Out);
9130     } else {
9131       Out.EmitInstruction(Inst, getSTI());
9132     }
9133     return false;
9134   case Match_MissingFeature: {
9135     assert(ErrorInfo && "Unknown missing feature!");
9136     // Special case the error message for the very common case where only
9137     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
9138     std::string Msg = "instruction requires:";
9139     uint64_t Mask = 1;
9140     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
9141       if (ErrorInfo & Mask) {
9142         Msg += " ";
9143         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
9144       }
9145       Mask <<= 1;
9146     }
9147     return Error(IDLoc, Msg);
9148   }
9149   case Match_InvalidOperand: {
9150     SMLoc ErrorLoc = IDLoc;
9151     if (ErrorInfo != ~0ULL) {
9152       if (ErrorInfo >= Operands.size())
9153         return Error(IDLoc, "too few operands for instruction");
9154 
9155       ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
9156       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9157     }
9158 
9159     return Error(ErrorLoc, "invalid operand for instruction");
9160   }
9161   case Match_MnemonicFail:
9162     return Error(IDLoc, "invalid instruction",
9163                  ((ARMOperand &)*Operands[0]).getLocRange());
9164   case Match_RequiresNotITBlock:
9165     return Error(IDLoc, "flag setting instruction only valid outside IT block");
9166   case Match_RequiresITBlock:
9167     return Error(IDLoc, "instruction only valid inside IT block");
9168   case Match_RequiresV6:
9169     return Error(IDLoc, "instruction variant requires ARMv6 or later");
9170   case Match_RequiresThumb2:
9171     return Error(IDLoc, "instruction variant requires Thumb2");
9172   case Match_RequiresV8:
9173     return Error(IDLoc, "instruction variant requires ARMv8 or later");
9174   case Match_ImmRange0_15: {
9175     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
9176     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9177     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
9178   }
9179   case Match_ImmRange0_239: {
9180     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
9181     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9182     return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
9183   }
9184   case Match_AlignedMemoryRequiresNone:
9185   case Match_DupAlignedMemoryRequiresNone:
9186   case Match_AlignedMemoryRequires16:
9187   case Match_DupAlignedMemoryRequires16:
9188   case Match_AlignedMemoryRequires32:
9189   case Match_DupAlignedMemoryRequires32:
9190   case Match_AlignedMemoryRequires64:
9191   case Match_DupAlignedMemoryRequires64:
9192   case Match_AlignedMemoryRequires64or128:
9193   case Match_DupAlignedMemoryRequires64or128:
9194   case Match_AlignedMemoryRequires64or128or256:
9195   {
9196     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
9197     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9198     switch (MatchResult) {
9199       default:
9200         llvm_unreachable("Missing Match_Aligned type");
9201       case Match_AlignedMemoryRequiresNone:
9202       case Match_DupAlignedMemoryRequiresNone:
9203         return Error(ErrorLoc, "alignment must be omitted");
9204       case Match_AlignedMemoryRequires16:
9205       case Match_DupAlignedMemoryRequires16:
9206         return Error(ErrorLoc, "alignment must be 16 or omitted");
9207       case Match_AlignedMemoryRequires32:
9208       case Match_DupAlignedMemoryRequires32:
9209         return Error(ErrorLoc, "alignment must be 32 or omitted");
9210       case Match_AlignedMemoryRequires64:
9211       case Match_DupAlignedMemoryRequires64:
9212         return Error(ErrorLoc, "alignment must be 64 or omitted");
9213       case Match_AlignedMemoryRequires64or128:
9214       case Match_DupAlignedMemoryRequires64or128:
9215         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
9216       case Match_AlignedMemoryRequires64or128or256:
9217         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
9218     }
9219   }
9220   }
9221 
9222   llvm_unreachable("Implement any new match types added!");
9223 }
9224 
9225 /// parseDirective parses the arm specific directives
9226 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
9227   const MCObjectFileInfo::Environment Format =
9228     getContext().getObjectFileInfo()->getObjectFileType();
9229   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
9230   bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
9231 
9232   StringRef IDVal = DirectiveID.getIdentifier();
9233   if (IDVal == ".word")
9234     parseLiteralValues(4, DirectiveID.getLoc());
9235   else if (IDVal == ".short" || IDVal == ".hword")
9236     parseLiteralValues(2, DirectiveID.getLoc());
9237   else if (IDVal == ".thumb")
9238     parseDirectiveThumb(DirectiveID.getLoc());
9239   else if (IDVal == ".arm")
9240     parseDirectiveARM(DirectiveID.getLoc());
9241   else if (IDVal == ".thumb_func")
9242     parseDirectiveThumbFunc(DirectiveID.getLoc());
9243   else if (IDVal == ".code")
9244     parseDirectiveCode(DirectiveID.getLoc());
9245   else if (IDVal == ".syntax")
9246     parseDirectiveSyntax(DirectiveID.getLoc());
9247   else if (IDVal == ".unreq")
9248     parseDirectiveUnreq(DirectiveID.getLoc());
9249   else if (IDVal == ".fnend")
9250     parseDirectiveFnEnd(DirectiveID.getLoc());
9251   else if (IDVal == ".cantunwind")
9252     parseDirectiveCantUnwind(DirectiveID.getLoc());
9253   else if (IDVal == ".personality")
9254     parseDirectivePersonality(DirectiveID.getLoc());
9255   else if (IDVal == ".handlerdata")
9256     parseDirectiveHandlerData(DirectiveID.getLoc());
9257   else if (IDVal == ".setfp")
9258     parseDirectiveSetFP(DirectiveID.getLoc());
9259   else if (IDVal == ".pad")
9260     parseDirectivePad(DirectiveID.getLoc());
9261   else if (IDVal == ".save")
9262     parseDirectiveRegSave(DirectiveID.getLoc(), false);
9263   else if (IDVal == ".vsave")
9264     parseDirectiveRegSave(DirectiveID.getLoc(), true);
9265   else if (IDVal == ".ltorg" || IDVal == ".pool")
9266     parseDirectiveLtorg(DirectiveID.getLoc());
9267   else if (IDVal == ".even")
9268     parseDirectiveEven(DirectiveID.getLoc());
9269   else if (IDVal == ".personalityindex")
9270     parseDirectivePersonalityIndex(DirectiveID.getLoc());
9271   else if (IDVal == ".unwind_raw")
9272     parseDirectiveUnwindRaw(DirectiveID.getLoc());
9273   else if (IDVal == ".movsp")
9274     parseDirectiveMovSP(DirectiveID.getLoc());
9275   else if (IDVal == ".arch_extension")
9276     parseDirectiveArchExtension(DirectiveID.getLoc());
9277   else if (IDVal == ".align")
9278     return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
9279   else if (IDVal == ".thumb_set")
9280     parseDirectiveThumbSet(DirectiveID.getLoc());
9281   else if (!IsMachO && !IsCOFF) {
9282     if (IDVal == ".arch")
9283       parseDirectiveArch(DirectiveID.getLoc());
9284     else if (IDVal == ".cpu")
9285       parseDirectiveCPU(DirectiveID.getLoc());
9286     else if (IDVal == ".eabi_attribute")
9287       parseDirectiveEabiAttr(DirectiveID.getLoc());
9288     else if (IDVal == ".fpu")
9289       parseDirectiveFPU(DirectiveID.getLoc());
9290     else if (IDVal == ".fnstart")
9291       parseDirectiveFnStart(DirectiveID.getLoc());
9292     else if (IDVal == ".inst")
9293       parseDirectiveInst(DirectiveID.getLoc());
9294     else if (IDVal == ".inst.n")
9295       parseDirectiveInst(DirectiveID.getLoc(), 'n');
9296     else if (IDVal == ".inst.w")
9297       parseDirectiveInst(DirectiveID.getLoc(), 'w');
9298     else if (IDVal == ".object_arch")
9299       parseDirectiveObjectArch(DirectiveID.getLoc());
9300     else if (IDVal == ".tlsdescseq")
9301       parseDirectiveTLSDescSeq(DirectiveID.getLoc());
9302     else
9303       return true;
9304   } else
9305     return true;
9306   return false;
9307 }
9308 
9309 /// parseLiteralValues
9310 ///  ::= .hword expression [, expression]*
9311 ///  ::= .short expression [, expression]*
9312 ///  ::= .word expression [, expression]*
9313 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
9314   auto parseOne = [&]() -> bool {
9315     const MCExpr *Value;
9316     if (getParser().parseExpression(Value))
9317       return true;
9318     getParser().getStreamer().EmitValue(Value, Size, L);
9319     return false;
9320   };
9321   return (parseMany(parseOne));
9322 }
9323 
9324 /// parseDirectiveThumb
9325 ///  ::= .thumb
9326 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
9327   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
9328       check(!hasThumb(), L, "target does not support Thumb mode"))
9329     return true;
9330 
9331   if (!isThumb())
9332     SwitchMode();
9333 
9334   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9335   return false;
9336 }
9337 
9338 /// parseDirectiveARM
9339 ///  ::= .arm
9340 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
9341   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
9342       check(!hasARM(), L, "target does not support ARM mode"))
9343     return true;
9344 
9345   if (isThumb())
9346     SwitchMode();
9347   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9348   return false;
9349 }
9350 
9351 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
9352   // We need to flush the current implicit IT block on a label, because it is
9353   // not legal to branch into an IT block.
9354   flushPendingInstructions(getStreamer());
9355   if (NextSymbolIsThumb) {
9356     getParser().getStreamer().EmitThumbFunc(Symbol);
9357     NextSymbolIsThumb = false;
9358   }
9359 }
9360 
9361 /// parseDirectiveThumbFunc
9362 ///  ::= .thumbfunc symbol_name
9363 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
9364   MCAsmParser &Parser = getParser();
9365   const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
9366   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
9367 
9368   // Darwin asm has (optionally) function name after .thumb_func direction
9369   // ELF doesn't
9370 
9371   if (IsMachO) {
9372     if (Parser.getTok().is(AsmToken::Identifier) ||
9373         Parser.getTok().is(AsmToken::String)) {
9374       MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
9375           Parser.getTok().getIdentifier());
9376       getParser().getStreamer().EmitThumbFunc(Func);
9377       Parser.Lex();
9378       if (parseToken(AsmToken::EndOfStatement,
9379                      "unexpected token in '.thumb_func' directive"))
9380         return true;
9381       return false;
9382     }
9383   }
9384 
9385   if (parseToken(AsmToken::EndOfStatement,
9386                  "unexpected token in '.thumb_func' directive"))
9387     return true;
9388 
9389   NextSymbolIsThumb = true;
9390   return false;
9391 }
9392 
9393 /// parseDirectiveSyntax
9394 ///  ::= .syntax unified | divided
9395 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
9396   MCAsmParser &Parser = getParser();
9397   const AsmToken &Tok = Parser.getTok();
9398   if (Tok.isNot(AsmToken::Identifier)) {
9399     Error(L, "unexpected token in .syntax directive");
9400     return false;
9401   }
9402 
9403   StringRef Mode = Tok.getString();
9404   Parser.Lex();
9405   if (check(Mode == "divided" || Mode == "DIVIDED", L,
9406             "'.syntax divided' arm assembly not supported") ||
9407       check(Mode != "unified" && Mode != "UNIFIED", L,
9408             "unrecognized syntax mode in .syntax directive") ||
9409       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9410     return true;
9411 
9412   // TODO tell the MC streamer the mode
9413   // getParser().getStreamer().Emit???();
9414   return false;
9415 }
9416 
9417 /// parseDirectiveCode
9418 ///  ::= .code 16 | 32
9419 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
9420   MCAsmParser &Parser = getParser();
9421   const AsmToken &Tok = Parser.getTok();
9422   if (Tok.isNot(AsmToken::Integer))
9423     return Error(L, "unexpected token in .code directive");
9424   int64_t Val = Parser.getTok().getIntVal();
9425   if (Val != 16 && Val != 32) {
9426     Error(L, "invalid operand to .code directive");
9427     return false;
9428   }
9429   Parser.Lex();
9430 
9431   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9432     return true;
9433 
9434   if (Val == 16) {
9435     if (!hasThumb())
9436       return Error(L, "target does not support Thumb mode");
9437 
9438     if (!isThumb())
9439       SwitchMode();
9440     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9441   } else {
9442     if (!hasARM())
9443       return Error(L, "target does not support ARM mode");
9444 
9445     if (isThumb())
9446       SwitchMode();
9447     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9448   }
9449 
9450   return false;
9451 }
9452 
9453 /// parseDirectiveReq
9454 ///  ::= name .req registername
9455 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
9456   MCAsmParser &Parser = getParser();
9457   Parser.Lex(); // Eat the '.req' token.
9458   unsigned Reg;
9459   SMLoc SRegLoc, ERegLoc;
9460   if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
9461             "register name expected") ||
9462       parseToken(AsmToken::EndOfStatement,
9463                  "unexpected input in .req directive."))
9464     return true;
9465 
9466   if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
9467     return Error(SRegLoc,
9468                  "redefinition of '" + Name + "' does not match original.");
9469 
9470   return false;
9471 }
9472 
9473 /// parseDirectiveUneq
9474 ///  ::= .unreq registername
9475 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9476   MCAsmParser &Parser = getParser();
9477   if (Parser.getTok().isNot(AsmToken::Identifier))
9478     return Error(L, "unexpected input in .unreq directive.");
9479   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9480   Parser.Lex(); // Eat the identifier.
9481   if (parseToken(AsmToken::EndOfStatement,
9482                  "unexpected input in '.unreq' directive"))
9483     return true;
9484   return false;
9485 }
9486 
9487 // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
9488 // before, if supported by the new target, or emit mapping symbols for the mode
9489 // switch.
9490 void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
9491   if (WasThumb != isThumb()) {
9492     if (WasThumb && hasThumb()) {
9493       // Stay in Thumb mode
9494       SwitchMode();
9495     } else if (!WasThumb && hasARM()) {
9496       // Stay in ARM mode
9497       SwitchMode();
9498     } else {
9499       // Mode switch forced, because the new arch doesn't support the old mode.
9500       getParser().getStreamer().EmitAssemblerFlag(isThumb() ? MCAF_Code16
9501                                                             : MCAF_Code32);
9502       // Warn about the implcit mode switch. GAS does not switch modes here,
9503       // but instead stays in the old mode, reporting an error on any following
9504       // instructions as the mode does not exist on the target.
9505       Warning(Loc, Twine("new target does not support ") +
9506                        (WasThumb ? "thumb" : "arm") + " mode, switching to " +
9507                        (!WasThumb ? "thumb" : "arm") + " mode");
9508     }
9509   }
9510 }
9511 
9512 /// parseDirectiveArch
9513 ///  ::= .arch token
9514 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9515   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9516   unsigned ID = ARM::parseArch(Arch);
9517 
9518   if (ID == ARM::AK_INVALID)
9519     return Error(L, "Unknown arch name");
9520 
9521   bool WasThumb = isThumb();
9522   Triple T;
9523   MCSubtargetInfo &STI = copySTI();
9524   STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
9525   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9526   FixModeAfterArchChange(WasThumb, L);
9527 
9528   getTargetStreamer().emitArch(ID);
9529   return false;
9530 }
9531 
9532 /// parseDirectiveEabiAttr
9533 ///  ::= .eabi_attribute int, int [, "str"]
9534 ///  ::= .eabi_attribute Tag_name, int [, "str"]
9535 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9536   MCAsmParser &Parser = getParser();
9537   int64_t Tag;
9538   SMLoc TagLoc;
9539   TagLoc = Parser.getTok().getLoc();
9540   if (Parser.getTok().is(AsmToken::Identifier)) {
9541     StringRef Name = Parser.getTok().getIdentifier();
9542     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9543     if (Tag == -1) {
9544       Error(TagLoc, "attribute name not recognised: " + Name);
9545       return false;
9546     }
9547     Parser.Lex();
9548   } else {
9549     const MCExpr *AttrExpr;
9550 
9551     TagLoc = Parser.getTok().getLoc();
9552     if (Parser.parseExpression(AttrExpr))
9553       return true;
9554 
9555     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9556     if (check(!CE, TagLoc, "expected numeric constant"))
9557       return true;
9558 
9559     Tag = CE->getValue();
9560   }
9561 
9562   if (Parser.parseToken(AsmToken::Comma, "comma expected"))
9563     return true;
9564 
9565   StringRef StringValue = "";
9566   bool IsStringValue = false;
9567 
9568   int64_t IntegerValue = 0;
9569   bool IsIntegerValue = false;
9570 
9571   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9572     IsStringValue = true;
9573   else if (Tag == ARMBuildAttrs::compatibility) {
9574     IsStringValue = true;
9575     IsIntegerValue = true;
9576   } else if (Tag < 32 || Tag % 2 == 0)
9577     IsIntegerValue = true;
9578   else if (Tag % 2 == 1)
9579     IsStringValue = true;
9580   else
9581     llvm_unreachable("invalid tag type");
9582 
9583   if (IsIntegerValue) {
9584     const MCExpr *ValueExpr;
9585     SMLoc ValueExprLoc = Parser.getTok().getLoc();
9586     if (Parser.parseExpression(ValueExpr))
9587       return true;
9588 
9589     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9590     if (!CE)
9591       return Error(ValueExprLoc, "expected numeric constant");
9592     IntegerValue = CE->getValue();
9593   }
9594 
9595   if (Tag == ARMBuildAttrs::compatibility) {
9596     if (Parser.parseToken(AsmToken::Comma, "comma expected"))
9597       return true;
9598   }
9599 
9600   if (IsStringValue) {
9601     if (Parser.getTok().isNot(AsmToken::String))
9602       return Error(Parser.getTok().getLoc(), "bad string constant");
9603 
9604     StringValue = Parser.getTok().getStringContents();
9605     Parser.Lex();
9606   }
9607 
9608   if (Parser.parseToken(AsmToken::EndOfStatement,
9609                         "unexpected token in '.eabi_attribute' directive"))
9610     return true;
9611 
9612   if (IsIntegerValue && IsStringValue) {
9613     assert(Tag == ARMBuildAttrs::compatibility);
9614     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9615   } else if (IsIntegerValue)
9616     getTargetStreamer().emitAttribute(Tag, IntegerValue);
9617   else if (IsStringValue)
9618     getTargetStreamer().emitTextAttribute(Tag, StringValue);
9619   return false;
9620 }
9621 
9622 /// parseDirectiveCPU
9623 ///  ::= .cpu str
9624 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9625   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9626   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9627 
9628   // FIXME: This is using table-gen data, but should be moved to
9629   // ARMTargetParser once that is table-gen'd.
9630   if (!getSTI().isCPUStringValid(CPU))
9631     return Error(L, "Unknown CPU name");
9632 
9633   bool WasThumb = isThumb();
9634   MCSubtargetInfo &STI = copySTI();
9635   STI.setDefaultFeatures(CPU, "");
9636   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9637   FixModeAfterArchChange(WasThumb, L);
9638 
9639   return false;
9640 }
9641 /// parseDirectiveFPU
9642 ///  ::= .fpu str
9643 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9644   SMLoc FPUNameLoc = getTok().getLoc();
9645   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9646 
9647   unsigned ID = ARM::parseFPU(FPU);
9648   std::vector<StringRef> Features;
9649   if (!ARM::getFPUFeatures(ID, Features))
9650     return Error(FPUNameLoc, "Unknown FPU name");
9651 
9652   MCSubtargetInfo &STI = copySTI();
9653   for (auto Feature : Features)
9654     STI.ApplyFeatureFlag(Feature);
9655   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9656 
9657   getTargetStreamer().emitFPU(ID);
9658   return false;
9659 }
9660 
9661 /// parseDirectiveFnStart
9662 ///  ::= .fnstart
9663 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9664   if (parseToken(AsmToken::EndOfStatement,
9665                  "unexpected token in '.fnstart' directive"))
9666     return true;
9667 
9668   if (UC.hasFnStart()) {
9669     Error(L, ".fnstart starts before the end of previous one");
9670     UC.emitFnStartLocNotes();
9671     return true;
9672   }
9673 
9674   // Reset the unwind directives parser state
9675   UC.reset();
9676 
9677   getTargetStreamer().emitFnStart();
9678 
9679   UC.recordFnStart(L);
9680   return false;
9681 }
9682 
9683 /// parseDirectiveFnEnd
9684 ///  ::= .fnend
9685 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9686   if (parseToken(AsmToken::EndOfStatement,
9687                  "unexpected token in '.fnend' directive"))
9688     return true;
9689   // Check the ordering of unwind directives
9690   if (!UC.hasFnStart())
9691     return Error(L, ".fnstart must precede .fnend directive");
9692 
9693   // Reset the unwind directives parser state
9694   getTargetStreamer().emitFnEnd();
9695 
9696   UC.reset();
9697   return false;
9698 }
9699 
9700 /// parseDirectiveCantUnwind
9701 ///  ::= .cantunwind
9702 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9703   if (parseToken(AsmToken::EndOfStatement,
9704                  "unexpected token in '.cantunwind' directive"))
9705     return true;
9706 
9707   UC.recordCantUnwind(L);
9708   // Check the ordering of unwind directives
9709   if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
9710     return true;
9711 
9712   if (UC.hasHandlerData()) {
9713     Error(L, ".cantunwind can't be used with .handlerdata directive");
9714     UC.emitHandlerDataLocNotes();
9715     return true;
9716   }
9717   if (UC.hasPersonality()) {
9718     Error(L, ".cantunwind can't be used with .personality directive");
9719     UC.emitPersonalityLocNotes();
9720     return true;
9721   }
9722 
9723   getTargetStreamer().emitCantUnwind();
9724   return false;
9725 }
9726 
9727 /// parseDirectivePersonality
9728 ///  ::= .personality name
9729 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9730   MCAsmParser &Parser = getParser();
9731   bool HasExistingPersonality = UC.hasPersonality();
9732 
9733   // Parse the name of the personality routine
9734   if (Parser.getTok().isNot(AsmToken::Identifier))
9735     return Error(L, "unexpected input in .personality directive.");
9736   StringRef Name(Parser.getTok().getIdentifier());
9737   Parser.Lex();
9738 
9739   if (parseToken(AsmToken::EndOfStatement,
9740                  "unexpected token in '.personality' directive"))
9741     return true;
9742 
9743   UC.recordPersonality(L);
9744 
9745   // Check the ordering of unwind directives
9746   if (!UC.hasFnStart())
9747     return Error(L, ".fnstart must precede .personality directive");
9748   if (UC.cantUnwind()) {
9749     Error(L, ".personality can't be used with .cantunwind directive");
9750     UC.emitCantUnwindLocNotes();
9751     return true;
9752   }
9753   if (UC.hasHandlerData()) {
9754     Error(L, ".personality must precede .handlerdata directive");
9755     UC.emitHandlerDataLocNotes();
9756     return true;
9757   }
9758   if (HasExistingPersonality) {
9759     Error(L, "multiple personality directives");
9760     UC.emitPersonalityLocNotes();
9761     return true;
9762   }
9763 
9764   MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
9765   getTargetStreamer().emitPersonality(PR);
9766   return false;
9767 }
9768 
9769 /// parseDirectiveHandlerData
9770 ///  ::= .handlerdata
9771 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9772   if (parseToken(AsmToken::EndOfStatement,
9773                  "unexpected token in '.handlerdata' directive"))
9774     return true;
9775 
9776   UC.recordHandlerData(L);
9777   // Check the ordering of unwind directives
9778   if (!UC.hasFnStart())
9779     return Error(L, ".fnstart must precede .personality directive");
9780   if (UC.cantUnwind()) {
9781     Error(L, ".handlerdata can't be used with .cantunwind directive");
9782     UC.emitCantUnwindLocNotes();
9783     return true;
9784   }
9785 
9786   getTargetStreamer().emitHandlerData();
9787   return false;
9788 }
9789 
9790 /// parseDirectiveSetFP
9791 ///  ::= .setfp fpreg, spreg [, offset]
9792 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9793   MCAsmParser &Parser = getParser();
9794   // Check the ordering of unwind directives
9795   if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
9796       check(UC.hasHandlerData(), L,
9797             ".setfp must precede .handlerdata directive"))
9798     return true;
9799 
9800   // Parse fpreg
9801   SMLoc FPRegLoc = Parser.getTok().getLoc();
9802   int FPReg = tryParseRegister();
9803 
9804   if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
9805       Parser.parseToken(AsmToken::Comma, "comma expected"))
9806     return true;
9807 
9808   // Parse spreg
9809   SMLoc SPRegLoc = Parser.getTok().getLoc();
9810   int SPReg = tryParseRegister();
9811   if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
9812       check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
9813             "register should be either $sp or the latest fp register"))
9814     return true;
9815 
9816   // Update the frame pointer register
9817   UC.saveFPReg(FPReg);
9818 
9819   // Parse offset
9820   int64_t Offset = 0;
9821   if (Parser.parseOptionalToken(AsmToken::Comma)) {
9822     if (Parser.getTok().isNot(AsmToken::Hash) &&
9823         Parser.getTok().isNot(AsmToken::Dollar))
9824       return Error(Parser.getTok().getLoc(), "'#' expected");
9825     Parser.Lex(); // skip hash token.
9826 
9827     const MCExpr *OffsetExpr;
9828     SMLoc ExLoc = Parser.getTok().getLoc();
9829     SMLoc EndLoc;
9830     if (getParser().parseExpression(OffsetExpr, EndLoc))
9831       return Error(ExLoc, "malformed setfp offset");
9832     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9833     if (check(!CE, ExLoc, "setfp offset must be an immediate"))
9834       return true;
9835     Offset = CE->getValue();
9836   }
9837 
9838   if (Parser.parseToken(AsmToken::EndOfStatement))
9839     return true;
9840 
9841   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9842                                 static_cast<unsigned>(SPReg), Offset);
9843   return false;
9844 }
9845 
9846 /// parseDirective
9847 ///  ::= .pad offset
9848 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9849   MCAsmParser &Parser = getParser();
9850   // Check the ordering of unwind directives
9851   if (!UC.hasFnStart())
9852     return Error(L, ".fnstart must precede .pad directive");
9853   if (UC.hasHandlerData())
9854     return Error(L, ".pad must precede .handlerdata directive");
9855 
9856   // Parse the offset
9857   if (Parser.getTok().isNot(AsmToken::Hash) &&
9858       Parser.getTok().isNot(AsmToken::Dollar))
9859     return Error(Parser.getTok().getLoc(), "'#' expected");
9860   Parser.Lex(); // skip hash token.
9861 
9862   const MCExpr *OffsetExpr;
9863   SMLoc ExLoc = Parser.getTok().getLoc();
9864   SMLoc EndLoc;
9865   if (getParser().parseExpression(OffsetExpr, EndLoc))
9866     return Error(ExLoc, "malformed pad offset");
9867   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9868   if (!CE)
9869     return Error(ExLoc, "pad offset must be an immediate");
9870 
9871   if (parseToken(AsmToken::EndOfStatement,
9872                  "unexpected token in '.pad' directive"))
9873     return true;
9874 
9875   getTargetStreamer().emitPad(CE->getValue());
9876   return false;
9877 }
9878 
9879 /// parseDirectiveRegSave
9880 ///  ::= .save  { registers }
9881 ///  ::= .vsave { registers }
9882 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9883   // Check the ordering of unwind directives
9884   if (!UC.hasFnStart())
9885     return Error(L, ".fnstart must precede .save or .vsave directives");
9886   if (UC.hasHandlerData())
9887     return Error(L, ".save or .vsave must precede .handlerdata directive");
9888 
9889   // RAII object to make sure parsed operands are deleted.
9890   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9891 
9892   // Parse the register list
9893   if (parseRegisterList(Operands) ||
9894       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9895     return true;
9896   ARMOperand &Op = (ARMOperand &)*Operands[0];
9897   if (!IsVector && !Op.isRegList())
9898     return Error(L, ".save expects GPR registers");
9899   if (IsVector && !Op.isDPRRegList())
9900     return Error(L, ".vsave expects DPR registers");
9901 
9902   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9903   return false;
9904 }
9905 
9906 /// parseDirectiveInst
9907 ///  ::= .inst opcode [, ...]
9908 ///  ::= .inst.n opcode [, ...]
9909 ///  ::= .inst.w opcode [, ...]
9910 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9911   int Width = 4;
9912 
9913   if (isThumb()) {
9914     switch (Suffix) {
9915     case 'n':
9916       Width = 2;
9917       break;
9918     case 'w':
9919       break;
9920     default:
9921       return Error(Loc, "cannot determine Thumb instruction size, "
9922                         "use inst.n/inst.w instead");
9923     }
9924   } else {
9925     if (Suffix)
9926       return Error(Loc, "width suffixes are invalid in ARM mode");
9927   }
9928 
9929   auto parseOne = [&]() -> bool {
9930     const MCExpr *Expr;
9931     if (getParser().parseExpression(Expr))
9932       return true;
9933     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9934     if (!Value) {
9935       return Error(Loc, "expected constant expression");
9936     }
9937 
9938     switch (Width) {
9939     case 2:
9940       if (Value->getValue() > 0xffff)
9941         return Error(Loc, "inst.n operand is too big, use inst.w instead");
9942       break;
9943     case 4:
9944       if (Value->getValue() > 0xffffffff)
9945         return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") +
9946                               " operand is too big");
9947       break;
9948     default:
9949       llvm_unreachable("only supported widths are 2 and 4");
9950     }
9951 
9952     getTargetStreamer().emitInst(Value->getValue(), Suffix);
9953     return false;
9954   };
9955 
9956   if (parseOptionalToken(AsmToken::EndOfStatement))
9957     return Error(Loc, "expected expression following directive");
9958   if (parseMany(parseOne))
9959     return true;
9960   return false;
9961 }
9962 
9963 /// parseDirectiveLtorg
9964 ///  ::= .ltorg | .pool
9965 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9966   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9967     return true;
9968   getTargetStreamer().emitCurrentConstantPool();
9969   return false;
9970 }
9971 
9972 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9973   const MCSection *Section = getStreamer().getCurrentSectionOnly();
9974 
9975   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9976     return true;
9977 
9978   if (!Section) {
9979     getStreamer().InitSections(false);
9980     Section = getStreamer().getCurrentSectionOnly();
9981   }
9982 
9983   assert(Section && "must have section to emit alignment");
9984   if (Section->UseCodeAlign())
9985     getStreamer().EmitCodeAlignment(2);
9986   else
9987     getStreamer().EmitValueToAlignment(2);
9988 
9989   return false;
9990 }
9991 
9992 /// parseDirectivePersonalityIndex
9993 ///   ::= .personalityindex index
9994 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9995   MCAsmParser &Parser = getParser();
9996   bool HasExistingPersonality = UC.hasPersonality();
9997 
9998   const MCExpr *IndexExpression;
9999   SMLoc IndexLoc = Parser.getTok().getLoc();
10000   if (Parser.parseExpression(IndexExpression) ||
10001       parseToken(AsmToken::EndOfStatement,
10002                  "unexpected token in '.personalityindex' directive")) {
10003     return true;
10004   }
10005 
10006   UC.recordPersonalityIndex(L);
10007 
10008   if (!UC.hasFnStart()) {
10009     return Error(L, ".fnstart must precede .personalityindex directive");
10010   }
10011   if (UC.cantUnwind()) {
10012     Error(L, ".personalityindex cannot be used with .cantunwind");
10013     UC.emitCantUnwindLocNotes();
10014     return true;
10015   }
10016   if (UC.hasHandlerData()) {
10017     Error(L, ".personalityindex must precede .handlerdata directive");
10018     UC.emitHandlerDataLocNotes();
10019     return true;
10020   }
10021   if (HasExistingPersonality) {
10022     Error(L, "multiple personality directives");
10023     UC.emitPersonalityLocNotes();
10024     return true;
10025   }
10026 
10027   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
10028   if (!CE)
10029     return Error(IndexLoc, "index must be a constant number");
10030   if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
10031     return Error(IndexLoc,
10032                  "personality routine index should be in range [0-3]");
10033 
10034   getTargetStreamer().emitPersonalityIndex(CE->getValue());
10035   return false;
10036 }
10037 
10038 /// parseDirectiveUnwindRaw
10039 ///   ::= .unwind_raw offset, opcode [, opcode...]
10040 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
10041   MCAsmParser &Parser = getParser();
10042   int64_t StackOffset;
10043   const MCExpr *OffsetExpr;
10044   SMLoc OffsetLoc = getLexer().getLoc();
10045 
10046   if (!UC.hasFnStart())
10047     return Error(L, ".fnstart must precede .unwind_raw directives");
10048   if (getParser().parseExpression(OffsetExpr))
10049     return Error(OffsetLoc, "expected expression");
10050 
10051   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
10052   if (!CE)
10053     return Error(OffsetLoc, "offset must be a constant");
10054 
10055   StackOffset = CE->getValue();
10056 
10057   if (Parser.parseToken(AsmToken::Comma, "expected comma"))
10058     return true;
10059 
10060   SmallVector<uint8_t, 16> Opcodes;
10061 
10062   auto parseOne = [&]() -> bool {
10063     const MCExpr *OE;
10064     SMLoc OpcodeLoc = getLexer().getLoc();
10065     if (check(getLexer().is(AsmToken::EndOfStatement) ||
10066                   Parser.parseExpression(OE),
10067               OpcodeLoc, "expected opcode expression"))
10068       return true;
10069     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
10070     if (!OC)
10071       return Error(OpcodeLoc, "opcode value must be a constant");
10072     const int64_t Opcode = OC->getValue();
10073     if (Opcode & ~0xff)
10074       return Error(OpcodeLoc, "invalid opcode");
10075     Opcodes.push_back(uint8_t(Opcode));
10076     return false;
10077   };
10078 
10079   // Must have at least 1 element
10080   SMLoc OpcodeLoc = getLexer().getLoc();
10081   if (parseOptionalToken(AsmToken::EndOfStatement))
10082     return Error(OpcodeLoc, "expected opcode expression");
10083   if (parseMany(parseOne))
10084     return true;
10085 
10086   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
10087   return false;
10088 }
10089 
10090 /// parseDirectiveTLSDescSeq
10091 ///   ::= .tlsdescseq tls-variable
10092 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
10093   MCAsmParser &Parser = getParser();
10094 
10095   if (getLexer().isNot(AsmToken::Identifier))
10096     return TokError("expected variable after '.tlsdescseq' directive");
10097 
10098   const MCSymbolRefExpr *SRE =
10099     MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
10100                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
10101   Lex();
10102 
10103   if (parseToken(AsmToken::EndOfStatement,
10104                  "unexpected token in '.tlsdescseq' directive"))
10105     return true;
10106 
10107   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
10108   return false;
10109 }
10110 
10111 /// parseDirectiveMovSP
10112 ///  ::= .movsp reg [, #offset]
10113 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
10114   MCAsmParser &Parser = getParser();
10115   if (!UC.hasFnStart())
10116     return Error(L, ".fnstart must precede .movsp directives");
10117   if (UC.getFPReg() != ARM::SP)
10118     return Error(L, "unexpected .movsp directive");
10119 
10120   SMLoc SPRegLoc = Parser.getTok().getLoc();
10121   int SPReg = tryParseRegister();
10122   if (SPReg == -1)
10123     return Error(SPRegLoc, "register expected");
10124   if (SPReg == ARM::SP || SPReg == ARM::PC)
10125     return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
10126 
10127   int64_t Offset = 0;
10128   if (Parser.parseOptionalToken(AsmToken::Comma)) {
10129     if (Parser.parseToken(AsmToken::Hash, "expected #constant"))
10130       return true;
10131 
10132     const MCExpr *OffsetExpr;
10133     SMLoc OffsetLoc = Parser.getTok().getLoc();
10134 
10135     if (Parser.parseExpression(OffsetExpr))
10136       return Error(OffsetLoc, "malformed offset expression");
10137 
10138     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
10139     if (!CE)
10140       return Error(OffsetLoc, "offset must be an immediate constant");
10141 
10142     Offset = CE->getValue();
10143   }
10144 
10145   if (parseToken(AsmToken::EndOfStatement,
10146                  "unexpected token in '.movsp' directive"))
10147     return true;
10148 
10149   getTargetStreamer().emitMovSP(SPReg, Offset);
10150   UC.saveFPReg(SPReg);
10151 
10152   return false;
10153 }
10154 
10155 /// parseDirectiveObjectArch
10156 ///   ::= .object_arch name
10157 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
10158   MCAsmParser &Parser = getParser();
10159   if (getLexer().isNot(AsmToken::Identifier))
10160     return Error(getLexer().getLoc(), "unexpected token");
10161 
10162   StringRef Arch = Parser.getTok().getString();
10163   SMLoc ArchLoc = Parser.getTok().getLoc();
10164   Lex();
10165 
10166   unsigned ID = ARM::parseArch(Arch);
10167 
10168   if (ID == ARM::AK_INVALID)
10169     return Error(ArchLoc, "unknown architecture '" + Arch + "'");
10170   if (parseToken(AsmToken::EndOfStatement))
10171     return true;
10172 
10173   getTargetStreamer().emitObjectArch(ID);
10174   return false;
10175 }
10176 
10177 /// parseDirectiveAlign
10178 ///   ::= .align
10179 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
10180   // NOTE: if this is not the end of the statement, fall back to the target
10181   // agnostic handling for this directive which will correctly handle this.
10182   if (parseOptionalToken(AsmToken::EndOfStatement)) {
10183     // '.align' is target specifically handled to mean 2**2 byte alignment.
10184     const MCSection *Section = getStreamer().getCurrentSectionOnly();
10185     assert(Section && "must have section to emit alignment");
10186     if (Section->UseCodeAlign())
10187       getStreamer().EmitCodeAlignment(4, 0);
10188     else
10189       getStreamer().EmitValueToAlignment(4, 0, 1, 0);
10190     return false;
10191   }
10192   return true;
10193 }
10194 
10195 /// parseDirectiveThumbSet
10196 ///  ::= .thumb_set name, value
10197 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
10198   MCAsmParser &Parser = getParser();
10199 
10200   StringRef Name;
10201   if (check(Parser.parseIdentifier(Name),
10202             "expected identifier after '.thumb_set'") ||
10203       parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'"))
10204     return true;
10205 
10206   MCSymbol *Sym;
10207   const MCExpr *Value;
10208   if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
10209                                                Parser, Sym, Value))
10210     return true;
10211 
10212   getTargetStreamer().emitThumbSet(Sym, Value);
10213   return false;
10214 }
10215 
10216 /// Force static initialization.
10217 extern "C" void LLVMInitializeARMAsmParser() {
10218   RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
10219   RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
10220   RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
10221   RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
10222 }
10223 
10224 #define GET_REGISTER_MATCHER
10225 #define GET_SUBTARGET_FEATURE_NAME
10226 #define GET_MATCHER_IMPLEMENTATION
10227 #include "ARMGenAsmMatcher.inc"
10228 
10229 // FIXME: This structure should be moved inside ARMTargetParser
10230 // when we start to table-generate them, and we can use the ARM
10231 // flags below, that were generated by table-gen.
10232 static const struct {
10233   const unsigned Kind;
10234   const uint64_t ArchCheck;
10235   const FeatureBitset Features;
10236 } Extensions[] = {
10237   { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
10238   { ARM::AEK_CRYPTO,  Feature_HasV8,
10239     {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10240   { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
10241   { (ARM::AEK_HWDIV | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
10242     {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
10243   { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
10244   { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10245   { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
10246   // FIXME: Only available in A-class, isel not predicated
10247   { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
10248   { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
10249   { ARM::AEK_RAS, Feature_HasV8, {ARM::FeatureRAS} },
10250   // FIXME: Unsupported extensions.
10251   { ARM::AEK_OS, Feature_None, {} },
10252   { ARM::AEK_IWMMXT, Feature_None, {} },
10253   { ARM::AEK_IWMMXT2, Feature_None, {} },
10254   { ARM::AEK_MAVERICK, Feature_None, {} },
10255   { ARM::AEK_XSCALE, Feature_None, {} },
10256 };
10257 
10258 /// parseDirectiveArchExtension
10259 ///   ::= .arch_extension [no]feature
10260 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
10261   MCAsmParser &Parser = getParser();
10262 
10263   if (getLexer().isNot(AsmToken::Identifier))
10264     return Error(getLexer().getLoc(), "expected architecture extension name");
10265 
10266   StringRef Name = Parser.getTok().getString();
10267   SMLoc ExtLoc = Parser.getTok().getLoc();
10268   Lex();
10269 
10270   if (parseToken(AsmToken::EndOfStatement,
10271                  "unexpected token in '.arch_extension' directive"))
10272     return true;
10273 
10274   bool EnableFeature = true;
10275   if (Name.startswith_lower("no")) {
10276     EnableFeature = false;
10277     Name = Name.substr(2);
10278   }
10279   unsigned FeatureKind = ARM::parseArchExt(Name);
10280   if (FeatureKind == ARM::AEK_INVALID)
10281     return Error(ExtLoc, "unknown architectural extension: " + Name);
10282 
10283   for (const auto &Extension : Extensions) {
10284     if (Extension.Kind != FeatureKind)
10285       continue;
10286 
10287     if (Extension.Features.none())
10288       return Error(ExtLoc, "unsupported architectural extension: " + Name);
10289 
10290     if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck)
10291       return Error(ExtLoc, "architectural extension '" + Name +
10292                                "' is not "
10293                                "allowed for the current base architecture");
10294 
10295     MCSubtargetInfo &STI = copySTI();
10296     FeatureBitset ToggleFeatures = EnableFeature
10297       ? (~STI.getFeatureBits() & Extension.Features)
10298       : ( STI.getFeatureBits() & Extension.Features);
10299 
10300     uint64_t Features =
10301         ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
10302     setAvailableFeatures(Features);
10303     return false;
10304   }
10305 
10306   return Error(ExtLoc, "unknown architectural extension: " + Name);
10307 }
10308 
10309 // Define this matcher function after the auto-generated include so we
10310 // have the match class enum definitions.
10311 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
10312                                                   unsigned Kind) {
10313   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
10314   // If the kind is a token for a literal immediate, check if our asm
10315   // operand matches. This is for InstAliases which have a fixed-value
10316   // immediate in the syntax.
10317   switch (Kind) {
10318   default: break;
10319   case MCK__35_0:
10320     if (Op.isImm())
10321       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10322         if (CE->getValue() == 0)
10323           return Match_Success;
10324     break;
10325   case MCK_ModImm:
10326     if (Op.isImm()) {
10327       const MCExpr *SOExpr = Op.getImm();
10328       int64_t Value;
10329       if (!SOExpr->evaluateAsAbsolute(Value))
10330         return Match_Success;
10331       assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10332              "expression value must be representable in 32 bits");
10333     }
10334     break;
10335   case MCK_rGPR:
10336     if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
10337       return Match_Success;
10338     break;
10339   case MCK_GPRPair:
10340     if (Op.isReg() &&
10341         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10342       return Match_Success;
10343     break;
10344   }
10345   return Match_InvalidOperand;
10346 }
10347