1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "ARMBuildAttrs.h" 11 #include "ARMFPUName.h" 12 #include "ARMFeatures.h" 13 #include "llvm/MC/MCTargetAsmParser.h" 14 #include "MCTargetDesc/ARMAddressingModes.h" 15 #include "MCTargetDesc/ARMBaseInfo.h" 16 #include "MCTargetDesc/ARMMCExpr.h" 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/OwningPtr.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/ADT/StringSwitch.h" 22 #include "llvm/ADT/Twine.h" 23 #include "llvm/MC/MCAsmInfo.h" 24 #include "llvm/MC/MCAssembler.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCELFStreamer.h" 27 #include "llvm/MC/MCExpr.h" 28 #include "llvm/MC/MCInst.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCInstrInfo.h" 31 #include "llvm/MC/MCParser/MCAsmLexer.h" 32 #include "llvm/MC/MCParser/MCAsmParser.h" 33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 34 #include "llvm/MC/MCRegisterInfo.h" 35 #include "llvm/MC/MCStreamer.h" 36 #include "llvm/MC/MCSubtargetInfo.h" 37 #include "llvm/Support/ELF.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/SourceMgr.h" 40 #include "llvm/Support/TargetRegistry.h" 41 #include "llvm/Support/raw_ostream.h" 42 43 using namespace llvm; 44 45 namespace { 46 47 class ARMOperand; 48 49 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 50 51 class ARMAsmParser : public MCTargetAsmParser { 52 MCSubtargetInfo &STI; 53 MCAsmParser &Parser; 54 const MCInstrInfo &MII; 55 const MCRegisterInfo *MRI; 56 57 ARMTargetStreamer &getTargetStreamer() { 58 MCTargetStreamer &TS = getParser().getStreamer().getTargetStreamer(); 59 return static_cast<ARMTargetStreamer &>(TS); 60 } 61 62 // Unwind directives state 63 SMLoc FnStartLoc; 64 SMLoc CantUnwindLoc; 65 SMLoc PersonalityLoc; 66 SMLoc HandlerDataLoc; 67 int FPReg; 68 void resetUnwindDirectiveParserState() { 69 FnStartLoc = SMLoc(); 70 CantUnwindLoc = SMLoc(); 71 PersonalityLoc = SMLoc(); 72 HandlerDataLoc = SMLoc(); 73 FPReg = -1; 74 } 75 76 // Map of register aliases registers via the .req directive. 77 StringMap<unsigned> RegisterReqs; 78 79 bool NextSymbolIsThumb; 80 81 struct { 82 ARMCC::CondCodes Cond; // Condition for IT block. 83 unsigned Mask:4; // Condition mask for instructions. 84 // Starting at first 1 (from lsb). 85 // '1' condition as indicated in IT. 86 // '0' inverse of condition (else). 87 // Count of instructions in IT block is 88 // 4 - trailingzeroes(mask) 89 90 bool FirstCond; // Explicit flag for when we're parsing the 91 // First instruction in the IT block. It's 92 // implied in the mask, so needs special 93 // handling. 94 95 unsigned CurPosition; // Current position in parsing of IT 96 // block. In range [0,3]. Initialized 97 // according to count of instructions in block. 98 // ~0U if no active IT block. 99 } ITState; 100 bool inITBlock() { return ITState.CurPosition != ~0U;} 101 void forwardITPosition() { 102 if (!inITBlock()) return; 103 // Move to the next instruction in the IT block, if there is one. If not, 104 // mark the block as done. 105 unsigned TZ = countTrailingZeros(ITState.Mask); 106 if (++ITState.CurPosition == 5 - TZ) 107 ITState.CurPosition = ~0U; // Done with the IT block after this. 108 } 109 110 111 MCAsmParser &getParser() const { return Parser; } 112 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 113 114 bool Warning(SMLoc L, const Twine &Msg, 115 ArrayRef<SMRange> Ranges = None) { 116 return Parser.Warning(L, Msg, Ranges); 117 } 118 bool Error(SMLoc L, const Twine &Msg, 119 ArrayRef<SMRange> Ranges = None) { 120 return Parser.Error(L, Msg, Ranges); 121 } 122 123 int tryParseRegister(); 124 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 125 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 126 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 127 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 128 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 129 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 130 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 131 unsigned &ShiftAmount); 132 bool parseDirectiveWord(unsigned Size, SMLoc L); 133 bool parseDirectiveThumb(SMLoc L); 134 bool parseDirectiveARM(SMLoc L); 135 bool parseDirectiveThumbFunc(SMLoc L); 136 bool parseDirectiveCode(SMLoc L); 137 bool parseDirectiveSyntax(SMLoc L); 138 bool parseDirectiveReq(StringRef Name, SMLoc L); 139 bool parseDirectiveUnreq(SMLoc L); 140 bool parseDirectiveArch(SMLoc L); 141 bool parseDirectiveEabiAttr(SMLoc L); 142 bool parseDirectiveCPU(SMLoc L); 143 bool parseDirectiveFPU(SMLoc L); 144 bool parseDirectiveFnStart(SMLoc L); 145 bool parseDirectiveFnEnd(SMLoc L); 146 bool parseDirectiveCantUnwind(SMLoc L); 147 bool parseDirectivePersonality(SMLoc L); 148 bool parseDirectiveHandlerData(SMLoc L); 149 bool parseDirectiveSetFP(SMLoc L); 150 bool parseDirectivePad(SMLoc L); 151 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 152 153 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 154 bool &CarrySetting, unsigned &ProcessorIMod, 155 StringRef &ITMask); 156 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 157 bool &CanAcceptCarrySet, 158 bool &CanAcceptPredicationCode); 159 160 bool isThumb() const { 161 // FIXME: Can tablegen auto-generate this? 162 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 163 } 164 bool isThumbOne() const { 165 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 166 } 167 bool isThumbTwo() const { 168 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 169 } 170 bool hasThumb() const { 171 return STI.getFeatureBits() & ARM::HasV4TOps; 172 } 173 bool hasV6Ops() const { 174 return STI.getFeatureBits() & ARM::HasV6Ops; 175 } 176 bool hasV6MOps() const { 177 return STI.getFeatureBits() & ARM::HasV6MOps; 178 } 179 bool hasV7Ops() const { 180 return STI.getFeatureBits() & ARM::HasV7Ops; 181 } 182 bool hasV8Ops() const { 183 return STI.getFeatureBits() & ARM::HasV8Ops; 184 } 185 bool hasARM() const { 186 return !(STI.getFeatureBits() & ARM::FeatureNoARM); 187 } 188 189 void SwitchMode() { 190 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 191 setAvailableFeatures(FB); 192 } 193 bool isMClass() const { 194 return STI.getFeatureBits() & ARM::FeatureMClass; 195 } 196 197 /// @name Auto-generated Match Functions 198 /// { 199 200 #define GET_ASSEMBLER_HEADER 201 #include "ARMGenAsmMatcher.inc" 202 203 /// } 204 205 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 206 OperandMatchResultTy parseCoprocNumOperand( 207 SmallVectorImpl<MCParsedAsmOperand*>&); 208 OperandMatchResultTy parseCoprocRegOperand( 209 SmallVectorImpl<MCParsedAsmOperand*>&); 210 OperandMatchResultTy parseCoprocOptionOperand( 211 SmallVectorImpl<MCParsedAsmOperand*>&); 212 OperandMatchResultTy parseMemBarrierOptOperand( 213 SmallVectorImpl<MCParsedAsmOperand*>&); 214 OperandMatchResultTy parseInstSyncBarrierOptOperand( 215 SmallVectorImpl<MCParsedAsmOperand*>&); 216 OperandMatchResultTy parseProcIFlagsOperand( 217 SmallVectorImpl<MCParsedAsmOperand*>&); 218 OperandMatchResultTy parseMSRMaskOperand( 219 SmallVectorImpl<MCParsedAsmOperand*>&); 220 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 221 StringRef Op, int Low, int High); 222 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 223 return parsePKHImm(O, "lsl", 0, 31); 224 } 225 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 226 return parsePKHImm(O, "asr", 1, 32); 227 } 228 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 229 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 230 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 231 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 232 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 233 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 234 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 235 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 236 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 237 SMLoc &EndLoc); 238 239 // Asm Match Converter Methods 240 void cvtThumbMultiply(MCInst &Inst, 241 const SmallVectorImpl<MCParsedAsmOperand*> &); 242 void cvtThumbBranches(MCInst &Inst, 243 const SmallVectorImpl<MCParsedAsmOperand*> &); 244 245 bool validateInstruction(MCInst &Inst, 246 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 247 bool processInstruction(MCInst &Inst, 248 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 249 bool shouldOmitCCOutOperand(StringRef Mnemonic, 250 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 251 bool shouldOmitPredicateOperand(StringRef Mnemonic, 252 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 253 public: 254 enum ARMMatchResultTy { 255 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 256 Match_RequiresNotITBlock, 257 Match_RequiresV6, 258 Match_RequiresThumb2, 259 #define GET_OPERAND_DIAGNOSTIC_TYPES 260 #include "ARMGenAsmMatcher.inc" 261 262 }; 263 264 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, 265 const MCInstrInfo &MII) 266 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), FPReg(-1) { 267 MCAsmParserExtension::Initialize(_Parser); 268 269 // Cache the MCRegisterInfo. 270 MRI = getContext().getRegisterInfo(); 271 272 // Initialize the set of available features. 273 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 274 275 // Not in an ITBlock to start with. 276 ITState.CurPosition = ~0U; 277 278 NextSymbolIsThumb = false; 279 } 280 281 // Implementation of the MCTargetAsmParser interface: 282 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 283 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 284 SMLoc NameLoc, 285 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 286 bool ParseDirective(AsmToken DirectiveID); 287 288 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); 289 unsigned checkTargetMatchPredicate(MCInst &Inst); 290 291 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 292 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 293 MCStreamer &Out, unsigned &ErrorInfo, 294 bool MatchingInlineAsm); 295 void onLabelParsed(MCSymbol *Symbol); 296 297 }; 298 } // end anonymous namespace 299 300 namespace { 301 302 /// ARMOperand - Instances of this class represent a parsed ARM machine 303 /// operand. 304 class ARMOperand : public MCParsedAsmOperand { 305 enum KindTy { 306 k_CondCode, 307 k_CCOut, 308 k_ITCondMask, 309 k_CoprocNum, 310 k_CoprocReg, 311 k_CoprocOption, 312 k_Immediate, 313 k_MemBarrierOpt, 314 k_InstSyncBarrierOpt, 315 k_Memory, 316 k_PostIndexRegister, 317 k_MSRMask, 318 k_ProcIFlags, 319 k_VectorIndex, 320 k_Register, 321 k_RegisterList, 322 k_DPRRegisterList, 323 k_SPRRegisterList, 324 k_VectorList, 325 k_VectorListAllLanes, 326 k_VectorListIndexed, 327 k_ShiftedRegister, 328 k_ShiftedImmediate, 329 k_ShifterImmediate, 330 k_RotateImmediate, 331 k_BitfieldDescriptor, 332 k_Token 333 } Kind; 334 335 SMLoc StartLoc, EndLoc; 336 SmallVector<unsigned, 8> Registers; 337 338 struct CCOp { 339 ARMCC::CondCodes Val; 340 }; 341 342 struct CopOp { 343 unsigned Val; 344 }; 345 346 struct CoprocOptionOp { 347 unsigned Val; 348 }; 349 350 struct ITMaskOp { 351 unsigned Mask:4; 352 }; 353 354 struct MBOptOp { 355 ARM_MB::MemBOpt Val; 356 }; 357 358 struct ISBOptOp { 359 ARM_ISB::InstSyncBOpt Val; 360 }; 361 362 struct IFlagsOp { 363 ARM_PROC::IFlags Val; 364 }; 365 366 struct MMaskOp { 367 unsigned Val; 368 }; 369 370 struct TokOp { 371 const char *Data; 372 unsigned Length; 373 }; 374 375 struct RegOp { 376 unsigned RegNum; 377 }; 378 379 // A vector register list is a sequential list of 1 to 4 registers. 380 struct VectorListOp { 381 unsigned RegNum; 382 unsigned Count; 383 unsigned LaneIndex; 384 bool isDoubleSpaced; 385 }; 386 387 struct VectorIndexOp { 388 unsigned Val; 389 }; 390 391 struct ImmOp { 392 const MCExpr *Val; 393 }; 394 395 /// Combined record for all forms of ARM address expressions. 396 struct MemoryOp { 397 unsigned BaseRegNum; 398 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 399 // was specified. 400 const MCConstantExpr *OffsetImm; // Offset immediate value 401 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 402 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 403 unsigned ShiftImm; // shift for OffsetReg. 404 unsigned Alignment; // 0 = no alignment specified 405 // n = alignment in bytes (2, 4, 8, 16, or 32) 406 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 407 }; 408 409 struct PostIdxRegOp { 410 unsigned RegNum; 411 bool isAdd; 412 ARM_AM::ShiftOpc ShiftTy; 413 unsigned ShiftImm; 414 }; 415 416 struct ShifterImmOp { 417 bool isASR; 418 unsigned Imm; 419 }; 420 421 struct RegShiftedRegOp { 422 ARM_AM::ShiftOpc ShiftTy; 423 unsigned SrcReg; 424 unsigned ShiftReg; 425 unsigned ShiftImm; 426 }; 427 428 struct RegShiftedImmOp { 429 ARM_AM::ShiftOpc ShiftTy; 430 unsigned SrcReg; 431 unsigned ShiftImm; 432 }; 433 434 struct RotImmOp { 435 unsigned Imm; 436 }; 437 438 struct BitfieldOp { 439 unsigned LSB; 440 unsigned Width; 441 }; 442 443 union { 444 struct CCOp CC; 445 struct CopOp Cop; 446 struct CoprocOptionOp CoprocOption; 447 struct MBOptOp MBOpt; 448 struct ISBOptOp ISBOpt; 449 struct ITMaskOp ITMask; 450 struct IFlagsOp IFlags; 451 struct MMaskOp MMask; 452 struct TokOp Tok; 453 struct RegOp Reg; 454 struct VectorListOp VectorList; 455 struct VectorIndexOp VectorIndex; 456 struct ImmOp Imm; 457 struct MemoryOp Memory; 458 struct PostIdxRegOp PostIdxReg; 459 struct ShifterImmOp ShifterImm; 460 struct RegShiftedRegOp RegShiftedReg; 461 struct RegShiftedImmOp RegShiftedImm; 462 struct RotImmOp RotImm; 463 struct BitfieldOp Bitfield; 464 }; 465 466 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 467 public: 468 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 469 Kind = o.Kind; 470 StartLoc = o.StartLoc; 471 EndLoc = o.EndLoc; 472 switch (Kind) { 473 case k_CondCode: 474 CC = o.CC; 475 break; 476 case k_ITCondMask: 477 ITMask = o.ITMask; 478 break; 479 case k_Token: 480 Tok = o.Tok; 481 break; 482 case k_CCOut: 483 case k_Register: 484 Reg = o.Reg; 485 break; 486 case k_RegisterList: 487 case k_DPRRegisterList: 488 case k_SPRRegisterList: 489 Registers = o.Registers; 490 break; 491 case k_VectorList: 492 case k_VectorListAllLanes: 493 case k_VectorListIndexed: 494 VectorList = o.VectorList; 495 break; 496 case k_CoprocNum: 497 case k_CoprocReg: 498 Cop = o.Cop; 499 break; 500 case k_CoprocOption: 501 CoprocOption = o.CoprocOption; 502 break; 503 case k_Immediate: 504 Imm = o.Imm; 505 break; 506 case k_MemBarrierOpt: 507 MBOpt = o.MBOpt; 508 break; 509 case k_InstSyncBarrierOpt: 510 ISBOpt = o.ISBOpt; 511 case k_Memory: 512 Memory = o.Memory; 513 break; 514 case k_PostIndexRegister: 515 PostIdxReg = o.PostIdxReg; 516 break; 517 case k_MSRMask: 518 MMask = o.MMask; 519 break; 520 case k_ProcIFlags: 521 IFlags = o.IFlags; 522 break; 523 case k_ShifterImmediate: 524 ShifterImm = o.ShifterImm; 525 break; 526 case k_ShiftedRegister: 527 RegShiftedReg = o.RegShiftedReg; 528 break; 529 case k_ShiftedImmediate: 530 RegShiftedImm = o.RegShiftedImm; 531 break; 532 case k_RotateImmediate: 533 RotImm = o.RotImm; 534 break; 535 case k_BitfieldDescriptor: 536 Bitfield = o.Bitfield; 537 break; 538 case k_VectorIndex: 539 VectorIndex = o.VectorIndex; 540 break; 541 } 542 } 543 544 /// getStartLoc - Get the location of the first token of this operand. 545 SMLoc getStartLoc() const { return StartLoc; } 546 /// getEndLoc - Get the location of the last token of this operand. 547 SMLoc getEndLoc() const { return EndLoc; } 548 /// getLocRange - Get the range between the first and last token of this 549 /// operand. 550 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 551 552 ARMCC::CondCodes getCondCode() const { 553 assert(Kind == k_CondCode && "Invalid access!"); 554 return CC.Val; 555 } 556 557 unsigned getCoproc() const { 558 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 559 return Cop.Val; 560 } 561 562 StringRef getToken() const { 563 assert(Kind == k_Token && "Invalid access!"); 564 return StringRef(Tok.Data, Tok.Length); 565 } 566 567 unsigned getReg() const { 568 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 569 return Reg.RegNum; 570 } 571 572 const SmallVectorImpl<unsigned> &getRegList() const { 573 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 574 Kind == k_SPRRegisterList) && "Invalid access!"); 575 return Registers; 576 } 577 578 const MCExpr *getImm() const { 579 assert(isImm() && "Invalid access!"); 580 return Imm.Val; 581 } 582 583 unsigned getVectorIndex() const { 584 assert(Kind == k_VectorIndex && "Invalid access!"); 585 return VectorIndex.Val; 586 } 587 588 ARM_MB::MemBOpt getMemBarrierOpt() const { 589 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 590 return MBOpt.Val; 591 } 592 593 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 594 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 595 return ISBOpt.Val; 596 } 597 598 ARM_PROC::IFlags getProcIFlags() const { 599 assert(Kind == k_ProcIFlags && "Invalid access!"); 600 return IFlags.Val; 601 } 602 603 unsigned getMSRMask() const { 604 assert(Kind == k_MSRMask && "Invalid access!"); 605 return MMask.Val; 606 } 607 608 bool isCoprocNum() const { return Kind == k_CoprocNum; } 609 bool isCoprocReg() const { return Kind == k_CoprocReg; } 610 bool isCoprocOption() const { return Kind == k_CoprocOption; } 611 bool isCondCode() const { return Kind == k_CondCode; } 612 bool isCCOut() const { return Kind == k_CCOut; } 613 bool isITMask() const { return Kind == k_ITCondMask; } 614 bool isITCondCode() const { return Kind == k_CondCode; } 615 bool isImm() const { return Kind == k_Immediate; } 616 // checks whether this operand is an unsigned offset which fits is a field 617 // of specified width and scaled by a specific number of bits 618 template<unsigned width, unsigned scale> 619 bool isUnsignedOffset() const { 620 if (!isImm()) return false; 621 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 622 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 623 int64_t Val = CE->getValue(); 624 int64_t Align = 1LL << scale; 625 int64_t Max = Align * ((1LL << width) - 1); 626 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); 627 } 628 return false; 629 } 630 // checks whether this operand is an signed offset which fits is a field 631 // of specified width and scaled by a specific number of bits 632 template<unsigned width, unsigned scale> 633 bool isSignedOffset() const { 634 if (!isImm()) return false; 635 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 636 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 637 int64_t Val = CE->getValue(); 638 int64_t Align = 1LL << scale; 639 int64_t Max = Align * ((1LL << (width-1)) - 1); 640 int64_t Min = -Align * (1LL << (width-1)); 641 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); 642 } 643 return false; 644 } 645 646 // checks whether this operand is a memory operand computed as an offset 647 // applied to PC. the offset may have 8 bits of magnitude and is represented 648 // with two bits of shift. textually it may be either [pc, #imm], #imm or 649 // relocable expression... 650 bool isThumbMemPC() const { 651 int64_t Val = 0; 652 if (isImm()) { 653 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); 655 if (!CE) return false; 656 Val = CE->getValue(); 657 } 658 else if (isMem()) { 659 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; 660 if(Memory.BaseRegNum != ARM::PC) return false; 661 Val = Memory.OffsetImm->getValue(); 662 } 663 else return false; 664 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); 665 } 666 bool isFPImm() const { 667 if (!isImm()) return false; 668 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 669 if (!CE) return false; 670 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 671 return Val != -1; 672 } 673 bool isFBits16() const { 674 if (!isImm()) return false; 675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 676 if (!CE) return false; 677 int64_t Value = CE->getValue(); 678 return Value >= 0 && Value <= 16; 679 } 680 bool isFBits32() const { 681 if (!isImm()) return false; 682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 683 if (!CE) return false; 684 int64_t Value = CE->getValue(); 685 return Value >= 1 && Value <= 32; 686 } 687 bool isImm8s4() const { 688 if (!isImm()) return false; 689 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 690 if (!CE) return false; 691 int64_t Value = CE->getValue(); 692 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 693 } 694 bool isImm0_1020s4() const { 695 if (!isImm()) return false; 696 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 697 if (!CE) return false; 698 int64_t Value = CE->getValue(); 699 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 700 } 701 bool isImm0_508s4() const { 702 if (!isImm()) return false; 703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 704 if (!CE) return false; 705 int64_t Value = CE->getValue(); 706 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 707 } 708 bool isImm0_508s4Neg() const { 709 if (!isImm()) return false; 710 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 711 if (!CE) return false; 712 int64_t Value = -CE->getValue(); 713 // explicitly exclude zero. we want that to use the normal 0_508 version. 714 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 715 } 716 bool isImm0_239() const { 717 if (!isImm()) return false; 718 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 719 if (!CE) return false; 720 int64_t Value = CE->getValue(); 721 return Value >= 0 && Value < 240; 722 } 723 bool isImm0_255() const { 724 if (!isImm()) return false; 725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 726 if (!CE) return false; 727 int64_t Value = CE->getValue(); 728 return Value >= 0 && Value < 256; 729 } 730 bool isImm0_4095() const { 731 if (!isImm()) return false; 732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 733 if (!CE) return false; 734 int64_t Value = CE->getValue(); 735 return Value >= 0 && Value < 4096; 736 } 737 bool isImm0_4095Neg() const { 738 if (!isImm()) return false; 739 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 740 if (!CE) return false; 741 int64_t Value = -CE->getValue(); 742 return Value > 0 && Value < 4096; 743 } 744 bool isImm0_1() const { 745 if (!isImm()) return false; 746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 747 if (!CE) return false; 748 int64_t Value = CE->getValue(); 749 return Value >= 0 && Value < 2; 750 } 751 bool isImm0_3() const { 752 if (!isImm()) return false; 753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 754 if (!CE) return false; 755 int64_t Value = CE->getValue(); 756 return Value >= 0 && Value < 4; 757 } 758 bool isImm0_7() const { 759 if (!isImm()) return false; 760 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 761 if (!CE) return false; 762 int64_t Value = CE->getValue(); 763 return Value >= 0 && Value < 8; 764 } 765 bool isImm0_15() const { 766 if (!isImm()) return false; 767 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 768 if (!CE) return false; 769 int64_t Value = CE->getValue(); 770 return Value >= 0 && Value < 16; 771 } 772 bool isImm0_31() const { 773 if (!isImm()) return false; 774 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 775 if (!CE) return false; 776 int64_t Value = CE->getValue(); 777 return Value >= 0 && Value < 32; 778 } 779 bool isImm0_63() const { 780 if (!isImm()) return false; 781 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 782 if (!CE) return false; 783 int64_t Value = CE->getValue(); 784 return Value >= 0 && Value < 64; 785 } 786 bool isImm8() const { 787 if (!isImm()) return false; 788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 789 if (!CE) return false; 790 int64_t Value = CE->getValue(); 791 return Value == 8; 792 } 793 bool isImm16() const { 794 if (!isImm()) return false; 795 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 796 if (!CE) return false; 797 int64_t Value = CE->getValue(); 798 return Value == 16; 799 } 800 bool isImm32() const { 801 if (!isImm()) return false; 802 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 803 if (!CE) return false; 804 int64_t Value = CE->getValue(); 805 return Value == 32; 806 } 807 bool isShrImm8() const { 808 if (!isImm()) return false; 809 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 810 if (!CE) return false; 811 int64_t Value = CE->getValue(); 812 return Value > 0 && Value <= 8; 813 } 814 bool isShrImm16() const { 815 if (!isImm()) return false; 816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 817 if (!CE) return false; 818 int64_t Value = CE->getValue(); 819 return Value > 0 && Value <= 16; 820 } 821 bool isShrImm32() const { 822 if (!isImm()) return false; 823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 824 if (!CE) return false; 825 int64_t Value = CE->getValue(); 826 return Value > 0 && Value <= 32; 827 } 828 bool isShrImm64() const { 829 if (!isImm()) return false; 830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 831 if (!CE) return false; 832 int64_t Value = CE->getValue(); 833 return Value > 0 && Value <= 64; 834 } 835 bool isImm1_7() const { 836 if (!isImm()) return false; 837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 838 if (!CE) return false; 839 int64_t Value = CE->getValue(); 840 return Value > 0 && Value < 8; 841 } 842 bool isImm1_15() const { 843 if (!isImm()) return false; 844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 845 if (!CE) return false; 846 int64_t Value = CE->getValue(); 847 return Value > 0 && Value < 16; 848 } 849 bool isImm1_31() const { 850 if (!isImm()) return false; 851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 852 if (!CE) return false; 853 int64_t Value = CE->getValue(); 854 return Value > 0 && Value < 32; 855 } 856 bool isImm1_16() const { 857 if (!isImm()) return false; 858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 859 if (!CE) return false; 860 int64_t Value = CE->getValue(); 861 return Value > 0 && Value < 17; 862 } 863 bool isImm1_32() const { 864 if (!isImm()) return false; 865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 866 if (!CE) return false; 867 int64_t Value = CE->getValue(); 868 return Value > 0 && Value < 33; 869 } 870 bool isImm0_32() const { 871 if (!isImm()) return false; 872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 873 if (!CE) return false; 874 int64_t Value = CE->getValue(); 875 return Value >= 0 && Value < 33; 876 } 877 bool isImm0_65535() const { 878 if (!isImm()) return false; 879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 880 if (!CE) return false; 881 int64_t Value = CE->getValue(); 882 return Value >= 0 && Value < 65536; 883 } 884 bool isImm256_65535Expr() const { 885 if (!isImm()) return false; 886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 887 // If it's not a constant expression, it'll generate a fixup and be 888 // handled later. 889 if (!CE) return true; 890 int64_t Value = CE->getValue(); 891 return Value >= 256 && Value < 65536; 892 } 893 bool isImm0_65535Expr() const { 894 if (!isImm()) return false; 895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 896 // If it's not a constant expression, it'll generate a fixup and be 897 // handled later. 898 if (!CE) return true; 899 int64_t Value = CE->getValue(); 900 return Value >= 0 && Value < 65536; 901 } 902 bool isImm24bit() const { 903 if (!isImm()) return false; 904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 905 if (!CE) return false; 906 int64_t Value = CE->getValue(); 907 return Value >= 0 && Value <= 0xffffff; 908 } 909 bool isImmThumbSR() const { 910 if (!isImm()) return false; 911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 912 if (!CE) return false; 913 int64_t Value = CE->getValue(); 914 return Value > 0 && Value < 33; 915 } 916 bool isPKHLSLImm() const { 917 if (!isImm()) return false; 918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 919 if (!CE) return false; 920 int64_t Value = CE->getValue(); 921 return Value >= 0 && Value < 32; 922 } 923 bool isPKHASRImm() const { 924 if (!isImm()) return false; 925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 926 if (!CE) return false; 927 int64_t Value = CE->getValue(); 928 return Value > 0 && Value <= 32; 929 } 930 bool isAdrLabel() const { 931 // If we have an immediate that's not a constant, treat it as a label 932 // reference needing a fixup. If it is a constant, but it can't fit 933 // into shift immediate encoding, we reject it. 934 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 935 else return (isARMSOImm() || isARMSOImmNeg()); 936 } 937 bool isARMSOImm() const { 938 if (!isImm()) return false; 939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 940 if (!CE) return false; 941 int64_t Value = CE->getValue(); 942 return ARM_AM::getSOImmVal(Value) != -1; 943 } 944 bool isARMSOImmNot() const { 945 if (!isImm()) return false; 946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 947 if (!CE) return false; 948 int64_t Value = CE->getValue(); 949 return ARM_AM::getSOImmVal(~Value) != -1; 950 } 951 bool isARMSOImmNeg() const { 952 if (!isImm()) return false; 953 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 954 if (!CE) return false; 955 int64_t Value = CE->getValue(); 956 // Only use this when not representable as a plain so_imm. 957 return ARM_AM::getSOImmVal(Value) == -1 && 958 ARM_AM::getSOImmVal(-Value) != -1; 959 } 960 bool isT2SOImm() const { 961 if (!isImm()) return false; 962 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 963 if (!CE) return false; 964 int64_t Value = CE->getValue(); 965 return ARM_AM::getT2SOImmVal(Value) != -1; 966 } 967 bool isT2SOImmNot() const { 968 if (!isImm()) return false; 969 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 970 if (!CE) return false; 971 int64_t Value = CE->getValue(); 972 return ARM_AM::getT2SOImmVal(Value) == -1 && 973 ARM_AM::getT2SOImmVal(~Value) != -1; 974 } 975 bool isT2SOImmNeg() const { 976 if (!isImm()) return false; 977 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 978 if (!CE) return false; 979 int64_t Value = CE->getValue(); 980 // Only use this when not representable as a plain so_imm. 981 return ARM_AM::getT2SOImmVal(Value) == -1 && 982 ARM_AM::getT2SOImmVal(-Value) != -1; 983 } 984 bool isSetEndImm() const { 985 if (!isImm()) return false; 986 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 987 if (!CE) return false; 988 int64_t Value = CE->getValue(); 989 return Value == 1 || Value == 0; 990 } 991 bool isReg() const { return Kind == k_Register; } 992 bool isRegList() const { return Kind == k_RegisterList; } 993 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 994 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 995 bool isToken() const { return Kind == k_Token; } 996 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 997 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 998 bool isMem() const { return Kind == k_Memory; } 999 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 1000 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 1001 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 1002 bool isRotImm() const { return Kind == k_RotateImmediate; } 1003 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 1004 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 1005 bool isPostIdxReg() const { 1006 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 1007 } 1008 bool isMemNoOffset(bool alignOK = false) const { 1009 if (!isMem()) 1010 return false; 1011 // No offset of any kind. 1012 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 1013 (alignOK || Memory.Alignment == 0); 1014 } 1015 bool isMemPCRelImm12() const { 1016 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1017 return false; 1018 // Base register must be PC. 1019 if (Memory.BaseRegNum != ARM::PC) 1020 return false; 1021 // Immediate offset in range [-4095, 4095]. 1022 if (!Memory.OffsetImm) return true; 1023 int64_t Val = Memory.OffsetImm->getValue(); 1024 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1025 } 1026 bool isAlignedMemory() const { 1027 return isMemNoOffset(true); 1028 } 1029 bool isAddrMode2() const { 1030 if (!isMem() || Memory.Alignment != 0) return false; 1031 // Check for register offset. 1032 if (Memory.OffsetRegNum) return true; 1033 // Immediate offset in range [-4095, 4095]. 1034 if (!Memory.OffsetImm) return true; 1035 int64_t Val = Memory.OffsetImm->getValue(); 1036 return Val > -4096 && Val < 4096; 1037 } 1038 bool isAM2OffsetImm() const { 1039 if (!isImm()) return false; 1040 // Immediate offset in range [-4095, 4095]. 1041 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1042 if (!CE) return false; 1043 int64_t Val = CE->getValue(); 1044 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 1045 } 1046 bool isAddrMode3() const { 1047 // If we have an immediate that's not a constant, treat it as a label 1048 // reference needing a fixup. If it is a constant, it's something else 1049 // and we reject it. 1050 if (isImm() && !isa<MCConstantExpr>(getImm())) 1051 return true; 1052 if (!isMem() || Memory.Alignment != 0) return false; 1053 // No shifts are legal for AM3. 1054 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1055 // Check for register offset. 1056 if (Memory.OffsetRegNum) return true; 1057 // Immediate offset in range [-255, 255]. 1058 if (!Memory.OffsetImm) return true; 1059 int64_t Val = Memory.OffsetImm->getValue(); 1060 // The #-0 offset is encoded as INT32_MIN, and we have to check 1061 // for this too. 1062 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1063 } 1064 bool isAM3Offset() const { 1065 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1066 return false; 1067 if (Kind == k_PostIndexRegister) 1068 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1069 // Immediate offset in range [-255, 255]. 1070 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1071 if (!CE) return false; 1072 int64_t Val = CE->getValue(); 1073 // Special case, #-0 is INT32_MIN. 1074 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1075 } 1076 bool isAddrMode5() const { 1077 // If we have an immediate that's not a constant, treat it as a label 1078 // reference needing a fixup. If it is a constant, it's something else 1079 // and we reject it. 1080 if (isImm() && !isa<MCConstantExpr>(getImm())) 1081 return true; 1082 if (!isMem() || Memory.Alignment != 0) return false; 1083 // Check for register offset. 1084 if (Memory.OffsetRegNum) return false; 1085 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1086 if (!Memory.OffsetImm) return true; 1087 int64_t Val = Memory.OffsetImm->getValue(); 1088 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1089 Val == INT32_MIN; 1090 } 1091 bool isMemTBB() const { 1092 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1093 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1094 return false; 1095 return true; 1096 } 1097 bool isMemTBH() const { 1098 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1099 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1100 Memory.Alignment != 0 ) 1101 return false; 1102 return true; 1103 } 1104 bool isMemRegOffset() const { 1105 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1106 return false; 1107 return true; 1108 } 1109 bool isT2MemRegOffset() const { 1110 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1111 Memory.Alignment != 0) 1112 return false; 1113 // Only lsl #{0, 1, 2, 3} allowed. 1114 if (Memory.ShiftType == ARM_AM::no_shift) 1115 return true; 1116 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1117 return false; 1118 return true; 1119 } 1120 bool isMemThumbRR() const { 1121 // Thumb reg+reg addressing is simple. Just two registers, a base and 1122 // an offset. No shifts, negations or any other complicating factors. 1123 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1124 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1125 return false; 1126 return isARMLowRegister(Memory.BaseRegNum) && 1127 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1128 } 1129 bool isMemThumbRIs4() const { 1130 if (!isMem() || Memory.OffsetRegNum != 0 || 1131 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1132 return false; 1133 // Immediate offset, multiple of 4 in range [0, 124]. 1134 if (!Memory.OffsetImm) return true; 1135 int64_t Val = Memory.OffsetImm->getValue(); 1136 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1137 } 1138 bool isMemThumbRIs2() const { 1139 if (!isMem() || Memory.OffsetRegNum != 0 || 1140 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1141 return false; 1142 // Immediate offset, multiple of 4 in range [0, 62]. 1143 if (!Memory.OffsetImm) return true; 1144 int64_t Val = Memory.OffsetImm->getValue(); 1145 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1146 } 1147 bool isMemThumbRIs1() const { 1148 if (!isMem() || Memory.OffsetRegNum != 0 || 1149 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1150 return false; 1151 // Immediate offset in range [0, 31]. 1152 if (!Memory.OffsetImm) return true; 1153 int64_t Val = Memory.OffsetImm->getValue(); 1154 return Val >= 0 && Val <= 31; 1155 } 1156 bool isMemThumbSPI() const { 1157 if (!isMem() || Memory.OffsetRegNum != 0 || 1158 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1159 return false; 1160 // Immediate offset, multiple of 4 in range [0, 1020]. 1161 if (!Memory.OffsetImm) return true; 1162 int64_t Val = Memory.OffsetImm->getValue(); 1163 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1164 } 1165 bool isMemImm8s4Offset() const { 1166 // If we have an immediate that's not a constant, treat it as a label 1167 // reference needing a fixup. If it is a constant, it's something else 1168 // and we reject it. 1169 if (isImm() && !isa<MCConstantExpr>(getImm())) 1170 return true; 1171 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1172 return false; 1173 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1174 if (!Memory.OffsetImm) return true; 1175 int64_t Val = Memory.OffsetImm->getValue(); 1176 // Special case, #-0 is INT32_MIN. 1177 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1178 } 1179 bool isMemImm0_1020s4Offset() const { 1180 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1181 return false; 1182 // Immediate offset a multiple of 4 in range [0, 1020]. 1183 if (!Memory.OffsetImm) return true; 1184 int64_t Val = Memory.OffsetImm->getValue(); 1185 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1186 } 1187 bool isMemImm8Offset() const { 1188 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1189 return false; 1190 // Base reg of PC isn't allowed for these encodings. 1191 if (Memory.BaseRegNum == ARM::PC) return false; 1192 // Immediate offset in range [-255, 255]. 1193 if (!Memory.OffsetImm) return true; 1194 int64_t Val = Memory.OffsetImm->getValue(); 1195 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1196 } 1197 bool isMemPosImm8Offset() const { 1198 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1199 return false; 1200 // Immediate offset in range [0, 255]. 1201 if (!Memory.OffsetImm) return true; 1202 int64_t Val = Memory.OffsetImm->getValue(); 1203 return Val >= 0 && Val < 256; 1204 } 1205 bool isMemNegImm8Offset() const { 1206 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1207 return false; 1208 // Base reg of PC isn't allowed for these encodings. 1209 if (Memory.BaseRegNum == ARM::PC) return false; 1210 // Immediate offset in range [-255, -1]. 1211 if (!Memory.OffsetImm) return false; 1212 int64_t Val = Memory.OffsetImm->getValue(); 1213 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1214 } 1215 bool isMemUImm12Offset() const { 1216 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1217 return false; 1218 // Immediate offset in range [0, 4095]. 1219 if (!Memory.OffsetImm) return true; 1220 int64_t Val = Memory.OffsetImm->getValue(); 1221 return (Val >= 0 && Val < 4096); 1222 } 1223 bool isMemImm12Offset() const { 1224 // If we have an immediate that's not a constant, treat it as a label 1225 // reference needing a fixup. If it is a constant, it's something else 1226 // and we reject it. 1227 if (isImm() && !isa<MCConstantExpr>(getImm())) 1228 return true; 1229 1230 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1231 return false; 1232 // Immediate offset in range [-4095, 4095]. 1233 if (!Memory.OffsetImm) return true; 1234 int64_t Val = Memory.OffsetImm->getValue(); 1235 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1236 } 1237 bool isPostIdxImm8() const { 1238 if (!isImm()) return false; 1239 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1240 if (!CE) return false; 1241 int64_t Val = CE->getValue(); 1242 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1243 } 1244 bool isPostIdxImm8s4() const { 1245 if (!isImm()) return false; 1246 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1247 if (!CE) return false; 1248 int64_t Val = CE->getValue(); 1249 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1250 (Val == INT32_MIN); 1251 } 1252 1253 bool isMSRMask() const { return Kind == k_MSRMask; } 1254 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1255 1256 // NEON operands. 1257 bool isSingleSpacedVectorList() const { 1258 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1259 } 1260 bool isDoubleSpacedVectorList() const { 1261 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1262 } 1263 bool isVecListOneD() const { 1264 if (!isSingleSpacedVectorList()) return false; 1265 return VectorList.Count == 1; 1266 } 1267 1268 bool isVecListDPair() const { 1269 if (!isSingleSpacedVectorList()) return false; 1270 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1271 .contains(VectorList.RegNum)); 1272 } 1273 1274 bool isVecListThreeD() const { 1275 if (!isSingleSpacedVectorList()) return false; 1276 return VectorList.Count == 3; 1277 } 1278 1279 bool isVecListFourD() const { 1280 if (!isSingleSpacedVectorList()) return false; 1281 return VectorList.Count == 4; 1282 } 1283 1284 bool isVecListDPairSpaced() const { 1285 if (isSingleSpacedVectorList()) return false; 1286 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1287 .contains(VectorList.RegNum)); 1288 } 1289 1290 bool isVecListThreeQ() const { 1291 if (!isDoubleSpacedVectorList()) return false; 1292 return VectorList.Count == 3; 1293 } 1294 1295 bool isVecListFourQ() const { 1296 if (!isDoubleSpacedVectorList()) return false; 1297 return VectorList.Count == 4; 1298 } 1299 1300 bool isSingleSpacedVectorAllLanes() const { 1301 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1302 } 1303 bool isDoubleSpacedVectorAllLanes() const { 1304 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1305 } 1306 bool isVecListOneDAllLanes() const { 1307 if (!isSingleSpacedVectorAllLanes()) return false; 1308 return VectorList.Count == 1; 1309 } 1310 1311 bool isVecListDPairAllLanes() const { 1312 if (!isSingleSpacedVectorAllLanes()) return false; 1313 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1314 .contains(VectorList.RegNum)); 1315 } 1316 1317 bool isVecListDPairSpacedAllLanes() const { 1318 if (!isDoubleSpacedVectorAllLanes()) return false; 1319 return VectorList.Count == 2; 1320 } 1321 1322 bool isVecListThreeDAllLanes() const { 1323 if (!isSingleSpacedVectorAllLanes()) return false; 1324 return VectorList.Count == 3; 1325 } 1326 1327 bool isVecListThreeQAllLanes() const { 1328 if (!isDoubleSpacedVectorAllLanes()) return false; 1329 return VectorList.Count == 3; 1330 } 1331 1332 bool isVecListFourDAllLanes() const { 1333 if (!isSingleSpacedVectorAllLanes()) return false; 1334 return VectorList.Count == 4; 1335 } 1336 1337 bool isVecListFourQAllLanes() const { 1338 if (!isDoubleSpacedVectorAllLanes()) return false; 1339 return VectorList.Count == 4; 1340 } 1341 1342 bool isSingleSpacedVectorIndexed() const { 1343 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1344 } 1345 bool isDoubleSpacedVectorIndexed() const { 1346 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1347 } 1348 bool isVecListOneDByteIndexed() const { 1349 if (!isSingleSpacedVectorIndexed()) return false; 1350 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1351 } 1352 1353 bool isVecListOneDHWordIndexed() const { 1354 if (!isSingleSpacedVectorIndexed()) return false; 1355 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1356 } 1357 1358 bool isVecListOneDWordIndexed() const { 1359 if (!isSingleSpacedVectorIndexed()) return false; 1360 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1361 } 1362 1363 bool isVecListTwoDByteIndexed() const { 1364 if (!isSingleSpacedVectorIndexed()) return false; 1365 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1366 } 1367 1368 bool isVecListTwoDHWordIndexed() const { 1369 if (!isSingleSpacedVectorIndexed()) return false; 1370 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1371 } 1372 1373 bool isVecListTwoQWordIndexed() const { 1374 if (!isDoubleSpacedVectorIndexed()) return false; 1375 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1376 } 1377 1378 bool isVecListTwoQHWordIndexed() const { 1379 if (!isDoubleSpacedVectorIndexed()) return false; 1380 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1381 } 1382 1383 bool isVecListTwoDWordIndexed() const { 1384 if (!isSingleSpacedVectorIndexed()) return false; 1385 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1386 } 1387 1388 bool isVecListThreeDByteIndexed() const { 1389 if (!isSingleSpacedVectorIndexed()) return false; 1390 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1391 } 1392 1393 bool isVecListThreeDHWordIndexed() const { 1394 if (!isSingleSpacedVectorIndexed()) return false; 1395 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1396 } 1397 1398 bool isVecListThreeQWordIndexed() const { 1399 if (!isDoubleSpacedVectorIndexed()) return false; 1400 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1401 } 1402 1403 bool isVecListThreeQHWordIndexed() const { 1404 if (!isDoubleSpacedVectorIndexed()) return false; 1405 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1406 } 1407 1408 bool isVecListThreeDWordIndexed() const { 1409 if (!isSingleSpacedVectorIndexed()) return false; 1410 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1411 } 1412 1413 bool isVecListFourDByteIndexed() const { 1414 if (!isSingleSpacedVectorIndexed()) return false; 1415 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1416 } 1417 1418 bool isVecListFourDHWordIndexed() const { 1419 if (!isSingleSpacedVectorIndexed()) return false; 1420 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1421 } 1422 1423 bool isVecListFourQWordIndexed() const { 1424 if (!isDoubleSpacedVectorIndexed()) return false; 1425 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1426 } 1427 1428 bool isVecListFourQHWordIndexed() const { 1429 if (!isDoubleSpacedVectorIndexed()) return false; 1430 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1431 } 1432 1433 bool isVecListFourDWordIndexed() const { 1434 if (!isSingleSpacedVectorIndexed()) return false; 1435 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1436 } 1437 1438 bool isVectorIndex8() const { 1439 if (Kind != k_VectorIndex) return false; 1440 return VectorIndex.Val < 8; 1441 } 1442 bool isVectorIndex16() const { 1443 if (Kind != k_VectorIndex) return false; 1444 return VectorIndex.Val < 4; 1445 } 1446 bool isVectorIndex32() const { 1447 if (Kind != k_VectorIndex) return false; 1448 return VectorIndex.Val < 2; 1449 } 1450 1451 bool isNEONi8splat() const { 1452 if (!isImm()) return false; 1453 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1454 // Must be a constant. 1455 if (!CE) return false; 1456 int64_t Value = CE->getValue(); 1457 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1458 // value. 1459 return Value >= 0 && Value < 256; 1460 } 1461 1462 bool isNEONi16splat() const { 1463 if (!isImm()) return false; 1464 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1465 // Must be a constant. 1466 if (!CE) return false; 1467 int64_t Value = CE->getValue(); 1468 // i16 value in the range [0,255] or [0x0100, 0xff00] 1469 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1470 } 1471 1472 bool isNEONi32splat() const { 1473 if (!isImm()) return false; 1474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1475 // Must be a constant. 1476 if (!CE) return false; 1477 int64_t Value = CE->getValue(); 1478 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1479 return (Value >= 0 && Value < 256) || 1480 (Value >= 0x0100 && Value <= 0xff00) || 1481 (Value >= 0x010000 && Value <= 0xff0000) || 1482 (Value >= 0x01000000 && Value <= 0xff000000); 1483 } 1484 1485 bool isNEONi32vmov() const { 1486 if (!isImm()) return false; 1487 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1488 // Must be a constant. 1489 if (!CE) return false; 1490 int64_t Value = CE->getValue(); 1491 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1492 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1493 return (Value >= 0 && Value < 256) || 1494 (Value >= 0x0100 && Value <= 0xff00) || 1495 (Value >= 0x010000 && Value <= 0xff0000) || 1496 (Value >= 0x01000000 && Value <= 0xff000000) || 1497 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1498 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1499 } 1500 bool isNEONi32vmovNeg() const { 1501 if (!isImm()) return false; 1502 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1503 // Must be a constant. 1504 if (!CE) return false; 1505 int64_t Value = ~CE->getValue(); 1506 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1507 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1508 return (Value >= 0 && Value < 256) || 1509 (Value >= 0x0100 && Value <= 0xff00) || 1510 (Value >= 0x010000 && Value <= 0xff0000) || 1511 (Value >= 0x01000000 && Value <= 0xff000000) || 1512 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1513 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1514 } 1515 1516 bool isNEONi64splat() const { 1517 if (!isImm()) return false; 1518 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1519 // Must be a constant. 1520 if (!CE) return false; 1521 uint64_t Value = CE->getValue(); 1522 // i64 value with each byte being either 0 or 0xff. 1523 for (unsigned i = 0; i < 8; ++i) 1524 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1525 return true; 1526 } 1527 1528 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1529 // Add as immediates when possible. Null MCExpr = 0. 1530 if (Expr == 0) 1531 Inst.addOperand(MCOperand::CreateImm(0)); 1532 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1533 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1534 else 1535 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1536 } 1537 1538 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1539 assert(N == 2 && "Invalid number of operands!"); 1540 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1541 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1542 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1543 } 1544 1545 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1546 assert(N == 1 && "Invalid number of operands!"); 1547 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1548 } 1549 1550 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1551 assert(N == 1 && "Invalid number of operands!"); 1552 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1553 } 1554 1555 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1556 assert(N == 1 && "Invalid number of operands!"); 1557 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1558 } 1559 1560 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1561 assert(N == 1 && "Invalid number of operands!"); 1562 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1563 } 1564 1565 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1566 assert(N == 1 && "Invalid number of operands!"); 1567 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1568 } 1569 1570 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1571 assert(N == 1 && "Invalid number of operands!"); 1572 Inst.addOperand(MCOperand::CreateReg(getReg())); 1573 } 1574 1575 void addRegOperands(MCInst &Inst, unsigned N) const { 1576 assert(N == 1 && "Invalid number of operands!"); 1577 Inst.addOperand(MCOperand::CreateReg(getReg())); 1578 } 1579 1580 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1581 assert(N == 3 && "Invalid number of operands!"); 1582 assert(isRegShiftedReg() && 1583 "addRegShiftedRegOperands() on non RegShiftedReg!"); 1584 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1585 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1586 Inst.addOperand(MCOperand::CreateImm( 1587 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1588 } 1589 1590 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1591 assert(N == 2 && "Invalid number of operands!"); 1592 assert(isRegShiftedImm() && 1593 "addRegShiftedImmOperands() on non RegShiftedImm!"); 1594 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1595 // Shift of #32 is encoded as 0 where permitted 1596 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1597 Inst.addOperand(MCOperand::CreateImm( 1598 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1599 } 1600 1601 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1602 assert(N == 1 && "Invalid number of operands!"); 1603 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1604 ShifterImm.Imm)); 1605 } 1606 1607 void addRegListOperands(MCInst &Inst, unsigned N) const { 1608 assert(N == 1 && "Invalid number of operands!"); 1609 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1610 for (SmallVectorImpl<unsigned>::const_iterator 1611 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1612 Inst.addOperand(MCOperand::CreateReg(*I)); 1613 } 1614 1615 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1616 addRegListOperands(Inst, N); 1617 } 1618 1619 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1620 addRegListOperands(Inst, N); 1621 } 1622 1623 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1624 assert(N == 1 && "Invalid number of operands!"); 1625 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1626 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1627 } 1628 1629 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1630 assert(N == 1 && "Invalid number of operands!"); 1631 // Munge the lsb/width into a bitfield mask. 1632 unsigned lsb = Bitfield.LSB; 1633 unsigned width = Bitfield.Width; 1634 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1635 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1636 (32 - (lsb + width))); 1637 Inst.addOperand(MCOperand::CreateImm(Mask)); 1638 } 1639 1640 void addImmOperands(MCInst &Inst, unsigned N) const { 1641 assert(N == 1 && "Invalid number of operands!"); 1642 addExpr(Inst, getImm()); 1643 } 1644 1645 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1646 assert(N == 1 && "Invalid number of operands!"); 1647 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1648 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1649 } 1650 1651 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1652 assert(N == 1 && "Invalid number of operands!"); 1653 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1654 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1655 } 1656 1657 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1658 assert(N == 1 && "Invalid number of operands!"); 1659 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1660 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1661 Inst.addOperand(MCOperand::CreateImm(Val)); 1662 } 1663 1664 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1665 assert(N == 1 && "Invalid number of operands!"); 1666 // FIXME: We really want to scale the value here, but the LDRD/STRD 1667 // instruction don't encode operands that way yet. 1668 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1669 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1670 } 1671 1672 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1673 assert(N == 1 && "Invalid number of operands!"); 1674 // The immediate is scaled by four in the encoding and is stored 1675 // in the MCInst as such. Lop off the low two bits here. 1676 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1677 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1678 } 1679 1680 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1681 assert(N == 1 && "Invalid number of operands!"); 1682 // The immediate is scaled by four in the encoding and is stored 1683 // in the MCInst as such. Lop off the low two bits here. 1684 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1685 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1686 } 1687 1688 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1689 assert(N == 1 && "Invalid number of operands!"); 1690 // The immediate is scaled by four in the encoding and is stored 1691 // in the MCInst as such. Lop off the low two bits here. 1692 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1693 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1694 } 1695 1696 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1697 assert(N == 1 && "Invalid number of operands!"); 1698 // The constant encodes as the immediate-1, and we store in the instruction 1699 // the bits as encoded, so subtract off one here. 1700 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1701 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1702 } 1703 1704 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1705 assert(N == 1 && "Invalid number of operands!"); 1706 // The constant encodes as the immediate-1, and we store in the instruction 1707 // the bits as encoded, so subtract off one here. 1708 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1709 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1710 } 1711 1712 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1713 assert(N == 1 && "Invalid number of operands!"); 1714 // The constant encodes as the immediate, except for 32, which encodes as 1715 // zero. 1716 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1717 unsigned Imm = CE->getValue(); 1718 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1719 } 1720 1721 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1722 assert(N == 1 && "Invalid number of operands!"); 1723 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1724 // the instruction as well. 1725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1726 int Val = CE->getValue(); 1727 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1728 } 1729 1730 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1731 assert(N == 1 && "Invalid number of operands!"); 1732 // The operand is actually a t2_so_imm, but we have its bitwise 1733 // negation in the assembly source, so twiddle it here. 1734 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1735 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1736 } 1737 1738 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1739 assert(N == 1 && "Invalid number of operands!"); 1740 // The operand is actually a t2_so_imm, but we have its 1741 // negation in the assembly source, so twiddle it here. 1742 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1743 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1744 } 1745 1746 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1747 assert(N == 1 && "Invalid number of operands!"); 1748 // The operand is actually an imm0_4095, but we have its 1749 // negation in the assembly source, so twiddle it here. 1750 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1751 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1752 } 1753 1754 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { 1755 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { 1756 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2)); 1757 return; 1758 } 1759 1760 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1761 assert(SR && "Unknown value type!"); 1762 Inst.addOperand(MCOperand::CreateExpr(SR)); 1763 } 1764 1765 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { 1766 assert(N == 1 && "Invalid number of operands!"); 1767 if (isImm()) { 1768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1769 if (CE) { 1770 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1771 return; 1772 } 1773 1774 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1775 assert(SR && "Unknown value type!"); 1776 Inst.addOperand(MCOperand::CreateExpr(SR)); 1777 return; 1778 } 1779 1780 assert(isMem() && "Unknown value type!"); 1781 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"); 1782 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue())); 1783 } 1784 1785 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1786 assert(N == 1 && "Invalid number of operands!"); 1787 // The operand is actually a so_imm, but we have its bitwise 1788 // negation in the assembly source, so twiddle it here. 1789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1790 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1791 } 1792 1793 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1794 assert(N == 1 && "Invalid number of operands!"); 1795 // The operand is actually a so_imm, but we have its 1796 // negation in the assembly source, so twiddle it here. 1797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1798 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1799 } 1800 1801 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1802 assert(N == 1 && "Invalid number of operands!"); 1803 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1804 } 1805 1806 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 1807 assert(N == 1 && "Invalid number of operands!"); 1808 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); 1809 } 1810 1811 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1812 assert(N == 1 && "Invalid number of operands!"); 1813 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1814 } 1815 1816 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1817 assert(N == 1 && "Invalid number of operands!"); 1818 int32_t Imm = Memory.OffsetImm->getValue(); 1819 Inst.addOperand(MCOperand::CreateImm(Imm)); 1820 } 1821 1822 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1823 assert(N == 1 && "Invalid number of operands!"); 1824 assert(isImm() && "Not an immediate!"); 1825 1826 // If we have an immediate that's not a constant, treat it as a label 1827 // reference needing a fixup. 1828 if (!isa<MCConstantExpr>(getImm())) { 1829 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1830 return; 1831 } 1832 1833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1834 int Val = CE->getValue(); 1835 Inst.addOperand(MCOperand::CreateImm(Val)); 1836 } 1837 1838 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1839 assert(N == 2 && "Invalid number of operands!"); 1840 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1841 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1842 } 1843 1844 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1845 assert(N == 3 && "Invalid number of operands!"); 1846 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1847 if (!Memory.OffsetRegNum) { 1848 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1849 // Special case for #-0 1850 if (Val == INT32_MIN) Val = 0; 1851 if (Val < 0) Val = -Val; 1852 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1853 } else { 1854 // For register offset, we encode the shift type and negation flag 1855 // here. 1856 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1857 Memory.ShiftImm, Memory.ShiftType); 1858 } 1859 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1860 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1861 Inst.addOperand(MCOperand::CreateImm(Val)); 1862 } 1863 1864 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1865 assert(N == 2 && "Invalid number of operands!"); 1866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1867 assert(CE && "non-constant AM2OffsetImm operand!"); 1868 int32_t Val = CE->getValue(); 1869 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1870 // Special case for #-0 1871 if (Val == INT32_MIN) Val = 0; 1872 if (Val < 0) Val = -Val; 1873 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1874 Inst.addOperand(MCOperand::CreateReg(0)); 1875 Inst.addOperand(MCOperand::CreateImm(Val)); 1876 } 1877 1878 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1879 assert(N == 3 && "Invalid number of operands!"); 1880 // If we have an immediate that's not a constant, treat it as a label 1881 // reference needing a fixup. If it is a constant, it's something else 1882 // and we reject it. 1883 if (isImm()) { 1884 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1885 Inst.addOperand(MCOperand::CreateReg(0)); 1886 Inst.addOperand(MCOperand::CreateImm(0)); 1887 return; 1888 } 1889 1890 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1891 if (!Memory.OffsetRegNum) { 1892 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1893 // Special case for #-0 1894 if (Val == INT32_MIN) Val = 0; 1895 if (Val < 0) Val = -Val; 1896 Val = ARM_AM::getAM3Opc(AddSub, Val); 1897 } else { 1898 // For register offset, we encode the shift type and negation flag 1899 // here. 1900 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1901 } 1902 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1903 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1904 Inst.addOperand(MCOperand::CreateImm(Val)); 1905 } 1906 1907 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1908 assert(N == 2 && "Invalid number of operands!"); 1909 if (Kind == k_PostIndexRegister) { 1910 int32_t Val = 1911 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1912 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1913 Inst.addOperand(MCOperand::CreateImm(Val)); 1914 return; 1915 } 1916 1917 // Constant offset. 1918 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1919 int32_t Val = CE->getValue(); 1920 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1921 // Special case for #-0 1922 if (Val == INT32_MIN) Val = 0; 1923 if (Val < 0) Val = -Val; 1924 Val = ARM_AM::getAM3Opc(AddSub, Val); 1925 Inst.addOperand(MCOperand::CreateReg(0)); 1926 Inst.addOperand(MCOperand::CreateImm(Val)); 1927 } 1928 1929 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1930 assert(N == 2 && "Invalid number of operands!"); 1931 // If we have an immediate that's not a constant, treat it as a label 1932 // reference needing a fixup. If it is a constant, it's something else 1933 // and we reject it. 1934 if (isImm()) { 1935 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1936 Inst.addOperand(MCOperand::CreateImm(0)); 1937 return; 1938 } 1939 1940 // The lower two bits are always zero and as such are not encoded. 1941 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1942 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1943 // Special case for #-0 1944 if (Val == INT32_MIN) Val = 0; 1945 if (Val < 0) Val = -Val; 1946 Val = ARM_AM::getAM5Opc(AddSub, Val); 1947 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1948 Inst.addOperand(MCOperand::CreateImm(Val)); 1949 } 1950 1951 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1952 assert(N == 2 && "Invalid number of operands!"); 1953 // If we have an immediate that's not a constant, treat it as a label 1954 // reference needing a fixup. If it is a constant, it's something else 1955 // and we reject it. 1956 if (isImm()) { 1957 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1958 Inst.addOperand(MCOperand::CreateImm(0)); 1959 return; 1960 } 1961 1962 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1963 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1964 Inst.addOperand(MCOperand::CreateImm(Val)); 1965 } 1966 1967 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1968 assert(N == 2 && "Invalid number of operands!"); 1969 // The lower two bits are always zero and as such are not encoded. 1970 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1971 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1972 Inst.addOperand(MCOperand::CreateImm(Val)); 1973 } 1974 1975 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1976 assert(N == 2 && "Invalid number of operands!"); 1977 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1978 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1979 Inst.addOperand(MCOperand::CreateImm(Val)); 1980 } 1981 1982 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1983 addMemImm8OffsetOperands(Inst, N); 1984 } 1985 1986 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1987 addMemImm8OffsetOperands(Inst, N); 1988 } 1989 1990 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1991 assert(N == 2 && "Invalid number of operands!"); 1992 // If this is an immediate, it's a label reference. 1993 if (isImm()) { 1994 addExpr(Inst, getImm()); 1995 Inst.addOperand(MCOperand::CreateImm(0)); 1996 return; 1997 } 1998 1999 // Otherwise, it's a normal memory reg+offset. 2000 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2001 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2002 Inst.addOperand(MCOperand::CreateImm(Val)); 2003 } 2004 2005 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2006 assert(N == 2 && "Invalid number of operands!"); 2007 // If this is an immediate, it's a label reference. 2008 if (isImm()) { 2009 addExpr(Inst, getImm()); 2010 Inst.addOperand(MCOperand::CreateImm(0)); 2011 return; 2012 } 2013 2014 // Otherwise, it's a normal memory reg+offset. 2015 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2016 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2017 Inst.addOperand(MCOperand::CreateImm(Val)); 2018 } 2019 2020 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 2021 assert(N == 2 && "Invalid number of operands!"); 2022 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2023 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2024 } 2025 2026 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 2027 assert(N == 2 && "Invalid number of operands!"); 2028 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2029 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2030 } 2031 2032 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2033 assert(N == 3 && "Invalid number of operands!"); 2034 unsigned Val = 2035 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2036 Memory.ShiftImm, Memory.ShiftType); 2037 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2038 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2039 Inst.addOperand(MCOperand::CreateImm(Val)); 2040 } 2041 2042 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2043 assert(N == 3 && "Invalid number of operands!"); 2044 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2045 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2046 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 2047 } 2048 2049 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 2050 assert(N == 2 && "Invalid number of operands!"); 2051 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2052 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2053 } 2054 2055 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 2056 assert(N == 2 && "Invalid number of operands!"); 2057 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2058 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2059 Inst.addOperand(MCOperand::CreateImm(Val)); 2060 } 2061 2062 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 2063 assert(N == 2 && "Invalid number of operands!"); 2064 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 2065 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2066 Inst.addOperand(MCOperand::CreateImm(Val)); 2067 } 2068 2069 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 2070 assert(N == 2 && "Invalid number of operands!"); 2071 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 2072 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2073 Inst.addOperand(MCOperand::CreateImm(Val)); 2074 } 2075 2076 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2077 assert(N == 2 && "Invalid number of operands!"); 2078 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2079 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2080 Inst.addOperand(MCOperand::CreateImm(Val)); 2081 } 2082 2083 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2084 assert(N == 1 && "Invalid number of operands!"); 2085 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2086 assert(CE && "non-constant post-idx-imm8 operand!"); 2087 int Imm = CE->getValue(); 2088 bool isAdd = Imm >= 0; 2089 if (Imm == INT32_MIN) Imm = 0; 2090 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2091 Inst.addOperand(MCOperand::CreateImm(Imm)); 2092 } 2093 2094 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2095 assert(N == 1 && "Invalid number of operands!"); 2096 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2097 assert(CE && "non-constant post-idx-imm8s4 operand!"); 2098 int Imm = CE->getValue(); 2099 bool isAdd = Imm >= 0; 2100 if (Imm == INT32_MIN) Imm = 0; 2101 // Immediate is scaled by 4. 2102 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2103 Inst.addOperand(MCOperand::CreateImm(Imm)); 2104 } 2105 2106 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2107 assert(N == 2 && "Invalid number of operands!"); 2108 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2109 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 2110 } 2111 2112 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2113 assert(N == 2 && "Invalid number of operands!"); 2114 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2115 // The sign, shift type, and shift amount are encoded in a single operand 2116 // using the AM2 encoding helpers. 2117 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2118 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2119 PostIdxReg.ShiftTy); 2120 Inst.addOperand(MCOperand::CreateImm(Imm)); 2121 } 2122 2123 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2124 assert(N == 1 && "Invalid number of operands!"); 2125 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 2126 } 2127 2128 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2129 assert(N == 1 && "Invalid number of operands!"); 2130 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 2131 } 2132 2133 void addVecListOperands(MCInst &Inst, unsigned N) const { 2134 assert(N == 1 && "Invalid number of operands!"); 2135 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2136 } 2137 2138 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2139 assert(N == 2 && "Invalid number of operands!"); 2140 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2141 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 2142 } 2143 2144 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2145 assert(N == 1 && "Invalid number of operands!"); 2146 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2147 } 2148 2149 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2150 assert(N == 1 && "Invalid number of operands!"); 2151 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2152 } 2153 2154 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2155 assert(N == 1 && "Invalid number of operands!"); 2156 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2157 } 2158 2159 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2160 assert(N == 1 && "Invalid number of operands!"); 2161 // The immediate encodes the type of constant as well as the value. 2162 // Mask in that this is an i8 splat. 2163 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2164 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 2165 } 2166 2167 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2168 assert(N == 1 && "Invalid number of operands!"); 2169 // The immediate encodes the type of constant as well as the value. 2170 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2171 unsigned Value = CE->getValue(); 2172 if (Value >= 256) 2173 Value = (Value >> 8) | 0xa00; 2174 else 2175 Value |= 0x800; 2176 Inst.addOperand(MCOperand::CreateImm(Value)); 2177 } 2178 2179 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2180 assert(N == 1 && "Invalid number of operands!"); 2181 // The immediate encodes the type of constant as well as the value. 2182 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2183 unsigned Value = CE->getValue(); 2184 if (Value >= 256 && Value <= 0xff00) 2185 Value = (Value >> 8) | 0x200; 2186 else if (Value > 0xffff && Value <= 0xff0000) 2187 Value = (Value >> 16) | 0x400; 2188 else if (Value > 0xffffff) 2189 Value = (Value >> 24) | 0x600; 2190 Inst.addOperand(MCOperand::CreateImm(Value)); 2191 } 2192 2193 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2194 assert(N == 1 && "Invalid number of operands!"); 2195 // The immediate encodes the type of constant as well as the value. 2196 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2197 unsigned Value = CE->getValue(); 2198 if (Value >= 256 && Value <= 0xffff) 2199 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2200 else if (Value > 0xffff && Value <= 0xffffff) 2201 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2202 else if (Value > 0xffffff) 2203 Value = (Value >> 24) | 0x600; 2204 Inst.addOperand(MCOperand::CreateImm(Value)); 2205 } 2206 2207 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2208 assert(N == 1 && "Invalid number of operands!"); 2209 // The immediate encodes the type of constant as well as the value. 2210 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2211 unsigned Value = ~CE->getValue(); 2212 if (Value >= 256 && Value <= 0xffff) 2213 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2214 else if (Value > 0xffff && Value <= 0xffffff) 2215 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2216 else if (Value > 0xffffff) 2217 Value = (Value >> 24) | 0x600; 2218 Inst.addOperand(MCOperand::CreateImm(Value)); 2219 } 2220 2221 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2222 assert(N == 1 && "Invalid number of operands!"); 2223 // The immediate encodes the type of constant as well as the value. 2224 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2225 uint64_t Value = CE->getValue(); 2226 unsigned Imm = 0; 2227 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2228 Imm |= (Value & 1) << i; 2229 } 2230 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2231 } 2232 2233 virtual void print(raw_ostream &OS) const; 2234 2235 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2236 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2237 Op->ITMask.Mask = Mask; 2238 Op->StartLoc = S; 2239 Op->EndLoc = S; 2240 return Op; 2241 } 2242 2243 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2244 ARMOperand *Op = new ARMOperand(k_CondCode); 2245 Op->CC.Val = CC; 2246 Op->StartLoc = S; 2247 Op->EndLoc = S; 2248 return Op; 2249 } 2250 2251 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2252 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2253 Op->Cop.Val = CopVal; 2254 Op->StartLoc = S; 2255 Op->EndLoc = S; 2256 return Op; 2257 } 2258 2259 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2260 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2261 Op->Cop.Val = CopVal; 2262 Op->StartLoc = S; 2263 Op->EndLoc = S; 2264 return Op; 2265 } 2266 2267 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2268 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2269 Op->Cop.Val = Val; 2270 Op->StartLoc = S; 2271 Op->EndLoc = E; 2272 return Op; 2273 } 2274 2275 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2276 ARMOperand *Op = new ARMOperand(k_CCOut); 2277 Op->Reg.RegNum = RegNum; 2278 Op->StartLoc = S; 2279 Op->EndLoc = S; 2280 return Op; 2281 } 2282 2283 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2284 ARMOperand *Op = new ARMOperand(k_Token); 2285 Op->Tok.Data = Str.data(); 2286 Op->Tok.Length = Str.size(); 2287 Op->StartLoc = S; 2288 Op->EndLoc = S; 2289 return Op; 2290 } 2291 2292 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2293 ARMOperand *Op = new ARMOperand(k_Register); 2294 Op->Reg.RegNum = RegNum; 2295 Op->StartLoc = S; 2296 Op->EndLoc = E; 2297 return Op; 2298 } 2299 2300 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2301 unsigned SrcReg, 2302 unsigned ShiftReg, 2303 unsigned ShiftImm, 2304 SMLoc S, SMLoc E) { 2305 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2306 Op->RegShiftedReg.ShiftTy = ShTy; 2307 Op->RegShiftedReg.SrcReg = SrcReg; 2308 Op->RegShiftedReg.ShiftReg = ShiftReg; 2309 Op->RegShiftedReg.ShiftImm = ShiftImm; 2310 Op->StartLoc = S; 2311 Op->EndLoc = E; 2312 return Op; 2313 } 2314 2315 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2316 unsigned SrcReg, 2317 unsigned ShiftImm, 2318 SMLoc S, SMLoc E) { 2319 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2320 Op->RegShiftedImm.ShiftTy = ShTy; 2321 Op->RegShiftedImm.SrcReg = SrcReg; 2322 Op->RegShiftedImm.ShiftImm = ShiftImm; 2323 Op->StartLoc = S; 2324 Op->EndLoc = E; 2325 return Op; 2326 } 2327 2328 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2329 SMLoc S, SMLoc E) { 2330 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2331 Op->ShifterImm.isASR = isASR; 2332 Op->ShifterImm.Imm = Imm; 2333 Op->StartLoc = S; 2334 Op->EndLoc = E; 2335 return Op; 2336 } 2337 2338 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2339 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2340 Op->RotImm.Imm = Imm; 2341 Op->StartLoc = S; 2342 Op->EndLoc = E; 2343 return Op; 2344 } 2345 2346 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2347 SMLoc S, SMLoc E) { 2348 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2349 Op->Bitfield.LSB = LSB; 2350 Op->Bitfield.Width = Width; 2351 Op->StartLoc = S; 2352 Op->EndLoc = E; 2353 return Op; 2354 } 2355 2356 static ARMOperand * 2357 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs, 2358 SMLoc StartLoc, SMLoc EndLoc) { 2359 assert (Regs.size() > 0 && "RegList contains no registers?"); 2360 KindTy Kind = k_RegisterList; 2361 2362 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2363 Kind = k_DPRRegisterList; 2364 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2365 contains(Regs.front().second)) 2366 Kind = k_SPRRegisterList; 2367 2368 // Sort based on the register encoding values. 2369 array_pod_sort(Regs.begin(), Regs.end()); 2370 2371 ARMOperand *Op = new ARMOperand(Kind); 2372 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator 2373 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2374 Op->Registers.push_back(I->second); 2375 Op->StartLoc = StartLoc; 2376 Op->EndLoc = EndLoc; 2377 return Op; 2378 } 2379 2380 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2381 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2382 ARMOperand *Op = new ARMOperand(k_VectorList); 2383 Op->VectorList.RegNum = RegNum; 2384 Op->VectorList.Count = Count; 2385 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2386 Op->StartLoc = S; 2387 Op->EndLoc = E; 2388 return Op; 2389 } 2390 2391 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2392 bool isDoubleSpaced, 2393 SMLoc S, SMLoc E) { 2394 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2395 Op->VectorList.RegNum = RegNum; 2396 Op->VectorList.Count = Count; 2397 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2398 Op->StartLoc = S; 2399 Op->EndLoc = E; 2400 return Op; 2401 } 2402 2403 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2404 unsigned Index, 2405 bool isDoubleSpaced, 2406 SMLoc S, SMLoc E) { 2407 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2408 Op->VectorList.RegNum = RegNum; 2409 Op->VectorList.Count = Count; 2410 Op->VectorList.LaneIndex = Index; 2411 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2412 Op->StartLoc = S; 2413 Op->EndLoc = E; 2414 return Op; 2415 } 2416 2417 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2418 MCContext &Ctx) { 2419 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2420 Op->VectorIndex.Val = Idx; 2421 Op->StartLoc = S; 2422 Op->EndLoc = E; 2423 return Op; 2424 } 2425 2426 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2427 ARMOperand *Op = new ARMOperand(k_Immediate); 2428 Op->Imm.Val = Val; 2429 Op->StartLoc = S; 2430 Op->EndLoc = E; 2431 return Op; 2432 } 2433 2434 static ARMOperand *CreateMem(unsigned BaseRegNum, 2435 const MCConstantExpr *OffsetImm, 2436 unsigned OffsetRegNum, 2437 ARM_AM::ShiftOpc ShiftType, 2438 unsigned ShiftImm, 2439 unsigned Alignment, 2440 bool isNegative, 2441 SMLoc S, SMLoc E) { 2442 ARMOperand *Op = new ARMOperand(k_Memory); 2443 Op->Memory.BaseRegNum = BaseRegNum; 2444 Op->Memory.OffsetImm = OffsetImm; 2445 Op->Memory.OffsetRegNum = OffsetRegNum; 2446 Op->Memory.ShiftType = ShiftType; 2447 Op->Memory.ShiftImm = ShiftImm; 2448 Op->Memory.Alignment = Alignment; 2449 Op->Memory.isNegative = isNegative; 2450 Op->StartLoc = S; 2451 Op->EndLoc = E; 2452 return Op; 2453 } 2454 2455 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2456 ARM_AM::ShiftOpc ShiftTy, 2457 unsigned ShiftImm, 2458 SMLoc S, SMLoc E) { 2459 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2460 Op->PostIdxReg.RegNum = RegNum; 2461 Op->PostIdxReg.isAdd = isAdd; 2462 Op->PostIdxReg.ShiftTy = ShiftTy; 2463 Op->PostIdxReg.ShiftImm = ShiftImm; 2464 Op->StartLoc = S; 2465 Op->EndLoc = E; 2466 return Op; 2467 } 2468 2469 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2470 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2471 Op->MBOpt.Val = Opt; 2472 Op->StartLoc = S; 2473 Op->EndLoc = S; 2474 return Op; 2475 } 2476 2477 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, 2478 SMLoc S) { 2479 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt); 2480 Op->ISBOpt.Val = Opt; 2481 Op->StartLoc = S; 2482 Op->EndLoc = S; 2483 return Op; 2484 } 2485 2486 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2487 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2488 Op->IFlags.Val = IFlags; 2489 Op->StartLoc = S; 2490 Op->EndLoc = S; 2491 return Op; 2492 } 2493 2494 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2495 ARMOperand *Op = new ARMOperand(k_MSRMask); 2496 Op->MMask.Val = MMask; 2497 Op->StartLoc = S; 2498 Op->EndLoc = S; 2499 return Op; 2500 } 2501 }; 2502 2503 } // end anonymous namespace. 2504 2505 void ARMOperand::print(raw_ostream &OS) const { 2506 switch (Kind) { 2507 case k_CondCode: 2508 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2509 break; 2510 case k_CCOut: 2511 OS << "<ccout " << getReg() << ">"; 2512 break; 2513 case k_ITCondMask: { 2514 static const char *const MaskStr[] = { 2515 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2516 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2517 }; 2518 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2519 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2520 break; 2521 } 2522 case k_CoprocNum: 2523 OS << "<coprocessor number: " << getCoproc() << ">"; 2524 break; 2525 case k_CoprocReg: 2526 OS << "<coprocessor register: " << getCoproc() << ">"; 2527 break; 2528 case k_CoprocOption: 2529 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2530 break; 2531 case k_MSRMask: 2532 OS << "<mask: " << getMSRMask() << ">"; 2533 break; 2534 case k_Immediate: 2535 getImm()->print(OS); 2536 break; 2537 case k_MemBarrierOpt: 2538 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; 2539 break; 2540 case k_InstSyncBarrierOpt: 2541 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2542 break; 2543 case k_Memory: 2544 OS << "<memory " 2545 << " base:" << Memory.BaseRegNum; 2546 OS << ">"; 2547 break; 2548 case k_PostIndexRegister: 2549 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2550 << PostIdxReg.RegNum; 2551 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2552 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2553 << PostIdxReg.ShiftImm; 2554 OS << ">"; 2555 break; 2556 case k_ProcIFlags: { 2557 OS << "<ARM_PROC::"; 2558 unsigned IFlags = getProcIFlags(); 2559 for (int i=2; i >= 0; --i) 2560 if (IFlags & (1 << i)) 2561 OS << ARM_PROC::IFlagsToString(1 << i); 2562 OS << ">"; 2563 break; 2564 } 2565 case k_Register: 2566 OS << "<register " << getReg() << ">"; 2567 break; 2568 case k_ShifterImmediate: 2569 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2570 << " #" << ShifterImm.Imm << ">"; 2571 break; 2572 case k_ShiftedRegister: 2573 OS << "<so_reg_reg " 2574 << RegShiftedReg.SrcReg << " " 2575 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2576 << " " << RegShiftedReg.ShiftReg << ">"; 2577 break; 2578 case k_ShiftedImmediate: 2579 OS << "<so_reg_imm " 2580 << RegShiftedImm.SrcReg << " " 2581 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2582 << " #" << RegShiftedImm.ShiftImm << ">"; 2583 break; 2584 case k_RotateImmediate: 2585 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2586 break; 2587 case k_BitfieldDescriptor: 2588 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2589 << ", width: " << Bitfield.Width << ">"; 2590 break; 2591 case k_RegisterList: 2592 case k_DPRRegisterList: 2593 case k_SPRRegisterList: { 2594 OS << "<register_list "; 2595 2596 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2597 for (SmallVectorImpl<unsigned>::const_iterator 2598 I = RegList.begin(), E = RegList.end(); I != E; ) { 2599 OS << *I; 2600 if (++I < E) OS << ", "; 2601 } 2602 2603 OS << ">"; 2604 break; 2605 } 2606 case k_VectorList: 2607 OS << "<vector_list " << VectorList.Count << " * " 2608 << VectorList.RegNum << ">"; 2609 break; 2610 case k_VectorListAllLanes: 2611 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2612 << VectorList.RegNum << ">"; 2613 break; 2614 case k_VectorListIndexed: 2615 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2616 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2617 break; 2618 case k_Token: 2619 OS << "'" << getToken() << "'"; 2620 break; 2621 case k_VectorIndex: 2622 OS << "<vectorindex " << getVectorIndex() << ">"; 2623 break; 2624 } 2625 } 2626 2627 /// @name Auto-generated Match Functions 2628 /// { 2629 2630 static unsigned MatchRegisterName(StringRef Name); 2631 2632 /// } 2633 2634 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2635 SMLoc &StartLoc, SMLoc &EndLoc) { 2636 StartLoc = Parser.getTok().getLoc(); 2637 EndLoc = Parser.getTok().getEndLoc(); 2638 RegNo = tryParseRegister(); 2639 2640 return (RegNo == (unsigned)-1); 2641 } 2642 2643 /// Try to parse a register name. The token must be an Identifier when called, 2644 /// and if it is a register name the token is eaten and the register number is 2645 /// returned. Otherwise return -1. 2646 /// 2647 int ARMAsmParser::tryParseRegister() { 2648 const AsmToken &Tok = Parser.getTok(); 2649 if (Tok.isNot(AsmToken::Identifier)) return -1; 2650 2651 std::string lowerCase = Tok.getString().lower(); 2652 unsigned RegNum = MatchRegisterName(lowerCase); 2653 if (!RegNum) { 2654 RegNum = StringSwitch<unsigned>(lowerCase) 2655 .Case("r13", ARM::SP) 2656 .Case("r14", ARM::LR) 2657 .Case("r15", ARM::PC) 2658 .Case("ip", ARM::R12) 2659 // Additional register name aliases for 'gas' compatibility. 2660 .Case("a1", ARM::R0) 2661 .Case("a2", ARM::R1) 2662 .Case("a3", ARM::R2) 2663 .Case("a4", ARM::R3) 2664 .Case("v1", ARM::R4) 2665 .Case("v2", ARM::R5) 2666 .Case("v3", ARM::R6) 2667 .Case("v4", ARM::R7) 2668 .Case("v5", ARM::R8) 2669 .Case("v6", ARM::R9) 2670 .Case("v7", ARM::R10) 2671 .Case("v8", ARM::R11) 2672 .Case("sb", ARM::R9) 2673 .Case("sl", ARM::R10) 2674 .Case("fp", ARM::R11) 2675 .Default(0); 2676 } 2677 if (!RegNum) { 2678 // Check for aliases registered via .req. Canonicalize to lower case. 2679 // That's more consistent since register names are case insensitive, and 2680 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2681 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2682 // If no match, return failure. 2683 if (Entry == RegisterReqs.end()) 2684 return -1; 2685 Parser.Lex(); // Eat identifier token. 2686 return Entry->getValue(); 2687 } 2688 2689 Parser.Lex(); // Eat identifier token. 2690 2691 return RegNum; 2692 } 2693 2694 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2695 // If a recoverable error occurs, return 1. If an irrecoverable error 2696 // occurs, return -1. An irrecoverable error is one where tokens have been 2697 // consumed in the process of trying to parse the shifter (i.e., when it is 2698 // indeed a shifter operand, but malformed). 2699 int ARMAsmParser::tryParseShiftRegister( 2700 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2701 SMLoc S = Parser.getTok().getLoc(); 2702 const AsmToken &Tok = Parser.getTok(); 2703 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2704 2705 std::string lowerCase = Tok.getString().lower(); 2706 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2707 .Case("asl", ARM_AM::lsl) 2708 .Case("lsl", ARM_AM::lsl) 2709 .Case("lsr", ARM_AM::lsr) 2710 .Case("asr", ARM_AM::asr) 2711 .Case("ror", ARM_AM::ror) 2712 .Case("rrx", ARM_AM::rrx) 2713 .Default(ARM_AM::no_shift); 2714 2715 if (ShiftTy == ARM_AM::no_shift) 2716 return 1; 2717 2718 Parser.Lex(); // Eat the operator. 2719 2720 // The source register for the shift has already been added to the 2721 // operand list, so we need to pop it off and combine it into the shifted 2722 // register operand instead. 2723 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2724 if (!PrevOp->isReg()) 2725 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2726 int SrcReg = PrevOp->getReg(); 2727 2728 SMLoc EndLoc; 2729 int64_t Imm = 0; 2730 int ShiftReg = 0; 2731 if (ShiftTy == ARM_AM::rrx) { 2732 // RRX Doesn't have an explicit shift amount. The encoder expects 2733 // the shift register to be the same as the source register. Seems odd, 2734 // but OK. 2735 ShiftReg = SrcReg; 2736 } else { 2737 // Figure out if this is shifted by a constant or a register (for non-RRX). 2738 if (Parser.getTok().is(AsmToken::Hash) || 2739 Parser.getTok().is(AsmToken::Dollar)) { 2740 Parser.Lex(); // Eat hash. 2741 SMLoc ImmLoc = Parser.getTok().getLoc(); 2742 const MCExpr *ShiftExpr = 0; 2743 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 2744 Error(ImmLoc, "invalid immediate shift value"); 2745 return -1; 2746 } 2747 // The expression must be evaluatable as an immediate. 2748 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2749 if (!CE) { 2750 Error(ImmLoc, "invalid immediate shift value"); 2751 return -1; 2752 } 2753 // Range check the immediate. 2754 // lsl, ror: 0 <= imm <= 31 2755 // lsr, asr: 0 <= imm <= 32 2756 Imm = CE->getValue(); 2757 if (Imm < 0 || 2758 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2759 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2760 Error(ImmLoc, "immediate shift value out of range"); 2761 return -1; 2762 } 2763 // shift by zero is a nop. Always send it through as lsl. 2764 // ('as' compatibility) 2765 if (Imm == 0) 2766 ShiftTy = ARM_AM::lsl; 2767 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2768 SMLoc L = Parser.getTok().getLoc(); 2769 EndLoc = Parser.getTok().getEndLoc(); 2770 ShiftReg = tryParseRegister(); 2771 if (ShiftReg == -1) { 2772 Error (L, "expected immediate or register in shift operand"); 2773 return -1; 2774 } 2775 } else { 2776 Error (Parser.getTok().getLoc(), 2777 "expected immediate or register in shift operand"); 2778 return -1; 2779 } 2780 } 2781 2782 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2783 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2784 ShiftReg, Imm, 2785 S, EndLoc)); 2786 else 2787 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2788 S, EndLoc)); 2789 2790 return 0; 2791 } 2792 2793 2794 /// Try to parse a register name. The token must be an Identifier when called. 2795 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 2796 /// if there is a "writeback". 'true' if it's not a register. 2797 /// 2798 /// TODO this is likely to change to allow different register types and or to 2799 /// parse for a specific register type. 2800 bool ARMAsmParser:: 2801 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2802 const AsmToken &RegTok = Parser.getTok(); 2803 int RegNo = tryParseRegister(); 2804 if (RegNo == -1) 2805 return true; 2806 2807 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 2808 RegTok.getEndLoc())); 2809 2810 const AsmToken &ExclaimTok = Parser.getTok(); 2811 if (ExclaimTok.is(AsmToken::Exclaim)) { 2812 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2813 ExclaimTok.getLoc())); 2814 Parser.Lex(); // Eat exclaim token 2815 return false; 2816 } 2817 2818 // Also check for an index operand. This is only legal for vector registers, 2819 // but that'll get caught OK in operand matching, so we don't need to 2820 // explicitly filter everything else out here. 2821 if (Parser.getTok().is(AsmToken::LBrac)) { 2822 SMLoc SIdx = Parser.getTok().getLoc(); 2823 Parser.Lex(); // Eat left bracket token. 2824 2825 const MCExpr *ImmVal; 2826 if (getParser().parseExpression(ImmVal)) 2827 return true; 2828 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2829 if (!MCE) 2830 return TokError("immediate value expected for vector index"); 2831 2832 if (Parser.getTok().isNot(AsmToken::RBrac)) 2833 return Error(Parser.getTok().getLoc(), "']' expected"); 2834 2835 SMLoc E = Parser.getTok().getEndLoc(); 2836 Parser.Lex(); // Eat right bracket token. 2837 2838 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2839 SIdx, E, 2840 getContext())); 2841 } 2842 2843 return false; 2844 } 2845 2846 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 2847 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2848 /// "c5", ... 2849 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2850 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2851 // but efficient. 2852 switch (Name.size()) { 2853 default: return -1; 2854 case 2: 2855 if (Name[0] != CoprocOp) 2856 return -1; 2857 switch (Name[1]) { 2858 default: return -1; 2859 case '0': return 0; 2860 case '1': return 1; 2861 case '2': return 2; 2862 case '3': return 3; 2863 case '4': return 4; 2864 case '5': return 5; 2865 case '6': return 6; 2866 case '7': return 7; 2867 case '8': return 8; 2868 case '9': return 9; 2869 } 2870 case 3: 2871 if (Name[0] != CoprocOp || Name[1] != '1') 2872 return -1; 2873 switch (Name[2]) { 2874 default: return -1; 2875 case '0': return 10; 2876 case '1': return 11; 2877 case '2': return 12; 2878 case '3': return 13; 2879 case '4': return 14; 2880 case '5': return 15; 2881 } 2882 } 2883 } 2884 2885 /// parseITCondCode - Try to parse a condition code for an IT instruction. 2886 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2887 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2888 SMLoc S = Parser.getTok().getLoc(); 2889 const AsmToken &Tok = Parser.getTok(); 2890 if (!Tok.is(AsmToken::Identifier)) 2891 return MatchOperand_NoMatch; 2892 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2893 .Case("eq", ARMCC::EQ) 2894 .Case("ne", ARMCC::NE) 2895 .Case("hs", ARMCC::HS) 2896 .Case("cs", ARMCC::HS) 2897 .Case("lo", ARMCC::LO) 2898 .Case("cc", ARMCC::LO) 2899 .Case("mi", ARMCC::MI) 2900 .Case("pl", ARMCC::PL) 2901 .Case("vs", ARMCC::VS) 2902 .Case("vc", ARMCC::VC) 2903 .Case("hi", ARMCC::HI) 2904 .Case("ls", ARMCC::LS) 2905 .Case("ge", ARMCC::GE) 2906 .Case("lt", ARMCC::LT) 2907 .Case("gt", ARMCC::GT) 2908 .Case("le", ARMCC::LE) 2909 .Case("al", ARMCC::AL) 2910 .Default(~0U); 2911 if (CC == ~0U) 2912 return MatchOperand_NoMatch; 2913 Parser.Lex(); // Eat the token. 2914 2915 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2916 2917 return MatchOperand_Success; 2918 } 2919 2920 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2921 /// token must be an Identifier when called, and if it is a coprocessor 2922 /// number, the token is eaten and the operand is added to the operand list. 2923 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2924 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2925 SMLoc S = Parser.getTok().getLoc(); 2926 const AsmToken &Tok = Parser.getTok(); 2927 if (Tok.isNot(AsmToken::Identifier)) 2928 return MatchOperand_NoMatch; 2929 2930 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2931 if (Num == -1) 2932 return MatchOperand_NoMatch; 2933 2934 Parser.Lex(); // Eat identifier token. 2935 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2936 return MatchOperand_Success; 2937 } 2938 2939 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2940 /// token must be an Identifier when called, and if it is a coprocessor 2941 /// number, the token is eaten and the operand is added to the operand list. 2942 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2943 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2944 SMLoc S = Parser.getTok().getLoc(); 2945 const AsmToken &Tok = Parser.getTok(); 2946 if (Tok.isNot(AsmToken::Identifier)) 2947 return MatchOperand_NoMatch; 2948 2949 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2950 if (Reg == -1) 2951 return MatchOperand_NoMatch; 2952 2953 Parser.Lex(); // Eat identifier token. 2954 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2955 return MatchOperand_Success; 2956 } 2957 2958 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2959 /// coproc_option : '{' imm0_255 '}' 2960 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2961 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2962 SMLoc S = Parser.getTok().getLoc(); 2963 2964 // If this isn't a '{', this isn't a coprocessor immediate operand. 2965 if (Parser.getTok().isNot(AsmToken::LCurly)) 2966 return MatchOperand_NoMatch; 2967 Parser.Lex(); // Eat the '{' 2968 2969 const MCExpr *Expr; 2970 SMLoc Loc = Parser.getTok().getLoc(); 2971 if (getParser().parseExpression(Expr)) { 2972 Error(Loc, "illegal expression"); 2973 return MatchOperand_ParseFail; 2974 } 2975 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2976 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2977 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2978 return MatchOperand_ParseFail; 2979 } 2980 int Val = CE->getValue(); 2981 2982 // Check for and consume the closing '}' 2983 if (Parser.getTok().isNot(AsmToken::RCurly)) 2984 return MatchOperand_ParseFail; 2985 SMLoc E = Parser.getTok().getEndLoc(); 2986 Parser.Lex(); // Eat the '}' 2987 2988 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2989 return MatchOperand_Success; 2990 } 2991 2992 // For register list parsing, we need to map from raw GPR register numbering 2993 // to the enumeration values. The enumeration values aren't sorted by 2994 // register number due to our using "sp", "lr" and "pc" as canonical names. 2995 static unsigned getNextRegister(unsigned Reg) { 2996 // If this is a GPR, we need to do it manually, otherwise we can rely 2997 // on the sort ordering of the enumeration since the other reg-classes 2998 // are sane. 2999 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3000 return Reg + 1; 3001 switch(Reg) { 3002 default: llvm_unreachable("Invalid GPR number!"); 3003 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 3004 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 3005 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 3006 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 3007 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 3008 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 3009 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 3010 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 3011 } 3012 } 3013 3014 // Return the low-subreg of a given Q register. 3015 static unsigned getDRegFromQReg(unsigned QReg) { 3016 switch (QReg) { 3017 default: llvm_unreachable("expected a Q register!"); 3018 case ARM::Q0: return ARM::D0; 3019 case ARM::Q1: return ARM::D2; 3020 case ARM::Q2: return ARM::D4; 3021 case ARM::Q3: return ARM::D6; 3022 case ARM::Q4: return ARM::D8; 3023 case ARM::Q5: return ARM::D10; 3024 case ARM::Q6: return ARM::D12; 3025 case ARM::Q7: return ARM::D14; 3026 case ARM::Q8: return ARM::D16; 3027 case ARM::Q9: return ARM::D18; 3028 case ARM::Q10: return ARM::D20; 3029 case ARM::Q11: return ARM::D22; 3030 case ARM::Q12: return ARM::D24; 3031 case ARM::Q13: return ARM::D26; 3032 case ARM::Q14: return ARM::D28; 3033 case ARM::Q15: return ARM::D30; 3034 } 3035 } 3036 3037 /// Parse a register list. 3038 bool ARMAsmParser:: 3039 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3040 assert(Parser.getTok().is(AsmToken::LCurly) && 3041 "Token is not a Left Curly Brace"); 3042 SMLoc S = Parser.getTok().getLoc(); 3043 Parser.Lex(); // Eat '{' token. 3044 SMLoc RegLoc = Parser.getTok().getLoc(); 3045 3046 // Check the first register in the list to see what register class 3047 // this is a list of. 3048 int Reg = tryParseRegister(); 3049 if (Reg == -1) 3050 return Error(RegLoc, "register expected"); 3051 3052 // The reglist instructions have at most 16 registers, so reserve 3053 // space for that many. 3054 int EReg = 0; 3055 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; 3056 3057 // Allow Q regs and just interpret them as the two D sub-registers. 3058 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3059 Reg = getDRegFromQReg(Reg); 3060 EReg = MRI->getEncodingValue(Reg); 3061 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3062 ++Reg; 3063 } 3064 const MCRegisterClass *RC; 3065 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3066 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 3067 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 3068 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 3069 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 3070 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 3071 else 3072 return Error(RegLoc, "invalid register in register list"); 3073 3074 // Store the register. 3075 EReg = MRI->getEncodingValue(Reg); 3076 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3077 3078 // This starts immediately after the first register token in the list, 3079 // so we can see either a comma or a minus (range separator) as a legal 3080 // next token. 3081 while (Parser.getTok().is(AsmToken::Comma) || 3082 Parser.getTok().is(AsmToken::Minus)) { 3083 if (Parser.getTok().is(AsmToken::Minus)) { 3084 Parser.Lex(); // Eat the minus. 3085 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3086 int EndReg = tryParseRegister(); 3087 if (EndReg == -1) 3088 return Error(AfterMinusLoc, "register expected"); 3089 // Allow Q regs and just interpret them as the two D sub-registers. 3090 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3091 EndReg = getDRegFromQReg(EndReg) + 1; 3092 // If the register is the same as the start reg, there's nothing 3093 // more to do. 3094 if (Reg == EndReg) 3095 continue; 3096 // The register must be in the same register class as the first. 3097 if (!RC->contains(EndReg)) 3098 return Error(AfterMinusLoc, "invalid register in register list"); 3099 // Ranges must go from low to high. 3100 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3101 return Error(AfterMinusLoc, "bad range in register list"); 3102 3103 // Add all the registers in the range to the register list. 3104 while (Reg != EndReg) { 3105 Reg = getNextRegister(Reg); 3106 EReg = MRI->getEncodingValue(Reg); 3107 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3108 } 3109 continue; 3110 } 3111 Parser.Lex(); // Eat the comma. 3112 RegLoc = Parser.getTok().getLoc(); 3113 int OldReg = Reg; 3114 const AsmToken RegTok = Parser.getTok(); 3115 Reg = tryParseRegister(); 3116 if (Reg == -1) 3117 return Error(RegLoc, "register expected"); 3118 // Allow Q regs and just interpret them as the two D sub-registers. 3119 bool isQReg = false; 3120 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3121 Reg = getDRegFromQReg(Reg); 3122 isQReg = true; 3123 } 3124 // The register must be in the same register class as the first. 3125 if (!RC->contains(Reg)) 3126 return Error(RegLoc, "invalid register in register list"); 3127 // List must be monotonically increasing. 3128 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3129 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3130 Warning(RegLoc, "register list not in ascending order"); 3131 else 3132 return Error(RegLoc, "register list not in ascending order"); 3133 } 3134 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3135 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3136 ") in register list"); 3137 continue; 3138 } 3139 // VFP register lists must also be contiguous. 3140 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3141 Reg != OldReg + 1) 3142 return Error(RegLoc, "non-contiguous register range"); 3143 EReg = MRI->getEncodingValue(Reg); 3144 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3145 if (isQReg) { 3146 EReg = MRI->getEncodingValue(++Reg); 3147 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3148 } 3149 } 3150 3151 if (Parser.getTok().isNot(AsmToken::RCurly)) 3152 return Error(Parser.getTok().getLoc(), "'}' expected"); 3153 SMLoc E = Parser.getTok().getEndLoc(); 3154 Parser.Lex(); // Eat '}' token. 3155 3156 // Push the register list operand. 3157 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3158 3159 // The ARM system instruction variants for LDM/STM have a '^' token here. 3160 if (Parser.getTok().is(AsmToken::Caret)) { 3161 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3162 Parser.Lex(); // Eat '^' token. 3163 } 3164 3165 return false; 3166 } 3167 3168 // Helper function to parse the lane index for vector lists. 3169 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3170 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3171 Index = 0; // Always return a defined index value. 3172 if (Parser.getTok().is(AsmToken::LBrac)) { 3173 Parser.Lex(); // Eat the '['. 3174 if (Parser.getTok().is(AsmToken::RBrac)) { 3175 // "Dn[]" is the 'all lanes' syntax. 3176 LaneKind = AllLanes; 3177 EndLoc = Parser.getTok().getEndLoc(); 3178 Parser.Lex(); // Eat the ']'. 3179 return MatchOperand_Success; 3180 } 3181 3182 // There's an optional '#' token here. Normally there wouldn't be, but 3183 // inline assemble puts one in, and it's friendly to accept that. 3184 if (Parser.getTok().is(AsmToken::Hash)) 3185 Parser.Lex(); // Eat '#' or '$'. 3186 3187 const MCExpr *LaneIndex; 3188 SMLoc Loc = Parser.getTok().getLoc(); 3189 if (getParser().parseExpression(LaneIndex)) { 3190 Error(Loc, "illegal expression"); 3191 return MatchOperand_ParseFail; 3192 } 3193 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3194 if (!CE) { 3195 Error(Loc, "lane index must be empty or an integer"); 3196 return MatchOperand_ParseFail; 3197 } 3198 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3199 Error(Parser.getTok().getLoc(), "']' expected"); 3200 return MatchOperand_ParseFail; 3201 } 3202 EndLoc = Parser.getTok().getEndLoc(); 3203 Parser.Lex(); // Eat the ']'. 3204 int64_t Val = CE->getValue(); 3205 3206 // FIXME: Make this range check context sensitive for .8, .16, .32. 3207 if (Val < 0 || Val > 7) { 3208 Error(Parser.getTok().getLoc(), "lane index out of range"); 3209 return MatchOperand_ParseFail; 3210 } 3211 Index = Val; 3212 LaneKind = IndexedLane; 3213 return MatchOperand_Success; 3214 } 3215 LaneKind = NoLanes; 3216 return MatchOperand_Success; 3217 } 3218 3219 // parse a vector register list 3220 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3221 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3222 VectorLaneTy LaneKind; 3223 unsigned LaneIndex; 3224 SMLoc S = Parser.getTok().getLoc(); 3225 // As an extension (to match gas), support a plain D register or Q register 3226 // (without encosing curly braces) as a single or double entry list, 3227 // respectively. 3228 if (Parser.getTok().is(AsmToken::Identifier)) { 3229 SMLoc E = Parser.getTok().getEndLoc(); 3230 int Reg = tryParseRegister(); 3231 if (Reg == -1) 3232 return MatchOperand_NoMatch; 3233 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3234 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3235 if (Res != MatchOperand_Success) 3236 return Res; 3237 switch (LaneKind) { 3238 case NoLanes: 3239 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3240 break; 3241 case AllLanes: 3242 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3243 S, E)); 3244 break; 3245 case IndexedLane: 3246 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3247 LaneIndex, 3248 false, S, E)); 3249 break; 3250 } 3251 return MatchOperand_Success; 3252 } 3253 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3254 Reg = getDRegFromQReg(Reg); 3255 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3256 if (Res != MatchOperand_Success) 3257 return Res; 3258 switch (LaneKind) { 3259 case NoLanes: 3260 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3261 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3262 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3263 break; 3264 case AllLanes: 3265 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3266 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3267 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3268 S, E)); 3269 break; 3270 case IndexedLane: 3271 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3272 LaneIndex, 3273 false, S, E)); 3274 break; 3275 } 3276 return MatchOperand_Success; 3277 } 3278 Error(S, "vector register expected"); 3279 return MatchOperand_ParseFail; 3280 } 3281 3282 if (Parser.getTok().isNot(AsmToken::LCurly)) 3283 return MatchOperand_NoMatch; 3284 3285 Parser.Lex(); // Eat '{' token. 3286 SMLoc RegLoc = Parser.getTok().getLoc(); 3287 3288 int Reg = tryParseRegister(); 3289 if (Reg == -1) { 3290 Error(RegLoc, "register expected"); 3291 return MatchOperand_ParseFail; 3292 } 3293 unsigned Count = 1; 3294 int Spacing = 0; 3295 unsigned FirstReg = Reg; 3296 // The list is of D registers, but we also allow Q regs and just interpret 3297 // them as the two D sub-registers. 3298 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3299 FirstReg = Reg = getDRegFromQReg(Reg); 3300 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3301 // it's ambiguous with four-register single spaced. 3302 ++Reg; 3303 ++Count; 3304 } 3305 3306 SMLoc E; 3307 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3308 return MatchOperand_ParseFail; 3309 3310 while (Parser.getTok().is(AsmToken::Comma) || 3311 Parser.getTok().is(AsmToken::Minus)) { 3312 if (Parser.getTok().is(AsmToken::Minus)) { 3313 if (!Spacing) 3314 Spacing = 1; // Register range implies a single spaced list. 3315 else if (Spacing == 2) { 3316 Error(Parser.getTok().getLoc(), 3317 "sequential registers in double spaced list"); 3318 return MatchOperand_ParseFail; 3319 } 3320 Parser.Lex(); // Eat the minus. 3321 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3322 int EndReg = tryParseRegister(); 3323 if (EndReg == -1) { 3324 Error(AfterMinusLoc, "register expected"); 3325 return MatchOperand_ParseFail; 3326 } 3327 // Allow Q regs and just interpret them as the two D sub-registers. 3328 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3329 EndReg = getDRegFromQReg(EndReg) + 1; 3330 // If the register is the same as the start reg, there's nothing 3331 // more to do. 3332 if (Reg == EndReg) 3333 continue; 3334 // The register must be in the same register class as the first. 3335 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3336 Error(AfterMinusLoc, "invalid register in register list"); 3337 return MatchOperand_ParseFail; 3338 } 3339 // Ranges must go from low to high. 3340 if (Reg > EndReg) { 3341 Error(AfterMinusLoc, "bad range in register list"); 3342 return MatchOperand_ParseFail; 3343 } 3344 // Parse the lane specifier if present. 3345 VectorLaneTy NextLaneKind; 3346 unsigned NextLaneIndex; 3347 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3348 MatchOperand_Success) 3349 return MatchOperand_ParseFail; 3350 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3351 Error(AfterMinusLoc, "mismatched lane index in register list"); 3352 return MatchOperand_ParseFail; 3353 } 3354 3355 // Add all the registers in the range to the register list. 3356 Count += EndReg - Reg; 3357 Reg = EndReg; 3358 continue; 3359 } 3360 Parser.Lex(); // Eat the comma. 3361 RegLoc = Parser.getTok().getLoc(); 3362 int OldReg = Reg; 3363 Reg = tryParseRegister(); 3364 if (Reg == -1) { 3365 Error(RegLoc, "register expected"); 3366 return MatchOperand_ParseFail; 3367 } 3368 // vector register lists must be contiguous. 3369 // It's OK to use the enumeration values directly here rather, as the 3370 // VFP register classes have the enum sorted properly. 3371 // 3372 // The list is of D registers, but we also allow Q regs and just interpret 3373 // them as the two D sub-registers. 3374 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3375 if (!Spacing) 3376 Spacing = 1; // Register range implies a single spaced list. 3377 else if (Spacing == 2) { 3378 Error(RegLoc, 3379 "invalid register in double-spaced list (must be 'D' register')"); 3380 return MatchOperand_ParseFail; 3381 } 3382 Reg = getDRegFromQReg(Reg); 3383 if (Reg != OldReg + 1) { 3384 Error(RegLoc, "non-contiguous register range"); 3385 return MatchOperand_ParseFail; 3386 } 3387 ++Reg; 3388 Count += 2; 3389 // Parse the lane specifier if present. 3390 VectorLaneTy NextLaneKind; 3391 unsigned NextLaneIndex; 3392 SMLoc LaneLoc = Parser.getTok().getLoc(); 3393 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3394 MatchOperand_Success) 3395 return MatchOperand_ParseFail; 3396 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3397 Error(LaneLoc, "mismatched lane index in register list"); 3398 return MatchOperand_ParseFail; 3399 } 3400 continue; 3401 } 3402 // Normal D register. 3403 // Figure out the register spacing (single or double) of the list if 3404 // we don't know it already. 3405 if (!Spacing) 3406 Spacing = 1 + (Reg == OldReg + 2); 3407 3408 // Just check that it's contiguous and keep going. 3409 if (Reg != OldReg + Spacing) { 3410 Error(RegLoc, "non-contiguous register range"); 3411 return MatchOperand_ParseFail; 3412 } 3413 ++Count; 3414 // Parse the lane specifier if present. 3415 VectorLaneTy NextLaneKind; 3416 unsigned NextLaneIndex; 3417 SMLoc EndLoc = Parser.getTok().getLoc(); 3418 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3419 return MatchOperand_ParseFail; 3420 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3421 Error(EndLoc, "mismatched lane index in register list"); 3422 return MatchOperand_ParseFail; 3423 } 3424 } 3425 3426 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3427 Error(Parser.getTok().getLoc(), "'}' expected"); 3428 return MatchOperand_ParseFail; 3429 } 3430 E = Parser.getTok().getEndLoc(); 3431 Parser.Lex(); // Eat '}' token. 3432 3433 switch (LaneKind) { 3434 case NoLanes: 3435 // Two-register operands have been converted to the 3436 // composite register classes. 3437 if (Count == 2) { 3438 const MCRegisterClass *RC = (Spacing == 1) ? 3439 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3440 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3441 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3442 } 3443 3444 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3445 (Spacing == 2), S, E)); 3446 break; 3447 case AllLanes: 3448 // Two-register operands have been converted to the 3449 // composite register classes. 3450 if (Count == 2) { 3451 const MCRegisterClass *RC = (Spacing == 1) ? 3452 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3453 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3454 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3455 } 3456 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3457 (Spacing == 2), 3458 S, E)); 3459 break; 3460 case IndexedLane: 3461 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3462 LaneIndex, 3463 (Spacing == 2), 3464 S, E)); 3465 break; 3466 } 3467 return MatchOperand_Success; 3468 } 3469 3470 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3471 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3472 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3473 SMLoc S = Parser.getTok().getLoc(); 3474 const AsmToken &Tok = Parser.getTok(); 3475 unsigned Opt; 3476 3477 if (Tok.is(AsmToken::Identifier)) { 3478 StringRef OptStr = Tok.getString(); 3479 3480 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3481 .Case("sy", ARM_MB::SY) 3482 .Case("st", ARM_MB::ST) 3483 .Case("ld", ARM_MB::LD) 3484 .Case("sh", ARM_MB::ISH) 3485 .Case("ish", ARM_MB::ISH) 3486 .Case("shst", ARM_MB::ISHST) 3487 .Case("ishst", ARM_MB::ISHST) 3488 .Case("ishld", ARM_MB::ISHLD) 3489 .Case("nsh", ARM_MB::NSH) 3490 .Case("un", ARM_MB::NSH) 3491 .Case("nshst", ARM_MB::NSHST) 3492 .Case("nshld", ARM_MB::NSHLD) 3493 .Case("unst", ARM_MB::NSHST) 3494 .Case("osh", ARM_MB::OSH) 3495 .Case("oshst", ARM_MB::OSHST) 3496 .Case("oshld", ARM_MB::OSHLD) 3497 .Default(~0U); 3498 3499 // ishld, oshld, nshld and ld are only available from ARMv8. 3500 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || 3501 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) 3502 Opt = ~0U; 3503 3504 if (Opt == ~0U) 3505 return MatchOperand_NoMatch; 3506 3507 Parser.Lex(); // Eat identifier token. 3508 } else if (Tok.is(AsmToken::Hash) || 3509 Tok.is(AsmToken::Dollar) || 3510 Tok.is(AsmToken::Integer)) { 3511 if (Parser.getTok().isNot(AsmToken::Integer)) 3512 Parser.Lex(); // Eat '#' or '$'. 3513 SMLoc Loc = Parser.getTok().getLoc(); 3514 3515 const MCExpr *MemBarrierID; 3516 if (getParser().parseExpression(MemBarrierID)) { 3517 Error(Loc, "illegal expression"); 3518 return MatchOperand_ParseFail; 3519 } 3520 3521 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3522 if (!CE) { 3523 Error(Loc, "constant expression expected"); 3524 return MatchOperand_ParseFail; 3525 } 3526 3527 int Val = CE->getValue(); 3528 if (Val & ~0xf) { 3529 Error(Loc, "immediate value out of range"); 3530 return MatchOperand_ParseFail; 3531 } 3532 3533 Opt = ARM_MB::RESERVED_0 + Val; 3534 } else 3535 return MatchOperand_ParseFail; 3536 3537 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3538 return MatchOperand_Success; 3539 } 3540 3541 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3542 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3543 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3544 SMLoc S = Parser.getTok().getLoc(); 3545 const AsmToken &Tok = Parser.getTok(); 3546 unsigned Opt; 3547 3548 if (Tok.is(AsmToken::Identifier)) { 3549 StringRef OptStr = Tok.getString(); 3550 3551 if (OptStr.lower() == "sy") 3552 Opt = ARM_ISB::SY; 3553 else 3554 return MatchOperand_NoMatch; 3555 3556 Parser.Lex(); // Eat identifier token. 3557 } else if (Tok.is(AsmToken::Hash) || 3558 Tok.is(AsmToken::Dollar) || 3559 Tok.is(AsmToken::Integer)) { 3560 if (Parser.getTok().isNot(AsmToken::Integer)) 3561 Parser.Lex(); // Eat '#' or '$'. 3562 SMLoc Loc = Parser.getTok().getLoc(); 3563 3564 const MCExpr *ISBarrierID; 3565 if (getParser().parseExpression(ISBarrierID)) { 3566 Error(Loc, "illegal expression"); 3567 return MatchOperand_ParseFail; 3568 } 3569 3570 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3571 if (!CE) { 3572 Error(Loc, "constant expression expected"); 3573 return MatchOperand_ParseFail; 3574 } 3575 3576 int Val = CE->getValue(); 3577 if (Val & ~0xf) { 3578 Error(Loc, "immediate value out of range"); 3579 return MatchOperand_ParseFail; 3580 } 3581 3582 Opt = ARM_ISB::RESERVED_0 + Val; 3583 } else 3584 return MatchOperand_ParseFail; 3585 3586 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3587 (ARM_ISB::InstSyncBOpt)Opt, S)); 3588 return MatchOperand_Success; 3589 } 3590 3591 3592 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3593 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3594 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3595 SMLoc S = Parser.getTok().getLoc(); 3596 const AsmToken &Tok = Parser.getTok(); 3597 if (!Tok.is(AsmToken::Identifier)) 3598 return MatchOperand_NoMatch; 3599 StringRef IFlagsStr = Tok.getString(); 3600 3601 // An iflags string of "none" is interpreted to mean that none of the AIF 3602 // bits are set. Not a terribly useful instruction, but a valid encoding. 3603 unsigned IFlags = 0; 3604 if (IFlagsStr != "none") { 3605 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3606 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3607 .Case("a", ARM_PROC::A) 3608 .Case("i", ARM_PROC::I) 3609 .Case("f", ARM_PROC::F) 3610 .Default(~0U); 3611 3612 // If some specific iflag is already set, it means that some letter is 3613 // present more than once, this is not acceptable. 3614 if (Flag == ~0U || (IFlags & Flag)) 3615 return MatchOperand_NoMatch; 3616 3617 IFlags |= Flag; 3618 } 3619 } 3620 3621 Parser.Lex(); // Eat identifier token. 3622 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3623 return MatchOperand_Success; 3624 } 3625 3626 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3627 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3628 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3629 SMLoc S = Parser.getTok().getLoc(); 3630 const AsmToken &Tok = Parser.getTok(); 3631 if (!Tok.is(AsmToken::Identifier)) 3632 return MatchOperand_NoMatch; 3633 StringRef Mask = Tok.getString(); 3634 3635 if (isMClass()) { 3636 // See ARMv6-M 10.1.1 3637 std::string Name = Mask.lower(); 3638 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3639 // Note: in the documentation: 3640 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3641 // for MSR APSR_nzcvq. 3642 // but we do make it an alias here. This is so to get the "mask encoding" 3643 // bits correct on MSR APSR writes. 3644 // 3645 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3646 // should really only be allowed when writing a special register. Note 3647 // they get dropped in the MRS instruction reading a special register as 3648 // the SYSm field is only 8 bits. 3649 // 3650 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3651 // includes the DSP extension but that is not checked. 3652 .Case("apsr", 0x800) 3653 .Case("apsr_nzcvq", 0x800) 3654 .Case("apsr_g", 0x400) 3655 .Case("apsr_nzcvqg", 0xc00) 3656 .Case("iapsr", 0x801) 3657 .Case("iapsr_nzcvq", 0x801) 3658 .Case("iapsr_g", 0x401) 3659 .Case("iapsr_nzcvqg", 0xc01) 3660 .Case("eapsr", 0x802) 3661 .Case("eapsr_nzcvq", 0x802) 3662 .Case("eapsr_g", 0x402) 3663 .Case("eapsr_nzcvqg", 0xc02) 3664 .Case("xpsr", 0x803) 3665 .Case("xpsr_nzcvq", 0x803) 3666 .Case("xpsr_g", 0x403) 3667 .Case("xpsr_nzcvqg", 0xc03) 3668 .Case("ipsr", 0x805) 3669 .Case("epsr", 0x806) 3670 .Case("iepsr", 0x807) 3671 .Case("msp", 0x808) 3672 .Case("psp", 0x809) 3673 .Case("primask", 0x810) 3674 .Case("basepri", 0x811) 3675 .Case("basepri_max", 0x812) 3676 .Case("faultmask", 0x813) 3677 .Case("control", 0x814) 3678 .Default(~0U); 3679 3680 if (FlagsVal == ~0U) 3681 return MatchOperand_NoMatch; 3682 3683 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3684 // basepri, basepri_max and faultmask only valid for V7m. 3685 return MatchOperand_NoMatch; 3686 3687 Parser.Lex(); // Eat identifier token. 3688 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3689 return MatchOperand_Success; 3690 } 3691 3692 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3693 size_t Start = 0, Next = Mask.find('_'); 3694 StringRef Flags = ""; 3695 std::string SpecReg = Mask.slice(Start, Next).lower(); 3696 if (Next != StringRef::npos) 3697 Flags = Mask.slice(Next+1, Mask.size()); 3698 3699 // FlagsVal contains the complete mask: 3700 // 3-0: Mask 3701 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3702 unsigned FlagsVal = 0; 3703 3704 if (SpecReg == "apsr") { 3705 FlagsVal = StringSwitch<unsigned>(Flags) 3706 .Case("nzcvq", 0x8) // same as CPSR_f 3707 .Case("g", 0x4) // same as CPSR_s 3708 .Case("nzcvqg", 0xc) // same as CPSR_fs 3709 .Default(~0U); 3710 3711 if (FlagsVal == ~0U) { 3712 if (!Flags.empty()) 3713 return MatchOperand_NoMatch; 3714 else 3715 FlagsVal = 8; // No flag 3716 } 3717 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3718 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3719 if (Flags == "all" || Flags == "") 3720 Flags = "fc"; 3721 for (int i = 0, e = Flags.size(); i != e; ++i) { 3722 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3723 .Case("c", 1) 3724 .Case("x", 2) 3725 .Case("s", 4) 3726 .Case("f", 8) 3727 .Default(~0U); 3728 3729 // If some specific flag is already set, it means that some letter is 3730 // present more than once, this is not acceptable. 3731 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3732 return MatchOperand_NoMatch; 3733 FlagsVal |= Flag; 3734 } 3735 } else // No match for special register. 3736 return MatchOperand_NoMatch; 3737 3738 // Special register without flags is NOT equivalent to "fc" flags. 3739 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3740 // two lines would enable gas compatibility at the expense of breaking 3741 // round-tripping. 3742 // 3743 // if (!FlagsVal) 3744 // FlagsVal = 0x9; 3745 3746 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3747 if (SpecReg == "spsr") 3748 FlagsVal |= 16; 3749 3750 Parser.Lex(); // Eat identifier token. 3751 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3752 return MatchOperand_Success; 3753 } 3754 3755 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3756 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3757 int Low, int High) { 3758 const AsmToken &Tok = Parser.getTok(); 3759 if (Tok.isNot(AsmToken::Identifier)) { 3760 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3761 return MatchOperand_ParseFail; 3762 } 3763 StringRef ShiftName = Tok.getString(); 3764 std::string LowerOp = Op.lower(); 3765 std::string UpperOp = Op.upper(); 3766 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3767 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3768 return MatchOperand_ParseFail; 3769 } 3770 Parser.Lex(); // Eat shift type token. 3771 3772 // There must be a '#' and a shift amount. 3773 if (Parser.getTok().isNot(AsmToken::Hash) && 3774 Parser.getTok().isNot(AsmToken::Dollar)) { 3775 Error(Parser.getTok().getLoc(), "'#' expected"); 3776 return MatchOperand_ParseFail; 3777 } 3778 Parser.Lex(); // Eat hash token. 3779 3780 const MCExpr *ShiftAmount; 3781 SMLoc Loc = Parser.getTok().getLoc(); 3782 SMLoc EndLoc; 3783 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3784 Error(Loc, "illegal expression"); 3785 return MatchOperand_ParseFail; 3786 } 3787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3788 if (!CE) { 3789 Error(Loc, "constant expression expected"); 3790 return MatchOperand_ParseFail; 3791 } 3792 int Val = CE->getValue(); 3793 if (Val < Low || Val > High) { 3794 Error(Loc, "immediate value out of range"); 3795 return MatchOperand_ParseFail; 3796 } 3797 3798 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 3799 3800 return MatchOperand_Success; 3801 } 3802 3803 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3804 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3805 const AsmToken &Tok = Parser.getTok(); 3806 SMLoc S = Tok.getLoc(); 3807 if (Tok.isNot(AsmToken::Identifier)) { 3808 Error(S, "'be' or 'le' operand expected"); 3809 return MatchOperand_ParseFail; 3810 } 3811 int Val = StringSwitch<int>(Tok.getString().lower()) 3812 .Case("be", 1) 3813 .Case("le", 0) 3814 .Default(-1); 3815 Parser.Lex(); // Eat the token. 3816 3817 if (Val == -1) { 3818 Error(S, "'be' or 'le' operand expected"); 3819 return MatchOperand_ParseFail; 3820 } 3821 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3822 getContext()), 3823 S, Tok.getEndLoc())); 3824 return MatchOperand_Success; 3825 } 3826 3827 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3828 /// instructions. Legal values are: 3829 /// lsl #n 'n' in [0,31] 3830 /// asr #n 'n' in [1,32] 3831 /// n == 32 encoded as n == 0. 3832 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3833 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3834 const AsmToken &Tok = Parser.getTok(); 3835 SMLoc S = Tok.getLoc(); 3836 if (Tok.isNot(AsmToken::Identifier)) { 3837 Error(S, "shift operator 'asr' or 'lsl' expected"); 3838 return MatchOperand_ParseFail; 3839 } 3840 StringRef ShiftName = Tok.getString(); 3841 bool isASR; 3842 if (ShiftName == "lsl" || ShiftName == "LSL") 3843 isASR = false; 3844 else if (ShiftName == "asr" || ShiftName == "ASR") 3845 isASR = true; 3846 else { 3847 Error(S, "shift operator 'asr' or 'lsl' expected"); 3848 return MatchOperand_ParseFail; 3849 } 3850 Parser.Lex(); // Eat the operator. 3851 3852 // A '#' and a shift amount. 3853 if (Parser.getTok().isNot(AsmToken::Hash) && 3854 Parser.getTok().isNot(AsmToken::Dollar)) { 3855 Error(Parser.getTok().getLoc(), "'#' expected"); 3856 return MatchOperand_ParseFail; 3857 } 3858 Parser.Lex(); // Eat hash token. 3859 SMLoc ExLoc = Parser.getTok().getLoc(); 3860 3861 const MCExpr *ShiftAmount; 3862 SMLoc EndLoc; 3863 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3864 Error(ExLoc, "malformed shift expression"); 3865 return MatchOperand_ParseFail; 3866 } 3867 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3868 if (!CE) { 3869 Error(ExLoc, "shift amount must be an immediate"); 3870 return MatchOperand_ParseFail; 3871 } 3872 3873 int64_t Val = CE->getValue(); 3874 if (isASR) { 3875 // Shift amount must be in [1,32] 3876 if (Val < 1 || Val > 32) { 3877 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 3878 return MatchOperand_ParseFail; 3879 } 3880 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3881 if (isThumb() && Val == 32) { 3882 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 3883 return MatchOperand_ParseFail; 3884 } 3885 if (Val == 32) Val = 0; 3886 } else { 3887 // Shift amount must be in [1,32] 3888 if (Val < 0 || Val > 31) { 3889 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 3890 return MatchOperand_ParseFail; 3891 } 3892 } 3893 3894 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 3895 3896 return MatchOperand_Success; 3897 } 3898 3899 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3900 /// of instructions. Legal values are: 3901 /// ror #n 'n' in {0, 8, 16, 24} 3902 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3903 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3904 const AsmToken &Tok = Parser.getTok(); 3905 SMLoc S = Tok.getLoc(); 3906 if (Tok.isNot(AsmToken::Identifier)) 3907 return MatchOperand_NoMatch; 3908 StringRef ShiftName = Tok.getString(); 3909 if (ShiftName != "ror" && ShiftName != "ROR") 3910 return MatchOperand_NoMatch; 3911 Parser.Lex(); // Eat the operator. 3912 3913 // A '#' and a rotate amount. 3914 if (Parser.getTok().isNot(AsmToken::Hash) && 3915 Parser.getTok().isNot(AsmToken::Dollar)) { 3916 Error(Parser.getTok().getLoc(), "'#' expected"); 3917 return MatchOperand_ParseFail; 3918 } 3919 Parser.Lex(); // Eat hash token. 3920 SMLoc ExLoc = Parser.getTok().getLoc(); 3921 3922 const MCExpr *ShiftAmount; 3923 SMLoc EndLoc; 3924 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3925 Error(ExLoc, "malformed rotate expression"); 3926 return MatchOperand_ParseFail; 3927 } 3928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3929 if (!CE) { 3930 Error(ExLoc, "rotate amount must be an immediate"); 3931 return MatchOperand_ParseFail; 3932 } 3933 3934 int64_t Val = CE->getValue(); 3935 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 3936 // normally, zero is represented in asm by omitting the rotate operand 3937 // entirely. 3938 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 3939 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 3940 return MatchOperand_ParseFail; 3941 } 3942 3943 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 3944 3945 return MatchOperand_Success; 3946 } 3947 3948 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3949 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3950 SMLoc S = Parser.getTok().getLoc(); 3951 // The bitfield descriptor is really two operands, the LSB and the width. 3952 if (Parser.getTok().isNot(AsmToken::Hash) && 3953 Parser.getTok().isNot(AsmToken::Dollar)) { 3954 Error(Parser.getTok().getLoc(), "'#' expected"); 3955 return MatchOperand_ParseFail; 3956 } 3957 Parser.Lex(); // Eat hash token. 3958 3959 const MCExpr *LSBExpr; 3960 SMLoc E = Parser.getTok().getLoc(); 3961 if (getParser().parseExpression(LSBExpr)) { 3962 Error(E, "malformed immediate expression"); 3963 return MatchOperand_ParseFail; 3964 } 3965 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3966 if (!CE) { 3967 Error(E, "'lsb' operand must be an immediate"); 3968 return MatchOperand_ParseFail; 3969 } 3970 3971 int64_t LSB = CE->getValue(); 3972 // The LSB must be in the range [0,31] 3973 if (LSB < 0 || LSB > 31) { 3974 Error(E, "'lsb' operand must be in the range [0,31]"); 3975 return MatchOperand_ParseFail; 3976 } 3977 E = Parser.getTok().getLoc(); 3978 3979 // Expect another immediate operand. 3980 if (Parser.getTok().isNot(AsmToken::Comma)) { 3981 Error(Parser.getTok().getLoc(), "too few operands"); 3982 return MatchOperand_ParseFail; 3983 } 3984 Parser.Lex(); // Eat hash token. 3985 if (Parser.getTok().isNot(AsmToken::Hash) && 3986 Parser.getTok().isNot(AsmToken::Dollar)) { 3987 Error(Parser.getTok().getLoc(), "'#' expected"); 3988 return MatchOperand_ParseFail; 3989 } 3990 Parser.Lex(); // Eat hash token. 3991 3992 const MCExpr *WidthExpr; 3993 SMLoc EndLoc; 3994 if (getParser().parseExpression(WidthExpr, EndLoc)) { 3995 Error(E, "malformed immediate expression"); 3996 return MatchOperand_ParseFail; 3997 } 3998 CE = dyn_cast<MCConstantExpr>(WidthExpr); 3999 if (!CE) { 4000 Error(E, "'width' operand must be an immediate"); 4001 return MatchOperand_ParseFail; 4002 } 4003 4004 int64_t Width = CE->getValue(); 4005 // The LSB must be in the range [1,32-lsb] 4006 if (Width < 1 || Width > 32 - LSB) { 4007 Error(E, "'width' operand must be in the range [1,32-lsb]"); 4008 return MatchOperand_ParseFail; 4009 } 4010 4011 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 4012 4013 return MatchOperand_Success; 4014 } 4015 4016 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4017 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4018 // Check for a post-index addressing register operand. Specifically: 4019 // postidx_reg := '+' register {, shift} 4020 // | '-' register {, shift} 4021 // | register {, shift} 4022 4023 // This method must return MatchOperand_NoMatch without consuming any tokens 4024 // in the case where there is no match, as other alternatives take other 4025 // parse methods. 4026 AsmToken Tok = Parser.getTok(); 4027 SMLoc S = Tok.getLoc(); 4028 bool haveEaten = false; 4029 bool isAdd = true; 4030 if (Tok.is(AsmToken::Plus)) { 4031 Parser.Lex(); // Eat the '+' token. 4032 haveEaten = true; 4033 } else if (Tok.is(AsmToken::Minus)) { 4034 Parser.Lex(); // Eat the '-' token. 4035 isAdd = false; 4036 haveEaten = true; 4037 } 4038 4039 SMLoc E = Parser.getTok().getEndLoc(); 4040 int Reg = tryParseRegister(); 4041 if (Reg == -1) { 4042 if (!haveEaten) 4043 return MatchOperand_NoMatch; 4044 Error(Parser.getTok().getLoc(), "register expected"); 4045 return MatchOperand_ParseFail; 4046 } 4047 4048 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 4049 unsigned ShiftImm = 0; 4050 if (Parser.getTok().is(AsmToken::Comma)) { 4051 Parser.Lex(); // Eat the ','. 4052 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 4053 return MatchOperand_ParseFail; 4054 4055 // FIXME: Only approximates end...may include intervening whitespace. 4056 E = Parser.getTok().getLoc(); 4057 } 4058 4059 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 4060 ShiftImm, S, E)); 4061 4062 return MatchOperand_Success; 4063 } 4064 4065 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4066 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4067 // Check for a post-index addressing register operand. Specifically: 4068 // am3offset := '+' register 4069 // | '-' register 4070 // | register 4071 // | # imm 4072 // | # + imm 4073 // | # - imm 4074 4075 // This method must return MatchOperand_NoMatch without consuming any tokens 4076 // in the case where there is no match, as other alternatives take other 4077 // parse methods. 4078 AsmToken Tok = Parser.getTok(); 4079 SMLoc S = Tok.getLoc(); 4080 4081 // Do immediates first, as we always parse those if we have a '#'. 4082 if (Parser.getTok().is(AsmToken::Hash) || 4083 Parser.getTok().is(AsmToken::Dollar)) { 4084 Parser.Lex(); // Eat '#' or '$'. 4085 // Explicitly look for a '-', as we need to encode negative zero 4086 // differently. 4087 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4088 const MCExpr *Offset; 4089 SMLoc E; 4090 if (getParser().parseExpression(Offset, E)) 4091 return MatchOperand_ParseFail; 4092 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4093 if (!CE) { 4094 Error(S, "constant expression expected"); 4095 return MatchOperand_ParseFail; 4096 } 4097 // Negative zero is encoded as the flag value INT32_MIN. 4098 int32_t Val = CE->getValue(); 4099 if (isNegative && Val == 0) 4100 Val = INT32_MIN; 4101 4102 Operands.push_back( 4103 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 4104 4105 return MatchOperand_Success; 4106 } 4107 4108 4109 bool haveEaten = false; 4110 bool isAdd = true; 4111 if (Tok.is(AsmToken::Plus)) { 4112 Parser.Lex(); // Eat the '+' token. 4113 haveEaten = true; 4114 } else if (Tok.is(AsmToken::Minus)) { 4115 Parser.Lex(); // Eat the '-' token. 4116 isAdd = false; 4117 haveEaten = true; 4118 } 4119 4120 Tok = Parser.getTok(); 4121 int Reg = tryParseRegister(); 4122 if (Reg == -1) { 4123 if (!haveEaten) 4124 return MatchOperand_NoMatch; 4125 Error(Tok.getLoc(), "register expected"); 4126 return MatchOperand_ParseFail; 4127 } 4128 4129 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 4130 0, S, Tok.getEndLoc())); 4131 4132 return MatchOperand_Success; 4133 } 4134 4135 /// Convert parsed operands to MCInst. Needed here because this instruction 4136 /// only has two register operands, but multiplication is commutative so 4137 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". 4138 void ARMAsmParser:: 4139 cvtThumbMultiply(MCInst &Inst, 4140 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4141 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4142 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4143 // If we have a three-operand form, make sure to set Rn to be the operand 4144 // that isn't the same as Rd. 4145 unsigned RegOp = 4; 4146 if (Operands.size() == 6 && 4147 ((ARMOperand*)Operands[4])->getReg() == 4148 ((ARMOperand*)Operands[3])->getReg()) 4149 RegOp = 5; 4150 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4151 Inst.addOperand(Inst.getOperand(0)); 4152 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4153 } 4154 4155 void ARMAsmParser:: 4156 cvtThumbBranches(MCInst &Inst, 4157 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4158 int CondOp = -1, ImmOp = -1; 4159 switch(Inst.getOpcode()) { 4160 case ARM::tB: 4161 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; 4162 4163 case ARM::t2B: 4164 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; 4165 4166 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches"); 4167 } 4168 // first decide whether or not the branch should be conditional 4169 // by looking at it's location relative to an IT block 4170 if(inITBlock()) { 4171 // inside an IT block we cannot have any conditional branches. any 4172 // such instructions needs to be converted to unconditional form 4173 switch(Inst.getOpcode()) { 4174 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; 4175 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; 4176 } 4177 } else { 4178 // outside IT blocks we can only have unconditional branches with AL 4179 // condition code or conditional branches with non-AL condition code 4180 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode(); 4181 switch(Inst.getOpcode()) { 4182 case ARM::tB: 4183 case ARM::tBcc: 4184 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); 4185 break; 4186 case ARM::t2B: 4187 case ARM::t2Bcc: 4188 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); 4189 break; 4190 } 4191 } 4192 4193 // now decide on encoding size based on branch target range 4194 switch(Inst.getOpcode()) { 4195 // classify tB as either t2B or t1B based on range of immediate operand 4196 case ARM::tB: { 4197 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]); 4198 if(!op->isSignedOffset<11, 1>() && isThumbTwo()) 4199 Inst.setOpcode(ARM::t2B); 4200 break; 4201 } 4202 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand 4203 case ARM::tBcc: { 4204 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]); 4205 if(!op->isSignedOffset<8, 1>() && isThumbTwo()) 4206 Inst.setOpcode(ARM::t2Bcc); 4207 break; 4208 } 4209 } 4210 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1); 4211 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2); 4212 } 4213 4214 /// Parse an ARM memory expression, return false if successful else return true 4215 /// or an error. The first token must be a '[' when called. 4216 bool ARMAsmParser:: 4217 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4218 SMLoc S, E; 4219 assert(Parser.getTok().is(AsmToken::LBrac) && 4220 "Token is not a Left Bracket"); 4221 S = Parser.getTok().getLoc(); 4222 Parser.Lex(); // Eat left bracket token. 4223 4224 const AsmToken &BaseRegTok = Parser.getTok(); 4225 int BaseRegNum = tryParseRegister(); 4226 if (BaseRegNum == -1) 4227 return Error(BaseRegTok.getLoc(), "register expected"); 4228 4229 // The next token must either be a comma, a colon or a closing bracket. 4230 const AsmToken &Tok = Parser.getTok(); 4231 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 4232 !Tok.is(AsmToken::RBrac)) 4233 return Error(Tok.getLoc(), "malformed memory operand"); 4234 4235 if (Tok.is(AsmToken::RBrac)) { 4236 E = Tok.getEndLoc(); 4237 Parser.Lex(); // Eat right bracket token. 4238 4239 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4240 0, 0, false, S, E)); 4241 4242 // If there's a pre-indexing writeback marker, '!', just add it as a token 4243 // operand. It's rather odd, but syntactically valid. 4244 if (Parser.getTok().is(AsmToken::Exclaim)) { 4245 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4246 Parser.Lex(); // Eat the '!'. 4247 } 4248 4249 return false; 4250 } 4251 4252 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 4253 "Lost colon or comma in memory operand?!"); 4254 if (Tok.is(AsmToken::Comma)) { 4255 Parser.Lex(); // Eat the comma. 4256 } 4257 4258 // If we have a ':', it's an alignment specifier. 4259 if (Parser.getTok().is(AsmToken::Colon)) { 4260 Parser.Lex(); // Eat the ':'. 4261 E = Parser.getTok().getLoc(); 4262 4263 const MCExpr *Expr; 4264 if (getParser().parseExpression(Expr)) 4265 return true; 4266 4267 // The expression has to be a constant. Memory references with relocations 4268 // don't come through here, as they use the <label> forms of the relevant 4269 // instructions. 4270 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4271 if (!CE) 4272 return Error (E, "constant expression expected"); 4273 4274 unsigned Align = 0; 4275 switch (CE->getValue()) { 4276 default: 4277 return Error(E, 4278 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4279 case 16: Align = 2; break; 4280 case 32: Align = 4; break; 4281 case 64: Align = 8; break; 4282 case 128: Align = 16; break; 4283 case 256: Align = 32; break; 4284 } 4285 4286 // Now we should have the closing ']' 4287 if (Parser.getTok().isNot(AsmToken::RBrac)) 4288 return Error(Parser.getTok().getLoc(), "']' expected"); 4289 E = Parser.getTok().getEndLoc(); 4290 Parser.Lex(); // Eat right bracket token. 4291 4292 // Don't worry about range checking the value here. That's handled by 4293 // the is*() predicates. 4294 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4295 ARM_AM::no_shift, 0, Align, 4296 false, S, E)); 4297 4298 // If there's a pre-indexing writeback marker, '!', just add it as a token 4299 // operand. 4300 if (Parser.getTok().is(AsmToken::Exclaim)) { 4301 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4302 Parser.Lex(); // Eat the '!'. 4303 } 4304 4305 return false; 4306 } 4307 4308 // If we have a '#', it's an immediate offset, else assume it's a register 4309 // offset. Be friendly and also accept a plain integer (without a leading 4310 // hash) for gas compatibility. 4311 if (Parser.getTok().is(AsmToken::Hash) || 4312 Parser.getTok().is(AsmToken::Dollar) || 4313 Parser.getTok().is(AsmToken::Integer)) { 4314 if (Parser.getTok().isNot(AsmToken::Integer)) 4315 Parser.Lex(); // Eat '#' or '$'. 4316 E = Parser.getTok().getLoc(); 4317 4318 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4319 const MCExpr *Offset; 4320 if (getParser().parseExpression(Offset)) 4321 return true; 4322 4323 // The expression has to be a constant. Memory references with relocations 4324 // don't come through here, as they use the <label> forms of the relevant 4325 // instructions. 4326 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4327 if (!CE) 4328 return Error (E, "constant expression expected"); 4329 4330 // If the constant was #-0, represent it as INT32_MIN. 4331 int32_t Val = CE->getValue(); 4332 if (isNegative && Val == 0) 4333 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4334 4335 // Now we should have the closing ']' 4336 if (Parser.getTok().isNot(AsmToken::RBrac)) 4337 return Error(Parser.getTok().getLoc(), "']' expected"); 4338 E = Parser.getTok().getEndLoc(); 4339 Parser.Lex(); // Eat right bracket token. 4340 4341 // Don't worry about range checking the value here. That's handled by 4342 // the is*() predicates. 4343 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4344 ARM_AM::no_shift, 0, 0, 4345 false, S, E)); 4346 4347 // If there's a pre-indexing writeback marker, '!', just add it as a token 4348 // operand. 4349 if (Parser.getTok().is(AsmToken::Exclaim)) { 4350 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4351 Parser.Lex(); // Eat the '!'. 4352 } 4353 4354 return false; 4355 } 4356 4357 // The register offset is optionally preceded by a '+' or '-' 4358 bool isNegative = false; 4359 if (Parser.getTok().is(AsmToken::Minus)) { 4360 isNegative = true; 4361 Parser.Lex(); // Eat the '-'. 4362 } else if (Parser.getTok().is(AsmToken::Plus)) { 4363 // Nothing to do. 4364 Parser.Lex(); // Eat the '+'. 4365 } 4366 4367 E = Parser.getTok().getLoc(); 4368 int OffsetRegNum = tryParseRegister(); 4369 if (OffsetRegNum == -1) 4370 return Error(E, "register expected"); 4371 4372 // If there's a shift operator, handle it. 4373 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4374 unsigned ShiftImm = 0; 4375 if (Parser.getTok().is(AsmToken::Comma)) { 4376 Parser.Lex(); // Eat the ','. 4377 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4378 return true; 4379 } 4380 4381 // Now we should have the closing ']' 4382 if (Parser.getTok().isNot(AsmToken::RBrac)) 4383 return Error(Parser.getTok().getLoc(), "']' expected"); 4384 E = Parser.getTok().getEndLoc(); 4385 Parser.Lex(); // Eat right bracket token. 4386 4387 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4388 ShiftType, ShiftImm, 0, isNegative, 4389 S, E)); 4390 4391 // If there's a pre-indexing writeback marker, '!', just add it as a token 4392 // operand. 4393 if (Parser.getTok().is(AsmToken::Exclaim)) { 4394 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4395 Parser.Lex(); // Eat the '!'. 4396 } 4397 4398 return false; 4399 } 4400 4401 /// parseMemRegOffsetShift - one of these two: 4402 /// ( lsl | lsr | asr | ror ) , # shift_amount 4403 /// rrx 4404 /// return true if it parses a shift otherwise it returns false. 4405 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4406 unsigned &Amount) { 4407 SMLoc Loc = Parser.getTok().getLoc(); 4408 const AsmToken &Tok = Parser.getTok(); 4409 if (Tok.isNot(AsmToken::Identifier)) 4410 return true; 4411 StringRef ShiftName = Tok.getString(); 4412 if (ShiftName == "lsl" || ShiftName == "LSL" || 4413 ShiftName == "asl" || ShiftName == "ASL") 4414 St = ARM_AM::lsl; 4415 else if (ShiftName == "lsr" || ShiftName == "LSR") 4416 St = ARM_AM::lsr; 4417 else if (ShiftName == "asr" || ShiftName == "ASR") 4418 St = ARM_AM::asr; 4419 else if (ShiftName == "ror" || ShiftName == "ROR") 4420 St = ARM_AM::ror; 4421 else if (ShiftName == "rrx" || ShiftName == "RRX") 4422 St = ARM_AM::rrx; 4423 else 4424 return Error(Loc, "illegal shift operator"); 4425 Parser.Lex(); // Eat shift type token. 4426 4427 // rrx stands alone. 4428 Amount = 0; 4429 if (St != ARM_AM::rrx) { 4430 Loc = Parser.getTok().getLoc(); 4431 // A '#' and a shift amount. 4432 const AsmToken &HashTok = Parser.getTok(); 4433 if (HashTok.isNot(AsmToken::Hash) && 4434 HashTok.isNot(AsmToken::Dollar)) 4435 return Error(HashTok.getLoc(), "'#' expected"); 4436 Parser.Lex(); // Eat hash token. 4437 4438 const MCExpr *Expr; 4439 if (getParser().parseExpression(Expr)) 4440 return true; 4441 // Range check the immediate. 4442 // lsl, ror: 0 <= imm <= 31 4443 // lsr, asr: 0 <= imm <= 32 4444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4445 if (!CE) 4446 return Error(Loc, "shift amount must be an immediate"); 4447 int64_t Imm = CE->getValue(); 4448 if (Imm < 0 || 4449 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4450 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4451 return Error(Loc, "immediate shift value out of range"); 4452 // If <ShiftTy> #0, turn it into a no_shift. 4453 if (Imm == 0) 4454 St = ARM_AM::lsl; 4455 // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 4456 if (Imm == 32) 4457 Imm = 0; 4458 Amount = Imm; 4459 } 4460 4461 return false; 4462 } 4463 4464 /// parseFPImm - A floating point immediate expression operand. 4465 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4466 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4467 // Anything that can accept a floating point constant as an operand 4468 // needs to go through here, as the regular parseExpression is 4469 // integer only. 4470 // 4471 // This routine still creates a generic Immediate operand, containing 4472 // a bitcast of the 64-bit floating point value. The various operands 4473 // that accept floats can check whether the value is valid for them 4474 // via the standard is*() predicates. 4475 4476 SMLoc S = Parser.getTok().getLoc(); 4477 4478 if (Parser.getTok().isNot(AsmToken::Hash) && 4479 Parser.getTok().isNot(AsmToken::Dollar)) 4480 return MatchOperand_NoMatch; 4481 4482 // Disambiguate the VMOV forms that can accept an FP immediate. 4483 // vmov.f32 <sreg>, #imm 4484 // vmov.f64 <dreg>, #imm 4485 // vmov.f32 <dreg>, #imm @ vector f32x2 4486 // vmov.f32 <qreg>, #imm @ vector f32x4 4487 // 4488 // There are also the NEON VMOV instructions which expect an 4489 // integer constant. Make sure we don't try to parse an FPImm 4490 // for these: 4491 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4492 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4493 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 4494 TyOp->getToken() != ".f64")) 4495 return MatchOperand_NoMatch; 4496 4497 Parser.Lex(); // Eat '#' or '$'. 4498 4499 // Handle negation, as that still comes through as a separate token. 4500 bool isNegative = false; 4501 if (Parser.getTok().is(AsmToken::Minus)) { 4502 isNegative = true; 4503 Parser.Lex(); 4504 } 4505 const AsmToken &Tok = Parser.getTok(); 4506 SMLoc Loc = Tok.getLoc(); 4507 if (Tok.is(AsmToken::Real)) { 4508 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4509 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4510 // If we had a '-' in front, toggle the sign bit. 4511 IntVal ^= (uint64_t)isNegative << 31; 4512 Parser.Lex(); // Eat the token. 4513 Operands.push_back(ARMOperand::CreateImm( 4514 MCConstantExpr::Create(IntVal, getContext()), 4515 S, Parser.getTok().getLoc())); 4516 return MatchOperand_Success; 4517 } 4518 // Also handle plain integers. Instructions which allow floating point 4519 // immediates also allow a raw encoded 8-bit value. 4520 if (Tok.is(AsmToken::Integer)) { 4521 int64_t Val = Tok.getIntVal(); 4522 Parser.Lex(); // Eat the token. 4523 if (Val > 255 || Val < 0) { 4524 Error(Loc, "encoded floating point value out of range"); 4525 return MatchOperand_ParseFail; 4526 } 4527 double RealVal = ARM_AM::getFPImmFloat(Val); 4528 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 4529 Operands.push_back(ARMOperand::CreateImm( 4530 MCConstantExpr::Create(Val, getContext()), S, 4531 Parser.getTok().getLoc())); 4532 return MatchOperand_Success; 4533 } 4534 4535 Error(Loc, "invalid floating point immediate"); 4536 return MatchOperand_ParseFail; 4537 } 4538 4539 /// Parse a arm instruction operand. For now this parses the operand regardless 4540 /// of the mnemonic. 4541 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4542 StringRef Mnemonic) { 4543 SMLoc S, E; 4544 4545 // Check if the current operand has a custom associated parser, if so, try to 4546 // custom parse the operand, or fallback to the general approach. 4547 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4548 if (ResTy == MatchOperand_Success) 4549 return false; 4550 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4551 // there was a match, but an error occurred, in which case, just return that 4552 // the operand parsing failed. 4553 if (ResTy == MatchOperand_ParseFail) 4554 return true; 4555 4556 switch (getLexer().getKind()) { 4557 default: 4558 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4559 return true; 4560 case AsmToken::Identifier: { 4561 // If we've seen a branch mnemonic, the next operand must be a label. This 4562 // is true even if the label is a register name. So "br r1" means branch to 4563 // label "r1". 4564 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 4565 if (!ExpectLabel) { 4566 if (!tryParseRegisterWithWriteBack(Operands)) 4567 return false; 4568 int Res = tryParseShiftRegister(Operands); 4569 if (Res == 0) // success 4570 return false; 4571 else if (Res == -1) // irrecoverable error 4572 return true; 4573 // If this is VMRS, check for the apsr_nzcv operand. 4574 if (Mnemonic == "vmrs" && 4575 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4576 S = Parser.getTok().getLoc(); 4577 Parser.Lex(); 4578 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4579 return false; 4580 } 4581 } 4582 4583 // Fall though for the Identifier case that is not a register or a 4584 // special name. 4585 } 4586 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4587 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4588 case AsmToken::String: // quoted label names. 4589 case AsmToken::Dot: { // . as a branch target 4590 // This was not a register so parse other operands that start with an 4591 // identifier (like labels) as expressions and create them as immediates. 4592 const MCExpr *IdVal; 4593 S = Parser.getTok().getLoc(); 4594 if (getParser().parseExpression(IdVal)) 4595 return true; 4596 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4597 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4598 return false; 4599 } 4600 case AsmToken::LBrac: 4601 return parseMemory(Operands); 4602 case AsmToken::LCurly: 4603 return parseRegisterList(Operands); 4604 case AsmToken::Dollar: 4605 case AsmToken::Hash: { 4606 // #42 -> immediate. 4607 S = Parser.getTok().getLoc(); 4608 Parser.Lex(); 4609 4610 if (Parser.getTok().isNot(AsmToken::Colon)) { 4611 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4612 const MCExpr *ImmVal; 4613 if (getParser().parseExpression(ImmVal)) 4614 return true; 4615 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4616 if (CE) { 4617 int32_t Val = CE->getValue(); 4618 if (isNegative && Val == 0) 4619 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4620 } 4621 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4622 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4623 4624 // There can be a trailing '!' on operands that we want as a separate 4625 // '!' Token operand. Handle that here. For example, the compatibilty 4626 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 4627 if (Parser.getTok().is(AsmToken::Exclaim)) { 4628 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 4629 Parser.getTok().getLoc())); 4630 Parser.Lex(); // Eat exclaim token 4631 } 4632 return false; 4633 } 4634 // w/ a ':' after the '#', it's just like a plain ':'. 4635 // FALLTHROUGH 4636 } 4637 case AsmToken::Colon: { 4638 // ":lower16:" and ":upper16:" expression prefixes 4639 // FIXME: Check it's an expression prefix, 4640 // e.g. (FOO - :lower16:BAR) isn't legal. 4641 ARMMCExpr::VariantKind RefKind; 4642 if (parsePrefix(RefKind)) 4643 return true; 4644 4645 const MCExpr *SubExprVal; 4646 if (getParser().parseExpression(SubExprVal)) 4647 return true; 4648 4649 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4650 getContext()); 4651 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4652 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4653 return false; 4654 } 4655 } 4656 } 4657 4658 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4659 // :lower16: and :upper16:. 4660 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4661 RefKind = ARMMCExpr::VK_ARM_None; 4662 4663 // :lower16: and :upper16: modifiers 4664 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4665 Parser.Lex(); // Eat ':' 4666 4667 if (getLexer().isNot(AsmToken::Identifier)) { 4668 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4669 return true; 4670 } 4671 4672 StringRef IDVal = Parser.getTok().getIdentifier(); 4673 if (IDVal == "lower16") { 4674 RefKind = ARMMCExpr::VK_ARM_LO16; 4675 } else if (IDVal == "upper16") { 4676 RefKind = ARMMCExpr::VK_ARM_HI16; 4677 } else { 4678 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4679 return true; 4680 } 4681 Parser.Lex(); 4682 4683 if (getLexer().isNot(AsmToken::Colon)) { 4684 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4685 return true; 4686 } 4687 Parser.Lex(); // Eat the last ':' 4688 return false; 4689 } 4690 4691 /// \brief Given a mnemonic, split out possible predication code and carry 4692 /// setting letters to form a canonical mnemonic and flags. 4693 // 4694 // FIXME: Would be nice to autogen this. 4695 // FIXME: This is a bit of a maze of special cases. 4696 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4697 unsigned &PredicationCode, 4698 bool &CarrySetting, 4699 unsigned &ProcessorIMod, 4700 StringRef &ITMask) { 4701 PredicationCode = ARMCC::AL; 4702 CarrySetting = false; 4703 ProcessorIMod = 0; 4704 4705 // Ignore some mnemonics we know aren't predicated forms. 4706 // 4707 // FIXME: Would be nice to autogen this. 4708 if ((Mnemonic == "movs" && isThumb()) || 4709 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4710 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4711 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4712 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4713 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" || 4714 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4715 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4716 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4717 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || 4718 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || 4719 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || 4720 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel")) 4721 return Mnemonic; 4722 4723 // First, split out any predication code. Ignore mnemonics we know aren't 4724 // predicated but do have a carry-set and so weren't caught above. 4725 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4726 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4727 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4728 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4729 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4730 .Case("eq", ARMCC::EQ) 4731 .Case("ne", ARMCC::NE) 4732 .Case("hs", ARMCC::HS) 4733 .Case("cs", ARMCC::HS) 4734 .Case("lo", ARMCC::LO) 4735 .Case("cc", ARMCC::LO) 4736 .Case("mi", ARMCC::MI) 4737 .Case("pl", ARMCC::PL) 4738 .Case("vs", ARMCC::VS) 4739 .Case("vc", ARMCC::VC) 4740 .Case("hi", ARMCC::HI) 4741 .Case("ls", ARMCC::LS) 4742 .Case("ge", ARMCC::GE) 4743 .Case("lt", ARMCC::LT) 4744 .Case("gt", ARMCC::GT) 4745 .Case("le", ARMCC::LE) 4746 .Case("al", ARMCC::AL) 4747 .Default(~0U); 4748 if (CC != ~0U) { 4749 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4750 PredicationCode = CC; 4751 } 4752 } 4753 4754 // Next, determine if we have a carry setting bit. We explicitly ignore all 4755 // the instructions we know end in 's'. 4756 if (Mnemonic.endswith("s") && 4757 !(Mnemonic == "cps" || Mnemonic == "mls" || 4758 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4759 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4760 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4761 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4762 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4763 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4764 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4765 Mnemonic == "vfms" || Mnemonic == "vfnms" || 4766 (Mnemonic == "movs" && isThumb()))) { 4767 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4768 CarrySetting = true; 4769 } 4770 4771 // The "cps" instruction can have a interrupt mode operand which is glued into 4772 // the mnemonic. Check if this is the case, split it and parse the imod op 4773 if (Mnemonic.startswith("cps")) { 4774 // Split out any imod code. 4775 unsigned IMod = 4776 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4777 .Case("ie", ARM_PROC::IE) 4778 .Case("id", ARM_PROC::ID) 4779 .Default(~0U); 4780 if (IMod != ~0U) { 4781 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4782 ProcessorIMod = IMod; 4783 } 4784 } 4785 4786 // The "it" instruction has the condition mask on the end of the mnemonic. 4787 if (Mnemonic.startswith("it")) { 4788 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4789 Mnemonic = Mnemonic.slice(0, 2); 4790 } 4791 4792 return Mnemonic; 4793 } 4794 4795 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 4796 /// inclusion of carry set or predication code operands. 4797 // 4798 // FIXME: It would be nice to autogen this. 4799 void ARMAsmParser:: 4800 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 4801 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) { 4802 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4803 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4804 Mnemonic == "add" || Mnemonic == "adc" || 4805 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4806 Mnemonic == "orr" || Mnemonic == "mvn" || 4807 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4808 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4809 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4810 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4811 Mnemonic == "mla" || Mnemonic == "smlal" || 4812 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4813 CanAcceptCarrySet = true; 4814 } else 4815 CanAcceptCarrySet = false; 4816 4817 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || 4818 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || 4819 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") || 4820 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") || 4821 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" || 4822 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || 4823 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" || 4824 Mnemonic == "vrintm" || Mnemonic.startswith("aes") || 4825 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") || 4826 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) { 4827 // These mnemonics are never predicable 4828 CanAcceptPredicationCode = false; 4829 } else if (!isThumb()) { 4830 // Some instructions are only predicable in Thumb mode 4831 CanAcceptPredicationCode 4832 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && 4833 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && 4834 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" && 4835 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" && 4836 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && 4837 Mnemonic != "stc2" && Mnemonic != "stc2l" && 4838 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs"); 4839 } else if (isThumbOne()) { 4840 if (hasV6MOps()) 4841 CanAcceptPredicationCode = Mnemonic != "movs"; 4842 else 4843 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; 4844 } else 4845 CanAcceptPredicationCode = true; 4846 } 4847 4848 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4849 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4850 // FIXME: This is all horribly hacky. We really need a better way to deal 4851 // with optional operands like this in the matcher table. 4852 4853 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4854 // another does not. Specifically, the MOVW instruction does not. So we 4855 // special case it here and remove the defaulted (non-setting) cc_out 4856 // operand if that's the instruction we're trying to match. 4857 // 4858 // We do this as post-processing of the explicit operands rather than just 4859 // conditionally adding the cc_out in the first place because we need 4860 // to check the type of the parsed immediate operand. 4861 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4862 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4863 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4864 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4865 return true; 4866 4867 // Register-register 'add' for thumb does not have a cc_out operand 4868 // when there are only two register operands. 4869 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4870 static_cast<ARMOperand*>(Operands[3])->isReg() && 4871 static_cast<ARMOperand*>(Operands[4])->isReg() && 4872 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4873 return true; 4874 // Register-register 'add' for thumb does not have a cc_out operand 4875 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4876 // have to check the immediate range here since Thumb2 has a variant 4877 // that can handle a different range and has a cc_out operand. 4878 if (((isThumb() && Mnemonic == "add") || 4879 (isThumbTwo() && Mnemonic == "sub")) && 4880 Operands.size() == 6 && 4881 static_cast<ARMOperand*>(Operands[3])->isReg() && 4882 static_cast<ARMOperand*>(Operands[4])->isReg() && 4883 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4884 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4885 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 4886 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4887 return true; 4888 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4889 // imm0_4095 variant. That's the least-preferred variant when 4890 // selecting via the generic "add" mnemonic, so to know that we 4891 // should remove the cc_out operand, we have to explicitly check that 4892 // it's not one of the other variants. Ugh. 4893 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4894 Operands.size() == 6 && 4895 static_cast<ARMOperand*>(Operands[3])->isReg() && 4896 static_cast<ARMOperand*>(Operands[4])->isReg() && 4897 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4898 // Nest conditions rather than one big 'if' statement for readability. 4899 // 4900 // If both registers are low, we're in an IT block, and the immediate is 4901 // in range, we should use encoding T1 instead, which has a cc_out. 4902 if (inITBlock() && 4903 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4904 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 4905 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 4906 return false; 4907 // Check against T3. If the second register is the PC, this is an 4908 // alternate form of ADR, which uses encoding T4, so check for that too. 4909 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 4910 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 4911 return false; 4912 4913 // Otherwise, we use encoding T4, which does not have a cc_out 4914 // operand. 4915 return true; 4916 } 4917 4918 // The thumb2 multiply instruction doesn't have a CCOut register, so 4919 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 4920 // use the 16-bit encoding or not. 4921 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 4922 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4923 static_cast<ARMOperand*>(Operands[3])->isReg() && 4924 static_cast<ARMOperand*>(Operands[4])->isReg() && 4925 static_cast<ARMOperand*>(Operands[5])->isReg() && 4926 // If the registers aren't low regs, the destination reg isn't the 4927 // same as one of the source regs, or the cc_out operand is zero 4928 // outside of an IT block, we have to use the 32-bit encoding, so 4929 // remove the cc_out operand. 4930 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4931 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4932 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 4933 !inITBlock() || 4934 (static_cast<ARMOperand*>(Operands[3])->getReg() != 4935 static_cast<ARMOperand*>(Operands[5])->getReg() && 4936 static_cast<ARMOperand*>(Operands[3])->getReg() != 4937 static_cast<ARMOperand*>(Operands[4])->getReg()))) 4938 return true; 4939 4940 // Also check the 'mul' syntax variant that doesn't specify an explicit 4941 // destination register. 4942 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 4943 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4944 static_cast<ARMOperand*>(Operands[3])->isReg() && 4945 static_cast<ARMOperand*>(Operands[4])->isReg() && 4946 // If the registers aren't low regs or the cc_out operand is zero 4947 // outside of an IT block, we have to use the 32-bit encoding, so 4948 // remove the cc_out operand. 4949 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4950 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4951 !inITBlock())) 4952 return true; 4953 4954 4955 4956 // Register-register 'add/sub' for thumb does not have a cc_out operand 4957 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4958 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4959 // right, this will result in better diagnostics (which operand is off) 4960 // anyway. 4961 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4962 (Operands.size() == 5 || Operands.size() == 6) && 4963 static_cast<ARMOperand*>(Operands[3])->isReg() && 4964 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 4965 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4966 (static_cast<ARMOperand*>(Operands[4])->isImm() || 4967 (Operands.size() == 6 && 4968 static_cast<ARMOperand*>(Operands[5])->isImm()))) 4969 return true; 4970 4971 return false; 4972 } 4973 4974 bool ARMAsmParser::shouldOmitPredicateOperand( 4975 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) { 4976 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON 4977 unsigned RegIdx = 3; 4978 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") && 4979 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") { 4980 if (static_cast<ARMOperand *>(Operands[3])->isToken() && 4981 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32") 4982 RegIdx = 4; 4983 4984 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() && 4985 (ARMMCRegisterClasses[ARM::DPRRegClassID] 4986 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) || 4987 ARMMCRegisterClasses[ARM::QPRRegClassID] 4988 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()))) 4989 return true; 4990 } 4991 return false; 4992 } 4993 4994 static bool isDataTypeToken(StringRef Tok) { 4995 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 4996 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 4997 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 4998 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 4999 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 5000 Tok == ".f" || Tok == ".d"; 5001 } 5002 5003 // FIXME: This bit should probably be handled via an explicit match class 5004 // in the .td files that matches the suffix instead of having it be 5005 // a literal string token the way it is now. 5006 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 5007 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 5008 } 5009 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, 5010 unsigned VariantID); 5011 /// Parse an arm instruction mnemonic followed by its operands. 5012 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 5013 SMLoc NameLoc, 5014 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5015 // Apply mnemonic aliases before doing anything else, as the destination 5016 // mnemnonic may include suffices and we want to handle them normally. 5017 // The generic tblgen'erated code does this later, at the start of 5018 // MatchInstructionImpl(), but that's too late for aliases that include 5019 // any sort of suffix. 5020 unsigned AvailableFeatures = getAvailableFeatures(); 5021 unsigned AssemblerDialect = getParser().getAssemblerDialect(); 5022 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 5023 5024 // First check for the ARM-specific .req directive. 5025 if (Parser.getTok().is(AsmToken::Identifier) && 5026 Parser.getTok().getIdentifier() == ".req") { 5027 parseDirectiveReq(Name, NameLoc); 5028 // We always return 'error' for this, as we're done with this 5029 // statement and don't need to match the 'instruction." 5030 return true; 5031 } 5032 5033 // Create the leading tokens for the mnemonic, split by '.' characters. 5034 size_t Start = 0, Next = Name.find('.'); 5035 StringRef Mnemonic = Name.slice(Start, Next); 5036 5037 // Split out the predication code and carry setting flag from the mnemonic. 5038 unsigned PredicationCode; 5039 unsigned ProcessorIMod; 5040 bool CarrySetting; 5041 StringRef ITMask; 5042 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5043 ProcessorIMod, ITMask); 5044 5045 // In Thumb1, only the branch (B) instruction can be predicated. 5046 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 5047 Parser.eatToEndOfStatement(); 5048 return Error(NameLoc, "conditional execution not supported in Thumb1"); 5049 } 5050 5051 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5052 5053 // Handle the IT instruction ITMask. Convert it to a bitmask. This 5054 // is the mask as it will be for the IT encoding if the conditional 5055 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5056 // where the conditional bit0 is zero, the instruction post-processing 5057 // will adjust the mask accordingly. 5058 if (Mnemonic == "it") { 5059 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5060 if (ITMask.size() > 3) { 5061 Parser.eatToEndOfStatement(); 5062 return Error(Loc, "too many conditions on IT instruction"); 5063 } 5064 unsigned Mask = 8; 5065 for (unsigned i = ITMask.size(); i != 0; --i) { 5066 char pos = ITMask[i - 1]; 5067 if (pos != 't' && pos != 'e') { 5068 Parser.eatToEndOfStatement(); 5069 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5070 } 5071 Mask >>= 1; 5072 if (ITMask[i - 1] == 't') 5073 Mask |= 8; 5074 } 5075 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5076 } 5077 5078 // FIXME: This is all a pretty gross hack. We should automatically handle 5079 // optional operands like this via tblgen. 5080 5081 // Next, add the CCOut and ConditionCode operands, if needed. 5082 // 5083 // For mnemonics which can ever incorporate a carry setting bit or predication 5084 // code, our matching model involves us always generating CCOut and 5085 // ConditionCode operands to match the mnemonic "as written" and then we let 5086 // the matcher deal with finding the right instruction or generating an 5087 // appropriate error. 5088 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5089 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode); 5090 5091 // If we had a carry-set on an instruction that can't do that, issue an 5092 // error. 5093 if (!CanAcceptCarrySet && CarrySetting) { 5094 Parser.eatToEndOfStatement(); 5095 return Error(NameLoc, "instruction '" + Mnemonic + 5096 "' can not set flags, but 's' suffix specified"); 5097 } 5098 // If we had a predication code on an instruction that can't do that, issue an 5099 // error. 5100 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5101 Parser.eatToEndOfStatement(); 5102 return Error(NameLoc, "instruction '" + Mnemonic + 5103 "' is not predicable, but condition code specified"); 5104 } 5105 5106 // Add the carry setting operand, if necessary. 5107 if (CanAcceptCarrySet) { 5108 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5109 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5110 Loc)); 5111 } 5112 5113 // Add the predication code operand, if necessary. 5114 if (CanAcceptPredicationCode) { 5115 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5116 CarrySetting); 5117 Operands.push_back(ARMOperand::CreateCondCode( 5118 ARMCC::CondCodes(PredicationCode), Loc)); 5119 } 5120 5121 // Add the processor imod operand, if necessary. 5122 if (ProcessorIMod) { 5123 Operands.push_back(ARMOperand::CreateImm( 5124 MCConstantExpr::Create(ProcessorIMod, getContext()), 5125 NameLoc, NameLoc)); 5126 } 5127 5128 // Add the remaining tokens in the mnemonic. 5129 while (Next != StringRef::npos) { 5130 Start = Next; 5131 Next = Name.find('.', Start + 1); 5132 StringRef ExtraToken = Name.slice(Start, Next); 5133 5134 // Some NEON instructions have an optional datatype suffix that is 5135 // completely ignored. Check for that. 5136 if (isDataTypeToken(ExtraToken) && 5137 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5138 continue; 5139 5140 // For for ARM mode generate an error if the .n qualifier is used. 5141 if (ExtraToken == ".n" && !isThumb()) { 5142 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5143 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 5144 "arm mode"); 5145 } 5146 5147 // The .n qualifier is always discarded as that is what the tables 5148 // and matcher expect. In ARM mode the .w qualifier has no effect, 5149 // so discard it to avoid errors that can be caused by the matcher. 5150 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { 5151 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5152 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5153 } 5154 } 5155 5156 // Read the remaining operands. 5157 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5158 // Read the first operand. 5159 if (parseOperand(Operands, Mnemonic)) { 5160 Parser.eatToEndOfStatement(); 5161 return true; 5162 } 5163 5164 while (getLexer().is(AsmToken::Comma)) { 5165 Parser.Lex(); // Eat the comma. 5166 5167 // Parse and remember the operand. 5168 if (parseOperand(Operands, Mnemonic)) { 5169 Parser.eatToEndOfStatement(); 5170 return true; 5171 } 5172 } 5173 } 5174 5175 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5176 SMLoc Loc = getLexer().getLoc(); 5177 Parser.eatToEndOfStatement(); 5178 return Error(Loc, "unexpected token in argument list"); 5179 } 5180 5181 Parser.Lex(); // Consume the EndOfStatement 5182 5183 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5184 // do and don't have a cc_out optional-def operand. With some spot-checks 5185 // of the operand list, we can figure out which variant we're trying to 5186 // parse and adjust accordingly before actually matching. We shouldn't ever 5187 // try to remove a cc_out operand that was explicitly set on the the 5188 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5189 // table driven matcher doesn't fit well with the ARM instruction set. 5190 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5191 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5192 Operands.erase(Operands.begin() + 1); 5193 delete Op; 5194 } 5195 5196 // Some instructions have the same mnemonic, but don't always 5197 // have a predicate. Distinguish them here and delete the 5198 // predicate if needed. 5199 if (shouldOmitPredicateOperand(Mnemonic, Operands)) { 5200 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5201 Operands.erase(Operands.begin() + 1); 5202 delete Op; 5203 } 5204 5205 // ARM mode 'blx' need special handling, as the register operand version 5206 // is predicable, but the label operand version is not. So, we can't rely 5207 // on the Mnemonic based checking to correctly figure out when to put 5208 // a k_CondCode operand in the list. If we're trying to match the label 5209 // version, remove the k_CondCode operand here. 5210 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5211 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5212 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5213 Operands.erase(Operands.begin() + 1); 5214 delete Op; 5215 } 5216 5217 // Adjust operands of ldrexd/strexd to MCK_GPRPair. 5218 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 5219 // a single GPRPair reg operand is used in the .td file to replace the two 5220 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 5221 // expressed as a GPRPair, so we have to manually merge them. 5222 // FIXME: We would really like to be able to tablegen'erate this. 5223 if (!isThumb() && Operands.size() > 4 && 5224 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || 5225 Mnemonic == "stlexd")) { 5226 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); 5227 unsigned Idx = isLoad ? 2 : 3; 5228 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]); 5229 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]); 5230 5231 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 5232 // Adjust only if Op1 and Op2 are GPRs. 5233 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) && 5234 MRC.contains(Op2->getReg())) { 5235 unsigned Reg1 = Op1->getReg(); 5236 unsigned Reg2 = Op2->getReg(); 5237 unsigned Rt = MRI->getEncodingValue(Reg1); 5238 unsigned Rt2 = MRI->getEncodingValue(Reg2); 5239 5240 // Rt2 must be Rt + 1 and Rt must be even. 5241 if (Rt + 1 != Rt2 || (Rt & 1)) { 5242 Error(Op2->getStartLoc(), isLoad ? 5243 "destination operands must be sequential" : 5244 "source operands must be sequential"); 5245 return true; 5246 } 5247 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 5248 &(MRI->getRegClass(ARM::GPRPairRegClassID))); 5249 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2); 5250 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg( 5251 NewReg, Op1->getStartLoc(), Op2->getEndLoc())); 5252 delete Op1; 5253 delete Op2; 5254 } 5255 } 5256 5257 // FIXME: As said above, this is all a pretty gross hack. This instruction 5258 // does not fit with other "subs" and tblgen. 5259 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction 5260 // so the Mnemonic is the original name "subs" and delete the predicate 5261 // operand so it will match the table entry. 5262 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && 5263 static_cast<ARMOperand*>(Operands[3])->isReg() && 5264 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC && 5265 static_cast<ARMOperand*>(Operands[4])->isReg() && 5266 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR && 5267 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5268 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]); 5269 Operands.erase(Operands.begin()); 5270 delete Op0; 5271 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc)); 5272 5273 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]); 5274 Operands.erase(Operands.begin() + 1); 5275 delete Op1; 5276 } 5277 return false; 5278 } 5279 5280 // Validate context-sensitive operand constraints. 5281 5282 // return 'true' if register list contains non-low GPR registers, 5283 // 'false' otherwise. If Reg is in the register list or is HiReg, set 5284 // 'containsReg' to true. 5285 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5286 unsigned HiReg, bool &containsReg) { 5287 containsReg = false; 5288 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5289 unsigned OpReg = Inst.getOperand(i).getReg(); 5290 if (OpReg == Reg) 5291 containsReg = true; 5292 // Anything other than a low register isn't legal here. 5293 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5294 return true; 5295 } 5296 return false; 5297 } 5298 5299 // Check if the specified regisgter is in the register list of the inst, 5300 // starting at the indicated operand number. 5301 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5302 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5303 unsigned OpReg = Inst.getOperand(i).getReg(); 5304 if (OpReg == Reg) 5305 return true; 5306 } 5307 return false; 5308 } 5309 5310 // Return true if instruction has the interesting property of being 5311 // allowed in IT blocks, but not being predicable. 5312 static bool instIsBreakpoint(const MCInst &Inst) { 5313 return Inst.getOpcode() == ARM::tBKPT || 5314 Inst.getOpcode() == ARM::BKPT || 5315 Inst.getOpcode() == ARM::tHLT || 5316 Inst.getOpcode() == ARM::HLT; 5317 5318 } 5319 5320 // FIXME: We would really like to be able to tablegen'erate this. 5321 bool ARMAsmParser:: 5322 validateInstruction(MCInst &Inst, 5323 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5324 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 5325 SMLoc Loc = Operands[0]->getStartLoc(); 5326 5327 // Check the IT block state first. 5328 // NOTE: BKPT and HLT instructions have the interesting property of being 5329 // allowed in IT blocks, but not being predicable. They just always execute. 5330 if (inITBlock() && !instIsBreakpoint(Inst)) { 5331 unsigned Bit = 1; 5332 if (ITState.FirstCond) 5333 ITState.FirstCond = false; 5334 else 5335 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5336 // The instruction must be predicable. 5337 if (!MCID.isPredicable()) 5338 return Error(Loc, "instructions in IT block must be predicable"); 5339 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5340 unsigned ITCond = Bit ? ITState.Cond : 5341 ARMCC::getOppositeCondition(ITState.Cond); 5342 if (Cond != ITCond) { 5343 // Find the condition code Operand to get its SMLoc information. 5344 SMLoc CondLoc; 5345 for (unsigned I = 1; I < Operands.size(); ++I) 5346 if (static_cast<ARMOperand*>(Operands[I])->isCondCode()) 5347 CondLoc = Operands[I]->getStartLoc(); 5348 return Error(CondLoc, "incorrect condition in IT block; got '" + 5349 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5350 "', but expected '" + 5351 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5352 } 5353 // Check for non-'al' condition codes outside of the IT block. 5354 } else if (isThumbTwo() && MCID.isPredicable() && 5355 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5356 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && 5357 Inst.getOpcode() != ARM::t2Bcc) 5358 return Error(Loc, "predicated instructions must be in IT block"); 5359 5360 const unsigned Opcode = Inst.getOpcode(); 5361 switch (Opcode) { 5362 case ARM::LDRD: 5363 case ARM::LDRD_PRE: 5364 case ARM::LDRD_POST: { 5365 const unsigned RtReg = Inst.getOperand(0).getReg(); 5366 5367 // Rt can't be R14. 5368 if (RtReg == ARM::LR) 5369 return Error(Operands[3]->getStartLoc(), 5370 "Rt can't be R14"); 5371 5372 const unsigned Rt = MRI->getEncodingValue(RtReg); 5373 // Rt must be even-numbered. 5374 if ((Rt & 1) == 1) 5375 return Error(Operands[3]->getStartLoc(), 5376 "Rt must be even-numbered"); 5377 5378 // Rt2 must be Rt + 1. 5379 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5380 if (Rt2 != Rt + 1) 5381 return Error(Operands[3]->getStartLoc(), 5382 "destination operands must be sequential"); 5383 5384 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) { 5385 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 5386 // For addressing modes with writeback, the base register needs to be 5387 // different from the destination registers. 5388 if (Rn == Rt || Rn == Rt2) 5389 return Error(Operands[3]->getStartLoc(), 5390 "base register needs to be different from destination " 5391 "registers"); 5392 } 5393 5394 return false; 5395 } 5396 case ARM::t2LDRDi8: 5397 case ARM::t2LDRD_PRE: 5398 case ARM::t2LDRD_POST: { 5399 // Rt2 must be different from Rt. 5400 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5401 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5402 if (Rt2 == Rt) 5403 return Error(Operands[3]->getStartLoc(), 5404 "destination operands can't be identical"); 5405 return false; 5406 } 5407 case ARM::STRD: { 5408 // Rt2 must be Rt + 1. 5409 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5410 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5411 if (Rt2 != Rt + 1) 5412 return Error(Operands[3]->getStartLoc(), 5413 "source operands must be sequential"); 5414 return false; 5415 } 5416 case ARM::STRD_PRE: 5417 case ARM::STRD_POST: { 5418 // Rt2 must be Rt + 1. 5419 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5420 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5421 if (Rt2 != Rt + 1) 5422 return Error(Operands[3]->getStartLoc(), 5423 "source operands must be sequential"); 5424 return false; 5425 } 5426 case ARM::SBFX: 5427 case ARM::UBFX: { 5428 // Width must be in range [1, 32-lsb]. 5429 unsigned LSB = Inst.getOperand(2).getImm(); 5430 unsigned Widthm1 = Inst.getOperand(3).getImm(); 5431 if (Widthm1 >= 32 - LSB) 5432 return Error(Operands[5]->getStartLoc(), 5433 "bitfield width must be in range [1,32-lsb]"); 5434 return false; 5435 } 5436 // Notionally handles ARM::tLDMIA_UPD too. 5437 case ARM::tLDMIA: { 5438 // If we're parsing Thumb2, the .w variant is available and handles 5439 // most cases that are normally illegal for a Thumb1 LDM instruction. 5440 // We'll make the transformation in processInstruction() if necessary. 5441 // 5442 // Thumb LDM instructions are writeback iff the base register is not 5443 // in the register list. 5444 unsigned Rn = Inst.getOperand(0).getReg(); 5445 bool HasWritebackToken = 5446 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5447 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5448 bool ListContainsBase; 5449 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo()) 5450 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), 5451 "registers must be in range r0-r7"); 5452 // If we should have writeback, then there should be a '!' token. 5453 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo()) 5454 return Error(Operands[2]->getStartLoc(), 5455 "writeback operator '!' expected"); 5456 // If we should not have writeback, there must not be a '!'. This is 5457 // true even for the 32-bit wide encodings. 5458 if (ListContainsBase && HasWritebackToken) 5459 return Error(Operands[3]->getStartLoc(), 5460 "writeback operator '!' not allowed when base register " 5461 "in register list"); 5462 5463 break; 5464 } 5465 case ARM::LDMIA_UPD: 5466 case ARM::LDMDB_UPD: 5467 case ARM::LDMIB_UPD: 5468 case ARM::LDMDA_UPD: 5469 // ARM variants loading and updating the same register are only officially 5470 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before. 5471 if (!hasV7Ops()) 5472 break; 5473 // Fallthrough 5474 case ARM::t2LDMIA_UPD: 5475 case ARM::t2LDMDB_UPD: 5476 case ARM::t2STMIA_UPD: 5477 case ARM::t2STMDB_UPD: { 5478 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5479 return Error(Operands.back()->getStartLoc(), 5480 "writeback register not allowed in register list"); 5481 break; 5482 } 5483 case ARM::tMUL: { 5484 // The second source operand must be the same register as the destination 5485 // operand. 5486 // 5487 // In this case, we must directly check the parsed operands because the 5488 // cvtThumbMultiply() function is written in such a way that it guarantees 5489 // this first statement is always true for the new Inst. Essentially, the 5490 // destination is unconditionally copied into the second source operand 5491 // without checking to see if it matches what we actually parsed. 5492 if (Operands.size() == 6 && 5493 (((ARMOperand*)Operands[3])->getReg() != 5494 ((ARMOperand*)Operands[5])->getReg()) && 5495 (((ARMOperand*)Operands[3])->getReg() != 5496 ((ARMOperand*)Operands[4])->getReg())) { 5497 return Error(Operands[3]->getStartLoc(), 5498 "destination register must match source register"); 5499 } 5500 break; 5501 } 5502 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5503 // so only issue a diagnostic for thumb1. The instructions will be 5504 // switched to the t2 encodings in processInstruction() if necessary. 5505 case ARM::tPOP: { 5506 bool ListContainsBase; 5507 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && 5508 !isThumbTwo()) 5509 return Error(Operands[2]->getStartLoc(), 5510 "registers must be in range r0-r7 or pc"); 5511 break; 5512 } 5513 case ARM::tPUSH: { 5514 bool ListContainsBase; 5515 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && 5516 !isThumbTwo()) 5517 return Error(Operands[2]->getStartLoc(), 5518 "registers must be in range r0-r7 or lr"); 5519 break; 5520 } 5521 case ARM::tSTMIA_UPD: { 5522 bool ListContainsBase, InvalidLowList; 5523 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), 5524 0, ListContainsBase); 5525 if (InvalidLowList && !isThumbTwo()) 5526 return Error(Operands[4]->getStartLoc(), 5527 "registers must be in range r0-r7"); 5528 5529 // This would be converted to a 32-bit stm, but that's not valid if the 5530 // writeback register is in the list. 5531 if (InvalidLowList && ListContainsBase) 5532 return Error(Operands[4]->getStartLoc(), 5533 "writeback operator '!' not allowed when base register " 5534 "in register list"); 5535 break; 5536 } 5537 case ARM::tADDrSP: { 5538 // If the non-SP source operand and the destination operand are not the 5539 // same, we need thumb2 (for the wide encoding), or we have an error. 5540 if (!isThumbTwo() && 5541 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5542 return Error(Operands[4]->getStartLoc(), 5543 "source register must be the same as destination"); 5544 } 5545 break; 5546 } 5547 // Final range checking for Thumb unconditional branch instructions. 5548 case ARM::tB: 5549 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>()) 5550 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 5551 break; 5552 case ARM::t2B: { 5553 int op = (Operands[2]->isImm()) ? 2 : 3; 5554 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>()) 5555 return Error(Operands[op]->getStartLoc(), "branch target out of range"); 5556 break; 5557 } 5558 // Final range checking for Thumb conditional branch instructions. 5559 case ARM::tBcc: 5560 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>()) 5561 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 5562 break; 5563 case ARM::t2Bcc: { 5564 int Op = (Operands[2]->isImm()) ? 2 : 3; 5565 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>()) 5566 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); 5567 break; 5568 } 5569 } 5570 5571 return false; 5572 } 5573 5574 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5575 switch(Opc) { 5576 default: llvm_unreachable("unexpected opcode!"); 5577 // VST1LN 5578 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5579 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5580 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5581 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5582 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5583 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5584 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5585 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5586 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5587 5588 // VST2LN 5589 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5590 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5591 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5592 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5593 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5594 5595 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5596 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5597 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5598 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5599 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5600 5601 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5602 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5603 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5604 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5605 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5606 5607 // VST3LN 5608 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5609 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5610 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5611 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5612 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5613 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5614 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5615 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5616 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5617 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5618 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5619 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5620 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5621 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5622 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5623 5624 // VST3 5625 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5626 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5627 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5628 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5629 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5630 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5631 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5632 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5633 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5634 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5635 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5636 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5637 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5638 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5639 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5640 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5641 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5642 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5643 5644 // VST4LN 5645 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5646 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5647 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5648 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5649 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5650 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5651 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5652 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5653 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5654 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5655 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5656 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5657 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5658 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5659 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5660 5661 // VST4 5662 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5663 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5664 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5665 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5666 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5667 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5668 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5669 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5670 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5671 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5672 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5673 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5674 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5675 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5676 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5677 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5678 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5679 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5680 } 5681 } 5682 5683 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5684 switch(Opc) { 5685 default: llvm_unreachable("unexpected opcode!"); 5686 // VLD1LN 5687 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5688 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5689 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5690 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5691 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5692 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5693 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5694 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5695 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5696 5697 // VLD2LN 5698 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5699 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5700 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5701 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5702 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5703 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5704 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5705 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5706 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5707 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5708 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5709 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5710 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5711 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5712 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5713 5714 // VLD3DUP 5715 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5716 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5717 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5718 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5719 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5720 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5721 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5722 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5723 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5724 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5725 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5726 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5727 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5728 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5729 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5730 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5731 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5732 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5733 5734 // VLD3LN 5735 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5736 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5737 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5738 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5739 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5740 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5741 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5742 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5743 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5744 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5745 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5746 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5747 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5748 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5749 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5750 5751 // VLD3 5752 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5753 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5754 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5755 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5756 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5757 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5758 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5759 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5760 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5761 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5762 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5763 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5764 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5765 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5766 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5767 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5768 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5769 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5770 5771 // VLD4LN 5772 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5773 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5774 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5775 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5776 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5777 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5778 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5779 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5780 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5781 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5782 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5783 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5784 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5785 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5786 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5787 5788 // VLD4DUP 5789 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5790 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5791 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5792 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5793 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5794 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5795 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5796 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5797 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5798 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5799 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5800 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5801 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5802 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5803 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5804 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5805 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5806 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5807 5808 // VLD4 5809 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5810 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5811 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5812 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5813 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5814 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5815 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5816 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5817 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5818 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5819 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5820 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5821 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 5822 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 5823 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 5824 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 5825 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 5826 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 5827 } 5828 } 5829 5830 bool ARMAsmParser:: 5831 processInstruction(MCInst &Inst, 5832 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5833 switch (Inst.getOpcode()) { 5834 // Alias for alternate form of 'ADR Rd, #imm' instruction. 5835 case ARM::ADDri: { 5836 if (Inst.getOperand(1).getReg() != ARM::PC || 5837 Inst.getOperand(5).getReg() != 0) 5838 return false; 5839 MCInst TmpInst; 5840 TmpInst.setOpcode(ARM::ADR); 5841 TmpInst.addOperand(Inst.getOperand(0)); 5842 TmpInst.addOperand(Inst.getOperand(2)); 5843 TmpInst.addOperand(Inst.getOperand(3)); 5844 TmpInst.addOperand(Inst.getOperand(4)); 5845 Inst = TmpInst; 5846 return true; 5847 } 5848 // Aliases for alternate PC+imm syntax of LDR instructions. 5849 case ARM::t2LDRpcrel: 5850 // Select the narrow version if the immediate will fit. 5851 if (Inst.getOperand(1).getImm() > 0 && 5852 Inst.getOperand(1).getImm() <= 0xff && 5853 !(static_cast<ARMOperand*>(Operands[2])->isToken() && 5854 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w")) 5855 Inst.setOpcode(ARM::tLDRpci); 5856 else 5857 Inst.setOpcode(ARM::t2LDRpci); 5858 return true; 5859 case ARM::t2LDRBpcrel: 5860 Inst.setOpcode(ARM::t2LDRBpci); 5861 return true; 5862 case ARM::t2LDRHpcrel: 5863 Inst.setOpcode(ARM::t2LDRHpci); 5864 return true; 5865 case ARM::t2LDRSBpcrel: 5866 Inst.setOpcode(ARM::t2LDRSBpci); 5867 return true; 5868 case ARM::t2LDRSHpcrel: 5869 Inst.setOpcode(ARM::t2LDRSHpci); 5870 return true; 5871 // Handle NEON VST complex aliases. 5872 case ARM::VST1LNdWB_register_Asm_8: 5873 case ARM::VST1LNdWB_register_Asm_16: 5874 case ARM::VST1LNdWB_register_Asm_32: { 5875 MCInst TmpInst; 5876 // Shuffle the operands around so the lane index operand is in the 5877 // right place. 5878 unsigned Spacing; 5879 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5880 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5881 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5882 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5883 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5884 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5885 TmpInst.addOperand(Inst.getOperand(1)); // lane 5886 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5887 TmpInst.addOperand(Inst.getOperand(6)); 5888 Inst = TmpInst; 5889 return true; 5890 } 5891 5892 case ARM::VST2LNdWB_register_Asm_8: 5893 case ARM::VST2LNdWB_register_Asm_16: 5894 case ARM::VST2LNdWB_register_Asm_32: 5895 case ARM::VST2LNqWB_register_Asm_16: 5896 case ARM::VST2LNqWB_register_Asm_32: { 5897 MCInst TmpInst; 5898 // Shuffle the operands around so the lane index operand is in the 5899 // right place. 5900 unsigned Spacing; 5901 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5902 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5903 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5904 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5905 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5906 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5907 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5908 Spacing)); 5909 TmpInst.addOperand(Inst.getOperand(1)); // lane 5910 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5911 TmpInst.addOperand(Inst.getOperand(6)); 5912 Inst = TmpInst; 5913 return true; 5914 } 5915 5916 case ARM::VST3LNdWB_register_Asm_8: 5917 case ARM::VST3LNdWB_register_Asm_16: 5918 case ARM::VST3LNdWB_register_Asm_32: 5919 case ARM::VST3LNqWB_register_Asm_16: 5920 case ARM::VST3LNqWB_register_Asm_32: { 5921 MCInst TmpInst; 5922 // Shuffle the operands around so the lane index operand is in the 5923 // right place. 5924 unsigned Spacing; 5925 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5926 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5927 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5928 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5929 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5930 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5931 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5932 Spacing)); 5933 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5934 Spacing * 2)); 5935 TmpInst.addOperand(Inst.getOperand(1)); // lane 5936 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5937 TmpInst.addOperand(Inst.getOperand(6)); 5938 Inst = TmpInst; 5939 return true; 5940 } 5941 5942 case ARM::VST4LNdWB_register_Asm_8: 5943 case ARM::VST4LNdWB_register_Asm_16: 5944 case ARM::VST4LNdWB_register_Asm_32: 5945 case ARM::VST4LNqWB_register_Asm_16: 5946 case ARM::VST4LNqWB_register_Asm_32: { 5947 MCInst TmpInst; 5948 // Shuffle the operands around so the lane index operand is in the 5949 // right place. 5950 unsigned Spacing; 5951 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5952 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5953 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5954 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5955 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5956 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5957 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5958 Spacing)); 5959 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5960 Spacing * 2)); 5961 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5962 Spacing * 3)); 5963 TmpInst.addOperand(Inst.getOperand(1)); // lane 5964 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5965 TmpInst.addOperand(Inst.getOperand(6)); 5966 Inst = TmpInst; 5967 return true; 5968 } 5969 5970 case ARM::VST1LNdWB_fixed_Asm_8: 5971 case ARM::VST1LNdWB_fixed_Asm_16: 5972 case ARM::VST1LNdWB_fixed_Asm_32: { 5973 MCInst TmpInst; 5974 // Shuffle the operands around so the lane index operand is in the 5975 // right place. 5976 unsigned Spacing; 5977 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5978 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5979 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5980 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5981 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5982 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5983 TmpInst.addOperand(Inst.getOperand(1)); // lane 5984 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5985 TmpInst.addOperand(Inst.getOperand(5)); 5986 Inst = TmpInst; 5987 return true; 5988 } 5989 5990 case ARM::VST2LNdWB_fixed_Asm_8: 5991 case ARM::VST2LNdWB_fixed_Asm_16: 5992 case ARM::VST2LNdWB_fixed_Asm_32: 5993 case ARM::VST2LNqWB_fixed_Asm_16: 5994 case ARM::VST2LNqWB_fixed_Asm_32: { 5995 MCInst TmpInst; 5996 // Shuffle the operands around so the lane index operand is in the 5997 // right place. 5998 unsigned Spacing; 5999 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6000 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6001 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6002 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6003 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6004 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6005 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6006 Spacing)); 6007 TmpInst.addOperand(Inst.getOperand(1)); // lane 6008 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6009 TmpInst.addOperand(Inst.getOperand(5)); 6010 Inst = TmpInst; 6011 return true; 6012 } 6013 6014 case ARM::VST3LNdWB_fixed_Asm_8: 6015 case ARM::VST3LNdWB_fixed_Asm_16: 6016 case ARM::VST3LNdWB_fixed_Asm_32: 6017 case ARM::VST3LNqWB_fixed_Asm_16: 6018 case ARM::VST3LNqWB_fixed_Asm_32: { 6019 MCInst TmpInst; 6020 // Shuffle the operands around so the lane index operand is in the 6021 // right place. 6022 unsigned Spacing; 6023 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6024 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6025 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6026 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6027 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6028 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6029 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6030 Spacing)); 6031 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6032 Spacing * 2)); 6033 TmpInst.addOperand(Inst.getOperand(1)); // lane 6034 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6035 TmpInst.addOperand(Inst.getOperand(5)); 6036 Inst = TmpInst; 6037 return true; 6038 } 6039 6040 case ARM::VST4LNdWB_fixed_Asm_8: 6041 case ARM::VST4LNdWB_fixed_Asm_16: 6042 case ARM::VST4LNdWB_fixed_Asm_32: 6043 case ARM::VST4LNqWB_fixed_Asm_16: 6044 case ARM::VST4LNqWB_fixed_Asm_32: { 6045 MCInst TmpInst; 6046 // Shuffle the operands around so the lane index operand is in the 6047 // right place. 6048 unsigned Spacing; 6049 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6050 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6051 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6052 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6053 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6054 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6055 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6056 Spacing)); 6057 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6058 Spacing * 2)); 6059 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6060 Spacing * 3)); 6061 TmpInst.addOperand(Inst.getOperand(1)); // lane 6062 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6063 TmpInst.addOperand(Inst.getOperand(5)); 6064 Inst = TmpInst; 6065 return true; 6066 } 6067 6068 case ARM::VST1LNdAsm_8: 6069 case ARM::VST1LNdAsm_16: 6070 case ARM::VST1LNdAsm_32: { 6071 MCInst TmpInst; 6072 // Shuffle the operands around so the lane index operand is in the 6073 // right place. 6074 unsigned Spacing; 6075 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6076 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6077 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6078 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6079 TmpInst.addOperand(Inst.getOperand(1)); // lane 6080 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6081 TmpInst.addOperand(Inst.getOperand(5)); 6082 Inst = TmpInst; 6083 return true; 6084 } 6085 6086 case ARM::VST2LNdAsm_8: 6087 case ARM::VST2LNdAsm_16: 6088 case ARM::VST2LNdAsm_32: 6089 case ARM::VST2LNqAsm_16: 6090 case ARM::VST2LNqAsm_32: { 6091 MCInst TmpInst; 6092 // Shuffle the operands around so the lane index operand is in the 6093 // right place. 6094 unsigned Spacing; 6095 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6096 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6097 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6098 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6099 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6100 Spacing)); 6101 TmpInst.addOperand(Inst.getOperand(1)); // lane 6102 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6103 TmpInst.addOperand(Inst.getOperand(5)); 6104 Inst = TmpInst; 6105 return true; 6106 } 6107 6108 case ARM::VST3LNdAsm_8: 6109 case ARM::VST3LNdAsm_16: 6110 case ARM::VST3LNdAsm_32: 6111 case ARM::VST3LNqAsm_16: 6112 case ARM::VST3LNqAsm_32: { 6113 MCInst TmpInst; 6114 // Shuffle the operands around so the lane index operand is in the 6115 // right place. 6116 unsigned Spacing; 6117 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6118 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6119 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6120 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6121 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6122 Spacing)); 6123 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6124 Spacing * 2)); 6125 TmpInst.addOperand(Inst.getOperand(1)); // lane 6126 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6127 TmpInst.addOperand(Inst.getOperand(5)); 6128 Inst = TmpInst; 6129 return true; 6130 } 6131 6132 case ARM::VST4LNdAsm_8: 6133 case ARM::VST4LNdAsm_16: 6134 case ARM::VST4LNdAsm_32: 6135 case ARM::VST4LNqAsm_16: 6136 case ARM::VST4LNqAsm_32: { 6137 MCInst TmpInst; 6138 // Shuffle the operands around so the lane index operand is in the 6139 // right place. 6140 unsigned Spacing; 6141 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6142 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6143 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6144 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6145 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6146 Spacing)); 6147 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6148 Spacing * 2)); 6149 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6150 Spacing * 3)); 6151 TmpInst.addOperand(Inst.getOperand(1)); // lane 6152 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6153 TmpInst.addOperand(Inst.getOperand(5)); 6154 Inst = TmpInst; 6155 return true; 6156 } 6157 6158 // Handle NEON VLD complex aliases. 6159 case ARM::VLD1LNdWB_register_Asm_8: 6160 case ARM::VLD1LNdWB_register_Asm_16: 6161 case ARM::VLD1LNdWB_register_Asm_32: { 6162 MCInst TmpInst; 6163 // Shuffle the operands around so the lane index operand is in the 6164 // right place. 6165 unsigned Spacing; 6166 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6167 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6168 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6169 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6170 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6171 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6172 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6173 TmpInst.addOperand(Inst.getOperand(1)); // lane 6174 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6175 TmpInst.addOperand(Inst.getOperand(6)); 6176 Inst = TmpInst; 6177 return true; 6178 } 6179 6180 case ARM::VLD2LNdWB_register_Asm_8: 6181 case ARM::VLD2LNdWB_register_Asm_16: 6182 case ARM::VLD2LNdWB_register_Asm_32: 6183 case ARM::VLD2LNqWB_register_Asm_16: 6184 case ARM::VLD2LNqWB_register_Asm_32: { 6185 MCInst TmpInst; 6186 // Shuffle the operands around so the lane index operand is in the 6187 // right place. 6188 unsigned Spacing; 6189 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6190 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6191 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6192 Spacing)); 6193 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6194 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6195 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6196 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6197 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6198 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6199 Spacing)); 6200 TmpInst.addOperand(Inst.getOperand(1)); // lane 6201 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6202 TmpInst.addOperand(Inst.getOperand(6)); 6203 Inst = TmpInst; 6204 return true; 6205 } 6206 6207 case ARM::VLD3LNdWB_register_Asm_8: 6208 case ARM::VLD3LNdWB_register_Asm_16: 6209 case ARM::VLD3LNdWB_register_Asm_32: 6210 case ARM::VLD3LNqWB_register_Asm_16: 6211 case ARM::VLD3LNqWB_register_Asm_32: { 6212 MCInst TmpInst; 6213 // Shuffle the operands around so the lane index operand is in the 6214 // right place. 6215 unsigned Spacing; 6216 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6217 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6218 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6219 Spacing)); 6220 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6221 Spacing * 2)); 6222 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6223 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6224 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6225 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6226 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6227 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6228 Spacing)); 6229 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6230 Spacing * 2)); 6231 TmpInst.addOperand(Inst.getOperand(1)); // lane 6232 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6233 TmpInst.addOperand(Inst.getOperand(6)); 6234 Inst = TmpInst; 6235 return true; 6236 } 6237 6238 case ARM::VLD4LNdWB_register_Asm_8: 6239 case ARM::VLD4LNdWB_register_Asm_16: 6240 case ARM::VLD4LNdWB_register_Asm_32: 6241 case ARM::VLD4LNqWB_register_Asm_16: 6242 case ARM::VLD4LNqWB_register_Asm_32: { 6243 MCInst TmpInst; 6244 // Shuffle the operands around so the lane index operand is in the 6245 // right place. 6246 unsigned Spacing; 6247 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6248 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6249 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6250 Spacing)); 6251 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6252 Spacing * 2)); 6253 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6254 Spacing * 3)); 6255 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6256 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6257 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6258 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6259 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6260 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6261 Spacing)); 6262 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6263 Spacing * 2)); 6264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6265 Spacing * 3)); 6266 TmpInst.addOperand(Inst.getOperand(1)); // lane 6267 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6268 TmpInst.addOperand(Inst.getOperand(6)); 6269 Inst = TmpInst; 6270 return true; 6271 } 6272 6273 case ARM::VLD1LNdWB_fixed_Asm_8: 6274 case ARM::VLD1LNdWB_fixed_Asm_16: 6275 case ARM::VLD1LNdWB_fixed_Asm_32: { 6276 MCInst TmpInst; 6277 // Shuffle the operands around so the lane index operand is in the 6278 // right place. 6279 unsigned Spacing; 6280 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6281 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6282 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6283 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6284 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6285 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6286 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6287 TmpInst.addOperand(Inst.getOperand(1)); // lane 6288 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6289 TmpInst.addOperand(Inst.getOperand(5)); 6290 Inst = TmpInst; 6291 return true; 6292 } 6293 6294 case ARM::VLD2LNdWB_fixed_Asm_8: 6295 case ARM::VLD2LNdWB_fixed_Asm_16: 6296 case ARM::VLD2LNdWB_fixed_Asm_32: 6297 case ARM::VLD2LNqWB_fixed_Asm_16: 6298 case ARM::VLD2LNqWB_fixed_Asm_32: { 6299 MCInst TmpInst; 6300 // Shuffle the operands around so the lane index operand is in the 6301 // right place. 6302 unsigned Spacing; 6303 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6304 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6306 Spacing)); 6307 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6308 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6309 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6310 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6311 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6312 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6313 Spacing)); 6314 TmpInst.addOperand(Inst.getOperand(1)); // lane 6315 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6316 TmpInst.addOperand(Inst.getOperand(5)); 6317 Inst = TmpInst; 6318 return true; 6319 } 6320 6321 case ARM::VLD3LNdWB_fixed_Asm_8: 6322 case ARM::VLD3LNdWB_fixed_Asm_16: 6323 case ARM::VLD3LNdWB_fixed_Asm_32: 6324 case ARM::VLD3LNqWB_fixed_Asm_16: 6325 case ARM::VLD3LNqWB_fixed_Asm_32: { 6326 MCInst TmpInst; 6327 // Shuffle the operands around so the lane index operand is in the 6328 // right place. 6329 unsigned Spacing; 6330 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6331 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6332 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6333 Spacing)); 6334 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6335 Spacing * 2)); 6336 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6337 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6338 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6339 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6340 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6341 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6342 Spacing)); 6343 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6344 Spacing * 2)); 6345 TmpInst.addOperand(Inst.getOperand(1)); // lane 6346 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6347 TmpInst.addOperand(Inst.getOperand(5)); 6348 Inst = TmpInst; 6349 return true; 6350 } 6351 6352 case ARM::VLD4LNdWB_fixed_Asm_8: 6353 case ARM::VLD4LNdWB_fixed_Asm_16: 6354 case ARM::VLD4LNdWB_fixed_Asm_32: 6355 case ARM::VLD4LNqWB_fixed_Asm_16: 6356 case ARM::VLD4LNqWB_fixed_Asm_32: { 6357 MCInst TmpInst; 6358 // Shuffle the operands around so the lane index operand is in the 6359 // right place. 6360 unsigned Spacing; 6361 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6362 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6363 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6364 Spacing)); 6365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6366 Spacing * 2)); 6367 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6368 Spacing * 3)); 6369 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6370 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6371 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6372 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6373 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6374 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6375 Spacing)); 6376 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6377 Spacing * 2)); 6378 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6379 Spacing * 3)); 6380 TmpInst.addOperand(Inst.getOperand(1)); // lane 6381 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6382 TmpInst.addOperand(Inst.getOperand(5)); 6383 Inst = TmpInst; 6384 return true; 6385 } 6386 6387 case ARM::VLD1LNdAsm_8: 6388 case ARM::VLD1LNdAsm_16: 6389 case ARM::VLD1LNdAsm_32: { 6390 MCInst TmpInst; 6391 // Shuffle the operands around so the lane index operand is in the 6392 // right place. 6393 unsigned Spacing; 6394 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6395 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6396 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6397 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6398 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6399 TmpInst.addOperand(Inst.getOperand(1)); // lane 6400 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6401 TmpInst.addOperand(Inst.getOperand(5)); 6402 Inst = TmpInst; 6403 return true; 6404 } 6405 6406 case ARM::VLD2LNdAsm_8: 6407 case ARM::VLD2LNdAsm_16: 6408 case ARM::VLD2LNdAsm_32: 6409 case ARM::VLD2LNqAsm_16: 6410 case ARM::VLD2LNqAsm_32: { 6411 MCInst TmpInst; 6412 // Shuffle the operands around so the lane index operand is in the 6413 // right place. 6414 unsigned Spacing; 6415 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6416 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6417 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6418 Spacing)); 6419 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6420 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6421 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6422 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6423 Spacing)); 6424 TmpInst.addOperand(Inst.getOperand(1)); // lane 6425 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6426 TmpInst.addOperand(Inst.getOperand(5)); 6427 Inst = TmpInst; 6428 return true; 6429 } 6430 6431 case ARM::VLD3LNdAsm_8: 6432 case ARM::VLD3LNdAsm_16: 6433 case ARM::VLD3LNdAsm_32: 6434 case ARM::VLD3LNqAsm_16: 6435 case ARM::VLD3LNqAsm_32: { 6436 MCInst TmpInst; 6437 // Shuffle the operands around so the lane index operand is in the 6438 // right place. 6439 unsigned Spacing; 6440 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6441 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6442 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6443 Spacing)); 6444 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6445 Spacing * 2)); 6446 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6447 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6448 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6449 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6450 Spacing)); 6451 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6452 Spacing * 2)); 6453 TmpInst.addOperand(Inst.getOperand(1)); // lane 6454 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6455 TmpInst.addOperand(Inst.getOperand(5)); 6456 Inst = TmpInst; 6457 return true; 6458 } 6459 6460 case ARM::VLD4LNdAsm_8: 6461 case ARM::VLD4LNdAsm_16: 6462 case ARM::VLD4LNdAsm_32: 6463 case ARM::VLD4LNqAsm_16: 6464 case ARM::VLD4LNqAsm_32: { 6465 MCInst TmpInst; 6466 // Shuffle the operands around so the lane index operand is in the 6467 // right place. 6468 unsigned Spacing; 6469 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6470 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6472 Spacing)); 6473 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6474 Spacing * 2)); 6475 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6476 Spacing * 3)); 6477 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6478 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6479 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6480 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6481 Spacing)); 6482 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6483 Spacing * 2)); 6484 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6485 Spacing * 3)); 6486 TmpInst.addOperand(Inst.getOperand(1)); // lane 6487 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6488 TmpInst.addOperand(Inst.getOperand(5)); 6489 Inst = TmpInst; 6490 return true; 6491 } 6492 6493 // VLD3DUP single 3-element structure to all lanes instructions. 6494 case ARM::VLD3DUPdAsm_8: 6495 case ARM::VLD3DUPdAsm_16: 6496 case ARM::VLD3DUPdAsm_32: 6497 case ARM::VLD3DUPqAsm_8: 6498 case ARM::VLD3DUPqAsm_16: 6499 case ARM::VLD3DUPqAsm_32: { 6500 MCInst TmpInst; 6501 unsigned Spacing; 6502 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6503 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6504 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6505 Spacing)); 6506 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6507 Spacing * 2)); 6508 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6509 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6510 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6511 TmpInst.addOperand(Inst.getOperand(4)); 6512 Inst = TmpInst; 6513 return true; 6514 } 6515 6516 case ARM::VLD3DUPdWB_fixed_Asm_8: 6517 case ARM::VLD3DUPdWB_fixed_Asm_16: 6518 case ARM::VLD3DUPdWB_fixed_Asm_32: 6519 case ARM::VLD3DUPqWB_fixed_Asm_8: 6520 case ARM::VLD3DUPqWB_fixed_Asm_16: 6521 case ARM::VLD3DUPqWB_fixed_Asm_32: { 6522 MCInst TmpInst; 6523 unsigned Spacing; 6524 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6525 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6526 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6527 Spacing)); 6528 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6529 Spacing * 2)); 6530 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6531 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6532 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6533 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6534 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6535 TmpInst.addOperand(Inst.getOperand(4)); 6536 Inst = TmpInst; 6537 return true; 6538 } 6539 6540 case ARM::VLD3DUPdWB_register_Asm_8: 6541 case ARM::VLD3DUPdWB_register_Asm_16: 6542 case ARM::VLD3DUPdWB_register_Asm_32: 6543 case ARM::VLD3DUPqWB_register_Asm_8: 6544 case ARM::VLD3DUPqWB_register_Asm_16: 6545 case ARM::VLD3DUPqWB_register_Asm_32: { 6546 MCInst TmpInst; 6547 unsigned Spacing; 6548 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6549 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6550 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6551 Spacing)); 6552 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6553 Spacing * 2)); 6554 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6555 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6556 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6557 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6558 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6559 TmpInst.addOperand(Inst.getOperand(5)); 6560 Inst = TmpInst; 6561 return true; 6562 } 6563 6564 // VLD3 multiple 3-element structure instructions. 6565 case ARM::VLD3dAsm_8: 6566 case ARM::VLD3dAsm_16: 6567 case ARM::VLD3dAsm_32: 6568 case ARM::VLD3qAsm_8: 6569 case ARM::VLD3qAsm_16: 6570 case ARM::VLD3qAsm_32: { 6571 MCInst TmpInst; 6572 unsigned Spacing; 6573 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6574 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6575 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6576 Spacing)); 6577 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6578 Spacing * 2)); 6579 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6580 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6581 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6582 TmpInst.addOperand(Inst.getOperand(4)); 6583 Inst = TmpInst; 6584 return true; 6585 } 6586 6587 case ARM::VLD3dWB_fixed_Asm_8: 6588 case ARM::VLD3dWB_fixed_Asm_16: 6589 case ARM::VLD3dWB_fixed_Asm_32: 6590 case ARM::VLD3qWB_fixed_Asm_8: 6591 case ARM::VLD3qWB_fixed_Asm_16: 6592 case ARM::VLD3qWB_fixed_Asm_32: { 6593 MCInst TmpInst; 6594 unsigned Spacing; 6595 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6596 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6597 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6598 Spacing)); 6599 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6600 Spacing * 2)); 6601 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6602 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6603 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6604 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6605 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6606 TmpInst.addOperand(Inst.getOperand(4)); 6607 Inst = TmpInst; 6608 return true; 6609 } 6610 6611 case ARM::VLD3dWB_register_Asm_8: 6612 case ARM::VLD3dWB_register_Asm_16: 6613 case ARM::VLD3dWB_register_Asm_32: 6614 case ARM::VLD3qWB_register_Asm_8: 6615 case ARM::VLD3qWB_register_Asm_16: 6616 case ARM::VLD3qWB_register_Asm_32: { 6617 MCInst TmpInst; 6618 unsigned Spacing; 6619 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6620 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6621 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6622 Spacing)); 6623 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6624 Spacing * 2)); 6625 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6626 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6627 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6628 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6629 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6630 TmpInst.addOperand(Inst.getOperand(5)); 6631 Inst = TmpInst; 6632 return true; 6633 } 6634 6635 // VLD4DUP single 3-element structure to all lanes instructions. 6636 case ARM::VLD4DUPdAsm_8: 6637 case ARM::VLD4DUPdAsm_16: 6638 case ARM::VLD4DUPdAsm_32: 6639 case ARM::VLD4DUPqAsm_8: 6640 case ARM::VLD4DUPqAsm_16: 6641 case ARM::VLD4DUPqAsm_32: { 6642 MCInst TmpInst; 6643 unsigned Spacing; 6644 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6645 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6646 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6647 Spacing)); 6648 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6649 Spacing * 2)); 6650 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6651 Spacing * 3)); 6652 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6653 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6654 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6655 TmpInst.addOperand(Inst.getOperand(4)); 6656 Inst = TmpInst; 6657 return true; 6658 } 6659 6660 case ARM::VLD4DUPdWB_fixed_Asm_8: 6661 case ARM::VLD4DUPdWB_fixed_Asm_16: 6662 case ARM::VLD4DUPdWB_fixed_Asm_32: 6663 case ARM::VLD4DUPqWB_fixed_Asm_8: 6664 case ARM::VLD4DUPqWB_fixed_Asm_16: 6665 case ARM::VLD4DUPqWB_fixed_Asm_32: { 6666 MCInst TmpInst; 6667 unsigned Spacing; 6668 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6669 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6670 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6671 Spacing)); 6672 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6673 Spacing * 2)); 6674 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6675 Spacing * 3)); 6676 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6677 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6678 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6679 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6680 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6681 TmpInst.addOperand(Inst.getOperand(4)); 6682 Inst = TmpInst; 6683 return true; 6684 } 6685 6686 case ARM::VLD4DUPdWB_register_Asm_8: 6687 case ARM::VLD4DUPdWB_register_Asm_16: 6688 case ARM::VLD4DUPdWB_register_Asm_32: 6689 case ARM::VLD4DUPqWB_register_Asm_8: 6690 case ARM::VLD4DUPqWB_register_Asm_16: 6691 case ARM::VLD4DUPqWB_register_Asm_32: { 6692 MCInst TmpInst; 6693 unsigned Spacing; 6694 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6695 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6697 Spacing)); 6698 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6699 Spacing * 2)); 6700 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6701 Spacing * 3)); 6702 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6703 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6704 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6705 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6706 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6707 TmpInst.addOperand(Inst.getOperand(5)); 6708 Inst = TmpInst; 6709 return true; 6710 } 6711 6712 // VLD4 multiple 4-element structure instructions. 6713 case ARM::VLD4dAsm_8: 6714 case ARM::VLD4dAsm_16: 6715 case ARM::VLD4dAsm_32: 6716 case ARM::VLD4qAsm_8: 6717 case ARM::VLD4qAsm_16: 6718 case ARM::VLD4qAsm_32: { 6719 MCInst TmpInst; 6720 unsigned Spacing; 6721 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6722 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6723 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6724 Spacing)); 6725 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6726 Spacing * 2)); 6727 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6728 Spacing * 3)); 6729 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6730 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6731 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6732 TmpInst.addOperand(Inst.getOperand(4)); 6733 Inst = TmpInst; 6734 return true; 6735 } 6736 6737 case ARM::VLD4dWB_fixed_Asm_8: 6738 case ARM::VLD4dWB_fixed_Asm_16: 6739 case ARM::VLD4dWB_fixed_Asm_32: 6740 case ARM::VLD4qWB_fixed_Asm_8: 6741 case ARM::VLD4qWB_fixed_Asm_16: 6742 case ARM::VLD4qWB_fixed_Asm_32: { 6743 MCInst TmpInst; 6744 unsigned Spacing; 6745 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6746 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6747 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6748 Spacing)); 6749 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6750 Spacing * 2)); 6751 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6752 Spacing * 3)); 6753 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6754 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6755 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6756 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6757 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6758 TmpInst.addOperand(Inst.getOperand(4)); 6759 Inst = TmpInst; 6760 return true; 6761 } 6762 6763 case ARM::VLD4dWB_register_Asm_8: 6764 case ARM::VLD4dWB_register_Asm_16: 6765 case ARM::VLD4dWB_register_Asm_32: 6766 case ARM::VLD4qWB_register_Asm_8: 6767 case ARM::VLD4qWB_register_Asm_16: 6768 case ARM::VLD4qWB_register_Asm_32: { 6769 MCInst TmpInst; 6770 unsigned Spacing; 6771 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6772 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6773 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6774 Spacing)); 6775 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6776 Spacing * 2)); 6777 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6778 Spacing * 3)); 6779 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6780 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6781 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6782 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6783 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6784 TmpInst.addOperand(Inst.getOperand(5)); 6785 Inst = TmpInst; 6786 return true; 6787 } 6788 6789 // VST3 multiple 3-element structure instructions. 6790 case ARM::VST3dAsm_8: 6791 case ARM::VST3dAsm_16: 6792 case ARM::VST3dAsm_32: 6793 case ARM::VST3qAsm_8: 6794 case ARM::VST3qAsm_16: 6795 case ARM::VST3qAsm_32: { 6796 MCInst TmpInst; 6797 unsigned Spacing; 6798 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6799 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6800 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6801 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6802 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6803 Spacing)); 6804 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6805 Spacing * 2)); 6806 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6807 TmpInst.addOperand(Inst.getOperand(4)); 6808 Inst = TmpInst; 6809 return true; 6810 } 6811 6812 case ARM::VST3dWB_fixed_Asm_8: 6813 case ARM::VST3dWB_fixed_Asm_16: 6814 case ARM::VST3dWB_fixed_Asm_32: 6815 case ARM::VST3qWB_fixed_Asm_8: 6816 case ARM::VST3qWB_fixed_Asm_16: 6817 case ARM::VST3qWB_fixed_Asm_32: { 6818 MCInst TmpInst; 6819 unsigned Spacing; 6820 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6821 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6822 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6823 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6824 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6825 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6827 Spacing)); 6828 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6829 Spacing * 2)); 6830 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6831 TmpInst.addOperand(Inst.getOperand(4)); 6832 Inst = TmpInst; 6833 return true; 6834 } 6835 6836 case ARM::VST3dWB_register_Asm_8: 6837 case ARM::VST3dWB_register_Asm_16: 6838 case ARM::VST3dWB_register_Asm_32: 6839 case ARM::VST3qWB_register_Asm_8: 6840 case ARM::VST3qWB_register_Asm_16: 6841 case ARM::VST3qWB_register_Asm_32: { 6842 MCInst TmpInst; 6843 unsigned Spacing; 6844 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6845 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6846 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6847 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6848 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6849 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6850 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6851 Spacing)); 6852 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6853 Spacing * 2)); 6854 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6855 TmpInst.addOperand(Inst.getOperand(5)); 6856 Inst = TmpInst; 6857 return true; 6858 } 6859 6860 // VST4 multiple 3-element structure instructions. 6861 case ARM::VST4dAsm_8: 6862 case ARM::VST4dAsm_16: 6863 case ARM::VST4dAsm_32: 6864 case ARM::VST4qAsm_8: 6865 case ARM::VST4qAsm_16: 6866 case ARM::VST4qAsm_32: { 6867 MCInst TmpInst; 6868 unsigned Spacing; 6869 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6870 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6871 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6872 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6873 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6874 Spacing)); 6875 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6876 Spacing * 2)); 6877 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6878 Spacing * 3)); 6879 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6880 TmpInst.addOperand(Inst.getOperand(4)); 6881 Inst = TmpInst; 6882 return true; 6883 } 6884 6885 case ARM::VST4dWB_fixed_Asm_8: 6886 case ARM::VST4dWB_fixed_Asm_16: 6887 case ARM::VST4dWB_fixed_Asm_32: 6888 case ARM::VST4qWB_fixed_Asm_8: 6889 case ARM::VST4qWB_fixed_Asm_16: 6890 case ARM::VST4qWB_fixed_Asm_32: { 6891 MCInst TmpInst; 6892 unsigned Spacing; 6893 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6894 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6895 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6896 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6897 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6898 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6899 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6900 Spacing)); 6901 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6902 Spacing * 2)); 6903 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6904 Spacing * 3)); 6905 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6906 TmpInst.addOperand(Inst.getOperand(4)); 6907 Inst = TmpInst; 6908 return true; 6909 } 6910 6911 case ARM::VST4dWB_register_Asm_8: 6912 case ARM::VST4dWB_register_Asm_16: 6913 case ARM::VST4dWB_register_Asm_32: 6914 case ARM::VST4qWB_register_Asm_8: 6915 case ARM::VST4qWB_register_Asm_16: 6916 case ARM::VST4qWB_register_Asm_32: { 6917 MCInst TmpInst; 6918 unsigned Spacing; 6919 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6920 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6921 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6922 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6923 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6924 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6925 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6926 Spacing)); 6927 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6928 Spacing * 2)); 6929 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6930 Spacing * 3)); 6931 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6932 TmpInst.addOperand(Inst.getOperand(5)); 6933 Inst = TmpInst; 6934 return true; 6935 } 6936 6937 // Handle encoding choice for the shift-immediate instructions. 6938 case ARM::t2LSLri: 6939 case ARM::t2LSRri: 6940 case ARM::t2ASRri: { 6941 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6942 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6943 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 6944 !(static_cast<ARMOperand*>(Operands[3])->isToken() && 6945 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 6946 unsigned NewOpc; 6947 switch (Inst.getOpcode()) { 6948 default: llvm_unreachable("unexpected opcode"); 6949 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6950 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6951 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6952 } 6953 // The Thumb1 operands aren't in the same order. Awesome, eh? 6954 MCInst TmpInst; 6955 TmpInst.setOpcode(NewOpc); 6956 TmpInst.addOperand(Inst.getOperand(0)); 6957 TmpInst.addOperand(Inst.getOperand(5)); 6958 TmpInst.addOperand(Inst.getOperand(1)); 6959 TmpInst.addOperand(Inst.getOperand(2)); 6960 TmpInst.addOperand(Inst.getOperand(3)); 6961 TmpInst.addOperand(Inst.getOperand(4)); 6962 Inst = TmpInst; 6963 return true; 6964 } 6965 return false; 6966 } 6967 6968 // Handle the Thumb2 mode MOV complex aliases. 6969 case ARM::t2MOVsr: 6970 case ARM::t2MOVSsr: { 6971 // Which instruction to expand to depends on the CCOut operand and 6972 // whether we're in an IT block if the register operands are low 6973 // registers. 6974 bool isNarrow = false; 6975 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6976 isARMLowRegister(Inst.getOperand(1).getReg()) && 6977 isARMLowRegister(Inst.getOperand(2).getReg()) && 6978 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6979 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 6980 isNarrow = true; 6981 MCInst TmpInst; 6982 unsigned newOpc; 6983 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 6984 default: llvm_unreachable("unexpected opcode!"); 6985 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 6986 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 6987 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 6988 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 6989 } 6990 TmpInst.setOpcode(newOpc); 6991 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6992 if (isNarrow) 6993 TmpInst.addOperand(MCOperand::CreateReg( 6994 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 6995 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6996 TmpInst.addOperand(Inst.getOperand(2)); // Rm 6997 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6998 TmpInst.addOperand(Inst.getOperand(5)); 6999 if (!isNarrow) 7000 TmpInst.addOperand(MCOperand::CreateReg( 7001 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7002 Inst = TmpInst; 7003 return true; 7004 } 7005 case ARM::t2MOVsi: 7006 case ARM::t2MOVSsi: { 7007 // Which instruction to expand to depends on the CCOut operand and 7008 // whether we're in an IT block if the register operands are low 7009 // registers. 7010 bool isNarrow = false; 7011 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7012 isARMLowRegister(Inst.getOperand(1).getReg()) && 7013 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 7014 isNarrow = true; 7015 MCInst TmpInst; 7016 unsigned newOpc; 7017 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 7018 default: llvm_unreachable("unexpected opcode!"); 7019 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 7020 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 7021 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 7022 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 7023 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 7024 } 7025 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 7026 if (Amount == 32) Amount = 0; 7027 TmpInst.setOpcode(newOpc); 7028 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7029 if (isNarrow) 7030 TmpInst.addOperand(MCOperand::CreateReg( 7031 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7032 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7033 if (newOpc != ARM::t2RRX) 7034 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 7035 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7036 TmpInst.addOperand(Inst.getOperand(4)); 7037 if (!isNarrow) 7038 TmpInst.addOperand(MCOperand::CreateReg( 7039 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7040 Inst = TmpInst; 7041 return true; 7042 } 7043 // Handle the ARM mode MOV complex aliases. 7044 case ARM::ASRr: 7045 case ARM::LSRr: 7046 case ARM::LSLr: 7047 case ARM::RORr: { 7048 ARM_AM::ShiftOpc ShiftTy; 7049 switch(Inst.getOpcode()) { 7050 default: llvm_unreachable("unexpected opcode!"); 7051 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 7052 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 7053 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 7054 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 7055 } 7056 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 7057 MCInst TmpInst; 7058 TmpInst.setOpcode(ARM::MOVsr); 7059 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7060 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7061 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7062 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7063 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7064 TmpInst.addOperand(Inst.getOperand(4)); 7065 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7066 Inst = TmpInst; 7067 return true; 7068 } 7069 case ARM::ASRi: 7070 case ARM::LSRi: 7071 case ARM::LSLi: 7072 case ARM::RORi: { 7073 ARM_AM::ShiftOpc ShiftTy; 7074 switch(Inst.getOpcode()) { 7075 default: llvm_unreachable("unexpected opcode!"); 7076 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 7077 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 7078 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 7079 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 7080 } 7081 // A shift by zero is a plain MOVr, not a MOVsi. 7082 unsigned Amt = Inst.getOperand(2).getImm(); 7083 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 7084 // A shift by 32 should be encoded as 0 when permitted 7085 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 7086 Amt = 0; 7087 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 7088 MCInst TmpInst; 7089 TmpInst.setOpcode(Opc); 7090 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7091 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7092 if (Opc == ARM::MOVsi) 7093 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7094 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7095 TmpInst.addOperand(Inst.getOperand(4)); 7096 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7097 Inst = TmpInst; 7098 return true; 7099 } 7100 case ARM::RRXi: { 7101 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 7102 MCInst TmpInst; 7103 TmpInst.setOpcode(ARM::MOVsi); 7104 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7105 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7106 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7107 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7108 TmpInst.addOperand(Inst.getOperand(3)); 7109 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 7110 Inst = TmpInst; 7111 return true; 7112 } 7113 case ARM::t2LDMIA_UPD: { 7114 // If this is a load of a single register, then we should use 7115 // a post-indexed LDR instruction instead, per the ARM ARM. 7116 if (Inst.getNumOperands() != 5) 7117 return false; 7118 MCInst TmpInst; 7119 TmpInst.setOpcode(ARM::t2LDR_POST); 7120 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7121 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7122 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7123 TmpInst.addOperand(MCOperand::CreateImm(4)); 7124 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7125 TmpInst.addOperand(Inst.getOperand(3)); 7126 Inst = TmpInst; 7127 return true; 7128 } 7129 case ARM::t2STMDB_UPD: { 7130 // If this is a store of a single register, then we should use 7131 // a pre-indexed STR instruction instead, per the ARM ARM. 7132 if (Inst.getNumOperands() != 5) 7133 return false; 7134 MCInst TmpInst; 7135 TmpInst.setOpcode(ARM::t2STR_PRE); 7136 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7137 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7138 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7139 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7140 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7141 TmpInst.addOperand(Inst.getOperand(3)); 7142 Inst = TmpInst; 7143 return true; 7144 } 7145 case ARM::LDMIA_UPD: 7146 // If this is a load of a single register via a 'pop', then we should use 7147 // a post-indexed LDR instruction instead, per the ARM ARM. 7148 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 7149 Inst.getNumOperands() == 5) { 7150 MCInst TmpInst; 7151 TmpInst.setOpcode(ARM::LDR_POST_IMM); 7152 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7153 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7154 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7155 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 7156 TmpInst.addOperand(MCOperand::CreateImm(4)); 7157 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7158 TmpInst.addOperand(Inst.getOperand(3)); 7159 Inst = TmpInst; 7160 return true; 7161 } 7162 break; 7163 case ARM::STMDB_UPD: 7164 // If this is a store of a single register via a 'push', then we should use 7165 // a pre-indexed STR instruction instead, per the ARM ARM. 7166 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 7167 Inst.getNumOperands() == 5) { 7168 MCInst TmpInst; 7169 TmpInst.setOpcode(ARM::STR_PRE_IMM); 7170 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7171 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7172 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 7173 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7174 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7175 TmpInst.addOperand(Inst.getOperand(3)); 7176 Inst = TmpInst; 7177 } 7178 break; 7179 case ARM::t2ADDri12: 7180 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 7181 // mnemonic was used (not "addw"), encoding T3 is preferred. 7182 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 7183 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7184 break; 7185 Inst.setOpcode(ARM::t2ADDri); 7186 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7187 break; 7188 case ARM::t2SUBri12: 7189 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 7190 // mnemonic was used (not "subw"), encoding T3 is preferred. 7191 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 7192 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7193 break; 7194 Inst.setOpcode(ARM::t2SUBri); 7195 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7196 break; 7197 case ARM::tADDi8: 7198 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7199 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7200 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7201 // to encoding T1 if <Rd> is omitted." 7202 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7203 Inst.setOpcode(ARM::tADDi3); 7204 return true; 7205 } 7206 break; 7207 case ARM::tSUBi8: 7208 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7209 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7210 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7211 // to encoding T1 if <Rd> is omitted." 7212 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7213 Inst.setOpcode(ARM::tSUBi3); 7214 return true; 7215 } 7216 break; 7217 case ARM::t2ADDri: 7218 case ARM::t2SUBri: { 7219 // If the destination and first source operand are the same, and 7220 // the flags are compatible with the current IT status, use encoding T2 7221 // instead of T3. For compatibility with the system 'as'. Make sure the 7222 // wide encoding wasn't explicit. 7223 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7224 !isARMLowRegister(Inst.getOperand(0).getReg()) || 7225 (unsigned)Inst.getOperand(2).getImm() > 255 || 7226 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 7227 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 7228 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7229 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7230 break; 7231 MCInst TmpInst; 7232 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7233 ARM::tADDi8 : ARM::tSUBi8); 7234 TmpInst.addOperand(Inst.getOperand(0)); 7235 TmpInst.addOperand(Inst.getOperand(5)); 7236 TmpInst.addOperand(Inst.getOperand(0)); 7237 TmpInst.addOperand(Inst.getOperand(2)); 7238 TmpInst.addOperand(Inst.getOperand(3)); 7239 TmpInst.addOperand(Inst.getOperand(4)); 7240 Inst = TmpInst; 7241 return true; 7242 } 7243 case ARM::t2ADDrr: { 7244 // If the destination and first source operand are the same, and 7245 // there's no setting of the flags, use encoding T2 instead of T3. 7246 // Note that this is only for ADD, not SUB. This mirrors the system 7247 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7248 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7249 Inst.getOperand(5).getReg() != 0 || 7250 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7251 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7252 break; 7253 MCInst TmpInst; 7254 TmpInst.setOpcode(ARM::tADDhirr); 7255 TmpInst.addOperand(Inst.getOperand(0)); 7256 TmpInst.addOperand(Inst.getOperand(0)); 7257 TmpInst.addOperand(Inst.getOperand(2)); 7258 TmpInst.addOperand(Inst.getOperand(3)); 7259 TmpInst.addOperand(Inst.getOperand(4)); 7260 Inst = TmpInst; 7261 return true; 7262 } 7263 case ARM::tADDrSP: { 7264 // If the non-SP source operand and the destination operand are not the 7265 // same, we need to use the 32-bit encoding if it's available. 7266 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7267 Inst.setOpcode(ARM::t2ADDrr); 7268 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7269 return true; 7270 } 7271 break; 7272 } 7273 case ARM::tB: 7274 // A Thumb conditional branch outside of an IT block is a tBcc. 7275 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7276 Inst.setOpcode(ARM::tBcc); 7277 return true; 7278 } 7279 break; 7280 case ARM::t2B: 7281 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7282 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7283 Inst.setOpcode(ARM::t2Bcc); 7284 return true; 7285 } 7286 break; 7287 case ARM::t2Bcc: 7288 // If the conditional is AL or we're in an IT block, we really want t2B. 7289 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7290 Inst.setOpcode(ARM::t2B); 7291 return true; 7292 } 7293 break; 7294 case ARM::tBcc: 7295 // If the conditional is AL, we really want tB. 7296 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7297 Inst.setOpcode(ARM::tB); 7298 return true; 7299 } 7300 break; 7301 case ARM::tLDMIA: { 7302 // If the register list contains any high registers, or if the writeback 7303 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7304 // instead if we're in Thumb2. Otherwise, this should have generated 7305 // an error in validateInstruction(). 7306 unsigned Rn = Inst.getOperand(0).getReg(); 7307 bool hasWritebackToken = 7308 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7309 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 7310 bool listContainsBase; 7311 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7312 (!listContainsBase && !hasWritebackToken) || 7313 (listContainsBase && hasWritebackToken)) { 7314 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7315 assert (isThumbTwo()); 7316 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7317 // If we're switching to the updating version, we need to insert 7318 // the writeback tied operand. 7319 if (hasWritebackToken) 7320 Inst.insert(Inst.begin(), 7321 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7322 return true; 7323 } 7324 break; 7325 } 7326 case ARM::tSTMIA_UPD: { 7327 // If the register list contains any high registers, we need to use 7328 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7329 // should have generated an error in validateInstruction(). 7330 unsigned Rn = Inst.getOperand(0).getReg(); 7331 bool listContainsBase; 7332 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7333 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7334 assert (isThumbTwo()); 7335 Inst.setOpcode(ARM::t2STMIA_UPD); 7336 return true; 7337 } 7338 break; 7339 } 7340 case ARM::tPOP: { 7341 bool listContainsBase; 7342 // If the register list contains any high registers, we need to use 7343 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7344 // should have generated an error in validateInstruction(). 7345 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7346 return false; 7347 assert (isThumbTwo()); 7348 Inst.setOpcode(ARM::t2LDMIA_UPD); 7349 // Add the base register and writeback operands. 7350 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7351 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7352 return true; 7353 } 7354 case ARM::tPUSH: { 7355 bool listContainsBase; 7356 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7357 return false; 7358 assert (isThumbTwo()); 7359 Inst.setOpcode(ARM::t2STMDB_UPD); 7360 // Add the base register and writeback operands. 7361 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7362 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7363 return true; 7364 } 7365 case ARM::t2MOVi: { 7366 // If we can use the 16-bit encoding and the user didn't explicitly 7367 // request the 32-bit variant, transform it here. 7368 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7369 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7370 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7371 Inst.getOperand(4).getReg() == ARM::CPSR) || 7372 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7373 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7374 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7375 // The operands aren't in the same order for tMOVi8... 7376 MCInst TmpInst; 7377 TmpInst.setOpcode(ARM::tMOVi8); 7378 TmpInst.addOperand(Inst.getOperand(0)); 7379 TmpInst.addOperand(Inst.getOperand(4)); 7380 TmpInst.addOperand(Inst.getOperand(1)); 7381 TmpInst.addOperand(Inst.getOperand(2)); 7382 TmpInst.addOperand(Inst.getOperand(3)); 7383 Inst = TmpInst; 7384 return true; 7385 } 7386 break; 7387 } 7388 case ARM::t2MOVr: { 7389 // If we can use the 16-bit encoding and the user didn't explicitly 7390 // request the 32-bit variant, transform it here. 7391 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7392 isARMLowRegister(Inst.getOperand(1).getReg()) && 7393 Inst.getOperand(2).getImm() == ARMCC::AL && 7394 Inst.getOperand(4).getReg() == ARM::CPSR && 7395 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7396 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7397 // The operands aren't the same for tMOV[S]r... (no cc_out) 7398 MCInst TmpInst; 7399 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 7400 TmpInst.addOperand(Inst.getOperand(0)); 7401 TmpInst.addOperand(Inst.getOperand(1)); 7402 TmpInst.addOperand(Inst.getOperand(2)); 7403 TmpInst.addOperand(Inst.getOperand(3)); 7404 Inst = TmpInst; 7405 return true; 7406 } 7407 break; 7408 } 7409 case ARM::t2SXTH: 7410 case ARM::t2SXTB: 7411 case ARM::t2UXTH: 7412 case ARM::t2UXTB: { 7413 // If we can use the 16-bit encoding and the user didn't explicitly 7414 // request the 32-bit variant, transform it here. 7415 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7416 isARMLowRegister(Inst.getOperand(1).getReg()) && 7417 Inst.getOperand(2).getImm() == 0 && 7418 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7419 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7420 unsigned NewOpc; 7421 switch (Inst.getOpcode()) { 7422 default: llvm_unreachable("Illegal opcode!"); 7423 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7424 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7425 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7426 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 7427 } 7428 // The operands aren't the same for thumb1 (no rotate operand). 7429 MCInst TmpInst; 7430 TmpInst.setOpcode(NewOpc); 7431 TmpInst.addOperand(Inst.getOperand(0)); 7432 TmpInst.addOperand(Inst.getOperand(1)); 7433 TmpInst.addOperand(Inst.getOperand(3)); 7434 TmpInst.addOperand(Inst.getOperand(4)); 7435 Inst = TmpInst; 7436 return true; 7437 } 7438 break; 7439 } 7440 case ARM::MOVsi: { 7441 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7442 // rrx shifts and asr/lsr of #32 is encoded as 0 7443 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7444 return false; 7445 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 7446 // Shifting by zero is accepted as a vanilla 'MOVr' 7447 MCInst TmpInst; 7448 TmpInst.setOpcode(ARM::MOVr); 7449 TmpInst.addOperand(Inst.getOperand(0)); 7450 TmpInst.addOperand(Inst.getOperand(1)); 7451 TmpInst.addOperand(Inst.getOperand(3)); 7452 TmpInst.addOperand(Inst.getOperand(4)); 7453 TmpInst.addOperand(Inst.getOperand(5)); 7454 Inst = TmpInst; 7455 return true; 7456 } 7457 return false; 7458 } 7459 case ARM::ANDrsi: 7460 case ARM::ORRrsi: 7461 case ARM::EORrsi: 7462 case ARM::BICrsi: 7463 case ARM::SUBrsi: 7464 case ARM::ADDrsi: { 7465 unsigned newOpc; 7466 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 7467 if (SOpc == ARM_AM::rrx) return false; 7468 switch (Inst.getOpcode()) { 7469 default: llvm_unreachable("unexpected opcode!"); 7470 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 7471 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 7472 case ARM::EORrsi: newOpc = ARM::EORrr; break; 7473 case ARM::BICrsi: newOpc = ARM::BICrr; break; 7474 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 7475 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 7476 } 7477 // If the shift is by zero, use the non-shifted instruction definition. 7478 // The exception is for right shifts, where 0 == 32 7479 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 7480 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 7481 MCInst TmpInst; 7482 TmpInst.setOpcode(newOpc); 7483 TmpInst.addOperand(Inst.getOperand(0)); 7484 TmpInst.addOperand(Inst.getOperand(1)); 7485 TmpInst.addOperand(Inst.getOperand(2)); 7486 TmpInst.addOperand(Inst.getOperand(4)); 7487 TmpInst.addOperand(Inst.getOperand(5)); 7488 TmpInst.addOperand(Inst.getOperand(6)); 7489 Inst = TmpInst; 7490 return true; 7491 } 7492 return false; 7493 } 7494 case ARM::ITasm: 7495 case ARM::t2IT: { 7496 // The mask bits for all but the first condition are represented as 7497 // the low bit of the condition code value implies 't'. We currently 7498 // always have 1 implies 't', so XOR toggle the bits if the low bit 7499 // of the condition code is zero. 7500 MCOperand &MO = Inst.getOperand(1); 7501 unsigned Mask = MO.getImm(); 7502 unsigned OrigMask = Mask; 7503 unsigned TZ = countTrailingZeros(Mask); 7504 if ((Inst.getOperand(0).getImm() & 1) == 0) { 7505 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 7506 Mask ^= (0xE << TZ) & 0xF; 7507 } 7508 MO.setImm(Mask); 7509 7510 // Set up the IT block state according to the IT instruction we just 7511 // matched. 7512 assert(!inITBlock() && "nested IT blocks?!"); 7513 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7514 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7515 ITState.CurPosition = 0; 7516 ITState.FirstCond = true; 7517 break; 7518 } 7519 case ARM::t2LSLrr: 7520 case ARM::t2LSRrr: 7521 case ARM::t2ASRrr: 7522 case ARM::t2SBCrr: 7523 case ARM::t2RORrr: 7524 case ARM::t2BICrr: 7525 { 7526 // Assemblers should use the narrow encodings of these instructions when permissible. 7527 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7528 isARMLowRegister(Inst.getOperand(2).getReg())) && 7529 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7530 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7531 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7532 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7533 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7534 unsigned NewOpc; 7535 switch (Inst.getOpcode()) { 7536 default: llvm_unreachable("unexpected opcode"); 7537 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 7538 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 7539 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 7540 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 7541 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 7542 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 7543 } 7544 MCInst TmpInst; 7545 TmpInst.setOpcode(NewOpc); 7546 TmpInst.addOperand(Inst.getOperand(0)); 7547 TmpInst.addOperand(Inst.getOperand(5)); 7548 TmpInst.addOperand(Inst.getOperand(1)); 7549 TmpInst.addOperand(Inst.getOperand(2)); 7550 TmpInst.addOperand(Inst.getOperand(3)); 7551 TmpInst.addOperand(Inst.getOperand(4)); 7552 Inst = TmpInst; 7553 return true; 7554 } 7555 return false; 7556 } 7557 case ARM::t2ANDrr: 7558 case ARM::t2EORrr: 7559 case ARM::t2ADCrr: 7560 case ARM::t2ORRrr: 7561 { 7562 // Assemblers should use the narrow encodings of these instructions when permissible. 7563 // These instructions are special in that they are commutable, so shorter encodings 7564 // are available more often. 7565 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7566 isARMLowRegister(Inst.getOperand(2).getReg())) && 7567 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 7568 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 7569 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7570 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7571 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7572 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7573 unsigned NewOpc; 7574 switch (Inst.getOpcode()) { 7575 default: llvm_unreachable("unexpected opcode"); 7576 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 7577 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 7578 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 7579 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 7580 } 7581 MCInst TmpInst; 7582 TmpInst.setOpcode(NewOpc); 7583 TmpInst.addOperand(Inst.getOperand(0)); 7584 TmpInst.addOperand(Inst.getOperand(5)); 7585 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 7586 TmpInst.addOperand(Inst.getOperand(1)); 7587 TmpInst.addOperand(Inst.getOperand(2)); 7588 } else { 7589 TmpInst.addOperand(Inst.getOperand(2)); 7590 TmpInst.addOperand(Inst.getOperand(1)); 7591 } 7592 TmpInst.addOperand(Inst.getOperand(3)); 7593 TmpInst.addOperand(Inst.getOperand(4)); 7594 Inst = TmpInst; 7595 return true; 7596 } 7597 return false; 7598 } 7599 } 7600 return false; 7601 } 7602 7603 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 7604 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 7605 // suffix depending on whether they're in an IT block or not. 7606 unsigned Opc = Inst.getOpcode(); 7607 const MCInstrDesc &MCID = MII.get(Opc); 7608 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 7609 assert(MCID.hasOptionalDef() && 7610 "optionally flag setting instruction missing optional def operand"); 7611 assert(MCID.NumOperands == Inst.getNumOperands() && 7612 "operand count mismatch!"); 7613 // Find the optional-def operand (cc_out). 7614 unsigned OpNo; 7615 for (OpNo = 0; 7616 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 7617 ++OpNo) 7618 ; 7619 // If we're parsing Thumb1, reject it completely. 7620 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 7621 return Match_MnemonicFail; 7622 // If we're parsing Thumb2, which form is legal depends on whether we're 7623 // in an IT block. 7624 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7625 !inITBlock()) 7626 return Match_RequiresITBlock; 7627 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7628 inITBlock()) 7629 return Match_RequiresNotITBlock; 7630 } 7631 // Some high-register supporting Thumb1 encodings only allow both registers 7632 // to be from r0-r7 when in Thumb2. 7633 else if (Opc == ARM::tADDhirr && isThumbOne() && 7634 isARMLowRegister(Inst.getOperand(1).getReg()) && 7635 isARMLowRegister(Inst.getOperand(2).getReg())) 7636 return Match_RequiresThumb2; 7637 // Others only require ARMv6 or later. 7638 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7639 isARMLowRegister(Inst.getOperand(0).getReg()) && 7640 isARMLowRegister(Inst.getOperand(1).getReg())) 7641 return Match_RequiresV6; 7642 return Match_Success; 7643 } 7644 7645 static const char *getSubtargetFeatureName(unsigned Val); 7646 bool ARMAsmParser:: 7647 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 7648 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7649 MCStreamer &Out, unsigned &ErrorInfo, 7650 bool MatchingInlineAsm) { 7651 MCInst Inst; 7652 unsigned MatchResult; 7653 7654 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 7655 MatchingInlineAsm); 7656 switch (MatchResult) { 7657 default: break; 7658 case Match_Success: 7659 // Context sensitive operand constraints aren't handled by the matcher, 7660 // so check them here. 7661 if (validateInstruction(Inst, Operands)) { 7662 // Still progress the IT block, otherwise one wrong condition causes 7663 // nasty cascading errors. 7664 forwardITPosition(); 7665 return true; 7666 } 7667 7668 { // processInstruction() updates inITBlock state, we need to save it away 7669 bool wasInITBlock = inITBlock(); 7670 7671 // Some instructions need post-processing to, for example, tweak which 7672 // encoding is selected. Loop on it while changes happen so the 7673 // individual transformations can chain off each other. E.g., 7674 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 7675 while (processInstruction(Inst, Operands)) 7676 ; 7677 7678 // Only after the instruction is fully processed, we can validate it 7679 if (wasInITBlock && hasV8Ops() && isThumb() && 7680 !isV8EligibleForIT(&Inst, 2)) { 7681 Warning(IDLoc, "deprecated instruction in IT block"); 7682 } 7683 } 7684 7685 // Only move forward at the very end so that everything in validate 7686 // and process gets a consistent answer about whether we're in an IT 7687 // block. 7688 forwardITPosition(); 7689 7690 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 7691 // doesn't actually encode. 7692 if (Inst.getOpcode() == ARM::ITasm) 7693 return false; 7694 7695 Inst.setLoc(IDLoc); 7696 Out.EmitInstruction(Inst); 7697 return false; 7698 case Match_MissingFeature: { 7699 assert(ErrorInfo && "Unknown missing feature!"); 7700 // Special case the error message for the very common case where only 7701 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 7702 std::string Msg = "instruction requires:"; 7703 unsigned Mask = 1; 7704 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 7705 if (ErrorInfo & Mask) { 7706 Msg += " "; 7707 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 7708 } 7709 Mask <<= 1; 7710 } 7711 return Error(IDLoc, Msg); 7712 } 7713 case Match_InvalidOperand: { 7714 SMLoc ErrorLoc = IDLoc; 7715 if (ErrorInfo != ~0U) { 7716 if (ErrorInfo >= Operands.size()) 7717 return Error(IDLoc, "too few operands for instruction"); 7718 7719 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7720 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7721 } 7722 7723 return Error(ErrorLoc, "invalid operand for instruction"); 7724 } 7725 case Match_MnemonicFail: 7726 return Error(IDLoc, "invalid instruction", 7727 ((ARMOperand*)Operands[0])->getLocRange()); 7728 case Match_RequiresNotITBlock: 7729 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 7730 case Match_RequiresITBlock: 7731 return Error(IDLoc, "instruction only valid inside IT block"); 7732 case Match_RequiresV6: 7733 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7734 case Match_RequiresThumb2: 7735 return Error(IDLoc, "instruction variant requires Thumb2"); 7736 case Match_ImmRange0_15: { 7737 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7738 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7739 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 7740 } 7741 case Match_ImmRange0_239: { 7742 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7743 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7744 return Error(ErrorLoc, "immediate operand must be in the range [0,239]"); 7745 } 7746 } 7747 7748 llvm_unreachable("Implement any new match types added!"); 7749 } 7750 7751 /// parseDirective parses the arm specific directives 7752 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7753 StringRef IDVal = DirectiveID.getIdentifier(); 7754 if (IDVal == ".word") 7755 return parseDirectiveWord(4, DirectiveID.getLoc()); 7756 else if (IDVal == ".thumb") 7757 return parseDirectiveThumb(DirectiveID.getLoc()); 7758 else if (IDVal == ".arm") 7759 return parseDirectiveARM(DirectiveID.getLoc()); 7760 else if (IDVal == ".thumb_func") 7761 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7762 else if (IDVal == ".code") 7763 return parseDirectiveCode(DirectiveID.getLoc()); 7764 else if (IDVal == ".syntax") 7765 return parseDirectiveSyntax(DirectiveID.getLoc()); 7766 else if (IDVal == ".unreq") 7767 return parseDirectiveUnreq(DirectiveID.getLoc()); 7768 else if (IDVal == ".arch") 7769 return parseDirectiveArch(DirectiveID.getLoc()); 7770 else if (IDVal == ".eabi_attribute") 7771 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7772 else if (IDVal == ".cpu") 7773 return parseDirectiveCPU(DirectiveID.getLoc()); 7774 else if (IDVal == ".fpu") 7775 return parseDirectiveFPU(DirectiveID.getLoc()); 7776 else if (IDVal == ".fnstart") 7777 return parseDirectiveFnStart(DirectiveID.getLoc()); 7778 else if (IDVal == ".fnend") 7779 return parseDirectiveFnEnd(DirectiveID.getLoc()); 7780 else if (IDVal == ".cantunwind") 7781 return parseDirectiveCantUnwind(DirectiveID.getLoc()); 7782 else if (IDVal == ".personality") 7783 return parseDirectivePersonality(DirectiveID.getLoc()); 7784 else if (IDVal == ".handlerdata") 7785 return parseDirectiveHandlerData(DirectiveID.getLoc()); 7786 else if (IDVal == ".setfp") 7787 return parseDirectiveSetFP(DirectiveID.getLoc()); 7788 else if (IDVal == ".pad") 7789 return parseDirectivePad(DirectiveID.getLoc()); 7790 else if (IDVal == ".save") 7791 return parseDirectiveRegSave(DirectiveID.getLoc(), false); 7792 else if (IDVal == ".vsave") 7793 return parseDirectiveRegSave(DirectiveID.getLoc(), true); 7794 return true; 7795 } 7796 7797 /// parseDirectiveWord 7798 /// ::= .word [ expression (, expression)* ] 7799 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 7800 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7801 for (;;) { 7802 const MCExpr *Value; 7803 if (getParser().parseExpression(Value)) 7804 return true; 7805 7806 getParser().getStreamer().EmitValue(Value, Size); 7807 7808 if (getLexer().is(AsmToken::EndOfStatement)) 7809 break; 7810 7811 // FIXME: Improve diagnostic. 7812 if (getLexer().isNot(AsmToken::Comma)) 7813 return Error(L, "unexpected token in directive"); 7814 Parser.Lex(); 7815 } 7816 } 7817 7818 Parser.Lex(); 7819 return false; 7820 } 7821 7822 /// parseDirectiveThumb 7823 /// ::= .thumb 7824 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 7825 if (getLexer().isNot(AsmToken::EndOfStatement)) 7826 return Error(L, "unexpected token in directive"); 7827 Parser.Lex(); 7828 7829 if (!hasThumb()) 7830 return Error(L, "target does not support Thumb mode"); 7831 7832 if (!isThumb()) 7833 SwitchMode(); 7834 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7835 return false; 7836 } 7837 7838 /// parseDirectiveARM 7839 /// ::= .arm 7840 bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 7841 if (getLexer().isNot(AsmToken::EndOfStatement)) 7842 return Error(L, "unexpected token in directive"); 7843 Parser.Lex(); 7844 7845 if (!hasARM()) 7846 return Error(L, "target does not support ARM mode"); 7847 7848 if (isThumb()) 7849 SwitchMode(); 7850 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7851 return false; 7852 } 7853 7854 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { 7855 if (NextSymbolIsThumb) { 7856 getParser().getStreamer().EmitThumbFunc(Symbol); 7857 NextSymbolIsThumb = false; 7858 } 7859 } 7860 7861 /// parseDirectiveThumbFunc 7862 /// ::= .thumbfunc symbol_name 7863 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 7864 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 7865 bool isMachO = MAI->hasSubsectionsViaSymbols(); 7866 7867 // Darwin asm has (optionally) function name after .thumb_func direction 7868 // ELF doesn't 7869 if (isMachO) { 7870 const AsmToken &Tok = Parser.getTok(); 7871 if (Tok.isNot(AsmToken::EndOfStatement)) { 7872 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 7873 return Error(L, "unexpected token in .thumb_func directive"); 7874 MCSymbol *Func = 7875 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier()); 7876 getParser().getStreamer().EmitThumbFunc(Func); 7877 Parser.Lex(); // Consume the identifier token. 7878 return false; 7879 } 7880 } 7881 7882 if (getLexer().isNot(AsmToken::EndOfStatement)) 7883 return Error(L, "unexpected token in directive"); 7884 7885 NextSymbolIsThumb = true; 7886 7887 return false; 7888 } 7889 7890 /// parseDirectiveSyntax 7891 /// ::= .syntax unified | divided 7892 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 7893 const AsmToken &Tok = Parser.getTok(); 7894 if (Tok.isNot(AsmToken::Identifier)) 7895 return Error(L, "unexpected token in .syntax directive"); 7896 StringRef Mode = Tok.getString(); 7897 if (Mode == "unified" || Mode == "UNIFIED") 7898 Parser.Lex(); 7899 else if (Mode == "divided" || Mode == "DIVIDED") 7900 return Error(L, "'.syntax divided' arm asssembly not supported"); 7901 else 7902 return Error(L, "unrecognized syntax mode in .syntax directive"); 7903 7904 if (getLexer().isNot(AsmToken::EndOfStatement)) 7905 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7906 Parser.Lex(); 7907 7908 // TODO tell the MC streamer the mode 7909 // getParser().getStreamer().Emit???(); 7910 return false; 7911 } 7912 7913 /// parseDirectiveCode 7914 /// ::= .code 16 | 32 7915 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 7916 const AsmToken &Tok = Parser.getTok(); 7917 if (Tok.isNot(AsmToken::Integer)) 7918 return Error(L, "unexpected token in .code directive"); 7919 int64_t Val = Parser.getTok().getIntVal(); 7920 if (Val == 16) 7921 Parser.Lex(); 7922 else if (Val == 32) 7923 Parser.Lex(); 7924 else 7925 return Error(L, "invalid operand to .code directive"); 7926 7927 if (getLexer().isNot(AsmToken::EndOfStatement)) 7928 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7929 Parser.Lex(); 7930 7931 if (Val == 16) { 7932 if (!hasThumb()) 7933 return Error(L, "target does not support Thumb mode"); 7934 7935 if (!isThumb()) 7936 SwitchMode(); 7937 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7938 } else { 7939 if (!hasARM()) 7940 return Error(L, "target does not support ARM mode"); 7941 7942 if (isThumb()) 7943 SwitchMode(); 7944 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7945 } 7946 7947 return false; 7948 } 7949 7950 /// parseDirectiveReq 7951 /// ::= name .req registername 7952 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 7953 Parser.Lex(); // Eat the '.req' token. 7954 unsigned Reg; 7955 SMLoc SRegLoc, ERegLoc; 7956 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 7957 Parser.eatToEndOfStatement(); 7958 return Error(SRegLoc, "register name expected"); 7959 } 7960 7961 // Shouldn't be anything else. 7962 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7963 Parser.eatToEndOfStatement(); 7964 return Error(Parser.getTok().getLoc(), 7965 "unexpected input in .req directive."); 7966 } 7967 7968 Parser.Lex(); // Consume the EndOfStatement 7969 7970 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 7971 return Error(SRegLoc, "redefinition of '" + Name + 7972 "' does not match original."); 7973 7974 return false; 7975 } 7976 7977 /// parseDirectiveUneq 7978 /// ::= .unreq registername 7979 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 7980 if (Parser.getTok().isNot(AsmToken::Identifier)) { 7981 Parser.eatToEndOfStatement(); 7982 return Error(L, "unexpected input in .unreq directive."); 7983 } 7984 RegisterReqs.erase(Parser.getTok().getIdentifier()); 7985 Parser.Lex(); // Eat the identifier. 7986 return false; 7987 } 7988 7989 /// parseDirectiveArch 7990 /// ::= .arch token 7991 bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 7992 return true; 7993 } 7994 7995 /// parseDirectiveEabiAttr 7996 /// ::= .eabi_attribute int, int 7997 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 7998 if (Parser.getTok().isNot(AsmToken::Integer)) 7999 return Error(L, "integer expected"); 8000 int64_t Tag = Parser.getTok().getIntVal(); 8001 Parser.Lex(); // eat tag integer 8002 8003 if (Parser.getTok().isNot(AsmToken::Comma)) 8004 return Error(L, "comma expected"); 8005 Parser.Lex(); // skip comma 8006 8007 L = Parser.getTok().getLoc(); 8008 if (Parser.getTok().isNot(AsmToken::Integer)) 8009 return Error(L, "integer expected"); 8010 int64_t Value = Parser.getTok().getIntVal(); 8011 Parser.Lex(); // eat value integer 8012 8013 getTargetStreamer().emitAttribute(Tag, Value); 8014 return false; 8015 } 8016 8017 /// parseDirectiveCPU 8018 /// ::= .cpu str 8019 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { 8020 StringRef CPU = getParser().parseStringToEndOfStatement().trim(); 8021 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU); 8022 return false; 8023 } 8024 8025 /// parseDirectiveFPU 8026 /// ::= .fpu str 8027 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { 8028 StringRef FPU = getParser().parseStringToEndOfStatement().trim(); 8029 8030 unsigned ID = StringSwitch<unsigned>(FPU) 8031 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID) 8032 #include "ARMFPUName.def" 8033 .Default(ARM::INVALID_FPU); 8034 8035 if (ID == ARM::INVALID_FPU) 8036 return Error(L, "Unknown FPU name"); 8037 8038 getTargetStreamer().emitFPU(ID); 8039 return false; 8040 } 8041 8042 /// parseDirectiveFnStart 8043 /// ::= .fnstart 8044 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { 8045 if (FnStartLoc.isValid()) { 8046 Error(L, ".fnstart starts before the end of previous one"); 8047 Error(FnStartLoc, "previous .fnstart starts here"); 8048 return true; 8049 } 8050 8051 FnStartLoc = L; 8052 getTargetStreamer().emitFnStart(); 8053 return false; 8054 } 8055 8056 /// parseDirectiveFnEnd 8057 /// ::= .fnend 8058 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { 8059 // Check the ordering of unwind directives 8060 if (!FnStartLoc.isValid()) 8061 return Error(L, ".fnstart must precede .fnend directive"); 8062 8063 // Reset the unwind directives parser state 8064 resetUnwindDirectiveParserState(); 8065 getTargetStreamer().emitFnEnd(); 8066 return false; 8067 } 8068 8069 /// parseDirectiveCantUnwind 8070 /// ::= .cantunwind 8071 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { 8072 // Check the ordering of unwind directives 8073 CantUnwindLoc = L; 8074 if (!FnStartLoc.isValid()) 8075 return Error(L, ".fnstart must precede .cantunwind directive"); 8076 if (HandlerDataLoc.isValid()) { 8077 Error(L, ".cantunwind can't be used with .handlerdata directive"); 8078 Error(HandlerDataLoc, ".handlerdata was specified here"); 8079 return true; 8080 } 8081 if (PersonalityLoc.isValid()) { 8082 Error(L, ".cantunwind can't be used with .personality directive"); 8083 Error(PersonalityLoc, ".personality was specified here"); 8084 return true; 8085 } 8086 8087 getTargetStreamer().emitCantUnwind(); 8088 return false; 8089 } 8090 8091 /// parseDirectivePersonality 8092 /// ::= .personality name 8093 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { 8094 // Check the ordering of unwind directives 8095 PersonalityLoc = L; 8096 if (!FnStartLoc.isValid()) 8097 return Error(L, ".fnstart must precede .personality directive"); 8098 if (CantUnwindLoc.isValid()) { 8099 Error(L, ".personality can't be used with .cantunwind directive"); 8100 Error(CantUnwindLoc, ".cantunwind was specified here"); 8101 return true; 8102 } 8103 if (HandlerDataLoc.isValid()) { 8104 Error(L, ".personality must precede .handlerdata directive"); 8105 Error(HandlerDataLoc, ".handlerdata was specified here"); 8106 return true; 8107 } 8108 8109 // Parse the name of the personality routine 8110 if (Parser.getTok().isNot(AsmToken::Identifier)) { 8111 Parser.eatToEndOfStatement(); 8112 return Error(L, "unexpected input in .personality directive."); 8113 } 8114 StringRef Name(Parser.getTok().getIdentifier()); 8115 Parser.Lex(); 8116 8117 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name); 8118 getTargetStreamer().emitPersonality(PR); 8119 return false; 8120 } 8121 8122 /// parseDirectiveHandlerData 8123 /// ::= .handlerdata 8124 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { 8125 // Check the ordering of unwind directives 8126 HandlerDataLoc = L; 8127 if (!FnStartLoc.isValid()) 8128 return Error(L, ".fnstart must precede .personality directive"); 8129 if (CantUnwindLoc.isValid()) { 8130 Error(L, ".handlerdata can't be used with .cantunwind directive"); 8131 Error(CantUnwindLoc, ".cantunwind was specified here"); 8132 return true; 8133 } 8134 8135 getTargetStreamer().emitHandlerData(); 8136 return false; 8137 } 8138 8139 /// parseDirectiveSetFP 8140 /// ::= .setfp fpreg, spreg [, offset] 8141 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { 8142 // Check the ordering of unwind directives 8143 if (!FnStartLoc.isValid()) 8144 return Error(L, ".fnstart must precede .setfp directive"); 8145 if (HandlerDataLoc.isValid()) 8146 return Error(L, ".setfp must precede .handlerdata directive"); 8147 8148 // Parse fpreg 8149 SMLoc NewFPRegLoc = Parser.getTok().getLoc(); 8150 int NewFPReg = tryParseRegister(); 8151 if (NewFPReg == -1) 8152 return Error(NewFPRegLoc, "frame pointer register expected"); 8153 8154 // Consume comma 8155 if (!Parser.getTok().is(AsmToken::Comma)) 8156 return Error(Parser.getTok().getLoc(), "comma expected"); 8157 Parser.Lex(); // skip comma 8158 8159 // Parse spreg 8160 SMLoc NewSPRegLoc = Parser.getTok().getLoc(); 8161 int NewSPReg = tryParseRegister(); 8162 if (NewSPReg == -1) 8163 return Error(NewSPRegLoc, "stack pointer register expected"); 8164 8165 if (NewSPReg != ARM::SP && NewSPReg != FPReg) 8166 return Error(NewSPRegLoc, 8167 "register should be either $sp or the latest fp register"); 8168 8169 // Update the frame pointer register 8170 FPReg = NewFPReg; 8171 8172 // Parse offset 8173 int64_t Offset = 0; 8174 if (Parser.getTok().is(AsmToken::Comma)) { 8175 Parser.Lex(); // skip comma 8176 8177 if (Parser.getTok().isNot(AsmToken::Hash) && 8178 Parser.getTok().isNot(AsmToken::Dollar)) { 8179 return Error(Parser.getTok().getLoc(), "'#' expected"); 8180 } 8181 Parser.Lex(); // skip hash token. 8182 8183 const MCExpr *OffsetExpr; 8184 SMLoc ExLoc = Parser.getTok().getLoc(); 8185 SMLoc EndLoc; 8186 if (getParser().parseExpression(OffsetExpr, EndLoc)) 8187 return Error(ExLoc, "malformed setfp offset"); 8188 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8189 if (!CE) 8190 return Error(ExLoc, "setfp offset must be an immediate"); 8191 8192 Offset = CE->getValue(); 8193 } 8194 8195 getTargetStreamer().emitSetFP(static_cast<unsigned>(NewFPReg), 8196 static_cast<unsigned>(NewSPReg), Offset); 8197 return false; 8198 } 8199 8200 /// parseDirective 8201 /// ::= .pad offset 8202 bool ARMAsmParser::parseDirectivePad(SMLoc L) { 8203 // Check the ordering of unwind directives 8204 if (!FnStartLoc.isValid()) 8205 return Error(L, ".fnstart must precede .pad directive"); 8206 if (HandlerDataLoc.isValid()) 8207 return Error(L, ".pad must precede .handlerdata directive"); 8208 8209 // Parse the offset 8210 if (Parser.getTok().isNot(AsmToken::Hash) && 8211 Parser.getTok().isNot(AsmToken::Dollar)) { 8212 return Error(Parser.getTok().getLoc(), "'#' expected"); 8213 } 8214 Parser.Lex(); // skip hash token. 8215 8216 const MCExpr *OffsetExpr; 8217 SMLoc ExLoc = Parser.getTok().getLoc(); 8218 SMLoc EndLoc; 8219 if (getParser().parseExpression(OffsetExpr, EndLoc)) 8220 return Error(ExLoc, "malformed pad offset"); 8221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8222 if (!CE) 8223 return Error(ExLoc, "pad offset must be an immediate"); 8224 8225 getTargetStreamer().emitPad(CE->getValue()); 8226 return false; 8227 } 8228 8229 /// parseDirectiveRegSave 8230 /// ::= .save { registers } 8231 /// ::= .vsave { registers } 8232 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { 8233 // Check the ordering of unwind directives 8234 if (!FnStartLoc.isValid()) 8235 return Error(L, ".fnstart must precede .save or .vsave directives"); 8236 if (HandlerDataLoc.isValid()) 8237 return Error(L, ".save or .vsave must precede .handlerdata directive"); 8238 8239 // RAII object to make sure parsed operands are deleted. 8240 struct CleanupObject { 8241 SmallVector<MCParsedAsmOperand *, 1> Operands; 8242 ~CleanupObject() { 8243 for (unsigned I = 0, E = Operands.size(); I != E; ++I) 8244 delete Operands[I]; 8245 } 8246 } CO; 8247 8248 // Parse the register list 8249 if (parseRegisterList(CO.Operands)) 8250 return true; 8251 ARMOperand *Op = (ARMOperand*)CO.Operands[0]; 8252 if (!IsVector && !Op->isRegList()) 8253 return Error(L, ".save expects GPR registers"); 8254 if (IsVector && !Op->isDPRRegList()) 8255 return Error(L, ".vsave expects DPR registers"); 8256 8257 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector); 8258 return false; 8259 } 8260 8261 /// Force static initialization. 8262 extern "C" void LLVMInitializeARMAsmParser() { 8263 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 8264 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 8265 } 8266 8267 #define GET_REGISTER_MATCHER 8268 #define GET_SUBTARGET_FEATURE_NAME 8269 #define GET_MATCHER_IMPLEMENTATION 8270 #include "ARMGenAsmMatcher.inc" 8271 8272 // Define this matcher function after the auto-generated include so we 8273 // have the match class enum definitions. 8274 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp, 8275 unsigned Kind) { 8276 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp); 8277 // If the kind is a token for a literal immediate, check if our asm 8278 // operand matches. This is for InstAliases which have a fixed-value 8279 // immediate in the syntax. 8280 if (Kind == MCK__35_0 && Op->isImm()) { 8281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 8282 if (!CE) 8283 return Match_InvalidOperand; 8284 if (CE->getValue() == 0) 8285 return Match_Success; 8286 } 8287 return Match_InvalidOperand; 8288 } 8289