1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "ARMFPUName.h" 11 #include "ARMFeatures.h" 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMArchName.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/ADT/BitVector.h" 17 #include "llvm/ADT/MapVector.h" 18 #include "llvm/ADT/OwningPtr.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/ADT/SmallVector.h" 21 #include "llvm/ADT/StringExtras.h" 22 #include "llvm/ADT/StringSwitch.h" 23 #include "llvm/ADT/Twine.h" 24 #include "llvm/MC/MCAsmInfo.h" 25 #include "llvm/MC/MCAssembler.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCDisassembler.h" 28 #include "llvm/MC/MCELFStreamer.h" 29 #include "llvm/MC/MCExpr.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCInstrInfo.h" 33 #include "llvm/MC/MCParser/MCAsmLexer.h" 34 #include "llvm/MC/MCParser/MCAsmParser.h" 35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 36 #include "llvm/MC/MCRegisterInfo.h" 37 #include "llvm/MC/MCSection.h" 38 #include "llvm/MC/MCStreamer.h" 39 #include "llvm/MC/MCSubtargetInfo.h" 40 #include "llvm/MC/MCSymbol.h" 41 #include "llvm/MC/MCTargetAsmParser.h" 42 #include "llvm/Support/ARMBuildAttributes.h" 43 #include "llvm/Support/ARMEHABI.h" 44 #include "llvm/Support/Debug.h" 45 #include "llvm/Support/ELF.h" 46 #include "llvm/Support/MathExtras.h" 47 #include "llvm/Support/SourceMgr.h" 48 #include "llvm/Support/TargetRegistry.h" 49 #include "llvm/Support/raw_ostream.h" 50 51 using namespace llvm; 52 53 namespace { 54 55 class ARMOperand; 56 57 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 58 59 class UnwindContext { 60 MCAsmParser &Parser; 61 62 typedef SmallVector<SMLoc, 4> Locs; 63 64 Locs FnStartLocs; 65 Locs CantUnwindLocs; 66 Locs PersonalityLocs; 67 Locs PersonalityIndexLocs; 68 Locs HandlerDataLocs; 69 int FPReg; 70 71 public: 72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} 73 74 bool hasFnStart() const { return !FnStartLocs.empty(); } 75 bool cantUnwind() const { return !CantUnwindLocs.empty(); } 76 bool hasHandlerData() const { return !HandlerDataLocs.empty(); } 77 bool hasPersonality() const { 78 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); 79 } 80 81 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } 82 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } 83 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } 84 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } 85 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } 86 87 void saveFPReg(int Reg) { FPReg = Reg; } 88 int getFPReg() const { return FPReg; } 89 90 void emitFnStartLocNotes() const { 91 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); 92 FI != FE; ++FI) 93 Parser.Note(*FI, ".fnstart was specified here"); 94 } 95 void emitCantUnwindLocNotes() const { 96 for (Locs::const_iterator UI = CantUnwindLocs.begin(), 97 UE = CantUnwindLocs.end(); UI != UE; ++UI) 98 Parser.Note(*UI, ".cantunwind was specified here"); 99 } 100 void emitHandlerDataLocNotes() const { 101 for (Locs::const_iterator HI = HandlerDataLocs.begin(), 102 HE = HandlerDataLocs.end(); HI != HE; ++HI) 103 Parser.Note(*HI, ".handlerdata was specified here"); 104 } 105 void emitPersonalityLocNotes() const { 106 for (Locs::const_iterator PI = PersonalityLocs.begin(), 107 PE = PersonalityLocs.end(), 108 PII = PersonalityIndexLocs.begin(), 109 PIE = PersonalityIndexLocs.end(); 110 PI != PE || PII != PIE;) { 111 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) 112 Parser.Note(*PI++, ".personality was specified here"); 113 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) 114 Parser.Note(*PII++, ".personalityindex was specified here"); 115 else 116 llvm_unreachable(".personality and .personalityindex cannot be " 117 "at the same location"); 118 } 119 } 120 121 void reset() { 122 FnStartLocs = Locs(); 123 CantUnwindLocs = Locs(); 124 PersonalityLocs = Locs(); 125 HandlerDataLocs = Locs(); 126 PersonalityIndexLocs = Locs(); 127 FPReg = ARM::SP; 128 } 129 }; 130 131 class ARMAsmParser : public MCTargetAsmParser { 132 MCSubtargetInfo &STI; 133 MCAsmParser &Parser; 134 const MCInstrInfo &MII; 135 const MCRegisterInfo *MRI; 136 UnwindContext UC; 137 138 ARMTargetStreamer &getTargetStreamer() { 139 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); 140 return static_cast<ARMTargetStreamer &>(TS); 141 } 142 143 // Map of register aliases registers via the .req directive. 144 StringMap<unsigned> RegisterReqs; 145 146 bool NextSymbolIsThumb; 147 148 struct { 149 ARMCC::CondCodes Cond; // Condition for IT block. 150 unsigned Mask:4; // Condition mask for instructions. 151 // Starting at first 1 (from lsb). 152 // '1' condition as indicated in IT. 153 // '0' inverse of condition (else). 154 // Count of instructions in IT block is 155 // 4 - trailingzeroes(mask) 156 157 bool FirstCond; // Explicit flag for when we're parsing the 158 // First instruction in the IT block. It's 159 // implied in the mask, so needs special 160 // handling. 161 162 unsigned CurPosition; // Current position in parsing of IT 163 // block. In range [0,3]. Initialized 164 // according to count of instructions in block. 165 // ~0U if no active IT block. 166 } ITState; 167 bool inITBlock() { return ITState.CurPosition != ~0U;} 168 void forwardITPosition() { 169 if (!inITBlock()) return; 170 // Move to the next instruction in the IT block, if there is one. If not, 171 // mark the block as done. 172 unsigned TZ = countTrailingZeros(ITState.Mask); 173 if (++ITState.CurPosition == 5 - TZ) 174 ITState.CurPosition = ~0U; // Done with the IT block after this. 175 } 176 177 178 MCAsmParser &getParser() const { return Parser; } 179 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 180 181 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) { 182 return Parser.Note(L, Msg, Ranges); 183 } 184 bool Warning(SMLoc L, const Twine &Msg, 185 ArrayRef<SMRange> Ranges = None) { 186 return Parser.Warning(L, Msg, Ranges); 187 } 188 bool Error(SMLoc L, const Twine &Msg, 189 ArrayRef<SMRange> Ranges = None) { 190 return Parser.Error(L, Msg, Ranges); 191 } 192 193 int tryParseRegister(); 194 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 195 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 196 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 197 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 198 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 199 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 200 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 201 unsigned &ShiftAmount); 202 bool parseLiteralValues(unsigned Size, SMLoc L); 203 bool parseDirectiveThumb(SMLoc L); 204 bool parseDirectiveARM(SMLoc L); 205 bool parseDirectiveThumbFunc(SMLoc L); 206 bool parseDirectiveCode(SMLoc L); 207 bool parseDirectiveSyntax(SMLoc L); 208 bool parseDirectiveReq(StringRef Name, SMLoc L); 209 bool parseDirectiveUnreq(SMLoc L); 210 bool parseDirectiveArch(SMLoc L); 211 bool parseDirectiveEabiAttr(SMLoc L); 212 bool parseDirectiveCPU(SMLoc L); 213 bool parseDirectiveFPU(SMLoc L); 214 bool parseDirectiveFnStart(SMLoc L); 215 bool parseDirectiveFnEnd(SMLoc L); 216 bool parseDirectiveCantUnwind(SMLoc L); 217 bool parseDirectivePersonality(SMLoc L); 218 bool parseDirectiveHandlerData(SMLoc L); 219 bool parseDirectiveSetFP(SMLoc L); 220 bool parseDirectivePad(SMLoc L); 221 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 222 bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); 223 bool parseDirectiveLtorg(SMLoc L); 224 bool parseDirectiveEven(SMLoc L); 225 bool parseDirectivePersonalityIndex(SMLoc L); 226 bool parseDirectiveUnwindRaw(SMLoc L); 227 bool parseDirectiveTLSDescSeq(SMLoc L); 228 bool parseDirectiveMovSP(SMLoc L); 229 bool parseDirectiveObjectArch(SMLoc L); 230 bool parseDirectiveArchExtension(SMLoc L); 231 bool parseDirectiveAlign(SMLoc L); 232 233 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 234 bool &CarrySetting, unsigned &ProcessorIMod, 235 StringRef &ITMask); 236 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 237 bool &CanAcceptCarrySet, 238 bool &CanAcceptPredicationCode); 239 240 bool isThumb() const { 241 // FIXME: Can tablegen auto-generate this? 242 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 243 } 244 bool isThumbOne() const { 245 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 246 } 247 bool isThumbTwo() const { 248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 249 } 250 bool hasThumb() const { 251 return STI.getFeatureBits() & ARM::HasV4TOps; 252 } 253 bool hasV6Ops() const { 254 return STI.getFeatureBits() & ARM::HasV6Ops; 255 } 256 bool hasV6MOps() const { 257 return STI.getFeatureBits() & ARM::HasV6MOps; 258 } 259 bool hasV7Ops() const { 260 return STI.getFeatureBits() & ARM::HasV7Ops; 261 } 262 bool hasV8Ops() const { 263 return STI.getFeatureBits() & ARM::HasV8Ops; 264 } 265 bool hasARM() const { 266 return !(STI.getFeatureBits() & ARM::FeatureNoARM); 267 } 268 269 void SwitchMode() { 270 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 271 setAvailableFeatures(FB); 272 } 273 bool isMClass() const { 274 return STI.getFeatureBits() & ARM::FeatureMClass; 275 } 276 277 /// @name Auto-generated Match Functions 278 /// { 279 280 #define GET_ASSEMBLER_HEADER 281 #include "ARMGenAsmMatcher.inc" 282 283 /// } 284 285 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 286 OperandMatchResultTy parseCoprocNumOperand( 287 SmallVectorImpl<MCParsedAsmOperand*>&); 288 OperandMatchResultTy parseCoprocRegOperand( 289 SmallVectorImpl<MCParsedAsmOperand*>&); 290 OperandMatchResultTy parseCoprocOptionOperand( 291 SmallVectorImpl<MCParsedAsmOperand*>&); 292 OperandMatchResultTy parseMemBarrierOptOperand( 293 SmallVectorImpl<MCParsedAsmOperand*>&); 294 OperandMatchResultTy parseInstSyncBarrierOptOperand( 295 SmallVectorImpl<MCParsedAsmOperand*>&); 296 OperandMatchResultTy parseProcIFlagsOperand( 297 SmallVectorImpl<MCParsedAsmOperand*>&); 298 OperandMatchResultTy parseMSRMaskOperand( 299 SmallVectorImpl<MCParsedAsmOperand*>&); 300 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 301 StringRef Op, int Low, int High); 302 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 303 return parsePKHImm(O, "lsl", 0, 31); 304 } 305 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 306 return parsePKHImm(O, "asr", 1, 32); 307 } 308 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 309 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 310 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 311 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 312 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 313 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 314 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 315 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 316 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 317 SMLoc &EndLoc); 318 319 // Asm Match Converter Methods 320 void cvtThumbMultiply(MCInst &Inst, 321 const SmallVectorImpl<MCParsedAsmOperand*> &); 322 void cvtThumbBranches(MCInst &Inst, 323 const SmallVectorImpl<MCParsedAsmOperand*> &); 324 325 bool validateInstruction(MCInst &Inst, 326 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 327 bool processInstruction(MCInst &Inst, 328 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 329 bool shouldOmitCCOutOperand(StringRef Mnemonic, 330 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 331 bool shouldOmitPredicateOperand(StringRef Mnemonic, 332 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 333 public: 334 enum ARMMatchResultTy { 335 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 336 Match_RequiresNotITBlock, 337 Match_RequiresV6, 338 Match_RequiresThumb2, 339 #define GET_OPERAND_DIAGNOSTIC_TYPES 340 #include "ARMGenAsmMatcher.inc" 341 342 }; 343 344 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, 345 const MCInstrInfo &MII) 346 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) { 347 MCAsmParserExtension::Initialize(_Parser); 348 349 // Cache the MCRegisterInfo. 350 MRI = getContext().getRegisterInfo(); 351 352 // Initialize the set of available features. 353 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 354 355 // Not in an ITBlock to start with. 356 ITState.CurPosition = ~0U; 357 358 NextSymbolIsThumb = false; 359 } 360 361 // Implementation of the MCTargetAsmParser interface: 362 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 363 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 364 SMLoc NameLoc, 365 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 366 bool ParseDirective(AsmToken DirectiveID); 367 368 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); 369 unsigned checkTargetMatchPredicate(MCInst &Inst); 370 371 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 372 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 373 MCStreamer &Out, unsigned &ErrorInfo, 374 bool MatchingInlineAsm); 375 void onLabelParsed(MCSymbol *Symbol); 376 }; 377 } // end anonymous namespace 378 379 namespace { 380 381 /// ARMOperand - Instances of this class represent a parsed ARM machine 382 /// operand. 383 class ARMOperand : public MCParsedAsmOperand { 384 enum KindTy { 385 k_CondCode, 386 k_CCOut, 387 k_ITCondMask, 388 k_CoprocNum, 389 k_CoprocReg, 390 k_CoprocOption, 391 k_Immediate, 392 k_MemBarrierOpt, 393 k_InstSyncBarrierOpt, 394 k_Memory, 395 k_PostIndexRegister, 396 k_MSRMask, 397 k_ProcIFlags, 398 k_VectorIndex, 399 k_Register, 400 k_RegisterList, 401 k_DPRRegisterList, 402 k_SPRRegisterList, 403 k_VectorList, 404 k_VectorListAllLanes, 405 k_VectorListIndexed, 406 k_ShiftedRegister, 407 k_ShiftedImmediate, 408 k_ShifterImmediate, 409 k_RotateImmediate, 410 k_BitfieldDescriptor, 411 k_Token 412 } Kind; 413 414 SMLoc StartLoc, EndLoc; 415 SmallVector<unsigned, 8> Registers; 416 417 struct CCOp { 418 ARMCC::CondCodes Val; 419 }; 420 421 struct CopOp { 422 unsigned Val; 423 }; 424 425 struct CoprocOptionOp { 426 unsigned Val; 427 }; 428 429 struct ITMaskOp { 430 unsigned Mask:4; 431 }; 432 433 struct MBOptOp { 434 ARM_MB::MemBOpt Val; 435 }; 436 437 struct ISBOptOp { 438 ARM_ISB::InstSyncBOpt Val; 439 }; 440 441 struct IFlagsOp { 442 ARM_PROC::IFlags Val; 443 }; 444 445 struct MMaskOp { 446 unsigned Val; 447 }; 448 449 struct TokOp { 450 const char *Data; 451 unsigned Length; 452 }; 453 454 struct RegOp { 455 unsigned RegNum; 456 }; 457 458 // A vector register list is a sequential list of 1 to 4 registers. 459 struct VectorListOp { 460 unsigned RegNum; 461 unsigned Count; 462 unsigned LaneIndex; 463 bool isDoubleSpaced; 464 }; 465 466 struct VectorIndexOp { 467 unsigned Val; 468 }; 469 470 struct ImmOp { 471 const MCExpr *Val; 472 }; 473 474 /// Combined record for all forms of ARM address expressions. 475 struct MemoryOp { 476 unsigned BaseRegNum; 477 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 478 // was specified. 479 const MCConstantExpr *OffsetImm; // Offset immediate value 480 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 481 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 482 unsigned ShiftImm; // shift for OffsetReg. 483 unsigned Alignment; // 0 = no alignment specified 484 // n = alignment in bytes (2, 4, 8, 16, or 32) 485 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 486 }; 487 488 struct PostIdxRegOp { 489 unsigned RegNum; 490 bool isAdd; 491 ARM_AM::ShiftOpc ShiftTy; 492 unsigned ShiftImm; 493 }; 494 495 struct ShifterImmOp { 496 bool isASR; 497 unsigned Imm; 498 }; 499 500 struct RegShiftedRegOp { 501 ARM_AM::ShiftOpc ShiftTy; 502 unsigned SrcReg; 503 unsigned ShiftReg; 504 unsigned ShiftImm; 505 }; 506 507 struct RegShiftedImmOp { 508 ARM_AM::ShiftOpc ShiftTy; 509 unsigned SrcReg; 510 unsigned ShiftImm; 511 }; 512 513 struct RotImmOp { 514 unsigned Imm; 515 }; 516 517 struct BitfieldOp { 518 unsigned LSB; 519 unsigned Width; 520 }; 521 522 union { 523 struct CCOp CC; 524 struct CopOp Cop; 525 struct CoprocOptionOp CoprocOption; 526 struct MBOptOp MBOpt; 527 struct ISBOptOp ISBOpt; 528 struct ITMaskOp ITMask; 529 struct IFlagsOp IFlags; 530 struct MMaskOp MMask; 531 struct TokOp Tok; 532 struct RegOp Reg; 533 struct VectorListOp VectorList; 534 struct VectorIndexOp VectorIndex; 535 struct ImmOp Imm; 536 struct MemoryOp Memory; 537 struct PostIdxRegOp PostIdxReg; 538 struct ShifterImmOp ShifterImm; 539 struct RegShiftedRegOp RegShiftedReg; 540 struct RegShiftedImmOp RegShiftedImm; 541 struct RotImmOp RotImm; 542 struct BitfieldOp Bitfield; 543 }; 544 545 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 546 public: 547 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 548 Kind = o.Kind; 549 StartLoc = o.StartLoc; 550 EndLoc = o.EndLoc; 551 switch (Kind) { 552 case k_CondCode: 553 CC = o.CC; 554 break; 555 case k_ITCondMask: 556 ITMask = o.ITMask; 557 break; 558 case k_Token: 559 Tok = o.Tok; 560 break; 561 case k_CCOut: 562 case k_Register: 563 Reg = o.Reg; 564 break; 565 case k_RegisterList: 566 case k_DPRRegisterList: 567 case k_SPRRegisterList: 568 Registers = o.Registers; 569 break; 570 case k_VectorList: 571 case k_VectorListAllLanes: 572 case k_VectorListIndexed: 573 VectorList = o.VectorList; 574 break; 575 case k_CoprocNum: 576 case k_CoprocReg: 577 Cop = o.Cop; 578 break; 579 case k_CoprocOption: 580 CoprocOption = o.CoprocOption; 581 break; 582 case k_Immediate: 583 Imm = o.Imm; 584 break; 585 case k_MemBarrierOpt: 586 MBOpt = o.MBOpt; 587 break; 588 case k_InstSyncBarrierOpt: 589 ISBOpt = o.ISBOpt; 590 case k_Memory: 591 Memory = o.Memory; 592 break; 593 case k_PostIndexRegister: 594 PostIdxReg = o.PostIdxReg; 595 break; 596 case k_MSRMask: 597 MMask = o.MMask; 598 break; 599 case k_ProcIFlags: 600 IFlags = o.IFlags; 601 break; 602 case k_ShifterImmediate: 603 ShifterImm = o.ShifterImm; 604 break; 605 case k_ShiftedRegister: 606 RegShiftedReg = o.RegShiftedReg; 607 break; 608 case k_ShiftedImmediate: 609 RegShiftedImm = o.RegShiftedImm; 610 break; 611 case k_RotateImmediate: 612 RotImm = o.RotImm; 613 break; 614 case k_BitfieldDescriptor: 615 Bitfield = o.Bitfield; 616 break; 617 case k_VectorIndex: 618 VectorIndex = o.VectorIndex; 619 break; 620 } 621 } 622 623 /// getStartLoc - Get the location of the first token of this operand. 624 SMLoc getStartLoc() const { return StartLoc; } 625 /// getEndLoc - Get the location of the last token of this operand. 626 SMLoc getEndLoc() const { return EndLoc; } 627 /// getLocRange - Get the range between the first and last token of this 628 /// operand. 629 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 630 631 ARMCC::CondCodes getCondCode() const { 632 assert(Kind == k_CondCode && "Invalid access!"); 633 return CC.Val; 634 } 635 636 unsigned getCoproc() const { 637 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 638 return Cop.Val; 639 } 640 641 StringRef getToken() const { 642 assert(Kind == k_Token && "Invalid access!"); 643 return StringRef(Tok.Data, Tok.Length); 644 } 645 646 unsigned getReg() const { 647 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 648 return Reg.RegNum; 649 } 650 651 const SmallVectorImpl<unsigned> &getRegList() const { 652 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 653 Kind == k_SPRRegisterList) && "Invalid access!"); 654 return Registers; 655 } 656 657 const MCExpr *getImm() const { 658 assert(isImm() && "Invalid access!"); 659 return Imm.Val; 660 } 661 662 unsigned getVectorIndex() const { 663 assert(Kind == k_VectorIndex && "Invalid access!"); 664 return VectorIndex.Val; 665 } 666 667 ARM_MB::MemBOpt getMemBarrierOpt() const { 668 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 669 return MBOpt.Val; 670 } 671 672 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 673 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 674 return ISBOpt.Val; 675 } 676 677 ARM_PROC::IFlags getProcIFlags() const { 678 assert(Kind == k_ProcIFlags && "Invalid access!"); 679 return IFlags.Val; 680 } 681 682 unsigned getMSRMask() const { 683 assert(Kind == k_MSRMask && "Invalid access!"); 684 return MMask.Val; 685 } 686 687 bool isCoprocNum() const { return Kind == k_CoprocNum; } 688 bool isCoprocReg() const { return Kind == k_CoprocReg; } 689 bool isCoprocOption() const { return Kind == k_CoprocOption; } 690 bool isCondCode() const { return Kind == k_CondCode; } 691 bool isCCOut() const { return Kind == k_CCOut; } 692 bool isITMask() const { return Kind == k_ITCondMask; } 693 bool isITCondCode() const { return Kind == k_CondCode; } 694 bool isImm() const { return Kind == k_Immediate; } 695 // checks whether this operand is an unsigned offset which fits is a field 696 // of specified width and scaled by a specific number of bits 697 template<unsigned width, unsigned scale> 698 bool isUnsignedOffset() const { 699 if (!isImm()) return false; 700 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 701 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 702 int64_t Val = CE->getValue(); 703 int64_t Align = 1LL << scale; 704 int64_t Max = Align * ((1LL << width) - 1); 705 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); 706 } 707 return false; 708 } 709 // checks whether this operand is an signed offset which fits is a field 710 // of specified width and scaled by a specific number of bits 711 template<unsigned width, unsigned scale> 712 bool isSignedOffset() const { 713 if (!isImm()) return false; 714 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 715 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 716 int64_t Val = CE->getValue(); 717 int64_t Align = 1LL << scale; 718 int64_t Max = Align * ((1LL << (width-1)) - 1); 719 int64_t Min = -Align * (1LL << (width-1)); 720 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); 721 } 722 return false; 723 } 724 725 // checks whether this operand is a memory operand computed as an offset 726 // applied to PC. the offset may have 8 bits of magnitude and is represented 727 // with two bits of shift. textually it may be either [pc, #imm], #imm or 728 // relocable expression... 729 bool isThumbMemPC() const { 730 int64_t Val = 0; 731 if (isImm()) { 732 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); 734 if (!CE) return false; 735 Val = CE->getValue(); 736 } 737 else if (isMem()) { 738 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; 739 if(Memory.BaseRegNum != ARM::PC) return false; 740 Val = Memory.OffsetImm->getValue(); 741 } 742 else return false; 743 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); 744 } 745 bool isFPImm() const { 746 if (!isImm()) return false; 747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 748 if (!CE) return false; 749 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 750 return Val != -1; 751 } 752 bool isFBits16() const { 753 if (!isImm()) return false; 754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 755 if (!CE) return false; 756 int64_t Value = CE->getValue(); 757 return Value >= 0 && Value <= 16; 758 } 759 bool isFBits32() const { 760 if (!isImm()) return false; 761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 762 if (!CE) return false; 763 int64_t Value = CE->getValue(); 764 return Value >= 1 && Value <= 32; 765 } 766 bool isImm8s4() const { 767 if (!isImm()) return false; 768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 769 if (!CE) return false; 770 int64_t Value = CE->getValue(); 771 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 772 } 773 bool isImm0_1020s4() const { 774 if (!isImm()) return false; 775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 776 if (!CE) return false; 777 int64_t Value = CE->getValue(); 778 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 779 } 780 bool isImm0_508s4() const { 781 if (!isImm()) return false; 782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 783 if (!CE) return false; 784 int64_t Value = CE->getValue(); 785 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 786 } 787 bool isImm0_508s4Neg() const { 788 if (!isImm()) return false; 789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 790 if (!CE) return false; 791 int64_t Value = -CE->getValue(); 792 // explicitly exclude zero. we want that to use the normal 0_508 version. 793 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 794 } 795 bool isImm0_239() const { 796 if (!isImm()) return false; 797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 798 if (!CE) return false; 799 int64_t Value = CE->getValue(); 800 return Value >= 0 && Value < 240; 801 } 802 bool isImm0_255() const { 803 if (!isImm()) return false; 804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 805 if (!CE) return false; 806 int64_t Value = CE->getValue(); 807 return Value >= 0 && Value < 256; 808 } 809 bool isImm0_4095() const { 810 if (!isImm()) return false; 811 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 812 if (!CE) return false; 813 int64_t Value = CE->getValue(); 814 return Value >= 0 && Value < 4096; 815 } 816 bool isImm0_4095Neg() const { 817 if (!isImm()) return false; 818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 819 if (!CE) return false; 820 int64_t Value = -CE->getValue(); 821 return Value > 0 && Value < 4096; 822 } 823 bool isImm0_1() const { 824 if (!isImm()) return false; 825 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 826 if (!CE) return false; 827 int64_t Value = CE->getValue(); 828 return Value >= 0 && Value < 2; 829 } 830 bool isImm0_3() const { 831 if (!isImm()) return false; 832 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 833 if (!CE) return false; 834 int64_t Value = CE->getValue(); 835 return Value >= 0 && Value < 4; 836 } 837 bool isImm0_7() const { 838 if (!isImm()) return false; 839 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 840 if (!CE) return false; 841 int64_t Value = CE->getValue(); 842 return Value >= 0 && Value < 8; 843 } 844 bool isImm0_15() const { 845 if (!isImm()) return false; 846 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 847 if (!CE) return false; 848 int64_t Value = CE->getValue(); 849 return Value >= 0 && Value < 16; 850 } 851 bool isImm0_31() const { 852 if (!isImm()) return false; 853 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 854 if (!CE) return false; 855 int64_t Value = CE->getValue(); 856 return Value >= 0 && Value < 32; 857 } 858 bool isImm0_63() const { 859 if (!isImm()) return false; 860 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 861 if (!CE) return false; 862 int64_t Value = CE->getValue(); 863 return Value >= 0 && Value < 64; 864 } 865 bool isImm8() const { 866 if (!isImm()) return false; 867 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 868 if (!CE) return false; 869 int64_t Value = CE->getValue(); 870 return Value == 8; 871 } 872 bool isImm16() const { 873 if (!isImm()) return false; 874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 875 if (!CE) return false; 876 int64_t Value = CE->getValue(); 877 return Value == 16; 878 } 879 bool isImm32() const { 880 if (!isImm()) return false; 881 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 882 if (!CE) return false; 883 int64_t Value = CE->getValue(); 884 return Value == 32; 885 } 886 bool isShrImm8() const { 887 if (!isImm()) return false; 888 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 889 if (!CE) return false; 890 int64_t Value = CE->getValue(); 891 return Value > 0 && Value <= 8; 892 } 893 bool isShrImm16() const { 894 if (!isImm()) return false; 895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 896 if (!CE) return false; 897 int64_t Value = CE->getValue(); 898 return Value > 0 && Value <= 16; 899 } 900 bool isShrImm32() const { 901 if (!isImm()) return false; 902 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 903 if (!CE) return false; 904 int64_t Value = CE->getValue(); 905 return Value > 0 && Value <= 32; 906 } 907 bool isShrImm64() const { 908 if (!isImm()) return false; 909 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 910 if (!CE) return false; 911 int64_t Value = CE->getValue(); 912 return Value > 0 && Value <= 64; 913 } 914 bool isImm1_7() const { 915 if (!isImm()) return false; 916 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 917 if (!CE) return false; 918 int64_t Value = CE->getValue(); 919 return Value > 0 && Value < 8; 920 } 921 bool isImm1_15() const { 922 if (!isImm()) return false; 923 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 924 if (!CE) return false; 925 int64_t Value = CE->getValue(); 926 return Value > 0 && Value < 16; 927 } 928 bool isImm1_31() const { 929 if (!isImm()) return false; 930 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 931 if (!CE) return false; 932 int64_t Value = CE->getValue(); 933 return Value > 0 && Value < 32; 934 } 935 bool isImm1_16() const { 936 if (!isImm()) return false; 937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 938 if (!CE) return false; 939 int64_t Value = CE->getValue(); 940 return Value > 0 && Value < 17; 941 } 942 bool isImm1_32() const { 943 if (!isImm()) return false; 944 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 945 if (!CE) return false; 946 int64_t Value = CE->getValue(); 947 return Value > 0 && Value < 33; 948 } 949 bool isImm0_32() const { 950 if (!isImm()) return false; 951 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 952 if (!CE) return false; 953 int64_t Value = CE->getValue(); 954 return Value >= 0 && Value < 33; 955 } 956 bool isImm0_65535() const { 957 if (!isImm()) return false; 958 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 959 if (!CE) return false; 960 int64_t Value = CE->getValue(); 961 return Value >= 0 && Value < 65536; 962 } 963 bool isImm256_65535Expr() const { 964 if (!isImm()) return false; 965 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 966 // If it's not a constant expression, it'll generate a fixup and be 967 // handled later. 968 if (!CE) return true; 969 int64_t Value = CE->getValue(); 970 return Value >= 256 && Value < 65536; 971 } 972 bool isImm0_65535Expr() const { 973 if (!isImm()) return false; 974 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 975 // If it's not a constant expression, it'll generate a fixup and be 976 // handled later. 977 if (!CE) return true; 978 int64_t Value = CE->getValue(); 979 return Value >= 0 && Value < 65536; 980 } 981 bool isImm24bit() const { 982 if (!isImm()) return false; 983 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 984 if (!CE) return false; 985 int64_t Value = CE->getValue(); 986 return Value >= 0 && Value <= 0xffffff; 987 } 988 bool isImmThumbSR() const { 989 if (!isImm()) return false; 990 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 991 if (!CE) return false; 992 int64_t Value = CE->getValue(); 993 return Value > 0 && Value < 33; 994 } 995 bool isPKHLSLImm() const { 996 if (!isImm()) return false; 997 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 998 if (!CE) return false; 999 int64_t Value = CE->getValue(); 1000 return Value >= 0 && Value < 32; 1001 } 1002 bool isPKHASRImm() const { 1003 if (!isImm()) return false; 1004 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1005 if (!CE) return false; 1006 int64_t Value = CE->getValue(); 1007 return Value > 0 && Value <= 32; 1008 } 1009 bool isAdrLabel() const { 1010 // If we have an immediate that's not a constant, treat it as a label 1011 // reference needing a fixup. If it is a constant, but it can't fit 1012 // into shift immediate encoding, we reject it. 1013 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 1014 else return (isARMSOImm() || isARMSOImmNeg()); 1015 } 1016 bool isARMSOImm() const { 1017 if (!isImm()) return false; 1018 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1019 if (!CE) return false; 1020 int64_t Value = CE->getValue(); 1021 return ARM_AM::getSOImmVal(Value) != -1; 1022 } 1023 bool isARMSOImmNot() const { 1024 if (!isImm()) return false; 1025 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1026 if (!CE) return false; 1027 int64_t Value = CE->getValue(); 1028 return ARM_AM::getSOImmVal(~Value) != -1; 1029 } 1030 bool isARMSOImmNeg() const { 1031 if (!isImm()) return false; 1032 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1033 if (!CE) return false; 1034 int64_t Value = CE->getValue(); 1035 // Only use this when not representable as a plain so_imm. 1036 return ARM_AM::getSOImmVal(Value) == -1 && 1037 ARM_AM::getSOImmVal(-Value) != -1; 1038 } 1039 bool isT2SOImm() const { 1040 if (!isImm()) return false; 1041 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1042 if (!CE) return false; 1043 int64_t Value = CE->getValue(); 1044 return ARM_AM::getT2SOImmVal(Value) != -1; 1045 } 1046 bool isT2SOImmNot() const { 1047 if (!isImm()) return false; 1048 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1049 if (!CE) return false; 1050 int64_t Value = CE->getValue(); 1051 return ARM_AM::getT2SOImmVal(Value) == -1 && 1052 ARM_AM::getT2SOImmVal(~Value) != -1; 1053 } 1054 bool isT2SOImmNeg() const { 1055 if (!isImm()) return false; 1056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1057 if (!CE) return false; 1058 int64_t Value = CE->getValue(); 1059 // Only use this when not representable as a plain so_imm. 1060 return ARM_AM::getT2SOImmVal(Value) == -1 && 1061 ARM_AM::getT2SOImmVal(-Value) != -1; 1062 } 1063 bool isSetEndImm() const { 1064 if (!isImm()) return false; 1065 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1066 if (!CE) return false; 1067 int64_t Value = CE->getValue(); 1068 return Value == 1 || Value == 0; 1069 } 1070 bool isReg() const { return Kind == k_Register; } 1071 bool isRegList() const { return Kind == k_RegisterList; } 1072 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 1073 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 1074 bool isToken() const { return Kind == k_Token; } 1075 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 1076 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 1077 bool isMem() const { return Kind == k_Memory; } 1078 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 1079 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 1080 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 1081 bool isRotImm() const { return Kind == k_RotateImmediate; } 1082 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 1083 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 1084 bool isPostIdxReg() const { 1085 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 1086 } 1087 bool isMemNoOffset(bool alignOK = false) const { 1088 if (!isMem()) 1089 return false; 1090 // No offset of any kind. 1091 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 1092 (alignOK || Memory.Alignment == 0); 1093 } 1094 bool isMemPCRelImm12() const { 1095 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1096 return false; 1097 // Base register must be PC. 1098 if (Memory.BaseRegNum != ARM::PC) 1099 return false; 1100 // Immediate offset in range [-4095, 4095]. 1101 if (!Memory.OffsetImm) return true; 1102 int64_t Val = Memory.OffsetImm->getValue(); 1103 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1104 } 1105 bool isAlignedMemory() const { 1106 return isMemNoOffset(true); 1107 } 1108 bool isAddrMode2() const { 1109 if (!isMem() || Memory.Alignment != 0) return false; 1110 // Check for register offset. 1111 if (Memory.OffsetRegNum) return true; 1112 // Immediate offset in range [-4095, 4095]. 1113 if (!Memory.OffsetImm) return true; 1114 int64_t Val = Memory.OffsetImm->getValue(); 1115 return Val > -4096 && Val < 4096; 1116 } 1117 bool isAM2OffsetImm() const { 1118 if (!isImm()) return false; 1119 // Immediate offset in range [-4095, 4095]. 1120 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1121 if (!CE) return false; 1122 int64_t Val = CE->getValue(); 1123 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 1124 } 1125 bool isAddrMode3() const { 1126 // If we have an immediate that's not a constant, treat it as a label 1127 // reference needing a fixup. If it is a constant, it's something else 1128 // and we reject it. 1129 if (isImm() && !isa<MCConstantExpr>(getImm())) 1130 return true; 1131 if (!isMem() || Memory.Alignment != 0) return false; 1132 // No shifts are legal for AM3. 1133 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1134 // Check for register offset. 1135 if (Memory.OffsetRegNum) return true; 1136 // Immediate offset in range [-255, 255]. 1137 if (!Memory.OffsetImm) return true; 1138 int64_t Val = Memory.OffsetImm->getValue(); 1139 // The #-0 offset is encoded as INT32_MIN, and we have to check 1140 // for this too. 1141 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1142 } 1143 bool isAM3Offset() const { 1144 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1145 return false; 1146 if (Kind == k_PostIndexRegister) 1147 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1148 // Immediate offset in range [-255, 255]. 1149 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1150 if (!CE) return false; 1151 int64_t Val = CE->getValue(); 1152 // Special case, #-0 is INT32_MIN. 1153 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1154 } 1155 bool isAddrMode5() const { 1156 // If we have an immediate that's not a constant, treat it as a label 1157 // reference needing a fixup. If it is a constant, it's something else 1158 // and we reject it. 1159 if (isImm() && !isa<MCConstantExpr>(getImm())) 1160 return true; 1161 if (!isMem() || Memory.Alignment != 0) return false; 1162 // Check for register offset. 1163 if (Memory.OffsetRegNum) return false; 1164 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1165 if (!Memory.OffsetImm) return true; 1166 int64_t Val = Memory.OffsetImm->getValue(); 1167 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1168 Val == INT32_MIN; 1169 } 1170 bool isMemTBB() const { 1171 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1172 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1173 return false; 1174 return true; 1175 } 1176 bool isMemTBH() const { 1177 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1178 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1179 Memory.Alignment != 0 ) 1180 return false; 1181 return true; 1182 } 1183 bool isMemRegOffset() const { 1184 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1185 return false; 1186 return true; 1187 } 1188 bool isT2MemRegOffset() const { 1189 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1190 Memory.Alignment != 0) 1191 return false; 1192 // Only lsl #{0, 1, 2, 3} allowed. 1193 if (Memory.ShiftType == ARM_AM::no_shift) 1194 return true; 1195 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1196 return false; 1197 return true; 1198 } 1199 bool isMemThumbRR() const { 1200 // Thumb reg+reg addressing is simple. Just two registers, a base and 1201 // an offset. No shifts, negations or any other complicating factors. 1202 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1203 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1204 return false; 1205 return isARMLowRegister(Memory.BaseRegNum) && 1206 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1207 } 1208 bool isMemThumbRIs4() const { 1209 if (!isMem() || Memory.OffsetRegNum != 0 || 1210 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1211 return false; 1212 // Immediate offset, multiple of 4 in range [0, 124]. 1213 if (!Memory.OffsetImm) return true; 1214 int64_t Val = Memory.OffsetImm->getValue(); 1215 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1216 } 1217 bool isMemThumbRIs2() const { 1218 if (!isMem() || Memory.OffsetRegNum != 0 || 1219 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1220 return false; 1221 // Immediate offset, multiple of 4 in range [0, 62]. 1222 if (!Memory.OffsetImm) return true; 1223 int64_t Val = Memory.OffsetImm->getValue(); 1224 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1225 } 1226 bool isMemThumbRIs1() const { 1227 if (!isMem() || Memory.OffsetRegNum != 0 || 1228 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1229 return false; 1230 // Immediate offset in range [0, 31]. 1231 if (!Memory.OffsetImm) return true; 1232 int64_t Val = Memory.OffsetImm->getValue(); 1233 return Val >= 0 && Val <= 31; 1234 } 1235 bool isMemThumbSPI() const { 1236 if (!isMem() || Memory.OffsetRegNum != 0 || 1237 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1238 return false; 1239 // Immediate offset, multiple of 4 in range [0, 1020]. 1240 if (!Memory.OffsetImm) return true; 1241 int64_t Val = Memory.OffsetImm->getValue(); 1242 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1243 } 1244 bool isMemImm8s4Offset() const { 1245 // If we have an immediate that's not a constant, treat it as a label 1246 // reference needing a fixup. If it is a constant, it's something else 1247 // and we reject it. 1248 if (isImm() && !isa<MCConstantExpr>(getImm())) 1249 return true; 1250 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1251 return false; 1252 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1253 if (!Memory.OffsetImm) return true; 1254 int64_t Val = Memory.OffsetImm->getValue(); 1255 // Special case, #-0 is INT32_MIN. 1256 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1257 } 1258 bool isMemImm0_1020s4Offset() const { 1259 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1260 return false; 1261 // Immediate offset a multiple of 4 in range [0, 1020]. 1262 if (!Memory.OffsetImm) return true; 1263 int64_t Val = Memory.OffsetImm->getValue(); 1264 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1265 } 1266 bool isMemImm8Offset() const { 1267 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1268 return false; 1269 // Base reg of PC isn't allowed for these encodings. 1270 if (Memory.BaseRegNum == ARM::PC) return false; 1271 // Immediate offset in range [-255, 255]. 1272 if (!Memory.OffsetImm) return true; 1273 int64_t Val = Memory.OffsetImm->getValue(); 1274 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1275 } 1276 bool isMemPosImm8Offset() const { 1277 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1278 return false; 1279 // Immediate offset in range [0, 255]. 1280 if (!Memory.OffsetImm) return true; 1281 int64_t Val = Memory.OffsetImm->getValue(); 1282 return Val >= 0 && Val < 256; 1283 } 1284 bool isMemNegImm8Offset() const { 1285 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1286 return false; 1287 // Base reg of PC isn't allowed for these encodings. 1288 if (Memory.BaseRegNum == ARM::PC) return false; 1289 // Immediate offset in range [-255, -1]. 1290 if (!Memory.OffsetImm) return false; 1291 int64_t Val = Memory.OffsetImm->getValue(); 1292 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1293 } 1294 bool isMemUImm12Offset() const { 1295 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1296 return false; 1297 // Immediate offset in range [0, 4095]. 1298 if (!Memory.OffsetImm) return true; 1299 int64_t Val = Memory.OffsetImm->getValue(); 1300 return (Val >= 0 && Val < 4096); 1301 } 1302 bool isMemImm12Offset() const { 1303 // If we have an immediate that's not a constant, treat it as a label 1304 // reference needing a fixup. If it is a constant, it's something else 1305 // and we reject it. 1306 if (isImm() && !isa<MCConstantExpr>(getImm())) 1307 return true; 1308 1309 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1310 return false; 1311 // Immediate offset in range [-4095, 4095]. 1312 if (!Memory.OffsetImm) return true; 1313 int64_t Val = Memory.OffsetImm->getValue(); 1314 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1315 } 1316 bool isPostIdxImm8() const { 1317 if (!isImm()) return false; 1318 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1319 if (!CE) return false; 1320 int64_t Val = CE->getValue(); 1321 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1322 } 1323 bool isPostIdxImm8s4() const { 1324 if (!isImm()) return false; 1325 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1326 if (!CE) return false; 1327 int64_t Val = CE->getValue(); 1328 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1329 (Val == INT32_MIN); 1330 } 1331 1332 bool isMSRMask() const { return Kind == k_MSRMask; } 1333 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1334 1335 // NEON operands. 1336 bool isSingleSpacedVectorList() const { 1337 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1338 } 1339 bool isDoubleSpacedVectorList() const { 1340 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1341 } 1342 bool isVecListOneD() const { 1343 if (!isSingleSpacedVectorList()) return false; 1344 return VectorList.Count == 1; 1345 } 1346 1347 bool isVecListDPair() const { 1348 if (!isSingleSpacedVectorList()) return false; 1349 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1350 .contains(VectorList.RegNum)); 1351 } 1352 1353 bool isVecListThreeD() const { 1354 if (!isSingleSpacedVectorList()) return false; 1355 return VectorList.Count == 3; 1356 } 1357 1358 bool isVecListFourD() const { 1359 if (!isSingleSpacedVectorList()) return false; 1360 return VectorList.Count == 4; 1361 } 1362 1363 bool isVecListDPairSpaced() const { 1364 if (isSingleSpacedVectorList()) return false; 1365 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1366 .contains(VectorList.RegNum)); 1367 } 1368 1369 bool isVecListThreeQ() const { 1370 if (!isDoubleSpacedVectorList()) return false; 1371 return VectorList.Count == 3; 1372 } 1373 1374 bool isVecListFourQ() const { 1375 if (!isDoubleSpacedVectorList()) return false; 1376 return VectorList.Count == 4; 1377 } 1378 1379 bool isSingleSpacedVectorAllLanes() const { 1380 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1381 } 1382 bool isDoubleSpacedVectorAllLanes() const { 1383 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1384 } 1385 bool isVecListOneDAllLanes() const { 1386 if (!isSingleSpacedVectorAllLanes()) return false; 1387 return VectorList.Count == 1; 1388 } 1389 1390 bool isVecListDPairAllLanes() const { 1391 if (!isSingleSpacedVectorAllLanes()) return false; 1392 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1393 .contains(VectorList.RegNum)); 1394 } 1395 1396 bool isVecListDPairSpacedAllLanes() const { 1397 if (!isDoubleSpacedVectorAllLanes()) return false; 1398 return VectorList.Count == 2; 1399 } 1400 1401 bool isVecListThreeDAllLanes() const { 1402 if (!isSingleSpacedVectorAllLanes()) return false; 1403 return VectorList.Count == 3; 1404 } 1405 1406 bool isVecListThreeQAllLanes() const { 1407 if (!isDoubleSpacedVectorAllLanes()) return false; 1408 return VectorList.Count == 3; 1409 } 1410 1411 bool isVecListFourDAllLanes() const { 1412 if (!isSingleSpacedVectorAllLanes()) return false; 1413 return VectorList.Count == 4; 1414 } 1415 1416 bool isVecListFourQAllLanes() const { 1417 if (!isDoubleSpacedVectorAllLanes()) return false; 1418 return VectorList.Count == 4; 1419 } 1420 1421 bool isSingleSpacedVectorIndexed() const { 1422 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1423 } 1424 bool isDoubleSpacedVectorIndexed() const { 1425 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1426 } 1427 bool isVecListOneDByteIndexed() const { 1428 if (!isSingleSpacedVectorIndexed()) return false; 1429 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1430 } 1431 1432 bool isVecListOneDHWordIndexed() const { 1433 if (!isSingleSpacedVectorIndexed()) return false; 1434 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1435 } 1436 1437 bool isVecListOneDWordIndexed() const { 1438 if (!isSingleSpacedVectorIndexed()) return false; 1439 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1440 } 1441 1442 bool isVecListTwoDByteIndexed() const { 1443 if (!isSingleSpacedVectorIndexed()) return false; 1444 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1445 } 1446 1447 bool isVecListTwoDHWordIndexed() const { 1448 if (!isSingleSpacedVectorIndexed()) return false; 1449 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1450 } 1451 1452 bool isVecListTwoQWordIndexed() const { 1453 if (!isDoubleSpacedVectorIndexed()) return false; 1454 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1455 } 1456 1457 bool isVecListTwoQHWordIndexed() const { 1458 if (!isDoubleSpacedVectorIndexed()) return false; 1459 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1460 } 1461 1462 bool isVecListTwoDWordIndexed() const { 1463 if (!isSingleSpacedVectorIndexed()) return false; 1464 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1465 } 1466 1467 bool isVecListThreeDByteIndexed() const { 1468 if (!isSingleSpacedVectorIndexed()) return false; 1469 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1470 } 1471 1472 bool isVecListThreeDHWordIndexed() const { 1473 if (!isSingleSpacedVectorIndexed()) return false; 1474 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1475 } 1476 1477 bool isVecListThreeQWordIndexed() const { 1478 if (!isDoubleSpacedVectorIndexed()) return false; 1479 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1480 } 1481 1482 bool isVecListThreeQHWordIndexed() const { 1483 if (!isDoubleSpacedVectorIndexed()) return false; 1484 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1485 } 1486 1487 bool isVecListThreeDWordIndexed() const { 1488 if (!isSingleSpacedVectorIndexed()) return false; 1489 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1490 } 1491 1492 bool isVecListFourDByteIndexed() const { 1493 if (!isSingleSpacedVectorIndexed()) return false; 1494 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1495 } 1496 1497 bool isVecListFourDHWordIndexed() const { 1498 if (!isSingleSpacedVectorIndexed()) return false; 1499 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1500 } 1501 1502 bool isVecListFourQWordIndexed() const { 1503 if (!isDoubleSpacedVectorIndexed()) return false; 1504 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1505 } 1506 1507 bool isVecListFourQHWordIndexed() const { 1508 if (!isDoubleSpacedVectorIndexed()) return false; 1509 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1510 } 1511 1512 bool isVecListFourDWordIndexed() const { 1513 if (!isSingleSpacedVectorIndexed()) return false; 1514 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1515 } 1516 1517 bool isVectorIndex8() const { 1518 if (Kind != k_VectorIndex) return false; 1519 return VectorIndex.Val < 8; 1520 } 1521 bool isVectorIndex16() const { 1522 if (Kind != k_VectorIndex) return false; 1523 return VectorIndex.Val < 4; 1524 } 1525 bool isVectorIndex32() const { 1526 if (Kind != k_VectorIndex) return false; 1527 return VectorIndex.Val < 2; 1528 } 1529 1530 bool isNEONi8splat() const { 1531 if (!isImm()) return false; 1532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1533 // Must be a constant. 1534 if (!CE) return false; 1535 int64_t Value = CE->getValue(); 1536 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1537 // value. 1538 return Value >= 0 && Value < 256; 1539 } 1540 1541 bool isNEONi16splat() const { 1542 if (!isImm()) return false; 1543 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1544 // Must be a constant. 1545 if (!CE) return false; 1546 int64_t Value = CE->getValue(); 1547 // i16 value in the range [0,255] or [0x0100, 0xff00] 1548 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1549 } 1550 1551 bool isNEONi32splat() const { 1552 if (!isImm()) return false; 1553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1554 // Must be a constant. 1555 if (!CE) return false; 1556 int64_t Value = CE->getValue(); 1557 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1558 return (Value >= 0 && Value < 256) || 1559 (Value >= 0x0100 && Value <= 0xff00) || 1560 (Value >= 0x010000 && Value <= 0xff0000) || 1561 (Value >= 0x01000000 && Value <= 0xff000000); 1562 } 1563 1564 bool isNEONi32vmov() const { 1565 if (!isImm()) return false; 1566 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1567 // Must be a constant. 1568 if (!CE) return false; 1569 int64_t Value = CE->getValue(); 1570 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1571 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1572 return (Value >= 0 && Value < 256) || 1573 (Value >= 0x0100 && Value <= 0xff00) || 1574 (Value >= 0x010000 && Value <= 0xff0000) || 1575 (Value >= 0x01000000 && Value <= 0xff000000) || 1576 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1577 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1578 } 1579 bool isNEONi32vmovNeg() const { 1580 if (!isImm()) return false; 1581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1582 // Must be a constant. 1583 if (!CE) return false; 1584 int64_t Value = ~CE->getValue(); 1585 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1586 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1587 return (Value >= 0 && Value < 256) || 1588 (Value >= 0x0100 && Value <= 0xff00) || 1589 (Value >= 0x010000 && Value <= 0xff0000) || 1590 (Value >= 0x01000000 && Value <= 0xff000000) || 1591 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1592 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1593 } 1594 1595 bool isNEONi64splat() const { 1596 if (!isImm()) return false; 1597 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1598 // Must be a constant. 1599 if (!CE) return false; 1600 uint64_t Value = CE->getValue(); 1601 // i64 value with each byte being either 0 or 0xff. 1602 for (unsigned i = 0; i < 8; ++i) 1603 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1604 return true; 1605 } 1606 1607 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1608 // Add as immediates when possible. Null MCExpr = 0. 1609 if (Expr == 0) 1610 Inst.addOperand(MCOperand::CreateImm(0)); 1611 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1612 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1613 else 1614 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1615 } 1616 1617 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1618 assert(N == 2 && "Invalid number of operands!"); 1619 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1620 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1621 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1622 } 1623 1624 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1625 assert(N == 1 && "Invalid number of operands!"); 1626 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1627 } 1628 1629 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1630 assert(N == 1 && "Invalid number of operands!"); 1631 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1632 } 1633 1634 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1635 assert(N == 1 && "Invalid number of operands!"); 1636 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1637 } 1638 1639 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1640 assert(N == 1 && "Invalid number of operands!"); 1641 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1642 } 1643 1644 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1645 assert(N == 1 && "Invalid number of operands!"); 1646 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1647 } 1648 1649 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1650 assert(N == 1 && "Invalid number of operands!"); 1651 Inst.addOperand(MCOperand::CreateReg(getReg())); 1652 } 1653 1654 void addRegOperands(MCInst &Inst, unsigned N) const { 1655 assert(N == 1 && "Invalid number of operands!"); 1656 Inst.addOperand(MCOperand::CreateReg(getReg())); 1657 } 1658 1659 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1660 assert(N == 3 && "Invalid number of operands!"); 1661 assert(isRegShiftedReg() && 1662 "addRegShiftedRegOperands() on non-RegShiftedReg!"); 1663 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1664 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1665 Inst.addOperand(MCOperand::CreateImm( 1666 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1667 } 1668 1669 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1670 assert(N == 2 && "Invalid number of operands!"); 1671 assert(isRegShiftedImm() && 1672 "addRegShiftedImmOperands() on non-RegShiftedImm!"); 1673 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1674 // Shift of #32 is encoded as 0 where permitted 1675 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1676 Inst.addOperand(MCOperand::CreateImm( 1677 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1678 } 1679 1680 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1681 assert(N == 1 && "Invalid number of operands!"); 1682 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1683 ShifterImm.Imm)); 1684 } 1685 1686 void addRegListOperands(MCInst &Inst, unsigned N) const { 1687 assert(N == 1 && "Invalid number of operands!"); 1688 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1689 for (SmallVectorImpl<unsigned>::const_iterator 1690 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1691 Inst.addOperand(MCOperand::CreateReg(*I)); 1692 } 1693 1694 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1695 addRegListOperands(Inst, N); 1696 } 1697 1698 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1699 addRegListOperands(Inst, N); 1700 } 1701 1702 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1703 assert(N == 1 && "Invalid number of operands!"); 1704 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1705 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1706 } 1707 1708 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1709 assert(N == 1 && "Invalid number of operands!"); 1710 // Munge the lsb/width into a bitfield mask. 1711 unsigned lsb = Bitfield.LSB; 1712 unsigned width = Bitfield.Width; 1713 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1714 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1715 (32 - (lsb + width))); 1716 Inst.addOperand(MCOperand::CreateImm(Mask)); 1717 } 1718 1719 void addImmOperands(MCInst &Inst, unsigned N) const { 1720 assert(N == 1 && "Invalid number of operands!"); 1721 addExpr(Inst, getImm()); 1722 } 1723 1724 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1725 assert(N == 1 && "Invalid number of operands!"); 1726 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1727 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1728 } 1729 1730 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1731 assert(N == 1 && "Invalid number of operands!"); 1732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1733 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1734 } 1735 1736 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1737 assert(N == 1 && "Invalid number of operands!"); 1738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1739 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1740 Inst.addOperand(MCOperand::CreateImm(Val)); 1741 } 1742 1743 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1744 assert(N == 1 && "Invalid number of operands!"); 1745 // FIXME: We really want to scale the value here, but the LDRD/STRD 1746 // instruction don't encode operands that way yet. 1747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1748 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1749 } 1750 1751 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1752 assert(N == 1 && "Invalid number of operands!"); 1753 // The immediate is scaled by four in the encoding and is stored 1754 // in the MCInst as such. Lop off the low two bits here. 1755 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1756 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1757 } 1758 1759 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1760 assert(N == 1 && "Invalid number of operands!"); 1761 // The immediate is scaled by four in the encoding and is stored 1762 // in the MCInst as such. Lop off the low two bits here. 1763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1764 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1765 } 1766 1767 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1768 assert(N == 1 && "Invalid number of operands!"); 1769 // The immediate is scaled by four in the encoding and is stored 1770 // in the MCInst as such. Lop off the low two bits here. 1771 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1772 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1773 } 1774 1775 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1776 assert(N == 1 && "Invalid number of operands!"); 1777 // The constant encodes as the immediate-1, and we store in the instruction 1778 // the bits as encoded, so subtract off one here. 1779 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1780 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1781 } 1782 1783 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1784 assert(N == 1 && "Invalid number of operands!"); 1785 // The constant encodes as the immediate-1, and we store in the instruction 1786 // the bits as encoded, so subtract off one here. 1787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1788 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1789 } 1790 1791 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1792 assert(N == 1 && "Invalid number of operands!"); 1793 // The constant encodes as the immediate, except for 32, which encodes as 1794 // zero. 1795 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1796 unsigned Imm = CE->getValue(); 1797 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1798 } 1799 1800 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1801 assert(N == 1 && "Invalid number of operands!"); 1802 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1803 // the instruction as well. 1804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1805 int Val = CE->getValue(); 1806 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1807 } 1808 1809 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1810 assert(N == 1 && "Invalid number of operands!"); 1811 // The operand is actually a t2_so_imm, but we have its bitwise 1812 // negation in the assembly source, so twiddle it here. 1813 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1814 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1815 } 1816 1817 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1818 assert(N == 1 && "Invalid number of operands!"); 1819 // The operand is actually a t2_so_imm, but we have its 1820 // negation in the assembly source, so twiddle it here. 1821 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1822 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1823 } 1824 1825 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1826 assert(N == 1 && "Invalid number of operands!"); 1827 // The operand is actually an imm0_4095, but we have its 1828 // negation in the assembly source, so twiddle it here. 1829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1830 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1831 } 1832 1833 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { 1834 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { 1835 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2)); 1836 return; 1837 } 1838 1839 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1840 assert(SR && "Unknown value type!"); 1841 Inst.addOperand(MCOperand::CreateExpr(SR)); 1842 } 1843 1844 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { 1845 assert(N == 1 && "Invalid number of operands!"); 1846 if (isImm()) { 1847 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1848 if (CE) { 1849 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1850 return; 1851 } 1852 1853 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1854 assert(SR && "Unknown value type!"); 1855 Inst.addOperand(MCOperand::CreateExpr(SR)); 1856 return; 1857 } 1858 1859 assert(isMem() && "Unknown value type!"); 1860 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"); 1861 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue())); 1862 } 1863 1864 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1865 assert(N == 1 && "Invalid number of operands!"); 1866 // The operand is actually a so_imm, but we have its bitwise 1867 // negation in the assembly source, so twiddle it here. 1868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1869 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1870 } 1871 1872 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1873 assert(N == 1 && "Invalid number of operands!"); 1874 // The operand is actually a so_imm, but we have its 1875 // negation in the assembly source, so twiddle it here. 1876 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1877 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1878 } 1879 1880 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1881 assert(N == 1 && "Invalid number of operands!"); 1882 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1883 } 1884 1885 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 1886 assert(N == 1 && "Invalid number of operands!"); 1887 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); 1888 } 1889 1890 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1891 assert(N == 1 && "Invalid number of operands!"); 1892 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1893 } 1894 1895 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1896 assert(N == 1 && "Invalid number of operands!"); 1897 int32_t Imm = Memory.OffsetImm->getValue(); 1898 Inst.addOperand(MCOperand::CreateImm(Imm)); 1899 } 1900 1901 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1902 assert(N == 1 && "Invalid number of operands!"); 1903 assert(isImm() && "Not an immediate!"); 1904 1905 // If we have an immediate that's not a constant, treat it as a label 1906 // reference needing a fixup. 1907 if (!isa<MCConstantExpr>(getImm())) { 1908 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1909 return; 1910 } 1911 1912 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1913 int Val = CE->getValue(); 1914 Inst.addOperand(MCOperand::CreateImm(Val)); 1915 } 1916 1917 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1918 assert(N == 2 && "Invalid number of operands!"); 1919 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1920 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1921 } 1922 1923 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1924 assert(N == 3 && "Invalid number of operands!"); 1925 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1926 if (!Memory.OffsetRegNum) { 1927 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1928 // Special case for #-0 1929 if (Val == INT32_MIN) Val = 0; 1930 if (Val < 0) Val = -Val; 1931 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1932 } else { 1933 // For register offset, we encode the shift type and negation flag 1934 // here. 1935 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1936 Memory.ShiftImm, Memory.ShiftType); 1937 } 1938 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1939 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1940 Inst.addOperand(MCOperand::CreateImm(Val)); 1941 } 1942 1943 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1944 assert(N == 2 && "Invalid number of operands!"); 1945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1946 assert(CE && "non-constant AM2OffsetImm operand!"); 1947 int32_t Val = CE->getValue(); 1948 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1949 // Special case for #-0 1950 if (Val == INT32_MIN) Val = 0; 1951 if (Val < 0) Val = -Val; 1952 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1953 Inst.addOperand(MCOperand::CreateReg(0)); 1954 Inst.addOperand(MCOperand::CreateImm(Val)); 1955 } 1956 1957 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1958 assert(N == 3 && "Invalid number of operands!"); 1959 // If we have an immediate that's not a constant, treat it as a label 1960 // reference needing a fixup. If it is a constant, it's something else 1961 // and we reject it. 1962 if (isImm()) { 1963 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1964 Inst.addOperand(MCOperand::CreateReg(0)); 1965 Inst.addOperand(MCOperand::CreateImm(0)); 1966 return; 1967 } 1968 1969 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1970 if (!Memory.OffsetRegNum) { 1971 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1972 // Special case for #-0 1973 if (Val == INT32_MIN) Val = 0; 1974 if (Val < 0) Val = -Val; 1975 Val = ARM_AM::getAM3Opc(AddSub, Val); 1976 } else { 1977 // For register offset, we encode the shift type and negation flag 1978 // here. 1979 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1980 } 1981 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1982 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1983 Inst.addOperand(MCOperand::CreateImm(Val)); 1984 } 1985 1986 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1987 assert(N == 2 && "Invalid number of operands!"); 1988 if (Kind == k_PostIndexRegister) { 1989 int32_t Val = 1990 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1991 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1992 Inst.addOperand(MCOperand::CreateImm(Val)); 1993 return; 1994 } 1995 1996 // Constant offset. 1997 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1998 int32_t Val = CE->getValue(); 1999 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2000 // Special case for #-0 2001 if (Val == INT32_MIN) Val = 0; 2002 if (Val < 0) Val = -Val; 2003 Val = ARM_AM::getAM3Opc(AddSub, Val); 2004 Inst.addOperand(MCOperand::CreateReg(0)); 2005 Inst.addOperand(MCOperand::CreateImm(Val)); 2006 } 2007 2008 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 2009 assert(N == 2 && "Invalid number of operands!"); 2010 // If we have an immediate that's not a constant, treat it as a label 2011 // reference needing a fixup. If it is a constant, it's something else 2012 // and we reject it. 2013 if (isImm()) { 2014 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2015 Inst.addOperand(MCOperand::CreateImm(0)); 2016 return; 2017 } 2018 2019 // The lower two bits are always zero and as such are not encoded. 2020 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2021 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2022 // Special case for #-0 2023 if (Val == INT32_MIN) Val = 0; 2024 if (Val < 0) Val = -Val; 2025 Val = ARM_AM::getAM5Opc(AddSub, Val); 2026 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2027 Inst.addOperand(MCOperand::CreateImm(Val)); 2028 } 2029 2030 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 2031 assert(N == 2 && "Invalid number of operands!"); 2032 // If we have an immediate that's not a constant, treat it as a label 2033 // reference needing a fixup. If it is a constant, it's something else 2034 // and we reject it. 2035 if (isImm()) { 2036 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2037 Inst.addOperand(MCOperand::CreateImm(0)); 2038 return; 2039 } 2040 2041 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2042 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2043 Inst.addOperand(MCOperand::CreateImm(Val)); 2044 } 2045 2046 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 2047 assert(N == 2 && "Invalid number of operands!"); 2048 // The lower two bits are always zero and as such are not encoded. 2049 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2050 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2051 Inst.addOperand(MCOperand::CreateImm(Val)); 2052 } 2053 2054 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2055 assert(N == 2 && "Invalid number of operands!"); 2056 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2057 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2058 Inst.addOperand(MCOperand::CreateImm(Val)); 2059 } 2060 2061 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2062 addMemImm8OffsetOperands(Inst, N); 2063 } 2064 2065 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2066 addMemImm8OffsetOperands(Inst, N); 2067 } 2068 2069 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2070 assert(N == 2 && "Invalid number of operands!"); 2071 // If this is an immediate, it's a label reference. 2072 if (isImm()) { 2073 addExpr(Inst, getImm()); 2074 Inst.addOperand(MCOperand::CreateImm(0)); 2075 return; 2076 } 2077 2078 // Otherwise, it's a normal memory reg+offset. 2079 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2080 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2081 Inst.addOperand(MCOperand::CreateImm(Val)); 2082 } 2083 2084 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2085 assert(N == 2 && "Invalid number of operands!"); 2086 // If this is an immediate, it's a label reference. 2087 if (isImm()) { 2088 addExpr(Inst, getImm()); 2089 Inst.addOperand(MCOperand::CreateImm(0)); 2090 return; 2091 } 2092 2093 // Otherwise, it's a normal memory reg+offset. 2094 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2095 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2096 Inst.addOperand(MCOperand::CreateImm(Val)); 2097 } 2098 2099 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 2100 assert(N == 2 && "Invalid number of operands!"); 2101 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2102 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2103 } 2104 2105 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 2106 assert(N == 2 && "Invalid number of operands!"); 2107 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2108 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2109 } 2110 2111 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2112 assert(N == 3 && "Invalid number of operands!"); 2113 unsigned Val = 2114 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2115 Memory.ShiftImm, Memory.ShiftType); 2116 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2117 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2118 Inst.addOperand(MCOperand::CreateImm(Val)); 2119 } 2120 2121 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2122 assert(N == 3 && "Invalid number of operands!"); 2123 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2124 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2125 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 2126 } 2127 2128 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 2129 assert(N == 2 && "Invalid number of operands!"); 2130 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2131 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2132 } 2133 2134 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 2135 assert(N == 2 && "Invalid number of operands!"); 2136 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2137 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2138 Inst.addOperand(MCOperand::CreateImm(Val)); 2139 } 2140 2141 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 2142 assert(N == 2 && "Invalid number of operands!"); 2143 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 2144 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2145 Inst.addOperand(MCOperand::CreateImm(Val)); 2146 } 2147 2148 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 2149 assert(N == 2 && "Invalid number of operands!"); 2150 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 2151 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2152 Inst.addOperand(MCOperand::CreateImm(Val)); 2153 } 2154 2155 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2156 assert(N == 2 && "Invalid number of operands!"); 2157 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2158 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2159 Inst.addOperand(MCOperand::CreateImm(Val)); 2160 } 2161 2162 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2163 assert(N == 1 && "Invalid number of operands!"); 2164 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2165 assert(CE && "non-constant post-idx-imm8 operand!"); 2166 int Imm = CE->getValue(); 2167 bool isAdd = Imm >= 0; 2168 if (Imm == INT32_MIN) Imm = 0; 2169 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2170 Inst.addOperand(MCOperand::CreateImm(Imm)); 2171 } 2172 2173 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2174 assert(N == 1 && "Invalid number of operands!"); 2175 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2176 assert(CE && "non-constant post-idx-imm8s4 operand!"); 2177 int Imm = CE->getValue(); 2178 bool isAdd = Imm >= 0; 2179 if (Imm == INT32_MIN) Imm = 0; 2180 // Immediate is scaled by 4. 2181 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2182 Inst.addOperand(MCOperand::CreateImm(Imm)); 2183 } 2184 2185 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2186 assert(N == 2 && "Invalid number of operands!"); 2187 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2188 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 2189 } 2190 2191 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2192 assert(N == 2 && "Invalid number of operands!"); 2193 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2194 // The sign, shift type, and shift amount are encoded in a single operand 2195 // using the AM2 encoding helpers. 2196 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2197 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2198 PostIdxReg.ShiftTy); 2199 Inst.addOperand(MCOperand::CreateImm(Imm)); 2200 } 2201 2202 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2203 assert(N == 1 && "Invalid number of operands!"); 2204 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 2205 } 2206 2207 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2208 assert(N == 1 && "Invalid number of operands!"); 2209 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 2210 } 2211 2212 void addVecListOperands(MCInst &Inst, unsigned N) const { 2213 assert(N == 1 && "Invalid number of operands!"); 2214 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2215 } 2216 2217 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2218 assert(N == 2 && "Invalid number of operands!"); 2219 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2220 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 2221 } 2222 2223 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2224 assert(N == 1 && "Invalid number of operands!"); 2225 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2226 } 2227 2228 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2229 assert(N == 1 && "Invalid number of operands!"); 2230 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2231 } 2232 2233 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2234 assert(N == 1 && "Invalid number of operands!"); 2235 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2236 } 2237 2238 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2239 assert(N == 1 && "Invalid number of operands!"); 2240 // The immediate encodes the type of constant as well as the value. 2241 // Mask in that this is an i8 splat. 2242 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2243 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 2244 } 2245 2246 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2247 assert(N == 1 && "Invalid number of operands!"); 2248 // The immediate encodes the type of constant as well as the value. 2249 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2250 unsigned Value = CE->getValue(); 2251 if (Value >= 256) 2252 Value = (Value >> 8) | 0xa00; 2253 else 2254 Value |= 0x800; 2255 Inst.addOperand(MCOperand::CreateImm(Value)); 2256 } 2257 2258 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2259 assert(N == 1 && "Invalid number of operands!"); 2260 // The immediate encodes the type of constant as well as the value. 2261 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2262 unsigned Value = CE->getValue(); 2263 if (Value >= 256 && Value <= 0xff00) 2264 Value = (Value >> 8) | 0x200; 2265 else if (Value > 0xffff && Value <= 0xff0000) 2266 Value = (Value >> 16) | 0x400; 2267 else if (Value > 0xffffff) 2268 Value = (Value >> 24) | 0x600; 2269 Inst.addOperand(MCOperand::CreateImm(Value)); 2270 } 2271 2272 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2273 assert(N == 1 && "Invalid number of operands!"); 2274 // The immediate encodes the type of constant as well as the value. 2275 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2276 unsigned Value = CE->getValue(); 2277 if (Value >= 256 && Value <= 0xffff) 2278 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2279 else if (Value > 0xffff && Value <= 0xffffff) 2280 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2281 else if (Value > 0xffffff) 2282 Value = (Value >> 24) | 0x600; 2283 Inst.addOperand(MCOperand::CreateImm(Value)); 2284 } 2285 2286 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2287 assert(N == 1 && "Invalid number of operands!"); 2288 // The immediate encodes the type of constant as well as the value. 2289 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2290 unsigned Value = ~CE->getValue(); 2291 if (Value >= 256 && Value <= 0xffff) 2292 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2293 else if (Value > 0xffff && Value <= 0xffffff) 2294 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2295 else if (Value > 0xffffff) 2296 Value = (Value >> 24) | 0x600; 2297 Inst.addOperand(MCOperand::CreateImm(Value)); 2298 } 2299 2300 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2301 assert(N == 1 && "Invalid number of operands!"); 2302 // The immediate encodes the type of constant as well as the value. 2303 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2304 uint64_t Value = CE->getValue(); 2305 unsigned Imm = 0; 2306 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2307 Imm |= (Value & 1) << i; 2308 } 2309 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2310 } 2311 2312 virtual void print(raw_ostream &OS) const; 2313 2314 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2315 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2316 Op->ITMask.Mask = Mask; 2317 Op->StartLoc = S; 2318 Op->EndLoc = S; 2319 return Op; 2320 } 2321 2322 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2323 ARMOperand *Op = new ARMOperand(k_CondCode); 2324 Op->CC.Val = CC; 2325 Op->StartLoc = S; 2326 Op->EndLoc = S; 2327 return Op; 2328 } 2329 2330 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2331 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2332 Op->Cop.Val = CopVal; 2333 Op->StartLoc = S; 2334 Op->EndLoc = S; 2335 return Op; 2336 } 2337 2338 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2339 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2340 Op->Cop.Val = CopVal; 2341 Op->StartLoc = S; 2342 Op->EndLoc = S; 2343 return Op; 2344 } 2345 2346 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2347 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2348 Op->Cop.Val = Val; 2349 Op->StartLoc = S; 2350 Op->EndLoc = E; 2351 return Op; 2352 } 2353 2354 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2355 ARMOperand *Op = new ARMOperand(k_CCOut); 2356 Op->Reg.RegNum = RegNum; 2357 Op->StartLoc = S; 2358 Op->EndLoc = S; 2359 return Op; 2360 } 2361 2362 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2363 ARMOperand *Op = new ARMOperand(k_Token); 2364 Op->Tok.Data = Str.data(); 2365 Op->Tok.Length = Str.size(); 2366 Op->StartLoc = S; 2367 Op->EndLoc = S; 2368 return Op; 2369 } 2370 2371 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2372 ARMOperand *Op = new ARMOperand(k_Register); 2373 Op->Reg.RegNum = RegNum; 2374 Op->StartLoc = S; 2375 Op->EndLoc = E; 2376 return Op; 2377 } 2378 2379 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2380 unsigned SrcReg, 2381 unsigned ShiftReg, 2382 unsigned ShiftImm, 2383 SMLoc S, SMLoc E) { 2384 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2385 Op->RegShiftedReg.ShiftTy = ShTy; 2386 Op->RegShiftedReg.SrcReg = SrcReg; 2387 Op->RegShiftedReg.ShiftReg = ShiftReg; 2388 Op->RegShiftedReg.ShiftImm = ShiftImm; 2389 Op->StartLoc = S; 2390 Op->EndLoc = E; 2391 return Op; 2392 } 2393 2394 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2395 unsigned SrcReg, 2396 unsigned ShiftImm, 2397 SMLoc S, SMLoc E) { 2398 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2399 Op->RegShiftedImm.ShiftTy = ShTy; 2400 Op->RegShiftedImm.SrcReg = SrcReg; 2401 Op->RegShiftedImm.ShiftImm = ShiftImm; 2402 Op->StartLoc = S; 2403 Op->EndLoc = E; 2404 return Op; 2405 } 2406 2407 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2408 SMLoc S, SMLoc E) { 2409 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2410 Op->ShifterImm.isASR = isASR; 2411 Op->ShifterImm.Imm = Imm; 2412 Op->StartLoc = S; 2413 Op->EndLoc = E; 2414 return Op; 2415 } 2416 2417 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2418 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2419 Op->RotImm.Imm = Imm; 2420 Op->StartLoc = S; 2421 Op->EndLoc = E; 2422 return Op; 2423 } 2424 2425 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2426 SMLoc S, SMLoc E) { 2427 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2428 Op->Bitfield.LSB = LSB; 2429 Op->Bitfield.Width = Width; 2430 Op->StartLoc = S; 2431 Op->EndLoc = E; 2432 return Op; 2433 } 2434 2435 static ARMOperand * 2436 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs, 2437 SMLoc StartLoc, SMLoc EndLoc) { 2438 assert (Regs.size() > 0 && "RegList contains no registers?"); 2439 KindTy Kind = k_RegisterList; 2440 2441 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2442 Kind = k_DPRRegisterList; 2443 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2444 contains(Regs.front().second)) 2445 Kind = k_SPRRegisterList; 2446 2447 // Sort based on the register encoding values. 2448 array_pod_sort(Regs.begin(), Regs.end()); 2449 2450 ARMOperand *Op = new ARMOperand(Kind); 2451 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator 2452 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2453 Op->Registers.push_back(I->second); 2454 Op->StartLoc = StartLoc; 2455 Op->EndLoc = EndLoc; 2456 return Op; 2457 } 2458 2459 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2460 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2461 ARMOperand *Op = new ARMOperand(k_VectorList); 2462 Op->VectorList.RegNum = RegNum; 2463 Op->VectorList.Count = Count; 2464 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2465 Op->StartLoc = S; 2466 Op->EndLoc = E; 2467 return Op; 2468 } 2469 2470 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2471 bool isDoubleSpaced, 2472 SMLoc S, SMLoc E) { 2473 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2474 Op->VectorList.RegNum = RegNum; 2475 Op->VectorList.Count = Count; 2476 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2477 Op->StartLoc = S; 2478 Op->EndLoc = E; 2479 return Op; 2480 } 2481 2482 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2483 unsigned Index, 2484 bool isDoubleSpaced, 2485 SMLoc S, SMLoc E) { 2486 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2487 Op->VectorList.RegNum = RegNum; 2488 Op->VectorList.Count = Count; 2489 Op->VectorList.LaneIndex = Index; 2490 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2491 Op->StartLoc = S; 2492 Op->EndLoc = E; 2493 return Op; 2494 } 2495 2496 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2497 MCContext &Ctx) { 2498 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2499 Op->VectorIndex.Val = Idx; 2500 Op->StartLoc = S; 2501 Op->EndLoc = E; 2502 return Op; 2503 } 2504 2505 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2506 ARMOperand *Op = new ARMOperand(k_Immediate); 2507 Op->Imm.Val = Val; 2508 Op->StartLoc = S; 2509 Op->EndLoc = E; 2510 return Op; 2511 } 2512 2513 static ARMOperand *CreateMem(unsigned BaseRegNum, 2514 const MCConstantExpr *OffsetImm, 2515 unsigned OffsetRegNum, 2516 ARM_AM::ShiftOpc ShiftType, 2517 unsigned ShiftImm, 2518 unsigned Alignment, 2519 bool isNegative, 2520 SMLoc S, SMLoc E) { 2521 ARMOperand *Op = new ARMOperand(k_Memory); 2522 Op->Memory.BaseRegNum = BaseRegNum; 2523 Op->Memory.OffsetImm = OffsetImm; 2524 Op->Memory.OffsetRegNum = OffsetRegNum; 2525 Op->Memory.ShiftType = ShiftType; 2526 Op->Memory.ShiftImm = ShiftImm; 2527 Op->Memory.Alignment = Alignment; 2528 Op->Memory.isNegative = isNegative; 2529 Op->StartLoc = S; 2530 Op->EndLoc = E; 2531 return Op; 2532 } 2533 2534 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2535 ARM_AM::ShiftOpc ShiftTy, 2536 unsigned ShiftImm, 2537 SMLoc S, SMLoc E) { 2538 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2539 Op->PostIdxReg.RegNum = RegNum; 2540 Op->PostIdxReg.isAdd = isAdd; 2541 Op->PostIdxReg.ShiftTy = ShiftTy; 2542 Op->PostIdxReg.ShiftImm = ShiftImm; 2543 Op->StartLoc = S; 2544 Op->EndLoc = E; 2545 return Op; 2546 } 2547 2548 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2549 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2550 Op->MBOpt.Val = Opt; 2551 Op->StartLoc = S; 2552 Op->EndLoc = S; 2553 return Op; 2554 } 2555 2556 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, 2557 SMLoc S) { 2558 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt); 2559 Op->ISBOpt.Val = Opt; 2560 Op->StartLoc = S; 2561 Op->EndLoc = S; 2562 return Op; 2563 } 2564 2565 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2566 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2567 Op->IFlags.Val = IFlags; 2568 Op->StartLoc = S; 2569 Op->EndLoc = S; 2570 return Op; 2571 } 2572 2573 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2574 ARMOperand *Op = new ARMOperand(k_MSRMask); 2575 Op->MMask.Val = MMask; 2576 Op->StartLoc = S; 2577 Op->EndLoc = S; 2578 return Op; 2579 } 2580 }; 2581 2582 } // end anonymous namespace. 2583 2584 void ARMOperand::print(raw_ostream &OS) const { 2585 switch (Kind) { 2586 case k_CondCode: 2587 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2588 break; 2589 case k_CCOut: 2590 OS << "<ccout " << getReg() << ">"; 2591 break; 2592 case k_ITCondMask: { 2593 static const char *const MaskStr[] = { 2594 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2595 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2596 }; 2597 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2598 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2599 break; 2600 } 2601 case k_CoprocNum: 2602 OS << "<coprocessor number: " << getCoproc() << ">"; 2603 break; 2604 case k_CoprocReg: 2605 OS << "<coprocessor register: " << getCoproc() << ">"; 2606 break; 2607 case k_CoprocOption: 2608 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2609 break; 2610 case k_MSRMask: 2611 OS << "<mask: " << getMSRMask() << ">"; 2612 break; 2613 case k_Immediate: 2614 getImm()->print(OS); 2615 break; 2616 case k_MemBarrierOpt: 2617 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; 2618 break; 2619 case k_InstSyncBarrierOpt: 2620 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2621 break; 2622 case k_Memory: 2623 OS << "<memory " 2624 << " base:" << Memory.BaseRegNum; 2625 OS << ">"; 2626 break; 2627 case k_PostIndexRegister: 2628 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2629 << PostIdxReg.RegNum; 2630 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2631 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2632 << PostIdxReg.ShiftImm; 2633 OS << ">"; 2634 break; 2635 case k_ProcIFlags: { 2636 OS << "<ARM_PROC::"; 2637 unsigned IFlags = getProcIFlags(); 2638 for (int i=2; i >= 0; --i) 2639 if (IFlags & (1 << i)) 2640 OS << ARM_PROC::IFlagsToString(1 << i); 2641 OS << ">"; 2642 break; 2643 } 2644 case k_Register: 2645 OS << "<register " << getReg() << ">"; 2646 break; 2647 case k_ShifterImmediate: 2648 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2649 << " #" << ShifterImm.Imm << ">"; 2650 break; 2651 case k_ShiftedRegister: 2652 OS << "<so_reg_reg " 2653 << RegShiftedReg.SrcReg << " " 2654 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2655 << " " << RegShiftedReg.ShiftReg << ">"; 2656 break; 2657 case k_ShiftedImmediate: 2658 OS << "<so_reg_imm " 2659 << RegShiftedImm.SrcReg << " " 2660 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2661 << " #" << RegShiftedImm.ShiftImm << ">"; 2662 break; 2663 case k_RotateImmediate: 2664 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2665 break; 2666 case k_BitfieldDescriptor: 2667 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2668 << ", width: " << Bitfield.Width << ">"; 2669 break; 2670 case k_RegisterList: 2671 case k_DPRRegisterList: 2672 case k_SPRRegisterList: { 2673 OS << "<register_list "; 2674 2675 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2676 for (SmallVectorImpl<unsigned>::const_iterator 2677 I = RegList.begin(), E = RegList.end(); I != E; ) { 2678 OS << *I; 2679 if (++I < E) OS << ", "; 2680 } 2681 2682 OS << ">"; 2683 break; 2684 } 2685 case k_VectorList: 2686 OS << "<vector_list " << VectorList.Count << " * " 2687 << VectorList.RegNum << ">"; 2688 break; 2689 case k_VectorListAllLanes: 2690 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2691 << VectorList.RegNum << ">"; 2692 break; 2693 case k_VectorListIndexed: 2694 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2695 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2696 break; 2697 case k_Token: 2698 OS << "'" << getToken() << "'"; 2699 break; 2700 case k_VectorIndex: 2701 OS << "<vectorindex " << getVectorIndex() << ">"; 2702 break; 2703 } 2704 } 2705 2706 /// @name Auto-generated Match Functions 2707 /// { 2708 2709 static unsigned MatchRegisterName(StringRef Name); 2710 2711 /// } 2712 2713 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2714 SMLoc &StartLoc, SMLoc &EndLoc) { 2715 StartLoc = Parser.getTok().getLoc(); 2716 EndLoc = Parser.getTok().getEndLoc(); 2717 RegNo = tryParseRegister(); 2718 2719 return (RegNo == (unsigned)-1); 2720 } 2721 2722 /// Try to parse a register name. The token must be an Identifier when called, 2723 /// and if it is a register name the token is eaten and the register number is 2724 /// returned. Otherwise return -1. 2725 /// 2726 int ARMAsmParser::tryParseRegister() { 2727 const AsmToken &Tok = Parser.getTok(); 2728 if (Tok.isNot(AsmToken::Identifier)) return -1; 2729 2730 std::string lowerCase = Tok.getString().lower(); 2731 unsigned RegNum = MatchRegisterName(lowerCase); 2732 if (!RegNum) { 2733 RegNum = StringSwitch<unsigned>(lowerCase) 2734 .Case("r13", ARM::SP) 2735 .Case("r14", ARM::LR) 2736 .Case("r15", ARM::PC) 2737 .Case("ip", ARM::R12) 2738 // Additional register name aliases for 'gas' compatibility. 2739 .Case("a1", ARM::R0) 2740 .Case("a2", ARM::R1) 2741 .Case("a3", ARM::R2) 2742 .Case("a4", ARM::R3) 2743 .Case("v1", ARM::R4) 2744 .Case("v2", ARM::R5) 2745 .Case("v3", ARM::R6) 2746 .Case("v4", ARM::R7) 2747 .Case("v5", ARM::R8) 2748 .Case("v6", ARM::R9) 2749 .Case("v7", ARM::R10) 2750 .Case("v8", ARM::R11) 2751 .Case("sb", ARM::R9) 2752 .Case("sl", ARM::R10) 2753 .Case("fp", ARM::R11) 2754 .Default(0); 2755 } 2756 if (!RegNum) { 2757 // Check for aliases registered via .req. Canonicalize to lower case. 2758 // That's more consistent since register names are case insensitive, and 2759 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2760 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2761 // If no match, return failure. 2762 if (Entry == RegisterReqs.end()) 2763 return -1; 2764 Parser.Lex(); // Eat identifier token. 2765 return Entry->getValue(); 2766 } 2767 2768 Parser.Lex(); // Eat identifier token. 2769 2770 return RegNum; 2771 } 2772 2773 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2774 // If a recoverable error occurs, return 1. If an irrecoverable error 2775 // occurs, return -1. An irrecoverable error is one where tokens have been 2776 // consumed in the process of trying to parse the shifter (i.e., when it is 2777 // indeed a shifter operand, but malformed). 2778 int ARMAsmParser::tryParseShiftRegister( 2779 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2780 SMLoc S = Parser.getTok().getLoc(); 2781 const AsmToken &Tok = Parser.getTok(); 2782 if (Tok.isNot(AsmToken::Identifier)) 2783 return -1; 2784 2785 std::string lowerCase = Tok.getString().lower(); 2786 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2787 .Case("asl", ARM_AM::lsl) 2788 .Case("lsl", ARM_AM::lsl) 2789 .Case("lsr", ARM_AM::lsr) 2790 .Case("asr", ARM_AM::asr) 2791 .Case("ror", ARM_AM::ror) 2792 .Case("rrx", ARM_AM::rrx) 2793 .Default(ARM_AM::no_shift); 2794 2795 if (ShiftTy == ARM_AM::no_shift) 2796 return 1; 2797 2798 Parser.Lex(); // Eat the operator. 2799 2800 // The source register for the shift has already been added to the 2801 // operand list, so we need to pop it off and combine it into the shifted 2802 // register operand instead. 2803 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2804 if (!PrevOp->isReg()) 2805 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2806 int SrcReg = PrevOp->getReg(); 2807 2808 SMLoc EndLoc; 2809 int64_t Imm = 0; 2810 int ShiftReg = 0; 2811 if (ShiftTy == ARM_AM::rrx) { 2812 // RRX Doesn't have an explicit shift amount. The encoder expects 2813 // the shift register to be the same as the source register. Seems odd, 2814 // but OK. 2815 ShiftReg = SrcReg; 2816 } else { 2817 // Figure out if this is shifted by a constant or a register (for non-RRX). 2818 if (Parser.getTok().is(AsmToken::Hash) || 2819 Parser.getTok().is(AsmToken::Dollar)) { 2820 Parser.Lex(); // Eat hash. 2821 SMLoc ImmLoc = Parser.getTok().getLoc(); 2822 const MCExpr *ShiftExpr = 0; 2823 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 2824 Error(ImmLoc, "invalid immediate shift value"); 2825 return -1; 2826 } 2827 // The expression must be evaluatable as an immediate. 2828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2829 if (!CE) { 2830 Error(ImmLoc, "invalid immediate shift value"); 2831 return -1; 2832 } 2833 // Range check the immediate. 2834 // lsl, ror: 0 <= imm <= 31 2835 // lsr, asr: 0 <= imm <= 32 2836 Imm = CE->getValue(); 2837 if (Imm < 0 || 2838 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2839 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2840 Error(ImmLoc, "immediate shift value out of range"); 2841 return -1; 2842 } 2843 // shift by zero is a nop. Always send it through as lsl. 2844 // ('as' compatibility) 2845 if (Imm == 0) 2846 ShiftTy = ARM_AM::lsl; 2847 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2848 SMLoc L = Parser.getTok().getLoc(); 2849 EndLoc = Parser.getTok().getEndLoc(); 2850 ShiftReg = tryParseRegister(); 2851 if (ShiftReg == -1) { 2852 Error (L, "expected immediate or register in shift operand"); 2853 return -1; 2854 } 2855 } else { 2856 Error (Parser.getTok().getLoc(), 2857 "expected immediate or register in shift operand"); 2858 return -1; 2859 } 2860 } 2861 2862 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2863 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2864 ShiftReg, Imm, 2865 S, EndLoc)); 2866 else 2867 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2868 S, EndLoc)); 2869 2870 return 0; 2871 } 2872 2873 2874 /// Try to parse a register name. The token must be an Identifier when called. 2875 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 2876 /// if there is a "writeback". 'true' if it's not a register. 2877 /// 2878 /// TODO this is likely to change to allow different register types and or to 2879 /// parse for a specific register type. 2880 bool ARMAsmParser:: 2881 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2882 const AsmToken &RegTok = Parser.getTok(); 2883 int RegNo = tryParseRegister(); 2884 if (RegNo == -1) 2885 return true; 2886 2887 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 2888 RegTok.getEndLoc())); 2889 2890 const AsmToken &ExclaimTok = Parser.getTok(); 2891 if (ExclaimTok.is(AsmToken::Exclaim)) { 2892 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2893 ExclaimTok.getLoc())); 2894 Parser.Lex(); // Eat exclaim token 2895 return false; 2896 } 2897 2898 // Also check for an index operand. This is only legal for vector registers, 2899 // but that'll get caught OK in operand matching, so we don't need to 2900 // explicitly filter everything else out here. 2901 if (Parser.getTok().is(AsmToken::LBrac)) { 2902 SMLoc SIdx = Parser.getTok().getLoc(); 2903 Parser.Lex(); // Eat left bracket token. 2904 2905 const MCExpr *ImmVal; 2906 if (getParser().parseExpression(ImmVal)) 2907 return true; 2908 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2909 if (!MCE) 2910 return TokError("immediate value expected for vector index"); 2911 2912 if (Parser.getTok().isNot(AsmToken::RBrac)) 2913 return Error(Parser.getTok().getLoc(), "']' expected"); 2914 2915 SMLoc E = Parser.getTok().getEndLoc(); 2916 Parser.Lex(); // Eat right bracket token. 2917 2918 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2919 SIdx, E, 2920 getContext())); 2921 } 2922 2923 return false; 2924 } 2925 2926 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 2927 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2928 /// "c5", ... 2929 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2930 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2931 // but efficient. 2932 switch (Name.size()) { 2933 default: return -1; 2934 case 2: 2935 if (Name[0] != CoprocOp) 2936 return -1; 2937 switch (Name[1]) { 2938 default: return -1; 2939 case '0': return 0; 2940 case '1': return 1; 2941 case '2': return 2; 2942 case '3': return 3; 2943 case '4': return 4; 2944 case '5': return 5; 2945 case '6': return 6; 2946 case '7': return 7; 2947 case '8': return 8; 2948 case '9': return 9; 2949 } 2950 case 3: 2951 if (Name[0] != CoprocOp || Name[1] != '1') 2952 return -1; 2953 switch (Name[2]) { 2954 default: return -1; 2955 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON) 2956 case '0': return CoprocOp == 'p'? -1: 10; 2957 case '1': return CoprocOp == 'p'? -1: 11; 2958 case '2': return 12; 2959 case '3': return 13; 2960 case '4': return 14; 2961 case '5': return 15; 2962 } 2963 } 2964 } 2965 2966 /// parseITCondCode - Try to parse a condition code for an IT instruction. 2967 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2968 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2969 SMLoc S = Parser.getTok().getLoc(); 2970 const AsmToken &Tok = Parser.getTok(); 2971 if (!Tok.is(AsmToken::Identifier)) 2972 return MatchOperand_NoMatch; 2973 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2974 .Case("eq", ARMCC::EQ) 2975 .Case("ne", ARMCC::NE) 2976 .Case("hs", ARMCC::HS) 2977 .Case("cs", ARMCC::HS) 2978 .Case("lo", ARMCC::LO) 2979 .Case("cc", ARMCC::LO) 2980 .Case("mi", ARMCC::MI) 2981 .Case("pl", ARMCC::PL) 2982 .Case("vs", ARMCC::VS) 2983 .Case("vc", ARMCC::VC) 2984 .Case("hi", ARMCC::HI) 2985 .Case("ls", ARMCC::LS) 2986 .Case("ge", ARMCC::GE) 2987 .Case("lt", ARMCC::LT) 2988 .Case("gt", ARMCC::GT) 2989 .Case("le", ARMCC::LE) 2990 .Case("al", ARMCC::AL) 2991 .Default(~0U); 2992 if (CC == ~0U) 2993 return MatchOperand_NoMatch; 2994 Parser.Lex(); // Eat the token. 2995 2996 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2997 2998 return MatchOperand_Success; 2999 } 3000 3001 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 3002 /// token must be an Identifier when called, and if it is a coprocessor 3003 /// number, the token is eaten and the operand is added to the operand list. 3004 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3005 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3006 SMLoc S = Parser.getTok().getLoc(); 3007 const AsmToken &Tok = Parser.getTok(); 3008 if (Tok.isNot(AsmToken::Identifier)) 3009 return MatchOperand_NoMatch; 3010 3011 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 3012 if (Num == -1) 3013 return MatchOperand_NoMatch; 3014 3015 Parser.Lex(); // Eat identifier token. 3016 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 3017 return MatchOperand_Success; 3018 } 3019 3020 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 3021 /// token must be an Identifier when called, and if it is a coprocessor 3022 /// number, the token is eaten and the operand is added to the operand list. 3023 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3024 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3025 SMLoc S = Parser.getTok().getLoc(); 3026 const AsmToken &Tok = Parser.getTok(); 3027 if (Tok.isNot(AsmToken::Identifier)) 3028 return MatchOperand_NoMatch; 3029 3030 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 3031 if (Reg == -1) 3032 return MatchOperand_NoMatch; 3033 3034 Parser.Lex(); // Eat identifier token. 3035 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 3036 return MatchOperand_Success; 3037 } 3038 3039 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 3040 /// coproc_option : '{' imm0_255 '}' 3041 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3042 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3043 SMLoc S = Parser.getTok().getLoc(); 3044 3045 // If this isn't a '{', this isn't a coprocessor immediate operand. 3046 if (Parser.getTok().isNot(AsmToken::LCurly)) 3047 return MatchOperand_NoMatch; 3048 Parser.Lex(); // Eat the '{' 3049 3050 const MCExpr *Expr; 3051 SMLoc Loc = Parser.getTok().getLoc(); 3052 if (getParser().parseExpression(Expr)) { 3053 Error(Loc, "illegal expression"); 3054 return MatchOperand_ParseFail; 3055 } 3056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3057 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 3058 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 3059 return MatchOperand_ParseFail; 3060 } 3061 int Val = CE->getValue(); 3062 3063 // Check for and consume the closing '}' 3064 if (Parser.getTok().isNot(AsmToken::RCurly)) 3065 return MatchOperand_ParseFail; 3066 SMLoc E = Parser.getTok().getEndLoc(); 3067 Parser.Lex(); // Eat the '}' 3068 3069 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 3070 return MatchOperand_Success; 3071 } 3072 3073 // For register list parsing, we need to map from raw GPR register numbering 3074 // to the enumeration values. The enumeration values aren't sorted by 3075 // register number due to our using "sp", "lr" and "pc" as canonical names. 3076 static unsigned getNextRegister(unsigned Reg) { 3077 // If this is a GPR, we need to do it manually, otherwise we can rely 3078 // on the sort ordering of the enumeration since the other reg-classes 3079 // are sane. 3080 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3081 return Reg + 1; 3082 switch(Reg) { 3083 default: llvm_unreachable("Invalid GPR number!"); 3084 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 3085 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 3086 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 3087 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 3088 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 3089 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 3090 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 3091 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 3092 } 3093 } 3094 3095 // Return the low-subreg of a given Q register. 3096 static unsigned getDRegFromQReg(unsigned QReg) { 3097 switch (QReg) { 3098 default: llvm_unreachable("expected a Q register!"); 3099 case ARM::Q0: return ARM::D0; 3100 case ARM::Q1: return ARM::D2; 3101 case ARM::Q2: return ARM::D4; 3102 case ARM::Q3: return ARM::D6; 3103 case ARM::Q4: return ARM::D8; 3104 case ARM::Q5: return ARM::D10; 3105 case ARM::Q6: return ARM::D12; 3106 case ARM::Q7: return ARM::D14; 3107 case ARM::Q8: return ARM::D16; 3108 case ARM::Q9: return ARM::D18; 3109 case ARM::Q10: return ARM::D20; 3110 case ARM::Q11: return ARM::D22; 3111 case ARM::Q12: return ARM::D24; 3112 case ARM::Q13: return ARM::D26; 3113 case ARM::Q14: return ARM::D28; 3114 case ARM::Q15: return ARM::D30; 3115 } 3116 } 3117 3118 /// Parse a register list. 3119 bool ARMAsmParser:: 3120 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3121 assert(Parser.getTok().is(AsmToken::LCurly) && 3122 "Token is not a Left Curly Brace"); 3123 SMLoc S = Parser.getTok().getLoc(); 3124 Parser.Lex(); // Eat '{' token. 3125 SMLoc RegLoc = Parser.getTok().getLoc(); 3126 3127 // Check the first register in the list to see what register class 3128 // this is a list of. 3129 int Reg = tryParseRegister(); 3130 if (Reg == -1) 3131 return Error(RegLoc, "register expected"); 3132 3133 // The reglist instructions have at most 16 registers, so reserve 3134 // space for that many. 3135 int EReg = 0; 3136 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; 3137 3138 // Allow Q regs and just interpret them as the two D sub-registers. 3139 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3140 Reg = getDRegFromQReg(Reg); 3141 EReg = MRI->getEncodingValue(Reg); 3142 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3143 ++Reg; 3144 } 3145 const MCRegisterClass *RC; 3146 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3147 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 3148 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 3149 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 3150 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 3151 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 3152 else 3153 return Error(RegLoc, "invalid register in register list"); 3154 3155 // Store the register. 3156 EReg = MRI->getEncodingValue(Reg); 3157 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3158 3159 // This starts immediately after the first register token in the list, 3160 // so we can see either a comma or a minus (range separator) as a legal 3161 // next token. 3162 while (Parser.getTok().is(AsmToken::Comma) || 3163 Parser.getTok().is(AsmToken::Minus)) { 3164 if (Parser.getTok().is(AsmToken::Minus)) { 3165 Parser.Lex(); // Eat the minus. 3166 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3167 int EndReg = tryParseRegister(); 3168 if (EndReg == -1) 3169 return Error(AfterMinusLoc, "register expected"); 3170 // Allow Q regs and just interpret them as the two D sub-registers. 3171 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3172 EndReg = getDRegFromQReg(EndReg) + 1; 3173 // If the register is the same as the start reg, there's nothing 3174 // more to do. 3175 if (Reg == EndReg) 3176 continue; 3177 // The register must be in the same register class as the first. 3178 if (!RC->contains(EndReg)) 3179 return Error(AfterMinusLoc, "invalid register in register list"); 3180 // Ranges must go from low to high. 3181 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3182 return Error(AfterMinusLoc, "bad range in register list"); 3183 3184 // Add all the registers in the range to the register list. 3185 while (Reg != EndReg) { 3186 Reg = getNextRegister(Reg); 3187 EReg = MRI->getEncodingValue(Reg); 3188 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3189 } 3190 continue; 3191 } 3192 Parser.Lex(); // Eat the comma. 3193 RegLoc = Parser.getTok().getLoc(); 3194 int OldReg = Reg; 3195 const AsmToken RegTok = Parser.getTok(); 3196 Reg = tryParseRegister(); 3197 if (Reg == -1) 3198 return Error(RegLoc, "register expected"); 3199 // Allow Q regs and just interpret them as the two D sub-registers. 3200 bool isQReg = false; 3201 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3202 Reg = getDRegFromQReg(Reg); 3203 isQReg = true; 3204 } 3205 // The register must be in the same register class as the first. 3206 if (!RC->contains(Reg)) 3207 return Error(RegLoc, "invalid register in register list"); 3208 // List must be monotonically increasing. 3209 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3210 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3211 Warning(RegLoc, "register list not in ascending order"); 3212 else 3213 return Error(RegLoc, "register list not in ascending order"); 3214 } 3215 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3216 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3217 ") in register list"); 3218 continue; 3219 } 3220 // VFP register lists must also be contiguous. 3221 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3222 Reg != OldReg + 1) 3223 return Error(RegLoc, "non-contiguous register range"); 3224 EReg = MRI->getEncodingValue(Reg); 3225 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3226 if (isQReg) { 3227 EReg = MRI->getEncodingValue(++Reg); 3228 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3229 } 3230 } 3231 3232 if (Parser.getTok().isNot(AsmToken::RCurly)) 3233 return Error(Parser.getTok().getLoc(), "'}' expected"); 3234 SMLoc E = Parser.getTok().getEndLoc(); 3235 Parser.Lex(); // Eat '}' token. 3236 3237 // Push the register list operand. 3238 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3239 3240 // The ARM system instruction variants for LDM/STM have a '^' token here. 3241 if (Parser.getTok().is(AsmToken::Caret)) { 3242 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3243 Parser.Lex(); // Eat '^' token. 3244 } 3245 3246 return false; 3247 } 3248 3249 // Helper function to parse the lane index for vector lists. 3250 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3251 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3252 Index = 0; // Always return a defined index value. 3253 if (Parser.getTok().is(AsmToken::LBrac)) { 3254 Parser.Lex(); // Eat the '['. 3255 if (Parser.getTok().is(AsmToken::RBrac)) { 3256 // "Dn[]" is the 'all lanes' syntax. 3257 LaneKind = AllLanes; 3258 EndLoc = Parser.getTok().getEndLoc(); 3259 Parser.Lex(); // Eat the ']'. 3260 return MatchOperand_Success; 3261 } 3262 3263 // There's an optional '#' token here. Normally there wouldn't be, but 3264 // inline assemble puts one in, and it's friendly to accept that. 3265 if (Parser.getTok().is(AsmToken::Hash)) 3266 Parser.Lex(); // Eat '#' or '$'. 3267 3268 const MCExpr *LaneIndex; 3269 SMLoc Loc = Parser.getTok().getLoc(); 3270 if (getParser().parseExpression(LaneIndex)) { 3271 Error(Loc, "illegal expression"); 3272 return MatchOperand_ParseFail; 3273 } 3274 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3275 if (!CE) { 3276 Error(Loc, "lane index must be empty or an integer"); 3277 return MatchOperand_ParseFail; 3278 } 3279 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3280 Error(Parser.getTok().getLoc(), "']' expected"); 3281 return MatchOperand_ParseFail; 3282 } 3283 EndLoc = Parser.getTok().getEndLoc(); 3284 Parser.Lex(); // Eat the ']'. 3285 int64_t Val = CE->getValue(); 3286 3287 // FIXME: Make this range check context sensitive for .8, .16, .32. 3288 if (Val < 0 || Val > 7) { 3289 Error(Parser.getTok().getLoc(), "lane index out of range"); 3290 return MatchOperand_ParseFail; 3291 } 3292 Index = Val; 3293 LaneKind = IndexedLane; 3294 return MatchOperand_Success; 3295 } 3296 LaneKind = NoLanes; 3297 return MatchOperand_Success; 3298 } 3299 3300 // parse a vector register list 3301 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3302 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3303 VectorLaneTy LaneKind; 3304 unsigned LaneIndex; 3305 SMLoc S = Parser.getTok().getLoc(); 3306 // As an extension (to match gas), support a plain D register or Q register 3307 // (without encosing curly braces) as a single or double entry list, 3308 // respectively. 3309 if (Parser.getTok().is(AsmToken::Identifier)) { 3310 SMLoc E = Parser.getTok().getEndLoc(); 3311 int Reg = tryParseRegister(); 3312 if (Reg == -1) 3313 return MatchOperand_NoMatch; 3314 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3315 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3316 if (Res != MatchOperand_Success) 3317 return Res; 3318 switch (LaneKind) { 3319 case NoLanes: 3320 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3321 break; 3322 case AllLanes: 3323 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3324 S, E)); 3325 break; 3326 case IndexedLane: 3327 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3328 LaneIndex, 3329 false, S, E)); 3330 break; 3331 } 3332 return MatchOperand_Success; 3333 } 3334 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3335 Reg = getDRegFromQReg(Reg); 3336 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3337 if (Res != MatchOperand_Success) 3338 return Res; 3339 switch (LaneKind) { 3340 case NoLanes: 3341 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3342 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3343 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3344 break; 3345 case AllLanes: 3346 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3347 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3348 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3349 S, E)); 3350 break; 3351 case IndexedLane: 3352 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3353 LaneIndex, 3354 false, S, E)); 3355 break; 3356 } 3357 return MatchOperand_Success; 3358 } 3359 Error(S, "vector register expected"); 3360 return MatchOperand_ParseFail; 3361 } 3362 3363 if (Parser.getTok().isNot(AsmToken::LCurly)) 3364 return MatchOperand_NoMatch; 3365 3366 Parser.Lex(); // Eat '{' token. 3367 SMLoc RegLoc = Parser.getTok().getLoc(); 3368 3369 int Reg = tryParseRegister(); 3370 if (Reg == -1) { 3371 Error(RegLoc, "register expected"); 3372 return MatchOperand_ParseFail; 3373 } 3374 unsigned Count = 1; 3375 int Spacing = 0; 3376 unsigned FirstReg = Reg; 3377 // The list is of D registers, but we also allow Q regs and just interpret 3378 // them as the two D sub-registers. 3379 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3380 FirstReg = Reg = getDRegFromQReg(Reg); 3381 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3382 // it's ambiguous with four-register single spaced. 3383 ++Reg; 3384 ++Count; 3385 } 3386 3387 SMLoc E; 3388 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3389 return MatchOperand_ParseFail; 3390 3391 while (Parser.getTok().is(AsmToken::Comma) || 3392 Parser.getTok().is(AsmToken::Minus)) { 3393 if (Parser.getTok().is(AsmToken::Minus)) { 3394 if (!Spacing) 3395 Spacing = 1; // Register range implies a single spaced list. 3396 else if (Spacing == 2) { 3397 Error(Parser.getTok().getLoc(), 3398 "sequential registers in double spaced list"); 3399 return MatchOperand_ParseFail; 3400 } 3401 Parser.Lex(); // Eat the minus. 3402 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3403 int EndReg = tryParseRegister(); 3404 if (EndReg == -1) { 3405 Error(AfterMinusLoc, "register expected"); 3406 return MatchOperand_ParseFail; 3407 } 3408 // Allow Q regs and just interpret them as the two D sub-registers. 3409 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3410 EndReg = getDRegFromQReg(EndReg) + 1; 3411 // If the register is the same as the start reg, there's nothing 3412 // more to do. 3413 if (Reg == EndReg) 3414 continue; 3415 // The register must be in the same register class as the first. 3416 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3417 Error(AfterMinusLoc, "invalid register in register list"); 3418 return MatchOperand_ParseFail; 3419 } 3420 // Ranges must go from low to high. 3421 if (Reg > EndReg) { 3422 Error(AfterMinusLoc, "bad range in register list"); 3423 return MatchOperand_ParseFail; 3424 } 3425 // Parse the lane specifier if present. 3426 VectorLaneTy NextLaneKind; 3427 unsigned NextLaneIndex; 3428 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3429 MatchOperand_Success) 3430 return MatchOperand_ParseFail; 3431 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3432 Error(AfterMinusLoc, "mismatched lane index in register list"); 3433 return MatchOperand_ParseFail; 3434 } 3435 3436 // Add all the registers in the range to the register list. 3437 Count += EndReg - Reg; 3438 Reg = EndReg; 3439 continue; 3440 } 3441 Parser.Lex(); // Eat the comma. 3442 RegLoc = Parser.getTok().getLoc(); 3443 int OldReg = Reg; 3444 Reg = tryParseRegister(); 3445 if (Reg == -1) { 3446 Error(RegLoc, "register expected"); 3447 return MatchOperand_ParseFail; 3448 } 3449 // vector register lists must be contiguous. 3450 // It's OK to use the enumeration values directly here rather, as the 3451 // VFP register classes have the enum sorted properly. 3452 // 3453 // The list is of D registers, but we also allow Q regs and just interpret 3454 // them as the two D sub-registers. 3455 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3456 if (!Spacing) 3457 Spacing = 1; // Register range implies a single spaced list. 3458 else if (Spacing == 2) { 3459 Error(RegLoc, 3460 "invalid register in double-spaced list (must be 'D' register')"); 3461 return MatchOperand_ParseFail; 3462 } 3463 Reg = getDRegFromQReg(Reg); 3464 if (Reg != OldReg + 1) { 3465 Error(RegLoc, "non-contiguous register range"); 3466 return MatchOperand_ParseFail; 3467 } 3468 ++Reg; 3469 Count += 2; 3470 // Parse the lane specifier if present. 3471 VectorLaneTy NextLaneKind; 3472 unsigned NextLaneIndex; 3473 SMLoc LaneLoc = Parser.getTok().getLoc(); 3474 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3475 MatchOperand_Success) 3476 return MatchOperand_ParseFail; 3477 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3478 Error(LaneLoc, "mismatched lane index in register list"); 3479 return MatchOperand_ParseFail; 3480 } 3481 continue; 3482 } 3483 // Normal D register. 3484 // Figure out the register spacing (single or double) of the list if 3485 // we don't know it already. 3486 if (!Spacing) 3487 Spacing = 1 + (Reg == OldReg + 2); 3488 3489 // Just check that it's contiguous and keep going. 3490 if (Reg != OldReg + Spacing) { 3491 Error(RegLoc, "non-contiguous register range"); 3492 return MatchOperand_ParseFail; 3493 } 3494 ++Count; 3495 // Parse the lane specifier if present. 3496 VectorLaneTy NextLaneKind; 3497 unsigned NextLaneIndex; 3498 SMLoc EndLoc = Parser.getTok().getLoc(); 3499 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3500 return MatchOperand_ParseFail; 3501 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3502 Error(EndLoc, "mismatched lane index in register list"); 3503 return MatchOperand_ParseFail; 3504 } 3505 } 3506 3507 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3508 Error(Parser.getTok().getLoc(), "'}' expected"); 3509 return MatchOperand_ParseFail; 3510 } 3511 E = Parser.getTok().getEndLoc(); 3512 Parser.Lex(); // Eat '}' token. 3513 3514 switch (LaneKind) { 3515 case NoLanes: 3516 // Two-register operands have been converted to the 3517 // composite register classes. 3518 if (Count == 2) { 3519 const MCRegisterClass *RC = (Spacing == 1) ? 3520 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3521 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3522 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3523 } 3524 3525 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3526 (Spacing == 2), S, E)); 3527 break; 3528 case AllLanes: 3529 // Two-register operands have been converted to the 3530 // composite register classes. 3531 if (Count == 2) { 3532 const MCRegisterClass *RC = (Spacing == 1) ? 3533 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3534 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3535 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3536 } 3537 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3538 (Spacing == 2), 3539 S, E)); 3540 break; 3541 case IndexedLane: 3542 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3543 LaneIndex, 3544 (Spacing == 2), 3545 S, E)); 3546 break; 3547 } 3548 return MatchOperand_Success; 3549 } 3550 3551 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3552 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3553 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3554 SMLoc S = Parser.getTok().getLoc(); 3555 const AsmToken &Tok = Parser.getTok(); 3556 unsigned Opt; 3557 3558 if (Tok.is(AsmToken::Identifier)) { 3559 StringRef OptStr = Tok.getString(); 3560 3561 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3562 .Case("sy", ARM_MB::SY) 3563 .Case("st", ARM_MB::ST) 3564 .Case("ld", ARM_MB::LD) 3565 .Case("sh", ARM_MB::ISH) 3566 .Case("ish", ARM_MB::ISH) 3567 .Case("shst", ARM_MB::ISHST) 3568 .Case("ishst", ARM_MB::ISHST) 3569 .Case("ishld", ARM_MB::ISHLD) 3570 .Case("nsh", ARM_MB::NSH) 3571 .Case("un", ARM_MB::NSH) 3572 .Case("nshst", ARM_MB::NSHST) 3573 .Case("nshld", ARM_MB::NSHLD) 3574 .Case("unst", ARM_MB::NSHST) 3575 .Case("osh", ARM_MB::OSH) 3576 .Case("oshst", ARM_MB::OSHST) 3577 .Case("oshld", ARM_MB::OSHLD) 3578 .Default(~0U); 3579 3580 // ishld, oshld, nshld and ld are only available from ARMv8. 3581 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || 3582 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) 3583 Opt = ~0U; 3584 3585 if (Opt == ~0U) 3586 return MatchOperand_NoMatch; 3587 3588 Parser.Lex(); // Eat identifier token. 3589 } else if (Tok.is(AsmToken::Hash) || 3590 Tok.is(AsmToken::Dollar) || 3591 Tok.is(AsmToken::Integer)) { 3592 if (Parser.getTok().isNot(AsmToken::Integer)) 3593 Parser.Lex(); // Eat '#' or '$'. 3594 SMLoc Loc = Parser.getTok().getLoc(); 3595 3596 const MCExpr *MemBarrierID; 3597 if (getParser().parseExpression(MemBarrierID)) { 3598 Error(Loc, "illegal expression"); 3599 return MatchOperand_ParseFail; 3600 } 3601 3602 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3603 if (!CE) { 3604 Error(Loc, "constant expression expected"); 3605 return MatchOperand_ParseFail; 3606 } 3607 3608 int Val = CE->getValue(); 3609 if (Val & ~0xf) { 3610 Error(Loc, "immediate value out of range"); 3611 return MatchOperand_ParseFail; 3612 } 3613 3614 Opt = ARM_MB::RESERVED_0 + Val; 3615 } else 3616 return MatchOperand_ParseFail; 3617 3618 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3619 return MatchOperand_Success; 3620 } 3621 3622 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3623 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3624 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3625 SMLoc S = Parser.getTok().getLoc(); 3626 const AsmToken &Tok = Parser.getTok(); 3627 unsigned Opt; 3628 3629 if (Tok.is(AsmToken::Identifier)) { 3630 StringRef OptStr = Tok.getString(); 3631 3632 if (OptStr.equals_lower("sy")) 3633 Opt = ARM_ISB::SY; 3634 else 3635 return MatchOperand_NoMatch; 3636 3637 Parser.Lex(); // Eat identifier token. 3638 } else if (Tok.is(AsmToken::Hash) || 3639 Tok.is(AsmToken::Dollar) || 3640 Tok.is(AsmToken::Integer)) { 3641 if (Parser.getTok().isNot(AsmToken::Integer)) 3642 Parser.Lex(); // Eat '#' or '$'. 3643 SMLoc Loc = Parser.getTok().getLoc(); 3644 3645 const MCExpr *ISBarrierID; 3646 if (getParser().parseExpression(ISBarrierID)) { 3647 Error(Loc, "illegal expression"); 3648 return MatchOperand_ParseFail; 3649 } 3650 3651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3652 if (!CE) { 3653 Error(Loc, "constant expression expected"); 3654 return MatchOperand_ParseFail; 3655 } 3656 3657 int Val = CE->getValue(); 3658 if (Val & ~0xf) { 3659 Error(Loc, "immediate value out of range"); 3660 return MatchOperand_ParseFail; 3661 } 3662 3663 Opt = ARM_ISB::RESERVED_0 + Val; 3664 } else 3665 return MatchOperand_ParseFail; 3666 3667 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3668 (ARM_ISB::InstSyncBOpt)Opt, S)); 3669 return MatchOperand_Success; 3670 } 3671 3672 3673 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3674 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3675 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3676 SMLoc S = Parser.getTok().getLoc(); 3677 const AsmToken &Tok = Parser.getTok(); 3678 if (!Tok.is(AsmToken::Identifier)) 3679 return MatchOperand_NoMatch; 3680 StringRef IFlagsStr = Tok.getString(); 3681 3682 // An iflags string of "none" is interpreted to mean that none of the AIF 3683 // bits are set. Not a terribly useful instruction, but a valid encoding. 3684 unsigned IFlags = 0; 3685 if (IFlagsStr != "none") { 3686 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3687 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3688 .Case("a", ARM_PROC::A) 3689 .Case("i", ARM_PROC::I) 3690 .Case("f", ARM_PROC::F) 3691 .Default(~0U); 3692 3693 // If some specific iflag is already set, it means that some letter is 3694 // present more than once, this is not acceptable. 3695 if (Flag == ~0U || (IFlags & Flag)) 3696 return MatchOperand_NoMatch; 3697 3698 IFlags |= Flag; 3699 } 3700 } 3701 3702 Parser.Lex(); // Eat identifier token. 3703 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3704 return MatchOperand_Success; 3705 } 3706 3707 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3708 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3709 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3710 SMLoc S = Parser.getTok().getLoc(); 3711 const AsmToken &Tok = Parser.getTok(); 3712 if (!Tok.is(AsmToken::Identifier)) 3713 return MatchOperand_NoMatch; 3714 StringRef Mask = Tok.getString(); 3715 3716 if (isMClass()) { 3717 // See ARMv6-M 10.1.1 3718 std::string Name = Mask.lower(); 3719 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3720 // Note: in the documentation: 3721 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3722 // for MSR APSR_nzcvq. 3723 // but we do make it an alias here. This is so to get the "mask encoding" 3724 // bits correct on MSR APSR writes. 3725 // 3726 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3727 // should really only be allowed when writing a special register. Note 3728 // they get dropped in the MRS instruction reading a special register as 3729 // the SYSm field is only 8 bits. 3730 // 3731 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3732 // includes the DSP extension but that is not checked. 3733 .Case("apsr", 0x800) 3734 .Case("apsr_nzcvq", 0x800) 3735 .Case("apsr_g", 0x400) 3736 .Case("apsr_nzcvqg", 0xc00) 3737 .Case("iapsr", 0x801) 3738 .Case("iapsr_nzcvq", 0x801) 3739 .Case("iapsr_g", 0x401) 3740 .Case("iapsr_nzcvqg", 0xc01) 3741 .Case("eapsr", 0x802) 3742 .Case("eapsr_nzcvq", 0x802) 3743 .Case("eapsr_g", 0x402) 3744 .Case("eapsr_nzcvqg", 0xc02) 3745 .Case("xpsr", 0x803) 3746 .Case("xpsr_nzcvq", 0x803) 3747 .Case("xpsr_g", 0x403) 3748 .Case("xpsr_nzcvqg", 0xc03) 3749 .Case("ipsr", 0x805) 3750 .Case("epsr", 0x806) 3751 .Case("iepsr", 0x807) 3752 .Case("msp", 0x808) 3753 .Case("psp", 0x809) 3754 .Case("primask", 0x810) 3755 .Case("basepri", 0x811) 3756 .Case("basepri_max", 0x812) 3757 .Case("faultmask", 0x813) 3758 .Case("control", 0x814) 3759 .Default(~0U); 3760 3761 if (FlagsVal == ~0U) 3762 return MatchOperand_NoMatch; 3763 3764 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3765 // basepri, basepri_max and faultmask only valid for V7m. 3766 return MatchOperand_NoMatch; 3767 3768 Parser.Lex(); // Eat identifier token. 3769 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3770 return MatchOperand_Success; 3771 } 3772 3773 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3774 size_t Start = 0, Next = Mask.find('_'); 3775 StringRef Flags = ""; 3776 std::string SpecReg = Mask.slice(Start, Next).lower(); 3777 if (Next != StringRef::npos) 3778 Flags = Mask.slice(Next+1, Mask.size()); 3779 3780 // FlagsVal contains the complete mask: 3781 // 3-0: Mask 3782 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3783 unsigned FlagsVal = 0; 3784 3785 if (SpecReg == "apsr") { 3786 FlagsVal = StringSwitch<unsigned>(Flags) 3787 .Case("nzcvq", 0x8) // same as CPSR_f 3788 .Case("g", 0x4) // same as CPSR_s 3789 .Case("nzcvqg", 0xc) // same as CPSR_fs 3790 .Default(~0U); 3791 3792 if (FlagsVal == ~0U) { 3793 if (!Flags.empty()) 3794 return MatchOperand_NoMatch; 3795 else 3796 FlagsVal = 8; // No flag 3797 } 3798 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3799 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3800 if (Flags == "all" || Flags == "") 3801 Flags = "fc"; 3802 for (int i = 0, e = Flags.size(); i != e; ++i) { 3803 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3804 .Case("c", 1) 3805 .Case("x", 2) 3806 .Case("s", 4) 3807 .Case("f", 8) 3808 .Default(~0U); 3809 3810 // If some specific flag is already set, it means that some letter is 3811 // present more than once, this is not acceptable. 3812 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3813 return MatchOperand_NoMatch; 3814 FlagsVal |= Flag; 3815 } 3816 } else // No match for special register. 3817 return MatchOperand_NoMatch; 3818 3819 // Special register without flags is NOT equivalent to "fc" flags. 3820 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3821 // two lines would enable gas compatibility at the expense of breaking 3822 // round-tripping. 3823 // 3824 // if (!FlagsVal) 3825 // FlagsVal = 0x9; 3826 3827 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3828 if (SpecReg == "spsr") 3829 FlagsVal |= 16; 3830 3831 Parser.Lex(); // Eat identifier token. 3832 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3833 return MatchOperand_Success; 3834 } 3835 3836 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3837 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3838 int Low, int High) { 3839 const AsmToken &Tok = Parser.getTok(); 3840 if (Tok.isNot(AsmToken::Identifier)) { 3841 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3842 return MatchOperand_ParseFail; 3843 } 3844 StringRef ShiftName = Tok.getString(); 3845 std::string LowerOp = Op.lower(); 3846 std::string UpperOp = Op.upper(); 3847 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3848 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3849 return MatchOperand_ParseFail; 3850 } 3851 Parser.Lex(); // Eat shift type token. 3852 3853 // There must be a '#' and a shift amount. 3854 if (Parser.getTok().isNot(AsmToken::Hash) && 3855 Parser.getTok().isNot(AsmToken::Dollar)) { 3856 Error(Parser.getTok().getLoc(), "'#' expected"); 3857 return MatchOperand_ParseFail; 3858 } 3859 Parser.Lex(); // Eat hash token. 3860 3861 const MCExpr *ShiftAmount; 3862 SMLoc Loc = Parser.getTok().getLoc(); 3863 SMLoc EndLoc; 3864 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3865 Error(Loc, "illegal expression"); 3866 return MatchOperand_ParseFail; 3867 } 3868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3869 if (!CE) { 3870 Error(Loc, "constant expression expected"); 3871 return MatchOperand_ParseFail; 3872 } 3873 int Val = CE->getValue(); 3874 if (Val < Low || Val > High) { 3875 Error(Loc, "immediate value out of range"); 3876 return MatchOperand_ParseFail; 3877 } 3878 3879 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 3880 3881 return MatchOperand_Success; 3882 } 3883 3884 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3885 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3886 const AsmToken &Tok = Parser.getTok(); 3887 SMLoc S = Tok.getLoc(); 3888 if (Tok.isNot(AsmToken::Identifier)) { 3889 Error(S, "'be' or 'le' operand expected"); 3890 return MatchOperand_ParseFail; 3891 } 3892 int Val = StringSwitch<int>(Tok.getString().lower()) 3893 .Case("be", 1) 3894 .Case("le", 0) 3895 .Default(-1); 3896 Parser.Lex(); // Eat the token. 3897 3898 if (Val == -1) { 3899 Error(S, "'be' or 'le' operand expected"); 3900 return MatchOperand_ParseFail; 3901 } 3902 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3903 getContext()), 3904 S, Tok.getEndLoc())); 3905 return MatchOperand_Success; 3906 } 3907 3908 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3909 /// instructions. Legal values are: 3910 /// lsl #n 'n' in [0,31] 3911 /// asr #n 'n' in [1,32] 3912 /// n == 32 encoded as n == 0. 3913 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3914 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3915 const AsmToken &Tok = Parser.getTok(); 3916 SMLoc S = Tok.getLoc(); 3917 if (Tok.isNot(AsmToken::Identifier)) { 3918 Error(S, "shift operator 'asr' or 'lsl' expected"); 3919 return MatchOperand_ParseFail; 3920 } 3921 StringRef ShiftName = Tok.getString(); 3922 bool isASR; 3923 if (ShiftName == "lsl" || ShiftName == "LSL") 3924 isASR = false; 3925 else if (ShiftName == "asr" || ShiftName == "ASR") 3926 isASR = true; 3927 else { 3928 Error(S, "shift operator 'asr' or 'lsl' expected"); 3929 return MatchOperand_ParseFail; 3930 } 3931 Parser.Lex(); // Eat the operator. 3932 3933 // A '#' and a shift amount. 3934 if (Parser.getTok().isNot(AsmToken::Hash) && 3935 Parser.getTok().isNot(AsmToken::Dollar)) { 3936 Error(Parser.getTok().getLoc(), "'#' expected"); 3937 return MatchOperand_ParseFail; 3938 } 3939 Parser.Lex(); // Eat hash token. 3940 SMLoc ExLoc = Parser.getTok().getLoc(); 3941 3942 const MCExpr *ShiftAmount; 3943 SMLoc EndLoc; 3944 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3945 Error(ExLoc, "malformed shift expression"); 3946 return MatchOperand_ParseFail; 3947 } 3948 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3949 if (!CE) { 3950 Error(ExLoc, "shift amount must be an immediate"); 3951 return MatchOperand_ParseFail; 3952 } 3953 3954 int64_t Val = CE->getValue(); 3955 if (isASR) { 3956 // Shift amount must be in [1,32] 3957 if (Val < 1 || Val > 32) { 3958 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 3959 return MatchOperand_ParseFail; 3960 } 3961 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3962 if (isThumb() && Val == 32) { 3963 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 3964 return MatchOperand_ParseFail; 3965 } 3966 if (Val == 32) Val = 0; 3967 } else { 3968 // Shift amount must be in [1,32] 3969 if (Val < 0 || Val > 31) { 3970 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 3971 return MatchOperand_ParseFail; 3972 } 3973 } 3974 3975 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 3976 3977 return MatchOperand_Success; 3978 } 3979 3980 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3981 /// of instructions. Legal values are: 3982 /// ror #n 'n' in {0, 8, 16, 24} 3983 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3984 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3985 const AsmToken &Tok = Parser.getTok(); 3986 SMLoc S = Tok.getLoc(); 3987 if (Tok.isNot(AsmToken::Identifier)) 3988 return MatchOperand_NoMatch; 3989 StringRef ShiftName = Tok.getString(); 3990 if (ShiftName != "ror" && ShiftName != "ROR") 3991 return MatchOperand_NoMatch; 3992 Parser.Lex(); // Eat the operator. 3993 3994 // A '#' and a rotate amount. 3995 if (Parser.getTok().isNot(AsmToken::Hash) && 3996 Parser.getTok().isNot(AsmToken::Dollar)) { 3997 Error(Parser.getTok().getLoc(), "'#' expected"); 3998 return MatchOperand_ParseFail; 3999 } 4000 Parser.Lex(); // Eat hash token. 4001 SMLoc ExLoc = Parser.getTok().getLoc(); 4002 4003 const MCExpr *ShiftAmount; 4004 SMLoc EndLoc; 4005 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4006 Error(ExLoc, "malformed rotate expression"); 4007 return MatchOperand_ParseFail; 4008 } 4009 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4010 if (!CE) { 4011 Error(ExLoc, "rotate amount must be an immediate"); 4012 return MatchOperand_ParseFail; 4013 } 4014 4015 int64_t Val = CE->getValue(); 4016 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 4017 // normally, zero is represented in asm by omitting the rotate operand 4018 // entirely. 4019 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 4020 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 4021 return MatchOperand_ParseFail; 4022 } 4023 4024 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 4025 4026 return MatchOperand_Success; 4027 } 4028 4029 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4030 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4031 SMLoc S = Parser.getTok().getLoc(); 4032 // The bitfield descriptor is really two operands, the LSB and the width. 4033 if (Parser.getTok().isNot(AsmToken::Hash) && 4034 Parser.getTok().isNot(AsmToken::Dollar)) { 4035 Error(Parser.getTok().getLoc(), "'#' expected"); 4036 return MatchOperand_ParseFail; 4037 } 4038 Parser.Lex(); // Eat hash token. 4039 4040 const MCExpr *LSBExpr; 4041 SMLoc E = Parser.getTok().getLoc(); 4042 if (getParser().parseExpression(LSBExpr)) { 4043 Error(E, "malformed immediate expression"); 4044 return MatchOperand_ParseFail; 4045 } 4046 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 4047 if (!CE) { 4048 Error(E, "'lsb' operand must be an immediate"); 4049 return MatchOperand_ParseFail; 4050 } 4051 4052 int64_t LSB = CE->getValue(); 4053 // The LSB must be in the range [0,31] 4054 if (LSB < 0 || LSB > 31) { 4055 Error(E, "'lsb' operand must be in the range [0,31]"); 4056 return MatchOperand_ParseFail; 4057 } 4058 E = Parser.getTok().getLoc(); 4059 4060 // Expect another immediate operand. 4061 if (Parser.getTok().isNot(AsmToken::Comma)) { 4062 Error(Parser.getTok().getLoc(), "too few operands"); 4063 return MatchOperand_ParseFail; 4064 } 4065 Parser.Lex(); // Eat hash token. 4066 if (Parser.getTok().isNot(AsmToken::Hash) && 4067 Parser.getTok().isNot(AsmToken::Dollar)) { 4068 Error(Parser.getTok().getLoc(), "'#' expected"); 4069 return MatchOperand_ParseFail; 4070 } 4071 Parser.Lex(); // Eat hash token. 4072 4073 const MCExpr *WidthExpr; 4074 SMLoc EndLoc; 4075 if (getParser().parseExpression(WidthExpr, EndLoc)) { 4076 Error(E, "malformed immediate expression"); 4077 return MatchOperand_ParseFail; 4078 } 4079 CE = dyn_cast<MCConstantExpr>(WidthExpr); 4080 if (!CE) { 4081 Error(E, "'width' operand must be an immediate"); 4082 return MatchOperand_ParseFail; 4083 } 4084 4085 int64_t Width = CE->getValue(); 4086 // The LSB must be in the range [1,32-lsb] 4087 if (Width < 1 || Width > 32 - LSB) { 4088 Error(E, "'width' operand must be in the range [1,32-lsb]"); 4089 return MatchOperand_ParseFail; 4090 } 4091 4092 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 4093 4094 return MatchOperand_Success; 4095 } 4096 4097 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4098 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4099 // Check for a post-index addressing register operand. Specifically: 4100 // postidx_reg := '+' register {, shift} 4101 // | '-' register {, shift} 4102 // | register {, shift} 4103 4104 // This method must return MatchOperand_NoMatch without consuming any tokens 4105 // in the case where there is no match, as other alternatives take other 4106 // parse methods. 4107 AsmToken Tok = Parser.getTok(); 4108 SMLoc S = Tok.getLoc(); 4109 bool haveEaten = false; 4110 bool isAdd = true; 4111 if (Tok.is(AsmToken::Plus)) { 4112 Parser.Lex(); // Eat the '+' token. 4113 haveEaten = true; 4114 } else if (Tok.is(AsmToken::Minus)) { 4115 Parser.Lex(); // Eat the '-' token. 4116 isAdd = false; 4117 haveEaten = true; 4118 } 4119 4120 SMLoc E = Parser.getTok().getEndLoc(); 4121 int Reg = tryParseRegister(); 4122 if (Reg == -1) { 4123 if (!haveEaten) 4124 return MatchOperand_NoMatch; 4125 Error(Parser.getTok().getLoc(), "register expected"); 4126 return MatchOperand_ParseFail; 4127 } 4128 4129 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 4130 unsigned ShiftImm = 0; 4131 if (Parser.getTok().is(AsmToken::Comma)) { 4132 Parser.Lex(); // Eat the ','. 4133 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 4134 return MatchOperand_ParseFail; 4135 4136 // FIXME: Only approximates end...may include intervening whitespace. 4137 E = Parser.getTok().getLoc(); 4138 } 4139 4140 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 4141 ShiftImm, S, E)); 4142 4143 return MatchOperand_Success; 4144 } 4145 4146 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4147 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4148 // Check for a post-index addressing register operand. Specifically: 4149 // am3offset := '+' register 4150 // | '-' register 4151 // | register 4152 // | # imm 4153 // | # + imm 4154 // | # - imm 4155 4156 // This method must return MatchOperand_NoMatch without consuming any tokens 4157 // in the case where there is no match, as other alternatives take other 4158 // parse methods. 4159 AsmToken Tok = Parser.getTok(); 4160 SMLoc S = Tok.getLoc(); 4161 4162 // Do immediates first, as we always parse those if we have a '#'. 4163 if (Parser.getTok().is(AsmToken::Hash) || 4164 Parser.getTok().is(AsmToken::Dollar)) { 4165 Parser.Lex(); // Eat '#' or '$'. 4166 // Explicitly look for a '-', as we need to encode negative zero 4167 // differently. 4168 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4169 const MCExpr *Offset; 4170 SMLoc E; 4171 if (getParser().parseExpression(Offset, E)) 4172 return MatchOperand_ParseFail; 4173 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4174 if (!CE) { 4175 Error(S, "constant expression expected"); 4176 return MatchOperand_ParseFail; 4177 } 4178 // Negative zero is encoded as the flag value INT32_MIN. 4179 int32_t Val = CE->getValue(); 4180 if (isNegative && Val == 0) 4181 Val = INT32_MIN; 4182 4183 Operands.push_back( 4184 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 4185 4186 return MatchOperand_Success; 4187 } 4188 4189 4190 bool haveEaten = false; 4191 bool isAdd = true; 4192 if (Tok.is(AsmToken::Plus)) { 4193 Parser.Lex(); // Eat the '+' token. 4194 haveEaten = true; 4195 } else if (Tok.is(AsmToken::Minus)) { 4196 Parser.Lex(); // Eat the '-' token. 4197 isAdd = false; 4198 haveEaten = true; 4199 } 4200 4201 Tok = Parser.getTok(); 4202 int Reg = tryParseRegister(); 4203 if (Reg == -1) { 4204 if (!haveEaten) 4205 return MatchOperand_NoMatch; 4206 Error(Tok.getLoc(), "register expected"); 4207 return MatchOperand_ParseFail; 4208 } 4209 4210 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 4211 0, S, Tok.getEndLoc())); 4212 4213 return MatchOperand_Success; 4214 } 4215 4216 /// Convert parsed operands to MCInst. Needed here because this instruction 4217 /// only has two register operands, but multiplication is commutative so 4218 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". 4219 void ARMAsmParser:: 4220 cvtThumbMultiply(MCInst &Inst, 4221 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4222 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4223 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4224 // If we have a three-operand form, make sure to set Rn to be the operand 4225 // that isn't the same as Rd. 4226 unsigned RegOp = 4; 4227 if (Operands.size() == 6 && 4228 ((ARMOperand*)Operands[4])->getReg() == 4229 ((ARMOperand*)Operands[3])->getReg()) 4230 RegOp = 5; 4231 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4232 Inst.addOperand(Inst.getOperand(0)); 4233 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4234 } 4235 4236 void ARMAsmParser:: 4237 cvtThumbBranches(MCInst &Inst, 4238 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4239 int CondOp = -1, ImmOp = -1; 4240 switch(Inst.getOpcode()) { 4241 case ARM::tB: 4242 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; 4243 4244 case ARM::t2B: 4245 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; 4246 4247 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches"); 4248 } 4249 // first decide whether or not the branch should be conditional 4250 // by looking at it's location relative to an IT block 4251 if(inITBlock()) { 4252 // inside an IT block we cannot have any conditional branches. any 4253 // such instructions needs to be converted to unconditional form 4254 switch(Inst.getOpcode()) { 4255 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; 4256 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; 4257 } 4258 } else { 4259 // outside IT blocks we can only have unconditional branches with AL 4260 // condition code or conditional branches with non-AL condition code 4261 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode(); 4262 switch(Inst.getOpcode()) { 4263 case ARM::tB: 4264 case ARM::tBcc: 4265 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); 4266 break; 4267 case ARM::t2B: 4268 case ARM::t2Bcc: 4269 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); 4270 break; 4271 } 4272 } 4273 4274 // now decide on encoding size based on branch target range 4275 switch(Inst.getOpcode()) { 4276 // classify tB as either t2B or t1B based on range of immediate operand 4277 case ARM::tB: { 4278 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]); 4279 if(!op->isSignedOffset<11, 1>() && isThumbTwo()) 4280 Inst.setOpcode(ARM::t2B); 4281 break; 4282 } 4283 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand 4284 case ARM::tBcc: { 4285 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]); 4286 if(!op->isSignedOffset<8, 1>() && isThumbTwo()) 4287 Inst.setOpcode(ARM::t2Bcc); 4288 break; 4289 } 4290 } 4291 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1); 4292 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2); 4293 } 4294 4295 /// Parse an ARM memory expression, return false if successful else return true 4296 /// or an error. The first token must be a '[' when called. 4297 bool ARMAsmParser:: 4298 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4299 SMLoc S, E; 4300 assert(Parser.getTok().is(AsmToken::LBrac) && 4301 "Token is not a Left Bracket"); 4302 S = Parser.getTok().getLoc(); 4303 Parser.Lex(); // Eat left bracket token. 4304 4305 const AsmToken &BaseRegTok = Parser.getTok(); 4306 int BaseRegNum = tryParseRegister(); 4307 if (BaseRegNum == -1) 4308 return Error(BaseRegTok.getLoc(), "register expected"); 4309 4310 // The next token must either be a comma, a colon or a closing bracket. 4311 const AsmToken &Tok = Parser.getTok(); 4312 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 4313 !Tok.is(AsmToken::RBrac)) 4314 return Error(Tok.getLoc(), "malformed memory operand"); 4315 4316 if (Tok.is(AsmToken::RBrac)) { 4317 E = Tok.getEndLoc(); 4318 Parser.Lex(); // Eat right bracket token. 4319 4320 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4321 0, 0, false, S, E)); 4322 4323 // If there's a pre-indexing writeback marker, '!', just add it as a token 4324 // operand. It's rather odd, but syntactically valid. 4325 if (Parser.getTok().is(AsmToken::Exclaim)) { 4326 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4327 Parser.Lex(); // Eat the '!'. 4328 } 4329 4330 return false; 4331 } 4332 4333 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 4334 "Lost colon or comma in memory operand?!"); 4335 if (Tok.is(AsmToken::Comma)) { 4336 Parser.Lex(); // Eat the comma. 4337 } 4338 4339 // If we have a ':', it's an alignment specifier. 4340 if (Parser.getTok().is(AsmToken::Colon)) { 4341 Parser.Lex(); // Eat the ':'. 4342 E = Parser.getTok().getLoc(); 4343 4344 const MCExpr *Expr; 4345 if (getParser().parseExpression(Expr)) 4346 return true; 4347 4348 // The expression has to be a constant. Memory references with relocations 4349 // don't come through here, as they use the <label> forms of the relevant 4350 // instructions. 4351 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4352 if (!CE) 4353 return Error (E, "constant expression expected"); 4354 4355 unsigned Align = 0; 4356 switch (CE->getValue()) { 4357 default: 4358 return Error(E, 4359 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4360 case 16: Align = 2; break; 4361 case 32: Align = 4; break; 4362 case 64: Align = 8; break; 4363 case 128: Align = 16; break; 4364 case 256: Align = 32; break; 4365 } 4366 4367 // Now we should have the closing ']' 4368 if (Parser.getTok().isNot(AsmToken::RBrac)) 4369 return Error(Parser.getTok().getLoc(), "']' expected"); 4370 E = Parser.getTok().getEndLoc(); 4371 Parser.Lex(); // Eat right bracket token. 4372 4373 // Don't worry about range checking the value here. That's handled by 4374 // the is*() predicates. 4375 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4376 ARM_AM::no_shift, 0, Align, 4377 false, S, E)); 4378 4379 // If there's a pre-indexing writeback marker, '!', just add it as a token 4380 // operand. 4381 if (Parser.getTok().is(AsmToken::Exclaim)) { 4382 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4383 Parser.Lex(); // Eat the '!'. 4384 } 4385 4386 return false; 4387 } 4388 4389 // If we have a '#', it's an immediate offset, else assume it's a register 4390 // offset. Be friendly and also accept a plain integer (without a leading 4391 // hash) for gas compatibility. 4392 if (Parser.getTok().is(AsmToken::Hash) || 4393 Parser.getTok().is(AsmToken::Dollar) || 4394 Parser.getTok().is(AsmToken::Integer)) { 4395 if (Parser.getTok().isNot(AsmToken::Integer)) 4396 Parser.Lex(); // Eat '#' or '$'. 4397 E = Parser.getTok().getLoc(); 4398 4399 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4400 const MCExpr *Offset; 4401 if (getParser().parseExpression(Offset)) 4402 return true; 4403 4404 // The expression has to be a constant. Memory references with relocations 4405 // don't come through here, as they use the <label> forms of the relevant 4406 // instructions. 4407 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4408 if (!CE) 4409 return Error (E, "constant expression expected"); 4410 4411 // If the constant was #-0, represent it as INT32_MIN. 4412 int32_t Val = CE->getValue(); 4413 if (isNegative && Val == 0) 4414 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4415 4416 // Now we should have the closing ']' 4417 if (Parser.getTok().isNot(AsmToken::RBrac)) 4418 return Error(Parser.getTok().getLoc(), "']' expected"); 4419 E = Parser.getTok().getEndLoc(); 4420 Parser.Lex(); // Eat right bracket token. 4421 4422 // Don't worry about range checking the value here. That's handled by 4423 // the is*() predicates. 4424 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4425 ARM_AM::no_shift, 0, 0, 4426 false, S, E)); 4427 4428 // If there's a pre-indexing writeback marker, '!', just add it as a token 4429 // operand. 4430 if (Parser.getTok().is(AsmToken::Exclaim)) { 4431 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4432 Parser.Lex(); // Eat the '!'. 4433 } 4434 4435 return false; 4436 } 4437 4438 // The register offset is optionally preceded by a '+' or '-' 4439 bool isNegative = false; 4440 if (Parser.getTok().is(AsmToken::Minus)) { 4441 isNegative = true; 4442 Parser.Lex(); // Eat the '-'. 4443 } else if (Parser.getTok().is(AsmToken::Plus)) { 4444 // Nothing to do. 4445 Parser.Lex(); // Eat the '+'. 4446 } 4447 4448 E = Parser.getTok().getLoc(); 4449 int OffsetRegNum = tryParseRegister(); 4450 if (OffsetRegNum == -1) 4451 return Error(E, "register expected"); 4452 4453 // If there's a shift operator, handle it. 4454 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4455 unsigned ShiftImm = 0; 4456 if (Parser.getTok().is(AsmToken::Comma)) { 4457 Parser.Lex(); // Eat the ','. 4458 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4459 return true; 4460 } 4461 4462 // Now we should have the closing ']' 4463 if (Parser.getTok().isNot(AsmToken::RBrac)) 4464 return Error(Parser.getTok().getLoc(), "']' expected"); 4465 E = Parser.getTok().getEndLoc(); 4466 Parser.Lex(); // Eat right bracket token. 4467 4468 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4469 ShiftType, ShiftImm, 0, isNegative, 4470 S, E)); 4471 4472 // If there's a pre-indexing writeback marker, '!', just add it as a token 4473 // operand. 4474 if (Parser.getTok().is(AsmToken::Exclaim)) { 4475 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4476 Parser.Lex(); // Eat the '!'. 4477 } 4478 4479 return false; 4480 } 4481 4482 /// parseMemRegOffsetShift - one of these two: 4483 /// ( lsl | lsr | asr | ror ) , # shift_amount 4484 /// rrx 4485 /// return true if it parses a shift otherwise it returns false. 4486 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4487 unsigned &Amount) { 4488 SMLoc Loc = Parser.getTok().getLoc(); 4489 const AsmToken &Tok = Parser.getTok(); 4490 if (Tok.isNot(AsmToken::Identifier)) 4491 return true; 4492 StringRef ShiftName = Tok.getString(); 4493 if (ShiftName == "lsl" || ShiftName == "LSL" || 4494 ShiftName == "asl" || ShiftName == "ASL") 4495 St = ARM_AM::lsl; 4496 else if (ShiftName == "lsr" || ShiftName == "LSR") 4497 St = ARM_AM::lsr; 4498 else if (ShiftName == "asr" || ShiftName == "ASR") 4499 St = ARM_AM::asr; 4500 else if (ShiftName == "ror" || ShiftName == "ROR") 4501 St = ARM_AM::ror; 4502 else if (ShiftName == "rrx" || ShiftName == "RRX") 4503 St = ARM_AM::rrx; 4504 else 4505 return Error(Loc, "illegal shift operator"); 4506 Parser.Lex(); // Eat shift type token. 4507 4508 // rrx stands alone. 4509 Amount = 0; 4510 if (St != ARM_AM::rrx) { 4511 Loc = Parser.getTok().getLoc(); 4512 // A '#' and a shift amount. 4513 const AsmToken &HashTok = Parser.getTok(); 4514 if (HashTok.isNot(AsmToken::Hash) && 4515 HashTok.isNot(AsmToken::Dollar)) 4516 return Error(HashTok.getLoc(), "'#' expected"); 4517 Parser.Lex(); // Eat hash token. 4518 4519 const MCExpr *Expr; 4520 if (getParser().parseExpression(Expr)) 4521 return true; 4522 // Range check the immediate. 4523 // lsl, ror: 0 <= imm <= 31 4524 // lsr, asr: 0 <= imm <= 32 4525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4526 if (!CE) 4527 return Error(Loc, "shift amount must be an immediate"); 4528 int64_t Imm = CE->getValue(); 4529 if (Imm < 0 || 4530 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4531 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4532 return Error(Loc, "immediate shift value out of range"); 4533 // If <ShiftTy> #0, turn it into a no_shift. 4534 if (Imm == 0) 4535 St = ARM_AM::lsl; 4536 // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 4537 if (Imm == 32) 4538 Imm = 0; 4539 Amount = Imm; 4540 } 4541 4542 return false; 4543 } 4544 4545 /// parseFPImm - A floating point immediate expression operand. 4546 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4547 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4548 // Anything that can accept a floating point constant as an operand 4549 // needs to go through here, as the regular parseExpression is 4550 // integer only. 4551 // 4552 // This routine still creates a generic Immediate operand, containing 4553 // a bitcast of the 64-bit floating point value. The various operands 4554 // that accept floats can check whether the value is valid for them 4555 // via the standard is*() predicates. 4556 4557 SMLoc S = Parser.getTok().getLoc(); 4558 4559 if (Parser.getTok().isNot(AsmToken::Hash) && 4560 Parser.getTok().isNot(AsmToken::Dollar)) 4561 return MatchOperand_NoMatch; 4562 4563 // Disambiguate the VMOV forms that can accept an FP immediate. 4564 // vmov.f32 <sreg>, #imm 4565 // vmov.f64 <dreg>, #imm 4566 // vmov.f32 <dreg>, #imm @ vector f32x2 4567 // vmov.f32 <qreg>, #imm @ vector f32x4 4568 // 4569 // There are also the NEON VMOV instructions which expect an 4570 // integer constant. Make sure we don't try to parse an FPImm 4571 // for these: 4572 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4573 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4574 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" || 4575 TyOp->getToken() == ".f64"); 4576 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]); 4577 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" || 4578 Mnemonic->getToken() == "fconsts"); 4579 if (!(isVmovf || isFconst)) 4580 return MatchOperand_NoMatch; 4581 4582 Parser.Lex(); // Eat '#' or '$'. 4583 4584 // Handle negation, as that still comes through as a separate token. 4585 bool isNegative = false; 4586 if (Parser.getTok().is(AsmToken::Minus)) { 4587 isNegative = true; 4588 Parser.Lex(); 4589 } 4590 const AsmToken &Tok = Parser.getTok(); 4591 SMLoc Loc = Tok.getLoc(); 4592 if (Tok.is(AsmToken::Real) && isVmovf) { 4593 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4594 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4595 // If we had a '-' in front, toggle the sign bit. 4596 IntVal ^= (uint64_t)isNegative << 31; 4597 Parser.Lex(); // Eat the token. 4598 Operands.push_back(ARMOperand::CreateImm( 4599 MCConstantExpr::Create(IntVal, getContext()), 4600 S, Parser.getTok().getLoc())); 4601 return MatchOperand_Success; 4602 } 4603 // Also handle plain integers. Instructions which allow floating point 4604 // immediates also allow a raw encoded 8-bit value. 4605 if (Tok.is(AsmToken::Integer) && isFconst) { 4606 int64_t Val = Tok.getIntVal(); 4607 Parser.Lex(); // Eat the token. 4608 if (Val > 255 || Val < 0) { 4609 Error(Loc, "encoded floating point value out of range"); 4610 return MatchOperand_ParseFail; 4611 } 4612 float RealVal = ARM_AM::getFPImmFloat(Val); 4613 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue(); 4614 4615 Operands.push_back(ARMOperand::CreateImm( 4616 MCConstantExpr::Create(Val, getContext()), S, 4617 Parser.getTok().getLoc())); 4618 return MatchOperand_Success; 4619 } 4620 4621 Error(Loc, "invalid floating point immediate"); 4622 return MatchOperand_ParseFail; 4623 } 4624 4625 /// Parse a arm instruction operand. For now this parses the operand regardless 4626 /// of the mnemonic. 4627 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4628 StringRef Mnemonic) { 4629 SMLoc S, E; 4630 4631 // Check if the current operand has a custom associated parser, if so, try to 4632 // custom parse the operand, or fallback to the general approach. 4633 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4634 if (ResTy == MatchOperand_Success) 4635 return false; 4636 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4637 // there was a match, but an error occurred, in which case, just return that 4638 // the operand parsing failed. 4639 if (ResTy == MatchOperand_ParseFail) 4640 return true; 4641 4642 switch (getLexer().getKind()) { 4643 default: 4644 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4645 return true; 4646 case AsmToken::Identifier: { 4647 // If we've seen a branch mnemonic, the next operand must be a label. This 4648 // is true even if the label is a register name. So "br r1" means branch to 4649 // label "r1". 4650 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 4651 if (!ExpectLabel) { 4652 if (!tryParseRegisterWithWriteBack(Operands)) 4653 return false; 4654 int Res = tryParseShiftRegister(Operands); 4655 if (Res == 0) // success 4656 return false; 4657 else if (Res == -1) // irrecoverable error 4658 return true; 4659 // If this is VMRS, check for the apsr_nzcv operand. 4660 if (Mnemonic == "vmrs" && 4661 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4662 S = Parser.getTok().getLoc(); 4663 Parser.Lex(); 4664 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4665 return false; 4666 } 4667 } 4668 4669 // Fall though for the Identifier case that is not a register or a 4670 // special name. 4671 } 4672 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4673 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4674 case AsmToken::String: // quoted label names. 4675 case AsmToken::Dot: { // . as a branch target 4676 // This was not a register so parse other operands that start with an 4677 // identifier (like labels) as expressions and create them as immediates. 4678 const MCExpr *IdVal; 4679 S = Parser.getTok().getLoc(); 4680 if (getParser().parseExpression(IdVal)) 4681 return true; 4682 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4683 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4684 return false; 4685 } 4686 case AsmToken::LBrac: 4687 return parseMemory(Operands); 4688 case AsmToken::LCurly: 4689 return parseRegisterList(Operands); 4690 case AsmToken::Dollar: 4691 case AsmToken::Hash: { 4692 // #42 -> immediate. 4693 S = Parser.getTok().getLoc(); 4694 Parser.Lex(); 4695 4696 if (Parser.getTok().isNot(AsmToken::Colon)) { 4697 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4698 const MCExpr *ImmVal; 4699 if (getParser().parseExpression(ImmVal)) 4700 return true; 4701 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4702 if (CE) { 4703 int32_t Val = CE->getValue(); 4704 if (isNegative && Val == 0) 4705 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4706 } 4707 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4708 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4709 4710 // There can be a trailing '!' on operands that we want as a separate 4711 // '!' Token operand. Handle that here. For example, the compatibility 4712 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 4713 if (Parser.getTok().is(AsmToken::Exclaim)) { 4714 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 4715 Parser.getTok().getLoc())); 4716 Parser.Lex(); // Eat exclaim token 4717 } 4718 return false; 4719 } 4720 // w/ a ':' after the '#', it's just like a plain ':'. 4721 // FALLTHROUGH 4722 } 4723 case AsmToken::Colon: { 4724 // ":lower16:" and ":upper16:" expression prefixes 4725 // FIXME: Check it's an expression prefix, 4726 // e.g. (FOO - :lower16:BAR) isn't legal. 4727 ARMMCExpr::VariantKind RefKind; 4728 if (parsePrefix(RefKind)) 4729 return true; 4730 4731 const MCExpr *SubExprVal; 4732 if (getParser().parseExpression(SubExprVal)) 4733 return true; 4734 4735 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4736 getContext()); 4737 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4738 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4739 return false; 4740 } 4741 case AsmToken::Equal: { 4742 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val) 4743 return Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4744 4745 Parser.Lex(); // Eat '=' 4746 const MCExpr *SubExprVal; 4747 if (getParser().parseExpression(SubExprVal)) 4748 return true; 4749 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4750 4751 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal); 4752 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E)); 4753 return false; 4754 } 4755 } 4756 } 4757 4758 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4759 // :lower16: and :upper16:. 4760 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4761 RefKind = ARMMCExpr::VK_ARM_None; 4762 4763 // consume an optional '#' (GNU compatibility) 4764 if (getLexer().is(AsmToken::Hash)) 4765 Parser.Lex(); 4766 4767 // :lower16: and :upper16: modifiers 4768 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4769 Parser.Lex(); // Eat ':' 4770 4771 if (getLexer().isNot(AsmToken::Identifier)) { 4772 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4773 return true; 4774 } 4775 4776 StringRef IDVal = Parser.getTok().getIdentifier(); 4777 if (IDVal == "lower16") { 4778 RefKind = ARMMCExpr::VK_ARM_LO16; 4779 } else if (IDVal == "upper16") { 4780 RefKind = ARMMCExpr::VK_ARM_HI16; 4781 } else { 4782 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4783 return true; 4784 } 4785 Parser.Lex(); 4786 4787 if (getLexer().isNot(AsmToken::Colon)) { 4788 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4789 return true; 4790 } 4791 Parser.Lex(); // Eat the last ':' 4792 return false; 4793 } 4794 4795 /// \brief Given a mnemonic, split out possible predication code and carry 4796 /// setting letters to form a canonical mnemonic and flags. 4797 // 4798 // FIXME: Would be nice to autogen this. 4799 // FIXME: This is a bit of a maze of special cases. 4800 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4801 unsigned &PredicationCode, 4802 bool &CarrySetting, 4803 unsigned &ProcessorIMod, 4804 StringRef &ITMask) { 4805 PredicationCode = ARMCC::AL; 4806 CarrySetting = false; 4807 ProcessorIMod = 0; 4808 4809 // Ignore some mnemonics we know aren't predicated forms. 4810 // 4811 // FIXME: Would be nice to autogen this. 4812 if ((Mnemonic == "movs" && isThumb()) || 4813 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4814 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4815 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4816 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4817 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" || 4818 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4819 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4820 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4821 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || 4822 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || 4823 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || 4824 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel")) 4825 return Mnemonic; 4826 4827 // First, split out any predication code. Ignore mnemonics we know aren't 4828 // predicated but do have a carry-set and so weren't caught above. 4829 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4830 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4831 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4832 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4833 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4834 .Case("eq", ARMCC::EQ) 4835 .Case("ne", ARMCC::NE) 4836 .Case("hs", ARMCC::HS) 4837 .Case("cs", ARMCC::HS) 4838 .Case("lo", ARMCC::LO) 4839 .Case("cc", ARMCC::LO) 4840 .Case("mi", ARMCC::MI) 4841 .Case("pl", ARMCC::PL) 4842 .Case("vs", ARMCC::VS) 4843 .Case("vc", ARMCC::VC) 4844 .Case("hi", ARMCC::HI) 4845 .Case("ls", ARMCC::LS) 4846 .Case("ge", ARMCC::GE) 4847 .Case("lt", ARMCC::LT) 4848 .Case("gt", ARMCC::GT) 4849 .Case("le", ARMCC::LE) 4850 .Case("al", ARMCC::AL) 4851 .Default(~0U); 4852 if (CC != ~0U) { 4853 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4854 PredicationCode = CC; 4855 } 4856 } 4857 4858 // Next, determine if we have a carry setting bit. We explicitly ignore all 4859 // the instructions we know end in 's'. 4860 if (Mnemonic.endswith("s") && 4861 !(Mnemonic == "cps" || Mnemonic == "mls" || 4862 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4863 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4864 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4865 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4866 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4867 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4868 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4869 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || 4870 (Mnemonic == "movs" && isThumb()))) { 4871 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4872 CarrySetting = true; 4873 } 4874 4875 // The "cps" instruction can have a interrupt mode operand which is glued into 4876 // the mnemonic. Check if this is the case, split it and parse the imod op 4877 if (Mnemonic.startswith("cps")) { 4878 // Split out any imod code. 4879 unsigned IMod = 4880 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4881 .Case("ie", ARM_PROC::IE) 4882 .Case("id", ARM_PROC::ID) 4883 .Default(~0U); 4884 if (IMod != ~0U) { 4885 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4886 ProcessorIMod = IMod; 4887 } 4888 } 4889 4890 // The "it" instruction has the condition mask on the end of the mnemonic. 4891 if (Mnemonic.startswith("it")) { 4892 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4893 Mnemonic = Mnemonic.slice(0, 2); 4894 } 4895 4896 return Mnemonic; 4897 } 4898 4899 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 4900 /// inclusion of carry set or predication code operands. 4901 // 4902 // FIXME: It would be nice to autogen this. 4903 void ARMAsmParser:: 4904 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 4905 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) { 4906 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4907 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4908 Mnemonic == "add" || Mnemonic == "adc" || 4909 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4910 Mnemonic == "orr" || Mnemonic == "mvn" || 4911 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4912 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4913 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4914 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4915 Mnemonic == "mla" || Mnemonic == "smlal" || 4916 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4917 CanAcceptCarrySet = true; 4918 } else 4919 CanAcceptCarrySet = false; 4920 4921 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || 4922 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || 4923 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") || 4924 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") || 4925 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" || 4926 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || 4927 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" || 4928 Mnemonic == "vrintm" || Mnemonic.startswith("aes") || 4929 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") || 4930 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) { 4931 // These mnemonics are never predicable 4932 CanAcceptPredicationCode = false; 4933 } else if (!isThumb()) { 4934 // Some instructions are only predicable in Thumb mode 4935 CanAcceptPredicationCode 4936 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && 4937 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && 4938 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" && 4939 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" && 4940 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && 4941 Mnemonic != "stc2" && Mnemonic != "stc2l" && 4942 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs"); 4943 } else if (isThumbOne()) { 4944 if (hasV6MOps()) 4945 CanAcceptPredicationCode = Mnemonic != "movs"; 4946 else 4947 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; 4948 } else 4949 CanAcceptPredicationCode = true; 4950 } 4951 4952 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4953 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4954 // FIXME: This is all horribly hacky. We really need a better way to deal 4955 // with optional operands like this in the matcher table. 4956 4957 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4958 // another does not. Specifically, the MOVW instruction does not. So we 4959 // special case it here and remove the defaulted (non-setting) cc_out 4960 // operand if that's the instruction we're trying to match. 4961 // 4962 // We do this as post-processing of the explicit operands rather than just 4963 // conditionally adding the cc_out in the first place because we need 4964 // to check the type of the parsed immediate operand. 4965 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4966 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4967 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4968 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4969 return true; 4970 4971 // Register-register 'add' for thumb does not have a cc_out operand 4972 // when there are only two register operands. 4973 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4974 static_cast<ARMOperand*>(Operands[3])->isReg() && 4975 static_cast<ARMOperand*>(Operands[4])->isReg() && 4976 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4977 return true; 4978 // Register-register 'add' for thumb does not have a cc_out operand 4979 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4980 // have to check the immediate range here since Thumb2 has a variant 4981 // that can handle a different range and has a cc_out operand. 4982 if (((isThumb() && Mnemonic == "add") || 4983 (isThumbTwo() && Mnemonic == "sub")) && 4984 Operands.size() == 6 && 4985 static_cast<ARMOperand*>(Operands[3])->isReg() && 4986 static_cast<ARMOperand*>(Operands[4])->isReg() && 4987 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4988 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4989 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 4990 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4991 return true; 4992 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4993 // imm0_4095 variant. That's the least-preferred variant when 4994 // selecting via the generic "add" mnemonic, so to know that we 4995 // should remove the cc_out operand, we have to explicitly check that 4996 // it's not one of the other variants. Ugh. 4997 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4998 Operands.size() == 6 && 4999 static_cast<ARMOperand*>(Operands[3])->isReg() && 5000 static_cast<ARMOperand*>(Operands[4])->isReg() && 5001 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5002 // Nest conditions rather than one big 'if' statement for readability. 5003 // 5004 // If both registers are low, we're in an IT block, and the immediate is 5005 // in range, we should use encoding T1 instead, which has a cc_out. 5006 if (inITBlock() && 5007 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 5008 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 5009 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 5010 return false; 5011 // Check against T3. If the second register is the PC, this is an 5012 // alternate form of ADR, which uses encoding T4, so check for that too. 5013 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 5014 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 5015 return false; 5016 5017 // Otherwise, we use encoding T4, which does not have a cc_out 5018 // operand. 5019 return true; 5020 } 5021 5022 // The thumb2 multiply instruction doesn't have a CCOut register, so 5023 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 5024 // use the 16-bit encoding or not. 5025 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 5026 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5027 static_cast<ARMOperand*>(Operands[3])->isReg() && 5028 static_cast<ARMOperand*>(Operands[4])->isReg() && 5029 static_cast<ARMOperand*>(Operands[5])->isReg() && 5030 // If the registers aren't low regs, the destination reg isn't the 5031 // same as one of the source regs, or the cc_out operand is zero 5032 // outside of an IT block, we have to use the 32-bit encoding, so 5033 // remove the cc_out operand. 5034 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5035 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 5036 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 5037 !inITBlock() || 5038 (static_cast<ARMOperand*>(Operands[3])->getReg() != 5039 static_cast<ARMOperand*>(Operands[5])->getReg() && 5040 static_cast<ARMOperand*>(Operands[3])->getReg() != 5041 static_cast<ARMOperand*>(Operands[4])->getReg()))) 5042 return true; 5043 5044 // Also check the 'mul' syntax variant that doesn't specify an explicit 5045 // destination register. 5046 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 5047 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5048 static_cast<ARMOperand*>(Operands[3])->isReg() && 5049 static_cast<ARMOperand*>(Operands[4])->isReg() && 5050 // If the registers aren't low regs or the cc_out operand is zero 5051 // outside of an IT block, we have to use the 32-bit encoding, so 5052 // remove the cc_out operand. 5053 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5054 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 5055 !inITBlock())) 5056 return true; 5057 5058 5059 5060 // Register-register 'add/sub' for thumb does not have a cc_out operand 5061 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 5062 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 5063 // right, this will result in better diagnostics (which operand is off) 5064 // anyway. 5065 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 5066 (Operands.size() == 5 || Operands.size() == 6) && 5067 static_cast<ARMOperand*>(Operands[3])->isReg() && 5068 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 5069 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5070 (static_cast<ARMOperand*>(Operands[4])->isImm() || 5071 (Operands.size() == 6 && 5072 static_cast<ARMOperand*>(Operands[5])->isImm()))) 5073 return true; 5074 5075 return false; 5076 } 5077 5078 bool ARMAsmParser::shouldOmitPredicateOperand( 5079 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) { 5080 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON 5081 unsigned RegIdx = 3; 5082 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") && 5083 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") { 5084 if (static_cast<ARMOperand *>(Operands[3])->isToken() && 5085 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32") 5086 RegIdx = 4; 5087 5088 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() && 5089 (ARMMCRegisterClasses[ARM::DPRRegClassID] 5090 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) || 5091 ARMMCRegisterClasses[ARM::QPRRegClassID] 5092 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()))) 5093 return true; 5094 } 5095 return false; 5096 } 5097 5098 static bool isDataTypeToken(StringRef Tok) { 5099 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 5100 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 5101 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 5102 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 5103 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 5104 Tok == ".f" || Tok == ".d"; 5105 } 5106 5107 // FIXME: This bit should probably be handled via an explicit match class 5108 // in the .td files that matches the suffix instead of having it be 5109 // a literal string token the way it is now. 5110 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 5111 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 5112 } 5113 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, 5114 unsigned VariantID); 5115 5116 static bool RequiresVFPRegListValidation(StringRef Inst, 5117 bool &AcceptSinglePrecisionOnly, 5118 bool &AcceptDoublePrecisionOnly) { 5119 if (Inst.size() < 7) 5120 return false; 5121 5122 if (Inst.startswith("fldm") || Inst.startswith("fstm")) { 5123 StringRef AddressingMode = Inst.substr(4, 2); 5124 if (AddressingMode == "ia" || AddressingMode == "db" || 5125 AddressingMode == "ea" || AddressingMode == "fd") { 5126 AcceptSinglePrecisionOnly = Inst[6] == 's'; 5127 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x'; 5128 return true; 5129 } 5130 } 5131 5132 return false; 5133 } 5134 5135 /// Parse an arm instruction mnemonic followed by its operands. 5136 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 5137 SMLoc NameLoc, 5138 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5139 // FIXME: Can this be done via tablegen in some fashion? 5140 bool RequireVFPRegisterListCheck; 5141 bool AcceptSinglePrecisionOnly; 5142 bool AcceptDoublePrecisionOnly; 5143 RequireVFPRegisterListCheck = 5144 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly, 5145 AcceptDoublePrecisionOnly); 5146 5147 // Apply mnemonic aliases before doing anything else, as the destination 5148 // mnemonic may include suffices and we want to handle them normally. 5149 // The generic tblgen'erated code does this later, at the start of 5150 // MatchInstructionImpl(), but that's too late for aliases that include 5151 // any sort of suffix. 5152 unsigned AvailableFeatures = getAvailableFeatures(); 5153 unsigned AssemblerDialect = getParser().getAssemblerDialect(); 5154 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 5155 5156 // First check for the ARM-specific .req directive. 5157 if (Parser.getTok().is(AsmToken::Identifier) && 5158 Parser.getTok().getIdentifier() == ".req") { 5159 parseDirectiveReq(Name, NameLoc); 5160 // We always return 'error' for this, as we're done with this 5161 // statement and don't need to match the 'instruction." 5162 return true; 5163 } 5164 5165 // Create the leading tokens for the mnemonic, split by '.' characters. 5166 size_t Start = 0, Next = Name.find('.'); 5167 StringRef Mnemonic = Name.slice(Start, Next); 5168 5169 // Split out the predication code and carry setting flag from the mnemonic. 5170 unsigned PredicationCode; 5171 unsigned ProcessorIMod; 5172 bool CarrySetting; 5173 StringRef ITMask; 5174 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5175 ProcessorIMod, ITMask); 5176 5177 // In Thumb1, only the branch (B) instruction can be predicated. 5178 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 5179 Parser.eatToEndOfStatement(); 5180 return Error(NameLoc, "conditional execution not supported in Thumb1"); 5181 } 5182 5183 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5184 5185 // Handle the IT instruction ITMask. Convert it to a bitmask. This 5186 // is the mask as it will be for the IT encoding if the conditional 5187 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5188 // where the conditional bit0 is zero, the instruction post-processing 5189 // will adjust the mask accordingly. 5190 if (Mnemonic == "it") { 5191 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5192 if (ITMask.size() > 3) { 5193 Parser.eatToEndOfStatement(); 5194 return Error(Loc, "too many conditions on IT instruction"); 5195 } 5196 unsigned Mask = 8; 5197 for (unsigned i = ITMask.size(); i != 0; --i) { 5198 char pos = ITMask[i - 1]; 5199 if (pos != 't' && pos != 'e') { 5200 Parser.eatToEndOfStatement(); 5201 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5202 } 5203 Mask >>= 1; 5204 if (ITMask[i - 1] == 't') 5205 Mask |= 8; 5206 } 5207 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5208 } 5209 5210 // FIXME: This is all a pretty gross hack. We should automatically handle 5211 // optional operands like this via tblgen. 5212 5213 // Next, add the CCOut and ConditionCode operands, if needed. 5214 // 5215 // For mnemonics which can ever incorporate a carry setting bit or predication 5216 // code, our matching model involves us always generating CCOut and 5217 // ConditionCode operands to match the mnemonic "as written" and then we let 5218 // the matcher deal with finding the right instruction or generating an 5219 // appropriate error. 5220 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5221 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode); 5222 5223 // If we had a carry-set on an instruction that can't do that, issue an 5224 // error. 5225 if (!CanAcceptCarrySet && CarrySetting) { 5226 Parser.eatToEndOfStatement(); 5227 return Error(NameLoc, "instruction '" + Mnemonic + 5228 "' can not set flags, but 's' suffix specified"); 5229 } 5230 // If we had a predication code on an instruction that can't do that, issue an 5231 // error. 5232 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5233 Parser.eatToEndOfStatement(); 5234 return Error(NameLoc, "instruction '" + Mnemonic + 5235 "' is not predicable, but condition code specified"); 5236 } 5237 5238 // Add the carry setting operand, if necessary. 5239 if (CanAcceptCarrySet) { 5240 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5241 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5242 Loc)); 5243 } 5244 5245 // Add the predication code operand, if necessary. 5246 if (CanAcceptPredicationCode) { 5247 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5248 CarrySetting); 5249 Operands.push_back(ARMOperand::CreateCondCode( 5250 ARMCC::CondCodes(PredicationCode), Loc)); 5251 } 5252 5253 // Add the processor imod operand, if necessary. 5254 if (ProcessorIMod) { 5255 Operands.push_back(ARMOperand::CreateImm( 5256 MCConstantExpr::Create(ProcessorIMod, getContext()), 5257 NameLoc, NameLoc)); 5258 } 5259 5260 // Add the remaining tokens in the mnemonic. 5261 while (Next != StringRef::npos) { 5262 Start = Next; 5263 Next = Name.find('.', Start + 1); 5264 StringRef ExtraToken = Name.slice(Start, Next); 5265 5266 // Some NEON instructions have an optional datatype suffix that is 5267 // completely ignored. Check for that. 5268 if (isDataTypeToken(ExtraToken) && 5269 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5270 continue; 5271 5272 // For for ARM mode generate an error if the .n qualifier is used. 5273 if (ExtraToken == ".n" && !isThumb()) { 5274 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5275 Parser.eatToEndOfStatement(); 5276 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 5277 "arm mode"); 5278 } 5279 5280 // The .n qualifier is always discarded as that is what the tables 5281 // and matcher expect. In ARM mode the .w qualifier has no effect, 5282 // so discard it to avoid errors that can be caused by the matcher. 5283 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { 5284 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5285 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5286 } 5287 } 5288 5289 // Read the remaining operands. 5290 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5291 // Read the first operand. 5292 if (parseOperand(Operands, Mnemonic)) { 5293 Parser.eatToEndOfStatement(); 5294 return true; 5295 } 5296 5297 while (getLexer().is(AsmToken::Comma)) { 5298 Parser.Lex(); // Eat the comma. 5299 5300 // Parse and remember the operand. 5301 if (parseOperand(Operands, Mnemonic)) { 5302 Parser.eatToEndOfStatement(); 5303 return true; 5304 } 5305 } 5306 } 5307 5308 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5309 SMLoc Loc = getLexer().getLoc(); 5310 Parser.eatToEndOfStatement(); 5311 return Error(Loc, "unexpected token in argument list"); 5312 } 5313 5314 Parser.Lex(); // Consume the EndOfStatement 5315 5316 if (RequireVFPRegisterListCheck) { 5317 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back()); 5318 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList()) 5319 return Error(Op->getStartLoc(), 5320 "VFP/Neon single precision register expected"); 5321 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList()) 5322 return Error(Op->getStartLoc(), 5323 "VFP/Neon double precision register expected"); 5324 } 5325 5326 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5327 // do and don't have a cc_out optional-def operand. With some spot-checks 5328 // of the operand list, we can figure out which variant we're trying to 5329 // parse and adjust accordingly before actually matching. We shouldn't ever 5330 // try to remove a cc_out operand that was explicitly set on the the 5331 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5332 // table driven matcher doesn't fit well with the ARM instruction set. 5333 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5334 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5335 Operands.erase(Operands.begin() + 1); 5336 delete Op; 5337 } 5338 5339 // Some instructions have the same mnemonic, but don't always 5340 // have a predicate. Distinguish them here and delete the 5341 // predicate if needed. 5342 if (shouldOmitPredicateOperand(Mnemonic, Operands)) { 5343 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5344 Operands.erase(Operands.begin() + 1); 5345 delete Op; 5346 } 5347 5348 // ARM mode 'blx' need special handling, as the register operand version 5349 // is predicable, but the label operand version is not. So, we can't rely 5350 // on the Mnemonic based checking to correctly figure out when to put 5351 // a k_CondCode operand in the list. If we're trying to match the label 5352 // version, remove the k_CondCode operand here. 5353 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5354 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5355 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5356 Operands.erase(Operands.begin() + 1); 5357 delete Op; 5358 } 5359 5360 // Adjust operands of ldrexd/strexd to MCK_GPRPair. 5361 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 5362 // a single GPRPair reg operand is used in the .td file to replace the two 5363 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 5364 // expressed as a GPRPair, so we have to manually merge them. 5365 // FIXME: We would really like to be able to tablegen'erate this. 5366 if (!isThumb() && Operands.size() > 4 && 5367 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || 5368 Mnemonic == "stlexd")) { 5369 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); 5370 unsigned Idx = isLoad ? 2 : 3; 5371 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]); 5372 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]); 5373 5374 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 5375 // Adjust only if Op1 and Op2 are GPRs. 5376 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) && 5377 MRC.contains(Op2->getReg())) { 5378 unsigned Reg1 = Op1->getReg(); 5379 unsigned Reg2 = Op2->getReg(); 5380 unsigned Rt = MRI->getEncodingValue(Reg1); 5381 unsigned Rt2 = MRI->getEncodingValue(Reg2); 5382 5383 // Rt2 must be Rt + 1 and Rt must be even. 5384 if (Rt + 1 != Rt2 || (Rt & 1)) { 5385 Error(Op2->getStartLoc(), isLoad ? 5386 "destination operands must be sequential" : 5387 "source operands must be sequential"); 5388 return true; 5389 } 5390 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 5391 &(MRI->getRegClass(ARM::GPRPairRegClassID))); 5392 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2); 5393 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg( 5394 NewReg, Op1->getStartLoc(), Op2->getEndLoc())); 5395 delete Op1; 5396 delete Op2; 5397 } 5398 } 5399 5400 // GNU Assembler extension (compatibility) 5401 if ((Mnemonic == "ldrd" || Mnemonic == "strd") && !isThumb() && 5402 Operands.size() == 4) { 5403 ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]); 5404 assert(Op->isReg() && "expected register argument"); 5405 assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0, 5406 &MRI->getRegClass(ARM::GPRPairRegClassID)) 5407 && "expected register pair"); 5408 Operands.insert(Operands.begin() + 3, 5409 ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(), 5410 Op->getEndLoc())); 5411 } 5412 5413 // FIXME: As said above, this is all a pretty gross hack. This instruction 5414 // does not fit with other "subs" and tblgen. 5415 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction 5416 // so the Mnemonic is the original name "subs" and delete the predicate 5417 // operand so it will match the table entry. 5418 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && 5419 static_cast<ARMOperand*>(Operands[3])->isReg() && 5420 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC && 5421 static_cast<ARMOperand*>(Operands[4])->isReg() && 5422 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR && 5423 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5424 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]); 5425 Operands.erase(Operands.begin()); 5426 delete Op0; 5427 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc)); 5428 5429 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]); 5430 Operands.erase(Operands.begin() + 1); 5431 delete Op1; 5432 } 5433 return false; 5434 } 5435 5436 // Validate context-sensitive operand constraints. 5437 5438 // return 'true' if register list contains non-low GPR registers, 5439 // 'false' otherwise. If Reg is in the register list or is HiReg, set 5440 // 'containsReg' to true. 5441 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5442 unsigned HiReg, bool &containsReg) { 5443 containsReg = false; 5444 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5445 unsigned OpReg = Inst.getOperand(i).getReg(); 5446 if (OpReg == Reg) 5447 containsReg = true; 5448 // Anything other than a low register isn't legal here. 5449 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5450 return true; 5451 } 5452 return false; 5453 } 5454 5455 // Check if the specified regisgter is in the register list of the inst, 5456 // starting at the indicated operand number. 5457 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5458 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5459 unsigned OpReg = Inst.getOperand(i).getReg(); 5460 if (OpReg == Reg) 5461 return true; 5462 } 5463 return false; 5464 } 5465 5466 // Return true if instruction has the interesting property of being 5467 // allowed in IT blocks, but not being predicable. 5468 static bool instIsBreakpoint(const MCInst &Inst) { 5469 return Inst.getOpcode() == ARM::tBKPT || 5470 Inst.getOpcode() == ARM::BKPT || 5471 Inst.getOpcode() == ARM::tHLT || 5472 Inst.getOpcode() == ARM::HLT; 5473 5474 } 5475 5476 // FIXME: We would really like to be able to tablegen'erate this. 5477 bool ARMAsmParser:: 5478 validateInstruction(MCInst &Inst, 5479 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5480 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 5481 SMLoc Loc = Operands[0]->getStartLoc(); 5482 5483 // Check the IT block state first. 5484 // NOTE: BKPT and HLT instructions have the interesting property of being 5485 // allowed in IT blocks, but not being predicable. They just always execute. 5486 if (inITBlock() && !instIsBreakpoint(Inst)) { 5487 unsigned Bit = 1; 5488 if (ITState.FirstCond) 5489 ITState.FirstCond = false; 5490 else 5491 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5492 // The instruction must be predicable. 5493 if (!MCID.isPredicable()) 5494 return Error(Loc, "instructions in IT block must be predicable"); 5495 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5496 unsigned ITCond = Bit ? ITState.Cond : 5497 ARMCC::getOppositeCondition(ITState.Cond); 5498 if (Cond != ITCond) { 5499 // Find the condition code Operand to get its SMLoc information. 5500 SMLoc CondLoc; 5501 for (unsigned I = 1; I < Operands.size(); ++I) 5502 if (static_cast<ARMOperand*>(Operands[I])->isCondCode()) 5503 CondLoc = Operands[I]->getStartLoc(); 5504 return Error(CondLoc, "incorrect condition in IT block; got '" + 5505 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5506 "', but expected '" + 5507 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5508 } 5509 // Check for non-'al' condition codes outside of the IT block. 5510 } else if (isThumbTwo() && MCID.isPredicable() && 5511 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5512 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && 5513 Inst.getOpcode() != ARM::t2Bcc) 5514 return Error(Loc, "predicated instructions must be in IT block"); 5515 5516 const unsigned Opcode = Inst.getOpcode(); 5517 switch (Opcode) { 5518 case ARM::LDRD: 5519 case ARM::LDRD_PRE: 5520 case ARM::LDRD_POST: { 5521 const unsigned RtReg = Inst.getOperand(0).getReg(); 5522 5523 // Rt can't be R14. 5524 if (RtReg == ARM::LR) 5525 return Error(Operands[3]->getStartLoc(), 5526 "Rt can't be R14"); 5527 5528 const unsigned Rt = MRI->getEncodingValue(RtReg); 5529 // Rt must be even-numbered. 5530 if ((Rt & 1) == 1) 5531 return Error(Operands[3]->getStartLoc(), 5532 "Rt must be even-numbered"); 5533 5534 // Rt2 must be Rt + 1. 5535 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5536 if (Rt2 != Rt + 1) 5537 return Error(Operands[3]->getStartLoc(), 5538 "destination operands must be sequential"); 5539 5540 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) { 5541 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 5542 // For addressing modes with writeback, the base register needs to be 5543 // different from the destination registers. 5544 if (Rn == Rt || Rn == Rt2) 5545 return Error(Operands[3]->getStartLoc(), 5546 "base register needs to be different from destination " 5547 "registers"); 5548 } 5549 5550 return false; 5551 } 5552 case ARM::t2LDRDi8: 5553 case ARM::t2LDRD_PRE: 5554 case ARM::t2LDRD_POST: { 5555 // Rt2 must be different from Rt. 5556 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5557 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5558 if (Rt2 == Rt) 5559 return Error(Operands[3]->getStartLoc(), 5560 "destination operands can't be identical"); 5561 return false; 5562 } 5563 case ARM::STRD: { 5564 // Rt2 must be Rt + 1. 5565 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5566 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5567 if (Rt2 != Rt + 1) 5568 return Error(Operands[3]->getStartLoc(), 5569 "source operands must be sequential"); 5570 return false; 5571 } 5572 case ARM::STRD_PRE: 5573 case ARM::STRD_POST: { 5574 // Rt2 must be Rt + 1. 5575 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5576 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5577 if (Rt2 != Rt + 1) 5578 return Error(Operands[3]->getStartLoc(), 5579 "source operands must be sequential"); 5580 return false; 5581 } 5582 case ARM::SBFX: 5583 case ARM::UBFX: { 5584 // Width must be in range [1, 32-lsb]. 5585 unsigned LSB = Inst.getOperand(2).getImm(); 5586 unsigned Widthm1 = Inst.getOperand(3).getImm(); 5587 if (Widthm1 >= 32 - LSB) 5588 return Error(Operands[5]->getStartLoc(), 5589 "bitfield width must be in range [1,32-lsb]"); 5590 return false; 5591 } 5592 // Notionally handles ARM::tLDMIA_UPD too. 5593 case ARM::tLDMIA: { 5594 // If we're parsing Thumb2, the .w variant is available and handles 5595 // most cases that are normally illegal for a Thumb1 LDM instruction. 5596 // We'll make the transformation in processInstruction() if necessary. 5597 // 5598 // Thumb LDM instructions are writeback iff the base register is not 5599 // in the register list. 5600 unsigned Rn = Inst.getOperand(0).getReg(); 5601 bool HasWritebackToken = 5602 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5603 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5604 bool ListContainsBase; 5605 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo()) 5606 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), 5607 "registers must be in range r0-r7"); 5608 // If we should have writeback, then there should be a '!' token. 5609 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo()) 5610 return Error(Operands[2]->getStartLoc(), 5611 "writeback operator '!' expected"); 5612 // If we should not have writeback, there must not be a '!'. This is 5613 // true even for the 32-bit wide encodings. 5614 if (ListContainsBase && HasWritebackToken) 5615 return Error(Operands[3]->getStartLoc(), 5616 "writeback operator '!' not allowed when base register " 5617 "in register list"); 5618 5619 break; 5620 } 5621 case ARM::LDMIA_UPD: 5622 case ARM::LDMDB_UPD: 5623 case ARM::LDMIB_UPD: 5624 case ARM::LDMDA_UPD: 5625 // ARM variants loading and updating the same register are only officially 5626 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before. 5627 if (!hasV7Ops()) 5628 break; 5629 // Fallthrough 5630 case ARM::t2LDMIA_UPD: 5631 case ARM::t2LDMDB_UPD: 5632 case ARM::t2STMIA_UPD: 5633 case ARM::t2STMDB_UPD: { 5634 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5635 return Error(Operands.back()->getStartLoc(), 5636 "writeback register not allowed in register list"); 5637 break; 5638 } 5639 case ARM::sysLDMIA_UPD: 5640 case ARM::sysLDMDA_UPD: 5641 case ARM::sysLDMDB_UPD: 5642 case ARM::sysLDMIB_UPD: 5643 if (!listContainsReg(Inst, 3, ARM::PC)) 5644 return Error(Operands[4]->getStartLoc(), 5645 "writeback register only allowed on system LDM " 5646 "if PC in register-list"); 5647 break; 5648 case ARM::sysSTMIA_UPD: 5649 case ARM::sysSTMDA_UPD: 5650 case ARM::sysSTMDB_UPD: 5651 case ARM::sysSTMIB_UPD: 5652 return Error(Operands[2]->getStartLoc(), 5653 "system STM cannot have writeback register"); 5654 break; 5655 case ARM::tMUL: { 5656 // The second source operand must be the same register as the destination 5657 // operand. 5658 // 5659 // In this case, we must directly check the parsed operands because the 5660 // cvtThumbMultiply() function is written in such a way that it guarantees 5661 // this first statement is always true for the new Inst. Essentially, the 5662 // destination is unconditionally copied into the second source operand 5663 // without checking to see if it matches what we actually parsed. 5664 if (Operands.size() == 6 && 5665 (((ARMOperand*)Operands[3])->getReg() != 5666 ((ARMOperand*)Operands[5])->getReg()) && 5667 (((ARMOperand*)Operands[3])->getReg() != 5668 ((ARMOperand*)Operands[4])->getReg())) { 5669 return Error(Operands[3]->getStartLoc(), 5670 "destination register must match source register"); 5671 } 5672 break; 5673 } 5674 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5675 // so only issue a diagnostic for thumb1. The instructions will be 5676 // switched to the t2 encodings in processInstruction() if necessary. 5677 case ARM::tPOP: { 5678 bool ListContainsBase; 5679 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && 5680 !isThumbTwo()) 5681 return Error(Operands[2]->getStartLoc(), 5682 "registers must be in range r0-r7 or pc"); 5683 break; 5684 } 5685 case ARM::tPUSH: { 5686 bool ListContainsBase; 5687 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && 5688 !isThumbTwo()) 5689 return Error(Operands[2]->getStartLoc(), 5690 "registers must be in range r0-r7 or lr"); 5691 break; 5692 } 5693 case ARM::tSTMIA_UPD: { 5694 bool ListContainsBase, InvalidLowList; 5695 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), 5696 0, ListContainsBase); 5697 if (InvalidLowList && !isThumbTwo()) 5698 return Error(Operands[4]->getStartLoc(), 5699 "registers must be in range r0-r7"); 5700 5701 // This would be converted to a 32-bit stm, but that's not valid if the 5702 // writeback register is in the list. 5703 if (InvalidLowList && ListContainsBase) 5704 return Error(Operands[4]->getStartLoc(), 5705 "writeback operator '!' not allowed when base register " 5706 "in register list"); 5707 break; 5708 } 5709 case ARM::tADDrSP: { 5710 // If the non-SP source operand and the destination operand are not the 5711 // same, we need thumb2 (for the wide encoding), or we have an error. 5712 if (!isThumbTwo() && 5713 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5714 return Error(Operands[4]->getStartLoc(), 5715 "source register must be the same as destination"); 5716 } 5717 break; 5718 } 5719 // Final range checking for Thumb unconditional branch instructions. 5720 case ARM::tB: 5721 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>()) 5722 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 5723 break; 5724 case ARM::t2B: { 5725 int op = (Operands[2]->isImm()) ? 2 : 3; 5726 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>()) 5727 return Error(Operands[op]->getStartLoc(), "branch target out of range"); 5728 break; 5729 } 5730 // Final range checking for Thumb conditional branch instructions. 5731 case ARM::tBcc: 5732 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>()) 5733 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 5734 break; 5735 case ARM::t2Bcc: { 5736 int Op = (Operands[2]->isImm()) ? 2 : 3; 5737 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>()) 5738 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); 5739 break; 5740 } 5741 } 5742 5743 return false; 5744 } 5745 5746 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5747 switch(Opc) { 5748 default: llvm_unreachable("unexpected opcode!"); 5749 // VST1LN 5750 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5751 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5752 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5753 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5754 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5755 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5756 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5757 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5758 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5759 5760 // VST2LN 5761 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5762 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5763 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5764 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5765 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5766 5767 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5768 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5769 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5770 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5771 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5772 5773 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5774 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5775 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5776 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5777 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5778 5779 // VST3LN 5780 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5781 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5782 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5783 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5784 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5785 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5786 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5787 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5788 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5789 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5790 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5791 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5792 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5793 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5794 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5795 5796 // VST3 5797 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5798 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5799 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5800 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5801 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5802 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5803 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5804 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5805 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5806 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5807 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5808 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5809 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5810 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5811 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5812 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5813 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5814 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5815 5816 // VST4LN 5817 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5818 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5819 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5820 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5821 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5822 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5823 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5824 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5825 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5826 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5827 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5828 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5829 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5830 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5831 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5832 5833 // VST4 5834 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5835 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5836 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5837 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5838 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5839 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5840 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5841 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5842 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5843 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5844 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5845 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5846 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5847 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5848 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5849 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5850 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5851 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5852 } 5853 } 5854 5855 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5856 switch(Opc) { 5857 default: llvm_unreachable("unexpected opcode!"); 5858 // VLD1LN 5859 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5860 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5861 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5862 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5863 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5864 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5865 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5866 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5867 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5868 5869 // VLD2LN 5870 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5871 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5872 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5873 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5874 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5875 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5876 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5877 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5878 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5879 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5880 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5881 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5882 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5883 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5884 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5885 5886 // VLD3DUP 5887 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5888 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5889 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5890 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5891 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5892 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5893 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5894 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5895 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5896 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5897 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5898 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5899 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5900 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5901 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5902 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5903 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5904 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5905 5906 // VLD3LN 5907 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5908 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5909 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5910 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5911 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5912 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5913 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5914 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5915 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5916 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5917 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5918 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5919 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5920 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5921 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5922 5923 // VLD3 5924 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5925 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5926 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5927 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5928 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5929 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5930 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5931 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5932 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5933 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5934 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5935 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5936 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5937 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5938 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5939 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5940 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5941 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5942 5943 // VLD4LN 5944 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5945 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5946 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5947 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5948 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5949 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5950 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5951 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5952 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5953 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5954 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5955 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5956 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5957 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5958 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5959 5960 // VLD4DUP 5961 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5962 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5963 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5964 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5965 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5966 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5967 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5968 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5969 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5970 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5971 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5972 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5973 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5974 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5975 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5976 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5977 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5978 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5979 5980 // VLD4 5981 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5982 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5983 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5984 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5985 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5986 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5987 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5988 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5989 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5990 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5991 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5992 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5993 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 5994 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 5995 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 5996 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 5997 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 5998 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 5999 } 6000 } 6001 6002 bool ARMAsmParser:: 6003 processInstruction(MCInst &Inst, 6004 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 6005 switch (Inst.getOpcode()) { 6006 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction. 6007 case ARM::LDRT_POST: 6008 case ARM::LDRBT_POST: { 6009 const unsigned Opcode = 6010 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM 6011 : ARM::LDRBT_POST_IMM; 6012 MCInst TmpInst; 6013 TmpInst.setOpcode(Opcode); 6014 TmpInst.addOperand(Inst.getOperand(0)); 6015 TmpInst.addOperand(Inst.getOperand(1)); 6016 TmpInst.addOperand(Inst.getOperand(1)); 6017 TmpInst.addOperand(MCOperand::CreateReg(0)); 6018 TmpInst.addOperand(MCOperand::CreateImm(0)); 6019 TmpInst.addOperand(Inst.getOperand(2)); 6020 TmpInst.addOperand(Inst.getOperand(3)); 6021 Inst = TmpInst; 6022 return true; 6023 } 6024 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction. 6025 case ARM::STRT_POST: 6026 case ARM::STRBT_POST: { 6027 const unsigned Opcode = 6028 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM 6029 : ARM::STRBT_POST_IMM; 6030 MCInst TmpInst; 6031 TmpInst.setOpcode(Opcode); 6032 TmpInst.addOperand(Inst.getOperand(1)); 6033 TmpInst.addOperand(Inst.getOperand(0)); 6034 TmpInst.addOperand(Inst.getOperand(1)); 6035 TmpInst.addOperand(MCOperand::CreateReg(0)); 6036 TmpInst.addOperand(MCOperand::CreateImm(0)); 6037 TmpInst.addOperand(Inst.getOperand(2)); 6038 TmpInst.addOperand(Inst.getOperand(3)); 6039 Inst = TmpInst; 6040 return true; 6041 } 6042 // Alias for alternate form of 'ADR Rd, #imm' instruction. 6043 case ARM::ADDri: { 6044 if (Inst.getOperand(1).getReg() != ARM::PC || 6045 Inst.getOperand(5).getReg() != 0) 6046 return false; 6047 MCInst TmpInst; 6048 TmpInst.setOpcode(ARM::ADR); 6049 TmpInst.addOperand(Inst.getOperand(0)); 6050 TmpInst.addOperand(Inst.getOperand(2)); 6051 TmpInst.addOperand(Inst.getOperand(3)); 6052 TmpInst.addOperand(Inst.getOperand(4)); 6053 Inst = TmpInst; 6054 return true; 6055 } 6056 // Aliases for alternate PC+imm syntax of LDR instructions. 6057 case ARM::t2LDRpcrel: 6058 // Select the narrow version if the immediate will fit. 6059 if (Inst.getOperand(1).getImm() > 0 && 6060 Inst.getOperand(1).getImm() <= 0xff && 6061 !(static_cast<ARMOperand*>(Operands[2])->isToken() && 6062 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w")) 6063 Inst.setOpcode(ARM::tLDRpci); 6064 else 6065 Inst.setOpcode(ARM::t2LDRpci); 6066 return true; 6067 case ARM::t2LDRBpcrel: 6068 Inst.setOpcode(ARM::t2LDRBpci); 6069 return true; 6070 case ARM::t2LDRHpcrel: 6071 Inst.setOpcode(ARM::t2LDRHpci); 6072 return true; 6073 case ARM::t2LDRSBpcrel: 6074 Inst.setOpcode(ARM::t2LDRSBpci); 6075 return true; 6076 case ARM::t2LDRSHpcrel: 6077 Inst.setOpcode(ARM::t2LDRSHpci); 6078 return true; 6079 // Handle NEON VST complex aliases. 6080 case ARM::VST1LNdWB_register_Asm_8: 6081 case ARM::VST1LNdWB_register_Asm_16: 6082 case ARM::VST1LNdWB_register_Asm_32: { 6083 MCInst TmpInst; 6084 // Shuffle the operands around so the lane index operand is in the 6085 // right place. 6086 unsigned Spacing; 6087 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6088 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6089 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6090 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6091 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6092 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6093 TmpInst.addOperand(Inst.getOperand(1)); // lane 6094 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6095 TmpInst.addOperand(Inst.getOperand(6)); 6096 Inst = TmpInst; 6097 return true; 6098 } 6099 6100 case ARM::VST2LNdWB_register_Asm_8: 6101 case ARM::VST2LNdWB_register_Asm_16: 6102 case ARM::VST2LNdWB_register_Asm_32: 6103 case ARM::VST2LNqWB_register_Asm_16: 6104 case ARM::VST2LNqWB_register_Asm_32: { 6105 MCInst TmpInst; 6106 // Shuffle the operands around so the lane index operand is in the 6107 // right place. 6108 unsigned Spacing; 6109 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6110 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6111 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6112 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6113 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6114 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6115 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6116 Spacing)); 6117 TmpInst.addOperand(Inst.getOperand(1)); // lane 6118 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6119 TmpInst.addOperand(Inst.getOperand(6)); 6120 Inst = TmpInst; 6121 return true; 6122 } 6123 6124 case ARM::VST3LNdWB_register_Asm_8: 6125 case ARM::VST3LNdWB_register_Asm_16: 6126 case ARM::VST3LNdWB_register_Asm_32: 6127 case ARM::VST3LNqWB_register_Asm_16: 6128 case ARM::VST3LNqWB_register_Asm_32: { 6129 MCInst TmpInst; 6130 // Shuffle the operands around so the lane index operand is in the 6131 // right place. 6132 unsigned Spacing; 6133 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6134 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6135 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6136 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6137 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6138 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6139 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6140 Spacing)); 6141 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6142 Spacing * 2)); 6143 TmpInst.addOperand(Inst.getOperand(1)); // lane 6144 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6145 TmpInst.addOperand(Inst.getOperand(6)); 6146 Inst = TmpInst; 6147 return true; 6148 } 6149 6150 case ARM::VST4LNdWB_register_Asm_8: 6151 case ARM::VST4LNdWB_register_Asm_16: 6152 case ARM::VST4LNdWB_register_Asm_32: 6153 case ARM::VST4LNqWB_register_Asm_16: 6154 case ARM::VST4LNqWB_register_Asm_32: { 6155 MCInst TmpInst; 6156 // Shuffle the operands around so the lane index operand is in the 6157 // right place. 6158 unsigned Spacing; 6159 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6160 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6161 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6162 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6163 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6164 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6165 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6166 Spacing)); 6167 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6168 Spacing * 2)); 6169 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6170 Spacing * 3)); 6171 TmpInst.addOperand(Inst.getOperand(1)); // lane 6172 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6173 TmpInst.addOperand(Inst.getOperand(6)); 6174 Inst = TmpInst; 6175 return true; 6176 } 6177 6178 case ARM::VST1LNdWB_fixed_Asm_8: 6179 case ARM::VST1LNdWB_fixed_Asm_16: 6180 case ARM::VST1LNdWB_fixed_Asm_32: { 6181 MCInst TmpInst; 6182 // Shuffle the operands around so the lane index operand is in the 6183 // right place. 6184 unsigned Spacing; 6185 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6186 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6187 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6188 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6189 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6190 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6191 TmpInst.addOperand(Inst.getOperand(1)); // lane 6192 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6193 TmpInst.addOperand(Inst.getOperand(5)); 6194 Inst = TmpInst; 6195 return true; 6196 } 6197 6198 case ARM::VST2LNdWB_fixed_Asm_8: 6199 case ARM::VST2LNdWB_fixed_Asm_16: 6200 case ARM::VST2LNdWB_fixed_Asm_32: 6201 case ARM::VST2LNqWB_fixed_Asm_16: 6202 case ARM::VST2LNqWB_fixed_Asm_32: { 6203 MCInst TmpInst; 6204 // Shuffle the operands around so the lane index operand is in the 6205 // right place. 6206 unsigned Spacing; 6207 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6208 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6209 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6210 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6211 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6212 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6213 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6214 Spacing)); 6215 TmpInst.addOperand(Inst.getOperand(1)); // lane 6216 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6217 TmpInst.addOperand(Inst.getOperand(5)); 6218 Inst = TmpInst; 6219 return true; 6220 } 6221 6222 case ARM::VST3LNdWB_fixed_Asm_8: 6223 case ARM::VST3LNdWB_fixed_Asm_16: 6224 case ARM::VST3LNdWB_fixed_Asm_32: 6225 case ARM::VST3LNqWB_fixed_Asm_16: 6226 case ARM::VST3LNqWB_fixed_Asm_32: { 6227 MCInst TmpInst; 6228 // Shuffle the operands around so the lane index operand is in the 6229 // right place. 6230 unsigned Spacing; 6231 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6232 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6233 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6234 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6235 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6236 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6237 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6238 Spacing)); 6239 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6240 Spacing * 2)); 6241 TmpInst.addOperand(Inst.getOperand(1)); // lane 6242 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6243 TmpInst.addOperand(Inst.getOperand(5)); 6244 Inst = TmpInst; 6245 return true; 6246 } 6247 6248 case ARM::VST4LNdWB_fixed_Asm_8: 6249 case ARM::VST4LNdWB_fixed_Asm_16: 6250 case ARM::VST4LNdWB_fixed_Asm_32: 6251 case ARM::VST4LNqWB_fixed_Asm_16: 6252 case ARM::VST4LNqWB_fixed_Asm_32: { 6253 MCInst TmpInst; 6254 // Shuffle the operands around so the lane index operand is in the 6255 // right place. 6256 unsigned Spacing; 6257 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6258 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6259 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6260 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6261 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6262 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6263 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6264 Spacing)); 6265 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6266 Spacing * 2)); 6267 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6268 Spacing * 3)); 6269 TmpInst.addOperand(Inst.getOperand(1)); // lane 6270 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6271 TmpInst.addOperand(Inst.getOperand(5)); 6272 Inst = TmpInst; 6273 return true; 6274 } 6275 6276 case ARM::VST1LNdAsm_8: 6277 case ARM::VST1LNdAsm_16: 6278 case ARM::VST1LNdAsm_32: { 6279 MCInst TmpInst; 6280 // Shuffle the operands around so the lane index operand is in the 6281 // right place. 6282 unsigned Spacing; 6283 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6284 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6285 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6286 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6287 TmpInst.addOperand(Inst.getOperand(1)); // lane 6288 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6289 TmpInst.addOperand(Inst.getOperand(5)); 6290 Inst = TmpInst; 6291 return true; 6292 } 6293 6294 case ARM::VST2LNdAsm_8: 6295 case ARM::VST2LNdAsm_16: 6296 case ARM::VST2LNdAsm_32: 6297 case ARM::VST2LNqAsm_16: 6298 case ARM::VST2LNqAsm_32: { 6299 MCInst TmpInst; 6300 // Shuffle the operands around so the lane index operand is in the 6301 // right place. 6302 unsigned Spacing; 6303 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6304 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6305 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6306 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6307 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6308 Spacing)); 6309 TmpInst.addOperand(Inst.getOperand(1)); // lane 6310 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6311 TmpInst.addOperand(Inst.getOperand(5)); 6312 Inst = TmpInst; 6313 return true; 6314 } 6315 6316 case ARM::VST3LNdAsm_8: 6317 case ARM::VST3LNdAsm_16: 6318 case ARM::VST3LNdAsm_32: 6319 case ARM::VST3LNqAsm_16: 6320 case ARM::VST3LNqAsm_32: { 6321 MCInst TmpInst; 6322 // Shuffle the operands around so the lane index operand is in the 6323 // right place. 6324 unsigned Spacing; 6325 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6326 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6327 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6328 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6329 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6330 Spacing)); 6331 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6332 Spacing * 2)); 6333 TmpInst.addOperand(Inst.getOperand(1)); // lane 6334 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6335 TmpInst.addOperand(Inst.getOperand(5)); 6336 Inst = TmpInst; 6337 return true; 6338 } 6339 6340 case ARM::VST4LNdAsm_8: 6341 case ARM::VST4LNdAsm_16: 6342 case ARM::VST4LNdAsm_32: 6343 case ARM::VST4LNqAsm_16: 6344 case ARM::VST4LNqAsm_32: { 6345 MCInst TmpInst; 6346 // Shuffle the operands around so the lane index operand is in the 6347 // right place. 6348 unsigned Spacing; 6349 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6350 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6351 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6352 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6353 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6354 Spacing)); 6355 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6356 Spacing * 2)); 6357 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6358 Spacing * 3)); 6359 TmpInst.addOperand(Inst.getOperand(1)); // lane 6360 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6361 TmpInst.addOperand(Inst.getOperand(5)); 6362 Inst = TmpInst; 6363 return true; 6364 } 6365 6366 // Handle NEON VLD complex aliases. 6367 case ARM::VLD1LNdWB_register_Asm_8: 6368 case ARM::VLD1LNdWB_register_Asm_16: 6369 case ARM::VLD1LNdWB_register_Asm_32: { 6370 MCInst TmpInst; 6371 // Shuffle the operands around so the lane index operand is in the 6372 // right place. 6373 unsigned Spacing; 6374 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6375 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6376 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6377 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6378 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6379 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6380 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6381 TmpInst.addOperand(Inst.getOperand(1)); // lane 6382 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6383 TmpInst.addOperand(Inst.getOperand(6)); 6384 Inst = TmpInst; 6385 return true; 6386 } 6387 6388 case ARM::VLD2LNdWB_register_Asm_8: 6389 case ARM::VLD2LNdWB_register_Asm_16: 6390 case ARM::VLD2LNdWB_register_Asm_32: 6391 case ARM::VLD2LNqWB_register_Asm_16: 6392 case ARM::VLD2LNqWB_register_Asm_32: { 6393 MCInst TmpInst; 6394 // Shuffle the operands around so the lane index operand is in the 6395 // right place. 6396 unsigned Spacing; 6397 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6398 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6399 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6400 Spacing)); 6401 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6402 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6403 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6404 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6405 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6406 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6407 Spacing)); 6408 TmpInst.addOperand(Inst.getOperand(1)); // lane 6409 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6410 TmpInst.addOperand(Inst.getOperand(6)); 6411 Inst = TmpInst; 6412 return true; 6413 } 6414 6415 case ARM::VLD3LNdWB_register_Asm_8: 6416 case ARM::VLD3LNdWB_register_Asm_16: 6417 case ARM::VLD3LNdWB_register_Asm_32: 6418 case ARM::VLD3LNqWB_register_Asm_16: 6419 case ARM::VLD3LNqWB_register_Asm_32: { 6420 MCInst TmpInst; 6421 // Shuffle the operands around so the lane index operand is in the 6422 // right place. 6423 unsigned Spacing; 6424 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6425 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6426 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6427 Spacing)); 6428 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6429 Spacing * 2)); 6430 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6431 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6432 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6433 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6434 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6435 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6436 Spacing)); 6437 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6438 Spacing * 2)); 6439 TmpInst.addOperand(Inst.getOperand(1)); // lane 6440 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6441 TmpInst.addOperand(Inst.getOperand(6)); 6442 Inst = TmpInst; 6443 return true; 6444 } 6445 6446 case ARM::VLD4LNdWB_register_Asm_8: 6447 case ARM::VLD4LNdWB_register_Asm_16: 6448 case ARM::VLD4LNdWB_register_Asm_32: 6449 case ARM::VLD4LNqWB_register_Asm_16: 6450 case ARM::VLD4LNqWB_register_Asm_32: { 6451 MCInst TmpInst; 6452 // Shuffle the operands around so the lane index operand is in the 6453 // right place. 6454 unsigned Spacing; 6455 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6456 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6457 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6458 Spacing)); 6459 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6460 Spacing * 2)); 6461 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6462 Spacing * 3)); 6463 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6464 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6465 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6466 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6467 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6468 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6469 Spacing)); 6470 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6471 Spacing * 2)); 6472 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6473 Spacing * 3)); 6474 TmpInst.addOperand(Inst.getOperand(1)); // lane 6475 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6476 TmpInst.addOperand(Inst.getOperand(6)); 6477 Inst = TmpInst; 6478 return true; 6479 } 6480 6481 case ARM::VLD1LNdWB_fixed_Asm_8: 6482 case ARM::VLD1LNdWB_fixed_Asm_16: 6483 case ARM::VLD1LNdWB_fixed_Asm_32: { 6484 MCInst TmpInst; 6485 // Shuffle the operands around so the lane index operand is in the 6486 // right place. 6487 unsigned Spacing; 6488 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6489 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6490 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6491 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6492 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6493 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6494 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6495 TmpInst.addOperand(Inst.getOperand(1)); // lane 6496 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6497 TmpInst.addOperand(Inst.getOperand(5)); 6498 Inst = TmpInst; 6499 return true; 6500 } 6501 6502 case ARM::VLD2LNdWB_fixed_Asm_8: 6503 case ARM::VLD2LNdWB_fixed_Asm_16: 6504 case ARM::VLD2LNdWB_fixed_Asm_32: 6505 case ARM::VLD2LNqWB_fixed_Asm_16: 6506 case ARM::VLD2LNqWB_fixed_Asm_32: { 6507 MCInst TmpInst; 6508 // Shuffle the operands around so the lane index operand is in the 6509 // right place. 6510 unsigned Spacing; 6511 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6512 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6513 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6514 Spacing)); 6515 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6516 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6517 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6518 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6519 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6520 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6521 Spacing)); 6522 TmpInst.addOperand(Inst.getOperand(1)); // lane 6523 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6524 TmpInst.addOperand(Inst.getOperand(5)); 6525 Inst = TmpInst; 6526 return true; 6527 } 6528 6529 case ARM::VLD3LNdWB_fixed_Asm_8: 6530 case ARM::VLD3LNdWB_fixed_Asm_16: 6531 case ARM::VLD3LNdWB_fixed_Asm_32: 6532 case ARM::VLD3LNqWB_fixed_Asm_16: 6533 case ARM::VLD3LNqWB_fixed_Asm_32: { 6534 MCInst TmpInst; 6535 // Shuffle the operands around so the lane index operand is in the 6536 // right place. 6537 unsigned Spacing; 6538 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6539 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6540 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6541 Spacing)); 6542 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6543 Spacing * 2)); 6544 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6545 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6546 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6547 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6548 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6549 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6550 Spacing)); 6551 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6552 Spacing * 2)); 6553 TmpInst.addOperand(Inst.getOperand(1)); // lane 6554 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6555 TmpInst.addOperand(Inst.getOperand(5)); 6556 Inst = TmpInst; 6557 return true; 6558 } 6559 6560 case ARM::VLD4LNdWB_fixed_Asm_8: 6561 case ARM::VLD4LNdWB_fixed_Asm_16: 6562 case ARM::VLD4LNdWB_fixed_Asm_32: 6563 case ARM::VLD4LNqWB_fixed_Asm_16: 6564 case ARM::VLD4LNqWB_fixed_Asm_32: { 6565 MCInst TmpInst; 6566 // Shuffle the operands around so the lane index operand is in the 6567 // right place. 6568 unsigned Spacing; 6569 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6570 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6571 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6572 Spacing)); 6573 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6574 Spacing * 2)); 6575 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6576 Spacing * 3)); 6577 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6578 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6579 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6580 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6581 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6582 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6583 Spacing)); 6584 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6585 Spacing * 2)); 6586 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6587 Spacing * 3)); 6588 TmpInst.addOperand(Inst.getOperand(1)); // lane 6589 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6590 TmpInst.addOperand(Inst.getOperand(5)); 6591 Inst = TmpInst; 6592 return true; 6593 } 6594 6595 case ARM::VLD1LNdAsm_8: 6596 case ARM::VLD1LNdAsm_16: 6597 case ARM::VLD1LNdAsm_32: { 6598 MCInst TmpInst; 6599 // Shuffle the operands around so the lane index operand is in the 6600 // right place. 6601 unsigned Spacing; 6602 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6603 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6604 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6605 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6606 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6607 TmpInst.addOperand(Inst.getOperand(1)); // lane 6608 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6609 TmpInst.addOperand(Inst.getOperand(5)); 6610 Inst = TmpInst; 6611 return true; 6612 } 6613 6614 case ARM::VLD2LNdAsm_8: 6615 case ARM::VLD2LNdAsm_16: 6616 case ARM::VLD2LNdAsm_32: 6617 case ARM::VLD2LNqAsm_16: 6618 case ARM::VLD2LNqAsm_32: { 6619 MCInst TmpInst; 6620 // Shuffle the operands around so the lane index operand is in the 6621 // right place. 6622 unsigned Spacing; 6623 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6624 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6625 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6626 Spacing)); 6627 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6628 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6629 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6630 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6631 Spacing)); 6632 TmpInst.addOperand(Inst.getOperand(1)); // lane 6633 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6634 TmpInst.addOperand(Inst.getOperand(5)); 6635 Inst = TmpInst; 6636 return true; 6637 } 6638 6639 case ARM::VLD3LNdAsm_8: 6640 case ARM::VLD3LNdAsm_16: 6641 case ARM::VLD3LNdAsm_32: 6642 case ARM::VLD3LNqAsm_16: 6643 case ARM::VLD3LNqAsm_32: { 6644 MCInst TmpInst; 6645 // Shuffle the operands around so the lane index operand is in the 6646 // right place. 6647 unsigned Spacing; 6648 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6649 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6650 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6651 Spacing)); 6652 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6653 Spacing * 2)); 6654 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6655 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6656 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6657 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6658 Spacing)); 6659 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6660 Spacing * 2)); 6661 TmpInst.addOperand(Inst.getOperand(1)); // lane 6662 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6663 TmpInst.addOperand(Inst.getOperand(5)); 6664 Inst = TmpInst; 6665 return true; 6666 } 6667 6668 case ARM::VLD4LNdAsm_8: 6669 case ARM::VLD4LNdAsm_16: 6670 case ARM::VLD4LNdAsm_32: 6671 case ARM::VLD4LNqAsm_16: 6672 case ARM::VLD4LNqAsm_32: { 6673 MCInst TmpInst; 6674 // Shuffle the operands around so the lane index operand is in the 6675 // right place. 6676 unsigned Spacing; 6677 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6678 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6679 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6680 Spacing)); 6681 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6682 Spacing * 2)); 6683 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6684 Spacing * 3)); 6685 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6686 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6687 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6688 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6689 Spacing)); 6690 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6691 Spacing * 2)); 6692 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6693 Spacing * 3)); 6694 TmpInst.addOperand(Inst.getOperand(1)); // lane 6695 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6696 TmpInst.addOperand(Inst.getOperand(5)); 6697 Inst = TmpInst; 6698 return true; 6699 } 6700 6701 // VLD3DUP single 3-element structure to all lanes instructions. 6702 case ARM::VLD3DUPdAsm_8: 6703 case ARM::VLD3DUPdAsm_16: 6704 case ARM::VLD3DUPdAsm_32: 6705 case ARM::VLD3DUPqAsm_8: 6706 case ARM::VLD3DUPqAsm_16: 6707 case ARM::VLD3DUPqAsm_32: { 6708 MCInst TmpInst; 6709 unsigned Spacing; 6710 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6711 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6712 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6713 Spacing)); 6714 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6715 Spacing * 2)); 6716 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6717 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6718 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6719 TmpInst.addOperand(Inst.getOperand(4)); 6720 Inst = TmpInst; 6721 return true; 6722 } 6723 6724 case ARM::VLD3DUPdWB_fixed_Asm_8: 6725 case ARM::VLD3DUPdWB_fixed_Asm_16: 6726 case ARM::VLD3DUPdWB_fixed_Asm_32: 6727 case ARM::VLD3DUPqWB_fixed_Asm_8: 6728 case ARM::VLD3DUPqWB_fixed_Asm_16: 6729 case ARM::VLD3DUPqWB_fixed_Asm_32: { 6730 MCInst TmpInst; 6731 unsigned Spacing; 6732 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6733 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6734 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6735 Spacing)); 6736 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6737 Spacing * 2)); 6738 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6739 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6740 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6741 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6742 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6743 TmpInst.addOperand(Inst.getOperand(4)); 6744 Inst = TmpInst; 6745 return true; 6746 } 6747 6748 case ARM::VLD3DUPdWB_register_Asm_8: 6749 case ARM::VLD3DUPdWB_register_Asm_16: 6750 case ARM::VLD3DUPdWB_register_Asm_32: 6751 case ARM::VLD3DUPqWB_register_Asm_8: 6752 case ARM::VLD3DUPqWB_register_Asm_16: 6753 case ARM::VLD3DUPqWB_register_Asm_32: { 6754 MCInst TmpInst; 6755 unsigned Spacing; 6756 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6757 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6758 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6759 Spacing)); 6760 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6761 Spacing * 2)); 6762 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6763 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6764 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6765 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6766 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6767 TmpInst.addOperand(Inst.getOperand(5)); 6768 Inst = TmpInst; 6769 return true; 6770 } 6771 6772 // VLD3 multiple 3-element structure instructions. 6773 case ARM::VLD3dAsm_8: 6774 case ARM::VLD3dAsm_16: 6775 case ARM::VLD3dAsm_32: 6776 case ARM::VLD3qAsm_8: 6777 case ARM::VLD3qAsm_16: 6778 case ARM::VLD3qAsm_32: { 6779 MCInst TmpInst; 6780 unsigned Spacing; 6781 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6782 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6783 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6784 Spacing)); 6785 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6786 Spacing * 2)); 6787 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6788 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6789 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6790 TmpInst.addOperand(Inst.getOperand(4)); 6791 Inst = TmpInst; 6792 return true; 6793 } 6794 6795 case ARM::VLD3dWB_fixed_Asm_8: 6796 case ARM::VLD3dWB_fixed_Asm_16: 6797 case ARM::VLD3dWB_fixed_Asm_32: 6798 case ARM::VLD3qWB_fixed_Asm_8: 6799 case ARM::VLD3qWB_fixed_Asm_16: 6800 case ARM::VLD3qWB_fixed_Asm_32: { 6801 MCInst TmpInst; 6802 unsigned Spacing; 6803 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6804 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6805 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6806 Spacing)); 6807 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6808 Spacing * 2)); 6809 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6810 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6811 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6812 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6813 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6814 TmpInst.addOperand(Inst.getOperand(4)); 6815 Inst = TmpInst; 6816 return true; 6817 } 6818 6819 case ARM::VLD3dWB_register_Asm_8: 6820 case ARM::VLD3dWB_register_Asm_16: 6821 case ARM::VLD3dWB_register_Asm_32: 6822 case ARM::VLD3qWB_register_Asm_8: 6823 case ARM::VLD3qWB_register_Asm_16: 6824 case ARM::VLD3qWB_register_Asm_32: { 6825 MCInst TmpInst; 6826 unsigned Spacing; 6827 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6828 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6829 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6830 Spacing)); 6831 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6832 Spacing * 2)); 6833 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6834 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6835 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6836 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6837 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6838 TmpInst.addOperand(Inst.getOperand(5)); 6839 Inst = TmpInst; 6840 return true; 6841 } 6842 6843 // VLD4DUP single 3-element structure to all lanes instructions. 6844 case ARM::VLD4DUPdAsm_8: 6845 case ARM::VLD4DUPdAsm_16: 6846 case ARM::VLD4DUPdAsm_32: 6847 case ARM::VLD4DUPqAsm_8: 6848 case ARM::VLD4DUPqAsm_16: 6849 case ARM::VLD4DUPqAsm_32: { 6850 MCInst TmpInst; 6851 unsigned Spacing; 6852 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6853 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6854 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6855 Spacing)); 6856 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6857 Spacing * 2)); 6858 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6859 Spacing * 3)); 6860 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6861 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6862 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6863 TmpInst.addOperand(Inst.getOperand(4)); 6864 Inst = TmpInst; 6865 return true; 6866 } 6867 6868 case ARM::VLD4DUPdWB_fixed_Asm_8: 6869 case ARM::VLD4DUPdWB_fixed_Asm_16: 6870 case ARM::VLD4DUPdWB_fixed_Asm_32: 6871 case ARM::VLD4DUPqWB_fixed_Asm_8: 6872 case ARM::VLD4DUPqWB_fixed_Asm_16: 6873 case ARM::VLD4DUPqWB_fixed_Asm_32: { 6874 MCInst TmpInst; 6875 unsigned Spacing; 6876 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6877 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6878 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6879 Spacing)); 6880 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6881 Spacing * 2)); 6882 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6883 Spacing * 3)); 6884 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6885 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6886 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6887 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6888 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6889 TmpInst.addOperand(Inst.getOperand(4)); 6890 Inst = TmpInst; 6891 return true; 6892 } 6893 6894 case ARM::VLD4DUPdWB_register_Asm_8: 6895 case ARM::VLD4DUPdWB_register_Asm_16: 6896 case ARM::VLD4DUPdWB_register_Asm_32: 6897 case ARM::VLD4DUPqWB_register_Asm_8: 6898 case ARM::VLD4DUPqWB_register_Asm_16: 6899 case ARM::VLD4DUPqWB_register_Asm_32: { 6900 MCInst TmpInst; 6901 unsigned Spacing; 6902 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6903 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6904 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6905 Spacing)); 6906 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6907 Spacing * 2)); 6908 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6909 Spacing * 3)); 6910 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6911 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6912 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6913 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6914 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6915 TmpInst.addOperand(Inst.getOperand(5)); 6916 Inst = TmpInst; 6917 return true; 6918 } 6919 6920 // VLD4 multiple 4-element structure instructions. 6921 case ARM::VLD4dAsm_8: 6922 case ARM::VLD4dAsm_16: 6923 case ARM::VLD4dAsm_32: 6924 case ARM::VLD4qAsm_8: 6925 case ARM::VLD4qAsm_16: 6926 case ARM::VLD4qAsm_32: { 6927 MCInst TmpInst; 6928 unsigned Spacing; 6929 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6930 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6931 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6932 Spacing)); 6933 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6934 Spacing * 2)); 6935 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6936 Spacing * 3)); 6937 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6938 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6939 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6940 TmpInst.addOperand(Inst.getOperand(4)); 6941 Inst = TmpInst; 6942 return true; 6943 } 6944 6945 case ARM::VLD4dWB_fixed_Asm_8: 6946 case ARM::VLD4dWB_fixed_Asm_16: 6947 case ARM::VLD4dWB_fixed_Asm_32: 6948 case ARM::VLD4qWB_fixed_Asm_8: 6949 case ARM::VLD4qWB_fixed_Asm_16: 6950 case ARM::VLD4qWB_fixed_Asm_32: { 6951 MCInst TmpInst; 6952 unsigned Spacing; 6953 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6954 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6955 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6956 Spacing)); 6957 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6958 Spacing * 2)); 6959 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6960 Spacing * 3)); 6961 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6962 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6963 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6964 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6965 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6966 TmpInst.addOperand(Inst.getOperand(4)); 6967 Inst = TmpInst; 6968 return true; 6969 } 6970 6971 case ARM::VLD4dWB_register_Asm_8: 6972 case ARM::VLD4dWB_register_Asm_16: 6973 case ARM::VLD4dWB_register_Asm_32: 6974 case ARM::VLD4qWB_register_Asm_8: 6975 case ARM::VLD4qWB_register_Asm_16: 6976 case ARM::VLD4qWB_register_Asm_32: { 6977 MCInst TmpInst; 6978 unsigned Spacing; 6979 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6980 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6981 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6982 Spacing)); 6983 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6984 Spacing * 2)); 6985 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6986 Spacing * 3)); 6987 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6988 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6989 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6990 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6991 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6992 TmpInst.addOperand(Inst.getOperand(5)); 6993 Inst = TmpInst; 6994 return true; 6995 } 6996 6997 // VST3 multiple 3-element structure instructions. 6998 case ARM::VST3dAsm_8: 6999 case ARM::VST3dAsm_16: 7000 case ARM::VST3dAsm_32: 7001 case ARM::VST3qAsm_8: 7002 case ARM::VST3qAsm_16: 7003 case ARM::VST3qAsm_32: { 7004 MCInst TmpInst; 7005 unsigned Spacing; 7006 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7007 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7008 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7009 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7010 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7011 Spacing)); 7012 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7013 Spacing * 2)); 7014 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7015 TmpInst.addOperand(Inst.getOperand(4)); 7016 Inst = TmpInst; 7017 return true; 7018 } 7019 7020 case ARM::VST3dWB_fixed_Asm_8: 7021 case ARM::VST3dWB_fixed_Asm_16: 7022 case ARM::VST3dWB_fixed_Asm_32: 7023 case ARM::VST3qWB_fixed_Asm_8: 7024 case ARM::VST3qWB_fixed_Asm_16: 7025 case ARM::VST3qWB_fixed_Asm_32: { 7026 MCInst TmpInst; 7027 unsigned Spacing; 7028 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7029 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7030 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7031 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7032 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7033 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7034 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7035 Spacing)); 7036 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7037 Spacing * 2)); 7038 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7039 TmpInst.addOperand(Inst.getOperand(4)); 7040 Inst = TmpInst; 7041 return true; 7042 } 7043 7044 case ARM::VST3dWB_register_Asm_8: 7045 case ARM::VST3dWB_register_Asm_16: 7046 case ARM::VST3dWB_register_Asm_32: 7047 case ARM::VST3qWB_register_Asm_8: 7048 case ARM::VST3qWB_register_Asm_16: 7049 case ARM::VST3qWB_register_Asm_32: { 7050 MCInst TmpInst; 7051 unsigned Spacing; 7052 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7053 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7054 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7055 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7056 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7057 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7058 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7059 Spacing)); 7060 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7061 Spacing * 2)); 7062 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7063 TmpInst.addOperand(Inst.getOperand(5)); 7064 Inst = TmpInst; 7065 return true; 7066 } 7067 7068 // VST4 multiple 3-element structure instructions. 7069 case ARM::VST4dAsm_8: 7070 case ARM::VST4dAsm_16: 7071 case ARM::VST4dAsm_32: 7072 case ARM::VST4qAsm_8: 7073 case ARM::VST4qAsm_16: 7074 case ARM::VST4qAsm_32: { 7075 MCInst TmpInst; 7076 unsigned Spacing; 7077 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7078 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7079 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7080 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7082 Spacing)); 7083 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7084 Spacing * 2)); 7085 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7086 Spacing * 3)); 7087 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7088 TmpInst.addOperand(Inst.getOperand(4)); 7089 Inst = TmpInst; 7090 return true; 7091 } 7092 7093 case ARM::VST4dWB_fixed_Asm_8: 7094 case ARM::VST4dWB_fixed_Asm_16: 7095 case ARM::VST4dWB_fixed_Asm_32: 7096 case ARM::VST4qWB_fixed_Asm_8: 7097 case ARM::VST4qWB_fixed_Asm_16: 7098 case ARM::VST4qWB_fixed_Asm_32: { 7099 MCInst TmpInst; 7100 unsigned Spacing; 7101 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7102 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7103 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7104 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7105 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7106 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7107 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7108 Spacing)); 7109 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7110 Spacing * 2)); 7111 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7112 Spacing * 3)); 7113 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7114 TmpInst.addOperand(Inst.getOperand(4)); 7115 Inst = TmpInst; 7116 return true; 7117 } 7118 7119 case ARM::VST4dWB_register_Asm_8: 7120 case ARM::VST4dWB_register_Asm_16: 7121 case ARM::VST4dWB_register_Asm_32: 7122 case ARM::VST4qWB_register_Asm_8: 7123 case ARM::VST4qWB_register_Asm_16: 7124 case ARM::VST4qWB_register_Asm_32: { 7125 MCInst TmpInst; 7126 unsigned Spacing; 7127 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7128 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7129 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7130 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7131 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7132 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7133 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7134 Spacing)); 7135 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7136 Spacing * 2)); 7137 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7138 Spacing * 3)); 7139 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7140 TmpInst.addOperand(Inst.getOperand(5)); 7141 Inst = TmpInst; 7142 return true; 7143 } 7144 7145 // Handle encoding choice for the shift-immediate instructions. 7146 case ARM::t2LSLri: 7147 case ARM::t2LSRri: 7148 case ARM::t2ASRri: { 7149 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7150 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7151 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 7152 !(static_cast<ARMOperand*>(Operands[3])->isToken() && 7153 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 7154 unsigned NewOpc; 7155 switch (Inst.getOpcode()) { 7156 default: llvm_unreachable("unexpected opcode"); 7157 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 7158 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 7159 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 7160 } 7161 // The Thumb1 operands aren't in the same order. Awesome, eh? 7162 MCInst TmpInst; 7163 TmpInst.setOpcode(NewOpc); 7164 TmpInst.addOperand(Inst.getOperand(0)); 7165 TmpInst.addOperand(Inst.getOperand(5)); 7166 TmpInst.addOperand(Inst.getOperand(1)); 7167 TmpInst.addOperand(Inst.getOperand(2)); 7168 TmpInst.addOperand(Inst.getOperand(3)); 7169 TmpInst.addOperand(Inst.getOperand(4)); 7170 Inst = TmpInst; 7171 return true; 7172 } 7173 return false; 7174 } 7175 7176 // Handle the Thumb2 mode MOV complex aliases. 7177 case ARM::t2MOVsr: 7178 case ARM::t2MOVSsr: { 7179 // Which instruction to expand to depends on the CCOut operand and 7180 // whether we're in an IT block if the register operands are low 7181 // registers. 7182 bool isNarrow = false; 7183 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7184 isARMLowRegister(Inst.getOperand(1).getReg()) && 7185 isARMLowRegister(Inst.getOperand(2).getReg()) && 7186 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7187 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 7188 isNarrow = true; 7189 MCInst TmpInst; 7190 unsigned newOpc; 7191 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 7192 default: llvm_unreachable("unexpected opcode!"); 7193 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 7194 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 7195 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 7196 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 7197 } 7198 TmpInst.setOpcode(newOpc); 7199 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7200 if (isNarrow) 7201 TmpInst.addOperand(MCOperand::CreateReg( 7202 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7203 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7204 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7205 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7206 TmpInst.addOperand(Inst.getOperand(5)); 7207 if (!isNarrow) 7208 TmpInst.addOperand(MCOperand::CreateReg( 7209 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7210 Inst = TmpInst; 7211 return true; 7212 } 7213 case ARM::t2MOVsi: 7214 case ARM::t2MOVSsi: { 7215 // Which instruction to expand to depends on the CCOut operand and 7216 // whether we're in an IT block if the register operands are low 7217 // registers. 7218 bool isNarrow = false; 7219 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7220 isARMLowRegister(Inst.getOperand(1).getReg()) && 7221 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 7222 isNarrow = true; 7223 MCInst TmpInst; 7224 unsigned newOpc; 7225 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 7226 default: llvm_unreachable("unexpected opcode!"); 7227 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 7228 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 7229 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 7230 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 7231 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 7232 } 7233 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 7234 if (Amount == 32) Amount = 0; 7235 TmpInst.setOpcode(newOpc); 7236 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7237 if (isNarrow) 7238 TmpInst.addOperand(MCOperand::CreateReg( 7239 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7240 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7241 if (newOpc != ARM::t2RRX) 7242 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 7243 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7244 TmpInst.addOperand(Inst.getOperand(4)); 7245 if (!isNarrow) 7246 TmpInst.addOperand(MCOperand::CreateReg( 7247 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7248 Inst = TmpInst; 7249 return true; 7250 } 7251 // Handle the ARM mode MOV complex aliases. 7252 case ARM::ASRr: 7253 case ARM::LSRr: 7254 case ARM::LSLr: 7255 case ARM::RORr: { 7256 ARM_AM::ShiftOpc ShiftTy; 7257 switch(Inst.getOpcode()) { 7258 default: llvm_unreachable("unexpected opcode!"); 7259 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 7260 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 7261 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 7262 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 7263 } 7264 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 7265 MCInst TmpInst; 7266 TmpInst.setOpcode(ARM::MOVsr); 7267 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7268 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7269 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7270 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7271 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7272 TmpInst.addOperand(Inst.getOperand(4)); 7273 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7274 Inst = TmpInst; 7275 return true; 7276 } 7277 case ARM::ASRi: 7278 case ARM::LSRi: 7279 case ARM::LSLi: 7280 case ARM::RORi: { 7281 ARM_AM::ShiftOpc ShiftTy; 7282 switch(Inst.getOpcode()) { 7283 default: llvm_unreachable("unexpected opcode!"); 7284 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 7285 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 7286 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 7287 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 7288 } 7289 // A shift by zero is a plain MOVr, not a MOVsi. 7290 unsigned Amt = Inst.getOperand(2).getImm(); 7291 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 7292 // A shift by 32 should be encoded as 0 when permitted 7293 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 7294 Amt = 0; 7295 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 7296 MCInst TmpInst; 7297 TmpInst.setOpcode(Opc); 7298 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7299 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7300 if (Opc == ARM::MOVsi) 7301 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7302 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7303 TmpInst.addOperand(Inst.getOperand(4)); 7304 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7305 Inst = TmpInst; 7306 return true; 7307 } 7308 case ARM::RRXi: { 7309 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 7310 MCInst TmpInst; 7311 TmpInst.setOpcode(ARM::MOVsi); 7312 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7313 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7314 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7315 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7316 TmpInst.addOperand(Inst.getOperand(3)); 7317 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 7318 Inst = TmpInst; 7319 return true; 7320 } 7321 case ARM::t2LDMIA_UPD: { 7322 // If this is a load of a single register, then we should use 7323 // a post-indexed LDR instruction instead, per the ARM ARM. 7324 if (Inst.getNumOperands() != 5) 7325 return false; 7326 MCInst TmpInst; 7327 TmpInst.setOpcode(ARM::t2LDR_POST); 7328 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7329 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7330 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7331 TmpInst.addOperand(MCOperand::CreateImm(4)); 7332 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7333 TmpInst.addOperand(Inst.getOperand(3)); 7334 Inst = TmpInst; 7335 return true; 7336 } 7337 case ARM::t2STMDB_UPD: { 7338 // If this is a store of a single register, then we should use 7339 // a pre-indexed STR instruction instead, per the ARM ARM. 7340 if (Inst.getNumOperands() != 5) 7341 return false; 7342 MCInst TmpInst; 7343 TmpInst.setOpcode(ARM::t2STR_PRE); 7344 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7345 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7346 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7347 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7348 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7349 TmpInst.addOperand(Inst.getOperand(3)); 7350 Inst = TmpInst; 7351 return true; 7352 } 7353 case ARM::LDMIA_UPD: 7354 // If this is a load of a single register via a 'pop', then we should use 7355 // a post-indexed LDR instruction instead, per the ARM ARM. 7356 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 7357 Inst.getNumOperands() == 5) { 7358 MCInst TmpInst; 7359 TmpInst.setOpcode(ARM::LDR_POST_IMM); 7360 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7361 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7362 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7363 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 7364 TmpInst.addOperand(MCOperand::CreateImm(4)); 7365 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7366 TmpInst.addOperand(Inst.getOperand(3)); 7367 Inst = TmpInst; 7368 return true; 7369 } 7370 break; 7371 case ARM::STMDB_UPD: 7372 // If this is a store of a single register via a 'push', then we should use 7373 // a pre-indexed STR instruction instead, per the ARM ARM. 7374 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 7375 Inst.getNumOperands() == 5) { 7376 MCInst TmpInst; 7377 TmpInst.setOpcode(ARM::STR_PRE_IMM); 7378 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7379 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7380 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 7381 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7382 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7383 TmpInst.addOperand(Inst.getOperand(3)); 7384 Inst = TmpInst; 7385 } 7386 break; 7387 case ARM::t2ADDri12: 7388 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 7389 // mnemonic was used (not "addw"), encoding T3 is preferred. 7390 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 7391 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7392 break; 7393 Inst.setOpcode(ARM::t2ADDri); 7394 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7395 break; 7396 case ARM::t2SUBri12: 7397 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 7398 // mnemonic was used (not "subw"), encoding T3 is preferred. 7399 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 7400 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7401 break; 7402 Inst.setOpcode(ARM::t2SUBri); 7403 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7404 break; 7405 case ARM::tADDi8: 7406 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7407 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7408 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7409 // to encoding T1 if <Rd> is omitted." 7410 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7411 Inst.setOpcode(ARM::tADDi3); 7412 return true; 7413 } 7414 break; 7415 case ARM::tSUBi8: 7416 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7417 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7418 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7419 // to encoding T1 if <Rd> is omitted." 7420 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7421 Inst.setOpcode(ARM::tSUBi3); 7422 return true; 7423 } 7424 break; 7425 case ARM::t2ADDri: 7426 case ARM::t2SUBri: { 7427 // If the destination and first source operand are the same, and 7428 // the flags are compatible with the current IT status, use encoding T2 7429 // instead of T3. For compatibility with the system 'as'. Make sure the 7430 // wide encoding wasn't explicit. 7431 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7432 !isARMLowRegister(Inst.getOperand(0).getReg()) || 7433 (unsigned)Inst.getOperand(2).getImm() > 255 || 7434 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 7435 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 7436 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7437 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7438 break; 7439 MCInst TmpInst; 7440 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7441 ARM::tADDi8 : ARM::tSUBi8); 7442 TmpInst.addOperand(Inst.getOperand(0)); 7443 TmpInst.addOperand(Inst.getOperand(5)); 7444 TmpInst.addOperand(Inst.getOperand(0)); 7445 TmpInst.addOperand(Inst.getOperand(2)); 7446 TmpInst.addOperand(Inst.getOperand(3)); 7447 TmpInst.addOperand(Inst.getOperand(4)); 7448 Inst = TmpInst; 7449 return true; 7450 } 7451 case ARM::t2ADDrr: { 7452 // If the destination and first source operand are the same, and 7453 // there's no setting of the flags, use encoding T2 instead of T3. 7454 // Note that this is only for ADD, not SUB. This mirrors the system 7455 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7456 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7457 Inst.getOperand(5).getReg() != 0 || 7458 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7459 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7460 break; 7461 MCInst TmpInst; 7462 TmpInst.setOpcode(ARM::tADDhirr); 7463 TmpInst.addOperand(Inst.getOperand(0)); 7464 TmpInst.addOperand(Inst.getOperand(0)); 7465 TmpInst.addOperand(Inst.getOperand(2)); 7466 TmpInst.addOperand(Inst.getOperand(3)); 7467 TmpInst.addOperand(Inst.getOperand(4)); 7468 Inst = TmpInst; 7469 return true; 7470 } 7471 case ARM::tADDrSP: { 7472 // If the non-SP source operand and the destination operand are not the 7473 // same, we need to use the 32-bit encoding if it's available. 7474 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7475 Inst.setOpcode(ARM::t2ADDrr); 7476 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7477 return true; 7478 } 7479 break; 7480 } 7481 case ARM::tB: 7482 // A Thumb conditional branch outside of an IT block is a tBcc. 7483 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7484 Inst.setOpcode(ARM::tBcc); 7485 return true; 7486 } 7487 break; 7488 case ARM::t2B: 7489 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7490 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7491 Inst.setOpcode(ARM::t2Bcc); 7492 return true; 7493 } 7494 break; 7495 case ARM::t2Bcc: 7496 // If the conditional is AL or we're in an IT block, we really want t2B. 7497 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7498 Inst.setOpcode(ARM::t2B); 7499 return true; 7500 } 7501 break; 7502 case ARM::tBcc: 7503 // If the conditional is AL, we really want tB. 7504 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7505 Inst.setOpcode(ARM::tB); 7506 return true; 7507 } 7508 break; 7509 case ARM::tLDMIA: { 7510 // If the register list contains any high registers, or if the writeback 7511 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7512 // instead if we're in Thumb2. Otherwise, this should have generated 7513 // an error in validateInstruction(). 7514 unsigned Rn = Inst.getOperand(0).getReg(); 7515 bool hasWritebackToken = 7516 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7517 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 7518 bool listContainsBase; 7519 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7520 (!listContainsBase && !hasWritebackToken) || 7521 (listContainsBase && hasWritebackToken)) { 7522 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7523 assert (isThumbTwo()); 7524 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7525 // If we're switching to the updating version, we need to insert 7526 // the writeback tied operand. 7527 if (hasWritebackToken) 7528 Inst.insert(Inst.begin(), 7529 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7530 return true; 7531 } 7532 break; 7533 } 7534 case ARM::tSTMIA_UPD: { 7535 // If the register list contains any high registers, we need to use 7536 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7537 // should have generated an error in validateInstruction(). 7538 unsigned Rn = Inst.getOperand(0).getReg(); 7539 bool listContainsBase; 7540 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7541 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7542 assert (isThumbTwo()); 7543 Inst.setOpcode(ARM::t2STMIA_UPD); 7544 return true; 7545 } 7546 break; 7547 } 7548 case ARM::tPOP: { 7549 bool listContainsBase; 7550 // If the register list contains any high registers, we need to use 7551 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7552 // should have generated an error in validateInstruction(). 7553 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7554 return false; 7555 assert (isThumbTwo()); 7556 Inst.setOpcode(ARM::t2LDMIA_UPD); 7557 // Add the base register and writeback operands. 7558 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7559 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7560 return true; 7561 } 7562 case ARM::tPUSH: { 7563 bool listContainsBase; 7564 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7565 return false; 7566 assert (isThumbTwo()); 7567 Inst.setOpcode(ARM::t2STMDB_UPD); 7568 // Add the base register and writeback operands. 7569 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7570 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7571 return true; 7572 } 7573 case ARM::t2MOVi: { 7574 // If we can use the 16-bit encoding and the user didn't explicitly 7575 // request the 32-bit variant, transform it here. 7576 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7577 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7578 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7579 Inst.getOperand(4).getReg() == ARM::CPSR) || 7580 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7581 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7582 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7583 // The operands aren't in the same order for tMOVi8... 7584 MCInst TmpInst; 7585 TmpInst.setOpcode(ARM::tMOVi8); 7586 TmpInst.addOperand(Inst.getOperand(0)); 7587 TmpInst.addOperand(Inst.getOperand(4)); 7588 TmpInst.addOperand(Inst.getOperand(1)); 7589 TmpInst.addOperand(Inst.getOperand(2)); 7590 TmpInst.addOperand(Inst.getOperand(3)); 7591 Inst = TmpInst; 7592 return true; 7593 } 7594 break; 7595 } 7596 case ARM::t2MOVr: { 7597 // If we can use the 16-bit encoding and the user didn't explicitly 7598 // request the 32-bit variant, transform it here. 7599 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7600 isARMLowRegister(Inst.getOperand(1).getReg()) && 7601 Inst.getOperand(2).getImm() == ARMCC::AL && 7602 Inst.getOperand(4).getReg() == ARM::CPSR && 7603 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7604 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7605 // The operands aren't the same for tMOV[S]r... (no cc_out) 7606 MCInst TmpInst; 7607 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 7608 TmpInst.addOperand(Inst.getOperand(0)); 7609 TmpInst.addOperand(Inst.getOperand(1)); 7610 TmpInst.addOperand(Inst.getOperand(2)); 7611 TmpInst.addOperand(Inst.getOperand(3)); 7612 Inst = TmpInst; 7613 return true; 7614 } 7615 break; 7616 } 7617 case ARM::t2SXTH: 7618 case ARM::t2SXTB: 7619 case ARM::t2UXTH: 7620 case ARM::t2UXTB: { 7621 // If we can use the 16-bit encoding and the user didn't explicitly 7622 // request the 32-bit variant, transform it here. 7623 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7624 isARMLowRegister(Inst.getOperand(1).getReg()) && 7625 Inst.getOperand(2).getImm() == 0 && 7626 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7627 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7628 unsigned NewOpc; 7629 switch (Inst.getOpcode()) { 7630 default: llvm_unreachable("Illegal opcode!"); 7631 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7632 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7633 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7634 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 7635 } 7636 // The operands aren't the same for thumb1 (no rotate operand). 7637 MCInst TmpInst; 7638 TmpInst.setOpcode(NewOpc); 7639 TmpInst.addOperand(Inst.getOperand(0)); 7640 TmpInst.addOperand(Inst.getOperand(1)); 7641 TmpInst.addOperand(Inst.getOperand(3)); 7642 TmpInst.addOperand(Inst.getOperand(4)); 7643 Inst = TmpInst; 7644 return true; 7645 } 7646 break; 7647 } 7648 case ARM::MOVsi: { 7649 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7650 // rrx shifts and asr/lsr of #32 is encoded as 0 7651 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7652 return false; 7653 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 7654 // Shifting by zero is accepted as a vanilla 'MOVr' 7655 MCInst TmpInst; 7656 TmpInst.setOpcode(ARM::MOVr); 7657 TmpInst.addOperand(Inst.getOperand(0)); 7658 TmpInst.addOperand(Inst.getOperand(1)); 7659 TmpInst.addOperand(Inst.getOperand(3)); 7660 TmpInst.addOperand(Inst.getOperand(4)); 7661 TmpInst.addOperand(Inst.getOperand(5)); 7662 Inst = TmpInst; 7663 return true; 7664 } 7665 return false; 7666 } 7667 case ARM::ANDrsi: 7668 case ARM::ORRrsi: 7669 case ARM::EORrsi: 7670 case ARM::BICrsi: 7671 case ARM::SUBrsi: 7672 case ARM::ADDrsi: { 7673 unsigned newOpc; 7674 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 7675 if (SOpc == ARM_AM::rrx) return false; 7676 switch (Inst.getOpcode()) { 7677 default: llvm_unreachable("unexpected opcode!"); 7678 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 7679 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 7680 case ARM::EORrsi: newOpc = ARM::EORrr; break; 7681 case ARM::BICrsi: newOpc = ARM::BICrr; break; 7682 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 7683 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 7684 } 7685 // If the shift is by zero, use the non-shifted instruction definition. 7686 // The exception is for right shifts, where 0 == 32 7687 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 7688 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 7689 MCInst TmpInst; 7690 TmpInst.setOpcode(newOpc); 7691 TmpInst.addOperand(Inst.getOperand(0)); 7692 TmpInst.addOperand(Inst.getOperand(1)); 7693 TmpInst.addOperand(Inst.getOperand(2)); 7694 TmpInst.addOperand(Inst.getOperand(4)); 7695 TmpInst.addOperand(Inst.getOperand(5)); 7696 TmpInst.addOperand(Inst.getOperand(6)); 7697 Inst = TmpInst; 7698 return true; 7699 } 7700 return false; 7701 } 7702 case ARM::ITasm: 7703 case ARM::t2IT: { 7704 // The mask bits for all but the first condition are represented as 7705 // the low bit of the condition code value implies 't'. We currently 7706 // always have 1 implies 't', so XOR toggle the bits if the low bit 7707 // of the condition code is zero. 7708 MCOperand &MO = Inst.getOperand(1); 7709 unsigned Mask = MO.getImm(); 7710 unsigned OrigMask = Mask; 7711 unsigned TZ = countTrailingZeros(Mask); 7712 if ((Inst.getOperand(0).getImm() & 1) == 0) { 7713 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 7714 Mask ^= (0xE << TZ) & 0xF; 7715 } 7716 MO.setImm(Mask); 7717 7718 // Set up the IT block state according to the IT instruction we just 7719 // matched. 7720 assert(!inITBlock() && "nested IT blocks?!"); 7721 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7722 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7723 ITState.CurPosition = 0; 7724 ITState.FirstCond = true; 7725 break; 7726 } 7727 case ARM::t2LSLrr: 7728 case ARM::t2LSRrr: 7729 case ARM::t2ASRrr: 7730 case ARM::t2SBCrr: 7731 case ARM::t2RORrr: 7732 case ARM::t2BICrr: 7733 { 7734 // Assemblers should use the narrow encodings of these instructions when permissible. 7735 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7736 isARMLowRegister(Inst.getOperand(2).getReg())) && 7737 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7738 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7739 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7740 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7741 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7742 unsigned NewOpc; 7743 switch (Inst.getOpcode()) { 7744 default: llvm_unreachable("unexpected opcode"); 7745 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 7746 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 7747 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 7748 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 7749 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 7750 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 7751 } 7752 MCInst TmpInst; 7753 TmpInst.setOpcode(NewOpc); 7754 TmpInst.addOperand(Inst.getOperand(0)); 7755 TmpInst.addOperand(Inst.getOperand(5)); 7756 TmpInst.addOperand(Inst.getOperand(1)); 7757 TmpInst.addOperand(Inst.getOperand(2)); 7758 TmpInst.addOperand(Inst.getOperand(3)); 7759 TmpInst.addOperand(Inst.getOperand(4)); 7760 Inst = TmpInst; 7761 return true; 7762 } 7763 return false; 7764 } 7765 case ARM::t2ANDrr: 7766 case ARM::t2EORrr: 7767 case ARM::t2ADCrr: 7768 case ARM::t2ORRrr: 7769 { 7770 // Assemblers should use the narrow encodings of these instructions when permissible. 7771 // These instructions are special in that they are commutable, so shorter encodings 7772 // are available more often. 7773 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7774 isARMLowRegister(Inst.getOperand(2).getReg())) && 7775 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 7776 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 7777 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7778 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7779 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7780 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7781 unsigned NewOpc; 7782 switch (Inst.getOpcode()) { 7783 default: llvm_unreachable("unexpected opcode"); 7784 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 7785 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 7786 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 7787 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 7788 } 7789 MCInst TmpInst; 7790 TmpInst.setOpcode(NewOpc); 7791 TmpInst.addOperand(Inst.getOperand(0)); 7792 TmpInst.addOperand(Inst.getOperand(5)); 7793 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 7794 TmpInst.addOperand(Inst.getOperand(1)); 7795 TmpInst.addOperand(Inst.getOperand(2)); 7796 } else { 7797 TmpInst.addOperand(Inst.getOperand(2)); 7798 TmpInst.addOperand(Inst.getOperand(1)); 7799 } 7800 TmpInst.addOperand(Inst.getOperand(3)); 7801 TmpInst.addOperand(Inst.getOperand(4)); 7802 Inst = TmpInst; 7803 return true; 7804 } 7805 return false; 7806 } 7807 } 7808 return false; 7809 } 7810 7811 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 7812 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 7813 // suffix depending on whether they're in an IT block or not. 7814 unsigned Opc = Inst.getOpcode(); 7815 const MCInstrDesc &MCID = MII.get(Opc); 7816 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 7817 assert(MCID.hasOptionalDef() && 7818 "optionally flag setting instruction missing optional def operand"); 7819 assert(MCID.NumOperands == Inst.getNumOperands() && 7820 "operand count mismatch!"); 7821 // Find the optional-def operand (cc_out). 7822 unsigned OpNo; 7823 for (OpNo = 0; 7824 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 7825 ++OpNo) 7826 ; 7827 // If we're parsing Thumb1, reject it completely. 7828 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 7829 return Match_MnemonicFail; 7830 // If we're parsing Thumb2, which form is legal depends on whether we're 7831 // in an IT block. 7832 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7833 !inITBlock()) 7834 return Match_RequiresITBlock; 7835 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7836 inITBlock()) 7837 return Match_RequiresNotITBlock; 7838 } 7839 // Some high-register supporting Thumb1 encodings only allow both registers 7840 // to be from r0-r7 when in Thumb2. 7841 else if (Opc == ARM::tADDhirr && isThumbOne() && 7842 isARMLowRegister(Inst.getOperand(1).getReg()) && 7843 isARMLowRegister(Inst.getOperand(2).getReg())) 7844 return Match_RequiresThumb2; 7845 // Others only require ARMv6 or later. 7846 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7847 isARMLowRegister(Inst.getOperand(0).getReg()) && 7848 isARMLowRegister(Inst.getOperand(1).getReg())) 7849 return Match_RequiresV6; 7850 return Match_Success; 7851 } 7852 7853 static const char *getSubtargetFeatureName(unsigned Val); 7854 bool ARMAsmParser:: 7855 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 7856 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7857 MCStreamer &Out, unsigned &ErrorInfo, 7858 bool MatchingInlineAsm) { 7859 MCInst Inst; 7860 unsigned MatchResult; 7861 7862 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 7863 MatchingInlineAsm); 7864 switch (MatchResult) { 7865 default: break; 7866 case Match_Success: 7867 // Context sensitive operand constraints aren't handled by the matcher, 7868 // so check them here. 7869 if (validateInstruction(Inst, Operands)) { 7870 // Still progress the IT block, otherwise one wrong condition causes 7871 // nasty cascading errors. 7872 forwardITPosition(); 7873 return true; 7874 } 7875 7876 { // processInstruction() updates inITBlock state, we need to save it away 7877 bool wasInITBlock = inITBlock(); 7878 7879 // Some instructions need post-processing to, for example, tweak which 7880 // encoding is selected. Loop on it while changes happen so the 7881 // individual transformations can chain off each other. E.g., 7882 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 7883 while (processInstruction(Inst, Operands)) 7884 ; 7885 7886 // Only after the instruction is fully processed, we can validate it 7887 if (wasInITBlock && hasV8Ops() && isThumb() && 7888 !isV8EligibleForIT(&Inst)) { 7889 Warning(IDLoc, "deprecated instruction in IT block"); 7890 } 7891 } 7892 7893 // Only move forward at the very end so that everything in validate 7894 // and process gets a consistent answer about whether we're in an IT 7895 // block. 7896 forwardITPosition(); 7897 7898 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 7899 // doesn't actually encode. 7900 if (Inst.getOpcode() == ARM::ITasm) 7901 return false; 7902 7903 Inst.setLoc(IDLoc); 7904 Out.EmitInstruction(Inst, STI); 7905 return false; 7906 case Match_MissingFeature: { 7907 assert(ErrorInfo && "Unknown missing feature!"); 7908 // Special case the error message for the very common case where only 7909 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 7910 std::string Msg = "instruction requires:"; 7911 unsigned Mask = 1; 7912 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 7913 if (ErrorInfo & Mask) { 7914 Msg += " "; 7915 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 7916 } 7917 Mask <<= 1; 7918 } 7919 return Error(IDLoc, Msg); 7920 } 7921 case Match_InvalidOperand: { 7922 SMLoc ErrorLoc = IDLoc; 7923 if (ErrorInfo != ~0U) { 7924 if (ErrorInfo >= Operands.size()) 7925 return Error(IDLoc, "too few operands for instruction"); 7926 7927 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7928 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7929 } 7930 7931 return Error(ErrorLoc, "invalid operand for instruction"); 7932 } 7933 case Match_MnemonicFail: 7934 return Error(IDLoc, "invalid instruction", 7935 ((ARMOperand*)Operands[0])->getLocRange()); 7936 case Match_RequiresNotITBlock: 7937 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 7938 case Match_RequiresITBlock: 7939 return Error(IDLoc, "instruction only valid inside IT block"); 7940 case Match_RequiresV6: 7941 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7942 case Match_RequiresThumb2: 7943 return Error(IDLoc, "instruction variant requires Thumb2"); 7944 case Match_ImmRange0_15: { 7945 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7946 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7947 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 7948 } 7949 case Match_ImmRange0_239: { 7950 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7951 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7952 return Error(ErrorLoc, "immediate operand must be in the range [0,239]"); 7953 } 7954 } 7955 7956 llvm_unreachable("Implement any new match types added!"); 7957 } 7958 7959 /// parseDirective parses the arm specific directives 7960 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7961 StringRef IDVal = DirectiveID.getIdentifier(); 7962 if (IDVal == ".word") 7963 return parseLiteralValues(4, DirectiveID.getLoc()); 7964 else if (IDVal == ".short" || IDVal == ".hword") 7965 return parseLiteralValues(2, DirectiveID.getLoc()); 7966 else if (IDVal == ".thumb") 7967 return parseDirectiveThumb(DirectiveID.getLoc()); 7968 else if (IDVal == ".arm") 7969 return parseDirectiveARM(DirectiveID.getLoc()); 7970 else if (IDVal == ".thumb_func") 7971 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7972 else if (IDVal == ".code") 7973 return parseDirectiveCode(DirectiveID.getLoc()); 7974 else if (IDVal == ".syntax") 7975 return parseDirectiveSyntax(DirectiveID.getLoc()); 7976 else if (IDVal == ".unreq") 7977 return parseDirectiveUnreq(DirectiveID.getLoc()); 7978 else if (IDVal == ".arch") 7979 return parseDirectiveArch(DirectiveID.getLoc()); 7980 else if (IDVal == ".eabi_attribute") 7981 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7982 else if (IDVal == ".cpu") 7983 return parseDirectiveCPU(DirectiveID.getLoc()); 7984 else if (IDVal == ".fpu") 7985 return parseDirectiveFPU(DirectiveID.getLoc()); 7986 else if (IDVal == ".fnstart") 7987 return parseDirectiveFnStart(DirectiveID.getLoc()); 7988 else if (IDVal == ".fnend") 7989 return parseDirectiveFnEnd(DirectiveID.getLoc()); 7990 else if (IDVal == ".cantunwind") 7991 return parseDirectiveCantUnwind(DirectiveID.getLoc()); 7992 else if (IDVal == ".personality") 7993 return parseDirectivePersonality(DirectiveID.getLoc()); 7994 else if (IDVal == ".handlerdata") 7995 return parseDirectiveHandlerData(DirectiveID.getLoc()); 7996 else if (IDVal == ".setfp") 7997 return parseDirectiveSetFP(DirectiveID.getLoc()); 7998 else if (IDVal == ".pad") 7999 return parseDirectivePad(DirectiveID.getLoc()); 8000 else if (IDVal == ".save") 8001 return parseDirectiveRegSave(DirectiveID.getLoc(), false); 8002 else if (IDVal == ".vsave") 8003 return parseDirectiveRegSave(DirectiveID.getLoc(), true); 8004 else if (IDVal == ".inst") 8005 return parseDirectiveInst(DirectiveID.getLoc()); 8006 else if (IDVal == ".inst.n") 8007 return parseDirectiveInst(DirectiveID.getLoc(), 'n'); 8008 else if (IDVal == ".inst.w") 8009 return parseDirectiveInst(DirectiveID.getLoc(), 'w'); 8010 else if (IDVal == ".ltorg" || IDVal == ".pool") 8011 return parseDirectiveLtorg(DirectiveID.getLoc()); 8012 else if (IDVal == ".even") 8013 return parseDirectiveEven(DirectiveID.getLoc()); 8014 else if (IDVal == ".personalityindex") 8015 return parseDirectivePersonalityIndex(DirectiveID.getLoc()); 8016 else if (IDVal == ".unwind_raw") 8017 return parseDirectiveUnwindRaw(DirectiveID.getLoc()); 8018 else if (IDVal == ".tlsdescseq") 8019 return parseDirectiveTLSDescSeq(DirectiveID.getLoc()); 8020 else if (IDVal == ".movsp") 8021 return parseDirectiveMovSP(DirectiveID.getLoc()); 8022 else if (IDVal == ".object_arch") 8023 return parseDirectiveObjectArch(DirectiveID.getLoc()); 8024 else if (IDVal == ".arch_extension") 8025 return parseDirectiveArchExtension(DirectiveID.getLoc()); 8026 else if (IDVal == ".align") 8027 return parseDirectiveAlign(DirectiveID.getLoc()); 8028 return true; 8029 } 8030 8031 /// parseLiteralValues 8032 /// ::= .hword expression [, expression]* 8033 /// ::= .short expression [, expression]* 8034 /// ::= .word expression [, expression]* 8035 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) { 8036 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8037 for (;;) { 8038 const MCExpr *Value; 8039 if (getParser().parseExpression(Value)) { 8040 Parser.eatToEndOfStatement(); 8041 return false; 8042 } 8043 8044 getParser().getStreamer().EmitValue(Value, Size); 8045 8046 if (getLexer().is(AsmToken::EndOfStatement)) 8047 break; 8048 8049 // FIXME: Improve diagnostic. 8050 if (getLexer().isNot(AsmToken::Comma)) { 8051 Error(L, "unexpected token in directive"); 8052 return false; 8053 } 8054 Parser.Lex(); 8055 } 8056 } 8057 8058 Parser.Lex(); 8059 return false; 8060 } 8061 8062 /// parseDirectiveThumb 8063 /// ::= .thumb 8064 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 8065 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8066 Error(L, "unexpected token in directive"); 8067 return false; 8068 } 8069 Parser.Lex(); 8070 8071 if (!hasThumb()) { 8072 Error(L, "target does not support Thumb mode"); 8073 return false; 8074 } 8075 8076 if (!isThumb()) 8077 SwitchMode(); 8078 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 8079 return false; 8080 } 8081 8082 /// parseDirectiveARM 8083 /// ::= .arm 8084 bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 8085 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8086 Error(L, "unexpected token in directive"); 8087 return false; 8088 } 8089 Parser.Lex(); 8090 8091 if (!hasARM()) { 8092 Error(L, "target does not support ARM mode"); 8093 return false; 8094 } 8095 8096 if (isThumb()) 8097 SwitchMode(); 8098 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 8099 return false; 8100 } 8101 8102 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { 8103 if (NextSymbolIsThumb) { 8104 getParser().getStreamer().EmitThumbFunc(Symbol); 8105 NextSymbolIsThumb = false; 8106 } 8107 } 8108 8109 /// parseDirectiveThumbFunc 8110 /// ::= .thumbfunc symbol_name 8111 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 8112 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo(); 8113 bool isMachO = MAI->hasSubsectionsViaSymbols(); 8114 8115 // Darwin asm has (optionally) function name after .thumb_func direction 8116 // ELF doesn't 8117 if (isMachO) { 8118 const AsmToken &Tok = Parser.getTok(); 8119 if (Tok.isNot(AsmToken::EndOfStatement)) { 8120 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) { 8121 Error(L, "unexpected token in .thumb_func directive"); 8122 return false; 8123 } 8124 8125 MCSymbol *Func = 8126 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier()); 8127 getParser().getStreamer().EmitThumbFunc(Func); 8128 Parser.Lex(); // Consume the identifier token. 8129 return false; 8130 } 8131 } 8132 8133 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8134 Error(L, "unexpected token in directive"); 8135 return false; 8136 } 8137 8138 NextSymbolIsThumb = true; 8139 return false; 8140 } 8141 8142 /// parseDirectiveSyntax 8143 /// ::= .syntax unified | divided 8144 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 8145 const AsmToken &Tok = Parser.getTok(); 8146 if (Tok.isNot(AsmToken::Identifier)) { 8147 Error(L, "unexpected token in .syntax directive"); 8148 return false; 8149 } 8150 8151 StringRef Mode = Tok.getString(); 8152 if (Mode == "unified" || Mode == "UNIFIED") { 8153 Parser.Lex(); 8154 } else if (Mode == "divided" || Mode == "DIVIDED") { 8155 Error(L, "'.syntax divided' arm asssembly not supported"); 8156 return false; 8157 } else { 8158 Error(L, "unrecognized syntax mode in .syntax directive"); 8159 return false; 8160 } 8161 8162 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8163 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8164 return false; 8165 } 8166 Parser.Lex(); 8167 8168 // TODO tell the MC streamer the mode 8169 // getParser().getStreamer().Emit???(); 8170 return false; 8171 } 8172 8173 /// parseDirectiveCode 8174 /// ::= .code 16 | 32 8175 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 8176 const AsmToken &Tok = Parser.getTok(); 8177 if (Tok.isNot(AsmToken::Integer)) { 8178 Error(L, "unexpected token in .code directive"); 8179 return false; 8180 } 8181 int64_t Val = Parser.getTok().getIntVal(); 8182 if (Val != 16 && Val != 32) { 8183 Error(L, "invalid operand to .code directive"); 8184 return false; 8185 } 8186 Parser.Lex(); 8187 8188 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8189 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8190 return false; 8191 } 8192 Parser.Lex(); 8193 8194 if (Val == 16) { 8195 if (!hasThumb()) { 8196 Error(L, "target does not support Thumb mode"); 8197 return false; 8198 } 8199 8200 if (!isThumb()) 8201 SwitchMode(); 8202 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 8203 } else { 8204 if (!hasARM()) { 8205 Error(L, "target does not support ARM mode"); 8206 return false; 8207 } 8208 8209 if (isThumb()) 8210 SwitchMode(); 8211 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 8212 } 8213 8214 return false; 8215 } 8216 8217 /// parseDirectiveReq 8218 /// ::= name .req registername 8219 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 8220 Parser.Lex(); // Eat the '.req' token. 8221 unsigned Reg; 8222 SMLoc SRegLoc, ERegLoc; 8223 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 8224 Parser.eatToEndOfStatement(); 8225 Error(SRegLoc, "register name expected"); 8226 return false; 8227 } 8228 8229 // Shouldn't be anything else. 8230 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 8231 Parser.eatToEndOfStatement(); 8232 Error(Parser.getTok().getLoc(), "unexpected input in .req directive."); 8233 return false; 8234 } 8235 8236 Parser.Lex(); // Consume the EndOfStatement 8237 8238 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) { 8239 Error(SRegLoc, "redefinition of '" + Name + "' does not match original."); 8240 return false; 8241 } 8242 8243 return false; 8244 } 8245 8246 /// parseDirectiveUneq 8247 /// ::= .unreq registername 8248 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 8249 if (Parser.getTok().isNot(AsmToken::Identifier)) { 8250 Parser.eatToEndOfStatement(); 8251 Error(L, "unexpected input in .unreq directive."); 8252 return false; 8253 } 8254 RegisterReqs.erase(Parser.getTok().getIdentifier()); 8255 Parser.Lex(); // Eat the identifier. 8256 return false; 8257 } 8258 8259 /// parseDirectiveArch 8260 /// ::= .arch token 8261 bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 8262 StringRef Arch = getParser().parseStringToEndOfStatement().trim(); 8263 8264 unsigned ID = StringSwitch<unsigned>(Arch) 8265 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \ 8266 .Case(NAME, ARM::ID) 8267 #define ARM_ARCH_ALIAS(NAME, ID) \ 8268 .Case(NAME, ARM::ID) 8269 #include "MCTargetDesc/ARMArchName.def" 8270 .Default(ARM::INVALID_ARCH); 8271 8272 if (ID == ARM::INVALID_ARCH) { 8273 Error(L, "Unknown arch name"); 8274 return false; 8275 } 8276 8277 getTargetStreamer().emitArch(ID); 8278 return false; 8279 } 8280 8281 /// parseDirectiveEabiAttr 8282 /// ::= .eabi_attribute int, int [, "str"] 8283 /// ::= .eabi_attribute Tag_name, int [, "str"] 8284 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 8285 int64_t Tag; 8286 SMLoc TagLoc; 8287 8288 TagLoc = Parser.getTok().getLoc(); 8289 if (Parser.getTok().is(AsmToken::Identifier)) { 8290 StringRef Name = Parser.getTok().getIdentifier(); 8291 Tag = ARMBuildAttrs::AttrTypeFromString(Name); 8292 if (Tag == -1) { 8293 Error(TagLoc, "attribute name not recognised: " + Name); 8294 Parser.eatToEndOfStatement(); 8295 return false; 8296 } 8297 Parser.Lex(); 8298 } else { 8299 const MCExpr *AttrExpr; 8300 8301 TagLoc = Parser.getTok().getLoc(); 8302 if (Parser.parseExpression(AttrExpr)) { 8303 Parser.eatToEndOfStatement(); 8304 return false; 8305 } 8306 8307 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr); 8308 if (!CE) { 8309 Error(TagLoc, "expected numeric constant"); 8310 Parser.eatToEndOfStatement(); 8311 return false; 8312 } 8313 8314 Tag = CE->getValue(); 8315 } 8316 8317 if (Parser.getTok().isNot(AsmToken::Comma)) { 8318 Error(Parser.getTok().getLoc(), "comma expected"); 8319 Parser.eatToEndOfStatement(); 8320 return false; 8321 } 8322 Parser.Lex(); // skip comma 8323 8324 StringRef StringValue = ""; 8325 bool IsStringValue = false; 8326 8327 int64_t IntegerValue = 0; 8328 bool IsIntegerValue = false; 8329 8330 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name) 8331 IsStringValue = true; 8332 else if (Tag == ARMBuildAttrs::compatibility) { 8333 IsStringValue = true; 8334 IsIntegerValue = true; 8335 } else if (Tag < 32 || Tag % 2 == 0) 8336 IsIntegerValue = true; 8337 else if (Tag % 2 == 1) 8338 IsStringValue = true; 8339 else 8340 llvm_unreachable("invalid tag type"); 8341 8342 if (IsIntegerValue) { 8343 const MCExpr *ValueExpr; 8344 SMLoc ValueExprLoc = Parser.getTok().getLoc(); 8345 if (Parser.parseExpression(ValueExpr)) { 8346 Parser.eatToEndOfStatement(); 8347 return false; 8348 } 8349 8350 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr); 8351 if (!CE) { 8352 Error(ValueExprLoc, "expected numeric constant"); 8353 Parser.eatToEndOfStatement(); 8354 return false; 8355 } 8356 8357 IntegerValue = CE->getValue(); 8358 } 8359 8360 if (Tag == ARMBuildAttrs::compatibility) { 8361 if (Parser.getTok().isNot(AsmToken::Comma)) 8362 IsStringValue = false; 8363 else 8364 Parser.Lex(); 8365 } 8366 8367 if (IsStringValue) { 8368 if (Parser.getTok().isNot(AsmToken::String)) { 8369 Error(Parser.getTok().getLoc(), "bad string constant"); 8370 Parser.eatToEndOfStatement(); 8371 return false; 8372 } 8373 8374 StringValue = Parser.getTok().getStringContents(); 8375 Parser.Lex(); 8376 } 8377 8378 if (IsIntegerValue && IsStringValue) { 8379 assert(Tag == ARMBuildAttrs::compatibility); 8380 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue); 8381 } else if (IsIntegerValue) 8382 getTargetStreamer().emitAttribute(Tag, IntegerValue); 8383 else if (IsStringValue) 8384 getTargetStreamer().emitTextAttribute(Tag, StringValue); 8385 return false; 8386 } 8387 8388 /// parseDirectiveCPU 8389 /// ::= .cpu str 8390 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { 8391 StringRef CPU = getParser().parseStringToEndOfStatement().trim(); 8392 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU); 8393 return false; 8394 } 8395 8396 /// parseDirectiveFPU 8397 /// ::= .fpu str 8398 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { 8399 StringRef FPU = getParser().parseStringToEndOfStatement().trim(); 8400 8401 unsigned ID = StringSwitch<unsigned>(FPU) 8402 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID) 8403 #include "ARMFPUName.def" 8404 .Default(ARM::INVALID_FPU); 8405 8406 if (ID == ARM::INVALID_FPU) { 8407 Error(L, "Unknown FPU name"); 8408 return false; 8409 } 8410 8411 getTargetStreamer().emitFPU(ID); 8412 return false; 8413 } 8414 8415 /// parseDirectiveFnStart 8416 /// ::= .fnstart 8417 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { 8418 if (UC.hasFnStart()) { 8419 Error(L, ".fnstart starts before the end of previous one"); 8420 UC.emitFnStartLocNotes(); 8421 return false; 8422 } 8423 8424 // Reset the unwind directives parser state 8425 UC.reset(); 8426 8427 getTargetStreamer().emitFnStart(); 8428 8429 UC.recordFnStart(L); 8430 return false; 8431 } 8432 8433 /// parseDirectiveFnEnd 8434 /// ::= .fnend 8435 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { 8436 // Check the ordering of unwind directives 8437 if (!UC.hasFnStart()) { 8438 Error(L, ".fnstart must precede .fnend directive"); 8439 return false; 8440 } 8441 8442 // Reset the unwind directives parser state 8443 getTargetStreamer().emitFnEnd(); 8444 8445 UC.reset(); 8446 return false; 8447 } 8448 8449 /// parseDirectiveCantUnwind 8450 /// ::= .cantunwind 8451 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { 8452 UC.recordCantUnwind(L); 8453 8454 // Check the ordering of unwind directives 8455 if (!UC.hasFnStart()) { 8456 Error(L, ".fnstart must precede .cantunwind directive"); 8457 return false; 8458 } 8459 if (UC.hasHandlerData()) { 8460 Error(L, ".cantunwind can't be used with .handlerdata directive"); 8461 UC.emitHandlerDataLocNotes(); 8462 return false; 8463 } 8464 if (UC.hasPersonality()) { 8465 Error(L, ".cantunwind can't be used with .personality directive"); 8466 UC.emitPersonalityLocNotes(); 8467 return false; 8468 } 8469 8470 getTargetStreamer().emitCantUnwind(); 8471 return false; 8472 } 8473 8474 /// parseDirectivePersonality 8475 /// ::= .personality name 8476 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { 8477 bool HasExistingPersonality = UC.hasPersonality(); 8478 8479 UC.recordPersonality(L); 8480 8481 // Check the ordering of unwind directives 8482 if (!UC.hasFnStart()) { 8483 Error(L, ".fnstart must precede .personality directive"); 8484 return false; 8485 } 8486 if (UC.cantUnwind()) { 8487 Error(L, ".personality can't be used with .cantunwind directive"); 8488 UC.emitCantUnwindLocNotes(); 8489 return false; 8490 } 8491 if (UC.hasHandlerData()) { 8492 Error(L, ".personality must precede .handlerdata directive"); 8493 UC.emitHandlerDataLocNotes(); 8494 return false; 8495 } 8496 if (HasExistingPersonality) { 8497 Parser.eatToEndOfStatement(); 8498 Error(L, "multiple personality directives"); 8499 UC.emitPersonalityLocNotes(); 8500 return false; 8501 } 8502 8503 // Parse the name of the personality routine 8504 if (Parser.getTok().isNot(AsmToken::Identifier)) { 8505 Parser.eatToEndOfStatement(); 8506 Error(L, "unexpected input in .personality directive."); 8507 return false; 8508 } 8509 StringRef Name(Parser.getTok().getIdentifier()); 8510 Parser.Lex(); 8511 8512 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name); 8513 getTargetStreamer().emitPersonality(PR); 8514 return false; 8515 } 8516 8517 /// parseDirectiveHandlerData 8518 /// ::= .handlerdata 8519 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { 8520 UC.recordHandlerData(L); 8521 8522 // Check the ordering of unwind directives 8523 if (!UC.hasFnStart()) { 8524 Error(L, ".fnstart must precede .personality directive"); 8525 return false; 8526 } 8527 if (UC.cantUnwind()) { 8528 Error(L, ".handlerdata can't be used with .cantunwind directive"); 8529 UC.emitCantUnwindLocNotes(); 8530 return false; 8531 } 8532 8533 getTargetStreamer().emitHandlerData(); 8534 return false; 8535 } 8536 8537 /// parseDirectiveSetFP 8538 /// ::= .setfp fpreg, spreg [, offset] 8539 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { 8540 // Check the ordering of unwind directives 8541 if (!UC.hasFnStart()) { 8542 Error(L, ".fnstart must precede .setfp directive"); 8543 return false; 8544 } 8545 if (UC.hasHandlerData()) { 8546 Error(L, ".setfp must precede .handlerdata directive"); 8547 return false; 8548 } 8549 8550 // Parse fpreg 8551 SMLoc FPRegLoc = Parser.getTok().getLoc(); 8552 int FPReg = tryParseRegister(); 8553 if (FPReg == -1) { 8554 Error(FPRegLoc, "frame pointer register expected"); 8555 return false; 8556 } 8557 8558 // Consume comma 8559 if (Parser.getTok().isNot(AsmToken::Comma)) { 8560 Error(Parser.getTok().getLoc(), "comma expected"); 8561 return false; 8562 } 8563 Parser.Lex(); // skip comma 8564 8565 // Parse spreg 8566 SMLoc SPRegLoc = Parser.getTok().getLoc(); 8567 int SPReg = tryParseRegister(); 8568 if (SPReg == -1) { 8569 Error(SPRegLoc, "stack pointer register expected"); 8570 return false; 8571 } 8572 8573 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) { 8574 Error(SPRegLoc, "register should be either $sp or the latest fp register"); 8575 return false; 8576 } 8577 8578 // Update the frame pointer register 8579 UC.saveFPReg(FPReg); 8580 8581 // Parse offset 8582 int64_t Offset = 0; 8583 if (Parser.getTok().is(AsmToken::Comma)) { 8584 Parser.Lex(); // skip comma 8585 8586 if (Parser.getTok().isNot(AsmToken::Hash) && 8587 Parser.getTok().isNot(AsmToken::Dollar)) { 8588 Error(Parser.getTok().getLoc(), "'#' expected"); 8589 return false; 8590 } 8591 Parser.Lex(); // skip hash token. 8592 8593 const MCExpr *OffsetExpr; 8594 SMLoc ExLoc = Parser.getTok().getLoc(); 8595 SMLoc EndLoc; 8596 if (getParser().parseExpression(OffsetExpr, EndLoc)) { 8597 Error(ExLoc, "malformed setfp offset"); 8598 return false; 8599 } 8600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8601 if (!CE) { 8602 Error(ExLoc, "setfp offset must be an immediate"); 8603 return false; 8604 } 8605 8606 Offset = CE->getValue(); 8607 } 8608 8609 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg), 8610 static_cast<unsigned>(SPReg), Offset); 8611 return false; 8612 } 8613 8614 /// parseDirective 8615 /// ::= .pad offset 8616 bool ARMAsmParser::parseDirectivePad(SMLoc L) { 8617 // Check the ordering of unwind directives 8618 if (!UC.hasFnStart()) { 8619 Error(L, ".fnstart must precede .pad directive"); 8620 return false; 8621 } 8622 if (UC.hasHandlerData()) { 8623 Error(L, ".pad must precede .handlerdata directive"); 8624 return false; 8625 } 8626 8627 // Parse the offset 8628 if (Parser.getTok().isNot(AsmToken::Hash) && 8629 Parser.getTok().isNot(AsmToken::Dollar)) { 8630 Error(Parser.getTok().getLoc(), "'#' expected"); 8631 return false; 8632 } 8633 Parser.Lex(); // skip hash token. 8634 8635 const MCExpr *OffsetExpr; 8636 SMLoc ExLoc = Parser.getTok().getLoc(); 8637 SMLoc EndLoc; 8638 if (getParser().parseExpression(OffsetExpr, EndLoc)) { 8639 Error(ExLoc, "malformed pad offset"); 8640 return false; 8641 } 8642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8643 if (!CE) { 8644 Error(ExLoc, "pad offset must be an immediate"); 8645 return false; 8646 } 8647 8648 getTargetStreamer().emitPad(CE->getValue()); 8649 return false; 8650 } 8651 8652 /// parseDirectiveRegSave 8653 /// ::= .save { registers } 8654 /// ::= .vsave { registers } 8655 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { 8656 // Check the ordering of unwind directives 8657 if (!UC.hasFnStart()) { 8658 Error(L, ".fnstart must precede .save or .vsave directives"); 8659 return false; 8660 } 8661 if (UC.hasHandlerData()) { 8662 Error(L, ".save or .vsave must precede .handlerdata directive"); 8663 return false; 8664 } 8665 8666 // RAII object to make sure parsed operands are deleted. 8667 struct CleanupObject { 8668 SmallVector<MCParsedAsmOperand *, 1> Operands; 8669 ~CleanupObject() { 8670 for (unsigned I = 0, E = Operands.size(); I != E; ++I) 8671 delete Operands[I]; 8672 } 8673 } CO; 8674 8675 // Parse the register list 8676 if (parseRegisterList(CO.Operands)) 8677 return false; 8678 ARMOperand *Op = (ARMOperand*)CO.Operands[0]; 8679 if (!IsVector && !Op->isRegList()) { 8680 Error(L, ".save expects GPR registers"); 8681 return false; 8682 } 8683 if (IsVector && !Op->isDPRRegList()) { 8684 Error(L, ".vsave expects DPR registers"); 8685 return false; 8686 } 8687 8688 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector); 8689 return false; 8690 } 8691 8692 /// parseDirectiveInst 8693 /// ::= .inst opcode [, ...] 8694 /// ::= .inst.n opcode [, ...] 8695 /// ::= .inst.w opcode [, ...] 8696 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) { 8697 int Width; 8698 8699 if (isThumb()) { 8700 switch (Suffix) { 8701 case 'n': 8702 Width = 2; 8703 break; 8704 case 'w': 8705 Width = 4; 8706 break; 8707 default: 8708 Parser.eatToEndOfStatement(); 8709 Error(Loc, "cannot determine Thumb instruction size, " 8710 "use inst.n/inst.w instead"); 8711 return false; 8712 } 8713 } else { 8714 if (Suffix) { 8715 Parser.eatToEndOfStatement(); 8716 Error(Loc, "width suffixes are invalid in ARM mode"); 8717 return false; 8718 } 8719 Width = 4; 8720 } 8721 8722 if (getLexer().is(AsmToken::EndOfStatement)) { 8723 Parser.eatToEndOfStatement(); 8724 Error(Loc, "expected expression following directive"); 8725 return false; 8726 } 8727 8728 for (;;) { 8729 const MCExpr *Expr; 8730 8731 if (getParser().parseExpression(Expr)) { 8732 Error(Loc, "expected expression"); 8733 return false; 8734 } 8735 8736 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr); 8737 if (!Value) { 8738 Error(Loc, "expected constant expression"); 8739 return false; 8740 } 8741 8742 switch (Width) { 8743 case 2: 8744 if (Value->getValue() > 0xffff) { 8745 Error(Loc, "inst.n operand is too big, use inst.w instead"); 8746 return false; 8747 } 8748 break; 8749 case 4: 8750 if (Value->getValue() > 0xffffffff) { 8751 Error(Loc, 8752 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big"); 8753 return false; 8754 } 8755 break; 8756 default: 8757 llvm_unreachable("only supported widths are 2 and 4"); 8758 } 8759 8760 getTargetStreamer().emitInst(Value->getValue(), Suffix); 8761 8762 if (getLexer().is(AsmToken::EndOfStatement)) 8763 break; 8764 8765 if (getLexer().isNot(AsmToken::Comma)) { 8766 Error(Loc, "unexpected token in directive"); 8767 return false; 8768 } 8769 8770 Parser.Lex(); 8771 } 8772 8773 Parser.Lex(); 8774 return false; 8775 } 8776 8777 /// parseDirectiveLtorg 8778 /// ::= .ltorg | .pool 8779 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) { 8780 getTargetStreamer().emitCurrentConstantPool(); 8781 return false; 8782 } 8783 8784 bool ARMAsmParser::parseDirectiveEven(SMLoc L) { 8785 const MCSection *Section = getStreamer().getCurrentSection().first; 8786 8787 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8788 TokError("unexpected token in directive"); 8789 return false; 8790 } 8791 8792 if (!Section) { 8793 getStreamer().InitSections(); 8794 Section = getStreamer().getCurrentSection().first; 8795 } 8796 8797 if (Section->UseCodeAlign()) 8798 getStreamer().EmitCodeAlignment(2); 8799 else 8800 getStreamer().EmitValueToAlignment(2); 8801 8802 return false; 8803 } 8804 8805 /// parseDirectivePersonalityIndex 8806 /// ::= .personalityindex index 8807 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) { 8808 bool HasExistingPersonality = UC.hasPersonality(); 8809 8810 UC.recordPersonalityIndex(L); 8811 8812 if (!UC.hasFnStart()) { 8813 Parser.eatToEndOfStatement(); 8814 Error(L, ".fnstart must precede .personalityindex directive"); 8815 return false; 8816 } 8817 if (UC.cantUnwind()) { 8818 Parser.eatToEndOfStatement(); 8819 Error(L, ".personalityindex cannot be used with .cantunwind"); 8820 UC.emitCantUnwindLocNotes(); 8821 return false; 8822 } 8823 if (UC.hasHandlerData()) { 8824 Parser.eatToEndOfStatement(); 8825 Error(L, ".personalityindex must precede .handlerdata directive"); 8826 UC.emitHandlerDataLocNotes(); 8827 return false; 8828 } 8829 if (HasExistingPersonality) { 8830 Parser.eatToEndOfStatement(); 8831 Error(L, "multiple personality directives"); 8832 UC.emitPersonalityLocNotes(); 8833 return false; 8834 } 8835 8836 const MCExpr *IndexExpression; 8837 SMLoc IndexLoc = Parser.getTok().getLoc(); 8838 if (Parser.parseExpression(IndexExpression)) { 8839 Parser.eatToEndOfStatement(); 8840 return false; 8841 } 8842 8843 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression); 8844 if (!CE) { 8845 Parser.eatToEndOfStatement(); 8846 Error(IndexLoc, "index must be a constant number"); 8847 return false; 8848 } 8849 if (CE->getValue() < 0 || 8850 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) { 8851 Parser.eatToEndOfStatement(); 8852 Error(IndexLoc, "personality routine index should be in range [0-3]"); 8853 return false; 8854 } 8855 8856 getTargetStreamer().emitPersonalityIndex(CE->getValue()); 8857 return false; 8858 } 8859 8860 /// parseDirectiveUnwindRaw 8861 /// ::= .unwind_raw offset, opcode [, opcode...] 8862 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) { 8863 if (!UC.hasFnStart()) { 8864 Parser.eatToEndOfStatement(); 8865 Error(L, ".fnstart must precede .unwind_raw directives"); 8866 return false; 8867 } 8868 8869 int64_t StackOffset; 8870 8871 const MCExpr *OffsetExpr; 8872 SMLoc OffsetLoc = getLexer().getLoc(); 8873 if (getLexer().is(AsmToken::EndOfStatement) || 8874 getParser().parseExpression(OffsetExpr)) { 8875 Error(OffsetLoc, "expected expression"); 8876 Parser.eatToEndOfStatement(); 8877 return false; 8878 } 8879 8880 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8881 if (!CE) { 8882 Error(OffsetLoc, "offset must be a constant"); 8883 Parser.eatToEndOfStatement(); 8884 return false; 8885 } 8886 8887 StackOffset = CE->getValue(); 8888 8889 if (getLexer().isNot(AsmToken::Comma)) { 8890 Error(getLexer().getLoc(), "expected comma"); 8891 Parser.eatToEndOfStatement(); 8892 return false; 8893 } 8894 Parser.Lex(); 8895 8896 SmallVector<uint8_t, 16> Opcodes; 8897 for (;;) { 8898 const MCExpr *OE; 8899 8900 SMLoc OpcodeLoc = getLexer().getLoc(); 8901 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) { 8902 Error(OpcodeLoc, "expected opcode expression"); 8903 Parser.eatToEndOfStatement(); 8904 return false; 8905 } 8906 8907 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE); 8908 if (!OC) { 8909 Error(OpcodeLoc, "opcode value must be a constant"); 8910 Parser.eatToEndOfStatement(); 8911 return false; 8912 } 8913 8914 const int64_t Opcode = OC->getValue(); 8915 if (Opcode & ~0xff) { 8916 Error(OpcodeLoc, "invalid opcode"); 8917 Parser.eatToEndOfStatement(); 8918 return false; 8919 } 8920 8921 Opcodes.push_back(uint8_t(Opcode)); 8922 8923 if (getLexer().is(AsmToken::EndOfStatement)) 8924 break; 8925 8926 if (getLexer().isNot(AsmToken::Comma)) { 8927 Error(getLexer().getLoc(), "unexpected token in directive"); 8928 Parser.eatToEndOfStatement(); 8929 return false; 8930 } 8931 8932 Parser.Lex(); 8933 } 8934 8935 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes); 8936 8937 Parser.Lex(); 8938 return false; 8939 } 8940 8941 /// parseDirectiveTLSDescSeq 8942 /// ::= .tlsdescseq tls-variable 8943 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) { 8944 if (getLexer().isNot(AsmToken::Identifier)) { 8945 TokError("expected variable after '.tlsdescseq' directive"); 8946 Parser.eatToEndOfStatement(); 8947 return false; 8948 } 8949 8950 const MCSymbolRefExpr *SRE = 8951 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(), 8952 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext()); 8953 Lex(); 8954 8955 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8956 Error(Parser.getTok().getLoc(), "unexpected token"); 8957 Parser.eatToEndOfStatement(); 8958 return false; 8959 } 8960 8961 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE); 8962 return false; 8963 } 8964 8965 /// parseDirectiveMovSP 8966 /// ::= .movsp reg [, #offset] 8967 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) { 8968 if (!UC.hasFnStart()) { 8969 Parser.eatToEndOfStatement(); 8970 Error(L, ".fnstart must precede .movsp directives"); 8971 return false; 8972 } 8973 if (UC.getFPReg() != ARM::SP) { 8974 Parser.eatToEndOfStatement(); 8975 Error(L, "unexpected .movsp directive"); 8976 return false; 8977 } 8978 8979 SMLoc SPRegLoc = Parser.getTok().getLoc(); 8980 int SPReg = tryParseRegister(); 8981 if (SPReg == -1) { 8982 Parser.eatToEndOfStatement(); 8983 Error(SPRegLoc, "register expected"); 8984 return false; 8985 } 8986 8987 if (SPReg == ARM::SP || SPReg == ARM::PC) { 8988 Parser.eatToEndOfStatement(); 8989 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive"); 8990 return false; 8991 } 8992 8993 int64_t Offset = 0; 8994 if (Parser.getTok().is(AsmToken::Comma)) { 8995 Parser.Lex(); 8996 8997 if (Parser.getTok().isNot(AsmToken::Hash)) { 8998 Error(Parser.getTok().getLoc(), "expected #constant"); 8999 Parser.eatToEndOfStatement(); 9000 return false; 9001 } 9002 Parser.Lex(); 9003 9004 const MCExpr *OffsetExpr; 9005 SMLoc OffsetLoc = Parser.getTok().getLoc(); 9006 if (Parser.parseExpression(OffsetExpr)) { 9007 Parser.eatToEndOfStatement(); 9008 Error(OffsetLoc, "malformed offset expression"); 9009 return false; 9010 } 9011 9012 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9013 if (!CE) { 9014 Parser.eatToEndOfStatement(); 9015 Error(OffsetLoc, "offset must be an immediate constant"); 9016 return false; 9017 } 9018 9019 Offset = CE->getValue(); 9020 } 9021 9022 getTargetStreamer().emitMovSP(SPReg, Offset); 9023 UC.saveFPReg(SPReg); 9024 9025 return false; 9026 } 9027 9028 /// parseDirectiveObjectArch 9029 /// ::= .object_arch name 9030 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) { 9031 if (getLexer().isNot(AsmToken::Identifier)) { 9032 Error(getLexer().getLoc(), "unexpected token"); 9033 Parser.eatToEndOfStatement(); 9034 return false; 9035 } 9036 9037 StringRef Arch = Parser.getTok().getString(); 9038 SMLoc ArchLoc = Parser.getTok().getLoc(); 9039 getLexer().Lex(); 9040 9041 unsigned ID = StringSwitch<unsigned>(Arch) 9042 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \ 9043 .Case(NAME, ARM::ID) 9044 #define ARM_ARCH_ALIAS(NAME, ID) \ 9045 .Case(NAME, ARM::ID) 9046 #include "MCTargetDesc/ARMArchName.def" 9047 #undef ARM_ARCH_NAME 9048 #undef ARM_ARCH_ALIAS 9049 .Default(ARM::INVALID_ARCH); 9050 9051 if (ID == ARM::INVALID_ARCH) { 9052 Error(ArchLoc, "unknown architecture '" + Arch + "'"); 9053 Parser.eatToEndOfStatement(); 9054 return false; 9055 } 9056 9057 getTargetStreamer().emitObjectArch(ID); 9058 9059 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9060 Error(getLexer().getLoc(), "unexpected token"); 9061 Parser.eatToEndOfStatement(); 9062 } 9063 9064 return false; 9065 } 9066 9067 /// parseDirectiveAlign 9068 /// ::= .align 9069 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) { 9070 // NOTE: if this is not the end of the statement, fall back to the target 9071 // agnostic handling for this directive which will correctly handle this. 9072 if (getLexer().isNot(AsmToken::EndOfStatement)) 9073 return true; 9074 9075 // '.align' is target specifically handled to mean 2**2 byte alignment. 9076 if (getStreamer().getCurrentSection().first->UseCodeAlign()) 9077 getStreamer().EmitCodeAlignment(4, 0); 9078 else 9079 getStreamer().EmitValueToAlignment(4, 0, 1, 0); 9080 9081 return false; 9082 } 9083 9084 /// Force static initialization. 9085 extern "C" void LLVMInitializeARMAsmParser() { 9086 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 9087 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 9088 } 9089 9090 #define GET_REGISTER_MATCHER 9091 #define GET_SUBTARGET_FEATURE_NAME 9092 #define GET_MATCHER_IMPLEMENTATION 9093 #include "ARMGenAsmMatcher.inc" 9094 9095 static const struct ExtMapEntry { 9096 const char *Extension; 9097 const unsigned ArchCheck; 9098 const uint64_t Features; 9099 } Extensions[] = { 9100 { "crc", Feature_HasV8, ARM::FeatureCRC }, 9101 { "crypto", Feature_HasV8, 9102 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 }, 9103 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 }, 9104 { "idiv", Feature_HasV7 | Feature_IsNotMClass, 9105 ARM::FeatureHWDiv | ARM::FeatureHWDivARM }, 9106 // FIXME: iWMMXT not supported 9107 { "iwmmxt", Feature_None, 0 }, 9108 // FIXME: iWMMXT2 not supported 9109 { "iwmmxt2", Feature_None, 0 }, 9110 // FIXME: Maverick not supported 9111 { "maverick", Feature_None, 0 }, 9112 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP }, 9113 // FIXME: ARMv6-m OS Extensions feature not checked 9114 { "os", Feature_None, 0 }, 9115 // FIXME: Also available in ARMv6-K 9116 { "sec", Feature_HasV7, ARM::FeatureTrustZone }, 9117 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 }, 9118 // FIXME: Only available in A-class, isel not predicated 9119 { "virt", Feature_HasV7, ARM::FeatureVirtualization }, 9120 // FIXME: xscale not supported 9121 { "xscale", Feature_None, 0 }, 9122 }; 9123 9124 /// parseDirectiveArchExtension 9125 /// ::= .arch_extension [no]feature 9126 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { 9127 if (getLexer().isNot(AsmToken::Identifier)) { 9128 Error(getLexer().getLoc(), "unexpected token"); 9129 Parser.eatToEndOfStatement(); 9130 return false; 9131 } 9132 9133 StringRef Extension = Parser.getTok().getString(); 9134 SMLoc ExtLoc = Parser.getTok().getLoc(); 9135 getLexer().Lex(); 9136 9137 bool EnableFeature = true; 9138 if (Extension.startswith_lower("no")) { 9139 EnableFeature = false; 9140 Extension = Extension.substr(2); 9141 } 9142 9143 for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) { 9144 if (Extensions[EI].Extension != Extension) 9145 continue; 9146 9147 unsigned FB = getAvailableFeatures(); 9148 if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) { 9149 Error(ExtLoc, "architectural extension '" + Extension + "' is not " 9150 "allowed for the current base architecture"); 9151 return false; 9152 } 9153 9154 if (!Extensions[EI].Features) 9155 report_fatal_error("unsupported architectural extension: " + Extension); 9156 9157 if (EnableFeature) 9158 FB |= ComputeAvailableFeatures(Extensions[EI].Features); 9159 else 9160 FB &= ~ComputeAvailableFeatures(Extensions[EI].Features); 9161 9162 setAvailableFeatures(FB); 9163 return false; 9164 } 9165 9166 Error(ExtLoc, "unknown architectural extension: " + Extension); 9167 Parser.eatToEndOfStatement(); 9168 return false; 9169 } 9170 9171 // Define this matcher function after the auto-generated include so we 9172 // have the match class enum definitions. 9173 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp, 9174 unsigned Kind) { 9175 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp); 9176 // If the kind is a token for a literal immediate, check if our asm 9177 // operand matches. This is for InstAliases which have a fixed-value 9178 // immediate in the syntax. 9179 switch (Kind) { 9180 default: break; 9181 case MCK__35_0: 9182 if (Op->isImm()) 9183 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm())) 9184 if (CE->getValue() == 0) 9185 return Match_Success; 9186 break; 9187 case MCK_ARMSOImm: 9188 if (Op->isImm()) { 9189 const MCExpr *SOExpr = Op->getImm(); 9190 int64_t Value; 9191 if (!SOExpr->EvaluateAsAbsolute(Value)) 9192 return Match_Success; 9193 assert((Value >= INT32_MIN && Value <= INT32_MAX) && 9194 "expression value must be representiable in 32 bits"); 9195 } 9196 break; 9197 case MCK_GPRPair: 9198 if (Op->isReg() && 9199 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg())) 9200 return Match_Success; 9201 break; 9202 } 9203 return Match_InvalidOperand; 9204 } 9205