1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMBaseInfo.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMMCExpr.h" 13 #include "llvm/MC/MCParser/MCAsmLexer.h" 14 #include "llvm/MC/MCParser/MCAsmParser.h" 15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCStreamer.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCInstrDesc.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/MC/MCTargetAsmParser.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/SourceMgr.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include "llvm/ADT/BitVector.h" 30 #include "llvm/ADT/OwningPtr.h" 31 #include "llvm/ADT/STLExtras.h" 32 #include "llvm/ADT/SmallVector.h" 33 #include "llvm/ADT/StringSwitch.h" 34 #include "llvm/ADT/Twine.h" 35 36 using namespace llvm; 37 38 namespace { 39 40 class ARMOperand; 41 42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 43 44 class ARMAsmParser : public MCTargetAsmParser { 45 MCSubtargetInfo &STI; 46 MCAsmParser &Parser; 47 const MCRegisterInfo *MRI; 48 49 // Map of register aliases registers via the .req directive. 50 StringMap<unsigned> RegisterReqs; 51 52 struct { 53 ARMCC::CondCodes Cond; // Condition for IT block. 54 unsigned Mask:4; // Condition mask for instructions. 55 // Starting at first 1 (from lsb). 56 // '1' condition as indicated in IT. 57 // '0' inverse of condition (else). 58 // Count of instructions in IT block is 59 // 4 - trailingzeroes(mask) 60 61 bool FirstCond; // Explicit flag for when we're parsing the 62 // First instruction in the IT block. It's 63 // implied in the mask, so needs special 64 // handling. 65 66 unsigned CurPosition; // Current position in parsing of IT 67 // block. In range [0,3]. Initialized 68 // according to count of instructions in block. 69 // ~0U if no active IT block. 70 } ITState; 71 bool inITBlock() { return ITState.CurPosition != ~0U;} 72 void forwardITPosition() { 73 if (!inITBlock()) return; 74 // Move to the next instruction in the IT block, if there is one. If not, 75 // mark the block as done. 76 unsigned TZ = CountTrailingZeros_32(ITState.Mask); 77 if (++ITState.CurPosition == 5 - TZ) 78 ITState.CurPosition = ~0U; // Done with the IT block after this. 79 } 80 81 82 MCAsmParser &getParser() const { return Parser; } 83 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 84 85 bool Warning(SMLoc L, const Twine &Msg, 86 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 87 return Parser.Warning(L, Msg, Ranges); 88 } 89 bool Error(SMLoc L, const Twine &Msg, 90 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 91 return Parser.Error(L, Msg, Ranges); 92 } 93 94 int tryParseRegister(); 95 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 96 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 97 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 98 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 99 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 100 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 102 unsigned &ShiftAmount); 103 bool parseDirectiveWord(unsigned Size, SMLoc L); 104 bool parseDirectiveThumb(SMLoc L); 105 bool parseDirectiveARM(SMLoc L); 106 bool parseDirectiveThumbFunc(SMLoc L); 107 bool parseDirectiveCode(SMLoc L); 108 bool parseDirectiveSyntax(SMLoc L); 109 bool parseDirectiveReq(StringRef Name, SMLoc L); 110 bool parseDirectiveUnreq(SMLoc L); 111 bool parseDirectiveArch(SMLoc L); 112 bool parseDirectiveEabiAttr(SMLoc L); 113 114 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 115 bool &CarrySetting, unsigned &ProcessorIMod, 116 StringRef &ITMask); 117 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 118 bool &CanAcceptPredicationCode); 119 120 bool isThumb() const { 121 // FIXME: Can tablegen auto-generate this? 122 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 123 } 124 bool isThumbOne() const { 125 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 126 } 127 bool isThumbTwo() const { 128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 129 } 130 bool hasV6Ops() const { 131 return STI.getFeatureBits() & ARM::HasV6Ops; 132 } 133 bool hasV7Ops() const { 134 return STI.getFeatureBits() & ARM::HasV7Ops; 135 } 136 void SwitchMode() { 137 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 138 setAvailableFeatures(FB); 139 } 140 bool isMClass() const { 141 return STI.getFeatureBits() & ARM::FeatureMClass; 142 } 143 144 /// @name Auto-generated Match Functions 145 /// { 146 147 #define GET_ASSEMBLER_HEADER 148 #include "ARMGenAsmMatcher.inc" 149 150 /// } 151 152 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 153 OperandMatchResultTy parseCoprocNumOperand( 154 SmallVectorImpl<MCParsedAsmOperand*>&); 155 OperandMatchResultTy parseCoprocRegOperand( 156 SmallVectorImpl<MCParsedAsmOperand*>&); 157 OperandMatchResultTy parseCoprocOptionOperand( 158 SmallVectorImpl<MCParsedAsmOperand*>&); 159 OperandMatchResultTy parseMemBarrierOptOperand( 160 SmallVectorImpl<MCParsedAsmOperand*>&); 161 OperandMatchResultTy parseProcIFlagsOperand( 162 SmallVectorImpl<MCParsedAsmOperand*>&); 163 OperandMatchResultTy parseMSRMaskOperand( 164 SmallVectorImpl<MCParsedAsmOperand*>&); 165 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 166 StringRef Op, int Low, int High); 167 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 168 return parsePKHImm(O, "lsl", 0, 31); 169 } 170 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 171 return parsePKHImm(O, "asr", 1, 32); 172 } 173 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 174 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 175 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 176 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 177 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 178 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 179 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 180 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 181 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); 182 183 // Asm Match Converter Methods 184 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 185 const SmallVectorImpl<MCParsedAsmOperand*> &); 186 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 187 const SmallVectorImpl<MCParsedAsmOperand*> &); 188 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 189 const SmallVectorImpl<MCParsedAsmOperand*> &); 190 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 191 const SmallVectorImpl<MCParsedAsmOperand*> &); 192 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 193 const SmallVectorImpl<MCParsedAsmOperand*> &); 194 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 195 const SmallVectorImpl<MCParsedAsmOperand*> &); 196 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 197 const SmallVectorImpl<MCParsedAsmOperand*> &); 198 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 199 const SmallVectorImpl<MCParsedAsmOperand*> &); 200 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 201 const SmallVectorImpl<MCParsedAsmOperand*> &); 202 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 203 const SmallVectorImpl<MCParsedAsmOperand*> &); 204 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 205 const SmallVectorImpl<MCParsedAsmOperand*> &); 206 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 207 const SmallVectorImpl<MCParsedAsmOperand*> &); 208 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 209 const SmallVectorImpl<MCParsedAsmOperand*> &); 210 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 211 const SmallVectorImpl<MCParsedAsmOperand*> &); 212 bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 213 const SmallVectorImpl<MCParsedAsmOperand*> &); 214 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 215 const SmallVectorImpl<MCParsedAsmOperand*> &); 216 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 217 const SmallVectorImpl<MCParsedAsmOperand*> &); 218 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 219 const SmallVectorImpl<MCParsedAsmOperand*> &); 220 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 221 const SmallVectorImpl<MCParsedAsmOperand*> &); 222 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 223 const SmallVectorImpl<MCParsedAsmOperand*> &); 224 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 225 const SmallVectorImpl<MCParsedAsmOperand*> &); 226 227 bool validateInstruction(MCInst &Inst, 228 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 229 bool processInstruction(MCInst &Inst, 230 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 231 bool shouldOmitCCOutOperand(StringRef Mnemonic, 232 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 233 234 public: 235 enum ARMMatchResultTy { 236 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 237 Match_RequiresNotITBlock, 238 Match_RequiresV6, 239 Match_RequiresThumb2 240 }; 241 242 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 243 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 244 MCAsmParserExtension::Initialize(_Parser); 245 246 // Cache the MCRegisterInfo. 247 MRI = &getContext().getRegisterInfo(); 248 249 // Initialize the set of available features. 250 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 251 252 // Not in an ITBlock to start with. 253 ITState.CurPosition = ~0U; 254 } 255 256 // Implementation of the MCTargetAsmParser interface: 257 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 258 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 259 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 260 bool ParseDirective(AsmToken DirectiveID); 261 262 unsigned checkTargetMatchPredicate(MCInst &Inst); 263 264 bool MatchAndEmitInstruction(SMLoc IDLoc, 265 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 266 MCStreamer &Out); 267 }; 268 } // end anonymous namespace 269 270 namespace { 271 272 /// ARMOperand - Instances of this class represent a parsed ARM machine 273 /// instruction. 274 class ARMOperand : public MCParsedAsmOperand { 275 enum KindTy { 276 k_CondCode, 277 k_CCOut, 278 k_ITCondMask, 279 k_CoprocNum, 280 k_CoprocReg, 281 k_CoprocOption, 282 k_Immediate, 283 k_MemBarrierOpt, 284 k_Memory, 285 k_PostIndexRegister, 286 k_MSRMask, 287 k_ProcIFlags, 288 k_VectorIndex, 289 k_Register, 290 k_RegisterList, 291 k_DPRRegisterList, 292 k_SPRRegisterList, 293 k_VectorList, 294 k_VectorListAllLanes, 295 k_VectorListIndexed, 296 k_ShiftedRegister, 297 k_ShiftedImmediate, 298 k_ShifterImmediate, 299 k_RotateImmediate, 300 k_BitfieldDescriptor, 301 k_Token 302 } Kind; 303 304 SMLoc StartLoc, EndLoc; 305 SmallVector<unsigned, 8> Registers; 306 307 union { 308 struct { 309 ARMCC::CondCodes Val; 310 } CC; 311 312 struct { 313 unsigned Val; 314 } Cop; 315 316 struct { 317 unsigned Val; 318 } CoprocOption; 319 320 struct { 321 unsigned Mask:4; 322 } ITMask; 323 324 struct { 325 ARM_MB::MemBOpt Val; 326 } MBOpt; 327 328 struct { 329 ARM_PROC::IFlags Val; 330 } IFlags; 331 332 struct { 333 unsigned Val; 334 } MMask; 335 336 struct { 337 const char *Data; 338 unsigned Length; 339 } Tok; 340 341 struct { 342 unsigned RegNum; 343 } Reg; 344 345 // A vector register list is a sequential list of 1 to 4 registers. 346 struct { 347 unsigned RegNum; 348 unsigned Count; 349 unsigned LaneIndex; 350 bool isDoubleSpaced; 351 } VectorList; 352 353 struct { 354 unsigned Val; 355 } VectorIndex; 356 357 struct { 358 const MCExpr *Val; 359 } Imm; 360 361 /// Combined record for all forms of ARM address expressions. 362 struct { 363 unsigned BaseRegNum; 364 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 365 // was specified. 366 const MCConstantExpr *OffsetImm; // Offset immediate value 367 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 368 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 369 unsigned ShiftImm; // shift for OffsetReg. 370 unsigned Alignment; // 0 = no alignment specified 371 // n = alignment in bytes (2, 4, 8, 16, or 32) 372 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 373 } Memory; 374 375 struct { 376 unsigned RegNum; 377 bool isAdd; 378 ARM_AM::ShiftOpc ShiftTy; 379 unsigned ShiftImm; 380 } PostIdxReg; 381 382 struct { 383 bool isASR; 384 unsigned Imm; 385 } ShifterImm; 386 struct { 387 ARM_AM::ShiftOpc ShiftTy; 388 unsigned SrcReg; 389 unsigned ShiftReg; 390 unsigned ShiftImm; 391 } RegShiftedReg; 392 struct { 393 ARM_AM::ShiftOpc ShiftTy; 394 unsigned SrcReg; 395 unsigned ShiftImm; 396 } RegShiftedImm; 397 struct { 398 unsigned Imm; 399 } RotImm; 400 struct { 401 unsigned LSB; 402 unsigned Width; 403 } Bitfield; 404 }; 405 406 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 407 public: 408 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 409 Kind = o.Kind; 410 StartLoc = o.StartLoc; 411 EndLoc = o.EndLoc; 412 switch (Kind) { 413 case k_CondCode: 414 CC = o.CC; 415 break; 416 case k_ITCondMask: 417 ITMask = o.ITMask; 418 break; 419 case k_Token: 420 Tok = o.Tok; 421 break; 422 case k_CCOut: 423 case k_Register: 424 Reg = o.Reg; 425 break; 426 case k_RegisterList: 427 case k_DPRRegisterList: 428 case k_SPRRegisterList: 429 Registers = o.Registers; 430 break; 431 case k_VectorList: 432 case k_VectorListAllLanes: 433 case k_VectorListIndexed: 434 VectorList = o.VectorList; 435 break; 436 case k_CoprocNum: 437 case k_CoprocReg: 438 Cop = o.Cop; 439 break; 440 case k_CoprocOption: 441 CoprocOption = o.CoprocOption; 442 break; 443 case k_Immediate: 444 Imm = o.Imm; 445 break; 446 case k_MemBarrierOpt: 447 MBOpt = o.MBOpt; 448 break; 449 case k_Memory: 450 Memory = o.Memory; 451 break; 452 case k_PostIndexRegister: 453 PostIdxReg = o.PostIdxReg; 454 break; 455 case k_MSRMask: 456 MMask = o.MMask; 457 break; 458 case k_ProcIFlags: 459 IFlags = o.IFlags; 460 break; 461 case k_ShifterImmediate: 462 ShifterImm = o.ShifterImm; 463 break; 464 case k_ShiftedRegister: 465 RegShiftedReg = o.RegShiftedReg; 466 break; 467 case k_ShiftedImmediate: 468 RegShiftedImm = o.RegShiftedImm; 469 break; 470 case k_RotateImmediate: 471 RotImm = o.RotImm; 472 break; 473 case k_BitfieldDescriptor: 474 Bitfield = o.Bitfield; 475 break; 476 case k_VectorIndex: 477 VectorIndex = o.VectorIndex; 478 break; 479 } 480 } 481 482 /// getStartLoc - Get the location of the first token of this operand. 483 SMLoc getStartLoc() const { return StartLoc; } 484 /// getEndLoc - Get the location of the last token of this operand. 485 SMLoc getEndLoc() const { return EndLoc; } 486 487 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 488 489 ARMCC::CondCodes getCondCode() const { 490 assert(Kind == k_CondCode && "Invalid access!"); 491 return CC.Val; 492 } 493 494 unsigned getCoproc() const { 495 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 496 return Cop.Val; 497 } 498 499 StringRef getToken() const { 500 assert(Kind == k_Token && "Invalid access!"); 501 return StringRef(Tok.Data, Tok.Length); 502 } 503 504 unsigned getReg() const { 505 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 506 return Reg.RegNum; 507 } 508 509 const SmallVectorImpl<unsigned> &getRegList() const { 510 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 511 Kind == k_SPRRegisterList) && "Invalid access!"); 512 return Registers; 513 } 514 515 const MCExpr *getImm() const { 516 assert(isImm() && "Invalid access!"); 517 return Imm.Val; 518 } 519 520 unsigned getVectorIndex() const { 521 assert(Kind == k_VectorIndex && "Invalid access!"); 522 return VectorIndex.Val; 523 } 524 525 ARM_MB::MemBOpt getMemBarrierOpt() const { 526 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 527 return MBOpt.Val; 528 } 529 530 ARM_PROC::IFlags getProcIFlags() const { 531 assert(Kind == k_ProcIFlags && "Invalid access!"); 532 return IFlags.Val; 533 } 534 535 unsigned getMSRMask() const { 536 assert(Kind == k_MSRMask && "Invalid access!"); 537 return MMask.Val; 538 } 539 540 bool isCoprocNum() const { return Kind == k_CoprocNum; } 541 bool isCoprocReg() const { return Kind == k_CoprocReg; } 542 bool isCoprocOption() const { return Kind == k_CoprocOption; } 543 bool isCondCode() const { return Kind == k_CondCode; } 544 bool isCCOut() const { return Kind == k_CCOut; } 545 bool isITMask() const { return Kind == k_ITCondMask; } 546 bool isITCondCode() const { return Kind == k_CondCode; } 547 bool isImm() const { return Kind == k_Immediate; } 548 bool isFPImm() const { 549 if (!isImm()) return false; 550 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 551 if (!CE) return false; 552 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 553 return Val != -1; 554 } 555 bool isFBits16() const { 556 if (!isImm()) return false; 557 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 558 if (!CE) return false; 559 int64_t Value = CE->getValue(); 560 return Value >= 0 && Value <= 16; 561 } 562 bool isFBits32() const { 563 if (!isImm()) return false; 564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 565 if (!CE) return false; 566 int64_t Value = CE->getValue(); 567 return Value >= 1 && Value <= 32; 568 } 569 bool isImm8s4() const { 570 if (!isImm()) return false; 571 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 572 if (!CE) return false; 573 int64_t Value = CE->getValue(); 574 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 575 } 576 bool isImm0_1020s4() const { 577 if (!isImm()) return false; 578 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 579 if (!CE) return false; 580 int64_t Value = CE->getValue(); 581 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 582 } 583 bool isImm0_508s4() const { 584 if (!isImm()) return false; 585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 586 if (!CE) return false; 587 int64_t Value = CE->getValue(); 588 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 589 } 590 bool isImm0_508s4Neg() const { 591 if (!isImm()) return false; 592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 593 if (!CE) return false; 594 int64_t Value = -CE->getValue(); 595 // explicitly exclude zero. we want that to use the normal 0_508 version. 596 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 597 } 598 bool isImm0_255() const { 599 if (!isImm()) return false; 600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 601 if (!CE) return false; 602 int64_t Value = CE->getValue(); 603 return Value >= 0 && Value < 256; 604 } 605 bool isImm0_4095() const { 606 if (!isImm()) return false; 607 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 608 if (!CE) return false; 609 int64_t Value = CE->getValue(); 610 return Value >= 0 && Value < 4096; 611 } 612 bool isImm0_4095Neg() const { 613 if (!isImm()) return false; 614 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 615 if (!CE) return false; 616 int64_t Value = -CE->getValue(); 617 return Value > 0 && Value < 4096; 618 } 619 bool isImm0_1() const { 620 if (!isImm()) return false; 621 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 622 if (!CE) return false; 623 int64_t Value = CE->getValue(); 624 return Value >= 0 && Value < 2; 625 } 626 bool isImm0_3() const { 627 if (!isImm()) return false; 628 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 629 if (!CE) return false; 630 int64_t Value = CE->getValue(); 631 return Value >= 0 && Value < 4; 632 } 633 bool isImm0_7() const { 634 if (!isImm()) return false; 635 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 636 if (!CE) return false; 637 int64_t Value = CE->getValue(); 638 return Value >= 0 && Value < 8; 639 } 640 bool isImm0_15() const { 641 if (!isImm()) return false; 642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 643 if (!CE) return false; 644 int64_t Value = CE->getValue(); 645 return Value >= 0 && Value < 16; 646 } 647 bool isImm0_31() const { 648 if (!isImm()) return false; 649 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 650 if (!CE) return false; 651 int64_t Value = CE->getValue(); 652 return Value >= 0 && Value < 32; 653 } 654 bool isImm0_63() const { 655 if (!isImm()) return false; 656 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 657 if (!CE) return false; 658 int64_t Value = CE->getValue(); 659 return Value >= 0 && Value < 64; 660 } 661 bool isImm8() const { 662 if (!isImm()) return false; 663 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 664 if (!CE) return false; 665 int64_t Value = CE->getValue(); 666 return Value == 8; 667 } 668 bool isImm16() const { 669 if (!isImm()) return false; 670 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 671 if (!CE) return false; 672 int64_t Value = CE->getValue(); 673 return Value == 16; 674 } 675 bool isImm32() const { 676 if (!isImm()) return false; 677 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 678 if (!CE) return false; 679 int64_t Value = CE->getValue(); 680 return Value == 32; 681 } 682 bool isShrImm8() const { 683 if (!isImm()) return false; 684 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 685 if (!CE) return false; 686 int64_t Value = CE->getValue(); 687 return Value > 0 && Value <= 8; 688 } 689 bool isShrImm16() const { 690 if (!isImm()) return false; 691 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 692 if (!CE) return false; 693 int64_t Value = CE->getValue(); 694 return Value > 0 && Value <= 16; 695 } 696 bool isShrImm32() const { 697 if (!isImm()) return false; 698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 699 if (!CE) return false; 700 int64_t Value = CE->getValue(); 701 return Value > 0 && Value <= 32; 702 } 703 bool isShrImm64() const { 704 if (!isImm()) return false; 705 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 706 if (!CE) return false; 707 int64_t Value = CE->getValue(); 708 return Value > 0 && Value <= 64; 709 } 710 bool isImm1_7() const { 711 if (!isImm()) return false; 712 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 713 if (!CE) return false; 714 int64_t Value = CE->getValue(); 715 return Value > 0 && Value < 8; 716 } 717 bool isImm1_15() const { 718 if (!isImm()) return false; 719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 720 if (!CE) return false; 721 int64_t Value = CE->getValue(); 722 return Value > 0 && Value < 16; 723 } 724 bool isImm1_31() const { 725 if (!isImm()) return false; 726 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 727 if (!CE) return false; 728 int64_t Value = CE->getValue(); 729 return Value > 0 && Value < 32; 730 } 731 bool isImm1_16() const { 732 if (!isImm()) return false; 733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 734 if (!CE) return false; 735 int64_t Value = CE->getValue(); 736 return Value > 0 && Value < 17; 737 } 738 bool isImm1_32() const { 739 if (!isImm()) return false; 740 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 741 if (!CE) return false; 742 int64_t Value = CE->getValue(); 743 return Value > 0 && Value < 33; 744 } 745 bool isImm0_32() const { 746 if (!isImm()) return false; 747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 748 if (!CE) return false; 749 int64_t Value = CE->getValue(); 750 return Value >= 0 && Value < 33; 751 } 752 bool isImm0_65535() const { 753 if (!isImm()) return false; 754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 755 if (!CE) return false; 756 int64_t Value = CE->getValue(); 757 return Value >= 0 && Value < 65536; 758 } 759 bool isImm0_65535Expr() const { 760 if (!isImm()) return false; 761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 762 // If it's not a constant expression, it'll generate a fixup and be 763 // handled later. 764 if (!CE) return true; 765 int64_t Value = CE->getValue(); 766 return Value >= 0 && Value < 65536; 767 } 768 bool isImm24bit() const { 769 if (!isImm()) return false; 770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 771 if (!CE) return false; 772 int64_t Value = CE->getValue(); 773 return Value >= 0 && Value <= 0xffffff; 774 } 775 bool isImmThumbSR() const { 776 if (!isImm()) return false; 777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 778 if (!CE) return false; 779 int64_t Value = CE->getValue(); 780 return Value > 0 && Value < 33; 781 } 782 bool isPKHLSLImm() const { 783 if (!isImm()) return false; 784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 785 if (!CE) return false; 786 int64_t Value = CE->getValue(); 787 return Value >= 0 && Value < 32; 788 } 789 bool isPKHASRImm() const { 790 if (!isImm()) return false; 791 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 792 if (!CE) return false; 793 int64_t Value = CE->getValue(); 794 return Value > 0 && Value <= 32; 795 } 796 bool isARMSOImm() const { 797 if (!isImm()) return false; 798 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 799 if (!CE) return false; 800 int64_t Value = CE->getValue(); 801 return ARM_AM::getSOImmVal(Value) != -1; 802 } 803 bool isARMSOImmNot() const { 804 if (!isImm()) return false; 805 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 806 if (!CE) return false; 807 int64_t Value = CE->getValue(); 808 return ARM_AM::getSOImmVal(~Value) != -1; 809 } 810 bool isARMSOImmNeg() const { 811 if (!isImm()) return false; 812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 813 if (!CE) return false; 814 int64_t Value = CE->getValue(); 815 // Only use this when not representable as a plain so_imm. 816 return ARM_AM::getSOImmVal(Value) == -1 && 817 ARM_AM::getSOImmVal(-Value) != -1; 818 } 819 bool isT2SOImm() const { 820 if (!isImm()) return false; 821 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 822 if (!CE) return false; 823 int64_t Value = CE->getValue(); 824 return ARM_AM::getT2SOImmVal(Value) != -1; 825 } 826 bool isT2SOImmNot() const { 827 if (!isImm()) return false; 828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 829 if (!CE) return false; 830 int64_t Value = CE->getValue(); 831 return ARM_AM::getT2SOImmVal(~Value) != -1; 832 } 833 bool isT2SOImmNeg() const { 834 if (!isImm()) return false; 835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 836 if (!CE) return false; 837 int64_t Value = CE->getValue(); 838 // Only use this when not representable as a plain so_imm. 839 return ARM_AM::getT2SOImmVal(Value) == -1 && 840 ARM_AM::getT2SOImmVal(-Value) != -1; 841 } 842 bool isSetEndImm() const { 843 if (!isImm()) return false; 844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 845 if (!CE) return false; 846 int64_t Value = CE->getValue(); 847 return Value == 1 || Value == 0; 848 } 849 bool isReg() const { return Kind == k_Register; } 850 bool isRegList() const { return Kind == k_RegisterList; } 851 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 852 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 853 bool isToken() const { return Kind == k_Token; } 854 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 855 bool isMemory() const { return Kind == k_Memory; } 856 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 857 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 858 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 859 bool isRotImm() const { return Kind == k_RotateImmediate; } 860 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 861 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 862 bool isPostIdxReg() const { 863 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 864 } 865 bool isMemNoOffset(bool alignOK = false) const { 866 if (!isMemory()) 867 return false; 868 // No offset of any kind. 869 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 870 (alignOK || Memory.Alignment == 0); 871 } 872 bool isMemPCRelImm12() const { 873 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 874 return false; 875 // Base register must be PC. 876 if (Memory.BaseRegNum != ARM::PC) 877 return false; 878 // Immediate offset in range [-4095, 4095]. 879 if (!Memory.OffsetImm) return true; 880 int64_t Val = Memory.OffsetImm->getValue(); 881 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 882 } 883 bool isAlignedMemory() const { 884 return isMemNoOffset(true); 885 } 886 bool isAddrMode2() const { 887 if (!isMemory() || Memory.Alignment != 0) return false; 888 // Check for register offset. 889 if (Memory.OffsetRegNum) return true; 890 // Immediate offset in range [-4095, 4095]. 891 if (!Memory.OffsetImm) return true; 892 int64_t Val = Memory.OffsetImm->getValue(); 893 return Val > -4096 && Val < 4096; 894 } 895 bool isAM2OffsetImm() const { 896 if (!isImm()) return false; 897 // Immediate offset in range [-4095, 4095]. 898 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 899 if (!CE) return false; 900 int64_t Val = CE->getValue(); 901 return Val > -4096 && Val < 4096; 902 } 903 bool isAddrMode3() const { 904 // If we have an immediate that's not a constant, treat it as a label 905 // reference needing a fixup. If it is a constant, it's something else 906 // and we reject it. 907 if (isImm() && !isa<MCConstantExpr>(getImm())) 908 return true; 909 if (!isMemory() || Memory.Alignment != 0) return false; 910 // No shifts are legal for AM3. 911 if (Memory.ShiftType != ARM_AM::no_shift) return false; 912 // Check for register offset. 913 if (Memory.OffsetRegNum) return true; 914 // Immediate offset in range [-255, 255]. 915 if (!Memory.OffsetImm) return true; 916 int64_t Val = Memory.OffsetImm->getValue(); 917 // The #-0 offset is encoded as INT32_MIN, and we have to check 918 // for this too. 919 return (Val > -256 && Val < 256) || Val == INT32_MIN; 920 } 921 bool isAM3Offset() const { 922 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 923 return false; 924 if (Kind == k_PostIndexRegister) 925 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 926 // Immediate offset in range [-255, 255]. 927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 928 if (!CE) return false; 929 int64_t Val = CE->getValue(); 930 // Special case, #-0 is INT32_MIN. 931 return (Val > -256 && Val < 256) || Val == INT32_MIN; 932 } 933 bool isAddrMode5() const { 934 // If we have an immediate that's not a constant, treat it as a label 935 // reference needing a fixup. If it is a constant, it's something else 936 // and we reject it. 937 if (isImm() && !isa<MCConstantExpr>(getImm())) 938 return true; 939 if (!isMemory() || Memory.Alignment != 0) return false; 940 // Check for register offset. 941 if (Memory.OffsetRegNum) return false; 942 // Immediate offset in range [-1020, 1020] and a multiple of 4. 943 if (!Memory.OffsetImm) return true; 944 int64_t Val = Memory.OffsetImm->getValue(); 945 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 946 Val == INT32_MIN; 947 } 948 bool isMemTBB() const { 949 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 950 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 951 return false; 952 return true; 953 } 954 bool isMemTBH() const { 955 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 956 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 957 Memory.Alignment != 0 ) 958 return false; 959 return true; 960 } 961 bool isMemRegOffset() const { 962 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 963 return false; 964 return true; 965 } 966 bool isT2MemRegOffset() const { 967 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 968 Memory.Alignment != 0) 969 return false; 970 // Only lsl #{0, 1, 2, 3} allowed. 971 if (Memory.ShiftType == ARM_AM::no_shift) 972 return true; 973 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 974 return false; 975 return true; 976 } 977 bool isMemThumbRR() const { 978 // Thumb reg+reg addressing is simple. Just two registers, a base and 979 // an offset. No shifts, negations or any other complicating factors. 980 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 981 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 982 return false; 983 return isARMLowRegister(Memory.BaseRegNum) && 984 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 985 } 986 bool isMemThumbRIs4() const { 987 if (!isMemory() || Memory.OffsetRegNum != 0 || 988 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 989 return false; 990 // Immediate offset, multiple of 4 in range [0, 124]. 991 if (!Memory.OffsetImm) return true; 992 int64_t Val = Memory.OffsetImm->getValue(); 993 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 994 } 995 bool isMemThumbRIs2() const { 996 if (!isMemory() || Memory.OffsetRegNum != 0 || 997 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 998 return false; 999 // Immediate offset, multiple of 4 in range [0, 62]. 1000 if (!Memory.OffsetImm) return true; 1001 int64_t Val = Memory.OffsetImm->getValue(); 1002 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1003 } 1004 bool isMemThumbRIs1() const { 1005 if (!isMemory() || Memory.OffsetRegNum != 0 || 1006 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1007 return false; 1008 // Immediate offset in range [0, 31]. 1009 if (!Memory.OffsetImm) return true; 1010 int64_t Val = Memory.OffsetImm->getValue(); 1011 return Val >= 0 && Val <= 31; 1012 } 1013 bool isMemThumbSPI() const { 1014 if (!isMemory() || Memory.OffsetRegNum != 0 || 1015 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1016 return false; 1017 // Immediate offset, multiple of 4 in range [0, 1020]. 1018 if (!Memory.OffsetImm) return true; 1019 int64_t Val = Memory.OffsetImm->getValue(); 1020 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1021 } 1022 bool isMemImm8s4Offset() const { 1023 // If we have an immediate that's not a constant, treat it as a label 1024 // reference needing a fixup. If it is a constant, it's something else 1025 // and we reject it. 1026 if (isImm() && !isa<MCConstantExpr>(getImm())) 1027 return true; 1028 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1029 return false; 1030 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1031 if (!Memory.OffsetImm) return true; 1032 int64_t Val = Memory.OffsetImm->getValue(); 1033 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; 1034 } 1035 bool isMemImm0_1020s4Offset() const { 1036 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1037 return false; 1038 // Immediate offset a multiple of 4 in range [0, 1020]. 1039 if (!Memory.OffsetImm) return true; 1040 int64_t Val = Memory.OffsetImm->getValue(); 1041 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1042 } 1043 bool isMemImm8Offset() const { 1044 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1045 return false; 1046 // Base reg of PC isn't allowed for these encodings. 1047 if (Memory.BaseRegNum == ARM::PC) return false; 1048 // Immediate offset in range [-255, 255]. 1049 if (!Memory.OffsetImm) return true; 1050 int64_t Val = Memory.OffsetImm->getValue(); 1051 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1052 } 1053 bool isMemPosImm8Offset() const { 1054 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1055 return false; 1056 // Immediate offset in range [0, 255]. 1057 if (!Memory.OffsetImm) return true; 1058 int64_t Val = Memory.OffsetImm->getValue(); 1059 return Val >= 0 && Val < 256; 1060 } 1061 bool isMemNegImm8Offset() const { 1062 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1063 return false; 1064 // Base reg of PC isn't allowed for these encodings. 1065 if (Memory.BaseRegNum == ARM::PC) return false; 1066 // Immediate offset in range [-255, -1]. 1067 if (!Memory.OffsetImm) return false; 1068 int64_t Val = Memory.OffsetImm->getValue(); 1069 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1070 } 1071 bool isMemUImm12Offset() const { 1072 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1073 return false; 1074 // Immediate offset in range [0, 4095]. 1075 if (!Memory.OffsetImm) return true; 1076 int64_t Val = Memory.OffsetImm->getValue(); 1077 return (Val >= 0 && Val < 4096); 1078 } 1079 bool isMemImm12Offset() const { 1080 // If we have an immediate that's not a constant, treat it as a label 1081 // reference needing a fixup. If it is a constant, it's something else 1082 // and we reject it. 1083 if (isImm() && !isa<MCConstantExpr>(getImm())) 1084 return true; 1085 1086 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1087 return false; 1088 // Immediate offset in range [-4095, 4095]. 1089 if (!Memory.OffsetImm) return true; 1090 int64_t Val = Memory.OffsetImm->getValue(); 1091 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1092 } 1093 bool isPostIdxImm8() const { 1094 if (!isImm()) return false; 1095 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1096 if (!CE) return false; 1097 int64_t Val = CE->getValue(); 1098 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1099 } 1100 bool isPostIdxImm8s4() const { 1101 if (!isImm()) return false; 1102 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1103 if (!CE) return false; 1104 int64_t Val = CE->getValue(); 1105 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1106 (Val == INT32_MIN); 1107 } 1108 1109 bool isMSRMask() const { return Kind == k_MSRMask; } 1110 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1111 1112 // NEON operands. 1113 bool isSingleSpacedVectorList() const { 1114 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1115 } 1116 bool isDoubleSpacedVectorList() const { 1117 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1118 } 1119 bool isVecListOneD() const { 1120 if (!isSingleSpacedVectorList()) return false; 1121 return VectorList.Count == 1; 1122 } 1123 1124 bool isVecListDPair() const { 1125 if (!isSingleSpacedVectorList()) return false; 1126 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1127 .contains(VectorList.RegNum)); 1128 } 1129 1130 bool isVecListThreeD() const { 1131 if (!isSingleSpacedVectorList()) return false; 1132 return VectorList.Count == 3; 1133 } 1134 1135 bool isVecListFourD() const { 1136 if (!isSingleSpacedVectorList()) return false; 1137 return VectorList.Count == 4; 1138 } 1139 1140 bool isVecListDPairSpaced() const { 1141 if (isSingleSpacedVectorList()) return false; 1142 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1143 .contains(VectorList.RegNum)); 1144 } 1145 1146 bool isVecListThreeQ() const { 1147 if (!isDoubleSpacedVectorList()) return false; 1148 return VectorList.Count == 3; 1149 } 1150 1151 bool isVecListFourQ() const { 1152 if (!isDoubleSpacedVectorList()) return false; 1153 return VectorList.Count == 4; 1154 } 1155 1156 bool isSingleSpacedVectorAllLanes() const { 1157 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1158 } 1159 bool isDoubleSpacedVectorAllLanes() const { 1160 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1161 } 1162 bool isVecListOneDAllLanes() const { 1163 if (!isSingleSpacedVectorAllLanes()) return false; 1164 return VectorList.Count == 1; 1165 } 1166 1167 bool isVecListDPairAllLanes() const { 1168 if (!isSingleSpacedVectorAllLanes()) return false; 1169 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1170 .contains(VectorList.RegNum)); 1171 } 1172 1173 bool isVecListDPairSpacedAllLanes() const { 1174 if (!isDoubleSpacedVectorAllLanes()) return false; 1175 return VectorList.Count == 2; 1176 } 1177 1178 bool isVecListThreeDAllLanes() const { 1179 if (!isSingleSpacedVectorAllLanes()) return false; 1180 return VectorList.Count == 3; 1181 } 1182 1183 bool isVecListThreeQAllLanes() const { 1184 if (!isDoubleSpacedVectorAllLanes()) return false; 1185 return VectorList.Count == 3; 1186 } 1187 1188 bool isVecListFourDAllLanes() const { 1189 if (!isSingleSpacedVectorAllLanes()) return false; 1190 return VectorList.Count == 4; 1191 } 1192 1193 bool isVecListFourQAllLanes() const { 1194 if (!isDoubleSpacedVectorAllLanes()) return false; 1195 return VectorList.Count == 4; 1196 } 1197 1198 bool isSingleSpacedVectorIndexed() const { 1199 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1200 } 1201 bool isDoubleSpacedVectorIndexed() const { 1202 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1203 } 1204 bool isVecListOneDByteIndexed() const { 1205 if (!isSingleSpacedVectorIndexed()) return false; 1206 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1207 } 1208 1209 bool isVecListOneDHWordIndexed() const { 1210 if (!isSingleSpacedVectorIndexed()) return false; 1211 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1212 } 1213 1214 bool isVecListOneDWordIndexed() const { 1215 if (!isSingleSpacedVectorIndexed()) return false; 1216 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1217 } 1218 1219 bool isVecListTwoDByteIndexed() const { 1220 if (!isSingleSpacedVectorIndexed()) return false; 1221 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1222 } 1223 1224 bool isVecListTwoDHWordIndexed() const { 1225 if (!isSingleSpacedVectorIndexed()) return false; 1226 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1227 } 1228 1229 bool isVecListTwoQWordIndexed() const { 1230 if (!isDoubleSpacedVectorIndexed()) return false; 1231 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1232 } 1233 1234 bool isVecListTwoQHWordIndexed() const { 1235 if (!isDoubleSpacedVectorIndexed()) return false; 1236 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1237 } 1238 1239 bool isVecListTwoDWordIndexed() const { 1240 if (!isSingleSpacedVectorIndexed()) return false; 1241 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1242 } 1243 1244 bool isVecListThreeDByteIndexed() const { 1245 if (!isSingleSpacedVectorIndexed()) return false; 1246 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1247 } 1248 1249 bool isVecListThreeDHWordIndexed() const { 1250 if (!isSingleSpacedVectorIndexed()) return false; 1251 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1252 } 1253 1254 bool isVecListThreeQWordIndexed() const { 1255 if (!isDoubleSpacedVectorIndexed()) return false; 1256 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1257 } 1258 1259 bool isVecListThreeQHWordIndexed() const { 1260 if (!isDoubleSpacedVectorIndexed()) return false; 1261 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1262 } 1263 1264 bool isVecListThreeDWordIndexed() const { 1265 if (!isSingleSpacedVectorIndexed()) return false; 1266 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1267 } 1268 1269 bool isVecListFourDByteIndexed() const { 1270 if (!isSingleSpacedVectorIndexed()) return false; 1271 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1272 } 1273 1274 bool isVecListFourDHWordIndexed() const { 1275 if (!isSingleSpacedVectorIndexed()) return false; 1276 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1277 } 1278 1279 bool isVecListFourQWordIndexed() const { 1280 if (!isDoubleSpacedVectorIndexed()) return false; 1281 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1282 } 1283 1284 bool isVecListFourQHWordIndexed() const { 1285 if (!isDoubleSpacedVectorIndexed()) return false; 1286 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1287 } 1288 1289 bool isVecListFourDWordIndexed() const { 1290 if (!isSingleSpacedVectorIndexed()) return false; 1291 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1292 } 1293 1294 bool isVectorIndex8() const { 1295 if (Kind != k_VectorIndex) return false; 1296 return VectorIndex.Val < 8; 1297 } 1298 bool isVectorIndex16() const { 1299 if (Kind != k_VectorIndex) return false; 1300 return VectorIndex.Val < 4; 1301 } 1302 bool isVectorIndex32() const { 1303 if (Kind != k_VectorIndex) return false; 1304 return VectorIndex.Val < 2; 1305 } 1306 1307 bool isNEONi8splat() const { 1308 if (!isImm()) return false; 1309 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1310 // Must be a constant. 1311 if (!CE) return false; 1312 int64_t Value = CE->getValue(); 1313 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1314 // value. 1315 return Value >= 0 && Value < 256; 1316 } 1317 1318 bool isNEONi16splat() const { 1319 if (!isImm()) return false; 1320 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1321 // Must be a constant. 1322 if (!CE) return false; 1323 int64_t Value = CE->getValue(); 1324 // i16 value in the range [0,255] or [0x0100, 0xff00] 1325 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1326 } 1327 1328 bool isNEONi32splat() const { 1329 if (!isImm()) return false; 1330 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1331 // Must be a constant. 1332 if (!CE) return false; 1333 int64_t Value = CE->getValue(); 1334 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1335 return (Value >= 0 && Value < 256) || 1336 (Value >= 0x0100 && Value <= 0xff00) || 1337 (Value >= 0x010000 && Value <= 0xff0000) || 1338 (Value >= 0x01000000 && Value <= 0xff000000); 1339 } 1340 1341 bool isNEONi32vmov() const { 1342 if (!isImm()) return false; 1343 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1344 // Must be a constant. 1345 if (!CE) return false; 1346 int64_t Value = CE->getValue(); 1347 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1348 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1349 return (Value >= 0 && Value < 256) || 1350 (Value >= 0x0100 && Value <= 0xff00) || 1351 (Value >= 0x010000 && Value <= 0xff0000) || 1352 (Value >= 0x01000000 && Value <= 0xff000000) || 1353 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1354 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1355 } 1356 bool isNEONi32vmovNeg() const { 1357 if (!isImm()) return false; 1358 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1359 // Must be a constant. 1360 if (!CE) return false; 1361 int64_t Value = ~CE->getValue(); 1362 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1363 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1364 return (Value >= 0 && Value < 256) || 1365 (Value >= 0x0100 && Value <= 0xff00) || 1366 (Value >= 0x010000 && Value <= 0xff0000) || 1367 (Value >= 0x01000000 && Value <= 0xff000000) || 1368 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1369 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1370 } 1371 1372 bool isNEONi64splat() const { 1373 if (!isImm()) return false; 1374 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1375 // Must be a constant. 1376 if (!CE) return false; 1377 uint64_t Value = CE->getValue(); 1378 // i64 value with each byte being either 0 or 0xff. 1379 for (unsigned i = 0; i < 8; ++i) 1380 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1381 return true; 1382 } 1383 1384 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1385 // Add as immediates when possible. Null MCExpr = 0. 1386 if (Expr == 0) 1387 Inst.addOperand(MCOperand::CreateImm(0)); 1388 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1389 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1390 else 1391 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1392 } 1393 1394 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1395 assert(N == 2 && "Invalid number of operands!"); 1396 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1397 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1398 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1399 } 1400 1401 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1402 assert(N == 1 && "Invalid number of operands!"); 1403 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1404 } 1405 1406 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1407 assert(N == 1 && "Invalid number of operands!"); 1408 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1409 } 1410 1411 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1412 assert(N == 1 && "Invalid number of operands!"); 1413 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1414 } 1415 1416 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1417 assert(N == 1 && "Invalid number of operands!"); 1418 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1419 } 1420 1421 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1422 assert(N == 1 && "Invalid number of operands!"); 1423 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1424 } 1425 1426 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1427 assert(N == 1 && "Invalid number of operands!"); 1428 Inst.addOperand(MCOperand::CreateReg(getReg())); 1429 } 1430 1431 void addRegOperands(MCInst &Inst, unsigned N) const { 1432 assert(N == 1 && "Invalid number of operands!"); 1433 Inst.addOperand(MCOperand::CreateReg(getReg())); 1434 } 1435 1436 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1437 assert(N == 3 && "Invalid number of operands!"); 1438 assert(isRegShiftedReg() && 1439 "addRegShiftedRegOperands() on non RegShiftedReg!"); 1440 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1441 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1442 Inst.addOperand(MCOperand::CreateImm( 1443 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1444 } 1445 1446 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1447 assert(N == 2 && "Invalid number of operands!"); 1448 assert(isRegShiftedImm() && 1449 "addRegShiftedImmOperands() on non RegShiftedImm!"); 1450 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1451 // Shift of #32 is encoded as 0 where permitted 1452 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1453 Inst.addOperand(MCOperand::CreateImm( 1454 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1455 } 1456 1457 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1458 assert(N == 1 && "Invalid number of operands!"); 1459 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1460 ShifterImm.Imm)); 1461 } 1462 1463 void addRegListOperands(MCInst &Inst, unsigned N) const { 1464 assert(N == 1 && "Invalid number of operands!"); 1465 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1466 for (SmallVectorImpl<unsigned>::const_iterator 1467 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1468 Inst.addOperand(MCOperand::CreateReg(*I)); 1469 } 1470 1471 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1472 addRegListOperands(Inst, N); 1473 } 1474 1475 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1476 addRegListOperands(Inst, N); 1477 } 1478 1479 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1480 assert(N == 1 && "Invalid number of operands!"); 1481 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1482 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1483 } 1484 1485 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1486 assert(N == 1 && "Invalid number of operands!"); 1487 // Munge the lsb/width into a bitfield mask. 1488 unsigned lsb = Bitfield.LSB; 1489 unsigned width = Bitfield.Width; 1490 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1491 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1492 (32 - (lsb + width))); 1493 Inst.addOperand(MCOperand::CreateImm(Mask)); 1494 } 1495 1496 void addImmOperands(MCInst &Inst, unsigned N) const { 1497 assert(N == 1 && "Invalid number of operands!"); 1498 addExpr(Inst, getImm()); 1499 } 1500 1501 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1502 assert(N == 1 && "Invalid number of operands!"); 1503 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1504 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1505 } 1506 1507 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1508 assert(N == 1 && "Invalid number of operands!"); 1509 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1510 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1511 } 1512 1513 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1514 assert(N == 1 && "Invalid number of operands!"); 1515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1516 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1517 Inst.addOperand(MCOperand::CreateImm(Val)); 1518 } 1519 1520 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1521 assert(N == 1 && "Invalid number of operands!"); 1522 // FIXME: We really want to scale the value here, but the LDRD/STRD 1523 // instruction don't encode operands that way yet. 1524 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1525 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1526 } 1527 1528 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1529 assert(N == 1 && "Invalid number of operands!"); 1530 // The immediate is scaled by four in the encoding and is stored 1531 // in the MCInst as such. Lop off the low two bits here. 1532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1533 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1534 } 1535 1536 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1537 assert(N == 1 && "Invalid number of operands!"); 1538 // The immediate is scaled by four in the encoding and is stored 1539 // in the MCInst as such. Lop off the low two bits here. 1540 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1541 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1542 } 1543 1544 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1545 assert(N == 1 && "Invalid number of operands!"); 1546 // The immediate is scaled by four in the encoding and is stored 1547 // in the MCInst as such. Lop off the low two bits here. 1548 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1549 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1550 } 1551 1552 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1553 assert(N == 1 && "Invalid number of operands!"); 1554 // The constant encodes as the immediate-1, and we store in the instruction 1555 // the bits as encoded, so subtract off one here. 1556 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1557 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1558 } 1559 1560 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1561 assert(N == 1 && "Invalid number of operands!"); 1562 // The constant encodes as the immediate-1, and we store in the instruction 1563 // the bits as encoded, so subtract off one here. 1564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1565 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1566 } 1567 1568 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1569 assert(N == 1 && "Invalid number of operands!"); 1570 // The constant encodes as the immediate, except for 32, which encodes as 1571 // zero. 1572 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1573 unsigned Imm = CE->getValue(); 1574 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1575 } 1576 1577 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1578 assert(N == 1 && "Invalid number of operands!"); 1579 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1580 // the instruction as well. 1581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1582 int Val = CE->getValue(); 1583 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1584 } 1585 1586 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1587 assert(N == 1 && "Invalid number of operands!"); 1588 // The operand is actually a t2_so_imm, but we have its bitwise 1589 // negation in the assembly source, so twiddle it here. 1590 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1591 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1592 } 1593 1594 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1595 assert(N == 1 && "Invalid number of operands!"); 1596 // The operand is actually a t2_so_imm, but we have its 1597 // negation in the assembly source, so twiddle it here. 1598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1599 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1600 } 1601 1602 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1603 assert(N == 1 && "Invalid number of operands!"); 1604 // The operand is actually an imm0_4095, but we have its 1605 // negation in the assembly source, so twiddle it here. 1606 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1607 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1608 } 1609 1610 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1611 assert(N == 1 && "Invalid number of operands!"); 1612 // The operand is actually a so_imm, but we have its bitwise 1613 // negation in the assembly source, so twiddle it here. 1614 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1615 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1616 } 1617 1618 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1619 assert(N == 1 && "Invalid number of operands!"); 1620 // The operand is actually a so_imm, but we have its 1621 // negation in the assembly source, so twiddle it here. 1622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1623 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1624 } 1625 1626 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1627 assert(N == 1 && "Invalid number of operands!"); 1628 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1629 } 1630 1631 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1632 assert(N == 1 && "Invalid number of operands!"); 1633 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1634 } 1635 1636 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1637 assert(N == 1 && "Invalid number of operands!"); 1638 int32_t Imm = Memory.OffsetImm->getValue(); 1639 // FIXME: Handle #-0 1640 if (Imm == INT32_MIN) Imm = 0; 1641 Inst.addOperand(MCOperand::CreateImm(Imm)); 1642 } 1643 1644 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1645 assert(N == 2 && "Invalid number of operands!"); 1646 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1647 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1648 } 1649 1650 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1651 assert(N == 3 && "Invalid number of operands!"); 1652 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1653 if (!Memory.OffsetRegNum) { 1654 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1655 // Special case for #-0 1656 if (Val == INT32_MIN) Val = 0; 1657 if (Val < 0) Val = -Val; 1658 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1659 } else { 1660 // For register offset, we encode the shift type and negation flag 1661 // here. 1662 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1663 Memory.ShiftImm, Memory.ShiftType); 1664 } 1665 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1666 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1667 Inst.addOperand(MCOperand::CreateImm(Val)); 1668 } 1669 1670 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1671 assert(N == 2 && "Invalid number of operands!"); 1672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1673 assert(CE && "non-constant AM2OffsetImm operand!"); 1674 int32_t Val = CE->getValue(); 1675 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1676 // Special case for #-0 1677 if (Val == INT32_MIN) Val = 0; 1678 if (Val < 0) Val = -Val; 1679 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1680 Inst.addOperand(MCOperand::CreateReg(0)); 1681 Inst.addOperand(MCOperand::CreateImm(Val)); 1682 } 1683 1684 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1685 assert(N == 3 && "Invalid number of operands!"); 1686 // If we have an immediate that's not a constant, treat it as a label 1687 // reference needing a fixup. If it is a constant, it's something else 1688 // and we reject it. 1689 if (isImm()) { 1690 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1691 Inst.addOperand(MCOperand::CreateReg(0)); 1692 Inst.addOperand(MCOperand::CreateImm(0)); 1693 return; 1694 } 1695 1696 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1697 if (!Memory.OffsetRegNum) { 1698 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1699 // Special case for #-0 1700 if (Val == INT32_MIN) Val = 0; 1701 if (Val < 0) Val = -Val; 1702 Val = ARM_AM::getAM3Opc(AddSub, Val); 1703 } else { 1704 // For register offset, we encode the shift type and negation flag 1705 // here. 1706 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1707 } 1708 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1709 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1710 Inst.addOperand(MCOperand::CreateImm(Val)); 1711 } 1712 1713 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1714 assert(N == 2 && "Invalid number of operands!"); 1715 if (Kind == k_PostIndexRegister) { 1716 int32_t Val = 1717 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1718 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1719 Inst.addOperand(MCOperand::CreateImm(Val)); 1720 return; 1721 } 1722 1723 // Constant offset. 1724 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1725 int32_t Val = CE->getValue(); 1726 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1727 // Special case for #-0 1728 if (Val == INT32_MIN) Val = 0; 1729 if (Val < 0) Val = -Val; 1730 Val = ARM_AM::getAM3Opc(AddSub, Val); 1731 Inst.addOperand(MCOperand::CreateReg(0)); 1732 Inst.addOperand(MCOperand::CreateImm(Val)); 1733 } 1734 1735 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1736 assert(N == 2 && "Invalid number of operands!"); 1737 // If we have an immediate that's not a constant, treat it as a label 1738 // reference needing a fixup. If it is a constant, it's something else 1739 // and we reject it. 1740 if (isImm()) { 1741 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1742 Inst.addOperand(MCOperand::CreateImm(0)); 1743 return; 1744 } 1745 1746 // The lower two bits are always zero and as such are not encoded. 1747 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1748 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1749 // Special case for #-0 1750 if (Val == INT32_MIN) Val = 0; 1751 if (Val < 0) Val = -Val; 1752 Val = ARM_AM::getAM5Opc(AddSub, Val); 1753 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1754 Inst.addOperand(MCOperand::CreateImm(Val)); 1755 } 1756 1757 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1758 assert(N == 2 && "Invalid number of operands!"); 1759 // If we have an immediate that's not a constant, treat it as a label 1760 // reference needing a fixup. If it is a constant, it's something else 1761 // and we reject it. 1762 if (isImm()) { 1763 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1764 Inst.addOperand(MCOperand::CreateImm(0)); 1765 return; 1766 } 1767 1768 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1769 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1770 Inst.addOperand(MCOperand::CreateImm(Val)); 1771 } 1772 1773 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1774 assert(N == 2 && "Invalid number of operands!"); 1775 // The lower two bits are always zero and as such are not encoded. 1776 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1777 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1778 Inst.addOperand(MCOperand::CreateImm(Val)); 1779 } 1780 1781 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1782 assert(N == 2 && "Invalid number of operands!"); 1783 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1784 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1785 Inst.addOperand(MCOperand::CreateImm(Val)); 1786 } 1787 1788 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1789 addMemImm8OffsetOperands(Inst, N); 1790 } 1791 1792 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1793 addMemImm8OffsetOperands(Inst, N); 1794 } 1795 1796 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1797 assert(N == 2 && "Invalid number of operands!"); 1798 // If this is an immediate, it's a label reference. 1799 if (isImm()) { 1800 addExpr(Inst, getImm()); 1801 Inst.addOperand(MCOperand::CreateImm(0)); 1802 return; 1803 } 1804 1805 // Otherwise, it's a normal memory reg+offset. 1806 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1807 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1808 Inst.addOperand(MCOperand::CreateImm(Val)); 1809 } 1810 1811 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1812 assert(N == 2 && "Invalid number of operands!"); 1813 // If this is an immediate, it's a label reference. 1814 if (isImm()) { 1815 addExpr(Inst, getImm()); 1816 Inst.addOperand(MCOperand::CreateImm(0)); 1817 return; 1818 } 1819 1820 // Otherwise, it's a normal memory reg+offset. 1821 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1822 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1823 Inst.addOperand(MCOperand::CreateImm(Val)); 1824 } 1825 1826 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 1827 assert(N == 2 && "Invalid number of operands!"); 1828 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1829 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1830 } 1831 1832 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 1833 assert(N == 2 && "Invalid number of operands!"); 1834 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1835 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1836 } 1837 1838 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1839 assert(N == 3 && "Invalid number of operands!"); 1840 unsigned Val = 1841 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1842 Memory.ShiftImm, Memory.ShiftType); 1843 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1844 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1845 Inst.addOperand(MCOperand::CreateImm(Val)); 1846 } 1847 1848 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1849 assert(N == 3 && "Invalid number of operands!"); 1850 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1851 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1852 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1853 } 1854 1855 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1856 assert(N == 2 && "Invalid number of operands!"); 1857 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1858 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1859 } 1860 1861 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1862 assert(N == 2 && "Invalid number of operands!"); 1863 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1864 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1865 Inst.addOperand(MCOperand::CreateImm(Val)); 1866 } 1867 1868 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1869 assert(N == 2 && "Invalid number of operands!"); 1870 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1871 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1872 Inst.addOperand(MCOperand::CreateImm(Val)); 1873 } 1874 1875 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1876 assert(N == 2 && "Invalid number of operands!"); 1877 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1878 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1879 Inst.addOperand(MCOperand::CreateImm(Val)); 1880 } 1881 1882 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1883 assert(N == 2 && "Invalid number of operands!"); 1884 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1885 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1886 Inst.addOperand(MCOperand::CreateImm(Val)); 1887 } 1888 1889 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 1890 assert(N == 1 && "Invalid number of operands!"); 1891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1892 assert(CE && "non-constant post-idx-imm8 operand!"); 1893 int Imm = CE->getValue(); 1894 bool isAdd = Imm >= 0; 1895 if (Imm == INT32_MIN) Imm = 0; 1896 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 1897 Inst.addOperand(MCOperand::CreateImm(Imm)); 1898 } 1899 1900 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 1901 assert(N == 1 && "Invalid number of operands!"); 1902 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1903 assert(CE && "non-constant post-idx-imm8s4 operand!"); 1904 int Imm = CE->getValue(); 1905 bool isAdd = Imm >= 0; 1906 if (Imm == INT32_MIN) Imm = 0; 1907 // Immediate is scaled by 4. 1908 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 1909 Inst.addOperand(MCOperand::CreateImm(Imm)); 1910 } 1911 1912 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 1913 assert(N == 2 && "Invalid number of operands!"); 1914 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1915 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1916 } 1917 1918 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1919 assert(N == 2 && "Invalid number of operands!"); 1920 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1921 // The sign, shift type, and shift amount are encoded in a single operand 1922 // using the AM2 encoding helpers. 1923 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1924 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1925 PostIdxReg.ShiftTy); 1926 Inst.addOperand(MCOperand::CreateImm(Imm)); 1927 } 1928 1929 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1930 assert(N == 1 && "Invalid number of operands!"); 1931 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1932 } 1933 1934 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1935 assert(N == 1 && "Invalid number of operands!"); 1936 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1937 } 1938 1939 void addVecListOperands(MCInst &Inst, unsigned N) const { 1940 assert(N == 1 && "Invalid number of operands!"); 1941 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1942 } 1943 1944 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 1945 assert(N == 2 && "Invalid number of operands!"); 1946 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1947 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 1948 } 1949 1950 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1951 assert(N == 1 && "Invalid number of operands!"); 1952 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1953 } 1954 1955 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1956 assert(N == 1 && "Invalid number of operands!"); 1957 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1958 } 1959 1960 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1961 assert(N == 1 && "Invalid number of operands!"); 1962 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1963 } 1964 1965 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 1966 assert(N == 1 && "Invalid number of operands!"); 1967 // The immediate encodes the type of constant as well as the value. 1968 // Mask in that this is an i8 splat. 1969 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1970 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 1971 } 1972 1973 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 1974 assert(N == 1 && "Invalid number of operands!"); 1975 // The immediate encodes the type of constant as well as the value. 1976 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1977 unsigned Value = CE->getValue(); 1978 if (Value >= 256) 1979 Value = (Value >> 8) | 0xa00; 1980 else 1981 Value |= 0x800; 1982 Inst.addOperand(MCOperand::CreateImm(Value)); 1983 } 1984 1985 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 1986 assert(N == 1 && "Invalid number of operands!"); 1987 // The immediate encodes the type of constant as well as the value. 1988 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1989 unsigned Value = CE->getValue(); 1990 if (Value >= 256 && Value <= 0xff00) 1991 Value = (Value >> 8) | 0x200; 1992 else if (Value > 0xffff && Value <= 0xff0000) 1993 Value = (Value >> 16) | 0x400; 1994 else if (Value > 0xffffff) 1995 Value = (Value >> 24) | 0x600; 1996 Inst.addOperand(MCOperand::CreateImm(Value)); 1997 } 1998 1999 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2000 assert(N == 1 && "Invalid number of operands!"); 2001 // The immediate encodes the type of constant as well as the value. 2002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2003 unsigned Value = CE->getValue(); 2004 if (Value >= 256 && Value <= 0xffff) 2005 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2006 else if (Value > 0xffff && Value <= 0xffffff) 2007 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2008 else if (Value > 0xffffff) 2009 Value = (Value >> 24) | 0x600; 2010 Inst.addOperand(MCOperand::CreateImm(Value)); 2011 } 2012 2013 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2014 assert(N == 1 && "Invalid number of operands!"); 2015 // The immediate encodes the type of constant as well as the value. 2016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2017 unsigned Value = ~CE->getValue(); 2018 if (Value >= 256 && Value <= 0xffff) 2019 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2020 else if (Value > 0xffff && Value <= 0xffffff) 2021 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2022 else if (Value > 0xffffff) 2023 Value = (Value >> 24) | 0x600; 2024 Inst.addOperand(MCOperand::CreateImm(Value)); 2025 } 2026 2027 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2028 assert(N == 1 && "Invalid number of operands!"); 2029 // The immediate encodes the type of constant as well as the value. 2030 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2031 uint64_t Value = CE->getValue(); 2032 unsigned Imm = 0; 2033 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2034 Imm |= (Value & 1) << i; 2035 } 2036 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2037 } 2038 2039 virtual void print(raw_ostream &OS) const; 2040 2041 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2042 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2043 Op->ITMask.Mask = Mask; 2044 Op->StartLoc = S; 2045 Op->EndLoc = S; 2046 return Op; 2047 } 2048 2049 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2050 ARMOperand *Op = new ARMOperand(k_CondCode); 2051 Op->CC.Val = CC; 2052 Op->StartLoc = S; 2053 Op->EndLoc = S; 2054 return Op; 2055 } 2056 2057 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2058 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2059 Op->Cop.Val = CopVal; 2060 Op->StartLoc = S; 2061 Op->EndLoc = S; 2062 return Op; 2063 } 2064 2065 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2066 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2067 Op->Cop.Val = CopVal; 2068 Op->StartLoc = S; 2069 Op->EndLoc = S; 2070 return Op; 2071 } 2072 2073 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2074 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2075 Op->Cop.Val = Val; 2076 Op->StartLoc = S; 2077 Op->EndLoc = E; 2078 return Op; 2079 } 2080 2081 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2082 ARMOperand *Op = new ARMOperand(k_CCOut); 2083 Op->Reg.RegNum = RegNum; 2084 Op->StartLoc = S; 2085 Op->EndLoc = S; 2086 return Op; 2087 } 2088 2089 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2090 ARMOperand *Op = new ARMOperand(k_Token); 2091 Op->Tok.Data = Str.data(); 2092 Op->Tok.Length = Str.size(); 2093 Op->StartLoc = S; 2094 Op->EndLoc = S; 2095 return Op; 2096 } 2097 2098 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2099 ARMOperand *Op = new ARMOperand(k_Register); 2100 Op->Reg.RegNum = RegNum; 2101 Op->StartLoc = S; 2102 Op->EndLoc = E; 2103 return Op; 2104 } 2105 2106 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2107 unsigned SrcReg, 2108 unsigned ShiftReg, 2109 unsigned ShiftImm, 2110 SMLoc S, SMLoc E) { 2111 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2112 Op->RegShiftedReg.ShiftTy = ShTy; 2113 Op->RegShiftedReg.SrcReg = SrcReg; 2114 Op->RegShiftedReg.ShiftReg = ShiftReg; 2115 Op->RegShiftedReg.ShiftImm = ShiftImm; 2116 Op->StartLoc = S; 2117 Op->EndLoc = E; 2118 return Op; 2119 } 2120 2121 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2122 unsigned SrcReg, 2123 unsigned ShiftImm, 2124 SMLoc S, SMLoc E) { 2125 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2126 Op->RegShiftedImm.ShiftTy = ShTy; 2127 Op->RegShiftedImm.SrcReg = SrcReg; 2128 Op->RegShiftedImm.ShiftImm = ShiftImm; 2129 Op->StartLoc = S; 2130 Op->EndLoc = E; 2131 return Op; 2132 } 2133 2134 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2135 SMLoc S, SMLoc E) { 2136 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2137 Op->ShifterImm.isASR = isASR; 2138 Op->ShifterImm.Imm = Imm; 2139 Op->StartLoc = S; 2140 Op->EndLoc = E; 2141 return Op; 2142 } 2143 2144 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2145 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2146 Op->RotImm.Imm = Imm; 2147 Op->StartLoc = S; 2148 Op->EndLoc = E; 2149 return Op; 2150 } 2151 2152 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2153 SMLoc S, SMLoc E) { 2154 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2155 Op->Bitfield.LSB = LSB; 2156 Op->Bitfield.Width = Width; 2157 Op->StartLoc = S; 2158 Op->EndLoc = E; 2159 return Op; 2160 } 2161 2162 static ARMOperand * 2163 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2164 SMLoc StartLoc, SMLoc EndLoc) { 2165 KindTy Kind = k_RegisterList; 2166 2167 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 2168 Kind = k_DPRRegisterList; 2169 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2170 contains(Regs.front().first)) 2171 Kind = k_SPRRegisterList; 2172 2173 ARMOperand *Op = new ARMOperand(Kind); 2174 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 2175 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2176 Op->Registers.push_back(I->first); 2177 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2178 Op->StartLoc = StartLoc; 2179 Op->EndLoc = EndLoc; 2180 return Op; 2181 } 2182 2183 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2184 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2185 ARMOperand *Op = new ARMOperand(k_VectorList); 2186 Op->VectorList.RegNum = RegNum; 2187 Op->VectorList.Count = Count; 2188 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2189 Op->StartLoc = S; 2190 Op->EndLoc = E; 2191 return Op; 2192 } 2193 2194 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2195 bool isDoubleSpaced, 2196 SMLoc S, SMLoc E) { 2197 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2198 Op->VectorList.RegNum = RegNum; 2199 Op->VectorList.Count = Count; 2200 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2201 Op->StartLoc = S; 2202 Op->EndLoc = E; 2203 return Op; 2204 } 2205 2206 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2207 unsigned Index, 2208 bool isDoubleSpaced, 2209 SMLoc S, SMLoc E) { 2210 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2211 Op->VectorList.RegNum = RegNum; 2212 Op->VectorList.Count = Count; 2213 Op->VectorList.LaneIndex = Index; 2214 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2215 Op->StartLoc = S; 2216 Op->EndLoc = E; 2217 return Op; 2218 } 2219 2220 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2221 MCContext &Ctx) { 2222 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2223 Op->VectorIndex.Val = Idx; 2224 Op->StartLoc = S; 2225 Op->EndLoc = E; 2226 return Op; 2227 } 2228 2229 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2230 ARMOperand *Op = new ARMOperand(k_Immediate); 2231 Op->Imm.Val = Val; 2232 Op->StartLoc = S; 2233 Op->EndLoc = E; 2234 return Op; 2235 } 2236 2237 static ARMOperand *CreateMem(unsigned BaseRegNum, 2238 const MCConstantExpr *OffsetImm, 2239 unsigned OffsetRegNum, 2240 ARM_AM::ShiftOpc ShiftType, 2241 unsigned ShiftImm, 2242 unsigned Alignment, 2243 bool isNegative, 2244 SMLoc S, SMLoc E) { 2245 ARMOperand *Op = new ARMOperand(k_Memory); 2246 Op->Memory.BaseRegNum = BaseRegNum; 2247 Op->Memory.OffsetImm = OffsetImm; 2248 Op->Memory.OffsetRegNum = OffsetRegNum; 2249 Op->Memory.ShiftType = ShiftType; 2250 Op->Memory.ShiftImm = ShiftImm; 2251 Op->Memory.Alignment = Alignment; 2252 Op->Memory.isNegative = isNegative; 2253 Op->StartLoc = S; 2254 Op->EndLoc = E; 2255 return Op; 2256 } 2257 2258 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2259 ARM_AM::ShiftOpc ShiftTy, 2260 unsigned ShiftImm, 2261 SMLoc S, SMLoc E) { 2262 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2263 Op->PostIdxReg.RegNum = RegNum; 2264 Op->PostIdxReg.isAdd = isAdd; 2265 Op->PostIdxReg.ShiftTy = ShiftTy; 2266 Op->PostIdxReg.ShiftImm = ShiftImm; 2267 Op->StartLoc = S; 2268 Op->EndLoc = E; 2269 return Op; 2270 } 2271 2272 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2273 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2274 Op->MBOpt.Val = Opt; 2275 Op->StartLoc = S; 2276 Op->EndLoc = S; 2277 return Op; 2278 } 2279 2280 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2281 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2282 Op->IFlags.Val = IFlags; 2283 Op->StartLoc = S; 2284 Op->EndLoc = S; 2285 return Op; 2286 } 2287 2288 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2289 ARMOperand *Op = new ARMOperand(k_MSRMask); 2290 Op->MMask.Val = MMask; 2291 Op->StartLoc = S; 2292 Op->EndLoc = S; 2293 return Op; 2294 } 2295 }; 2296 2297 } // end anonymous namespace. 2298 2299 void ARMOperand::print(raw_ostream &OS) const { 2300 switch (Kind) { 2301 case k_CondCode: 2302 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2303 break; 2304 case k_CCOut: 2305 OS << "<ccout " << getReg() << ">"; 2306 break; 2307 case k_ITCondMask: { 2308 static const char *const MaskStr[] = { 2309 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2310 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2311 }; 2312 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2313 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2314 break; 2315 } 2316 case k_CoprocNum: 2317 OS << "<coprocessor number: " << getCoproc() << ">"; 2318 break; 2319 case k_CoprocReg: 2320 OS << "<coprocessor register: " << getCoproc() << ">"; 2321 break; 2322 case k_CoprocOption: 2323 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2324 break; 2325 case k_MSRMask: 2326 OS << "<mask: " << getMSRMask() << ">"; 2327 break; 2328 case k_Immediate: 2329 getImm()->print(OS); 2330 break; 2331 case k_MemBarrierOpt: 2332 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2333 break; 2334 case k_Memory: 2335 OS << "<memory " 2336 << " base:" << Memory.BaseRegNum; 2337 OS << ">"; 2338 break; 2339 case k_PostIndexRegister: 2340 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2341 << PostIdxReg.RegNum; 2342 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2343 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2344 << PostIdxReg.ShiftImm; 2345 OS << ">"; 2346 break; 2347 case k_ProcIFlags: { 2348 OS << "<ARM_PROC::"; 2349 unsigned IFlags = getProcIFlags(); 2350 for (int i=2; i >= 0; --i) 2351 if (IFlags & (1 << i)) 2352 OS << ARM_PROC::IFlagsToString(1 << i); 2353 OS << ">"; 2354 break; 2355 } 2356 case k_Register: 2357 OS << "<register " << getReg() << ">"; 2358 break; 2359 case k_ShifterImmediate: 2360 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2361 << " #" << ShifterImm.Imm << ">"; 2362 break; 2363 case k_ShiftedRegister: 2364 OS << "<so_reg_reg " 2365 << RegShiftedReg.SrcReg << " " 2366 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2367 << " " << RegShiftedReg.ShiftReg << ">"; 2368 break; 2369 case k_ShiftedImmediate: 2370 OS << "<so_reg_imm " 2371 << RegShiftedImm.SrcReg << " " 2372 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2373 << " #" << RegShiftedImm.ShiftImm << ">"; 2374 break; 2375 case k_RotateImmediate: 2376 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2377 break; 2378 case k_BitfieldDescriptor: 2379 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2380 << ", width: " << Bitfield.Width << ">"; 2381 break; 2382 case k_RegisterList: 2383 case k_DPRRegisterList: 2384 case k_SPRRegisterList: { 2385 OS << "<register_list "; 2386 2387 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2388 for (SmallVectorImpl<unsigned>::const_iterator 2389 I = RegList.begin(), E = RegList.end(); I != E; ) { 2390 OS << *I; 2391 if (++I < E) OS << ", "; 2392 } 2393 2394 OS << ">"; 2395 break; 2396 } 2397 case k_VectorList: 2398 OS << "<vector_list " << VectorList.Count << " * " 2399 << VectorList.RegNum << ">"; 2400 break; 2401 case k_VectorListAllLanes: 2402 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2403 << VectorList.RegNum << ">"; 2404 break; 2405 case k_VectorListIndexed: 2406 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2407 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2408 break; 2409 case k_Token: 2410 OS << "'" << getToken() << "'"; 2411 break; 2412 case k_VectorIndex: 2413 OS << "<vectorindex " << getVectorIndex() << ">"; 2414 break; 2415 } 2416 } 2417 2418 /// @name Auto-generated Match Functions 2419 /// { 2420 2421 static unsigned MatchRegisterName(StringRef Name); 2422 2423 /// } 2424 2425 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2426 SMLoc &StartLoc, SMLoc &EndLoc) { 2427 StartLoc = Parser.getTok().getLoc(); 2428 RegNo = tryParseRegister(); 2429 EndLoc = Parser.getTok().getLoc(); 2430 2431 return (RegNo == (unsigned)-1); 2432 } 2433 2434 /// Try to parse a register name. The token must be an Identifier when called, 2435 /// and if it is a register name the token is eaten and the register number is 2436 /// returned. Otherwise return -1. 2437 /// 2438 int ARMAsmParser::tryParseRegister() { 2439 const AsmToken &Tok = Parser.getTok(); 2440 if (Tok.isNot(AsmToken::Identifier)) return -1; 2441 2442 std::string lowerCase = Tok.getString().lower(); 2443 unsigned RegNum = MatchRegisterName(lowerCase); 2444 if (!RegNum) { 2445 RegNum = StringSwitch<unsigned>(lowerCase) 2446 .Case("r13", ARM::SP) 2447 .Case("r14", ARM::LR) 2448 .Case("r15", ARM::PC) 2449 .Case("ip", ARM::R12) 2450 // Additional register name aliases for 'gas' compatibility. 2451 .Case("a1", ARM::R0) 2452 .Case("a2", ARM::R1) 2453 .Case("a3", ARM::R2) 2454 .Case("a4", ARM::R3) 2455 .Case("v1", ARM::R4) 2456 .Case("v2", ARM::R5) 2457 .Case("v3", ARM::R6) 2458 .Case("v4", ARM::R7) 2459 .Case("v5", ARM::R8) 2460 .Case("v6", ARM::R9) 2461 .Case("v7", ARM::R10) 2462 .Case("v8", ARM::R11) 2463 .Case("sb", ARM::R9) 2464 .Case("sl", ARM::R10) 2465 .Case("fp", ARM::R11) 2466 .Default(0); 2467 } 2468 if (!RegNum) { 2469 // Check for aliases registered via .req. Canonicalize to lower case. 2470 // That's more consistent since register names are case insensitive, and 2471 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2472 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2473 // If no match, return failure. 2474 if (Entry == RegisterReqs.end()) 2475 return -1; 2476 Parser.Lex(); // Eat identifier token. 2477 return Entry->getValue(); 2478 } 2479 2480 Parser.Lex(); // Eat identifier token. 2481 2482 return RegNum; 2483 } 2484 2485 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2486 // If a recoverable error occurs, return 1. If an irrecoverable error 2487 // occurs, return -1. An irrecoverable error is one where tokens have been 2488 // consumed in the process of trying to parse the shifter (i.e., when it is 2489 // indeed a shifter operand, but malformed). 2490 int ARMAsmParser::tryParseShiftRegister( 2491 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2492 SMLoc S = Parser.getTok().getLoc(); 2493 const AsmToken &Tok = Parser.getTok(); 2494 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2495 2496 std::string lowerCase = Tok.getString().lower(); 2497 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2498 .Case("asl", ARM_AM::lsl) 2499 .Case("lsl", ARM_AM::lsl) 2500 .Case("lsr", ARM_AM::lsr) 2501 .Case("asr", ARM_AM::asr) 2502 .Case("ror", ARM_AM::ror) 2503 .Case("rrx", ARM_AM::rrx) 2504 .Default(ARM_AM::no_shift); 2505 2506 if (ShiftTy == ARM_AM::no_shift) 2507 return 1; 2508 2509 Parser.Lex(); // Eat the operator. 2510 2511 // The source register for the shift has already been added to the 2512 // operand list, so we need to pop it off and combine it into the shifted 2513 // register operand instead. 2514 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2515 if (!PrevOp->isReg()) 2516 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2517 int SrcReg = PrevOp->getReg(); 2518 int64_t Imm = 0; 2519 int ShiftReg = 0; 2520 if (ShiftTy == ARM_AM::rrx) { 2521 // RRX Doesn't have an explicit shift amount. The encoder expects 2522 // the shift register to be the same as the source register. Seems odd, 2523 // but OK. 2524 ShiftReg = SrcReg; 2525 } else { 2526 // Figure out if this is shifted by a constant or a register (for non-RRX). 2527 if (Parser.getTok().is(AsmToken::Hash) || 2528 Parser.getTok().is(AsmToken::Dollar)) { 2529 Parser.Lex(); // Eat hash. 2530 SMLoc ImmLoc = Parser.getTok().getLoc(); 2531 const MCExpr *ShiftExpr = 0; 2532 if (getParser().ParseExpression(ShiftExpr)) { 2533 Error(ImmLoc, "invalid immediate shift value"); 2534 return -1; 2535 } 2536 // The expression must be evaluatable as an immediate. 2537 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2538 if (!CE) { 2539 Error(ImmLoc, "invalid immediate shift value"); 2540 return -1; 2541 } 2542 // Range check the immediate. 2543 // lsl, ror: 0 <= imm <= 31 2544 // lsr, asr: 0 <= imm <= 32 2545 Imm = CE->getValue(); 2546 if (Imm < 0 || 2547 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2548 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2549 Error(ImmLoc, "immediate shift value out of range"); 2550 return -1; 2551 } 2552 // shift by zero is a nop. Always send it through as lsl. 2553 // ('as' compatibility) 2554 if (Imm == 0) 2555 ShiftTy = ARM_AM::lsl; 2556 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2557 ShiftReg = tryParseRegister(); 2558 SMLoc L = Parser.getTok().getLoc(); 2559 if (ShiftReg == -1) { 2560 Error (L, "expected immediate or register in shift operand"); 2561 return -1; 2562 } 2563 } else { 2564 Error (Parser.getTok().getLoc(), 2565 "expected immediate or register in shift operand"); 2566 return -1; 2567 } 2568 } 2569 2570 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2571 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2572 ShiftReg, Imm, 2573 S, Parser.getTok().getLoc())); 2574 else 2575 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2576 S, Parser.getTok().getLoc())); 2577 2578 return 0; 2579 } 2580 2581 2582 /// Try to parse a register name. The token must be an Identifier when called. 2583 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 2584 /// if there is a "writeback". 'true' if it's not a register. 2585 /// 2586 /// TODO this is likely to change to allow different register types and or to 2587 /// parse for a specific register type. 2588 bool ARMAsmParser:: 2589 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2590 SMLoc S = Parser.getTok().getLoc(); 2591 int RegNo = tryParseRegister(); 2592 if (RegNo == -1) 2593 return true; 2594 2595 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2596 2597 const AsmToken &ExclaimTok = Parser.getTok(); 2598 if (ExclaimTok.is(AsmToken::Exclaim)) { 2599 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2600 ExclaimTok.getLoc())); 2601 Parser.Lex(); // Eat exclaim token 2602 return false; 2603 } 2604 2605 // Also check for an index operand. This is only legal for vector registers, 2606 // but that'll get caught OK in operand matching, so we don't need to 2607 // explicitly filter everything else out here. 2608 if (Parser.getTok().is(AsmToken::LBrac)) { 2609 SMLoc SIdx = Parser.getTok().getLoc(); 2610 Parser.Lex(); // Eat left bracket token. 2611 2612 const MCExpr *ImmVal; 2613 if (getParser().ParseExpression(ImmVal)) 2614 return true; 2615 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2616 if (!MCE) 2617 return TokError("immediate value expected for vector index"); 2618 2619 SMLoc E = Parser.getTok().getLoc(); 2620 if (Parser.getTok().isNot(AsmToken::RBrac)) 2621 return Error(E, "']' expected"); 2622 2623 Parser.Lex(); // Eat right bracket token. 2624 2625 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2626 SIdx, E, 2627 getContext())); 2628 } 2629 2630 return false; 2631 } 2632 2633 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 2634 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2635 /// "c5", ... 2636 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2637 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2638 // but efficient. 2639 switch (Name.size()) { 2640 default: return -1; 2641 case 2: 2642 if (Name[0] != CoprocOp) 2643 return -1; 2644 switch (Name[1]) { 2645 default: return -1; 2646 case '0': return 0; 2647 case '1': return 1; 2648 case '2': return 2; 2649 case '3': return 3; 2650 case '4': return 4; 2651 case '5': return 5; 2652 case '6': return 6; 2653 case '7': return 7; 2654 case '8': return 8; 2655 case '9': return 9; 2656 } 2657 case 3: 2658 if (Name[0] != CoprocOp || Name[1] != '1') 2659 return -1; 2660 switch (Name[2]) { 2661 default: return -1; 2662 case '0': return 10; 2663 case '1': return 11; 2664 case '2': return 12; 2665 case '3': return 13; 2666 case '4': return 14; 2667 case '5': return 15; 2668 } 2669 } 2670 } 2671 2672 /// parseITCondCode - Try to parse a condition code for an IT instruction. 2673 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2674 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2675 SMLoc S = Parser.getTok().getLoc(); 2676 const AsmToken &Tok = Parser.getTok(); 2677 if (!Tok.is(AsmToken::Identifier)) 2678 return MatchOperand_NoMatch; 2679 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2680 .Case("eq", ARMCC::EQ) 2681 .Case("ne", ARMCC::NE) 2682 .Case("hs", ARMCC::HS) 2683 .Case("cs", ARMCC::HS) 2684 .Case("lo", ARMCC::LO) 2685 .Case("cc", ARMCC::LO) 2686 .Case("mi", ARMCC::MI) 2687 .Case("pl", ARMCC::PL) 2688 .Case("vs", ARMCC::VS) 2689 .Case("vc", ARMCC::VC) 2690 .Case("hi", ARMCC::HI) 2691 .Case("ls", ARMCC::LS) 2692 .Case("ge", ARMCC::GE) 2693 .Case("lt", ARMCC::LT) 2694 .Case("gt", ARMCC::GT) 2695 .Case("le", ARMCC::LE) 2696 .Case("al", ARMCC::AL) 2697 .Default(~0U); 2698 if (CC == ~0U) 2699 return MatchOperand_NoMatch; 2700 Parser.Lex(); // Eat the token. 2701 2702 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2703 2704 return MatchOperand_Success; 2705 } 2706 2707 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2708 /// token must be an Identifier when called, and if it is a coprocessor 2709 /// number, the token is eaten and the operand is added to the operand list. 2710 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2711 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2712 SMLoc S = Parser.getTok().getLoc(); 2713 const AsmToken &Tok = Parser.getTok(); 2714 if (Tok.isNot(AsmToken::Identifier)) 2715 return MatchOperand_NoMatch; 2716 2717 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2718 if (Num == -1) 2719 return MatchOperand_NoMatch; 2720 2721 Parser.Lex(); // Eat identifier token. 2722 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2723 return MatchOperand_Success; 2724 } 2725 2726 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2727 /// token must be an Identifier when called, and if it is a coprocessor 2728 /// number, the token is eaten and the operand is added to the operand list. 2729 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2730 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2731 SMLoc S = Parser.getTok().getLoc(); 2732 const AsmToken &Tok = Parser.getTok(); 2733 if (Tok.isNot(AsmToken::Identifier)) 2734 return MatchOperand_NoMatch; 2735 2736 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2737 if (Reg == -1) 2738 return MatchOperand_NoMatch; 2739 2740 Parser.Lex(); // Eat identifier token. 2741 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2742 return MatchOperand_Success; 2743 } 2744 2745 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2746 /// coproc_option : '{' imm0_255 '}' 2747 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2748 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2749 SMLoc S = Parser.getTok().getLoc(); 2750 2751 // If this isn't a '{', this isn't a coprocessor immediate operand. 2752 if (Parser.getTok().isNot(AsmToken::LCurly)) 2753 return MatchOperand_NoMatch; 2754 Parser.Lex(); // Eat the '{' 2755 2756 const MCExpr *Expr; 2757 SMLoc Loc = Parser.getTok().getLoc(); 2758 if (getParser().ParseExpression(Expr)) { 2759 Error(Loc, "illegal expression"); 2760 return MatchOperand_ParseFail; 2761 } 2762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2763 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2764 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2765 return MatchOperand_ParseFail; 2766 } 2767 int Val = CE->getValue(); 2768 2769 // Check for and consume the closing '}' 2770 if (Parser.getTok().isNot(AsmToken::RCurly)) 2771 return MatchOperand_ParseFail; 2772 SMLoc E = Parser.getTok().getLoc(); 2773 Parser.Lex(); // Eat the '}' 2774 2775 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2776 return MatchOperand_Success; 2777 } 2778 2779 // For register list parsing, we need to map from raw GPR register numbering 2780 // to the enumeration values. The enumeration values aren't sorted by 2781 // register number due to our using "sp", "lr" and "pc" as canonical names. 2782 static unsigned getNextRegister(unsigned Reg) { 2783 // If this is a GPR, we need to do it manually, otherwise we can rely 2784 // on the sort ordering of the enumeration since the other reg-classes 2785 // are sane. 2786 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2787 return Reg + 1; 2788 switch(Reg) { 2789 default: llvm_unreachable("Invalid GPR number!"); 2790 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2791 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2792 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2793 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2794 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2795 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2796 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2797 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2798 } 2799 } 2800 2801 // Return the low-subreg of a given Q register. 2802 static unsigned getDRegFromQReg(unsigned QReg) { 2803 switch (QReg) { 2804 default: llvm_unreachable("expected a Q register!"); 2805 case ARM::Q0: return ARM::D0; 2806 case ARM::Q1: return ARM::D2; 2807 case ARM::Q2: return ARM::D4; 2808 case ARM::Q3: return ARM::D6; 2809 case ARM::Q4: return ARM::D8; 2810 case ARM::Q5: return ARM::D10; 2811 case ARM::Q6: return ARM::D12; 2812 case ARM::Q7: return ARM::D14; 2813 case ARM::Q8: return ARM::D16; 2814 case ARM::Q9: return ARM::D18; 2815 case ARM::Q10: return ARM::D20; 2816 case ARM::Q11: return ARM::D22; 2817 case ARM::Q12: return ARM::D24; 2818 case ARM::Q13: return ARM::D26; 2819 case ARM::Q14: return ARM::D28; 2820 case ARM::Q15: return ARM::D30; 2821 } 2822 } 2823 2824 /// Parse a register list. 2825 bool ARMAsmParser:: 2826 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2827 assert(Parser.getTok().is(AsmToken::LCurly) && 2828 "Token is not a Left Curly Brace"); 2829 SMLoc S = Parser.getTok().getLoc(); 2830 Parser.Lex(); // Eat '{' token. 2831 SMLoc RegLoc = Parser.getTok().getLoc(); 2832 2833 // Check the first register in the list to see what register class 2834 // this is a list of. 2835 int Reg = tryParseRegister(); 2836 if (Reg == -1) 2837 return Error(RegLoc, "register expected"); 2838 2839 // The reglist instructions have at most 16 registers, so reserve 2840 // space for that many. 2841 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2842 2843 // Allow Q regs and just interpret them as the two D sub-registers. 2844 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2845 Reg = getDRegFromQReg(Reg); 2846 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2847 ++Reg; 2848 } 2849 const MCRegisterClass *RC; 2850 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2851 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2852 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2853 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2854 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2855 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2856 else 2857 return Error(RegLoc, "invalid register in register list"); 2858 2859 // Store the register. 2860 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2861 2862 // This starts immediately after the first register token in the list, 2863 // so we can see either a comma or a minus (range separator) as a legal 2864 // next token. 2865 while (Parser.getTok().is(AsmToken::Comma) || 2866 Parser.getTok().is(AsmToken::Minus)) { 2867 if (Parser.getTok().is(AsmToken::Minus)) { 2868 Parser.Lex(); // Eat the minus. 2869 SMLoc EndLoc = Parser.getTok().getLoc(); 2870 int EndReg = tryParseRegister(); 2871 if (EndReg == -1) 2872 return Error(EndLoc, "register expected"); 2873 // Allow Q regs and just interpret them as the two D sub-registers. 2874 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2875 EndReg = getDRegFromQReg(EndReg) + 1; 2876 // If the register is the same as the start reg, there's nothing 2877 // more to do. 2878 if (Reg == EndReg) 2879 continue; 2880 // The register must be in the same register class as the first. 2881 if (!RC->contains(EndReg)) 2882 return Error(EndLoc, "invalid register in register list"); 2883 // Ranges must go from low to high. 2884 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 2885 return Error(EndLoc, "bad range in register list"); 2886 2887 // Add all the registers in the range to the register list. 2888 while (Reg != EndReg) { 2889 Reg = getNextRegister(Reg); 2890 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2891 } 2892 continue; 2893 } 2894 Parser.Lex(); // Eat the comma. 2895 RegLoc = Parser.getTok().getLoc(); 2896 int OldReg = Reg; 2897 const AsmToken RegTok = Parser.getTok(); 2898 Reg = tryParseRegister(); 2899 if (Reg == -1) 2900 return Error(RegLoc, "register expected"); 2901 // Allow Q regs and just interpret them as the two D sub-registers. 2902 bool isQReg = false; 2903 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2904 Reg = getDRegFromQReg(Reg); 2905 isQReg = true; 2906 } 2907 // The register must be in the same register class as the first. 2908 if (!RC->contains(Reg)) 2909 return Error(RegLoc, "invalid register in register list"); 2910 // List must be monotonically increasing. 2911 if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) { 2912 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2913 Warning(RegLoc, "register list not in ascending order"); 2914 else 2915 return Error(RegLoc, "register list not in ascending order"); 2916 } 2917 if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) { 2918 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 2919 ") in register list"); 2920 continue; 2921 } 2922 // VFP register lists must also be contiguous. 2923 // It's OK to use the enumeration values directly here rather, as the 2924 // VFP register classes have the enum sorted properly. 2925 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2926 Reg != OldReg + 1) 2927 return Error(RegLoc, "non-contiguous register range"); 2928 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2929 if (isQReg) 2930 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 2931 } 2932 2933 SMLoc E = Parser.getTok().getLoc(); 2934 if (Parser.getTok().isNot(AsmToken::RCurly)) 2935 return Error(E, "'}' expected"); 2936 Parser.Lex(); // Eat '}' token. 2937 2938 // Push the register list operand. 2939 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 2940 2941 // The ARM system instruction variants for LDM/STM have a '^' token here. 2942 if (Parser.getTok().is(AsmToken::Caret)) { 2943 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 2944 Parser.Lex(); // Eat '^' token. 2945 } 2946 2947 return false; 2948 } 2949 2950 // Helper function to parse the lane index for vector lists. 2951 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2952 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) { 2953 Index = 0; // Always return a defined index value. 2954 if (Parser.getTok().is(AsmToken::LBrac)) { 2955 Parser.Lex(); // Eat the '['. 2956 if (Parser.getTok().is(AsmToken::RBrac)) { 2957 // "Dn[]" is the 'all lanes' syntax. 2958 LaneKind = AllLanes; 2959 Parser.Lex(); // Eat the ']'. 2960 return MatchOperand_Success; 2961 } 2962 2963 // There's an optional '#' token here. Normally there wouldn't be, but 2964 // inline assemble puts one in, and it's friendly to accept that. 2965 if (Parser.getTok().is(AsmToken::Hash)) 2966 Parser.Lex(); // Eat the '#' 2967 2968 const MCExpr *LaneIndex; 2969 SMLoc Loc = Parser.getTok().getLoc(); 2970 if (getParser().ParseExpression(LaneIndex)) { 2971 Error(Loc, "illegal expression"); 2972 return MatchOperand_ParseFail; 2973 } 2974 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 2975 if (!CE) { 2976 Error(Loc, "lane index must be empty or an integer"); 2977 return MatchOperand_ParseFail; 2978 } 2979 if (Parser.getTok().isNot(AsmToken::RBrac)) { 2980 Error(Parser.getTok().getLoc(), "']' expected"); 2981 return MatchOperand_ParseFail; 2982 } 2983 Parser.Lex(); // Eat the ']'. 2984 int64_t Val = CE->getValue(); 2985 2986 // FIXME: Make this range check context sensitive for .8, .16, .32. 2987 if (Val < 0 || Val > 7) { 2988 Error(Parser.getTok().getLoc(), "lane index out of range"); 2989 return MatchOperand_ParseFail; 2990 } 2991 Index = Val; 2992 LaneKind = IndexedLane; 2993 return MatchOperand_Success; 2994 } 2995 LaneKind = NoLanes; 2996 return MatchOperand_Success; 2997 } 2998 2999 // parse a vector register list 3000 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3001 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3002 VectorLaneTy LaneKind; 3003 unsigned LaneIndex; 3004 SMLoc S = Parser.getTok().getLoc(); 3005 // As an extension (to match gas), support a plain D register or Q register 3006 // (without encosing curly braces) as a single or double entry list, 3007 // respectively. 3008 if (Parser.getTok().is(AsmToken::Identifier)) { 3009 int Reg = tryParseRegister(); 3010 if (Reg == -1) 3011 return MatchOperand_NoMatch; 3012 SMLoc E = Parser.getTok().getLoc(); 3013 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3014 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 3015 if (Res != MatchOperand_Success) 3016 return Res; 3017 switch (LaneKind) { 3018 case NoLanes: 3019 E = Parser.getTok().getLoc(); 3020 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3021 break; 3022 case AllLanes: 3023 E = Parser.getTok().getLoc(); 3024 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3025 S, E)); 3026 break; 3027 case IndexedLane: 3028 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3029 LaneIndex, 3030 false, S, E)); 3031 break; 3032 } 3033 return MatchOperand_Success; 3034 } 3035 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3036 Reg = getDRegFromQReg(Reg); 3037 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 3038 if (Res != MatchOperand_Success) 3039 return Res; 3040 switch (LaneKind) { 3041 case NoLanes: 3042 E = Parser.getTok().getLoc(); 3043 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3044 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3045 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3046 break; 3047 case AllLanes: 3048 E = Parser.getTok().getLoc(); 3049 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3050 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3051 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3052 S, E)); 3053 break; 3054 case IndexedLane: 3055 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3056 LaneIndex, 3057 false, S, E)); 3058 break; 3059 } 3060 return MatchOperand_Success; 3061 } 3062 Error(S, "vector register expected"); 3063 return MatchOperand_ParseFail; 3064 } 3065 3066 if (Parser.getTok().isNot(AsmToken::LCurly)) 3067 return MatchOperand_NoMatch; 3068 3069 Parser.Lex(); // Eat '{' token. 3070 SMLoc RegLoc = Parser.getTok().getLoc(); 3071 3072 int Reg = tryParseRegister(); 3073 if (Reg == -1) { 3074 Error(RegLoc, "register expected"); 3075 return MatchOperand_ParseFail; 3076 } 3077 unsigned Count = 1; 3078 int Spacing = 0; 3079 unsigned FirstReg = Reg; 3080 // The list is of D registers, but we also allow Q regs and just interpret 3081 // them as the two D sub-registers. 3082 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3083 FirstReg = Reg = getDRegFromQReg(Reg); 3084 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3085 // it's ambiguous with four-register single spaced. 3086 ++Reg; 3087 ++Count; 3088 } 3089 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success) 3090 return MatchOperand_ParseFail; 3091 3092 while (Parser.getTok().is(AsmToken::Comma) || 3093 Parser.getTok().is(AsmToken::Minus)) { 3094 if (Parser.getTok().is(AsmToken::Minus)) { 3095 if (!Spacing) 3096 Spacing = 1; // Register range implies a single spaced list. 3097 else if (Spacing == 2) { 3098 Error(Parser.getTok().getLoc(), 3099 "sequential registers in double spaced list"); 3100 return MatchOperand_ParseFail; 3101 } 3102 Parser.Lex(); // Eat the minus. 3103 SMLoc EndLoc = Parser.getTok().getLoc(); 3104 int EndReg = tryParseRegister(); 3105 if (EndReg == -1) { 3106 Error(EndLoc, "register expected"); 3107 return MatchOperand_ParseFail; 3108 } 3109 // Allow Q regs and just interpret them as the two D sub-registers. 3110 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3111 EndReg = getDRegFromQReg(EndReg) + 1; 3112 // If the register is the same as the start reg, there's nothing 3113 // more to do. 3114 if (Reg == EndReg) 3115 continue; 3116 // The register must be in the same register class as the first. 3117 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3118 Error(EndLoc, "invalid register in register list"); 3119 return MatchOperand_ParseFail; 3120 } 3121 // Ranges must go from low to high. 3122 if (Reg > EndReg) { 3123 Error(EndLoc, "bad range in register list"); 3124 return MatchOperand_ParseFail; 3125 } 3126 // Parse the lane specifier if present. 3127 VectorLaneTy NextLaneKind; 3128 unsigned NextLaneIndex; 3129 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3130 return MatchOperand_ParseFail; 3131 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3132 Error(EndLoc, "mismatched lane index in register list"); 3133 return MatchOperand_ParseFail; 3134 } 3135 EndLoc = Parser.getTok().getLoc(); 3136 3137 // Add all the registers in the range to the register list. 3138 Count += EndReg - Reg; 3139 Reg = EndReg; 3140 continue; 3141 } 3142 Parser.Lex(); // Eat the comma. 3143 RegLoc = Parser.getTok().getLoc(); 3144 int OldReg = Reg; 3145 Reg = tryParseRegister(); 3146 if (Reg == -1) { 3147 Error(RegLoc, "register expected"); 3148 return MatchOperand_ParseFail; 3149 } 3150 // vector register lists must be contiguous. 3151 // It's OK to use the enumeration values directly here rather, as the 3152 // VFP register classes have the enum sorted properly. 3153 // 3154 // The list is of D registers, but we also allow Q regs and just interpret 3155 // them as the two D sub-registers. 3156 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3157 if (!Spacing) 3158 Spacing = 1; // Register range implies a single spaced list. 3159 else if (Spacing == 2) { 3160 Error(RegLoc, 3161 "invalid register in double-spaced list (must be 'D' register')"); 3162 return MatchOperand_ParseFail; 3163 } 3164 Reg = getDRegFromQReg(Reg); 3165 if (Reg != OldReg + 1) { 3166 Error(RegLoc, "non-contiguous register range"); 3167 return MatchOperand_ParseFail; 3168 } 3169 ++Reg; 3170 Count += 2; 3171 // Parse the lane specifier if present. 3172 VectorLaneTy NextLaneKind; 3173 unsigned NextLaneIndex; 3174 SMLoc EndLoc = Parser.getTok().getLoc(); 3175 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3176 return MatchOperand_ParseFail; 3177 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3178 Error(EndLoc, "mismatched lane index in register list"); 3179 return MatchOperand_ParseFail; 3180 } 3181 continue; 3182 } 3183 // Normal D register. 3184 // Figure out the register spacing (single or double) of the list if 3185 // we don't know it already. 3186 if (!Spacing) 3187 Spacing = 1 + (Reg == OldReg + 2); 3188 3189 // Just check that it's contiguous and keep going. 3190 if (Reg != OldReg + Spacing) { 3191 Error(RegLoc, "non-contiguous register range"); 3192 return MatchOperand_ParseFail; 3193 } 3194 ++Count; 3195 // Parse the lane specifier if present. 3196 VectorLaneTy NextLaneKind; 3197 unsigned NextLaneIndex; 3198 SMLoc EndLoc = Parser.getTok().getLoc(); 3199 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3200 return MatchOperand_ParseFail; 3201 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3202 Error(EndLoc, "mismatched lane index in register list"); 3203 return MatchOperand_ParseFail; 3204 } 3205 } 3206 3207 SMLoc E = Parser.getTok().getLoc(); 3208 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3209 Error(E, "'}' expected"); 3210 return MatchOperand_ParseFail; 3211 } 3212 Parser.Lex(); // Eat '}' token. 3213 3214 switch (LaneKind) { 3215 case NoLanes: 3216 // Two-register operands have been converted to the 3217 // composite register classes. 3218 if (Count == 2) { 3219 const MCRegisterClass *RC = (Spacing == 1) ? 3220 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3221 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3222 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3223 } 3224 3225 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3226 (Spacing == 2), S, E)); 3227 break; 3228 case AllLanes: 3229 // Two-register operands have been converted to the 3230 // composite register classes. 3231 if (Count == 2) { 3232 const MCRegisterClass *RC = (Spacing == 1) ? 3233 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3234 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3235 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3236 } 3237 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3238 (Spacing == 2), 3239 S, E)); 3240 break; 3241 case IndexedLane: 3242 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3243 LaneIndex, 3244 (Spacing == 2), 3245 S, E)); 3246 break; 3247 } 3248 return MatchOperand_Success; 3249 } 3250 3251 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3252 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3253 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3254 SMLoc S = Parser.getTok().getLoc(); 3255 const AsmToken &Tok = Parser.getTok(); 3256 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3257 StringRef OptStr = Tok.getString(); 3258 3259 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 3260 .Case("sy", ARM_MB::SY) 3261 .Case("st", ARM_MB::ST) 3262 .Case("sh", ARM_MB::ISH) 3263 .Case("ish", ARM_MB::ISH) 3264 .Case("shst", ARM_MB::ISHST) 3265 .Case("ishst", ARM_MB::ISHST) 3266 .Case("nsh", ARM_MB::NSH) 3267 .Case("un", ARM_MB::NSH) 3268 .Case("nshst", ARM_MB::NSHST) 3269 .Case("unst", ARM_MB::NSHST) 3270 .Case("osh", ARM_MB::OSH) 3271 .Case("oshst", ARM_MB::OSHST) 3272 .Default(~0U); 3273 3274 if (Opt == ~0U) 3275 return MatchOperand_NoMatch; 3276 3277 Parser.Lex(); // Eat identifier token. 3278 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3279 return MatchOperand_Success; 3280 } 3281 3282 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3283 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3284 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3285 SMLoc S = Parser.getTok().getLoc(); 3286 const AsmToken &Tok = Parser.getTok(); 3287 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3288 StringRef IFlagsStr = Tok.getString(); 3289 3290 // An iflags string of "none" is interpreted to mean that none of the AIF 3291 // bits are set. Not a terribly useful instruction, but a valid encoding. 3292 unsigned IFlags = 0; 3293 if (IFlagsStr != "none") { 3294 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3295 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3296 .Case("a", ARM_PROC::A) 3297 .Case("i", ARM_PROC::I) 3298 .Case("f", ARM_PROC::F) 3299 .Default(~0U); 3300 3301 // If some specific iflag is already set, it means that some letter is 3302 // present more than once, this is not acceptable. 3303 if (Flag == ~0U || (IFlags & Flag)) 3304 return MatchOperand_NoMatch; 3305 3306 IFlags |= Flag; 3307 } 3308 } 3309 3310 Parser.Lex(); // Eat identifier token. 3311 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3312 return MatchOperand_Success; 3313 } 3314 3315 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3316 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3317 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3318 SMLoc S = Parser.getTok().getLoc(); 3319 const AsmToken &Tok = Parser.getTok(); 3320 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3321 StringRef Mask = Tok.getString(); 3322 3323 if (isMClass()) { 3324 // See ARMv6-M 10.1.1 3325 std::string Name = Mask.lower(); 3326 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3327 // Note: in the documentation: 3328 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3329 // for MSR APSR_nzcvq. 3330 // but we do make it an alias here. This is so to get the "mask encoding" 3331 // bits correct on MSR APSR writes. 3332 // 3333 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3334 // should really only be allowed when writing a special register. Note 3335 // they get dropped in the MRS instruction reading a special register as 3336 // the SYSm field is only 8 bits. 3337 // 3338 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3339 // includes the DSP extension but that is not checked. 3340 .Case("apsr", 0x800) 3341 .Case("apsr_nzcvq", 0x800) 3342 .Case("apsr_g", 0x400) 3343 .Case("apsr_nzcvqg", 0xc00) 3344 .Case("iapsr", 0x801) 3345 .Case("iapsr_nzcvq", 0x801) 3346 .Case("iapsr_g", 0x401) 3347 .Case("iapsr_nzcvqg", 0xc01) 3348 .Case("eapsr", 0x802) 3349 .Case("eapsr_nzcvq", 0x802) 3350 .Case("eapsr_g", 0x402) 3351 .Case("eapsr_nzcvqg", 0xc02) 3352 .Case("xpsr", 0x803) 3353 .Case("xpsr_nzcvq", 0x803) 3354 .Case("xpsr_g", 0x403) 3355 .Case("xpsr_nzcvqg", 0xc03) 3356 .Case("ipsr", 5) 3357 .Case("epsr", 6) 3358 .Case("iepsr", 7) 3359 .Case("msp", 8) 3360 .Case("psp", 9) 3361 .Case("primask", 16) 3362 .Case("basepri", 17) 3363 .Case("basepri_max", 18) 3364 .Case("faultmask", 19) 3365 .Case("control", 20) 3366 .Default(~0U); 3367 3368 if (FlagsVal == ~0U) 3369 return MatchOperand_NoMatch; 3370 3371 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19) 3372 // basepri, basepri_max and faultmask only valid for V7m. 3373 return MatchOperand_NoMatch; 3374 3375 Parser.Lex(); // Eat identifier token. 3376 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3377 return MatchOperand_Success; 3378 } 3379 3380 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3381 size_t Start = 0, Next = Mask.find('_'); 3382 StringRef Flags = ""; 3383 std::string SpecReg = Mask.slice(Start, Next).lower(); 3384 if (Next != StringRef::npos) 3385 Flags = Mask.slice(Next+1, Mask.size()); 3386 3387 // FlagsVal contains the complete mask: 3388 // 3-0: Mask 3389 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3390 unsigned FlagsVal = 0; 3391 3392 if (SpecReg == "apsr") { 3393 FlagsVal = StringSwitch<unsigned>(Flags) 3394 .Case("nzcvq", 0x8) // same as CPSR_f 3395 .Case("g", 0x4) // same as CPSR_s 3396 .Case("nzcvqg", 0xc) // same as CPSR_fs 3397 .Default(~0U); 3398 3399 if (FlagsVal == ~0U) { 3400 if (!Flags.empty()) 3401 return MatchOperand_NoMatch; 3402 else 3403 FlagsVal = 8; // No flag 3404 } 3405 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3406 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3407 if (Flags == "all" || Flags == "") 3408 Flags = "fc"; 3409 for (int i = 0, e = Flags.size(); i != e; ++i) { 3410 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3411 .Case("c", 1) 3412 .Case("x", 2) 3413 .Case("s", 4) 3414 .Case("f", 8) 3415 .Default(~0U); 3416 3417 // If some specific flag is already set, it means that some letter is 3418 // present more than once, this is not acceptable. 3419 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3420 return MatchOperand_NoMatch; 3421 FlagsVal |= Flag; 3422 } 3423 } else // No match for special register. 3424 return MatchOperand_NoMatch; 3425 3426 // Special register without flags is NOT equivalent to "fc" flags. 3427 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3428 // two lines would enable gas compatibility at the expense of breaking 3429 // round-tripping. 3430 // 3431 // if (!FlagsVal) 3432 // FlagsVal = 0x9; 3433 3434 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3435 if (SpecReg == "spsr") 3436 FlagsVal |= 16; 3437 3438 Parser.Lex(); // Eat identifier token. 3439 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3440 return MatchOperand_Success; 3441 } 3442 3443 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3444 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3445 int Low, int High) { 3446 const AsmToken &Tok = Parser.getTok(); 3447 if (Tok.isNot(AsmToken::Identifier)) { 3448 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3449 return MatchOperand_ParseFail; 3450 } 3451 StringRef ShiftName = Tok.getString(); 3452 std::string LowerOp = Op.lower(); 3453 std::string UpperOp = Op.upper(); 3454 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3455 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3456 return MatchOperand_ParseFail; 3457 } 3458 Parser.Lex(); // Eat shift type token. 3459 3460 // There must be a '#' and a shift amount. 3461 if (Parser.getTok().isNot(AsmToken::Hash) && 3462 Parser.getTok().isNot(AsmToken::Dollar)) { 3463 Error(Parser.getTok().getLoc(), "'#' expected"); 3464 return MatchOperand_ParseFail; 3465 } 3466 Parser.Lex(); // Eat hash token. 3467 3468 const MCExpr *ShiftAmount; 3469 SMLoc Loc = Parser.getTok().getLoc(); 3470 if (getParser().ParseExpression(ShiftAmount)) { 3471 Error(Loc, "illegal expression"); 3472 return MatchOperand_ParseFail; 3473 } 3474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3475 if (!CE) { 3476 Error(Loc, "constant expression expected"); 3477 return MatchOperand_ParseFail; 3478 } 3479 int Val = CE->getValue(); 3480 if (Val < Low || Val > High) { 3481 Error(Loc, "immediate value out of range"); 3482 return MatchOperand_ParseFail; 3483 } 3484 3485 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 3486 3487 return MatchOperand_Success; 3488 } 3489 3490 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3491 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3492 const AsmToken &Tok = Parser.getTok(); 3493 SMLoc S = Tok.getLoc(); 3494 if (Tok.isNot(AsmToken::Identifier)) { 3495 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3496 return MatchOperand_ParseFail; 3497 } 3498 int Val = StringSwitch<int>(Tok.getString()) 3499 .Case("be", 1) 3500 .Case("le", 0) 3501 .Default(-1); 3502 Parser.Lex(); // Eat the token. 3503 3504 if (Val == -1) { 3505 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3506 return MatchOperand_ParseFail; 3507 } 3508 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3509 getContext()), 3510 S, Parser.getTok().getLoc())); 3511 return MatchOperand_Success; 3512 } 3513 3514 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3515 /// instructions. Legal values are: 3516 /// lsl #n 'n' in [0,31] 3517 /// asr #n 'n' in [1,32] 3518 /// n == 32 encoded as n == 0. 3519 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3520 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3521 const AsmToken &Tok = Parser.getTok(); 3522 SMLoc S = Tok.getLoc(); 3523 if (Tok.isNot(AsmToken::Identifier)) { 3524 Error(S, "shift operator 'asr' or 'lsl' expected"); 3525 return MatchOperand_ParseFail; 3526 } 3527 StringRef ShiftName = Tok.getString(); 3528 bool isASR; 3529 if (ShiftName == "lsl" || ShiftName == "LSL") 3530 isASR = false; 3531 else if (ShiftName == "asr" || ShiftName == "ASR") 3532 isASR = true; 3533 else { 3534 Error(S, "shift operator 'asr' or 'lsl' expected"); 3535 return MatchOperand_ParseFail; 3536 } 3537 Parser.Lex(); // Eat the operator. 3538 3539 // A '#' and a shift amount. 3540 if (Parser.getTok().isNot(AsmToken::Hash) && 3541 Parser.getTok().isNot(AsmToken::Dollar)) { 3542 Error(Parser.getTok().getLoc(), "'#' expected"); 3543 return MatchOperand_ParseFail; 3544 } 3545 Parser.Lex(); // Eat hash token. 3546 3547 const MCExpr *ShiftAmount; 3548 SMLoc E = Parser.getTok().getLoc(); 3549 if (getParser().ParseExpression(ShiftAmount)) { 3550 Error(E, "malformed shift expression"); 3551 return MatchOperand_ParseFail; 3552 } 3553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3554 if (!CE) { 3555 Error(E, "shift amount must be an immediate"); 3556 return MatchOperand_ParseFail; 3557 } 3558 3559 int64_t Val = CE->getValue(); 3560 if (isASR) { 3561 // Shift amount must be in [1,32] 3562 if (Val < 1 || Val > 32) { 3563 Error(E, "'asr' shift amount must be in range [1,32]"); 3564 return MatchOperand_ParseFail; 3565 } 3566 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3567 if (isThumb() && Val == 32) { 3568 Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 3569 return MatchOperand_ParseFail; 3570 } 3571 if (Val == 32) Val = 0; 3572 } else { 3573 // Shift amount must be in [1,32] 3574 if (Val < 0 || Val > 31) { 3575 Error(E, "'lsr' shift amount must be in range [0,31]"); 3576 return MatchOperand_ParseFail; 3577 } 3578 } 3579 3580 E = Parser.getTok().getLoc(); 3581 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 3582 3583 return MatchOperand_Success; 3584 } 3585 3586 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3587 /// of instructions. Legal values are: 3588 /// ror #n 'n' in {0, 8, 16, 24} 3589 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3590 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3591 const AsmToken &Tok = Parser.getTok(); 3592 SMLoc S = Tok.getLoc(); 3593 if (Tok.isNot(AsmToken::Identifier)) 3594 return MatchOperand_NoMatch; 3595 StringRef ShiftName = Tok.getString(); 3596 if (ShiftName != "ror" && ShiftName != "ROR") 3597 return MatchOperand_NoMatch; 3598 Parser.Lex(); // Eat the operator. 3599 3600 // A '#' and a rotate amount. 3601 if (Parser.getTok().isNot(AsmToken::Hash) && 3602 Parser.getTok().isNot(AsmToken::Dollar)) { 3603 Error(Parser.getTok().getLoc(), "'#' expected"); 3604 return MatchOperand_ParseFail; 3605 } 3606 Parser.Lex(); // Eat hash token. 3607 3608 const MCExpr *ShiftAmount; 3609 SMLoc E = Parser.getTok().getLoc(); 3610 if (getParser().ParseExpression(ShiftAmount)) { 3611 Error(E, "malformed rotate expression"); 3612 return MatchOperand_ParseFail; 3613 } 3614 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3615 if (!CE) { 3616 Error(E, "rotate amount must be an immediate"); 3617 return MatchOperand_ParseFail; 3618 } 3619 3620 int64_t Val = CE->getValue(); 3621 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 3622 // normally, zero is represented in asm by omitting the rotate operand 3623 // entirely. 3624 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 3625 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 3626 return MatchOperand_ParseFail; 3627 } 3628 3629 E = Parser.getTok().getLoc(); 3630 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 3631 3632 return MatchOperand_Success; 3633 } 3634 3635 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3636 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3637 SMLoc S = Parser.getTok().getLoc(); 3638 // The bitfield descriptor is really two operands, the LSB and the width. 3639 if (Parser.getTok().isNot(AsmToken::Hash) && 3640 Parser.getTok().isNot(AsmToken::Dollar)) { 3641 Error(Parser.getTok().getLoc(), "'#' expected"); 3642 return MatchOperand_ParseFail; 3643 } 3644 Parser.Lex(); // Eat hash token. 3645 3646 const MCExpr *LSBExpr; 3647 SMLoc E = Parser.getTok().getLoc(); 3648 if (getParser().ParseExpression(LSBExpr)) { 3649 Error(E, "malformed immediate expression"); 3650 return MatchOperand_ParseFail; 3651 } 3652 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3653 if (!CE) { 3654 Error(E, "'lsb' operand must be an immediate"); 3655 return MatchOperand_ParseFail; 3656 } 3657 3658 int64_t LSB = CE->getValue(); 3659 // The LSB must be in the range [0,31] 3660 if (LSB < 0 || LSB > 31) { 3661 Error(E, "'lsb' operand must be in the range [0,31]"); 3662 return MatchOperand_ParseFail; 3663 } 3664 E = Parser.getTok().getLoc(); 3665 3666 // Expect another immediate operand. 3667 if (Parser.getTok().isNot(AsmToken::Comma)) { 3668 Error(Parser.getTok().getLoc(), "too few operands"); 3669 return MatchOperand_ParseFail; 3670 } 3671 Parser.Lex(); // Eat hash token. 3672 if (Parser.getTok().isNot(AsmToken::Hash) && 3673 Parser.getTok().isNot(AsmToken::Dollar)) { 3674 Error(Parser.getTok().getLoc(), "'#' expected"); 3675 return MatchOperand_ParseFail; 3676 } 3677 Parser.Lex(); // Eat hash token. 3678 3679 const MCExpr *WidthExpr; 3680 if (getParser().ParseExpression(WidthExpr)) { 3681 Error(E, "malformed immediate expression"); 3682 return MatchOperand_ParseFail; 3683 } 3684 CE = dyn_cast<MCConstantExpr>(WidthExpr); 3685 if (!CE) { 3686 Error(E, "'width' operand must be an immediate"); 3687 return MatchOperand_ParseFail; 3688 } 3689 3690 int64_t Width = CE->getValue(); 3691 // The LSB must be in the range [1,32-lsb] 3692 if (Width < 1 || Width > 32 - LSB) { 3693 Error(E, "'width' operand must be in the range [1,32-lsb]"); 3694 return MatchOperand_ParseFail; 3695 } 3696 E = Parser.getTok().getLoc(); 3697 3698 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3699 3700 return MatchOperand_Success; 3701 } 3702 3703 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3704 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3705 // Check for a post-index addressing register operand. Specifically: 3706 // postidx_reg := '+' register {, shift} 3707 // | '-' register {, shift} 3708 // | register {, shift} 3709 3710 // This method must return MatchOperand_NoMatch without consuming any tokens 3711 // in the case where there is no match, as other alternatives take other 3712 // parse methods. 3713 AsmToken Tok = Parser.getTok(); 3714 SMLoc S = Tok.getLoc(); 3715 bool haveEaten = false; 3716 bool isAdd = true; 3717 int Reg = -1; 3718 if (Tok.is(AsmToken::Plus)) { 3719 Parser.Lex(); // Eat the '+' token. 3720 haveEaten = true; 3721 } else if (Tok.is(AsmToken::Minus)) { 3722 Parser.Lex(); // Eat the '-' token. 3723 isAdd = false; 3724 haveEaten = true; 3725 } 3726 if (Parser.getTok().is(AsmToken::Identifier)) 3727 Reg = tryParseRegister(); 3728 if (Reg == -1) { 3729 if (!haveEaten) 3730 return MatchOperand_NoMatch; 3731 Error(Parser.getTok().getLoc(), "register expected"); 3732 return MatchOperand_ParseFail; 3733 } 3734 SMLoc E = Parser.getTok().getLoc(); 3735 3736 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3737 unsigned ShiftImm = 0; 3738 if (Parser.getTok().is(AsmToken::Comma)) { 3739 Parser.Lex(); // Eat the ','. 3740 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 3741 return MatchOperand_ParseFail; 3742 } 3743 3744 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3745 ShiftImm, S, E)); 3746 3747 return MatchOperand_Success; 3748 } 3749 3750 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3751 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3752 // Check for a post-index addressing register operand. Specifically: 3753 // am3offset := '+' register 3754 // | '-' register 3755 // | register 3756 // | # imm 3757 // | # + imm 3758 // | # - imm 3759 3760 // This method must return MatchOperand_NoMatch without consuming any tokens 3761 // in the case where there is no match, as other alternatives take other 3762 // parse methods. 3763 AsmToken Tok = Parser.getTok(); 3764 SMLoc S = Tok.getLoc(); 3765 3766 // Do immediates first, as we always parse those if we have a '#'. 3767 if (Parser.getTok().is(AsmToken::Hash) || 3768 Parser.getTok().is(AsmToken::Dollar)) { 3769 Parser.Lex(); // Eat the '#'. 3770 // Explicitly look for a '-', as we need to encode negative zero 3771 // differently. 3772 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3773 const MCExpr *Offset; 3774 if (getParser().ParseExpression(Offset)) 3775 return MatchOperand_ParseFail; 3776 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3777 if (!CE) { 3778 Error(S, "constant expression expected"); 3779 return MatchOperand_ParseFail; 3780 } 3781 SMLoc E = Tok.getLoc(); 3782 // Negative zero is encoded as the flag value INT32_MIN. 3783 int32_t Val = CE->getValue(); 3784 if (isNegative && Val == 0) 3785 Val = INT32_MIN; 3786 3787 Operands.push_back( 3788 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3789 3790 return MatchOperand_Success; 3791 } 3792 3793 3794 bool haveEaten = false; 3795 bool isAdd = true; 3796 int Reg = -1; 3797 if (Tok.is(AsmToken::Plus)) { 3798 Parser.Lex(); // Eat the '+' token. 3799 haveEaten = true; 3800 } else if (Tok.is(AsmToken::Minus)) { 3801 Parser.Lex(); // Eat the '-' token. 3802 isAdd = false; 3803 haveEaten = true; 3804 } 3805 if (Parser.getTok().is(AsmToken::Identifier)) 3806 Reg = tryParseRegister(); 3807 if (Reg == -1) { 3808 if (!haveEaten) 3809 return MatchOperand_NoMatch; 3810 Error(Parser.getTok().getLoc(), "register expected"); 3811 return MatchOperand_ParseFail; 3812 } 3813 SMLoc E = Parser.getTok().getLoc(); 3814 3815 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3816 0, S, E)); 3817 3818 return MatchOperand_Success; 3819 } 3820 3821 /// cvtT2LdrdPre - Convert parsed operands to MCInst. 3822 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3823 /// when they refer multiple MIOperands inside a single one. 3824 bool ARMAsmParser:: 3825 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 3826 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3827 // Rt, Rt2 3828 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3829 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3830 // Create a writeback register dummy placeholder. 3831 Inst.addOperand(MCOperand::CreateReg(0)); 3832 // addr 3833 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3834 // pred 3835 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3836 return true; 3837 } 3838 3839 /// cvtT2StrdPre - Convert parsed operands to MCInst. 3840 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3841 /// when they refer multiple MIOperands inside a single one. 3842 bool ARMAsmParser:: 3843 cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 3844 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3845 // Create a writeback register dummy placeholder. 3846 Inst.addOperand(MCOperand::CreateReg(0)); 3847 // Rt, Rt2 3848 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3849 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3850 // addr 3851 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3852 // pred 3853 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3854 return true; 3855 } 3856 3857 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3858 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3859 /// when they refer multiple MIOperands inside a single one. 3860 bool ARMAsmParser:: 3861 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3862 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3863 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3864 3865 // Create a writeback register dummy placeholder. 3866 Inst.addOperand(MCOperand::CreateImm(0)); 3867 3868 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3869 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3870 return true; 3871 } 3872 3873 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3874 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3875 /// when they refer multiple MIOperands inside a single one. 3876 bool ARMAsmParser:: 3877 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3878 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3879 // Create a writeback register dummy placeholder. 3880 Inst.addOperand(MCOperand::CreateImm(0)); 3881 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3882 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3883 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3884 return true; 3885 } 3886 3887 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3888 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3889 /// when they refer multiple MIOperands inside a single one. 3890 bool ARMAsmParser:: 3891 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3892 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3893 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3894 3895 // Create a writeback register dummy placeholder. 3896 Inst.addOperand(MCOperand::CreateImm(0)); 3897 3898 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3899 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3900 return true; 3901 } 3902 3903 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3904 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3905 /// when they refer multiple MIOperands inside a single one. 3906 bool ARMAsmParser:: 3907 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3908 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3909 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3910 3911 // Create a writeback register dummy placeholder. 3912 Inst.addOperand(MCOperand::CreateImm(0)); 3913 3914 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3915 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3916 return true; 3917 } 3918 3919 3920 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3921 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3922 /// when they refer multiple MIOperands inside a single one. 3923 bool ARMAsmParser:: 3924 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3925 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3926 // Create a writeback register dummy placeholder. 3927 Inst.addOperand(MCOperand::CreateImm(0)); 3928 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3929 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3930 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3931 return true; 3932 } 3933 3934 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3935 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3936 /// when they refer multiple MIOperands inside a single one. 3937 bool ARMAsmParser:: 3938 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3939 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3940 // Create a writeback register dummy placeholder. 3941 Inst.addOperand(MCOperand::CreateImm(0)); 3942 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3943 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3944 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3945 return true; 3946 } 3947 3948 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 3949 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3950 /// when they refer multiple MIOperands inside a single one. 3951 bool ARMAsmParser:: 3952 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 3953 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3954 // Create a writeback register dummy placeholder. 3955 Inst.addOperand(MCOperand::CreateImm(0)); 3956 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3957 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 3958 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3959 return true; 3960 } 3961 3962 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 3963 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3964 /// when they refer multiple MIOperands inside a single one. 3965 bool ARMAsmParser:: 3966 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 3967 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3968 // Rt 3969 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3970 // Create a writeback register dummy placeholder. 3971 Inst.addOperand(MCOperand::CreateImm(0)); 3972 // addr 3973 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3974 // offset 3975 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 3976 // pred 3977 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3978 return true; 3979 } 3980 3981 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 3982 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 3983 /// when they refer multiple MIOperands inside a single one. 3984 bool ARMAsmParser:: 3985 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 3986 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3987 // Rt 3988 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3989 // Create a writeback register dummy placeholder. 3990 Inst.addOperand(MCOperand::CreateImm(0)); 3991 // addr 3992 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3993 // offset 3994 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 3995 // pred 3996 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3997 return true; 3998 } 3999 4000 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 4001 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4002 /// when they refer multiple MIOperands inside a single one. 4003 bool ARMAsmParser:: 4004 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 4005 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4006 // Create a writeback register dummy placeholder. 4007 Inst.addOperand(MCOperand::CreateImm(0)); 4008 // Rt 4009 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4010 // addr 4011 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4012 // offset 4013 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4014 // pred 4015 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4016 return true; 4017 } 4018 4019 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 4020 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4021 /// when they refer multiple MIOperands inside a single one. 4022 bool ARMAsmParser:: 4023 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 4024 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4025 // Create a writeback register dummy placeholder. 4026 Inst.addOperand(MCOperand::CreateImm(0)); 4027 // Rt 4028 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4029 // addr 4030 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4031 // offset 4032 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4033 // pred 4034 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4035 return true; 4036 } 4037 4038 /// cvtLdrdPre - Convert parsed operands to MCInst. 4039 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4040 /// when they refer multiple MIOperands inside a single one. 4041 bool ARMAsmParser:: 4042 cvtLdrdPre(MCInst &Inst, unsigned Opcode, 4043 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4044 // Rt, Rt2 4045 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4046 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4047 // Create a writeback register dummy placeholder. 4048 Inst.addOperand(MCOperand::CreateImm(0)); 4049 // addr 4050 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4051 // pred 4052 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4053 return true; 4054 } 4055 4056 /// cvtStrdPre - Convert parsed operands to MCInst. 4057 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4058 /// when they refer multiple MIOperands inside a single one. 4059 bool ARMAsmParser:: 4060 cvtStrdPre(MCInst &Inst, unsigned Opcode, 4061 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4062 // Create a writeback register dummy placeholder. 4063 Inst.addOperand(MCOperand::CreateImm(0)); 4064 // Rt, Rt2 4065 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4066 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4067 // addr 4068 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4069 // pred 4070 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4071 return true; 4072 } 4073 4074 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4075 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4076 /// when they refer multiple MIOperands inside a single one. 4077 bool ARMAsmParser:: 4078 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 4079 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4080 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4081 // Create a writeback register dummy placeholder. 4082 Inst.addOperand(MCOperand::CreateImm(0)); 4083 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4084 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4085 return true; 4086 } 4087 4088 /// cvtThumbMultiple- Convert parsed operands to MCInst. 4089 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4090 /// when they refer multiple MIOperands inside a single one. 4091 bool ARMAsmParser:: 4092 cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 4093 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4094 // The second source operand must be the same register as the destination 4095 // operand. 4096 if (Operands.size() == 6 && 4097 (((ARMOperand*)Operands[3])->getReg() != 4098 ((ARMOperand*)Operands[5])->getReg()) && 4099 (((ARMOperand*)Operands[3])->getReg() != 4100 ((ARMOperand*)Operands[4])->getReg())) { 4101 Error(Operands[3]->getStartLoc(), 4102 "destination register must match source register"); 4103 return false; 4104 } 4105 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4106 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4107 // If we have a three-operand form, make sure to set Rn to be the operand 4108 // that isn't the same as Rd. 4109 unsigned RegOp = 4; 4110 if (Operands.size() == 6 && 4111 ((ARMOperand*)Operands[4])->getReg() == 4112 ((ARMOperand*)Operands[3])->getReg()) 4113 RegOp = 5; 4114 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4115 Inst.addOperand(Inst.getOperand(0)); 4116 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4117 4118 return true; 4119 } 4120 4121 bool ARMAsmParser:: 4122 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 4123 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4124 // Vd 4125 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4126 // Create a writeback register dummy placeholder. 4127 Inst.addOperand(MCOperand::CreateImm(0)); 4128 // Vn 4129 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4130 // pred 4131 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4132 return true; 4133 } 4134 4135 bool ARMAsmParser:: 4136 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 4137 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4138 // Vd 4139 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4140 // Create a writeback register dummy placeholder. 4141 Inst.addOperand(MCOperand::CreateImm(0)); 4142 // Vn 4143 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4144 // Vm 4145 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4146 // pred 4147 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4148 return true; 4149 } 4150 4151 bool ARMAsmParser:: 4152 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 4153 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4154 // Create a writeback register dummy placeholder. 4155 Inst.addOperand(MCOperand::CreateImm(0)); 4156 // Vn 4157 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4158 // Vt 4159 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4160 // pred 4161 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4162 return true; 4163 } 4164 4165 bool ARMAsmParser:: 4166 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 4167 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4168 // Create a writeback register dummy placeholder. 4169 Inst.addOperand(MCOperand::CreateImm(0)); 4170 // Vn 4171 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4172 // Vm 4173 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4174 // Vt 4175 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4176 // pred 4177 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4178 return true; 4179 } 4180 4181 /// Parse an ARM memory expression, return false if successful else return true 4182 /// or an error. The first token must be a '[' when called. 4183 bool ARMAsmParser:: 4184 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4185 SMLoc S, E; 4186 assert(Parser.getTok().is(AsmToken::LBrac) && 4187 "Token is not a Left Bracket"); 4188 S = Parser.getTok().getLoc(); 4189 Parser.Lex(); // Eat left bracket token. 4190 4191 const AsmToken &BaseRegTok = Parser.getTok(); 4192 int BaseRegNum = tryParseRegister(); 4193 if (BaseRegNum == -1) 4194 return Error(BaseRegTok.getLoc(), "register expected"); 4195 4196 // The next token must either be a comma or a closing bracket. 4197 const AsmToken &Tok = Parser.getTok(); 4198 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 4199 return Error(Tok.getLoc(), "malformed memory operand"); 4200 4201 if (Tok.is(AsmToken::RBrac)) { 4202 E = Tok.getLoc(); 4203 Parser.Lex(); // Eat right bracket token. 4204 4205 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4206 0, 0, false, S, E)); 4207 4208 // If there's a pre-indexing writeback marker, '!', just add it as a token 4209 // operand. It's rather odd, but syntactically valid. 4210 if (Parser.getTok().is(AsmToken::Exclaim)) { 4211 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4212 Parser.Lex(); // Eat the '!'. 4213 } 4214 4215 return false; 4216 } 4217 4218 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 4219 Parser.Lex(); // Eat the comma. 4220 4221 // If we have a ':', it's an alignment specifier. 4222 if (Parser.getTok().is(AsmToken::Colon)) { 4223 Parser.Lex(); // Eat the ':'. 4224 E = Parser.getTok().getLoc(); 4225 4226 const MCExpr *Expr; 4227 if (getParser().ParseExpression(Expr)) 4228 return true; 4229 4230 // The expression has to be a constant. Memory references with relocations 4231 // don't come through here, as they use the <label> forms of the relevant 4232 // instructions. 4233 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4234 if (!CE) 4235 return Error (E, "constant expression expected"); 4236 4237 unsigned Align = 0; 4238 switch (CE->getValue()) { 4239 default: 4240 return Error(E, 4241 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4242 case 16: Align = 2; break; 4243 case 32: Align = 4; break; 4244 case 64: Align = 8; break; 4245 case 128: Align = 16; break; 4246 case 256: Align = 32; break; 4247 } 4248 4249 // Now we should have the closing ']' 4250 E = Parser.getTok().getLoc(); 4251 if (Parser.getTok().isNot(AsmToken::RBrac)) 4252 return Error(E, "']' expected"); 4253 Parser.Lex(); // Eat right bracket token. 4254 4255 // Don't worry about range checking the value here. That's handled by 4256 // the is*() predicates. 4257 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4258 ARM_AM::no_shift, 0, Align, 4259 false, S, E)); 4260 4261 // If there's a pre-indexing writeback marker, '!', just add it as a token 4262 // operand. 4263 if (Parser.getTok().is(AsmToken::Exclaim)) { 4264 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4265 Parser.Lex(); // Eat the '!'. 4266 } 4267 4268 return false; 4269 } 4270 4271 // If we have a '#', it's an immediate offset, else assume it's a register 4272 // offset. Be friendly and also accept a plain integer (without a leading 4273 // hash) for gas compatibility. 4274 if (Parser.getTok().is(AsmToken::Hash) || 4275 Parser.getTok().is(AsmToken::Dollar) || 4276 Parser.getTok().is(AsmToken::Integer)) { 4277 if (Parser.getTok().isNot(AsmToken::Integer)) 4278 Parser.Lex(); // Eat the '#'. 4279 E = Parser.getTok().getLoc(); 4280 4281 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4282 const MCExpr *Offset; 4283 if (getParser().ParseExpression(Offset)) 4284 return true; 4285 4286 // The expression has to be a constant. Memory references with relocations 4287 // don't come through here, as they use the <label> forms of the relevant 4288 // instructions. 4289 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4290 if (!CE) 4291 return Error (E, "constant expression expected"); 4292 4293 // If the constant was #-0, represent it as INT32_MIN. 4294 int32_t Val = CE->getValue(); 4295 if (isNegative && Val == 0) 4296 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4297 4298 // Now we should have the closing ']' 4299 E = Parser.getTok().getLoc(); 4300 if (Parser.getTok().isNot(AsmToken::RBrac)) 4301 return Error(E, "']' expected"); 4302 Parser.Lex(); // Eat right bracket token. 4303 4304 // Don't worry about range checking the value here. That's handled by 4305 // the is*() predicates. 4306 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4307 ARM_AM::no_shift, 0, 0, 4308 false, S, E)); 4309 4310 // If there's a pre-indexing writeback marker, '!', just add it as a token 4311 // operand. 4312 if (Parser.getTok().is(AsmToken::Exclaim)) { 4313 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4314 Parser.Lex(); // Eat the '!'. 4315 } 4316 4317 return false; 4318 } 4319 4320 // The register offset is optionally preceded by a '+' or '-' 4321 bool isNegative = false; 4322 if (Parser.getTok().is(AsmToken::Minus)) { 4323 isNegative = true; 4324 Parser.Lex(); // Eat the '-'. 4325 } else if (Parser.getTok().is(AsmToken::Plus)) { 4326 // Nothing to do. 4327 Parser.Lex(); // Eat the '+'. 4328 } 4329 4330 E = Parser.getTok().getLoc(); 4331 int OffsetRegNum = tryParseRegister(); 4332 if (OffsetRegNum == -1) 4333 return Error(E, "register expected"); 4334 4335 // If there's a shift operator, handle it. 4336 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4337 unsigned ShiftImm = 0; 4338 if (Parser.getTok().is(AsmToken::Comma)) { 4339 Parser.Lex(); // Eat the ','. 4340 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4341 return true; 4342 } 4343 4344 // Now we should have the closing ']' 4345 E = Parser.getTok().getLoc(); 4346 if (Parser.getTok().isNot(AsmToken::RBrac)) 4347 return Error(E, "']' expected"); 4348 Parser.Lex(); // Eat right bracket token. 4349 4350 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4351 ShiftType, ShiftImm, 0, isNegative, 4352 S, E)); 4353 4354 // If there's a pre-indexing writeback marker, '!', just add it as a token 4355 // operand. 4356 if (Parser.getTok().is(AsmToken::Exclaim)) { 4357 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4358 Parser.Lex(); // Eat the '!'. 4359 } 4360 4361 return false; 4362 } 4363 4364 /// parseMemRegOffsetShift - one of these two: 4365 /// ( lsl | lsr | asr | ror ) , # shift_amount 4366 /// rrx 4367 /// return true if it parses a shift otherwise it returns false. 4368 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4369 unsigned &Amount) { 4370 SMLoc Loc = Parser.getTok().getLoc(); 4371 const AsmToken &Tok = Parser.getTok(); 4372 if (Tok.isNot(AsmToken::Identifier)) 4373 return true; 4374 StringRef ShiftName = Tok.getString(); 4375 if (ShiftName == "lsl" || ShiftName == "LSL" || 4376 ShiftName == "asl" || ShiftName == "ASL") 4377 St = ARM_AM::lsl; 4378 else if (ShiftName == "lsr" || ShiftName == "LSR") 4379 St = ARM_AM::lsr; 4380 else if (ShiftName == "asr" || ShiftName == "ASR") 4381 St = ARM_AM::asr; 4382 else if (ShiftName == "ror" || ShiftName == "ROR") 4383 St = ARM_AM::ror; 4384 else if (ShiftName == "rrx" || ShiftName == "RRX") 4385 St = ARM_AM::rrx; 4386 else 4387 return Error(Loc, "illegal shift operator"); 4388 Parser.Lex(); // Eat shift type token. 4389 4390 // rrx stands alone. 4391 Amount = 0; 4392 if (St != ARM_AM::rrx) { 4393 Loc = Parser.getTok().getLoc(); 4394 // A '#' and a shift amount. 4395 const AsmToken &HashTok = Parser.getTok(); 4396 if (HashTok.isNot(AsmToken::Hash) && 4397 HashTok.isNot(AsmToken::Dollar)) 4398 return Error(HashTok.getLoc(), "'#' expected"); 4399 Parser.Lex(); // Eat hash token. 4400 4401 const MCExpr *Expr; 4402 if (getParser().ParseExpression(Expr)) 4403 return true; 4404 // Range check the immediate. 4405 // lsl, ror: 0 <= imm <= 31 4406 // lsr, asr: 0 <= imm <= 32 4407 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4408 if (!CE) 4409 return Error(Loc, "shift amount must be an immediate"); 4410 int64_t Imm = CE->getValue(); 4411 if (Imm < 0 || 4412 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4413 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4414 return Error(Loc, "immediate shift value out of range"); 4415 Amount = Imm; 4416 } 4417 4418 return false; 4419 } 4420 4421 /// parseFPImm - A floating point immediate expression operand. 4422 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4423 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4424 // Anything that can accept a floating point constant as an operand 4425 // needs to go through here, as the regular ParseExpression is 4426 // integer only. 4427 // 4428 // This routine still creates a generic Immediate operand, containing 4429 // a bitcast of the 64-bit floating point value. The various operands 4430 // that accept floats can check whether the value is valid for them 4431 // via the standard is*() predicates. 4432 4433 SMLoc S = Parser.getTok().getLoc(); 4434 4435 if (Parser.getTok().isNot(AsmToken::Hash) && 4436 Parser.getTok().isNot(AsmToken::Dollar)) 4437 return MatchOperand_NoMatch; 4438 4439 // Disambiguate the VMOV forms that can accept an FP immediate. 4440 // vmov.f32 <sreg>, #imm 4441 // vmov.f64 <dreg>, #imm 4442 // vmov.f32 <dreg>, #imm @ vector f32x2 4443 // vmov.f32 <qreg>, #imm @ vector f32x4 4444 // 4445 // There are also the NEON VMOV instructions which expect an 4446 // integer constant. Make sure we don't try to parse an FPImm 4447 // for these: 4448 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4449 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4450 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 4451 TyOp->getToken() != ".f64")) 4452 return MatchOperand_NoMatch; 4453 4454 Parser.Lex(); // Eat the '#'. 4455 4456 // Handle negation, as that still comes through as a separate token. 4457 bool isNegative = false; 4458 if (Parser.getTok().is(AsmToken::Minus)) { 4459 isNegative = true; 4460 Parser.Lex(); 4461 } 4462 const AsmToken &Tok = Parser.getTok(); 4463 SMLoc Loc = Tok.getLoc(); 4464 if (Tok.is(AsmToken::Real)) { 4465 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4466 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4467 // If we had a '-' in front, toggle the sign bit. 4468 IntVal ^= (uint64_t)isNegative << 31; 4469 Parser.Lex(); // Eat the token. 4470 Operands.push_back(ARMOperand::CreateImm( 4471 MCConstantExpr::Create(IntVal, getContext()), 4472 S, Parser.getTok().getLoc())); 4473 return MatchOperand_Success; 4474 } 4475 // Also handle plain integers. Instructions which allow floating point 4476 // immediates also allow a raw encoded 8-bit value. 4477 if (Tok.is(AsmToken::Integer)) { 4478 int64_t Val = Tok.getIntVal(); 4479 Parser.Lex(); // Eat the token. 4480 if (Val > 255 || Val < 0) { 4481 Error(Loc, "encoded floating point value out of range"); 4482 return MatchOperand_ParseFail; 4483 } 4484 double RealVal = ARM_AM::getFPImmFloat(Val); 4485 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 4486 Operands.push_back(ARMOperand::CreateImm( 4487 MCConstantExpr::Create(Val, getContext()), S, 4488 Parser.getTok().getLoc())); 4489 return MatchOperand_Success; 4490 } 4491 4492 Error(Loc, "invalid floating point immediate"); 4493 return MatchOperand_ParseFail; 4494 } 4495 4496 /// Parse a arm instruction operand. For now this parses the operand regardless 4497 /// of the mnemonic. 4498 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4499 StringRef Mnemonic) { 4500 SMLoc S, E; 4501 4502 // Check if the current operand has a custom associated parser, if so, try to 4503 // custom parse the operand, or fallback to the general approach. 4504 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4505 if (ResTy == MatchOperand_Success) 4506 return false; 4507 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4508 // there was a match, but an error occurred, in which case, just return that 4509 // the operand parsing failed. 4510 if (ResTy == MatchOperand_ParseFail) 4511 return true; 4512 4513 switch (getLexer().getKind()) { 4514 default: 4515 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4516 return true; 4517 case AsmToken::Identifier: { 4518 if (!tryParseRegisterWithWriteBack(Operands)) 4519 return false; 4520 int Res = tryParseShiftRegister(Operands); 4521 if (Res == 0) // success 4522 return false; 4523 else if (Res == -1) // irrecoverable error 4524 return true; 4525 // If this is VMRS, check for the apsr_nzcv operand. 4526 if (Mnemonic == "vmrs" && 4527 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4528 S = Parser.getTok().getLoc(); 4529 Parser.Lex(); 4530 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4531 return false; 4532 } 4533 4534 // Fall though for the Identifier case that is not a register or a 4535 // special name. 4536 } 4537 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4538 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4539 case AsmToken::String: // quoted label names. 4540 case AsmToken::Dot: { // . as a branch target 4541 // This was not a register so parse other operands that start with an 4542 // identifier (like labels) as expressions and create them as immediates. 4543 const MCExpr *IdVal; 4544 S = Parser.getTok().getLoc(); 4545 if (getParser().ParseExpression(IdVal)) 4546 return true; 4547 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4548 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4549 return false; 4550 } 4551 case AsmToken::LBrac: 4552 return parseMemory(Operands); 4553 case AsmToken::LCurly: 4554 return parseRegisterList(Operands); 4555 case AsmToken::Dollar: 4556 case AsmToken::Hash: { 4557 // #42 -> immediate. 4558 S = Parser.getTok().getLoc(); 4559 Parser.Lex(); 4560 4561 if (Parser.getTok().isNot(AsmToken::Colon)) { 4562 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4563 const MCExpr *ImmVal; 4564 if (getParser().ParseExpression(ImmVal)) 4565 return true; 4566 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4567 if (CE) { 4568 int32_t Val = CE->getValue(); 4569 if (isNegative && Val == 0) 4570 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4571 } 4572 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4573 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4574 return false; 4575 } 4576 // w/ a ':' after the '#', it's just like a plain ':'. 4577 // FALLTHROUGH 4578 } 4579 case AsmToken::Colon: { 4580 // ":lower16:" and ":upper16:" expression prefixes 4581 // FIXME: Check it's an expression prefix, 4582 // e.g. (FOO - :lower16:BAR) isn't legal. 4583 ARMMCExpr::VariantKind RefKind; 4584 if (parsePrefix(RefKind)) 4585 return true; 4586 4587 const MCExpr *SubExprVal; 4588 if (getParser().ParseExpression(SubExprVal)) 4589 return true; 4590 4591 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4592 getContext()); 4593 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4594 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4595 return false; 4596 } 4597 } 4598 } 4599 4600 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4601 // :lower16: and :upper16:. 4602 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4603 RefKind = ARMMCExpr::VK_ARM_None; 4604 4605 // :lower16: and :upper16: modifiers 4606 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4607 Parser.Lex(); // Eat ':' 4608 4609 if (getLexer().isNot(AsmToken::Identifier)) { 4610 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4611 return true; 4612 } 4613 4614 StringRef IDVal = Parser.getTok().getIdentifier(); 4615 if (IDVal == "lower16") { 4616 RefKind = ARMMCExpr::VK_ARM_LO16; 4617 } else if (IDVal == "upper16") { 4618 RefKind = ARMMCExpr::VK_ARM_HI16; 4619 } else { 4620 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4621 return true; 4622 } 4623 Parser.Lex(); 4624 4625 if (getLexer().isNot(AsmToken::Colon)) { 4626 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4627 return true; 4628 } 4629 Parser.Lex(); // Eat the last ':' 4630 return false; 4631 } 4632 4633 /// \brief Given a mnemonic, split out possible predication code and carry 4634 /// setting letters to form a canonical mnemonic and flags. 4635 // 4636 // FIXME: Would be nice to autogen this. 4637 // FIXME: This is a bit of a maze of special cases. 4638 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4639 unsigned &PredicationCode, 4640 bool &CarrySetting, 4641 unsigned &ProcessorIMod, 4642 StringRef &ITMask) { 4643 PredicationCode = ARMCC::AL; 4644 CarrySetting = false; 4645 ProcessorIMod = 0; 4646 4647 // Ignore some mnemonics we know aren't predicated forms. 4648 // 4649 // FIXME: Would be nice to autogen this. 4650 if ((Mnemonic == "movs" && isThumb()) || 4651 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4652 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4653 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4654 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4655 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4656 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4657 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4658 Mnemonic == "fmuls") 4659 return Mnemonic; 4660 4661 // First, split out any predication code. Ignore mnemonics we know aren't 4662 // predicated but do have a carry-set and so weren't caught above. 4663 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4664 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4665 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4666 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4667 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4668 .Case("eq", ARMCC::EQ) 4669 .Case("ne", ARMCC::NE) 4670 .Case("hs", ARMCC::HS) 4671 .Case("cs", ARMCC::HS) 4672 .Case("lo", ARMCC::LO) 4673 .Case("cc", ARMCC::LO) 4674 .Case("mi", ARMCC::MI) 4675 .Case("pl", ARMCC::PL) 4676 .Case("vs", ARMCC::VS) 4677 .Case("vc", ARMCC::VC) 4678 .Case("hi", ARMCC::HI) 4679 .Case("ls", ARMCC::LS) 4680 .Case("ge", ARMCC::GE) 4681 .Case("lt", ARMCC::LT) 4682 .Case("gt", ARMCC::GT) 4683 .Case("le", ARMCC::LE) 4684 .Case("al", ARMCC::AL) 4685 .Default(~0U); 4686 if (CC != ~0U) { 4687 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4688 PredicationCode = CC; 4689 } 4690 } 4691 4692 // Next, determine if we have a carry setting bit. We explicitly ignore all 4693 // the instructions we know end in 's'. 4694 if (Mnemonic.endswith("s") && 4695 !(Mnemonic == "cps" || Mnemonic == "mls" || 4696 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4697 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4698 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4699 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4700 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4701 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4702 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4703 Mnemonic == "vfms" || Mnemonic == "vfnms" || 4704 (Mnemonic == "movs" && isThumb()))) { 4705 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4706 CarrySetting = true; 4707 } 4708 4709 // The "cps" instruction can have a interrupt mode operand which is glued into 4710 // the mnemonic. Check if this is the case, split it and parse the imod op 4711 if (Mnemonic.startswith("cps")) { 4712 // Split out any imod code. 4713 unsigned IMod = 4714 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4715 .Case("ie", ARM_PROC::IE) 4716 .Case("id", ARM_PROC::ID) 4717 .Default(~0U); 4718 if (IMod != ~0U) { 4719 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4720 ProcessorIMod = IMod; 4721 } 4722 } 4723 4724 // The "it" instruction has the condition mask on the end of the mnemonic. 4725 if (Mnemonic.startswith("it")) { 4726 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4727 Mnemonic = Mnemonic.slice(0, 2); 4728 } 4729 4730 return Mnemonic; 4731 } 4732 4733 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 4734 /// inclusion of carry set or predication code operands. 4735 // 4736 // FIXME: It would be nice to autogen this. 4737 void ARMAsmParser:: 4738 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4739 bool &CanAcceptPredicationCode) { 4740 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4741 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4742 Mnemonic == "add" || Mnemonic == "adc" || 4743 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4744 Mnemonic == "orr" || Mnemonic == "mvn" || 4745 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4746 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4747 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4748 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4749 Mnemonic == "mla" || Mnemonic == "smlal" || 4750 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4751 CanAcceptCarrySet = true; 4752 } else 4753 CanAcceptCarrySet = false; 4754 4755 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4756 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4757 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4758 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4759 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4760 (Mnemonic == "clrex" && !isThumb()) || 4761 (Mnemonic == "nop" && isThumbOne()) || 4762 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 4763 Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 4764 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 4765 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 4766 !isThumb()) || 4767 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 4768 CanAcceptPredicationCode = false; 4769 } else 4770 CanAcceptPredicationCode = true; 4771 4772 if (isThumb()) { 4773 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 4774 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4775 CanAcceptPredicationCode = false; 4776 } 4777 } 4778 4779 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4780 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4781 // FIXME: This is all horribly hacky. We really need a better way to deal 4782 // with optional operands like this in the matcher table. 4783 4784 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4785 // another does not. Specifically, the MOVW instruction does not. So we 4786 // special case it here and remove the defaulted (non-setting) cc_out 4787 // operand if that's the instruction we're trying to match. 4788 // 4789 // We do this as post-processing of the explicit operands rather than just 4790 // conditionally adding the cc_out in the first place because we need 4791 // to check the type of the parsed immediate operand. 4792 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4793 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4794 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4795 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4796 return true; 4797 4798 // Register-register 'add' for thumb does not have a cc_out operand 4799 // when there are only two register operands. 4800 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4801 static_cast<ARMOperand*>(Operands[3])->isReg() && 4802 static_cast<ARMOperand*>(Operands[4])->isReg() && 4803 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4804 return true; 4805 // Register-register 'add' for thumb does not have a cc_out operand 4806 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4807 // have to check the immediate range here since Thumb2 has a variant 4808 // that can handle a different range and has a cc_out operand. 4809 if (((isThumb() && Mnemonic == "add") || 4810 (isThumbTwo() && Mnemonic == "sub")) && 4811 Operands.size() == 6 && 4812 static_cast<ARMOperand*>(Operands[3])->isReg() && 4813 static_cast<ARMOperand*>(Operands[4])->isReg() && 4814 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4815 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4816 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 4817 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4818 return true; 4819 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4820 // imm0_4095 variant. That's the least-preferred variant when 4821 // selecting via the generic "add" mnemonic, so to know that we 4822 // should remove the cc_out operand, we have to explicitly check that 4823 // it's not one of the other variants. Ugh. 4824 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4825 Operands.size() == 6 && 4826 static_cast<ARMOperand*>(Operands[3])->isReg() && 4827 static_cast<ARMOperand*>(Operands[4])->isReg() && 4828 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4829 // Nest conditions rather than one big 'if' statement for readability. 4830 // 4831 // If either register is a high reg, it's either one of the SP 4832 // variants (handled above) or a 32-bit encoding, so we just 4833 // check against T3. If the second register is the PC, this is an 4834 // alternate form of ADR, which uses encoding T4, so check for that too. 4835 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4836 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 4837 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 4838 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 4839 return false; 4840 // If both registers are low, we're in an IT block, and the immediate is 4841 // in range, we should use encoding T1 instead, which has a cc_out. 4842 if (inITBlock() && 4843 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4844 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 4845 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 4846 return false; 4847 4848 // Otherwise, we use encoding T4, which does not have a cc_out 4849 // operand. 4850 return true; 4851 } 4852 4853 // The thumb2 multiply instruction doesn't have a CCOut register, so 4854 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 4855 // use the 16-bit encoding or not. 4856 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 4857 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4858 static_cast<ARMOperand*>(Operands[3])->isReg() && 4859 static_cast<ARMOperand*>(Operands[4])->isReg() && 4860 static_cast<ARMOperand*>(Operands[5])->isReg() && 4861 // If the registers aren't low regs, the destination reg isn't the 4862 // same as one of the source regs, or the cc_out operand is zero 4863 // outside of an IT block, we have to use the 32-bit encoding, so 4864 // remove the cc_out operand. 4865 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4866 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4867 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 4868 !inITBlock() || 4869 (static_cast<ARMOperand*>(Operands[3])->getReg() != 4870 static_cast<ARMOperand*>(Operands[5])->getReg() && 4871 static_cast<ARMOperand*>(Operands[3])->getReg() != 4872 static_cast<ARMOperand*>(Operands[4])->getReg()))) 4873 return true; 4874 4875 // Also check the 'mul' syntax variant that doesn't specify an explicit 4876 // destination register. 4877 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 4878 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4879 static_cast<ARMOperand*>(Operands[3])->isReg() && 4880 static_cast<ARMOperand*>(Operands[4])->isReg() && 4881 // If the registers aren't low regs or the cc_out operand is zero 4882 // outside of an IT block, we have to use the 32-bit encoding, so 4883 // remove the cc_out operand. 4884 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4885 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4886 !inITBlock())) 4887 return true; 4888 4889 4890 4891 // Register-register 'add/sub' for thumb does not have a cc_out operand 4892 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4893 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4894 // right, this will result in better diagnostics (which operand is off) 4895 // anyway. 4896 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4897 (Operands.size() == 5 || Operands.size() == 6) && 4898 static_cast<ARMOperand*>(Operands[3])->isReg() && 4899 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 4900 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4901 (static_cast<ARMOperand*>(Operands[4])->isImm() || 4902 (Operands.size() == 6 && 4903 static_cast<ARMOperand*>(Operands[5])->isImm()))) 4904 return true; 4905 4906 return false; 4907 } 4908 4909 static bool isDataTypeToken(StringRef Tok) { 4910 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 4911 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 4912 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 4913 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 4914 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 4915 Tok == ".f" || Tok == ".d"; 4916 } 4917 4918 // FIXME: This bit should probably be handled via an explicit match class 4919 // in the .td files that matches the suffix instead of having it be 4920 // a literal string token the way it is now. 4921 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 4922 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 4923 } 4924 4925 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features); 4926 /// Parse an arm instruction mnemonic followed by its operands. 4927 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4928 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4929 // Apply mnemonic aliases before doing anything else, as the destination 4930 // mnemnonic may include suffices and we want to handle them normally. 4931 // The generic tblgen'erated code does this later, at the start of 4932 // MatchInstructionImpl(), but that's too late for aliases that include 4933 // any sort of suffix. 4934 unsigned AvailableFeatures = getAvailableFeatures(); 4935 applyMnemonicAliases(Name, AvailableFeatures); 4936 4937 // First check for the ARM-specific .req directive. 4938 if (Parser.getTok().is(AsmToken::Identifier) && 4939 Parser.getTok().getIdentifier() == ".req") { 4940 parseDirectiveReq(Name, NameLoc); 4941 // We always return 'error' for this, as we're done with this 4942 // statement and don't need to match the 'instruction." 4943 return true; 4944 } 4945 4946 // Create the leading tokens for the mnemonic, split by '.' characters. 4947 size_t Start = 0, Next = Name.find('.'); 4948 StringRef Mnemonic = Name.slice(Start, Next); 4949 4950 // Split out the predication code and carry setting flag from the mnemonic. 4951 unsigned PredicationCode; 4952 unsigned ProcessorIMod; 4953 bool CarrySetting; 4954 StringRef ITMask; 4955 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 4956 ProcessorIMod, ITMask); 4957 4958 // In Thumb1, only the branch (B) instruction can be predicated. 4959 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 4960 Parser.EatToEndOfStatement(); 4961 return Error(NameLoc, "conditional execution not supported in Thumb1"); 4962 } 4963 4964 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4965 4966 // Handle the IT instruction ITMask. Convert it to a bitmask. This 4967 // is the mask as it will be for the IT encoding if the conditional 4968 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 4969 // where the conditional bit0 is zero, the instruction post-processing 4970 // will adjust the mask accordingly. 4971 if (Mnemonic == "it") { 4972 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 4973 if (ITMask.size() > 3) { 4974 Parser.EatToEndOfStatement(); 4975 return Error(Loc, "too many conditions on IT instruction"); 4976 } 4977 unsigned Mask = 8; 4978 for (unsigned i = ITMask.size(); i != 0; --i) { 4979 char pos = ITMask[i - 1]; 4980 if (pos != 't' && pos != 'e') { 4981 Parser.EatToEndOfStatement(); 4982 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 4983 } 4984 Mask >>= 1; 4985 if (ITMask[i - 1] == 't') 4986 Mask |= 8; 4987 } 4988 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 4989 } 4990 4991 // FIXME: This is all a pretty gross hack. We should automatically handle 4992 // optional operands like this via tblgen. 4993 4994 // Next, add the CCOut and ConditionCode operands, if needed. 4995 // 4996 // For mnemonics which can ever incorporate a carry setting bit or predication 4997 // code, our matching model involves us always generating CCOut and 4998 // ConditionCode operands to match the mnemonic "as written" and then we let 4999 // the matcher deal with finding the right instruction or generating an 5000 // appropriate error. 5001 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5002 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 5003 5004 // If we had a carry-set on an instruction that can't do that, issue an 5005 // error. 5006 if (!CanAcceptCarrySet && CarrySetting) { 5007 Parser.EatToEndOfStatement(); 5008 return Error(NameLoc, "instruction '" + Mnemonic + 5009 "' can not set flags, but 's' suffix specified"); 5010 } 5011 // If we had a predication code on an instruction that can't do that, issue an 5012 // error. 5013 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5014 Parser.EatToEndOfStatement(); 5015 return Error(NameLoc, "instruction '" + Mnemonic + 5016 "' is not predicable, but condition code specified"); 5017 } 5018 5019 // Add the carry setting operand, if necessary. 5020 if (CanAcceptCarrySet) { 5021 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5022 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5023 Loc)); 5024 } 5025 5026 // Add the predication code operand, if necessary. 5027 if (CanAcceptPredicationCode) { 5028 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5029 CarrySetting); 5030 Operands.push_back(ARMOperand::CreateCondCode( 5031 ARMCC::CondCodes(PredicationCode), Loc)); 5032 } 5033 5034 // Add the processor imod operand, if necessary. 5035 if (ProcessorIMod) { 5036 Operands.push_back(ARMOperand::CreateImm( 5037 MCConstantExpr::Create(ProcessorIMod, getContext()), 5038 NameLoc, NameLoc)); 5039 } 5040 5041 // Add the remaining tokens in the mnemonic. 5042 while (Next != StringRef::npos) { 5043 Start = Next; 5044 Next = Name.find('.', Start + 1); 5045 StringRef ExtraToken = Name.slice(Start, Next); 5046 5047 // Some NEON instructions have an optional datatype suffix that is 5048 // completely ignored. Check for that. 5049 if (isDataTypeToken(ExtraToken) && 5050 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5051 continue; 5052 5053 if (ExtraToken != ".n") { 5054 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5055 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5056 } 5057 } 5058 5059 // Read the remaining operands. 5060 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5061 // Read the first operand. 5062 if (parseOperand(Operands, Mnemonic)) { 5063 Parser.EatToEndOfStatement(); 5064 return true; 5065 } 5066 5067 while (getLexer().is(AsmToken::Comma)) { 5068 Parser.Lex(); // Eat the comma. 5069 5070 // Parse and remember the operand. 5071 if (parseOperand(Operands, Mnemonic)) { 5072 Parser.EatToEndOfStatement(); 5073 return true; 5074 } 5075 } 5076 } 5077 5078 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5079 SMLoc Loc = getLexer().getLoc(); 5080 Parser.EatToEndOfStatement(); 5081 return Error(Loc, "unexpected token in argument list"); 5082 } 5083 5084 Parser.Lex(); // Consume the EndOfStatement 5085 5086 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5087 // do and don't have a cc_out optional-def operand. With some spot-checks 5088 // of the operand list, we can figure out which variant we're trying to 5089 // parse and adjust accordingly before actually matching. We shouldn't ever 5090 // try to remove a cc_out operand that was explicitly set on the the 5091 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5092 // table driven matcher doesn't fit well with the ARM instruction set. 5093 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5094 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5095 Operands.erase(Operands.begin() + 1); 5096 delete Op; 5097 } 5098 5099 // ARM mode 'blx' need special handling, as the register operand version 5100 // is predicable, but the label operand version is not. So, we can't rely 5101 // on the Mnemonic based checking to correctly figure out when to put 5102 // a k_CondCode operand in the list. If we're trying to match the label 5103 // version, remove the k_CondCode operand here. 5104 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5105 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5106 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5107 Operands.erase(Operands.begin() + 1); 5108 delete Op; 5109 } 5110 5111 // The vector-compare-to-zero instructions have a literal token "#0" at 5112 // the end that comes to here as an immediate operand. Convert it to a 5113 // token to play nicely with the matcher. 5114 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 5115 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 5116 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5117 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5118 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5119 if (CE && CE->getValue() == 0) { 5120 Operands.erase(Operands.begin() + 5); 5121 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5122 delete Op; 5123 } 5124 } 5125 // VCMP{E} does the same thing, but with a different operand count. 5126 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 5127 static_cast<ARMOperand*>(Operands[4])->isImm()) { 5128 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 5129 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5130 if (CE && CE->getValue() == 0) { 5131 Operands.erase(Operands.begin() + 4); 5132 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5133 delete Op; 5134 } 5135 } 5136 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 5137 // end. Convert it to a token here. Take care not to convert those 5138 // that should hit the Thumb2 encoding. 5139 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 5140 static_cast<ARMOperand*>(Operands[3])->isReg() && 5141 static_cast<ARMOperand*>(Operands[4])->isReg() && 5142 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5143 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5144 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5145 if (CE && CE->getValue() == 0 && 5146 (isThumbOne() || 5147 // The cc_out operand matches the IT block. 5148 ((inITBlock() != CarrySetting) && 5149 // Neither register operand is a high register. 5150 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 5151 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){ 5152 Operands.erase(Operands.begin() + 5); 5153 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5154 delete Op; 5155 } 5156 } 5157 5158 return false; 5159 } 5160 5161 // Validate context-sensitive operand constraints. 5162 5163 // return 'true' if register list contains non-low GPR registers, 5164 // 'false' otherwise. If Reg is in the register list or is HiReg, set 5165 // 'containsReg' to true. 5166 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5167 unsigned HiReg, bool &containsReg) { 5168 containsReg = false; 5169 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5170 unsigned OpReg = Inst.getOperand(i).getReg(); 5171 if (OpReg == Reg) 5172 containsReg = true; 5173 // Anything other than a low register isn't legal here. 5174 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5175 return true; 5176 } 5177 return false; 5178 } 5179 5180 // Check if the specified regisgter is in the register list of the inst, 5181 // starting at the indicated operand number. 5182 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5183 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5184 unsigned OpReg = Inst.getOperand(i).getReg(); 5185 if (OpReg == Reg) 5186 return true; 5187 } 5188 return false; 5189 } 5190 5191 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around 5192 // the ARMInsts array) instead. Getting that here requires awkward 5193 // API changes, though. Better way? 5194 namespace llvm { 5195 extern const MCInstrDesc ARMInsts[]; 5196 } 5197 static const MCInstrDesc &getInstDesc(unsigned Opcode) { 5198 return ARMInsts[Opcode]; 5199 } 5200 5201 // FIXME: We would really like to be able to tablegen'erate this. 5202 bool ARMAsmParser:: 5203 validateInstruction(MCInst &Inst, 5204 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5205 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5206 SMLoc Loc = Operands[0]->getStartLoc(); 5207 // Check the IT block state first. 5208 // NOTE: BKPT instruction has the interesting property of being 5209 // allowed in IT blocks, but not being predicable. It just always 5210 // executes. 5211 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && 5212 Inst.getOpcode() != ARM::BKPT) { 5213 unsigned bit = 1; 5214 if (ITState.FirstCond) 5215 ITState.FirstCond = false; 5216 else 5217 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5218 // The instruction must be predicable. 5219 if (!MCID.isPredicable()) 5220 return Error(Loc, "instructions in IT block must be predicable"); 5221 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5222 unsigned ITCond = bit ? ITState.Cond : 5223 ARMCC::getOppositeCondition(ITState.Cond); 5224 if (Cond != ITCond) { 5225 // Find the condition code Operand to get its SMLoc information. 5226 SMLoc CondLoc; 5227 for (unsigned i = 1; i < Operands.size(); ++i) 5228 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5229 CondLoc = Operands[i]->getStartLoc(); 5230 return Error(CondLoc, "incorrect condition in IT block; got '" + 5231 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5232 "', but expected '" + 5233 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5234 } 5235 // Check for non-'al' condition codes outside of the IT block. 5236 } else if (isThumbTwo() && MCID.isPredicable() && 5237 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5238 ARMCC::AL && Inst.getOpcode() != ARM::tB && 5239 Inst.getOpcode() != ARM::t2B) 5240 return Error(Loc, "predicated instructions must be in IT block"); 5241 5242 switch (Inst.getOpcode()) { 5243 case ARM::LDRD: 5244 case ARM::LDRD_PRE: 5245 case ARM::LDRD_POST: 5246 case ARM::LDREXD: { 5247 // Rt2 must be Rt + 1. 5248 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 5249 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5250 if (Rt2 != Rt + 1) 5251 return Error(Operands[3]->getStartLoc(), 5252 "destination operands must be sequential"); 5253 return false; 5254 } 5255 case ARM::STRD: { 5256 // Rt2 must be Rt + 1. 5257 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 5258 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5259 if (Rt2 != Rt + 1) 5260 return Error(Operands[3]->getStartLoc(), 5261 "source operands must be sequential"); 5262 return false; 5263 } 5264 case ARM::STRD_PRE: 5265 case ARM::STRD_POST: 5266 case ARM::STREXD: { 5267 // Rt2 must be Rt + 1. 5268 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5269 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 5270 if (Rt2 != Rt + 1) 5271 return Error(Operands[3]->getStartLoc(), 5272 "source operands must be sequential"); 5273 return false; 5274 } 5275 case ARM::SBFX: 5276 case ARM::UBFX: { 5277 // width must be in range [1, 32-lsb] 5278 unsigned lsb = Inst.getOperand(2).getImm(); 5279 unsigned widthm1 = Inst.getOperand(3).getImm(); 5280 if (widthm1 >= 32 - lsb) 5281 return Error(Operands[5]->getStartLoc(), 5282 "bitfield width must be in range [1,32-lsb]"); 5283 return false; 5284 } 5285 case ARM::tLDMIA: { 5286 // If we're parsing Thumb2, the .w variant is available and handles 5287 // most cases that are normally illegal for a Thumb1 LDM 5288 // instruction. We'll make the transformation in processInstruction() 5289 // if necessary. 5290 // 5291 // Thumb LDM instructions are writeback iff the base register is not 5292 // in the register list. 5293 unsigned Rn = Inst.getOperand(0).getReg(); 5294 bool hasWritebackToken = 5295 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5296 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5297 bool listContainsBase; 5298 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5299 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5300 "registers must be in range r0-r7"); 5301 // If we should have writeback, then there should be a '!' token. 5302 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 5303 return Error(Operands[2]->getStartLoc(), 5304 "writeback operator '!' expected"); 5305 // If we should not have writeback, there must not be a '!'. This is 5306 // true even for the 32-bit wide encodings. 5307 if (listContainsBase && hasWritebackToken) 5308 return Error(Operands[3]->getStartLoc(), 5309 "writeback operator '!' not allowed when base register " 5310 "in register list"); 5311 5312 break; 5313 } 5314 case ARM::t2LDMIA_UPD: { 5315 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5316 return Error(Operands[4]->getStartLoc(), 5317 "writeback operator '!' not allowed when base register " 5318 "in register list"); 5319 break; 5320 } 5321 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5322 // so only issue a diagnostic for thumb1. The instructions will be 5323 // switched to the t2 encodings in processInstruction() if necessary. 5324 case ARM::tPOP: { 5325 bool listContainsBase; 5326 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 5327 !isThumbTwo()) 5328 return Error(Operands[2]->getStartLoc(), 5329 "registers must be in range r0-r7 or pc"); 5330 break; 5331 } 5332 case ARM::tPUSH: { 5333 bool listContainsBase; 5334 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 5335 !isThumbTwo()) 5336 return Error(Operands[2]->getStartLoc(), 5337 "registers must be in range r0-r7 or lr"); 5338 break; 5339 } 5340 case ARM::tSTMIA_UPD: { 5341 bool listContainsBase; 5342 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 5343 return Error(Operands[4]->getStartLoc(), 5344 "registers must be in range r0-r7"); 5345 break; 5346 } 5347 case ARM::tADDrSP: { 5348 // If the non-SP source operand and the destination operand are not the 5349 // same, we need thumb2 (for the wide encoding), or we have an error. 5350 if (!isThumbTwo() && 5351 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5352 return Error(Operands[4]->getStartLoc(), 5353 "source register must be the same as destination"); 5354 } 5355 break; 5356 } 5357 } 5358 5359 return false; 5360 } 5361 5362 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5363 switch(Opc) { 5364 default: llvm_unreachable("unexpected opcode!"); 5365 // VST1LN 5366 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5367 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5368 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5369 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5370 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5371 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5372 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5373 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5374 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5375 5376 // VST2LN 5377 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5378 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5379 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5380 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5381 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5382 5383 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5384 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5385 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5386 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5387 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5388 5389 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5390 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5391 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5392 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5393 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5394 5395 // VST3LN 5396 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5397 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5398 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5399 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5400 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5401 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5402 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5403 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5404 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5405 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5406 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5407 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5408 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5409 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5410 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5411 5412 // VST3 5413 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5414 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5415 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5416 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5417 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5418 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5419 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5420 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5421 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5422 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5423 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5424 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5425 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5426 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5427 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5428 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5429 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5430 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5431 5432 // VST4LN 5433 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5434 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5435 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5436 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5437 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5438 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5439 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5440 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5441 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5442 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5443 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5444 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5445 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5446 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5447 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5448 5449 // VST4 5450 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5451 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5452 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5453 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5454 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5455 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5456 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5457 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5458 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5459 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5460 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5461 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5462 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5463 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5464 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5465 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5466 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5467 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5468 } 5469 } 5470 5471 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5472 switch(Opc) { 5473 default: llvm_unreachable("unexpected opcode!"); 5474 // VLD1LN 5475 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5476 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5477 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5478 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5479 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5480 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5481 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5482 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5483 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5484 5485 // VLD2LN 5486 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5487 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5488 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5489 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5490 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5491 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5492 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5493 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5494 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5495 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5496 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5497 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5498 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5499 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5500 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5501 5502 // VLD3DUP 5503 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5504 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5505 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5506 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5507 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5508 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5509 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5510 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5511 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5512 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5513 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5514 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5515 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5516 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5517 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5518 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5519 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5520 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5521 5522 // VLD3LN 5523 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5524 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5525 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5526 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5527 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5528 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5529 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5530 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5531 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5532 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5533 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5534 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5535 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5536 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5537 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5538 5539 // VLD3 5540 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5541 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5542 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5543 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5544 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5545 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5546 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5547 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5548 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5549 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5550 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5551 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5552 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5553 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5554 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5555 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5556 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5557 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5558 5559 // VLD4LN 5560 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5561 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5562 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5563 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5564 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5565 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5566 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5567 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5568 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5569 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5570 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5571 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5572 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5573 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5574 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5575 5576 // VLD4DUP 5577 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5578 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5579 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5580 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5581 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5582 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5583 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5584 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5585 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5586 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5587 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5588 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5589 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5590 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5591 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5592 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5593 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5594 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5595 5596 // VLD4 5597 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5598 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5599 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5600 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5601 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5602 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5603 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5604 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5605 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5606 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5607 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5608 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5609 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 5610 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 5611 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 5612 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 5613 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 5614 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 5615 } 5616 } 5617 5618 bool ARMAsmParser:: 5619 processInstruction(MCInst &Inst, 5620 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5621 switch (Inst.getOpcode()) { 5622 // Aliases for alternate PC+imm syntax of LDR instructions. 5623 case ARM::t2LDRpcrel: 5624 Inst.setOpcode(ARM::t2LDRpci); 5625 return true; 5626 case ARM::t2LDRBpcrel: 5627 Inst.setOpcode(ARM::t2LDRBpci); 5628 return true; 5629 case ARM::t2LDRHpcrel: 5630 Inst.setOpcode(ARM::t2LDRHpci); 5631 return true; 5632 case ARM::t2LDRSBpcrel: 5633 Inst.setOpcode(ARM::t2LDRSBpci); 5634 return true; 5635 case ARM::t2LDRSHpcrel: 5636 Inst.setOpcode(ARM::t2LDRSHpci); 5637 return true; 5638 // Handle NEON VST complex aliases. 5639 case ARM::VST1LNdWB_register_Asm_8: 5640 case ARM::VST1LNdWB_register_Asm_16: 5641 case ARM::VST1LNdWB_register_Asm_32: { 5642 MCInst TmpInst; 5643 // Shuffle the operands around so the lane index operand is in the 5644 // right place. 5645 unsigned Spacing; 5646 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5647 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5648 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5649 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5650 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5651 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5652 TmpInst.addOperand(Inst.getOperand(1)); // lane 5653 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5654 TmpInst.addOperand(Inst.getOperand(6)); 5655 Inst = TmpInst; 5656 return true; 5657 } 5658 5659 case ARM::VST2LNdWB_register_Asm_8: 5660 case ARM::VST2LNdWB_register_Asm_16: 5661 case ARM::VST2LNdWB_register_Asm_32: 5662 case ARM::VST2LNqWB_register_Asm_16: 5663 case ARM::VST2LNqWB_register_Asm_32: { 5664 MCInst TmpInst; 5665 // Shuffle the operands around so the lane index operand is in the 5666 // right place. 5667 unsigned Spacing; 5668 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5669 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5670 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5671 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5672 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5673 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5674 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5675 Spacing)); 5676 TmpInst.addOperand(Inst.getOperand(1)); // lane 5677 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5678 TmpInst.addOperand(Inst.getOperand(6)); 5679 Inst = TmpInst; 5680 return true; 5681 } 5682 5683 case ARM::VST3LNdWB_register_Asm_8: 5684 case ARM::VST3LNdWB_register_Asm_16: 5685 case ARM::VST3LNdWB_register_Asm_32: 5686 case ARM::VST3LNqWB_register_Asm_16: 5687 case ARM::VST3LNqWB_register_Asm_32: { 5688 MCInst TmpInst; 5689 // Shuffle the operands around so the lane index operand is in the 5690 // right place. 5691 unsigned Spacing; 5692 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5693 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5694 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5695 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5696 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5697 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5698 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5699 Spacing)); 5700 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5701 Spacing * 2)); 5702 TmpInst.addOperand(Inst.getOperand(1)); // lane 5703 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5704 TmpInst.addOperand(Inst.getOperand(6)); 5705 Inst = TmpInst; 5706 return true; 5707 } 5708 5709 case ARM::VST4LNdWB_register_Asm_8: 5710 case ARM::VST4LNdWB_register_Asm_16: 5711 case ARM::VST4LNdWB_register_Asm_32: 5712 case ARM::VST4LNqWB_register_Asm_16: 5713 case ARM::VST4LNqWB_register_Asm_32: { 5714 MCInst TmpInst; 5715 // Shuffle the operands around so the lane index operand is in the 5716 // right place. 5717 unsigned Spacing; 5718 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5719 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5720 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5721 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5722 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5723 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5724 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5725 Spacing)); 5726 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5727 Spacing * 2)); 5728 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5729 Spacing * 3)); 5730 TmpInst.addOperand(Inst.getOperand(1)); // lane 5731 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5732 TmpInst.addOperand(Inst.getOperand(6)); 5733 Inst = TmpInst; 5734 return true; 5735 } 5736 5737 case ARM::VST1LNdWB_fixed_Asm_8: 5738 case ARM::VST1LNdWB_fixed_Asm_16: 5739 case ARM::VST1LNdWB_fixed_Asm_32: { 5740 MCInst TmpInst; 5741 // Shuffle the operands around so the lane index operand is in the 5742 // right place. 5743 unsigned Spacing; 5744 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5745 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5746 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5747 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5748 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5749 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5750 TmpInst.addOperand(Inst.getOperand(1)); // lane 5751 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5752 TmpInst.addOperand(Inst.getOperand(5)); 5753 Inst = TmpInst; 5754 return true; 5755 } 5756 5757 case ARM::VST2LNdWB_fixed_Asm_8: 5758 case ARM::VST2LNdWB_fixed_Asm_16: 5759 case ARM::VST2LNdWB_fixed_Asm_32: 5760 case ARM::VST2LNqWB_fixed_Asm_16: 5761 case ARM::VST2LNqWB_fixed_Asm_32: { 5762 MCInst TmpInst; 5763 // Shuffle the operands around so the lane index operand is in the 5764 // right place. 5765 unsigned Spacing; 5766 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5767 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5768 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5769 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5770 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5771 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5772 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5773 Spacing)); 5774 TmpInst.addOperand(Inst.getOperand(1)); // lane 5775 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5776 TmpInst.addOperand(Inst.getOperand(5)); 5777 Inst = TmpInst; 5778 return true; 5779 } 5780 5781 case ARM::VST3LNdWB_fixed_Asm_8: 5782 case ARM::VST3LNdWB_fixed_Asm_16: 5783 case ARM::VST3LNdWB_fixed_Asm_32: 5784 case ARM::VST3LNqWB_fixed_Asm_16: 5785 case ARM::VST3LNqWB_fixed_Asm_32: { 5786 MCInst TmpInst; 5787 // Shuffle the operands around so the lane index operand is in the 5788 // right place. 5789 unsigned Spacing; 5790 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5791 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5792 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5793 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5794 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5795 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5796 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5797 Spacing)); 5798 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5799 Spacing * 2)); 5800 TmpInst.addOperand(Inst.getOperand(1)); // lane 5801 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5802 TmpInst.addOperand(Inst.getOperand(5)); 5803 Inst = TmpInst; 5804 return true; 5805 } 5806 5807 case ARM::VST4LNdWB_fixed_Asm_8: 5808 case ARM::VST4LNdWB_fixed_Asm_16: 5809 case ARM::VST4LNdWB_fixed_Asm_32: 5810 case ARM::VST4LNqWB_fixed_Asm_16: 5811 case ARM::VST4LNqWB_fixed_Asm_32: { 5812 MCInst TmpInst; 5813 // Shuffle the operands around so the lane index operand is in the 5814 // right place. 5815 unsigned Spacing; 5816 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5817 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5818 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5819 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5820 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5821 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5822 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5823 Spacing)); 5824 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5825 Spacing * 2)); 5826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5827 Spacing * 3)); 5828 TmpInst.addOperand(Inst.getOperand(1)); // lane 5829 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5830 TmpInst.addOperand(Inst.getOperand(5)); 5831 Inst = TmpInst; 5832 return true; 5833 } 5834 5835 case ARM::VST1LNdAsm_8: 5836 case ARM::VST1LNdAsm_16: 5837 case ARM::VST1LNdAsm_32: { 5838 MCInst TmpInst; 5839 // Shuffle the operands around so the lane index operand is in the 5840 // right place. 5841 unsigned Spacing; 5842 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5843 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5844 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5845 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5846 TmpInst.addOperand(Inst.getOperand(1)); // lane 5847 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5848 TmpInst.addOperand(Inst.getOperand(5)); 5849 Inst = TmpInst; 5850 return true; 5851 } 5852 5853 case ARM::VST2LNdAsm_8: 5854 case ARM::VST2LNdAsm_16: 5855 case ARM::VST2LNdAsm_32: 5856 case ARM::VST2LNqAsm_16: 5857 case ARM::VST2LNqAsm_32: { 5858 MCInst TmpInst; 5859 // Shuffle the operands around so the lane index operand is in the 5860 // right place. 5861 unsigned Spacing; 5862 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5863 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5864 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5865 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5866 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5867 Spacing)); 5868 TmpInst.addOperand(Inst.getOperand(1)); // lane 5869 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5870 TmpInst.addOperand(Inst.getOperand(5)); 5871 Inst = TmpInst; 5872 return true; 5873 } 5874 5875 case ARM::VST3LNdAsm_8: 5876 case ARM::VST3LNdAsm_16: 5877 case ARM::VST3LNdAsm_32: 5878 case ARM::VST3LNqAsm_16: 5879 case ARM::VST3LNqAsm_32: { 5880 MCInst TmpInst; 5881 // Shuffle the operands around so the lane index operand is in the 5882 // right place. 5883 unsigned Spacing; 5884 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5885 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5886 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5887 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5889 Spacing)); 5890 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5891 Spacing * 2)); 5892 TmpInst.addOperand(Inst.getOperand(1)); // lane 5893 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5894 TmpInst.addOperand(Inst.getOperand(5)); 5895 Inst = TmpInst; 5896 return true; 5897 } 5898 5899 case ARM::VST4LNdAsm_8: 5900 case ARM::VST4LNdAsm_16: 5901 case ARM::VST4LNdAsm_32: 5902 case ARM::VST4LNqAsm_16: 5903 case ARM::VST4LNqAsm_32: { 5904 MCInst TmpInst; 5905 // Shuffle the operands around so the lane index operand is in the 5906 // right place. 5907 unsigned Spacing; 5908 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5909 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5910 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5911 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5912 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5913 Spacing)); 5914 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5915 Spacing * 2)); 5916 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5917 Spacing * 3)); 5918 TmpInst.addOperand(Inst.getOperand(1)); // lane 5919 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5920 TmpInst.addOperand(Inst.getOperand(5)); 5921 Inst = TmpInst; 5922 return true; 5923 } 5924 5925 // Handle NEON VLD complex aliases. 5926 case ARM::VLD1LNdWB_register_Asm_8: 5927 case ARM::VLD1LNdWB_register_Asm_16: 5928 case ARM::VLD1LNdWB_register_Asm_32: { 5929 MCInst TmpInst; 5930 // Shuffle the operands around so the lane index operand is in the 5931 // right place. 5932 unsigned Spacing; 5933 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5934 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5935 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5936 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5937 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5938 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5939 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5940 TmpInst.addOperand(Inst.getOperand(1)); // lane 5941 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5942 TmpInst.addOperand(Inst.getOperand(6)); 5943 Inst = TmpInst; 5944 return true; 5945 } 5946 5947 case ARM::VLD2LNdWB_register_Asm_8: 5948 case ARM::VLD2LNdWB_register_Asm_16: 5949 case ARM::VLD2LNdWB_register_Asm_32: 5950 case ARM::VLD2LNqWB_register_Asm_16: 5951 case ARM::VLD2LNqWB_register_Asm_32: { 5952 MCInst TmpInst; 5953 // Shuffle the operands around so the lane index operand is in the 5954 // right place. 5955 unsigned Spacing; 5956 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5957 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5958 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5959 Spacing)); 5960 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5961 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5962 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5963 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5964 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5965 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5966 Spacing)); 5967 TmpInst.addOperand(Inst.getOperand(1)); // lane 5968 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5969 TmpInst.addOperand(Inst.getOperand(6)); 5970 Inst = TmpInst; 5971 return true; 5972 } 5973 5974 case ARM::VLD3LNdWB_register_Asm_8: 5975 case ARM::VLD3LNdWB_register_Asm_16: 5976 case ARM::VLD3LNdWB_register_Asm_32: 5977 case ARM::VLD3LNqWB_register_Asm_16: 5978 case ARM::VLD3LNqWB_register_Asm_32: { 5979 MCInst TmpInst; 5980 // Shuffle the operands around so the lane index operand is in the 5981 // right place. 5982 unsigned Spacing; 5983 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5984 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5985 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5986 Spacing)); 5987 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5988 Spacing * 2)); 5989 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5990 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5991 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5992 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5993 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5994 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5995 Spacing)); 5996 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5997 Spacing * 2)); 5998 TmpInst.addOperand(Inst.getOperand(1)); // lane 5999 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6000 TmpInst.addOperand(Inst.getOperand(6)); 6001 Inst = TmpInst; 6002 return true; 6003 } 6004 6005 case ARM::VLD4LNdWB_register_Asm_8: 6006 case ARM::VLD4LNdWB_register_Asm_16: 6007 case ARM::VLD4LNdWB_register_Asm_32: 6008 case ARM::VLD4LNqWB_register_Asm_16: 6009 case ARM::VLD4LNqWB_register_Asm_32: { 6010 MCInst TmpInst; 6011 // Shuffle the operands around so the lane index operand is in the 6012 // right place. 6013 unsigned Spacing; 6014 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6015 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6016 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6017 Spacing)); 6018 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6019 Spacing * 2)); 6020 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6021 Spacing * 3)); 6022 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6023 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6024 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6025 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6026 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6027 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6028 Spacing)); 6029 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6030 Spacing * 2)); 6031 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6032 Spacing * 3)); 6033 TmpInst.addOperand(Inst.getOperand(1)); // lane 6034 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6035 TmpInst.addOperand(Inst.getOperand(6)); 6036 Inst = TmpInst; 6037 return true; 6038 } 6039 6040 case ARM::VLD1LNdWB_fixed_Asm_8: 6041 case ARM::VLD1LNdWB_fixed_Asm_16: 6042 case ARM::VLD1LNdWB_fixed_Asm_32: { 6043 MCInst TmpInst; 6044 // Shuffle the operands around so the lane index operand is in the 6045 // right place. 6046 unsigned Spacing; 6047 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6048 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6049 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6050 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6051 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6052 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6053 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6054 TmpInst.addOperand(Inst.getOperand(1)); // lane 6055 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6056 TmpInst.addOperand(Inst.getOperand(5)); 6057 Inst = TmpInst; 6058 return true; 6059 } 6060 6061 case ARM::VLD2LNdWB_fixed_Asm_8: 6062 case ARM::VLD2LNdWB_fixed_Asm_16: 6063 case ARM::VLD2LNdWB_fixed_Asm_32: 6064 case ARM::VLD2LNqWB_fixed_Asm_16: 6065 case ARM::VLD2LNqWB_fixed_Asm_32: { 6066 MCInst TmpInst; 6067 // Shuffle the operands around so the lane index operand is in the 6068 // right place. 6069 unsigned Spacing; 6070 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6071 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6072 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6073 Spacing)); 6074 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6075 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6076 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6077 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6078 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6079 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6080 Spacing)); 6081 TmpInst.addOperand(Inst.getOperand(1)); // lane 6082 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6083 TmpInst.addOperand(Inst.getOperand(5)); 6084 Inst = TmpInst; 6085 return true; 6086 } 6087 6088 case ARM::VLD3LNdWB_fixed_Asm_8: 6089 case ARM::VLD3LNdWB_fixed_Asm_16: 6090 case ARM::VLD3LNdWB_fixed_Asm_32: 6091 case ARM::VLD3LNqWB_fixed_Asm_16: 6092 case ARM::VLD3LNqWB_fixed_Asm_32: { 6093 MCInst TmpInst; 6094 // Shuffle the operands around so the lane index operand is in the 6095 // right place. 6096 unsigned Spacing; 6097 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6098 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6099 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6100 Spacing)); 6101 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6102 Spacing * 2)); 6103 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6104 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6105 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6106 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6107 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6108 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6109 Spacing)); 6110 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6111 Spacing * 2)); 6112 TmpInst.addOperand(Inst.getOperand(1)); // lane 6113 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6114 TmpInst.addOperand(Inst.getOperand(5)); 6115 Inst = TmpInst; 6116 return true; 6117 } 6118 6119 case ARM::VLD4LNdWB_fixed_Asm_8: 6120 case ARM::VLD4LNdWB_fixed_Asm_16: 6121 case ARM::VLD4LNdWB_fixed_Asm_32: 6122 case ARM::VLD4LNqWB_fixed_Asm_16: 6123 case ARM::VLD4LNqWB_fixed_Asm_32: { 6124 MCInst TmpInst; 6125 // Shuffle the operands around so the lane index operand is in the 6126 // right place. 6127 unsigned Spacing; 6128 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6129 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6130 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6131 Spacing)); 6132 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6133 Spacing * 2)); 6134 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6135 Spacing * 3)); 6136 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6137 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6138 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6139 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6140 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6141 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6142 Spacing)); 6143 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6144 Spacing * 2)); 6145 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6146 Spacing * 3)); 6147 TmpInst.addOperand(Inst.getOperand(1)); // lane 6148 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6149 TmpInst.addOperand(Inst.getOperand(5)); 6150 Inst = TmpInst; 6151 return true; 6152 } 6153 6154 case ARM::VLD1LNdAsm_8: 6155 case ARM::VLD1LNdAsm_16: 6156 case ARM::VLD1LNdAsm_32: { 6157 MCInst TmpInst; 6158 // Shuffle the operands around so the lane index operand is in the 6159 // right place. 6160 unsigned Spacing; 6161 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6162 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6163 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6164 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6165 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6166 TmpInst.addOperand(Inst.getOperand(1)); // lane 6167 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6168 TmpInst.addOperand(Inst.getOperand(5)); 6169 Inst = TmpInst; 6170 return true; 6171 } 6172 6173 case ARM::VLD2LNdAsm_8: 6174 case ARM::VLD2LNdAsm_16: 6175 case ARM::VLD2LNdAsm_32: 6176 case ARM::VLD2LNqAsm_16: 6177 case ARM::VLD2LNqAsm_32: { 6178 MCInst TmpInst; 6179 // Shuffle the operands around so the lane index operand is in the 6180 // right place. 6181 unsigned Spacing; 6182 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6183 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6184 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6185 Spacing)); 6186 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6187 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6188 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6189 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6190 Spacing)); 6191 TmpInst.addOperand(Inst.getOperand(1)); // lane 6192 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6193 TmpInst.addOperand(Inst.getOperand(5)); 6194 Inst = TmpInst; 6195 return true; 6196 } 6197 6198 case ARM::VLD3LNdAsm_8: 6199 case ARM::VLD3LNdAsm_16: 6200 case ARM::VLD3LNdAsm_32: 6201 case ARM::VLD3LNqAsm_16: 6202 case ARM::VLD3LNqAsm_32: { 6203 MCInst TmpInst; 6204 // Shuffle the operands around so the lane index operand is in the 6205 // right place. 6206 unsigned Spacing; 6207 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6208 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6209 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6210 Spacing)); 6211 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6212 Spacing * 2)); 6213 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6214 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6215 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6216 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6217 Spacing)); 6218 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6219 Spacing * 2)); 6220 TmpInst.addOperand(Inst.getOperand(1)); // lane 6221 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6222 TmpInst.addOperand(Inst.getOperand(5)); 6223 Inst = TmpInst; 6224 return true; 6225 } 6226 6227 case ARM::VLD4LNdAsm_8: 6228 case ARM::VLD4LNdAsm_16: 6229 case ARM::VLD4LNdAsm_32: 6230 case ARM::VLD4LNqAsm_16: 6231 case ARM::VLD4LNqAsm_32: { 6232 MCInst TmpInst; 6233 // Shuffle the operands around so the lane index operand is in the 6234 // right place. 6235 unsigned Spacing; 6236 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6237 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6238 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6239 Spacing)); 6240 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6241 Spacing * 2)); 6242 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6243 Spacing * 3)); 6244 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6245 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6246 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6247 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6248 Spacing)); 6249 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6250 Spacing * 2)); 6251 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6252 Spacing * 3)); 6253 TmpInst.addOperand(Inst.getOperand(1)); // lane 6254 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6255 TmpInst.addOperand(Inst.getOperand(5)); 6256 Inst = TmpInst; 6257 return true; 6258 } 6259 6260 // VLD3DUP single 3-element structure to all lanes instructions. 6261 case ARM::VLD3DUPdAsm_8: 6262 case ARM::VLD3DUPdAsm_16: 6263 case ARM::VLD3DUPdAsm_32: 6264 case ARM::VLD3DUPqAsm_8: 6265 case ARM::VLD3DUPqAsm_16: 6266 case ARM::VLD3DUPqAsm_32: { 6267 MCInst TmpInst; 6268 unsigned Spacing; 6269 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6270 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6271 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6272 Spacing)); 6273 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6274 Spacing * 2)); 6275 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6276 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6277 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6278 TmpInst.addOperand(Inst.getOperand(4)); 6279 Inst = TmpInst; 6280 return true; 6281 } 6282 6283 case ARM::VLD3DUPdWB_fixed_Asm_8: 6284 case ARM::VLD3DUPdWB_fixed_Asm_16: 6285 case ARM::VLD3DUPdWB_fixed_Asm_32: 6286 case ARM::VLD3DUPqWB_fixed_Asm_8: 6287 case ARM::VLD3DUPqWB_fixed_Asm_16: 6288 case ARM::VLD3DUPqWB_fixed_Asm_32: { 6289 MCInst TmpInst; 6290 unsigned Spacing; 6291 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6292 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6293 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6294 Spacing)); 6295 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6296 Spacing * 2)); 6297 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6298 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6299 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6300 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6301 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6302 TmpInst.addOperand(Inst.getOperand(4)); 6303 Inst = TmpInst; 6304 return true; 6305 } 6306 6307 case ARM::VLD3DUPdWB_register_Asm_8: 6308 case ARM::VLD3DUPdWB_register_Asm_16: 6309 case ARM::VLD3DUPdWB_register_Asm_32: 6310 case ARM::VLD3DUPqWB_register_Asm_8: 6311 case ARM::VLD3DUPqWB_register_Asm_16: 6312 case ARM::VLD3DUPqWB_register_Asm_32: { 6313 MCInst TmpInst; 6314 unsigned Spacing; 6315 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6316 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6317 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6318 Spacing)); 6319 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6320 Spacing * 2)); 6321 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6322 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6323 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6324 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6325 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6326 TmpInst.addOperand(Inst.getOperand(5)); 6327 Inst = TmpInst; 6328 return true; 6329 } 6330 6331 // VLD3 multiple 3-element structure instructions. 6332 case ARM::VLD3dAsm_8: 6333 case ARM::VLD3dAsm_16: 6334 case ARM::VLD3dAsm_32: 6335 case ARM::VLD3qAsm_8: 6336 case ARM::VLD3qAsm_16: 6337 case ARM::VLD3qAsm_32: { 6338 MCInst TmpInst; 6339 unsigned Spacing; 6340 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6341 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6342 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6343 Spacing)); 6344 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6345 Spacing * 2)); 6346 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6347 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6348 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6349 TmpInst.addOperand(Inst.getOperand(4)); 6350 Inst = TmpInst; 6351 return true; 6352 } 6353 6354 case ARM::VLD3dWB_fixed_Asm_8: 6355 case ARM::VLD3dWB_fixed_Asm_16: 6356 case ARM::VLD3dWB_fixed_Asm_32: 6357 case ARM::VLD3qWB_fixed_Asm_8: 6358 case ARM::VLD3qWB_fixed_Asm_16: 6359 case ARM::VLD3qWB_fixed_Asm_32: { 6360 MCInst TmpInst; 6361 unsigned Spacing; 6362 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6363 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6364 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6365 Spacing)); 6366 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6367 Spacing * 2)); 6368 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6369 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6370 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6371 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6372 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6373 TmpInst.addOperand(Inst.getOperand(4)); 6374 Inst = TmpInst; 6375 return true; 6376 } 6377 6378 case ARM::VLD3dWB_register_Asm_8: 6379 case ARM::VLD3dWB_register_Asm_16: 6380 case ARM::VLD3dWB_register_Asm_32: 6381 case ARM::VLD3qWB_register_Asm_8: 6382 case ARM::VLD3qWB_register_Asm_16: 6383 case ARM::VLD3qWB_register_Asm_32: { 6384 MCInst TmpInst; 6385 unsigned Spacing; 6386 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6387 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6388 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6389 Spacing)); 6390 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6391 Spacing * 2)); 6392 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6393 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6394 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6395 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6396 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6397 TmpInst.addOperand(Inst.getOperand(5)); 6398 Inst = TmpInst; 6399 return true; 6400 } 6401 6402 // VLD4DUP single 3-element structure to all lanes instructions. 6403 case ARM::VLD4DUPdAsm_8: 6404 case ARM::VLD4DUPdAsm_16: 6405 case ARM::VLD4DUPdAsm_32: 6406 case ARM::VLD4DUPqAsm_8: 6407 case ARM::VLD4DUPqAsm_16: 6408 case ARM::VLD4DUPqAsm_32: { 6409 MCInst TmpInst; 6410 unsigned Spacing; 6411 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6412 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6413 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6414 Spacing)); 6415 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6416 Spacing * 2)); 6417 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6418 Spacing * 3)); 6419 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6420 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6421 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6422 TmpInst.addOperand(Inst.getOperand(4)); 6423 Inst = TmpInst; 6424 return true; 6425 } 6426 6427 case ARM::VLD4DUPdWB_fixed_Asm_8: 6428 case ARM::VLD4DUPdWB_fixed_Asm_16: 6429 case ARM::VLD4DUPdWB_fixed_Asm_32: 6430 case ARM::VLD4DUPqWB_fixed_Asm_8: 6431 case ARM::VLD4DUPqWB_fixed_Asm_16: 6432 case ARM::VLD4DUPqWB_fixed_Asm_32: { 6433 MCInst TmpInst; 6434 unsigned Spacing; 6435 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6436 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6437 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6438 Spacing)); 6439 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6440 Spacing * 2)); 6441 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6442 Spacing * 3)); 6443 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6444 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6445 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6446 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6447 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6448 TmpInst.addOperand(Inst.getOperand(4)); 6449 Inst = TmpInst; 6450 return true; 6451 } 6452 6453 case ARM::VLD4DUPdWB_register_Asm_8: 6454 case ARM::VLD4DUPdWB_register_Asm_16: 6455 case ARM::VLD4DUPdWB_register_Asm_32: 6456 case ARM::VLD4DUPqWB_register_Asm_8: 6457 case ARM::VLD4DUPqWB_register_Asm_16: 6458 case ARM::VLD4DUPqWB_register_Asm_32: { 6459 MCInst TmpInst; 6460 unsigned Spacing; 6461 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6462 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6463 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6464 Spacing)); 6465 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6466 Spacing * 2)); 6467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6468 Spacing * 3)); 6469 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6470 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6471 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6472 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6473 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6474 TmpInst.addOperand(Inst.getOperand(5)); 6475 Inst = TmpInst; 6476 return true; 6477 } 6478 6479 // VLD4 multiple 4-element structure instructions. 6480 case ARM::VLD4dAsm_8: 6481 case ARM::VLD4dAsm_16: 6482 case ARM::VLD4dAsm_32: 6483 case ARM::VLD4qAsm_8: 6484 case ARM::VLD4qAsm_16: 6485 case ARM::VLD4qAsm_32: { 6486 MCInst TmpInst; 6487 unsigned Spacing; 6488 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6489 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6490 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6491 Spacing)); 6492 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6493 Spacing * 2)); 6494 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6495 Spacing * 3)); 6496 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6497 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6498 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6499 TmpInst.addOperand(Inst.getOperand(4)); 6500 Inst = TmpInst; 6501 return true; 6502 } 6503 6504 case ARM::VLD4dWB_fixed_Asm_8: 6505 case ARM::VLD4dWB_fixed_Asm_16: 6506 case ARM::VLD4dWB_fixed_Asm_32: 6507 case ARM::VLD4qWB_fixed_Asm_8: 6508 case ARM::VLD4qWB_fixed_Asm_16: 6509 case ARM::VLD4qWB_fixed_Asm_32: { 6510 MCInst TmpInst; 6511 unsigned Spacing; 6512 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6513 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6514 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6515 Spacing)); 6516 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6517 Spacing * 2)); 6518 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6519 Spacing * 3)); 6520 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6521 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6522 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6523 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6524 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6525 TmpInst.addOperand(Inst.getOperand(4)); 6526 Inst = TmpInst; 6527 return true; 6528 } 6529 6530 case ARM::VLD4dWB_register_Asm_8: 6531 case ARM::VLD4dWB_register_Asm_16: 6532 case ARM::VLD4dWB_register_Asm_32: 6533 case ARM::VLD4qWB_register_Asm_8: 6534 case ARM::VLD4qWB_register_Asm_16: 6535 case ARM::VLD4qWB_register_Asm_32: { 6536 MCInst TmpInst; 6537 unsigned Spacing; 6538 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6539 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6540 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6541 Spacing)); 6542 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6543 Spacing * 2)); 6544 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6545 Spacing * 3)); 6546 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6547 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6548 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6549 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6550 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6551 TmpInst.addOperand(Inst.getOperand(5)); 6552 Inst = TmpInst; 6553 return true; 6554 } 6555 6556 // VST3 multiple 3-element structure instructions. 6557 case ARM::VST3dAsm_8: 6558 case ARM::VST3dAsm_16: 6559 case ARM::VST3dAsm_32: 6560 case ARM::VST3qAsm_8: 6561 case ARM::VST3qAsm_16: 6562 case ARM::VST3qAsm_32: { 6563 MCInst TmpInst; 6564 unsigned Spacing; 6565 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6566 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6567 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6568 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6569 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6570 Spacing)); 6571 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6572 Spacing * 2)); 6573 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6574 TmpInst.addOperand(Inst.getOperand(4)); 6575 Inst = TmpInst; 6576 return true; 6577 } 6578 6579 case ARM::VST3dWB_fixed_Asm_8: 6580 case ARM::VST3dWB_fixed_Asm_16: 6581 case ARM::VST3dWB_fixed_Asm_32: 6582 case ARM::VST3qWB_fixed_Asm_8: 6583 case ARM::VST3qWB_fixed_Asm_16: 6584 case ARM::VST3qWB_fixed_Asm_32: { 6585 MCInst TmpInst; 6586 unsigned Spacing; 6587 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6588 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6589 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6590 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6591 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6592 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6593 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6594 Spacing)); 6595 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6596 Spacing * 2)); 6597 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6598 TmpInst.addOperand(Inst.getOperand(4)); 6599 Inst = TmpInst; 6600 return true; 6601 } 6602 6603 case ARM::VST3dWB_register_Asm_8: 6604 case ARM::VST3dWB_register_Asm_16: 6605 case ARM::VST3dWB_register_Asm_32: 6606 case ARM::VST3qWB_register_Asm_8: 6607 case ARM::VST3qWB_register_Asm_16: 6608 case ARM::VST3qWB_register_Asm_32: { 6609 MCInst TmpInst; 6610 unsigned Spacing; 6611 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6612 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6613 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6614 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6615 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6616 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6617 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6618 Spacing)); 6619 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6620 Spacing * 2)); 6621 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6622 TmpInst.addOperand(Inst.getOperand(5)); 6623 Inst = TmpInst; 6624 return true; 6625 } 6626 6627 // VST4 multiple 3-element structure instructions. 6628 case ARM::VST4dAsm_8: 6629 case ARM::VST4dAsm_16: 6630 case ARM::VST4dAsm_32: 6631 case ARM::VST4qAsm_8: 6632 case ARM::VST4qAsm_16: 6633 case ARM::VST4qAsm_32: { 6634 MCInst TmpInst; 6635 unsigned Spacing; 6636 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6637 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6638 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6639 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6640 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6641 Spacing)); 6642 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6643 Spacing * 2)); 6644 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6645 Spacing * 3)); 6646 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6647 TmpInst.addOperand(Inst.getOperand(4)); 6648 Inst = TmpInst; 6649 return true; 6650 } 6651 6652 case ARM::VST4dWB_fixed_Asm_8: 6653 case ARM::VST4dWB_fixed_Asm_16: 6654 case ARM::VST4dWB_fixed_Asm_32: 6655 case ARM::VST4qWB_fixed_Asm_8: 6656 case ARM::VST4qWB_fixed_Asm_16: 6657 case ARM::VST4qWB_fixed_Asm_32: { 6658 MCInst TmpInst; 6659 unsigned Spacing; 6660 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6661 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6662 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6663 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6664 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6665 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6666 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6667 Spacing)); 6668 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6669 Spacing * 2)); 6670 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6671 Spacing * 3)); 6672 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6673 TmpInst.addOperand(Inst.getOperand(4)); 6674 Inst = TmpInst; 6675 return true; 6676 } 6677 6678 case ARM::VST4dWB_register_Asm_8: 6679 case ARM::VST4dWB_register_Asm_16: 6680 case ARM::VST4dWB_register_Asm_32: 6681 case ARM::VST4qWB_register_Asm_8: 6682 case ARM::VST4qWB_register_Asm_16: 6683 case ARM::VST4qWB_register_Asm_32: { 6684 MCInst TmpInst; 6685 unsigned Spacing; 6686 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6687 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6688 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6689 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6690 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6691 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6692 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6693 Spacing)); 6694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6695 Spacing * 2)); 6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6697 Spacing * 3)); 6698 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6699 TmpInst.addOperand(Inst.getOperand(5)); 6700 Inst = TmpInst; 6701 return true; 6702 } 6703 6704 // Handle encoding choice for the shift-immediate instructions. 6705 case ARM::t2LSLri: 6706 case ARM::t2LSRri: 6707 case ARM::t2ASRri: { 6708 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6709 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6710 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 6711 !(static_cast<ARMOperand*>(Operands[3])->isToken() && 6712 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 6713 unsigned NewOpc; 6714 switch (Inst.getOpcode()) { 6715 default: llvm_unreachable("unexpected opcode"); 6716 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6717 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6718 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6719 } 6720 // The Thumb1 operands aren't in the same order. Awesome, eh? 6721 MCInst TmpInst; 6722 TmpInst.setOpcode(NewOpc); 6723 TmpInst.addOperand(Inst.getOperand(0)); 6724 TmpInst.addOperand(Inst.getOperand(5)); 6725 TmpInst.addOperand(Inst.getOperand(1)); 6726 TmpInst.addOperand(Inst.getOperand(2)); 6727 TmpInst.addOperand(Inst.getOperand(3)); 6728 TmpInst.addOperand(Inst.getOperand(4)); 6729 Inst = TmpInst; 6730 return true; 6731 } 6732 return false; 6733 } 6734 6735 // Handle the Thumb2 mode MOV complex aliases. 6736 case ARM::t2MOVsr: 6737 case ARM::t2MOVSsr: { 6738 // Which instruction to expand to depends on the CCOut operand and 6739 // whether we're in an IT block if the register operands are low 6740 // registers. 6741 bool isNarrow = false; 6742 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6743 isARMLowRegister(Inst.getOperand(1).getReg()) && 6744 isARMLowRegister(Inst.getOperand(2).getReg()) && 6745 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6746 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 6747 isNarrow = true; 6748 MCInst TmpInst; 6749 unsigned newOpc; 6750 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 6751 default: llvm_unreachable("unexpected opcode!"); 6752 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 6753 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 6754 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 6755 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 6756 } 6757 TmpInst.setOpcode(newOpc); 6758 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6759 if (isNarrow) 6760 TmpInst.addOperand(MCOperand::CreateReg( 6761 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 6762 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6763 TmpInst.addOperand(Inst.getOperand(2)); // Rm 6764 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6765 TmpInst.addOperand(Inst.getOperand(5)); 6766 if (!isNarrow) 6767 TmpInst.addOperand(MCOperand::CreateReg( 6768 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 6769 Inst = TmpInst; 6770 return true; 6771 } 6772 case ARM::t2MOVsi: 6773 case ARM::t2MOVSsi: { 6774 // Which instruction to expand to depends on the CCOut operand and 6775 // whether we're in an IT block if the register operands are low 6776 // registers. 6777 bool isNarrow = false; 6778 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6779 isARMLowRegister(Inst.getOperand(1).getReg()) && 6780 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 6781 isNarrow = true; 6782 MCInst TmpInst; 6783 unsigned newOpc; 6784 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 6785 default: llvm_unreachable("unexpected opcode!"); 6786 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 6787 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 6788 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 6789 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 6790 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 6791 } 6792 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 6793 if (Amount == 32) Amount = 0; 6794 TmpInst.setOpcode(newOpc); 6795 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6796 if (isNarrow) 6797 TmpInst.addOperand(MCOperand::CreateReg( 6798 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6799 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6800 if (newOpc != ARM::t2RRX) 6801 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 6802 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6803 TmpInst.addOperand(Inst.getOperand(4)); 6804 if (!isNarrow) 6805 TmpInst.addOperand(MCOperand::CreateReg( 6806 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6807 Inst = TmpInst; 6808 return true; 6809 } 6810 // Handle the ARM mode MOV complex aliases. 6811 case ARM::ASRr: 6812 case ARM::LSRr: 6813 case ARM::LSLr: 6814 case ARM::RORr: { 6815 ARM_AM::ShiftOpc ShiftTy; 6816 switch(Inst.getOpcode()) { 6817 default: llvm_unreachable("unexpected opcode!"); 6818 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 6819 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 6820 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 6821 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 6822 } 6823 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 6824 MCInst TmpInst; 6825 TmpInst.setOpcode(ARM::MOVsr); 6826 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6827 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6828 TmpInst.addOperand(Inst.getOperand(2)); // Rm 6829 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6830 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6831 TmpInst.addOperand(Inst.getOperand(4)); 6832 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 6833 Inst = TmpInst; 6834 return true; 6835 } 6836 case ARM::ASRi: 6837 case ARM::LSRi: 6838 case ARM::LSLi: 6839 case ARM::RORi: { 6840 ARM_AM::ShiftOpc ShiftTy; 6841 switch(Inst.getOpcode()) { 6842 default: llvm_unreachable("unexpected opcode!"); 6843 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 6844 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 6845 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 6846 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 6847 } 6848 // A shift by zero is a plain MOVr, not a MOVsi. 6849 unsigned Amt = Inst.getOperand(2).getImm(); 6850 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 6851 // A shift by 32 should be encoded as 0 when permitted 6852 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 6853 Amt = 0; 6854 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 6855 MCInst TmpInst; 6856 TmpInst.setOpcode(Opc); 6857 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6858 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6859 if (Opc == ARM::MOVsi) 6860 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6861 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6862 TmpInst.addOperand(Inst.getOperand(4)); 6863 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 6864 Inst = TmpInst; 6865 return true; 6866 } 6867 case ARM::RRXi: { 6868 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 6869 MCInst TmpInst; 6870 TmpInst.setOpcode(ARM::MOVsi); 6871 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6872 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6873 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6874 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6875 TmpInst.addOperand(Inst.getOperand(3)); 6876 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 6877 Inst = TmpInst; 6878 return true; 6879 } 6880 case ARM::t2LDMIA_UPD: { 6881 // If this is a load of a single register, then we should use 6882 // a post-indexed LDR instruction instead, per the ARM ARM. 6883 if (Inst.getNumOperands() != 5) 6884 return false; 6885 MCInst TmpInst; 6886 TmpInst.setOpcode(ARM::t2LDR_POST); 6887 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6888 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6889 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6890 TmpInst.addOperand(MCOperand::CreateImm(4)); 6891 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6892 TmpInst.addOperand(Inst.getOperand(3)); 6893 Inst = TmpInst; 6894 return true; 6895 } 6896 case ARM::t2STMDB_UPD: { 6897 // If this is a store of a single register, then we should use 6898 // a pre-indexed STR instruction instead, per the ARM ARM. 6899 if (Inst.getNumOperands() != 5) 6900 return false; 6901 MCInst TmpInst; 6902 TmpInst.setOpcode(ARM::t2STR_PRE); 6903 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6904 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6905 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6906 TmpInst.addOperand(MCOperand::CreateImm(-4)); 6907 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6908 TmpInst.addOperand(Inst.getOperand(3)); 6909 Inst = TmpInst; 6910 return true; 6911 } 6912 case ARM::LDMIA_UPD: 6913 // If this is a load of a single register via a 'pop', then we should use 6914 // a post-indexed LDR instruction instead, per the ARM ARM. 6915 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 6916 Inst.getNumOperands() == 5) { 6917 MCInst TmpInst; 6918 TmpInst.setOpcode(ARM::LDR_POST_IMM); 6919 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6920 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6921 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6922 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 6923 TmpInst.addOperand(MCOperand::CreateImm(4)); 6924 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6925 TmpInst.addOperand(Inst.getOperand(3)); 6926 Inst = TmpInst; 6927 return true; 6928 } 6929 break; 6930 case ARM::STMDB_UPD: 6931 // If this is a store of a single register via a 'push', then we should use 6932 // a pre-indexed STR instruction instead, per the ARM ARM. 6933 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 6934 Inst.getNumOperands() == 5) { 6935 MCInst TmpInst; 6936 TmpInst.setOpcode(ARM::STR_PRE_IMM); 6937 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6938 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6939 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 6940 TmpInst.addOperand(MCOperand::CreateImm(-4)); 6941 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6942 TmpInst.addOperand(Inst.getOperand(3)); 6943 Inst = TmpInst; 6944 } 6945 break; 6946 case ARM::t2ADDri12: 6947 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 6948 // mnemonic was used (not "addw"), encoding T3 is preferred. 6949 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 6950 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 6951 break; 6952 Inst.setOpcode(ARM::t2ADDri); 6953 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 6954 break; 6955 case ARM::t2SUBri12: 6956 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 6957 // mnemonic was used (not "subw"), encoding T3 is preferred. 6958 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 6959 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 6960 break; 6961 Inst.setOpcode(ARM::t2SUBri); 6962 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 6963 break; 6964 case ARM::tADDi8: 6965 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 6966 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 6967 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 6968 // to encoding T1 if <Rd> is omitted." 6969 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 6970 Inst.setOpcode(ARM::tADDi3); 6971 return true; 6972 } 6973 break; 6974 case ARM::tSUBi8: 6975 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 6976 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 6977 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 6978 // to encoding T1 if <Rd> is omitted." 6979 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 6980 Inst.setOpcode(ARM::tSUBi3); 6981 return true; 6982 } 6983 break; 6984 case ARM::t2ADDri: 6985 case ARM::t2SUBri: { 6986 // If the destination and first source operand are the same, and 6987 // the flags are compatible with the current IT status, use encoding T2 6988 // instead of T3. For compatibility with the system 'as'. Make sure the 6989 // wide encoding wasn't explicit. 6990 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 6991 !isARMLowRegister(Inst.getOperand(0).getReg()) || 6992 (unsigned)Inst.getOperand(2).getImm() > 255 || 6993 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 6994 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 6995 (static_cast<ARMOperand*>(Operands[3])->isToken() && 6996 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 6997 break; 6998 MCInst TmpInst; 6999 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7000 ARM::tADDi8 : ARM::tSUBi8); 7001 TmpInst.addOperand(Inst.getOperand(0)); 7002 TmpInst.addOperand(Inst.getOperand(5)); 7003 TmpInst.addOperand(Inst.getOperand(0)); 7004 TmpInst.addOperand(Inst.getOperand(2)); 7005 TmpInst.addOperand(Inst.getOperand(3)); 7006 TmpInst.addOperand(Inst.getOperand(4)); 7007 Inst = TmpInst; 7008 return true; 7009 } 7010 case ARM::t2ADDrr: { 7011 // If the destination and first source operand are the same, and 7012 // there's no setting of the flags, use encoding T2 instead of T3. 7013 // Note that this is only for ADD, not SUB. This mirrors the system 7014 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7015 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7016 Inst.getOperand(5).getReg() != 0 || 7017 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7018 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7019 break; 7020 MCInst TmpInst; 7021 TmpInst.setOpcode(ARM::tADDhirr); 7022 TmpInst.addOperand(Inst.getOperand(0)); 7023 TmpInst.addOperand(Inst.getOperand(0)); 7024 TmpInst.addOperand(Inst.getOperand(2)); 7025 TmpInst.addOperand(Inst.getOperand(3)); 7026 TmpInst.addOperand(Inst.getOperand(4)); 7027 Inst = TmpInst; 7028 return true; 7029 } 7030 case ARM::tADDrSP: { 7031 // If the non-SP source operand and the destination operand are not the 7032 // same, we need to use the 32-bit encoding if it's available. 7033 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7034 Inst.setOpcode(ARM::t2ADDrr); 7035 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7036 return true; 7037 } 7038 break; 7039 } 7040 case ARM::tB: 7041 // A Thumb conditional branch outside of an IT block is a tBcc. 7042 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7043 Inst.setOpcode(ARM::tBcc); 7044 return true; 7045 } 7046 break; 7047 case ARM::t2B: 7048 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7049 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7050 Inst.setOpcode(ARM::t2Bcc); 7051 return true; 7052 } 7053 break; 7054 case ARM::t2Bcc: 7055 // If the conditional is AL or we're in an IT block, we really want t2B. 7056 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7057 Inst.setOpcode(ARM::t2B); 7058 return true; 7059 } 7060 break; 7061 case ARM::tBcc: 7062 // If the conditional is AL, we really want tB. 7063 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7064 Inst.setOpcode(ARM::tB); 7065 return true; 7066 } 7067 break; 7068 case ARM::tLDMIA: { 7069 // If the register list contains any high registers, or if the writeback 7070 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7071 // instead if we're in Thumb2. Otherwise, this should have generated 7072 // an error in validateInstruction(). 7073 unsigned Rn = Inst.getOperand(0).getReg(); 7074 bool hasWritebackToken = 7075 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7076 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 7077 bool listContainsBase; 7078 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7079 (!listContainsBase && !hasWritebackToken) || 7080 (listContainsBase && hasWritebackToken)) { 7081 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7082 assert (isThumbTwo()); 7083 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7084 // If we're switching to the updating version, we need to insert 7085 // the writeback tied operand. 7086 if (hasWritebackToken) 7087 Inst.insert(Inst.begin(), 7088 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7089 return true; 7090 } 7091 break; 7092 } 7093 case ARM::tSTMIA_UPD: { 7094 // If the register list contains any high registers, we need to use 7095 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7096 // should have generated an error in validateInstruction(). 7097 unsigned Rn = Inst.getOperand(0).getReg(); 7098 bool listContainsBase; 7099 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7100 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7101 assert (isThumbTwo()); 7102 Inst.setOpcode(ARM::t2STMIA_UPD); 7103 return true; 7104 } 7105 break; 7106 } 7107 case ARM::tPOP: { 7108 bool listContainsBase; 7109 // If the register list contains any high registers, we need to use 7110 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7111 // should have generated an error in validateInstruction(). 7112 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7113 return false; 7114 assert (isThumbTwo()); 7115 Inst.setOpcode(ARM::t2LDMIA_UPD); 7116 // Add the base register and writeback operands. 7117 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7118 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7119 return true; 7120 } 7121 case ARM::tPUSH: { 7122 bool listContainsBase; 7123 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7124 return false; 7125 assert (isThumbTwo()); 7126 Inst.setOpcode(ARM::t2STMDB_UPD); 7127 // Add the base register and writeback operands. 7128 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7129 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7130 return true; 7131 } 7132 case ARM::t2MOVi: { 7133 // If we can use the 16-bit encoding and the user didn't explicitly 7134 // request the 32-bit variant, transform it here. 7135 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7136 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7137 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7138 Inst.getOperand(4).getReg() == ARM::CPSR) || 7139 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7140 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7141 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7142 // The operands aren't in the same order for tMOVi8... 7143 MCInst TmpInst; 7144 TmpInst.setOpcode(ARM::tMOVi8); 7145 TmpInst.addOperand(Inst.getOperand(0)); 7146 TmpInst.addOperand(Inst.getOperand(4)); 7147 TmpInst.addOperand(Inst.getOperand(1)); 7148 TmpInst.addOperand(Inst.getOperand(2)); 7149 TmpInst.addOperand(Inst.getOperand(3)); 7150 Inst = TmpInst; 7151 return true; 7152 } 7153 break; 7154 } 7155 case ARM::t2MOVr: { 7156 // If we can use the 16-bit encoding and the user didn't explicitly 7157 // request the 32-bit variant, transform it here. 7158 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7159 isARMLowRegister(Inst.getOperand(1).getReg()) && 7160 Inst.getOperand(2).getImm() == ARMCC::AL && 7161 Inst.getOperand(4).getReg() == ARM::CPSR && 7162 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7163 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7164 // The operands aren't the same for tMOV[S]r... (no cc_out) 7165 MCInst TmpInst; 7166 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 7167 TmpInst.addOperand(Inst.getOperand(0)); 7168 TmpInst.addOperand(Inst.getOperand(1)); 7169 TmpInst.addOperand(Inst.getOperand(2)); 7170 TmpInst.addOperand(Inst.getOperand(3)); 7171 Inst = TmpInst; 7172 return true; 7173 } 7174 break; 7175 } 7176 case ARM::t2SXTH: 7177 case ARM::t2SXTB: 7178 case ARM::t2UXTH: 7179 case ARM::t2UXTB: { 7180 // If we can use the 16-bit encoding and the user didn't explicitly 7181 // request the 32-bit variant, transform it here. 7182 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7183 isARMLowRegister(Inst.getOperand(1).getReg()) && 7184 Inst.getOperand(2).getImm() == 0 && 7185 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7186 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7187 unsigned NewOpc; 7188 switch (Inst.getOpcode()) { 7189 default: llvm_unreachable("Illegal opcode!"); 7190 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7191 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7192 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7193 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 7194 } 7195 // The operands aren't the same for thumb1 (no rotate operand). 7196 MCInst TmpInst; 7197 TmpInst.setOpcode(NewOpc); 7198 TmpInst.addOperand(Inst.getOperand(0)); 7199 TmpInst.addOperand(Inst.getOperand(1)); 7200 TmpInst.addOperand(Inst.getOperand(3)); 7201 TmpInst.addOperand(Inst.getOperand(4)); 7202 Inst = TmpInst; 7203 return true; 7204 } 7205 break; 7206 } 7207 case ARM::MOVsi: { 7208 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7209 // rrx shifts and asr/lsr of #32 is encoded as 0 7210 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7211 return false; 7212 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 7213 // Shifting by zero is accepted as a vanilla 'MOVr' 7214 MCInst TmpInst; 7215 TmpInst.setOpcode(ARM::MOVr); 7216 TmpInst.addOperand(Inst.getOperand(0)); 7217 TmpInst.addOperand(Inst.getOperand(1)); 7218 TmpInst.addOperand(Inst.getOperand(3)); 7219 TmpInst.addOperand(Inst.getOperand(4)); 7220 TmpInst.addOperand(Inst.getOperand(5)); 7221 Inst = TmpInst; 7222 return true; 7223 } 7224 return false; 7225 } 7226 case ARM::ANDrsi: 7227 case ARM::ORRrsi: 7228 case ARM::EORrsi: 7229 case ARM::BICrsi: 7230 case ARM::SUBrsi: 7231 case ARM::ADDrsi: { 7232 unsigned newOpc; 7233 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 7234 if (SOpc == ARM_AM::rrx) return false; 7235 switch (Inst.getOpcode()) { 7236 default: llvm_unreachable("unexpected opcode!"); 7237 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 7238 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 7239 case ARM::EORrsi: newOpc = ARM::EORrr; break; 7240 case ARM::BICrsi: newOpc = ARM::BICrr; break; 7241 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 7242 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 7243 } 7244 // If the shift is by zero, use the non-shifted instruction definition. 7245 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) { 7246 MCInst TmpInst; 7247 TmpInst.setOpcode(newOpc); 7248 TmpInst.addOperand(Inst.getOperand(0)); 7249 TmpInst.addOperand(Inst.getOperand(1)); 7250 TmpInst.addOperand(Inst.getOperand(2)); 7251 TmpInst.addOperand(Inst.getOperand(4)); 7252 TmpInst.addOperand(Inst.getOperand(5)); 7253 TmpInst.addOperand(Inst.getOperand(6)); 7254 Inst = TmpInst; 7255 return true; 7256 } 7257 return false; 7258 } 7259 case ARM::ITasm: 7260 case ARM::t2IT: { 7261 // The mask bits for all but the first condition are represented as 7262 // the low bit of the condition code value implies 't'. We currently 7263 // always have 1 implies 't', so XOR toggle the bits if the low bit 7264 // of the condition code is zero. 7265 MCOperand &MO = Inst.getOperand(1); 7266 unsigned Mask = MO.getImm(); 7267 unsigned OrigMask = Mask; 7268 unsigned TZ = CountTrailingZeros_32(Mask); 7269 if ((Inst.getOperand(0).getImm() & 1) == 0) { 7270 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 7271 for (unsigned i = 3; i != TZ; --i) 7272 Mask ^= 1 << i; 7273 } 7274 MO.setImm(Mask); 7275 7276 // Set up the IT block state according to the IT instruction we just 7277 // matched. 7278 assert(!inITBlock() && "nested IT blocks?!"); 7279 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7280 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7281 ITState.CurPosition = 0; 7282 ITState.FirstCond = true; 7283 break; 7284 } 7285 } 7286 return false; 7287 } 7288 7289 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 7290 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 7291 // suffix depending on whether they're in an IT block or not. 7292 unsigned Opc = Inst.getOpcode(); 7293 const MCInstrDesc &MCID = getInstDesc(Opc); 7294 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 7295 assert(MCID.hasOptionalDef() && 7296 "optionally flag setting instruction missing optional def operand"); 7297 assert(MCID.NumOperands == Inst.getNumOperands() && 7298 "operand count mismatch!"); 7299 // Find the optional-def operand (cc_out). 7300 unsigned OpNo; 7301 for (OpNo = 0; 7302 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 7303 ++OpNo) 7304 ; 7305 // If we're parsing Thumb1, reject it completely. 7306 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 7307 return Match_MnemonicFail; 7308 // If we're parsing Thumb2, which form is legal depends on whether we're 7309 // in an IT block. 7310 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7311 !inITBlock()) 7312 return Match_RequiresITBlock; 7313 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7314 inITBlock()) 7315 return Match_RequiresNotITBlock; 7316 } 7317 // Some high-register supporting Thumb1 encodings only allow both registers 7318 // to be from r0-r7 when in Thumb2. 7319 else if (Opc == ARM::tADDhirr && isThumbOne() && 7320 isARMLowRegister(Inst.getOperand(1).getReg()) && 7321 isARMLowRegister(Inst.getOperand(2).getReg())) 7322 return Match_RequiresThumb2; 7323 // Others only require ARMv6 or later. 7324 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7325 isARMLowRegister(Inst.getOperand(0).getReg()) && 7326 isARMLowRegister(Inst.getOperand(1).getReg())) 7327 return Match_RequiresV6; 7328 return Match_Success; 7329 } 7330 7331 static const char *getSubtargetFeatureName(unsigned Val); 7332 bool ARMAsmParser:: 7333 MatchAndEmitInstruction(SMLoc IDLoc, 7334 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7335 MCStreamer &Out) { 7336 MCInst Inst; 7337 unsigned ErrorInfo; 7338 unsigned MatchResult; 7339 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 7340 switch (MatchResult) { 7341 default: break; 7342 case Match_Success: 7343 // Context sensitive operand constraints aren't handled by the matcher, 7344 // so check them here. 7345 if (validateInstruction(Inst, Operands)) { 7346 // Still progress the IT block, otherwise one wrong condition causes 7347 // nasty cascading errors. 7348 forwardITPosition(); 7349 return true; 7350 } 7351 7352 // Some instructions need post-processing to, for example, tweak which 7353 // encoding is selected. Loop on it while changes happen so the 7354 // individual transformations can chain off each other. E.g., 7355 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 7356 while (processInstruction(Inst, Operands)) 7357 ; 7358 7359 // Only move forward at the very end so that everything in validate 7360 // and process gets a consistent answer about whether we're in an IT 7361 // block. 7362 forwardITPosition(); 7363 7364 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 7365 // doesn't actually encode. 7366 if (Inst.getOpcode() == ARM::ITasm) 7367 return false; 7368 7369 Inst.setLoc(IDLoc); 7370 Out.EmitInstruction(Inst); 7371 return false; 7372 case Match_MissingFeature: { 7373 assert(ErrorInfo && "Unknown missing feature!"); 7374 // Special case the error message for the very common case where only 7375 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 7376 std::string Msg = "instruction requires:"; 7377 unsigned Mask = 1; 7378 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 7379 if (ErrorInfo & Mask) { 7380 Msg += " "; 7381 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 7382 } 7383 Mask <<= 1; 7384 } 7385 return Error(IDLoc, Msg); 7386 } 7387 case Match_InvalidOperand: { 7388 SMLoc ErrorLoc = IDLoc; 7389 if (ErrorInfo != ~0U) { 7390 if (ErrorInfo >= Operands.size()) 7391 return Error(IDLoc, "too few operands for instruction"); 7392 7393 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7394 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7395 } 7396 7397 return Error(ErrorLoc, "invalid operand for instruction"); 7398 } 7399 case Match_MnemonicFail: 7400 return Error(IDLoc, "invalid instruction", 7401 ((ARMOperand*)Operands[0])->getLocRange()); 7402 case Match_ConversionFail: 7403 // The converter function will have already emitted a diagnostic. 7404 return true; 7405 case Match_RequiresNotITBlock: 7406 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 7407 case Match_RequiresITBlock: 7408 return Error(IDLoc, "instruction only valid inside IT block"); 7409 case Match_RequiresV6: 7410 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7411 case Match_RequiresThumb2: 7412 return Error(IDLoc, "instruction variant requires Thumb2"); 7413 } 7414 7415 llvm_unreachable("Implement any new match types added!"); 7416 } 7417 7418 /// parseDirective parses the arm specific directives 7419 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7420 StringRef IDVal = DirectiveID.getIdentifier(); 7421 if (IDVal == ".word") 7422 return parseDirectiveWord(4, DirectiveID.getLoc()); 7423 else if (IDVal == ".thumb") 7424 return parseDirectiveThumb(DirectiveID.getLoc()); 7425 else if (IDVal == ".arm") 7426 return parseDirectiveARM(DirectiveID.getLoc()); 7427 else if (IDVal == ".thumb_func") 7428 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7429 else if (IDVal == ".code") 7430 return parseDirectiveCode(DirectiveID.getLoc()); 7431 else if (IDVal == ".syntax") 7432 return parseDirectiveSyntax(DirectiveID.getLoc()); 7433 else if (IDVal == ".unreq") 7434 return parseDirectiveUnreq(DirectiveID.getLoc()); 7435 else if (IDVal == ".arch") 7436 return parseDirectiveArch(DirectiveID.getLoc()); 7437 else if (IDVal == ".eabi_attribute") 7438 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7439 return true; 7440 } 7441 7442 /// parseDirectiveWord 7443 /// ::= .word [ expression (, expression)* ] 7444 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 7445 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7446 for (;;) { 7447 const MCExpr *Value; 7448 if (getParser().ParseExpression(Value)) 7449 return true; 7450 7451 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 7452 7453 if (getLexer().is(AsmToken::EndOfStatement)) 7454 break; 7455 7456 // FIXME: Improve diagnostic. 7457 if (getLexer().isNot(AsmToken::Comma)) 7458 return Error(L, "unexpected token in directive"); 7459 Parser.Lex(); 7460 } 7461 } 7462 7463 Parser.Lex(); 7464 return false; 7465 } 7466 7467 /// parseDirectiveThumb 7468 /// ::= .thumb 7469 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 7470 if (getLexer().isNot(AsmToken::EndOfStatement)) 7471 return Error(L, "unexpected token in directive"); 7472 Parser.Lex(); 7473 7474 if (!isThumb()) 7475 SwitchMode(); 7476 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7477 return false; 7478 } 7479 7480 /// parseDirectiveARM 7481 /// ::= .arm 7482 bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 7483 if (getLexer().isNot(AsmToken::EndOfStatement)) 7484 return Error(L, "unexpected token in directive"); 7485 Parser.Lex(); 7486 7487 if (isThumb()) 7488 SwitchMode(); 7489 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7490 return false; 7491 } 7492 7493 /// parseDirectiveThumbFunc 7494 /// ::= .thumbfunc symbol_name 7495 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 7496 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 7497 bool isMachO = MAI.hasSubsectionsViaSymbols(); 7498 StringRef Name; 7499 bool needFuncName = true; 7500 7501 // Darwin asm has (optionally) function name after .thumb_func direction 7502 // ELF doesn't 7503 if (isMachO) { 7504 const AsmToken &Tok = Parser.getTok(); 7505 if (Tok.isNot(AsmToken::EndOfStatement)) { 7506 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 7507 return Error(L, "unexpected token in .thumb_func directive"); 7508 Name = Tok.getIdentifier(); 7509 Parser.Lex(); // Consume the identifier token. 7510 needFuncName = false; 7511 } 7512 } 7513 7514 if (getLexer().isNot(AsmToken::EndOfStatement)) 7515 return Error(L, "unexpected token in directive"); 7516 7517 // Eat the end of statement and any blank lines that follow. 7518 while (getLexer().is(AsmToken::EndOfStatement)) 7519 Parser.Lex(); 7520 7521 // FIXME: assuming function name will be the line following .thumb_func 7522 // We really should be checking the next symbol definition even if there's 7523 // stuff in between. 7524 if (needFuncName) { 7525 Name = Parser.getTok().getIdentifier(); 7526 } 7527 7528 // Mark symbol as a thumb symbol. 7529 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 7530 getParser().getStreamer().EmitThumbFunc(Func); 7531 return false; 7532 } 7533 7534 /// parseDirectiveSyntax 7535 /// ::= .syntax unified | divided 7536 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 7537 const AsmToken &Tok = Parser.getTok(); 7538 if (Tok.isNot(AsmToken::Identifier)) 7539 return Error(L, "unexpected token in .syntax directive"); 7540 StringRef Mode = Tok.getString(); 7541 if (Mode == "unified" || Mode == "UNIFIED") 7542 Parser.Lex(); 7543 else if (Mode == "divided" || Mode == "DIVIDED") 7544 return Error(L, "'.syntax divided' arm asssembly not supported"); 7545 else 7546 return Error(L, "unrecognized syntax mode in .syntax directive"); 7547 7548 if (getLexer().isNot(AsmToken::EndOfStatement)) 7549 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7550 Parser.Lex(); 7551 7552 // TODO tell the MC streamer the mode 7553 // getParser().getStreamer().Emit???(); 7554 return false; 7555 } 7556 7557 /// parseDirectiveCode 7558 /// ::= .code 16 | 32 7559 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 7560 const AsmToken &Tok = Parser.getTok(); 7561 if (Tok.isNot(AsmToken::Integer)) 7562 return Error(L, "unexpected token in .code directive"); 7563 int64_t Val = Parser.getTok().getIntVal(); 7564 if (Val == 16) 7565 Parser.Lex(); 7566 else if (Val == 32) 7567 Parser.Lex(); 7568 else 7569 return Error(L, "invalid operand to .code directive"); 7570 7571 if (getLexer().isNot(AsmToken::EndOfStatement)) 7572 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7573 Parser.Lex(); 7574 7575 if (Val == 16) { 7576 if (!isThumb()) 7577 SwitchMode(); 7578 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7579 } else { 7580 if (isThumb()) 7581 SwitchMode(); 7582 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7583 } 7584 7585 return false; 7586 } 7587 7588 /// parseDirectiveReq 7589 /// ::= name .req registername 7590 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 7591 Parser.Lex(); // Eat the '.req' token. 7592 unsigned Reg; 7593 SMLoc SRegLoc, ERegLoc; 7594 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 7595 Parser.EatToEndOfStatement(); 7596 return Error(SRegLoc, "register name expected"); 7597 } 7598 7599 // Shouldn't be anything else. 7600 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7601 Parser.EatToEndOfStatement(); 7602 return Error(Parser.getTok().getLoc(), 7603 "unexpected input in .req directive."); 7604 } 7605 7606 Parser.Lex(); // Consume the EndOfStatement 7607 7608 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 7609 return Error(SRegLoc, "redefinition of '" + Name + 7610 "' does not match original."); 7611 7612 return false; 7613 } 7614 7615 /// parseDirectiveUneq 7616 /// ::= .unreq registername 7617 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 7618 if (Parser.getTok().isNot(AsmToken::Identifier)) { 7619 Parser.EatToEndOfStatement(); 7620 return Error(L, "unexpected input in .unreq directive."); 7621 } 7622 RegisterReqs.erase(Parser.getTok().getIdentifier()); 7623 Parser.Lex(); // Eat the identifier. 7624 return false; 7625 } 7626 7627 /// parseDirectiveArch 7628 /// ::= .arch token 7629 bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 7630 return true; 7631 } 7632 7633 /// parseDirectiveEabiAttr 7634 /// ::= .eabi_attribute int, int 7635 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 7636 return true; 7637 } 7638 7639 extern "C" void LLVMInitializeARMAsmLexer(); 7640 7641 /// Force static initialization. 7642 extern "C" void LLVMInitializeARMAsmParser() { 7643 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 7644 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 7645 LLVMInitializeARMAsmLexer(); 7646 } 7647 7648 #define GET_REGISTER_MATCHER 7649 #define GET_SUBTARGET_FEATURE_NAME 7650 #define GET_MATCHER_IMPLEMENTATION 7651 #include "ARMGenAsmMatcher.inc" 7652