1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCTargetAsmParser.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "llvm/ADT/BitVector.h" 15 #include "llvm/ADT/OwningPtr.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Twine.h" 20 #include "llvm/MC/MCAsmInfo.h" 21 #include "llvm/MC/MCAssembler.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCELFStreamer.h" 24 #include "llvm/MC/MCExpr.h" 25 #include "llvm/MC/MCInst.h" 26 #include "llvm/MC/MCInstrDesc.h" 27 #include "llvm/MC/MCParser/MCAsmLexer.h" 28 #include "llvm/MC/MCParser/MCAsmParser.h" 29 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCStreamer.h" 32 #include "llvm/MC/MCSubtargetInfo.h" 33 #include "llvm/Support/ELF.h" 34 #include "llvm/Support/MathExtras.h" 35 #include "llvm/Support/SourceMgr.h" 36 #include "llvm/Support/TargetRegistry.h" 37 #include "llvm/Support/raw_ostream.h" 38 39 using namespace llvm; 40 41 namespace { 42 43 class ARMOperand; 44 45 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 46 47 class ARMAsmParser : public MCTargetAsmParser { 48 MCSubtargetInfo &STI; 49 MCAsmParser &Parser; 50 const MCRegisterInfo *MRI; 51 52 // Unwind directives state 53 SMLoc FnStartLoc; 54 SMLoc CantUnwindLoc; 55 SMLoc PersonalityLoc; 56 SMLoc HandlerDataLoc; 57 int FPReg; 58 void resetUnwindDirectiveParserState() { 59 FnStartLoc = SMLoc(); 60 CantUnwindLoc = SMLoc(); 61 PersonalityLoc = SMLoc(); 62 HandlerDataLoc = SMLoc(); 63 FPReg = -1; 64 } 65 66 // Map of register aliases registers via the .req directive. 67 StringMap<unsigned> RegisterReqs; 68 69 struct { 70 ARMCC::CondCodes Cond; // Condition for IT block. 71 unsigned Mask:4; // Condition mask for instructions. 72 // Starting at first 1 (from lsb). 73 // '1' condition as indicated in IT. 74 // '0' inverse of condition (else). 75 // Count of instructions in IT block is 76 // 4 - trailingzeroes(mask) 77 78 bool FirstCond; // Explicit flag for when we're parsing the 79 // First instruction in the IT block. It's 80 // implied in the mask, so needs special 81 // handling. 82 83 unsigned CurPosition; // Current position in parsing of IT 84 // block. In range [0,3]. Initialized 85 // according to count of instructions in block. 86 // ~0U if no active IT block. 87 } ITState; 88 bool inITBlock() { return ITState.CurPosition != ~0U;} 89 void forwardITPosition() { 90 if (!inITBlock()) return; 91 // Move to the next instruction in the IT block, if there is one. If not, 92 // mark the block as done. 93 unsigned TZ = countTrailingZeros(ITState.Mask); 94 if (++ITState.CurPosition == 5 - TZ) 95 ITState.CurPosition = ~0U; // Done with the IT block after this. 96 } 97 98 99 MCAsmParser &getParser() const { return Parser; } 100 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 101 102 bool Warning(SMLoc L, const Twine &Msg, 103 ArrayRef<SMRange> Ranges = None) { 104 return Parser.Warning(L, Msg, Ranges); 105 } 106 bool Error(SMLoc L, const Twine &Msg, 107 ArrayRef<SMRange> Ranges = None) { 108 return Parser.Error(L, Msg, Ranges); 109 } 110 111 int tryParseRegister(); 112 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 113 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 114 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 115 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 116 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 117 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 118 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 119 unsigned &ShiftAmount); 120 bool parseDirectiveWord(unsigned Size, SMLoc L); 121 bool parseDirectiveThumb(SMLoc L); 122 bool parseDirectiveARM(SMLoc L); 123 bool parseDirectiveThumbFunc(SMLoc L); 124 bool parseDirectiveCode(SMLoc L); 125 bool parseDirectiveSyntax(SMLoc L); 126 bool parseDirectiveReq(StringRef Name, SMLoc L); 127 bool parseDirectiveUnreq(SMLoc L); 128 bool parseDirectiveArch(SMLoc L); 129 bool parseDirectiveEabiAttr(SMLoc L); 130 bool parseDirectiveFnStart(SMLoc L); 131 bool parseDirectiveFnEnd(SMLoc L); 132 bool parseDirectiveCantUnwind(SMLoc L); 133 bool parseDirectivePersonality(SMLoc L); 134 bool parseDirectiveHandlerData(SMLoc L); 135 bool parseDirectiveSetFP(SMLoc L); 136 bool parseDirectivePad(SMLoc L); 137 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 138 139 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 140 bool &CarrySetting, unsigned &ProcessorIMod, 141 StringRef &ITMask); 142 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 143 bool &CanAcceptPredicationCode); 144 145 bool isThumb() const { 146 // FIXME: Can tablegen auto-generate this? 147 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 148 } 149 bool isThumbOne() const { 150 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 151 } 152 bool isThumbTwo() const { 153 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 154 } 155 bool hasThumb() const { 156 return STI.getFeatureBits() & ARM::HasV4TOps; 157 } 158 bool hasV6Ops() const { 159 return STI.getFeatureBits() & ARM::HasV6Ops; 160 } 161 bool hasV7Ops() const { 162 return STI.getFeatureBits() & ARM::HasV7Ops; 163 } 164 bool hasARM() const { 165 return !(STI.getFeatureBits() & ARM::FeatureNoARM); 166 } 167 168 void SwitchMode() { 169 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 170 setAvailableFeatures(FB); 171 } 172 bool isMClass() const { 173 return STI.getFeatureBits() & ARM::FeatureMClass; 174 } 175 176 /// @name Auto-generated Match Functions 177 /// { 178 179 #define GET_ASSEMBLER_HEADER 180 #include "ARMGenAsmMatcher.inc" 181 182 /// } 183 184 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 185 OperandMatchResultTy parseCoprocNumOperand( 186 SmallVectorImpl<MCParsedAsmOperand*>&); 187 OperandMatchResultTy parseCoprocRegOperand( 188 SmallVectorImpl<MCParsedAsmOperand*>&); 189 OperandMatchResultTy parseCoprocOptionOperand( 190 SmallVectorImpl<MCParsedAsmOperand*>&); 191 OperandMatchResultTy parseMemBarrierOptOperand( 192 SmallVectorImpl<MCParsedAsmOperand*>&); 193 OperandMatchResultTy parseInstSyncBarrierOptOperand( 194 SmallVectorImpl<MCParsedAsmOperand*>&); 195 OperandMatchResultTy parseProcIFlagsOperand( 196 SmallVectorImpl<MCParsedAsmOperand*>&); 197 OperandMatchResultTy parseMSRMaskOperand( 198 SmallVectorImpl<MCParsedAsmOperand*>&); 199 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 200 StringRef Op, int Low, int High); 201 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 202 return parsePKHImm(O, "lsl", 0, 31); 203 } 204 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 205 return parsePKHImm(O, "asr", 1, 32); 206 } 207 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 208 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 209 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 210 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 211 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 212 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 213 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 214 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 215 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 216 SMLoc &EndLoc); 217 218 // Asm Match Converter Methods 219 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 220 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 221 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 222 const SmallVectorImpl<MCParsedAsmOperand*> &); 223 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 224 const SmallVectorImpl<MCParsedAsmOperand*> &); 225 void cvtLdWriteBackRegAddrMode2(MCInst &Inst, 226 const SmallVectorImpl<MCParsedAsmOperand*> &); 227 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 228 const SmallVectorImpl<MCParsedAsmOperand*> &); 229 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 230 const SmallVectorImpl<MCParsedAsmOperand*> &); 231 void cvtStWriteBackRegAddrMode2(MCInst &Inst, 232 const SmallVectorImpl<MCParsedAsmOperand*> &); 233 void cvtStWriteBackRegAddrMode3(MCInst &Inst, 234 const SmallVectorImpl<MCParsedAsmOperand*> &); 235 void cvtLdExtTWriteBackImm(MCInst &Inst, 236 const SmallVectorImpl<MCParsedAsmOperand*> &); 237 void cvtLdExtTWriteBackReg(MCInst &Inst, 238 const SmallVectorImpl<MCParsedAsmOperand*> &); 239 void cvtStExtTWriteBackImm(MCInst &Inst, 240 const SmallVectorImpl<MCParsedAsmOperand*> &); 241 void cvtStExtTWriteBackReg(MCInst &Inst, 242 const SmallVectorImpl<MCParsedAsmOperand*> &); 243 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 244 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 245 void cvtLdWriteBackRegAddrMode3(MCInst &Inst, 246 const SmallVectorImpl<MCParsedAsmOperand*> &); 247 void cvtThumbMultiply(MCInst &Inst, 248 const SmallVectorImpl<MCParsedAsmOperand*> &); 249 void cvtVLDwbFixed(MCInst &Inst, 250 const SmallVectorImpl<MCParsedAsmOperand*> &); 251 void cvtVLDwbRegister(MCInst &Inst, 252 const SmallVectorImpl<MCParsedAsmOperand*> &); 253 void cvtVSTwbFixed(MCInst &Inst, 254 const SmallVectorImpl<MCParsedAsmOperand*> &); 255 void cvtVSTwbRegister(MCInst &Inst, 256 const SmallVectorImpl<MCParsedAsmOperand*> &); 257 bool validateInstruction(MCInst &Inst, 258 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 259 bool processInstruction(MCInst &Inst, 260 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 261 bool shouldOmitCCOutOperand(StringRef Mnemonic, 262 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 263 264 public: 265 enum ARMMatchResultTy { 266 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 267 Match_RequiresNotITBlock, 268 Match_RequiresV6, 269 Match_RequiresThumb2, 270 #define GET_OPERAND_DIAGNOSTIC_TYPES 271 #include "ARMGenAsmMatcher.inc" 272 273 }; 274 275 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 276 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) { 277 MCAsmParserExtension::Initialize(_Parser); 278 279 // Cache the MCRegisterInfo. 280 MRI = &getContext().getRegisterInfo(); 281 282 // Initialize the set of available features. 283 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 284 285 // Not in an ITBlock to start with. 286 ITState.CurPosition = ~0U; 287 288 // Set ELF header flags. 289 // FIXME: This should eventually end up somewhere else where more 290 // intelligent flag decisions can be made. For now we are just maintaining 291 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default. 292 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer())) 293 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5); 294 } 295 296 // Implementation of the MCTargetAsmParser interface: 297 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 298 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 299 SMLoc NameLoc, 300 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 301 bool ParseDirective(AsmToken DirectiveID); 302 303 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); 304 unsigned checkTargetMatchPredicate(MCInst &Inst); 305 306 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 307 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 308 MCStreamer &Out, unsigned &ErrorInfo, 309 bool MatchingInlineAsm); 310 }; 311 } // end anonymous namespace 312 313 namespace { 314 315 /// ARMOperand - Instances of this class represent a parsed ARM machine 316 /// operand. 317 class ARMOperand : public MCParsedAsmOperand { 318 enum KindTy { 319 k_CondCode, 320 k_CCOut, 321 k_ITCondMask, 322 k_CoprocNum, 323 k_CoprocReg, 324 k_CoprocOption, 325 k_Immediate, 326 k_MemBarrierOpt, 327 k_InstSyncBarrierOpt, 328 k_Memory, 329 k_PostIndexRegister, 330 k_MSRMask, 331 k_ProcIFlags, 332 k_VectorIndex, 333 k_Register, 334 k_RegisterList, 335 k_DPRRegisterList, 336 k_SPRRegisterList, 337 k_VectorList, 338 k_VectorListAllLanes, 339 k_VectorListIndexed, 340 k_ShiftedRegister, 341 k_ShiftedImmediate, 342 k_ShifterImmediate, 343 k_RotateImmediate, 344 k_BitfieldDescriptor, 345 k_Token 346 } Kind; 347 348 SMLoc StartLoc, EndLoc; 349 SmallVector<unsigned, 8> Registers; 350 351 struct CCOp { 352 ARMCC::CondCodes Val; 353 }; 354 355 struct CopOp { 356 unsigned Val; 357 }; 358 359 struct CoprocOptionOp { 360 unsigned Val; 361 }; 362 363 struct ITMaskOp { 364 unsigned Mask:4; 365 }; 366 367 struct MBOptOp { 368 ARM_MB::MemBOpt Val; 369 }; 370 371 struct ISBOptOp { 372 ARM_ISB::InstSyncBOpt Val; 373 }; 374 375 struct IFlagsOp { 376 ARM_PROC::IFlags Val; 377 }; 378 379 struct MMaskOp { 380 unsigned Val; 381 }; 382 383 struct TokOp { 384 const char *Data; 385 unsigned Length; 386 }; 387 388 struct RegOp { 389 unsigned RegNum; 390 }; 391 392 // A vector register list is a sequential list of 1 to 4 registers. 393 struct VectorListOp { 394 unsigned RegNum; 395 unsigned Count; 396 unsigned LaneIndex; 397 bool isDoubleSpaced; 398 }; 399 400 struct VectorIndexOp { 401 unsigned Val; 402 }; 403 404 struct ImmOp { 405 const MCExpr *Val; 406 }; 407 408 /// Combined record for all forms of ARM address expressions. 409 struct MemoryOp { 410 unsigned BaseRegNum; 411 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 412 // was specified. 413 const MCConstantExpr *OffsetImm; // Offset immediate value 414 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 415 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 416 unsigned ShiftImm; // shift for OffsetReg. 417 unsigned Alignment; // 0 = no alignment specified 418 // n = alignment in bytes (2, 4, 8, 16, or 32) 419 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 420 }; 421 422 struct PostIdxRegOp { 423 unsigned RegNum; 424 bool isAdd; 425 ARM_AM::ShiftOpc ShiftTy; 426 unsigned ShiftImm; 427 }; 428 429 struct ShifterImmOp { 430 bool isASR; 431 unsigned Imm; 432 }; 433 434 struct RegShiftedRegOp { 435 ARM_AM::ShiftOpc ShiftTy; 436 unsigned SrcReg; 437 unsigned ShiftReg; 438 unsigned ShiftImm; 439 }; 440 441 struct RegShiftedImmOp { 442 ARM_AM::ShiftOpc ShiftTy; 443 unsigned SrcReg; 444 unsigned ShiftImm; 445 }; 446 447 struct RotImmOp { 448 unsigned Imm; 449 }; 450 451 struct BitfieldOp { 452 unsigned LSB; 453 unsigned Width; 454 }; 455 456 union { 457 struct CCOp CC; 458 struct CopOp Cop; 459 struct CoprocOptionOp CoprocOption; 460 struct MBOptOp MBOpt; 461 struct ISBOptOp ISBOpt; 462 struct ITMaskOp ITMask; 463 struct IFlagsOp IFlags; 464 struct MMaskOp MMask; 465 struct TokOp Tok; 466 struct RegOp Reg; 467 struct VectorListOp VectorList; 468 struct VectorIndexOp VectorIndex; 469 struct ImmOp Imm; 470 struct MemoryOp Memory; 471 struct PostIdxRegOp PostIdxReg; 472 struct ShifterImmOp ShifterImm; 473 struct RegShiftedRegOp RegShiftedReg; 474 struct RegShiftedImmOp RegShiftedImm; 475 struct RotImmOp RotImm; 476 struct BitfieldOp Bitfield; 477 }; 478 479 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 480 public: 481 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 482 Kind = o.Kind; 483 StartLoc = o.StartLoc; 484 EndLoc = o.EndLoc; 485 switch (Kind) { 486 case k_CondCode: 487 CC = o.CC; 488 break; 489 case k_ITCondMask: 490 ITMask = o.ITMask; 491 break; 492 case k_Token: 493 Tok = o.Tok; 494 break; 495 case k_CCOut: 496 case k_Register: 497 Reg = o.Reg; 498 break; 499 case k_RegisterList: 500 case k_DPRRegisterList: 501 case k_SPRRegisterList: 502 Registers = o.Registers; 503 break; 504 case k_VectorList: 505 case k_VectorListAllLanes: 506 case k_VectorListIndexed: 507 VectorList = o.VectorList; 508 break; 509 case k_CoprocNum: 510 case k_CoprocReg: 511 Cop = o.Cop; 512 break; 513 case k_CoprocOption: 514 CoprocOption = o.CoprocOption; 515 break; 516 case k_Immediate: 517 Imm = o.Imm; 518 break; 519 case k_MemBarrierOpt: 520 MBOpt = o.MBOpt; 521 break; 522 case k_InstSyncBarrierOpt: 523 ISBOpt = o.ISBOpt; 524 case k_Memory: 525 Memory = o.Memory; 526 break; 527 case k_PostIndexRegister: 528 PostIdxReg = o.PostIdxReg; 529 break; 530 case k_MSRMask: 531 MMask = o.MMask; 532 break; 533 case k_ProcIFlags: 534 IFlags = o.IFlags; 535 break; 536 case k_ShifterImmediate: 537 ShifterImm = o.ShifterImm; 538 break; 539 case k_ShiftedRegister: 540 RegShiftedReg = o.RegShiftedReg; 541 break; 542 case k_ShiftedImmediate: 543 RegShiftedImm = o.RegShiftedImm; 544 break; 545 case k_RotateImmediate: 546 RotImm = o.RotImm; 547 break; 548 case k_BitfieldDescriptor: 549 Bitfield = o.Bitfield; 550 break; 551 case k_VectorIndex: 552 VectorIndex = o.VectorIndex; 553 break; 554 } 555 } 556 557 /// getStartLoc - Get the location of the first token of this operand. 558 SMLoc getStartLoc() const { return StartLoc; } 559 /// getEndLoc - Get the location of the last token of this operand. 560 SMLoc getEndLoc() const { return EndLoc; } 561 /// getLocRange - Get the range between the first and last token of this 562 /// operand. 563 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 564 565 ARMCC::CondCodes getCondCode() const { 566 assert(Kind == k_CondCode && "Invalid access!"); 567 return CC.Val; 568 } 569 570 unsigned getCoproc() const { 571 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 572 return Cop.Val; 573 } 574 575 StringRef getToken() const { 576 assert(Kind == k_Token && "Invalid access!"); 577 return StringRef(Tok.Data, Tok.Length); 578 } 579 580 unsigned getReg() const { 581 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 582 return Reg.RegNum; 583 } 584 585 const SmallVectorImpl<unsigned> &getRegList() const { 586 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 587 Kind == k_SPRRegisterList) && "Invalid access!"); 588 return Registers; 589 } 590 591 const MCExpr *getImm() const { 592 assert(isImm() && "Invalid access!"); 593 return Imm.Val; 594 } 595 596 unsigned getVectorIndex() const { 597 assert(Kind == k_VectorIndex && "Invalid access!"); 598 return VectorIndex.Val; 599 } 600 601 ARM_MB::MemBOpt getMemBarrierOpt() const { 602 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 603 return MBOpt.Val; 604 } 605 606 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 607 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 608 return ISBOpt.Val; 609 } 610 611 ARM_PROC::IFlags getProcIFlags() const { 612 assert(Kind == k_ProcIFlags && "Invalid access!"); 613 return IFlags.Val; 614 } 615 616 unsigned getMSRMask() const { 617 assert(Kind == k_MSRMask && "Invalid access!"); 618 return MMask.Val; 619 } 620 621 bool isCoprocNum() const { return Kind == k_CoprocNum; } 622 bool isCoprocReg() const { return Kind == k_CoprocReg; } 623 bool isCoprocOption() const { return Kind == k_CoprocOption; } 624 bool isCondCode() const { return Kind == k_CondCode; } 625 bool isCCOut() const { return Kind == k_CCOut; } 626 bool isITMask() const { return Kind == k_ITCondMask; } 627 bool isITCondCode() const { return Kind == k_CondCode; } 628 bool isImm() const { return Kind == k_Immediate; } 629 bool isFPImm() const { 630 if (!isImm()) return false; 631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 632 if (!CE) return false; 633 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 634 return Val != -1; 635 } 636 bool isFBits16() const { 637 if (!isImm()) return false; 638 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 639 if (!CE) return false; 640 int64_t Value = CE->getValue(); 641 return Value >= 0 && Value <= 16; 642 } 643 bool isFBits32() const { 644 if (!isImm()) return false; 645 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 646 if (!CE) return false; 647 int64_t Value = CE->getValue(); 648 return Value >= 1 && Value <= 32; 649 } 650 bool isImm8s4() const { 651 if (!isImm()) return false; 652 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 653 if (!CE) return false; 654 int64_t Value = CE->getValue(); 655 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 656 } 657 bool isImm0_4() const { 658 if (!isImm()) return false; 659 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 660 if (!CE) return false; 661 int64_t Value = CE->getValue(); 662 return Value >= 0 && Value < 5; 663 } 664 bool isImm0_1020s4() const { 665 if (!isImm()) return false; 666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 667 if (!CE) return false; 668 int64_t Value = CE->getValue(); 669 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 670 } 671 bool isImm0_508s4() const { 672 if (!isImm()) return false; 673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 674 if (!CE) return false; 675 int64_t Value = CE->getValue(); 676 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 677 } 678 bool isImm0_508s4Neg() const { 679 if (!isImm()) return false; 680 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 681 if (!CE) return false; 682 int64_t Value = -CE->getValue(); 683 // explicitly exclude zero. we want that to use the normal 0_508 version. 684 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 685 } 686 bool isImm0_255() const { 687 if (!isImm()) return false; 688 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 689 if (!CE) return false; 690 int64_t Value = CE->getValue(); 691 return Value >= 0 && Value < 256; 692 } 693 bool isImm0_4095() const { 694 if (!isImm()) return false; 695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 696 if (!CE) return false; 697 int64_t Value = CE->getValue(); 698 return Value >= 0 && Value < 4096; 699 } 700 bool isImm0_4095Neg() const { 701 if (!isImm()) return false; 702 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 703 if (!CE) return false; 704 int64_t Value = -CE->getValue(); 705 return Value > 0 && Value < 4096; 706 } 707 bool isImm0_1() const { 708 if (!isImm()) return false; 709 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 710 if (!CE) return false; 711 int64_t Value = CE->getValue(); 712 return Value >= 0 && Value < 2; 713 } 714 bool isImm0_3() const { 715 if (!isImm()) return false; 716 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 717 if (!CE) return false; 718 int64_t Value = CE->getValue(); 719 return Value >= 0 && Value < 4; 720 } 721 bool isImm0_7() const { 722 if (!isImm()) return false; 723 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 724 if (!CE) return false; 725 int64_t Value = CE->getValue(); 726 return Value >= 0 && Value < 8; 727 } 728 bool isImm0_15() const { 729 if (!isImm()) return false; 730 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 731 if (!CE) return false; 732 int64_t Value = CE->getValue(); 733 return Value >= 0 && Value < 16; 734 } 735 bool isImm0_31() const { 736 if (!isImm()) return false; 737 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 738 if (!CE) return false; 739 int64_t Value = CE->getValue(); 740 return Value >= 0 && Value < 32; 741 } 742 bool isImm0_63() const { 743 if (!isImm()) return false; 744 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 745 if (!CE) return false; 746 int64_t Value = CE->getValue(); 747 return Value >= 0 && Value < 64; 748 } 749 bool isImm8() const { 750 if (!isImm()) return false; 751 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 752 if (!CE) return false; 753 int64_t Value = CE->getValue(); 754 return Value == 8; 755 } 756 bool isImm16() const { 757 if (!isImm()) return false; 758 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 759 if (!CE) return false; 760 int64_t Value = CE->getValue(); 761 return Value == 16; 762 } 763 bool isImm32() const { 764 if (!isImm()) return false; 765 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 766 if (!CE) return false; 767 int64_t Value = CE->getValue(); 768 return Value == 32; 769 } 770 bool isShrImm8() const { 771 if (!isImm()) return false; 772 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 773 if (!CE) return false; 774 int64_t Value = CE->getValue(); 775 return Value > 0 && Value <= 8; 776 } 777 bool isShrImm16() const { 778 if (!isImm()) return false; 779 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 780 if (!CE) return false; 781 int64_t Value = CE->getValue(); 782 return Value > 0 && Value <= 16; 783 } 784 bool isShrImm32() const { 785 if (!isImm()) return false; 786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 787 if (!CE) return false; 788 int64_t Value = CE->getValue(); 789 return Value > 0 && Value <= 32; 790 } 791 bool isShrImm64() const { 792 if (!isImm()) return false; 793 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 794 if (!CE) return false; 795 int64_t Value = CE->getValue(); 796 return Value > 0 && Value <= 64; 797 } 798 bool isImm1_7() const { 799 if (!isImm()) return false; 800 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 801 if (!CE) return false; 802 int64_t Value = CE->getValue(); 803 return Value > 0 && Value < 8; 804 } 805 bool isImm1_15() const { 806 if (!isImm()) return false; 807 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 808 if (!CE) return false; 809 int64_t Value = CE->getValue(); 810 return Value > 0 && Value < 16; 811 } 812 bool isImm1_31() const { 813 if (!isImm()) return false; 814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 815 if (!CE) return false; 816 int64_t Value = CE->getValue(); 817 return Value > 0 && Value < 32; 818 } 819 bool isImm1_16() const { 820 if (!isImm()) return false; 821 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 822 if (!CE) return false; 823 int64_t Value = CE->getValue(); 824 return Value > 0 && Value < 17; 825 } 826 bool isImm1_32() const { 827 if (!isImm()) return false; 828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 829 if (!CE) return false; 830 int64_t Value = CE->getValue(); 831 return Value > 0 && Value < 33; 832 } 833 bool isImm0_32() const { 834 if (!isImm()) return false; 835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 836 if (!CE) return false; 837 int64_t Value = CE->getValue(); 838 return Value >= 0 && Value < 33; 839 } 840 bool isImm0_65535() const { 841 if (!isImm()) return false; 842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 843 if (!CE) return false; 844 int64_t Value = CE->getValue(); 845 return Value >= 0 && Value < 65536; 846 } 847 bool isImm0_65535Expr() const { 848 if (!isImm()) return false; 849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 850 // If it's not a constant expression, it'll generate a fixup and be 851 // handled later. 852 if (!CE) return true; 853 int64_t Value = CE->getValue(); 854 return Value >= 0 && Value < 65536; 855 } 856 bool isImm24bit() const { 857 if (!isImm()) return false; 858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 859 if (!CE) return false; 860 int64_t Value = CE->getValue(); 861 return Value >= 0 && Value <= 0xffffff; 862 } 863 bool isImmThumbSR() const { 864 if (!isImm()) return false; 865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 866 if (!CE) return false; 867 int64_t Value = CE->getValue(); 868 return Value > 0 && Value < 33; 869 } 870 bool isPKHLSLImm() const { 871 if (!isImm()) return false; 872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 873 if (!CE) return false; 874 int64_t Value = CE->getValue(); 875 return Value >= 0 && Value < 32; 876 } 877 bool isPKHASRImm() const { 878 if (!isImm()) return false; 879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 880 if (!CE) return false; 881 int64_t Value = CE->getValue(); 882 return Value > 0 && Value <= 32; 883 } 884 bool isAdrLabel() const { 885 // If we have an immediate that's not a constant, treat it as a label 886 // reference needing a fixup. If it is a constant, but it can't fit 887 // into shift immediate encoding, we reject it. 888 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 889 else return (isARMSOImm() || isARMSOImmNeg()); 890 } 891 bool isARMSOImm() const { 892 if (!isImm()) return false; 893 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 894 if (!CE) return false; 895 int64_t Value = CE->getValue(); 896 return ARM_AM::getSOImmVal(Value) != -1; 897 } 898 bool isARMSOImmNot() const { 899 if (!isImm()) return false; 900 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 901 if (!CE) return false; 902 int64_t Value = CE->getValue(); 903 return ARM_AM::getSOImmVal(~Value) != -1; 904 } 905 bool isARMSOImmNeg() const { 906 if (!isImm()) return false; 907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 908 if (!CE) return false; 909 int64_t Value = CE->getValue(); 910 // Only use this when not representable as a plain so_imm. 911 return ARM_AM::getSOImmVal(Value) == -1 && 912 ARM_AM::getSOImmVal(-Value) != -1; 913 } 914 bool isT2SOImm() const { 915 if (!isImm()) return false; 916 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 917 if (!CE) return false; 918 int64_t Value = CE->getValue(); 919 return ARM_AM::getT2SOImmVal(Value) != -1; 920 } 921 bool isT2SOImmNot() const { 922 if (!isImm()) return false; 923 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 924 if (!CE) return false; 925 int64_t Value = CE->getValue(); 926 return ARM_AM::getT2SOImmVal(~Value) != -1; 927 } 928 bool isT2SOImmNeg() const { 929 if (!isImm()) return false; 930 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 931 if (!CE) return false; 932 int64_t Value = CE->getValue(); 933 // Only use this when not representable as a plain so_imm. 934 return ARM_AM::getT2SOImmVal(Value) == -1 && 935 ARM_AM::getT2SOImmVal(-Value) != -1; 936 } 937 bool isSetEndImm() const { 938 if (!isImm()) return false; 939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 940 if (!CE) return false; 941 int64_t Value = CE->getValue(); 942 return Value == 1 || Value == 0; 943 } 944 bool isReg() const { return Kind == k_Register; } 945 bool isRegList() const { return Kind == k_RegisterList; } 946 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 947 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 948 bool isToken() const { return Kind == k_Token; } 949 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 950 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 951 bool isMem() const { return Kind == k_Memory; } 952 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 953 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 954 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 955 bool isRotImm() const { return Kind == k_RotateImmediate; } 956 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 957 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 958 bool isPostIdxReg() const { 959 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 960 } 961 bool isMemNoOffset(bool alignOK = false) const { 962 if (!isMem()) 963 return false; 964 // No offset of any kind. 965 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 966 (alignOK || Memory.Alignment == 0); 967 } 968 bool isMemPCRelImm12() const { 969 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 970 return false; 971 // Base register must be PC. 972 if (Memory.BaseRegNum != ARM::PC) 973 return false; 974 // Immediate offset in range [-4095, 4095]. 975 if (!Memory.OffsetImm) return true; 976 int64_t Val = Memory.OffsetImm->getValue(); 977 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 978 } 979 bool isAlignedMemory() const { 980 return isMemNoOffset(true); 981 } 982 bool isAddrMode2() const { 983 if (!isMem() || Memory.Alignment != 0) return false; 984 // Check for register offset. 985 if (Memory.OffsetRegNum) return true; 986 // Immediate offset in range [-4095, 4095]. 987 if (!Memory.OffsetImm) return true; 988 int64_t Val = Memory.OffsetImm->getValue(); 989 return Val > -4096 && Val < 4096; 990 } 991 bool isAM2OffsetImm() const { 992 if (!isImm()) return false; 993 // Immediate offset in range [-4095, 4095]. 994 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 995 if (!CE) return false; 996 int64_t Val = CE->getValue(); 997 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 998 } 999 bool isAddrMode3() const { 1000 // If we have an immediate that's not a constant, treat it as a label 1001 // reference needing a fixup. If it is a constant, it's something else 1002 // and we reject it. 1003 if (isImm() && !isa<MCConstantExpr>(getImm())) 1004 return true; 1005 if (!isMem() || Memory.Alignment != 0) return false; 1006 // No shifts are legal for AM3. 1007 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1008 // Check for register offset. 1009 if (Memory.OffsetRegNum) return true; 1010 // Immediate offset in range [-255, 255]. 1011 if (!Memory.OffsetImm) return true; 1012 int64_t Val = Memory.OffsetImm->getValue(); 1013 // The #-0 offset is encoded as INT32_MIN, and we have to check 1014 // for this too. 1015 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1016 } 1017 bool isAM3Offset() const { 1018 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1019 return false; 1020 if (Kind == k_PostIndexRegister) 1021 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1022 // Immediate offset in range [-255, 255]. 1023 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1024 if (!CE) return false; 1025 int64_t Val = CE->getValue(); 1026 // Special case, #-0 is INT32_MIN. 1027 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1028 } 1029 bool isAddrMode5() const { 1030 // If we have an immediate that's not a constant, treat it as a label 1031 // reference needing a fixup. If it is a constant, it's something else 1032 // and we reject it. 1033 if (isImm() && !isa<MCConstantExpr>(getImm())) 1034 return true; 1035 if (!isMem() || Memory.Alignment != 0) return false; 1036 // Check for register offset. 1037 if (Memory.OffsetRegNum) return false; 1038 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1039 if (!Memory.OffsetImm) return true; 1040 int64_t Val = Memory.OffsetImm->getValue(); 1041 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1042 Val == INT32_MIN; 1043 } 1044 bool isMemTBB() const { 1045 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1046 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1047 return false; 1048 return true; 1049 } 1050 bool isMemTBH() const { 1051 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1052 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1053 Memory.Alignment != 0 ) 1054 return false; 1055 return true; 1056 } 1057 bool isMemRegOffset() const { 1058 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1059 return false; 1060 return true; 1061 } 1062 bool isT2MemRegOffset() const { 1063 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1064 Memory.Alignment != 0) 1065 return false; 1066 // Only lsl #{0, 1, 2, 3} allowed. 1067 if (Memory.ShiftType == ARM_AM::no_shift) 1068 return true; 1069 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1070 return false; 1071 return true; 1072 } 1073 bool isMemThumbRR() const { 1074 // Thumb reg+reg addressing is simple. Just two registers, a base and 1075 // an offset. No shifts, negations or any other complicating factors. 1076 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1077 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1078 return false; 1079 return isARMLowRegister(Memory.BaseRegNum) && 1080 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1081 } 1082 bool isMemThumbRIs4() const { 1083 if (!isMem() || Memory.OffsetRegNum != 0 || 1084 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1085 return false; 1086 // Immediate offset, multiple of 4 in range [0, 124]. 1087 if (!Memory.OffsetImm) return true; 1088 int64_t Val = Memory.OffsetImm->getValue(); 1089 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1090 } 1091 bool isMemThumbRIs2() const { 1092 if (!isMem() || Memory.OffsetRegNum != 0 || 1093 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1094 return false; 1095 // Immediate offset, multiple of 4 in range [0, 62]. 1096 if (!Memory.OffsetImm) return true; 1097 int64_t Val = Memory.OffsetImm->getValue(); 1098 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1099 } 1100 bool isMemThumbRIs1() const { 1101 if (!isMem() || Memory.OffsetRegNum != 0 || 1102 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1103 return false; 1104 // Immediate offset in range [0, 31]. 1105 if (!Memory.OffsetImm) return true; 1106 int64_t Val = Memory.OffsetImm->getValue(); 1107 return Val >= 0 && Val <= 31; 1108 } 1109 bool isMemThumbSPI() const { 1110 if (!isMem() || Memory.OffsetRegNum != 0 || 1111 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1112 return false; 1113 // Immediate offset, multiple of 4 in range [0, 1020]. 1114 if (!Memory.OffsetImm) return true; 1115 int64_t Val = Memory.OffsetImm->getValue(); 1116 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1117 } 1118 bool isMemImm8s4Offset() const { 1119 // If we have an immediate that's not a constant, treat it as a label 1120 // reference needing a fixup. If it is a constant, it's something else 1121 // and we reject it. 1122 if (isImm() && !isa<MCConstantExpr>(getImm())) 1123 return true; 1124 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1125 return false; 1126 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1127 if (!Memory.OffsetImm) return true; 1128 int64_t Val = Memory.OffsetImm->getValue(); 1129 // Special case, #-0 is INT32_MIN. 1130 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1131 } 1132 bool isMemImm0_1020s4Offset() const { 1133 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1134 return false; 1135 // Immediate offset a multiple of 4 in range [0, 1020]. 1136 if (!Memory.OffsetImm) return true; 1137 int64_t Val = Memory.OffsetImm->getValue(); 1138 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1139 } 1140 bool isMemImm8Offset() const { 1141 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1142 return false; 1143 // Base reg of PC isn't allowed for these encodings. 1144 if (Memory.BaseRegNum == ARM::PC) return false; 1145 // Immediate offset in range [-255, 255]. 1146 if (!Memory.OffsetImm) return true; 1147 int64_t Val = Memory.OffsetImm->getValue(); 1148 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1149 } 1150 bool isMemPosImm8Offset() const { 1151 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1152 return false; 1153 // Immediate offset in range [0, 255]. 1154 if (!Memory.OffsetImm) return true; 1155 int64_t Val = Memory.OffsetImm->getValue(); 1156 return Val >= 0 && Val < 256; 1157 } 1158 bool isMemNegImm8Offset() const { 1159 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1160 return false; 1161 // Base reg of PC isn't allowed for these encodings. 1162 if (Memory.BaseRegNum == ARM::PC) return false; 1163 // Immediate offset in range [-255, -1]. 1164 if (!Memory.OffsetImm) return false; 1165 int64_t Val = Memory.OffsetImm->getValue(); 1166 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1167 } 1168 bool isMemUImm12Offset() const { 1169 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1170 return false; 1171 // Immediate offset in range [0, 4095]. 1172 if (!Memory.OffsetImm) return true; 1173 int64_t Val = Memory.OffsetImm->getValue(); 1174 return (Val >= 0 && Val < 4096); 1175 } 1176 bool isMemImm12Offset() const { 1177 // If we have an immediate that's not a constant, treat it as a label 1178 // reference needing a fixup. If it is a constant, it's something else 1179 // and we reject it. 1180 if (isImm() && !isa<MCConstantExpr>(getImm())) 1181 return true; 1182 1183 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1184 return false; 1185 // Immediate offset in range [-4095, 4095]. 1186 if (!Memory.OffsetImm) return true; 1187 int64_t Val = Memory.OffsetImm->getValue(); 1188 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1189 } 1190 bool isPostIdxImm8() const { 1191 if (!isImm()) return false; 1192 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1193 if (!CE) return false; 1194 int64_t Val = CE->getValue(); 1195 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1196 } 1197 bool isPostIdxImm8s4() const { 1198 if (!isImm()) return false; 1199 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1200 if (!CE) return false; 1201 int64_t Val = CE->getValue(); 1202 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1203 (Val == INT32_MIN); 1204 } 1205 1206 bool isMSRMask() const { return Kind == k_MSRMask; } 1207 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1208 1209 // NEON operands. 1210 bool isSingleSpacedVectorList() const { 1211 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1212 } 1213 bool isDoubleSpacedVectorList() const { 1214 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1215 } 1216 bool isVecListOneD() const { 1217 if (!isSingleSpacedVectorList()) return false; 1218 return VectorList.Count == 1; 1219 } 1220 1221 bool isVecListDPair() const { 1222 if (!isSingleSpacedVectorList()) return false; 1223 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1224 .contains(VectorList.RegNum)); 1225 } 1226 1227 bool isVecListThreeD() const { 1228 if (!isSingleSpacedVectorList()) return false; 1229 return VectorList.Count == 3; 1230 } 1231 1232 bool isVecListFourD() const { 1233 if (!isSingleSpacedVectorList()) return false; 1234 return VectorList.Count == 4; 1235 } 1236 1237 bool isVecListDPairSpaced() const { 1238 if (isSingleSpacedVectorList()) return false; 1239 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1240 .contains(VectorList.RegNum)); 1241 } 1242 1243 bool isVecListThreeQ() const { 1244 if (!isDoubleSpacedVectorList()) return false; 1245 return VectorList.Count == 3; 1246 } 1247 1248 bool isVecListFourQ() const { 1249 if (!isDoubleSpacedVectorList()) return false; 1250 return VectorList.Count == 4; 1251 } 1252 1253 bool isSingleSpacedVectorAllLanes() const { 1254 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1255 } 1256 bool isDoubleSpacedVectorAllLanes() const { 1257 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1258 } 1259 bool isVecListOneDAllLanes() const { 1260 if (!isSingleSpacedVectorAllLanes()) return false; 1261 return VectorList.Count == 1; 1262 } 1263 1264 bool isVecListDPairAllLanes() const { 1265 if (!isSingleSpacedVectorAllLanes()) return false; 1266 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1267 .contains(VectorList.RegNum)); 1268 } 1269 1270 bool isVecListDPairSpacedAllLanes() const { 1271 if (!isDoubleSpacedVectorAllLanes()) return false; 1272 return VectorList.Count == 2; 1273 } 1274 1275 bool isVecListThreeDAllLanes() const { 1276 if (!isSingleSpacedVectorAllLanes()) return false; 1277 return VectorList.Count == 3; 1278 } 1279 1280 bool isVecListThreeQAllLanes() const { 1281 if (!isDoubleSpacedVectorAllLanes()) return false; 1282 return VectorList.Count == 3; 1283 } 1284 1285 bool isVecListFourDAllLanes() const { 1286 if (!isSingleSpacedVectorAllLanes()) return false; 1287 return VectorList.Count == 4; 1288 } 1289 1290 bool isVecListFourQAllLanes() const { 1291 if (!isDoubleSpacedVectorAllLanes()) return false; 1292 return VectorList.Count == 4; 1293 } 1294 1295 bool isSingleSpacedVectorIndexed() const { 1296 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1297 } 1298 bool isDoubleSpacedVectorIndexed() const { 1299 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1300 } 1301 bool isVecListOneDByteIndexed() const { 1302 if (!isSingleSpacedVectorIndexed()) return false; 1303 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1304 } 1305 1306 bool isVecListOneDHWordIndexed() const { 1307 if (!isSingleSpacedVectorIndexed()) return false; 1308 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1309 } 1310 1311 bool isVecListOneDWordIndexed() const { 1312 if (!isSingleSpacedVectorIndexed()) return false; 1313 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1314 } 1315 1316 bool isVecListTwoDByteIndexed() const { 1317 if (!isSingleSpacedVectorIndexed()) return false; 1318 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1319 } 1320 1321 bool isVecListTwoDHWordIndexed() const { 1322 if (!isSingleSpacedVectorIndexed()) return false; 1323 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1324 } 1325 1326 bool isVecListTwoQWordIndexed() const { 1327 if (!isDoubleSpacedVectorIndexed()) return false; 1328 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1329 } 1330 1331 bool isVecListTwoQHWordIndexed() const { 1332 if (!isDoubleSpacedVectorIndexed()) return false; 1333 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1334 } 1335 1336 bool isVecListTwoDWordIndexed() const { 1337 if (!isSingleSpacedVectorIndexed()) return false; 1338 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1339 } 1340 1341 bool isVecListThreeDByteIndexed() const { 1342 if (!isSingleSpacedVectorIndexed()) return false; 1343 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1344 } 1345 1346 bool isVecListThreeDHWordIndexed() const { 1347 if (!isSingleSpacedVectorIndexed()) return false; 1348 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1349 } 1350 1351 bool isVecListThreeQWordIndexed() const { 1352 if (!isDoubleSpacedVectorIndexed()) return false; 1353 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1354 } 1355 1356 bool isVecListThreeQHWordIndexed() const { 1357 if (!isDoubleSpacedVectorIndexed()) return false; 1358 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1359 } 1360 1361 bool isVecListThreeDWordIndexed() const { 1362 if (!isSingleSpacedVectorIndexed()) return false; 1363 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1364 } 1365 1366 bool isVecListFourDByteIndexed() const { 1367 if (!isSingleSpacedVectorIndexed()) return false; 1368 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1369 } 1370 1371 bool isVecListFourDHWordIndexed() const { 1372 if (!isSingleSpacedVectorIndexed()) return false; 1373 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1374 } 1375 1376 bool isVecListFourQWordIndexed() const { 1377 if (!isDoubleSpacedVectorIndexed()) return false; 1378 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1379 } 1380 1381 bool isVecListFourQHWordIndexed() const { 1382 if (!isDoubleSpacedVectorIndexed()) return false; 1383 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1384 } 1385 1386 bool isVecListFourDWordIndexed() const { 1387 if (!isSingleSpacedVectorIndexed()) return false; 1388 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1389 } 1390 1391 bool isVectorIndex8() const { 1392 if (Kind != k_VectorIndex) return false; 1393 return VectorIndex.Val < 8; 1394 } 1395 bool isVectorIndex16() const { 1396 if (Kind != k_VectorIndex) return false; 1397 return VectorIndex.Val < 4; 1398 } 1399 bool isVectorIndex32() const { 1400 if (Kind != k_VectorIndex) return false; 1401 return VectorIndex.Val < 2; 1402 } 1403 1404 bool isNEONi8splat() const { 1405 if (!isImm()) return false; 1406 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1407 // Must be a constant. 1408 if (!CE) return false; 1409 int64_t Value = CE->getValue(); 1410 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1411 // value. 1412 return Value >= 0 && Value < 256; 1413 } 1414 1415 bool isNEONi16splat() const { 1416 if (!isImm()) return false; 1417 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1418 // Must be a constant. 1419 if (!CE) return false; 1420 int64_t Value = CE->getValue(); 1421 // i16 value in the range [0,255] or [0x0100, 0xff00] 1422 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1423 } 1424 1425 bool isNEONi32splat() const { 1426 if (!isImm()) return false; 1427 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1428 // Must be a constant. 1429 if (!CE) return false; 1430 int64_t Value = CE->getValue(); 1431 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1432 return (Value >= 0 && Value < 256) || 1433 (Value >= 0x0100 && Value <= 0xff00) || 1434 (Value >= 0x010000 && Value <= 0xff0000) || 1435 (Value >= 0x01000000 && Value <= 0xff000000); 1436 } 1437 1438 bool isNEONi32vmov() const { 1439 if (!isImm()) return false; 1440 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1441 // Must be a constant. 1442 if (!CE) return false; 1443 int64_t Value = CE->getValue(); 1444 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1445 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1446 return (Value >= 0 && Value < 256) || 1447 (Value >= 0x0100 && Value <= 0xff00) || 1448 (Value >= 0x010000 && Value <= 0xff0000) || 1449 (Value >= 0x01000000 && Value <= 0xff000000) || 1450 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1451 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1452 } 1453 bool isNEONi32vmovNeg() const { 1454 if (!isImm()) return false; 1455 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1456 // Must be a constant. 1457 if (!CE) return false; 1458 int64_t Value = ~CE->getValue(); 1459 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1460 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1461 return (Value >= 0 && Value < 256) || 1462 (Value >= 0x0100 && Value <= 0xff00) || 1463 (Value >= 0x010000 && Value <= 0xff0000) || 1464 (Value >= 0x01000000 && Value <= 0xff000000) || 1465 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1466 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1467 } 1468 1469 bool isNEONi64splat() const { 1470 if (!isImm()) return false; 1471 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1472 // Must be a constant. 1473 if (!CE) return false; 1474 uint64_t Value = CE->getValue(); 1475 // i64 value with each byte being either 0 or 0xff. 1476 for (unsigned i = 0; i < 8; ++i) 1477 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1478 return true; 1479 } 1480 1481 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1482 // Add as immediates when possible. Null MCExpr = 0. 1483 if (Expr == 0) 1484 Inst.addOperand(MCOperand::CreateImm(0)); 1485 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1486 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1487 else 1488 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1489 } 1490 1491 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1492 assert(N == 2 && "Invalid number of operands!"); 1493 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1494 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1495 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1496 } 1497 1498 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1499 assert(N == 1 && "Invalid number of operands!"); 1500 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1501 } 1502 1503 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1504 assert(N == 1 && "Invalid number of operands!"); 1505 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1506 } 1507 1508 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1509 assert(N == 1 && "Invalid number of operands!"); 1510 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1511 } 1512 1513 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1514 assert(N == 1 && "Invalid number of operands!"); 1515 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1516 } 1517 1518 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1519 assert(N == 1 && "Invalid number of operands!"); 1520 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1521 } 1522 1523 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1524 assert(N == 1 && "Invalid number of operands!"); 1525 Inst.addOperand(MCOperand::CreateReg(getReg())); 1526 } 1527 1528 void addRegOperands(MCInst &Inst, unsigned N) const { 1529 assert(N == 1 && "Invalid number of operands!"); 1530 Inst.addOperand(MCOperand::CreateReg(getReg())); 1531 } 1532 1533 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1534 assert(N == 3 && "Invalid number of operands!"); 1535 assert(isRegShiftedReg() && 1536 "addRegShiftedRegOperands() on non RegShiftedReg!"); 1537 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1538 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1539 Inst.addOperand(MCOperand::CreateImm( 1540 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1541 } 1542 1543 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1544 assert(N == 2 && "Invalid number of operands!"); 1545 assert(isRegShiftedImm() && 1546 "addRegShiftedImmOperands() on non RegShiftedImm!"); 1547 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1548 // Shift of #32 is encoded as 0 where permitted 1549 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1550 Inst.addOperand(MCOperand::CreateImm( 1551 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1552 } 1553 1554 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1555 assert(N == 1 && "Invalid number of operands!"); 1556 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1557 ShifterImm.Imm)); 1558 } 1559 1560 void addRegListOperands(MCInst &Inst, unsigned N) const { 1561 assert(N == 1 && "Invalid number of operands!"); 1562 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1563 for (SmallVectorImpl<unsigned>::const_iterator 1564 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1565 Inst.addOperand(MCOperand::CreateReg(*I)); 1566 } 1567 1568 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1569 addRegListOperands(Inst, N); 1570 } 1571 1572 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1573 addRegListOperands(Inst, N); 1574 } 1575 1576 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1577 assert(N == 1 && "Invalid number of operands!"); 1578 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1579 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1580 } 1581 1582 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1583 assert(N == 1 && "Invalid number of operands!"); 1584 // Munge the lsb/width into a bitfield mask. 1585 unsigned lsb = Bitfield.LSB; 1586 unsigned width = Bitfield.Width; 1587 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1588 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1589 (32 - (lsb + width))); 1590 Inst.addOperand(MCOperand::CreateImm(Mask)); 1591 } 1592 1593 void addImmOperands(MCInst &Inst, unsigned N) const { 1594 assert(N == 1 && "Invalid number of operands!"); 1595 addExpr(Inst, getImm()); 1596 } 1597 1598 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1599 assert(N == 1 && "Invalid number of operands!"); 1600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1601 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1602 } 1603 1604 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1605 assert(N == 1 && "Invalid number of operands!"); 1606 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1607 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1608 } 1609 1610 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1611 assert(N == 1 && "Invalid number of operands!"); 1612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1613 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1614 Inst.addOperand(MCOperand::CreateImm(Val)); 1615 } 1616 1617 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1618 assert(N == 1 && "Invalid number of operands!"); 1619 // FIXME: We really want to scale the value here, but the LDRD/STRD 1620 // instruction don't encode operands that way yet. 1621 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1622 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1623 } 1624 1625 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1626 assert(N == 1 && "Invalid number of operands!"); 1627 // The immediate is scaled by four in the encoding and is stored 1628 // in the MCInst as such. Lop off the low two bits here. 1629 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1630 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1631 } 1632 1633 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1634 assert(N == 1 && "Invalid number of operands!"); 1635 // The immediate is scaled by four in the encoding and is stored 1636 // in the MCInst as such. Lop off the low two bits here. 1637 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1638 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1639 } 1640 1641 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1642 assert(N == 1 && "Invalid number of operands!"); 1643 // The immediate is scaled by four in the encoding and is stored 1644 // in the MCInst as such. Lop off the low two bits here. 1645 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1646 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1647 } 1648 1649 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1650 assert(N == 1 && "Invalid number of operands!"); 1651 // The constant encodes as the immediate-1, and we store in the instruction 1652 // the bits as encoded, so subtract off one here. 1653 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1654 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1655 } 1656 1657 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1658 assert(N == 1 && "Invalid number of operands!"); 1659 // The constant encodes as the immediate-1, and we store in the instruction 1660 // the bits as encoded, so subtract off one here. 1661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1662 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1663 } 1664 1665 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1666 assert(N == 1 && "Invalid number of operands!"); 1667 // The constant encodes as the immediate, except for 32, which encodes as 1668 // zero. 1669 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1670 unsigned Imm = CE->getValue(); 1671 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1672 } 1673 1674 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1675 assert(N == 1 && "Invalid number of operands!"); 1676 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1677 // the instruction as well. 1678 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1679 int Val = CE->getValue(); 1680 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1681 } 1682 1683 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1684 assert(N == 1 && "Invalid number of operands!"); 1685 // The operand is actually a t2_so_imm, but we have its bitwise 1686 // negation in the assembly source, so twiddle it here. 1687 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1688 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1689 } 1690 1691 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1692 assert(N == 1 && "Invalid number of operands!"); 1693 // The operand is actually a t2_so_imm, but we have its 1694 // negation in the assembly source, so twiddle it here. 1695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1696 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1697 } 1698 1699 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1700 assert(N == 1 && "Invalid number of operands!"); 1701 // The operand is actually an imm0_4095, but we have its 1702 // negation in the assembly source, so twiddle it here. 1703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1704 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1705 } 1706 1707 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1708 assert(N == 1 && "Invalid number of operands!"); 1709 // The operand is actually a so_imm, but we have its bitwise 1710 // negation in the assembly source, so twiddle it here. 1711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1712 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1713 } 1714 1715 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1716 assert(N == 1 && "Invalid number of operands!"); 1717 // The operand is actually a so_imm, but we have its 1718 // negation in the assembly source, so twiddle it here. 1719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1720 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1721 } 1722 1723 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1724 assert(N == 1 && "Invalid number of operands!"); 1725 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1726 } 1727 1728 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 1729 assert(N == 1 && "Invalid number of operands!"); 1730 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); 1731 } 1732 1733 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1734 assert(N == 1 && "Invalid number of operands!"); 1735 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1736 } 1737 1738 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1739 assert(N == 1 && "Invalid number of operands!"); 1740 int32_t Imm = Memory.OffsetImm->getValue(); 1741 // FIXME: Handle #-0 1742 if (Imm == INT32_MIN) Imm = 0; 1743 Inst.addOperand(MCOperand::CreateImm(Imm)); 1744 } 1745 1746 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1747 assert(N == 1 && "Invalid number of operands!"); 1748 assert(isImm() && "Not an immediate!"); 1749 1750 // If we have an immediate that's not a constant, treat it as a label 1751 // reference needing a fixup. 1752 if (!isa<MCConstantExpr>(getImm())) { 1753 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1754 return; 1755 } 1756 1757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1758 int Val = CE->getValue(); 1759 Inst.addOperand(MCOperand::CreateImm(Val)); 1760 } 1761 1762 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1763 assert(N == 2 && "Invalid number of operands!"); 1764 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1765 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1766 } 1767 1768 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1769 assert(N == 3 && "Invalid number of operands!"); 1770 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1771 if (!Memory.OffsetRegNum) { 1772 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1773 // Special case for #-0 1774 if (Val == INT32_MIN) Val = 0; 1775 if (Val < 0) Val = -Val; 1776 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1777 } else { 1778 // For register offset, we encode the shift type and negation flag 1779 // here. 1780 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1781 Memory.ShiftImm, Memory.ShiftType); 1782 } 1783 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1784 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1785 Inst.addOperand(MCOperand::CreateImm(Val)); 1786 } 1787 1788 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1789 assert(N == 2 && "Invalid number of operands!"); 1790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1791 assert(CE && "non-constant AM2OffsetImm operand!"); 1792 int32_t Val = CE->getValue(); 1793 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1794 // Special case for #-0 1795 if (Val == INT32_MIN) Val = 0; 1796 if (Val < 0) Val = -Val; 1797 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1798 Inst.addOperand(MCOperand::CreateReg(0)); 1799 Inst.addOperand(MCOperand::CreateImm(Val)); 1800 } 1801 1802 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1803 assert(N == 3 && "Invalid number of operands!"); 1804 // If we have an immediate that's not a constant, treat it as a label 1805 // reference needing a fixup. If it is a constant, it's something else 1806 // and we reject it. 1807 if (isImm()) { 1808 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1809 Inst.addOperand(MCOperand::CreateReg(0)); 1810 Inst.addOperand(MCOperand::CreateImm(0)); 1811 return; 1812 } 1813 1814 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1815 if (!Memory.OffsetRegNum) { 1816 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1817 // Special case for #-0 1818 if (Val == INT32_MIN) Val = 0; 1819 if (Val < 0) Val = -Val; 1820 Val = ARM_AM::getAM3Opc(AddSub, Val); 1821 } else { 1822 // For register offset, we encode the shift type and negation flag 1823 // here. 1824 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1825 } 1826 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1827 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1828 Inst.addOperand(MCOperand::CreateImm(Val)); 1829 } 1830 1831 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1832 assert(N == 2 && "Invalid number of operands!"); 1833 if (Kind == k_PostIndexRegister) { 1834 int32_t Val = 1835 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1836 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1837 Inst.addOperand(MCOperand::CreateImm(Val)); 1838 return; 1839 } 1840 1841 // Constant offset. 1842 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1843 int32_t Val = CE->getValue(); 1844 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1845 // Special case for #-0 1846 if (Val == INT32_MIN) Val = 0; 1847 if (Val < 0) Val = -Val; 1848 Val = ARM_AM::getAM3Opc(AddSub, Val); 1849 Inst.addOperand(MCOperand::CreateReg(0)); 1850 Inst.addOperand(MCOperand::CreateImm(Val)); 1851 } 1852 1853 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1854 assert(N == 2 && "Invalid number of operands!"); 1855 // If we have an immediate that's not a constant, treat it as a label 1856 // reference needing a fixup. If it is a constant, it's something else 1857 // and we reject it. 1858 if (isImm()) { 1859 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1860 Inst.addOperand(MCOperand::CreateImm(0)); 1861 return; 1862 } 1863 1864 // The lower two bits are always zero and as such are not encoded. 1865 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1866 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1867 // Special case for #-0 1868 if (Val == INT32_MIN) Val = 0; 1869 if (Val < 0) Val = -Val; 1870 Val = ARM_AM::getAM5Opc(AddSub, Val); 1871 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1872 Inst.addOperand(MCOperand::CreateImm(Val)); 1873 } 1874 1875 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1876 assert(N == 2 && "Invalid number of operands!"); 1877 // If we have an immediate that's not a constant, treat it as a label 1878 // reference needing a fixup. If it is a constant, it's something else 1879 // and we reject it. 1880 if (isImm()) { 1881 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1882 Inst.addOperand(MCOperand::CreateImm(0)); 1883 return; 1884 } 1885 1886 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1887 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1888 Inst.addOperand(MCOperand::CreateImm(Val)); 1889 } 1890 1891 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1892 assert(N == 2 && "Invalid number of operands!"); 1893 // The lower two bits are always zero and as such are not encoded. 1894 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1895 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1896 Inst.addOperand(MCOperand::CreateImm(Val)); 1897 } 1898 1899 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1900 assert(N == 2 && "Invalid number of operands!"); 1901 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1902 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1903 Inst.addOperand(MCOperand::CreateImm(Val)); 1904 } 1905 1906 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1907 addMemImm8OffsetOperands(Inst, N); 1908 } 1909 1910 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1911 addMemImm8OffsetOperands(Inst, N); 1912 } 1913 1914 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1915 assert(N == 2 && "Invalid number of operands!"); 1916 // If this is an immediate, it's a label reference. 1917 if (isImm()) { 1918 addExpr(Inst, getImm()); 1919 Inst.addOperand(MCOperand::CreateImm(0)); 1920 return; 1921 } 1922 1923 // Otherwise, it's a normal memory reg+offset. 1924 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1925 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1926 Inst.addOperand(MCOperand::CreateImm(Val)); 1927 } 1928 1929 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1930 assert(N == 2 && "Invalid number of operands!"); 1931 // If this is an immediate, it's a label reference. 1932 if (isImm()) { 1933 addExpr(Inst, getImm()); 1934 Inst.addOperand(MCOperand::CreateImm(0)); 1935 return; 1936 } 1937 1938 // Otherwise, it's a normal memory reg+offset. 1939 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1940 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1941 Inst.addOperand(MCOperand::CreateImm(Val)); 1942 } 1943 1944 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 1945 assert(N == 2 && "Invalid number of operands!"); 1946 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1947 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1948 } 1949 1950 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 1951 assert(N == 2 && "Invalid number of operands!"); 1952 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1953 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1954 } 1955 1956 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1957 assert(N == 3 && "Invalid number of operands!"); 1958 unsigned Val = 1959 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1960 Memory.ShiftImm, Memory.ShiftType); 1961 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1962 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1963 Inst.addOperand(MCOperand::CreateImm(Val)); 1964 } 1965 1966 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1967 assert(N == 3 && "Invalid number of operands!"); 1968 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1969 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1970 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1971 } 1972 1973 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1974 assert(N == 2 && "Invalid number of operands!"); 1975 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1976 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1977 } 1978 1979 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1980 assert(N == 2 && "Invalid number of operands!"); 1981 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1982 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1983 Inst.addOperand(MCOperand::CreateImm(Val)); 1984 } 1985 1986 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1987 assert(N == 2 && "Invalid number of operands!"); 1988 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1989 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1990 Inst.addOperand(MCOperand::CreateImm(Val)); 1991 } 1992 1993 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1994 assert(N == 2 && "Invalid number of operands!"); 1995 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1996 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1997 Inst.addOperand(MCOperand::CreateImm(Val)); 1998 } 1999 2000 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2001 assert(N == 2 && "Invalid number of operands!"); 2002 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2003 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2004 Inst.addOperand(MCOperand::CreateImm(Val)); 2005 } 2006 2007 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2008 assert(N == 1 && "Invalid number of operands!"); 2009 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2010 assert(CE && "non-constant post-idx-imm8 operand!"); 2011 int Imm = CE->getValue(); 2012 bool isAdd = Imm >= 0; 2013 if (Imm == INT32_MIN) Imm = 0; 2014 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2015 Inst.addOperand(MCOperand::CreateImm(Imm)); 2016 } 2017 2018 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2019 assert(N == 1 && "Invalid number of operands!"); 2020 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2021 assert(CE && "non-constant post-idx-imm8s4 operand!"); 2022 int Imm = CE->getValue(); 2023 bool isAdd = Imm >= 0; 2024 if (Imm == INT32_MIN) Imm = 0; 2025 // Immediate is scaled by 4. 2026 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2027 Inst.addOperand(MCOperand::CreateImm(Imm)); 2028 } 2029 2030 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2031 assert(N == 2 && "Invalid number of operands!"); 2032 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2033 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 2034 } 2035 2036 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2037 assert(N == 2 && "Invalid number of operands!"); 2038 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2039 // The sign, shift type, and shift amount are encoded in a single operand 2040 // using the AM2 encoding helpers. 2041 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2042 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2043 PostIdxReg.ShiftTy); 2044 Inst.addOperand(MCOperand::CreateImm(Imm)); 2045 } 2046 2047 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2048 assert(N == 1 && "Invalid number of operands!"); 2049 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 2050 } 2051 2052 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2053 assert(N == 1 && "Invalid number of operands!"); 2054 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 2055 } 2056 2057 void addVecListOperands(MCInst &Inst, unsigned N) const { 2058 assert(N == 1 && "Invalid number of operands!"); 2059 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2060 } 2061 2062 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2063 assert(N == 2 && "Invalid number of operands!"); 2064 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2065 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 2066 } 2067 2068 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2069 assert(N == 1 && "Invalid number of operands!"); 2070 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2071 } 2072 2073 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2074 assert(N == 1 && "Invalid number of operands!"); 2075 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2076 } 2077 2078 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2079 assert(N == 1 && "Invalid number of operands!"); 2080 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2081 } 2082 2083 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2084 assert(N == 1 && "Invalid number of operands!"); 2085 // The immediate encodes the type of constant as well as the value. 2086 // Mask in that this is an i8 splat. 2087 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2088 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 2089 } 2090 2091 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2092 assert(N == 1 && "Invalid number of operands!"); 2093 // The immediate encodes the type of constant as well as the value. 2094 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2095 unsigned Value = CE->getValue(); 2096 if (Value >= 256) 2097 Value = (Value >> 8) | 0xa00; 2098 else 2099 Value |= 0x800; 2100 Inst.addOperand(MCOperand::CreateImm(Value)); 2101 } 2102 2103 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2104 assert(N == 1 && "Invalid number of operands!"); 2105 // The immediate encodes the type of constant as well as the value. 2106 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2107 unsigned Value = CE->getValue(); 2108 if (Value >= 256 && Value <= 0xff00) 2109 Value = (Value >> 8) | 0x200; 2110 else if (Value > 0xffff && Value <= 0xff0000) 2111 Value = (Value >> 16) | 0x400; 2112 else if (Value > 0xffffff) 2113 Value = (Value >> 24) | 0x600; 2114 Inst.addOperand(MCOperand::CreateImm(Value)); 2115 } 2116 2117 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2118 assert(N == 1 && "Invalid number of operands!"); 2119 // The immediate encodes the type of constant as well as the value. 2120 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2121 unsigned Value = CE->getValue(); 2122 if (Value >= 256 && Value <= 0xffff) 2123 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2124 else if (Value > 0xffff && Value <= 0xffffff) 2125 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2126 else if (Value > 0xffffff) 2127 Value = (Value >> 24) | 0x600; 2128 Inst.addOperand(MCOperand::CreateImm(Value)); 2129 } 2130 2131 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2132 assert(N == 1 && "Invalid number of operands!"); 2133 // The immediate encodes the type of constant as well as the value. 2134 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2135 unsigned Value = ~CE->getValue(); 2136 if (Value >= 256 && Value <= 0xffff) 2137 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2138 else if (Value > 0xffff && Value <= 0xffffff) 2139 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2140 else if (Value > 0xffffff) 2141 Value = (Value >> 24) | 0x600; 2142 Inst.addOperand(MCOperand::CreateImm(Value)); 2143 } 2144 2145 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2146 assert(N == 1 && "Invalid number of operands!"); 2147 // The immediate encodes the type of constant as well as the value. 2148 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2149 uint64_t Value = CE->getValue(); 2150 unsigned Imm = 0; 2151 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2152 Imm |= (Value & 1) << i; 2153 } 2154 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2155 } 2156 2157 virtual void print(raw_ostream &OS) const; 2158 2159 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2160 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2161 Op->ITMask.Mask = Mask; 2162 Op->StartLoc = S; 2163 Op->EndLoc = S; 2164 return Op; 2165 } 2166 2167 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2168 ARMOperand *Op = new ARMOperand(k_CondCode); 2169 Op->CC.Val = CC; 2170 Op->StartLoc = S; 2171 Op->EndLoc = S; 2172 return Op; 2173 } 2174 2175 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2176 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2177 Op->Cop.Val = CopVal; 2178 Op->StartLoc = S; 2179 Op->EndLoc = S; 2180 return Op; 2181 } 2182 2183 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2184 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2185 Op->Cop.Val = CopVal; 2186 Op->StartLoc = S; 2187 Op->EndLoc = S; 2188 return Op; 2189 } 2190 2191 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2192 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2193 Op->Cop.Val = Val; 2194 Op->StartLoc = S; 2195 Op->EndLoc = E; 2196 return Op; 2197 } 2198 2199 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2200 ARMOperand *Op = new ARMOperand(k_CCOut); 2201 Op->Reg.RegNum = RegNum; 2202 Op->StartLoc = S; 2203 Op->EndLoc = S; 2204 return Op; 2205 } 2206 2207 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2208 ARMOperand *Op = new ARMOperand(k_Token); 2209 Op->Tok.Data = Str.data(); 2210 Op->Tok.Length = Str.size(); 2211 Op->StartLoc = S; 2212 Op->EndLoc = S; 2213 return Op; 2214 } 2215 2216 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2217 ARMOperand *Op = new ARMOperand(k_Register); 2218 Op->Reg.RegNum = RegNum; 2219 Op->StartLoc = S; 2220 Op->EndLoc = E; 2221 return Op; 2222 } 2223 2224 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2225 unsigned SrcReg, 2226 unsigned ShiftReg, 2227 unsigned ShiftImm, 2228 SMLoc S, SMLoc E) { 2229 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2230 Op->RegShiftedReg.ShiftTy = ShTy; 2231 Op->RegShiftedReg.SrcReg = SrcReg; 2232 Op->RegShiftedReg.ShiftReg = ShiftReg; 2233 Op->RegShiftedReg.ShiftImm = ShiftImm; 2234 Op->StartLoc = S; 2235 Op->EndLoc = E; 2236 return Op; 2237 } 2238 2239 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2240 unsigned SrcReg, 2241 unsigned ShiftImm, 2242 SMLoc S, SMLoc E) { 2243 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2244 Op->RegShiftedImm.ShiftTy = ShTy; 2245 Op->RegShiftedImm.SrcReg = SrcReg; 2246 Op->RegShiftedImm.ShiftImm = ShiftImm; 2247 Op->StartLoc = S; 2248 Op->EndLoc = E; 2249 return Op; 2250 } 2251 2252 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2253 SMLoc S, SMLoc E) { 2254 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2255 Op->ShifterImm.isASR = isASR; 2256 Op->ShifterImm.Imm = Imm; 2257 Op->StartLoc = S; 2258 Op->EndLoc = E; 2259 return Op; 2260 } 2261 2262 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2263 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2264 Op->RotImm.Imm = Imm; 2265 Op->StartLoc = S; 2266 Op->EndLoc = E; 2267 return Op; 2268 } 2269 2270 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2271 SMLoc S, SMLoc E) { 2272 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2273 Op->Bitfield.LSB = LSB; 2274 Op->Bitfield.Width = Width; 2275 Op->StartLoc = S; 2276 Op->EndLoc = E; 2277 return Op; 2278 } 2279 2280 static ARMOperand * 2281 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2282 SMLoc StartLoc, SMLoc EndLoc) { 2283 KindTy Kind = k_RegisterList; 2284 2285 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 2286 Kind = k_DPRRegisterList; 2287 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2288 contains(Regs.front().first)) 2289 Kind = k_SPRRegisterList; 2290 2291 ARMOperand *Op = new ARMOperand(Kind); 2292 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 2293 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2294 Op->Registers.push_back(I->first); 2295 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2296 Op->StartLoc = StartLoc; 2297 Op->EndLoc = EndLoc; 2298 return Op; 2299 } 2300 2301 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2302 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2303 ARMOperand *Op = new ARMOperand(k_VectorList); 2304 Op->VectorList.RegNum = RegNum; 2305 Op->VectorList.Count = Count; 2306 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2307 Op->StartLoc = S; 2308 Op->EndLoc = E; 2309 return Op; 2310 } 2311 2312 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2313 bool isDoubleSpaced, 2314 SMLoc S, SMLoc E) { 2315 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2316 Op->VectorList.RegNum = RegNum; 2317 Op->VectorList.Count = Count; 2318 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2319 Op->StartLoc = S; 2320 Op->EndLoc = E; 2321 return Op; 2322 } 2323 2324 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2325 unsigned Index, 2326 bool isDoubleSpaced, 2327 SMLoc S, SMLoc E) { 2328 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2329 Op->VectorList.RegNum = RegNum; 2330 Op->VectorList.Count = Count; 2331 Op->VectorList.LaneIndex = Index; 2332 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2333 Op->StartLoc = S; 2334 Op->EndLoc = E; 2335 return Op; 2336 } 2337 2338 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2339 MCContext &Ctx) { 2340 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2341 Op->VectorIndex.Val = Idx; 2342 Op->StartLoc = S; 2343 Op->EndLoc = E; 2344 return Op; 2345 } 2346 2347 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2348 ARMOperand *Op = new ARMOperand(k_Immediate); 2349 Op->Imm.Val = Val; 2350 Op->StartLoc = S; 2351 Op->EndLoc = E; 2352 return Op; 2353 } 2354 2355 static ARMOperand *CreateMem(unsigned BaseRegNum, 2356 const MCConstantExpr *OffsetImm, 2357 unsigned OffsetRegNum, 2358 ARM_AM::ShiftOpc ShiftType, 2359 unsigned ShiftImm, 2360 unsigned Alignment, 2361 bool isNegative, 2362 SMLoc S, SMLoc E) { 2363 ARMOperand *Op = new ARMOperand(k_Memory); 2364 Op->Memory.BaseRegNum = BaseRegNum; 2365 Op->Memory.OffsetImm = OffsetImm; 2366 Op->Memory.OffsetRegNum = OffsetRegNum; 2367 Op->Memory.ShiftType = ShiftType; 2368 Op->Memory.ShiftImm = ShiftImm; 2369 Op->Memory.Alignment = Alignment; 2370 Op->Memory.isNegative = isNegative; 2371 Op->StartLoc = S; 2372 Op->EndLoc = E; 2373 return Op; 2374 } 2375 2376 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2377 ARM_AM::ShiftOpc ShiftTy, 2378 unsigned ShiftImm, 2379 SMLoc S, SMLoc E) { 2380 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2381 Op->PostIdxReg.RegNum = RegNum; 2382 Op->PostIdxReg.isAdd = isAdd; 2383 Op->PostIdxReg.ShiftTy = ShiftTy; 2384 Op->PostIdxReg.ShiftImm = ShiftImm; 2385 Op->StartLoc = S; 2386 Op->EndLoc = E; 2387 return Op; 2388 } 2389 2390 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2391 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2392 Op->MBOpt.Val = Opt; 2393 Op->StartLoc = S; 2394 Op->EndLoc = S; 2395 return Op; 2396 } 2397 2398 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, 2399 SMLoc S) { 2400 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt); 2401 Op->ISBOpt.Val = Opt; 2402 Op->StartLoc = S; 2403 Op->EndLoc = S; 2404 return Op; 2405 } 2406 2407 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2408 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2409 Op->IFlags.Val = IFlags; 2410 Op->StartLoc = S; 2411 Op->EndLoc = S; 2412 return Op; 2413 } 2414 2415 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2416 ARMOperand *Op = new ARMOperand(k_MSRMask); 2417 Op->MMask.Val = MMask; 2418 Op->StartLoc = S; 2419 Op->EndLoc = S; 2420 return Op; 2421 } 2422 }; 2423 2424 } // end anonymous namespace. 2425 2426 void ARMOperand::print(raw_ostream &OS) const { 2427 switch (Kind) { 2428 case k_CondCode: 2429 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2430 break; 2431 case k_CCOut: 2432 OS << "<ccout " << getReg() << ">"; 2433 break; 2434 case k_ITCondMask: { 2435 static const char *const MaskStr[] = { 2436 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2437 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2438 }; 2439 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2440 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2441 break; 2442 } 2443 case k_CoprocNum: 2444 OS << "<coprocessor number: " << getCoproc() << ">"; 2445 break; 2446 case k_CoprocReg: 2447 OS << "<coprocessor register: " << getCoproc() << ">"; 2448 break; 2449 case k_CoprocOption: 2450 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2451 break; 2452 case k_MSRMask: 2453 OS << "<mask: " << getMSRMask() << ">"; 2454 break; 2455 case k_Immediate: 2456 getImm()->print(OS); 2457 break; 2458 case k_MemBarrierOpt: 2459 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2460 break; 2461 case k_InstSyncBarrierOpt: 2462 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2463 break; 2464 case k_Memory: 2465 OS << "<memory " 2466 << " base:" << Memory.BaseRegNum; 2467 OS << ">"; 2468 break; 2469 case k_PostIndexRegister: 2470 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2471 << PostIdxReg.RegNum; 2472 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2473 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2474 << PostIdxReg.ShiftImm; 2475 OS << ">"; 2476 break; 2477 case k_ProcIFlags: { 2478 OS << "<ARM_PROC::"; 2479 unsigned IFlags = getProcIFlags(); 2480 for (int i=2; i >= 0; --i) 2481 if (IFlags & (1 << i)) 2482 OS << ARM_PROC::IFlagsToString(1 << i); 2483 OS << ">"; 2484 break; 2485 } 2486 case k_Register: 2487 OS << "<register " << getReg() << ">"; 2488 break; 2489 case k_ShifterImmediate: 2490 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2491 << " #" << ShifterImm.Imm << ">"; 2492 break; 2493 case k_ShiftedRegister: 2494 OS << "<so_reg_reg " 2495 << RegShiftedReg.SrcReg << " " 2496 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2497 << " " << RegShiftedReg.ShiftReg << ">"; 2498 break; 2499 case k_ShiftedImmediate: 2500 OS << "<so_reg_imm " 2501 << RegShiftedImm.SrcReg << " " 2502 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2503 << " #" << RegShiftedImm.ShiftImm << ">"; 2504 break; 2505 case k_RotateImmediate: 2506 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2507 break; 2508 case k_BitfieldDescriptor: 2509 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2510 << ", width: " << Bitfield.Width << ">"; 2511 break; 2512 case k_RegisterList: 2513 case k_DPRRegisterList: 2514 case k_SPRRegisterList: { 2515 OS << "<register_list "; 2516 2517 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2518 for (SmallVectorImpl<unsigned>::const_iterator 2519 I = RegList.begin(), E = RegList.end(); I != E; ) { 2520 OS << *I; 2521 if (++I < E) OS << ", "; 2522 } 2523 2524 OS << ">"; 2525 break; 2526 } 2527 case k_VectorList: 2528 OS << "<vector_list " << VectorList.Count << " * " 2529 << VectorList.RegNum << ">"; 2530 break; 2531 case k_VectorListAllLanes: 2532 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2533 << VectorList.RegNum << ">"; 2534 break; 2535 case k_VectorListIndexed: 2536 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2537 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2538 break; 2539 case k_Token: 2540 OS << "'" << getToken() << "'"; 2541 break; 2542 case k_VectorIndex: 2543 OS << "<vectorindex " << getVectorIndex() << ">"; 2544 break; 2545 } 2546 } 2547 2548 /// @name Auto-generated Match Functions 2549 /// { 2550 2551 static unsigned MatchRegisterName(StringRef Name); 2552 2553 /// } 2554 2555 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2556 SMLoc &StartLoc, SMLoc &EndLoc) { 2557 StartLoc = Parser.getTok().getLoc(); 2558 EndLoc = Parser.getTok().getEndLoc(); 2559 RegNo = tryParseRegister(); 2560 2561 return (RegNo == (unsigned)-1); 2562 } 2563 2564 /// Try to parse a register name. The token must be an Identifier when called, 2565 /// and if it is a register name the token is eaten and the register number is 2566 /// returned. Otherwise return -1. 2567 /// 2568 int ARMAsmParser::tryParseRegister() { 2569 const AsmToken &Tok = Parser.getTok(); 2570 if (Tok.isNot(AsmToken::Identifier)) return -1; 2571 2572 std::string lowerCase = Tok.getString().lower(); 2573 unsigned RegNum = MatchRegisterName(lowerCase); 2574 if (!RegNum) { 2575 RegNum = StringSwitch<unsigned>(lowerCase) 2576 .Case("r13", ARM::SP) 2577 .Case("r14", ARM::LR) 2578 .Case("r15", ARM::PC) 2579 .Case("ip", ARM::R12) 2580 // Additional register name aliases for 'gas' compatibility. 2581 .Case("a1", ARM::R0) 2582 .Case("a2", ARM::R1) 2583 .Case("a3", ARM::R2) 2584 .Case("a4", ARM::R3) 2585 .Case("v1", ARM::R4) 2586 .Case("v2", ARM::R5) 2587 .Case("v3", ARM::R6) 2588 .Case("v4", ARM::R7) 2589 .Case("v5", ARM::R8) 2590 .Case("v6", ARM::R9) 2591 .Case("v7", ARM::R10) 2592 .Case("v8", ARM::R11) 2593 .Case("sb", ARM::R9) 2594 .Case("sl", ARM::R10) 2595 .Case("fp", ARM::R11) 2596 .Default(0); 2597 } 2598 if (!RegNum) { 2599 // Check for aliases registered via .req. Canonicalize to lower case. 2600 // That's more consistent since register names are case insensitive, and 2601 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2602 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2603 // If no match, return failure. 2604 if (Entry == RegisterReqs.end()) 2605 return -1; 2606 Parser.Lex(); // Eat identifier token. 2607 return Entry->getValue(); 2608 } 2609 2610 Parser.Lex(); // Eat identifier token. 2611 2612 return RegNum; 2613 } 2614 2615 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2616 // If a recoverable error occurs, return 1. If an irrecoverable error 2617 // occurs, return -1. An irrecoverable error is one where tokens have been 2618 // consumed in the process of trying to parse the shifter (i.e., when it is 2619 // indeed a shifter operand, but malformed). 2620 int ARMAsmParser::tryParseShiftRegister( 2621 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2622 SMLoc S = Parser.getTok().getLoc(); 2623 const AsmToken &Tok = Parser.getTok(); 2624 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2625 2626 std::string lowerCase = Tok.getString().lower(); 2627 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2628 .Case("asl", ARM_AM::lsl) 2629 .Case("lsl", ARM_AM::lsl) 2630 .Case("lsr", ARM_AM::lsr) 2631 .Case("asr", ARM_AM::asr) 2632 .Case("ror", ARM_AM::ror) 2633 .Case("rrx", ARM_AM::rrx) 2634 .Default(ARM_AM::no_shift); 2635 2636 if (ShiftTy == ARM_AM::no_shift) 2637 return 1; 2638 2639 Parser.Lex(); // Eat the operator. 2640 2641 // The source register for the shift has already been added to the 2642 // operand list, so we need to pop it off and combine it into the shifted 2643 // register operand instead. 2644 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2645 if (!PrevOp->isReg()) 2646 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2647 int SrcReg = PrevOp->getReg(); 2648 2649 SMLoc EndLoc; 2650 int64_t Imm = 0; 2651 int ShiftReg = 0; 2652 if (ShiftTy == ARM_AM::rrx) { 2653 // RRX Doesn't have an explicit shift amount. The encoder expects 2654 // the shift register to be the same as the source register. Seems odd, 2655 // but OK. 2656 ShiftReg = SrcReg; 2657 } else { 2658 // Figure out if this is shifted by a constant or a register (for non-RRX). 2659 if (Parser.getTok().is(AsmToken::Hash) || 2660 Parser.getTok().is(AsmToken::Dollar)) { 2661 Parser.Lex(); // Eat hash. 2662 SMLoc ImmLoc = Parser.getTok().getLoc(); 2663 const MCExpr *ShiftExpr = 0; 2664 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 2665 Error(ImmLoc, "invalid immediate shift value"); 2666 return -1; 2667 } 2668 // The expression must be evaluatable as an immediate. 2669 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2670 if (!CE) { 2671 Error(ImmLoc, "invalid immediate shift value"); 2672 return -1; 2673 } 2674 // Range check the immediate. 2675 // lsl, ror: 0 <= imm <= 31 2676 // lsr, asr: 0 <= imm <= 32 2677 Imm = CE->getValue(); 2678 if (Imm < 0 || 2679 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2680 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2681 Error(ImmLoc, "immediate shift value out of range"); 2682 return -1; 2683 } 2684 // shift by zero is a nop. Always send it through as lsl. 2685 // ('as' compatibility) 2686 if (Imm == 0) 2687 ShiftTy = ARM_AM::lsl; 2688 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2689 SMLoc L = Parser.getTok().getLoc(); 2690 EndLoc = Parser.getTok().getEndLoc(); 2691 ShiftReg = tryParseRegister(); 2692 if (ShiftReg == -1) { 2693 Error (L, "expected immediate or register in shift operand"); 2694 return -1; 2695 } 2696 } else { 2697 Error (Parser.getTok().getLoc(), 2698 "expected immediate or register in shift operand"); 2699 return -1; 2700 } 2701 } 2702 2703 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2704 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2705 ShiftReg, Imm, 2706 S, EndLoc)); 2707 else 2708 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2709 S, EndLoc)); 2710 2711 return 0; 2712 } 2713 2714 2715 /// Try to parse a register name. The token must be an Identifier when called. 2716 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 2717 /// if there is a "writeback". 'true' if it's not a register. 2718 /// 2719 /// TODO this is likely to change to allow different register types and or to 2720 /// parse for a specific register type. 2721 bool ARMAsmParser:: 2722 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2723 const AsmToken &RegTok = Parser.getTok(); 2724 int RegNo = tryParseRegister(); 2725 if (RegNo == -1) 2726 return true; 2727 2728 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 2729 RegTok.getEndLoc())); 2730 2731 const AsmToken &ExclaimTok = Parser.getTok(); 2732 if (ExclaimTok.is(AsmToken::Exclaim)) { 2733 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2734 ExclaimTok.getLoc())); 2735 Parser.Lex(); // Eat exclaim token 2736 return false; 2737 } 2738 2739 // Also check for an index operand. This is only legal for vector registers, 2740 // but that'll get caught OK in operand matching, so we don't need to 2741 // explicitly filter everything else out here. 2742 if (Parser.getTok().is(AsmToken::LBrac)) { 2743 SMLoc SIdx = Parser.getTok().getLoc(); 2744 Parser.Lex(); // Eat left bracket token. 2745 2746 const MCExpr *ImmVal; 2747 if (getParser().parseExpression(ImmVal)) 2748 return true; 2749 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2750 if (!MCE) 2751 return TokError("immediate value expected for vector index"); 2752 2753 if (Parser.getTok().isNot(AsmToken::RBrac)) 2754 return Error(Parser.getTok().getLoc(), "']' expected"); 2755 2756 SMLoc E = Parser.getTok().getEndLoc(); 2757 Parser.Lex(); // Eat right bracket token. 2758 2759 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2760 SIdx, E, 2761 getContext())); 2762 } 2763 2764 return false; 2765 } 2766 2767 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 2768 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2769 /// "c5", ... 2770 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2771 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2772 // but efficient. 2773 switch (Name.size()) { 2774 default: return -1; 2775 case 2: 2776 if (Name[0] != CoprocOp) 2777 return -1; 2778 switch (Name[1]) { 2779 default: return -1; 2780 case '0': return 0; 2781 case '1': return 1; 2782 case '2': return 2; 2783 case '3': return 3; 2784 case '4': return 4; 2785 case '5': return 5; 2786 case '6': return 6; 2787 case '7': return 7; 2788 case '8': return 8; 2789 case '9': return 9; 2790 } 2791 case 3: 2792 if (Name[0] != CoprocOp || Name[1] != '1') 2793 return -1; 2794 switch (Name[2]) { 2795 default: return -1; 2796 case '0': return 10; 2797 case '1': return 11; 2798 case '2': return 12; 2799 case '3': return 13; 2800 case '4': return 14; 2801 case '5': return 15; 2802 } 2803 } 2804 } 2805 2806 /// parseITCondCode - Try to parse a condition code for an IT instruction. 2807 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2808 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2809 SMLoc S = Parser.getTok().getLoc(); 2810 const AsmToken &Tok = Parser.getTok(); 2811 if (!Tok.is(AsmToken::Identifier)) 2812 return MatchOperand_NoMatch; 2813 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2814 .Case("eq", ARMCC::EQ) 2815 .Case("ne", ARMCC::NE) 2816 .Case("hs", ARMCC::HS) 2817 .Case("cs", ARMCC::HS) 2818 .Case("lo", ARMCC::LO) 2819 .Case("cc", ARMCC::LO) 2820 .Case("mi", ARMCC::MI) 2821 .Case("pl", ARMCC::PL) 2822 .Case("vs", ARMCC::VS) 2823 .Case("vc", ARMCC::VC) 2824 .Case("hi", ARMCC::HI) 2825 .Case("ls", ARMCC::LS) 2826 .Case("ge", ARMCC::GE) 2827 .Case("lt", ARMCC::LT) 2828 .Case("gt", ARMCC::GT) 2829 .Case("le", ARMCC::LE) 2830 .Case("al", ARMCC::AL) 2831 .Default(~0U); 2832 if (CC == ~0U) 2833 return MatchOperand_NoMatch; 2834 Parser.Lex(); // Eat the token. 2835 2836 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2837 2838 return MatchOperand_Success; 2839 } 2840 2841 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2842 /// token must be an Identifier when called, and if it is a coprocessor 2843 /// number, the token is eaten and the operand is added to the operand list. 2844 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2845 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2846 SMLoc S = Parser.getTok().getLoc(); 2847 const AsmToken &Tok = Parser.getTok(); 2848 if (Tok.isNot(AsmToken::Identifier)) 2849 return MatchOperand_NoMatch; 2850 2851 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2852 if (Num == -1) 2853 return MatchOperand_NoMatch; 2854 2855 Parser.Lex(); // Eat identifier token. 2856 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2857 return MatchOperand_Success; 2858 } 2859 2860 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2861 /// token must be an Identifier when called, and if it is a coprocessor 2862 /// number, the token is eaten and the operand is added to the operand list. 2863 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2864 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2865 SMLoc S = Parser.getTok().getLoc(); 2866 const AsmToken &Tok = Parser.getTok(); 2867 if (Tok.isNot(AsmToken::Identifier)) 2868 return MatchOperand_NoMatch; 2869 2870 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2871 if (Reg == -1) 2872 return MatchOperand_NoMatch; 2873 2874 Parser.Lex(); // Eat identifier token. 2875 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2876 return MatchOperand_Success; 2877 } 2878 2879 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2880 /// coproc_option : '{' imm0_255 '}' 2881 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2882 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2883 SMLoc S = Parser.getTok().getLoc(); 2884 2885 // If this isn't a '{', this isn't a coprocessor immediate operand. 2886 if (Parser.getTok().isNot(AsmToken::LCurly)) 2887 return MatchOperand_NoMatch; 2888 Parser.Lex(); // Eat the '{' 2889 2890 const MCExpr *Expr; 2891 SMLoc Loc = Parser.getTok().getLoc(); 2892 if (getParser().parseExpression(Expr)) { 2893 Error(Loc, "illegal expression"); 2894 return MatchOperand_ParseFail; 2895 } 2896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2897 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2898 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2899 return MatchOperand_ParseFail; 2900 } 2901 int Val = CE->getValue(); 2902 2903 // Check for and consume the closing '}' 2904 if (Parser.getTok().isNot(AsmToken::RCurly)) 2905 return MatchOperand_ParseFail; 2906 SMLoc E = Parser.getTok().getEndLoc(); 2907 Parser.Lex(); // Eat the '}' 2908 2909 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2910 return MatchOperand_Success; 2911 } 2912 2913 // For register list parsing, we need to map from raw GPR register numbering 2914 // to the enumeration values. The enumeration values aren't sorted by 2915 // register number due to our using "sp", "lr" and "pc" as canonical names. 2916 static unsigned getNextRegister(unsigned Reg) { 2917 // If this is a GPR, we need to do it manually, otherwise we can rely 2918 // on the sort ordering of the enumeration since the other reg-classes 2919 // are sane. 2920 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2921 return Reg + 1; 2922 switch(Reg) { 2923 default: llvm_unreachable("Invalid GPR number!"); 2924 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2925 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2926 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2927 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2928 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2929 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2930 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2931 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2932 } 2933 } 2934 2935 // Return the low-subreg of a given Q register. 2936 static unsigned getDRegFromQReg(unsigned QReg) { 2937 switch (QReg) { 2938 default: llvm_unreachable("expected a Q register!"); 2939 case ARM::Q0: return ARM::D0; 2940 case ARM::Q1: return ARM::D2; 2941 case ARM::Q2: return ARM::D4; 2942 case ARM::Q3: return ARM::D6; 2943 case ARM::Q4: return ARM::D8; 2944 case ARM::Q5: return ARM::D10; 2945 case ARM::Q6: return ARM::D12; 2946 case ARM::Q7: return ARM::D14; 2947 case ARM::Q8: return ARM::D16; 2948 case ARM::Q9: return ARM::D18; 2949 case ARM::Q10: return ARM::D20; 2950 case ARM::Q11: return ARM::D22; 2951 case ARM::Q12: return ARM::D24; 2952 case ARM::Q13: return ARM::D26; 2953 case ARM::Q14: return ARM::D28; 2954 case ARM::Q15: return ARM::D30; 2955 } 2956 } 2957 2958 /// Parse a register list. 2959 bool ARMAsmParser:: 2960 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2961 assert(Parser.getTok().is(AsmToken::LCurly) && 2962 "Token is not a Left Curly Brace"); 2963 SMLoc S = Parser.getTok().getLoc(); 2964 Parser.Lex(); // Eat '{' token. 2965 SMLoc RegLoc = Parser.getTok().getLoc(); 2966 2967 // Check the first register in the list to see what register class 2968 // this is a list of. 2969 int Reg = tryParseRegister(); 2970 if (Reg == -1) 2971 return Error(RegLoc, "register expected"); 2972 2973 // The reglist instructions have at most 16 registers, so reserve 2974 // space for that many. 2975 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2976 2977 // Allow Q regs and just interpret them as the two D sub-registers. 2978 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2979 Reg = getDRegFromQReg(Reg); 2980 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2981 ++Reg; 2982 } 2983 const MCRegisterClass *RC; 2984 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2985 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2986 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2987 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2988 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2989 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2990 else 2991 return Error(RegLoc, "invalid register in register list"); 2992 2993 // Store the register. 2994 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2995 2996 // This starts immediately after the first register token in the list, 2997 // so we can see either a comma or a minus (range separator) as a legal 2998 // next token. 2999 while (Parser.getTok().is(AsmToken::Comma) || 3000 Parser.getTok().is(AsmToken::Minus)) { 3001 if (Parser.getTok().is(AsmToken::Minus)) { 3002 Parser.Lex(); // Eat the minus. 3003 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3004 int EndReg = tryParseRegister(); 3005 if (EndReg == -1) 3006 return Error(AfterMinusLoc, "register expected"); 3007 // Allow Q regs and just interpret them as the two D sub-registers. 3008 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3009 EndReg = getDRegFromQReg(EndReg) + 1; 3010 // If the register is the same as the start reg, there's nothing 3011 // more to do. 3012 if (Reg == EndReg) 3013 continue; 3014 // The register must be in the same register class as the first. 3015 if (!RC->contains(EndReg)) 3016 return Error(AfterMinusLoc, "invalid register in register list"); 3017 // Ranges must go from low to high. 3018 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3019 return Error(AfterMinusLoc, "bad range in register list"); 3020 3021 // Add all the registers in the range to the register list. 3022 while (Reg != EndReg) { 3023 Reg = getNextRegister(Reg); 3024 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 3025 } 3026 continue; 3027 } 3028 Parser.Lex(); // Eat the comma. 3029 RegLoc = Parser.getTok().getLoc(); 3030 int OldReg = Reg; 3031 const AsmToken RegTok = Parser.getTok(); 3032 Reg = tryParseRegister(); 3033 if (Reg == -1) 3034 return Error(RegLoc, "register expected"); 3035 // Allow Q regs and just interpret them as the two D sub-registers. 3036 bool isQReg = false; 3037 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3038 Reg = getDRegFromQReg(Reg); 3039 isQReg = true; 3040 } 3041 // The register must be in the same register class as the first. 3042 if (!RC->contains(Reg)) 3043 return Error(RegLoc, "invalid register in register list"); 3044 // List must be monotonically increasing. 3045 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3046 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3047 Warning(RegLoc, "register list not in ascending order"); 3048 else 3049 return Error(RegLoc, "register list not in ascending order"); 3050 } 3051 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3052 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3053 ") in register list"); 3054 continue; 3055 } 3056 // VFP register lists must also be contiguous. 3057 // It's OK to use the enumeration values directly here rather, as the 3058 // VFP register classes have the enum sorted properly. 3059 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3060 Reg != OldReg + 1) 3061 return Error(RegLoc, "non-contiguous register range"); 3062 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 3063 if (isQReg) 3064 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 3065 } 3066 3067 if (Parser.getTok().isNot(AsmToken::RCurly)) 3068 return Error(Parser.getTok().getLoc(), "'}' expected"); 3069 SMLoc E = Parser.getTok().getEndLoc(); 3070 Parser.Lex(); // Eat '}' token. 3071 3072 // Push the register list operand. 3073 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3074 3075 // The ARM system instruction variants for LDM/STM have a '^' token here. 3076 if (Parser.getTok().is(AsmToken::Caret)) { 3077 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3078 Parser.Lex(); // Eat '^' token. 3079 } 3080 3081 return false; 3082 } 3083 3084 // Helper function to parse the lane index for vector lists. 3085 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3086 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3087 Index = 0; // Always return a defined index value. 3088 if (Parser.getTok().is(AsmToken::LBrac)) { 3089 Parser.Lex(); // Eat the '['. 3090 if (Parser.getTok().is(AsmToken::RBrac)) { 3091 // "Dn[]" is the 'all lanes' syntax. 3092 LaneKind = AllLanes; 3093 EndLoc = Parser.getTok().getEndLoc(); 3094 Parser.Lex(); // Eat the ']'. 3095 return MatchOperand_Success; 3096 } 3097 3098 // There's an optional '#' token here. Normally there wouldn't be, but 3099 // inline assemble puts one in, and it's friendly to accept that. 3100 if (Parser.getTok().is(AsmToken::Hash)) 3101 Parser.Lex(); // Eat '#' or '$'. 3102 3103 const MCExpr *LaneIndex; 3104 SMLoc Loc = Parser.getTok().getLoc(); 3105 if (getParser().parseExpression(LaneIndex)) { 3106 Error(Loc, "illegal expression"); 3107 return MatchOperand_ParseFail; 3108 } 3109 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3110 if (!CE) { 3111 Error(Loc, "lane index must be empty or an integer"); 3112 return MatchOperand_ParseFail; 3113 } 3114 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3115 Error(Parser.getTok().getLoc(), "']' expected"); 3116 return MatchOperand_ParseFail; 3117 } 3118 EndLoc = Parser.getTok().getEndLoc(); 3119 Parser.Lex(); // Eat the ']'. 3120 int64_t Val = CE->getValue(); 3121 3122 // FIXME: Make this range check context sensitive for .8, .16, .32. 3123 if (Val < 0 || Val > 7) { 3124 Error(Parser.getTok().getLoc(), "lane index out of range"); 3125 return MatchOperand_ParseFail; 3126 } 3127 Index = Val; 3128 LaneKind = IndexedLane; 3129 return MatchOperand_Success; 3130 } 3131 LaneKind = NoLanes; 3132 return MatchOperand_Success; 3133 } 3134 3135 // parse a vector register list 3136 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3137 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3138 VectorLaneTy LaneKind; 3139 unsigned LaneIndex; 3140 SMLoc S = Parser.getTok().getLoc(); 3141 // As an extension (to match gas), support a plain D register or Q register 3142 // (without encosing curly braces) as a single or double entry list, 3143 // respectively. 3144 if (Parser.getTok().is(AsmToken::Identifier)) { 3145 SMLoc E = Parser.getTok().getEndLoc(); 3146 int Reg = tryParseRegister(); 3147 if (Reg == -1) 3148 return MatchOperand_NoMatch; 3149 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3150 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3151 if (Res != MatchOperand_Success) 3152 return Res; 3153 switch (LaneKind) { 3154 case NoLanes: 3155 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3156 break; 3157 case AllLanes: 3158 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3159 S, E)); 3160 break; 3161 case IndexedLane: 3162 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3163 LaneIndex, 3164 false, S, E)); 3165 break; 3166 } 3167 return MatchOperand_Success; 3168 } 3169 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3170 Reg = getDRegFromQReg(Reg); 3171 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3172 if (Res != MatchOperand_Success) 3173 return Res; 3174 switch (LaneKind) { 3175 case NoLanes: 3176 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3177 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3178 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3179 break; 3180 case AllLanes: 3181 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3182 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3183 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3184 S, E)); 3185 break; 3186 case IndexedLane: 3187 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3188 LaneIndex, 3189 false, S, E)); 3190 break; 3191 } 3192 return MatchOperand_Success; 3193 } 3194 Error(S, "vector register expected"); 3195 return MatchOperand_ParseFail; 3196 } 3197 3198 if (Parser.getTok().isNot(AsmToken::LCurly)) 3199 return MatchOperand_NoMatch; 3200 3201 Parser.Lex(); // Eat '{' token. 3202 SMLoc RegLoc = Parser.getTok().getLoc(); 3203 3204 int Reg = tryParseRegister(); 3205 if (Reg == -1) { 3206 Error(RegLoc, "register expected"); 3207 return MatchOperand_ParseFail; 3208 } 3209 unsigned Count = 1; 3210 int Spacing = 0; 3211 unsigned FirstReg = Reg; 3212 // The list is of D registers, but we also allow Q regs and just interpret 3213 // them as the two D sub-registers. 3214 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3215 FirstReg = Reg = getDRegFromQReg(Reg); 3216 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3217 // it's ambiguous with four-register single spaced. 3218 ++Reg; 3219 ++Count; 3220 } 3221 3222 SMLoc E; 3223 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3224 return MatchOperand_ParseFail; 3225 3226 while (Parser.getTok().is(AsmToken::Comma) || 3227 Parser.getTok().is(AsmToken::Minus)) { 3228 if (Parser.getTok().is(AsmToken::Minus)) { 3229 if (!Spacing) 3230 Spacing = 1; // Register range implies a single spaced list. 3231 else if (Spacing == 2) { 3232 Error(Parser.getTok().getLoc(), 3233 "sequential registers in double spaced list"); 3234 return MatchOperand_ParseFail; 3235 } 3236 Parser.Lex(); // Eat the minus. 3237 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3238 int EndReg = tryParseRegister(); 3239 if (EndReg == -1) { 3240 Error(AfterMinusLoc, "register expected"); 3241 return MatchOperand_ParseFail; 3242 } 3243 // Allow Q regs and just interpret them as the two D sub-registers. 3244 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3245 EndReg = getDRegFromQReg(EndReg) + 1; 3246 // If the register is the same as the start reg, there's nothing 3247 // more to do. 3248 if (Reg == EndReg) 3249 continue; 3250 // The register must be in the same register class as the first. 3251 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3252 Error(AfterMinusLoc, "invalid register in register list"); 3253 return MatchOperand_ParseFail; 3254 } 3255 // Ranges must go from low to high. 3256 if (Reg > EndReg) { 3257 Error(AfterMinusLoc, "bad range in register list"); 3258 return MatchOperand_ParseFail; 3259 } 3260 // Parse the lane specifier if present. 3261 VectorLaneTy NextLaneKind; 3262 unsigned NextLaneIndex; 3263 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3264 MatchOperand_Success) 3265 return MatchOperand_ParseFail; 3266 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3267 Error(AfterMinusLoc, "mismatched lane index in register list"); 3268 return MatchOperand_ParseFail; 3269 } 3270 3271 // Add all the registers in the range to the register list. 3272 Count += EndReg - Reg; 3273 Reg = EndReg; 3274 continue; 3275 } 3276 Parser.Lex(); // Eat the comma. 3277 RegLoc = Parser.getTok().getLoc(); 3278 int OldReg = Reg; 3279 Reg = tryParseRegister(); 3280 if (Reg == -1) { 3281 Error(RegLoc, "register expected"); 3282 return MatchOperand_ParseFail; 3283 } 3284 // vector register lists must be contiguous. 3285 // It's OK to use the enumeration values directly here rather, as the 3286 // VFP register classes have the enum sorted properly. 3287 // 3288 // The list is of D registers, but we also allow Q regs and just interpret 3289 // them as the two D sub-registers. 3290 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3291 if (!Spacing) 3292 Spacing = 1; // Register range implies a single spaced list. 3293 else if (Spacing == 2) { 3294 Error(RegLoc, 3295 "invalid register in double-spaced list (must be 'D' register')"); 3296 return MatchOperand_ParseFail; 3297 } 3298 Reg = getDRegFromQReg(Reg); 3299 if (Reg != OldReg + 1) { 3300 Error(RegLoc, "non-contiguous register range"); 3301 return MatchOperand_ParseFail; 3302 } 3303 ++Reg; 3304 Count += 2; 3305 // Parse the lane specifier if present. 3306 VectorLaneTy NextLaneKind; 3307 unsigned NextLaneIndex; 3308 SMLoc LaneLoc = Parser.getTok().getLoc(); 3309 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3310 MatchOperand_Success) 3311 return MatchOperand_ParseFail; 3312 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3313 Error(LaneLoc, "mismatched lane index in register list"); 3314 return MatchOperand_ParseFail; 3315 } 3316 continue; 3317 } 3318 // Normal D register. 3319 // Figure out the register spacing (single or double) of the list if 3320 // we don't know it already. 3321 if (!Spacing) 3322 Spacing = 1 + (Reg == OldReg + 2); 3323 3324 // Just check that it's contiguous and keep going. 3325 if (Reg != OldReg + Spacing) { 3326 Error(RegLoc, "non-contiguous register range"); 3327 return MatchOperand_ParseFail; 3328 } 3329 ++Count; 3330 // Parse the lane specifier if present. 3331 VectorLaneTy NextLaneKind; 3332 unsigned NextLaneIndex; 3333 SMLoc EndLoc = Parser.getTok().getLoc(); 3334 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3335 return MatchOperand_ParseFail; 3336 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3337 Error(EndLoc, "mismatched lane index in register list"); 3338 return MatchOperand_ParseFail; 3339 } 3340 } 3341 3342 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3343 Error(Parser.getTok().getLoc(), "'}' expected"); 3344 return MatchOperand_ParseFail; 3345 } 3346 E = Parser.getTok().getEndLoc(); 3347 Parser.Lex(); // Eat '}' token. 3348 3349 switch (LaneKind) { 3350 case NoLanes: 3351 // Two-register operands have been converted to the 3352 // composite register classes. 3353 if (Count == 2) { 3354 const MCRegisterClass *RC = (Spacing == 1) ? 3355 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3356 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3357 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3358 } 3359 3360 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3361 (Spacing == 2), S, E)); 3362 break; 3363 case AllLanes: 3364 // Two-register operands have been converted to the 3365 // composite register classes. 3366 if (Count == 2) { 3367 const MCRegisterClass *RC = (Spacing == 1) ? 3368 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3369 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3370 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3371 } 3372 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3373 (Spacing == 2), 3374 S, E)); 3375 break; 3376 case IndexedLane: 3377 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3378 LaneIndex, 3379 (Spacing == 2), 3380 S, E)); 3381 break; 3382 } 3383 return MatchOperand_Success; 3384 } 3385 3386 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3387 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3388 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3389 SMLoc S = Parser.getTok().getLoc(); 3390 const AsmToken &Tok = Parser.getTok(); 3391 unsigned Opt; 3392 3393 if (Tok.is(AsmToken::Identifier)) { 3394 StringRef OptStr = Tok.getString(); 3395 3396 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3397 .Case("sy", ARM_MB::SY) 3398 .Case("st", ARM_MB::ST) 3399 .Case("sh", ARM_MB::ISH) 3400 .Case("ish", ARM_MB::ISH) 3401 .Case("shst", ARM_MB::ISHST) 3402 .Case("ishst", ARM_MB::ISHST) 3403 .Case("nsh", ARM_MB::NSH) 3404 .Case("un", ARM_MB::NSH) 3405 .Case("nshst", ARM_MB::NSHST) 3406 .Case("unst", ARM_MB::NSHST) 3407 .Case("osh", ARM_MB::OSH) 3408 .Case("oshst", ARM_MB::OSHST) 3409 .Default(~0U); 3410 3411 if (Opt == ~0U) 3412 return MatchOperand_NoMatch; 3413 3414 Parser.Lex(); // Eat identifier token. 3415 } else if (Tok.is(AsmToken::Hash) || 3416 Tok.is(AsmToken::Dollar) || 3417 Tok.is(AsmToken::Integer)) { 3418 if (Parser.getTok().isNot(AsmToken::Integer)) 3419 Parser.Lex(); // Eat '#' or '$'. 3420 SMLoc Loc = Parser.getTok().getLoc(); 3421 3422 const MCExpr *MemBarrierID; 3423 if (getParser().parseExpression(MemBarrierID)) { 3424 Error(Loc, "illegal expression"); 3425 return MatchOperand_ParseFail; 3426 } 3427 3428 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3429 if (!CE) { 3430 Error(Loc, "constant expression expected"); 3431 return MatchOperand_ParseFail; 3432 } 3433 3434 int Val = CE->getValue(); 3435 if (Val & ~0xf) { 3436 Error(Loc, "immediate value out of range"); 3437 return MatchOperand_ParseFail; 3438 } 3439 3440 Opt = ARM_MB::RESERVED_0 + Val; 3441 } else 3442 return MatchOperand_ParseFail; 3443 3444 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3445 return MatchOperand_Success; 3446 } 3447 3448 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3449 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3450 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3451 SMLoc S = Parser.getTok().getLoc(); 3452 const AsmToken &Tok = Parser.getTok(); 3453 unsigned Opt; 3454 3455 if (Tok.is(AsmToken::Identifier)) { 3456 StringRef OptStr = Tok.getString(); 3457 3458 if (OptStr.lower() == "sy") 3459 Opt = ARM_ISB::SY; 3460 else 3461 return MatchOperand_NoMatch; 3462 3463 Parser.Lex(); // Eat identifier token. 3464 } else if (Tok.is(AsmToken::Hash) || 3465 Tok.is(AsmToken::Dollar) || 3466 Tok.is(AsmToken::Integer)) { 3467 if (Parser.getTok().isNot(AsmToken::Integer)) 3468 Parser.Lex(); // Eat '#' or '$'. 3469 SMLoc Loc = Parser.getTok().getLoc(); 3470 3471 const MCExpr *ISBarrierID; 3472 if (getParser().parseExpression(ISBarrierID)) { 3473 Error(Loc, "illegal expression"); 3474 return MatchOperand_ParseFail; 3475 } 3476 3477 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3478 if (!CE) { 3479 Error(Loc, "constant expression expected"); 3480 return MatchOperand_ParseFail; 3481 } 3482 3483 int Val = CE->getValue(); 3484 if (Val & ~0xf) { 3485 Error(Loc, "immediate value out of range"); 3486 return MatchOperand_ParseFail; 3487 } 3488 3489 Opt = ARM_ISB::RESERVED_0 + Val; 3490 } else 3491 return MatchOperand_ParseFail; 3492 3493 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3494 (ARM_ISB::InstSyncBOpt)Opt, S)); 3495 return MatchOperand_Success; 3496 } 3497 3498 3499 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3500 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3501 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3502 SMLoc S = Parser.getTok().getLoc(); 3503 const AsmToken &Tok = Parser.getTok(); 3504 if (!Tok.is(AsmToken::Identifier)) 3505 return MatchOperand_NoMatch; 3506 StringRef IFlagsStr = Tok.getString(); 3507 3508 // An iflags string of "none" is interpreted to mean that none of the AIF 3509 // bits are set. Not a terribly useful instruction, but a valid encoding. 3510 unsigned IFlags = 0; 3511 if (IFlagsStr != "none") { 3512 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3513 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3514 .Case("a", ARM_PROC::A) 3515 .Case("i", ARM_PROC::I) 3516 .Case("f", ARM_PROC::F) 3517 .Default(~0U); 3518 3519 // If some specific iflag is already set, it means that some letter is 3520 // present more than once, this is not acceptable. 3521 if (Flag == ~0U || (IFlags & Flag)) 3522 return MatchOperand_NoMatch; 3523 3524 IFlags |= Flag; 3525 } 3526 } 3527 3528 Parser.Lex(); // Eat identifier token. 3529 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3530 return MatchOperand_Success; 3531 } 3532 3533 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3534 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3535 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3536 SMLoc S = Parser.getTok().getLoc(); 3537 const AsmToken &Tok = Parser.getTok(); 3538 if (!Tok.is(AsmToken::Identifier)) 3539 return MatchOperand_NoMatch; 3540 StringRef Mask = Tok.getString(); 3541 3542 if (isMClass()) { 3543 // See ARMv6-M 10.1.1 3544 std::string Name = Mask.lower(); 3545 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3546 // Note: in the documentation: 3547 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3548 // for MSR APSR_nzcvq. 3549 // but we do make it an alias here. This is so to get the "mask encoding" 3550 // bits correct on MSR APSR writes. 3551 // 3552 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3553 // should really only be allowed when writing a special register. Note 3554 // they get dropped in the MRS instruction reading a special register as 3555 // the SYSm field is only 8 bits. 3556 // 3557 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3558 // includes the DSP extension but that is not checked. 3559 .Case("apsr", 0x800) 3560 .Case("apsr_nzcvq", 0x800) 3561 .Case("apsr_g", 0x400) 3562 .Case("apsr_nzcvqg", 0xc00) 3563 .Case("iapsr", 0x801) 3564 .Case("iapsr_nzcvq", 0x801) 3565 .Case("iapsr_g", 0x401) 3566 .Case("iapsr_nzcvqg", 0xc01) 3567 .Case("eapsr", 0x802) 3568 .Case("eapsr_nzcvq", 0x802) 3569 .Case("eapsr_g", 0x402) 3570 .Case("eapsr_nzcvqg", 0xc02) 3571 .Case("xpsr", 0x803) 3572 .Case("xpsr_nzcvq", 0x803) 3573 .Case("xpsr_g", 0x403) 3574 .Case("xpsr_nzcvqg", 0xc03) 3575 .Case("ipsr", 0x805) 3576 .Case("epsr", 0x806) 3577 .Case("iepsr", 0x807) 3578 .Case("msp", 0x808) 3579 .Case("psp", 0x809) 3580 .Case("primask", 0x810) 3581 .Case("basepri", 0x811) 3582 .Case("basepri_max", 0x812) 3583 .Case("faultmask", 0x813) 3584 .Case("control", 0x814) 3585 .Default(~0U); 3586 3587 if (FlagsVal == ~0U) 3588 return MatchOperand_NoMatch; 3589 3590 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3591 // basepri, basepri_max and faultmask only valid for V7m. 3592 return MatchOperand_NoMatch; 3593 3594 Parser.Lex(); // Eat identifier token. 3595 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3596 return MatchOperand_Success; 3597 } 3598 3599 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3600 size_t Start = 0, Next = Mask.find('_'); 3601 StringRef Flags = ""; 3602 std::string SpecReg = Mask.slice(Start, Next).lower(); 3603 if (Next != StringRef::npos) 3604 Flags = Mask.slice(Next+1, Mask.size()); 3605 3606 // FlagsVal contains the complete mask: 3607 // 3-0: Mask 3608 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3609 unsigned FlagsVal = 0; 3610 3611 if (SpecReg == "apsr") { 3612 FlagsVal = StringSwitch<unsigned>(Flags) 3613 .Case("nzcvq", 0x8) // same as CPSR_f 3614 .Case("g", 0x4) // same as CPSR_s 3615 .Case("nzcvqg", 0xc) // same as CPSR_fs 3616 .Default(~0U); 3617 3618 if (FlagsVal == ~0U) { 3619 if (!Flags.empty()) 3620 return MatchOperand_NoMatch; 3621 else 3622 FlagsVal = 8; // No flag 3623 } 3624 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3625 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3626 if (Flags == "all" || Flags == "") 3627 Flags = "fc"; 3628 for (int i = 0, e = Flags.size(); i != e; ++i) { 3629 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3630 .Case("c", 1) 3631 .Case("x", 2) 3632 .Case("s", 4) 3633 .Case("f", 8) 3634 .Default(~0U); 3635 3636 // If some specific flag is already set, it means that some letter is 3637 // present more than once, this is not acceptable. 3638 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3639 return MatchOperand_NoMatch; 3640 FlagsVal |= Flag; 3641 } 3642 } else // No match for special register. 3643 return MatchOperand_NoMatch; 3644 3645 // Special register without flags is NOT equivalent to "fc" flags. 3646 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3647 // two lines would enable gas compatibility at the expense of breaking 3648 // round-tripping. 3649 // 3650 // if (!FlagsVal) 3651 // FlagsVal = 0x9; 3652 3653 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3654 if (SpecReg == "spsr") 3655 FlagsVal |= 16; 3656 3657 Parser.Lex(); // Eat identifier token. 3658 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3659 return MatchOperand_Success; 3660 } 3661 3662 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3663 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3664 int Low, int High) { 3665 const AsmToken &Tok = Parser.getTok(); 3666 if (Tok.isNot(AsmToken::Identifier)) { 3667 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3668 return MatchOperand_ParseFail; 3669 } 3670 StringRef ShiftName = Tok.getString(); 3671 std::string LowerOp = Op.lower(); 3672 std::string UpperOp = Op.upper(); 3673 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3674 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3675 return MatchOperand_ParseFail; 3676 } 3677 Parser.Lex(); // Eat shift type token. 3678 3679 // There must be a '#' and a shift amount. 3680 if (Parser.getTok().isNot(AsmToken::Hash) && 3681 Parser.getTok().isNot(AsmToken::Dollar)) { 3682 Error(Parser.getTok().getLoc(), "'#' expected"); 3683 return MatchOperand_ParseFail; 3684 } 3685 Parser.Lex(); // Eat hash token. 3686 3687 const MCExpr *ShiftAmount; 3688 SMLoc Loc = Parser.getTok().getLoc(); 3689 SMLoc EndLoc; 3690 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3691 Error(Loc, "illegal expression"); 3692 return MatchOperand_ParseFail; 3693 } 3694 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3695 if (!CE) { 3696 Error(Loc, "constant expression expected"); 3697 return MatchOperand_ParseFail; 3698 } 3699 int Val = CE->getValue(); 3700 if (Val < Low || Val > High) { 3701 Error(Loc, "immediate value out of range"); 3702 return MatchOperand_ParseFail; 3703 } 3704 3705 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 3706 3707 return MatchOperand_Success; 3708 } 3709 3710 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3711 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3712 const AsmToken &Tok = Parser.getTok(); 3713 SMLoc S = Tok.getLoc(); 3714 if (Tok.isNot(AsmToken::Identifier)) { 3715 Error(S, "'be' or 'le' operand expected"); 3716 return MatchOperand_ParseFail; 3717 } 3718 int Val = StringSwitch<int>(Tok.getString().lower()) 3719 .Case("be", 1) 3720 .Case("le", 0) 3721 .Default(-1); 3722 Parser.Lex(); // Eat the token. 3723 3724 if (Val == -1) { 3725 Error(S, "'be' or 'le' operand expected"); 3726 return MatchOperand_ParseFail; 3727 } 3728 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3729 getContext()), 3730 S, Tok.getEndLoc())); 3731 return MatchOperand_Success; 3732 } 3733 3734 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3735 /// instructions. Legal values are: 3736 /// lsl #n 'n' in [0,31] 3737 /// asr #n 'n' in [1,32] 3738 /// n == 32 encoded as n == 0. 3739 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3740 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3741 const AsmToken &Tok = Parser.getTok(); 3742 SMLoc S = Tok.getLoc(); 3743 if (Tok.isNot(AsmToken::Identifier)) { 3744 Error(S, "shift operator 'asr' or 'lsl' expected"); 3745 return MatchOperand_ParseFail; 3746 } 3747 StringRef ShiftName = Tok.getString(); 3748 bool isASR; 3749 if (ShiftName == "lsl" || ShiftName == "LSL") 3750 isASR = false; 3751 else if (ShiftName == "asr" || ShiftName == "ASR") 3752 isASR = true; 3753 else { 3754 Error(S, "shift operator 'asr' or 'lsl' expected"); 3755 return MatchOperand_ParseFail; 3756 } 3757 Parser.Lex(); // Eat the operator. 3758 3759 // A '#' and a shift amount. 3760 if (Parser.getTok().isNot(AsmToken::Hash) && 3761 Parser.getTok().isNot(AsmToken::Dollar)) { 3762 Error(Parser.getTok().getLoc(), "'#' expected"); 3763 return MatchOperand_ParseFail; 3764 } 3765 Parser.Lex(); // Eat hash token. 3766 SMLoc ExLoc = Parser.getTok().getLoc(); 3767 3768 const MCExpr *ShiftAmount; 3769 SMLoc EndLoc; 3770 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3771 Error(ExLoc, "malformed shift expression"); 3772 return MatchOperand_ParseFail; 3773 } 3774 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3775 if (!CE) { 3776 Error(ExLoc, "shift amount must be an immediate"); 3777 return MatchOperand_ParseFail; 3778 } 3779 3780 int64_t Val = CE->getValue(); 3781 if (isASR) { 3782 // Shift amount must be in [1,32] 3783 if (Val < 1 || Val > 32) { 3784 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 3785 return MatchOperand_ParseFail; 3786 } 3787 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3788 if (isThumb() && Val == 32) { 3789 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 3790 return MatchOperand_ParseFail; 3791 } 3792 if (Val == 32) Val = 0; 3793 } else { 3794 // Shift amount must be in [1,32] 3795 if (Val < 0 || Val > 31) { 3796 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 3797 return MatchOperand_ParseFail; 3798 } 3799 } 3800 3801 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 3802 3803 return MatchOperand_Success; 3804 } 3805 3806 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3807 /// of instructions. Legal values are: 3808 /// ror #n 'n' in {0, 8, 16, 24} 3809 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3810 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3811 const AsmToken &Tok = Parser.getTok(); 3812 SMLoc S = Tok.getLoc(); 3813 if (Tok.isNot(AsmToken::Identifier)) 3814 return MatchOperand_NoMatch; 3815 StringRef ShiftName = Tok.getString(); 3816 if (ShiftName != "ror" && ShiftName != "ROR") 3817 return MatchOperand_NoMatch; 3818 Parser.Lex(); // Eat the operator. 3819 3820 // A '#' and a rotate amount. 3821 if (Parser.getTok().isNot(AsmToken::Hash) && 3822 Parser.getTok().isNot(AsmToken::Dollar)) { 3823 Error(Parser.getTok().getLoc(), "'#' expected"); 3824 return MatchOperand_ParseFail; 3825 } 3826 Parser.Lex(); // Eat hash token. 3827 SMLoc ExLoc = Parser.getTok().getLoc(); 3828 3829 const MCExpr *ShiftAmount; 3830 SMLoc EndLoc; 3831 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 3832 Error(ExLoc, "malformed rotate expression"); 3833 return MatchOperand_ParseFail; 3834 } 3835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3836 if (!CE) { 3837 Error(ExLoc, "rotate amount must be an immediate"); 3838 return MatchOperand_ParseFail; 3839 } 3840 3841 int64_t Val = CE->getValue(); 3842 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 3843 // normally, zero is represented in asm by omitting the rotate operand 3844 // entirely. 3845 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 3846 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 3847 return MatchOperand_ParseFail; 3848 } 3849 3850 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 3851 3852 return MatchOperand_Success; 3853 } 3854 3855 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3856 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3857 SMLoc S = Parser.getTok().getLoc(); 3858 // The bitfield descriptor is really two operands, the LSB and the width. 3859 if (Parser.getTok().isNot(AsmToken::Hash) && 3860 Parser.getTok().isNot(AsmToken::Dollar)) { 3861 Error(Parser.getTok().getLoc(), "'#' expected"); 3862 return MatchOperand_ParseFail; 3863 } 3864 Parser.Lex(); // Eat hash token. 3865 3866 const MCExpr *LSBExpr; 3867 SMLoc E = Parser.getTok().getLoc(); 3868 if (getParser().parseExpression(LSBExpr)) { 3869 Error(E, "malformed immediate expression"); 3870 return MatchOperand_ParseFail; 3871 } 3872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3873 if (!CE) { 3874 Error(E, "'lsb' operand must be an immediate"); 3875 return MatchOperand_ParseFail; 3876 } 3877 3878 int64_t LSB = CE->getValue(); 3879 // The LSB must be in the range [0,31] 3880 if (LSB < 0 || LSB > 31) { 3881 Error(E, "'lsb' operand must be in the range [0,31]"); 3882 return MatchOperand_ParseFail; 3883 } 3884 E = Parser.getTok().getLoc(); 3885 3886 // Expect another immediate operand. 3887 if (Parser.getTok().isNot(AsmToken::Comma)) { 3888 Error(Parser.getTok().getLoc(), "too few operands"); 3889 return MatchOperand_ParseFail; 3890 } 3891 Parser.Lex(); // Eat hash token. 3892 if (Parser.getTok().isNot(AsmToken::Hash) && 3893 Parser.getTok().isNot(AsmToken::Dollar)) { 3894 Error(Parser.getTok().getLoc(), "'#' expected"); 3895 return MatchOperand_ParseFail; 3896 } 3897 Parser.Lex(); // Eat hash token. 3898 3899 const MCExpr *WidthExpr; 3900 SMLoc EndLoc; 3901 if (getParser().parseExpression(WidthExpr, EndLoc)) { 3902 Error(E, "malformed immediate expression"); 3903 return MatchOperand_ParseFail; 3904 } 3905 CE = dyn_cast<MCConstantExpr>(WidthExpr); 3906 if (!CE) { 3907 Error(E, "'width' operand must be an immediate"); 3908 return MatchOperand_ParseFail; 3909 } 3910 3911 int64_t Width = CE->getValue(); 3912 // The LSB must be in the range [1,32-lsb] 3913 if (Width < 1 || Width > 32 - LSB) { 3914 Error(E, "'width' operand must be in the range [1,32-lsb]"); 3915 return MatchOperand_ParseFail; 3916 } 3917 3918 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 3919 3920 return MatchOperand_Success; 3921 } 3922 3923 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3924 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3925 // Check for a post-index addressing register operand. Specifically: 3926 // postidx_reg := '+' register {, shift} 3927 // | '-' register {, shift} 3928 // | register {, shift} 3929 3930 // This method must return MatchOperand_NoMatch without consuming any tokens 3931 // in the case where there is no match, as other alternatives take other 3932 // parse methods. 3933 AsmToken Tok = Parser.getTok(); 3934 SMLoc S = Tok.getLoc(); 3935 bool haveEaten = false; 3936 bool isAdd = true; 3937 if (Tok.is(AsmToken::Plus)) { 3938 Parser.Lex(); // Eat the '+' token. 3939 haveEaten = true; 3940 } else if (Tok.is(AsmToken::Minus)) { 3941 Parser.Lex(); // Eat the '-' token. 3942 isAdd = false; 3943 haveEaten = true; 3944 } 3945 3946 SMLoc E = Parser.getTok().getEndLoc(); 3947 int Reg = tryParseRegister(); 3948 if (Reg == -1) { 3949 if (!haveEaten) 3950 return MatchOperand_NoMatch; 3951 Error(Parser.getTok().getLoc(), "register expected"); 3952 return MatchOperand_ParseFail; 3953 } 3954 3955 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3956 unsigned ShiftImm = 0; 3957 if (Parser.getTok().is(AsmToken::Comma)) { 3958 Parser.Lex(); // Eat the ','. 3959 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 3960 return MatchOperand_ParseFail; 3961 3962 // FIXME: Only approximates end...may include intervening whitespace. 3963 E = Parser.getTok().getLoc(); 3964 } 3965 3966 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3967 ShiftImm, S, E)); 3968 3969 return MatchOperand_Success; 3970 } 3971 3972 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3973 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3974 // Check for a post-index addressing register operand. Specifically: 3975 // am3offset := '+' register 3976 // | '-' register 3977 // | register 3978 // | # imm 3979 // | # + imm 3980 // | # - imm 3981 3982 // This method must return MatchOperand_NoMatch without consuming any tokens 3983 // in the case where there is no match, as other alternatives take other 3984 // parse methods. 3985 AsmToken Tok = Parser.getTok(); 3986 SMLoc S = Tok.getLoc(); 3987 3988 // Do immediates first, as we always parse those if we have a '#'. 3989 if (Parser.getTok().is(AsmToken::Hash) || 3990 Parser.getTok().is(AsmToken::Dollar)) { 3991 Parser.Lex(); // Eat '#' or '$'. 3992 // Explicitly look for a '-', as we need to encode negative zero 3993 // differently. 3994 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3995 const MCExpr *Offset; 3996 SMLoc E; 3997 if (getParser().parseExpression(Offset, E)) 3998 return MatchOperand_ParseFail; 3999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4000 if (!CE) { 4001 Error(S, "constant expression expected"); 4002 return MatchOperand_ParseFail; 4003 } 4004 // Negative zero is encoded as the flag value INT32_MIN. 4005 int32_t Val = CE->getValue(); 4006 if (isNegative && Val == 0) 4007 Val = INT32_MIN; 4008 4009 Operands.push_back( 4010 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 4011 4012 return MatchOperand_Success; 4013 } 4014 4015 4016 bool haveEaten = false; 4017 bool isAdd = true; 4018 if (Tok.is(AsmToken::Plus)) { 4019 Parser.Lex(); // Eat the '+' token. 4020 haveEaten = true; 4021 } else if (Tok.is(AsmToken::Minus)) { 4022 Parser.Lex(); // Eat the '-' token. 4023 isAdd = false; 4024 haveEaten = true; 4025 } 4026 4027 Tok = Parser.getTok(); 4028 int Reg = tryParseRegister(); 4029 if (Reg == -1) { 4030 if (!haveEaten) 4031 return MatchOperand_NoMatch; 4032 Error(Tok.getLoc(), "register expected"); 4033 return MatchOperand_ParseFail; 4034 } 4035 4036 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 4037 0, S, Tok.getEndLoc())); 4038 4039 return MatchOperand_Success; 4040 } 4041 4042 /// cvtT2LdrdPre - Convert parsed operands to MCInst. 4043 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4044 /// when they refer multiple MIOperands inside a single one. 4045 void ARMAsmParser:: 4046 cvtT2LdrdPre(MCInst &Inst, 4047 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4048 // Rt, Rt2 4049 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4050 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4051 // Create a writeback register dummy placeholder. 4052 Inst.addOperand(MCOperand::CreateReg(0)); 4053 // addr 4054 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 4055 // pred 4056 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4057 } 4058 4059 /// cvtT2StrdPre - Convert parsed operands to MCInst. 4060 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4061 /// when they refer multiple MIOperands inside a single one. 4062 void ARMAsmParser:: 4063 cvtT2StrdPre(MCInst &Inst, 4064 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4065 // Create a writeback register dummy placeholder. 4066 Inst.addOperand(MCOperand::CreateReg(0)); 4067 // Rt, Rt2 4068 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4069 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4070 // addr 4071 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 4072 // pred 4073 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4074 } 4075 4076 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 4077 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4078 /// when they refer multiple MIOperands inside a single one. 4079 void ARMAsmParser:: 4080 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 4081 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4082 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4083 4084 // Create a writeback register dummy placeholder. 4085 Inst.addOperand(MCOperand::CreateImm(0)); 4086 4087 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 4088 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4089 } 4090 4091 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 4092 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4093 /// when they refer multiple MIOperands inside a single one. 4094 void ARMAsmParser:: 4095 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 4096 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4097 // Create a writeback register dummy placeholder. 4098 Inst.addOperand(MCOperand::CreateImm(0)); 4099 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4100 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 4101 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4102 } 4103 4104 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 4105 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4106 /// when they refer multiple MIOperands inside a single one. 4107 void ARMAsmParser:: 4108 cvtLdWriteBackRegAddrMode2(MCInst &Inst, 4109 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4110 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4111 4112 // Create a writeback register dummy placeholder. 4113 Inst.addOperand(MCOperand::CreateImm(0)); 4114 4115 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 4116 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4117 } 4118 4119 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 4120 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4121 /// when they refer multiple MIOperands inside a single one. 4122 void ARMAsmParser:: 4123 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 4124 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4125 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4126 4127 // Create a writeback register dummy placeholder. 4128 Inst.addOperand(MCOperand::CreateImm(0)); 4129 4130 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 4131 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4132 } 4133 4134 4135 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 4136 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4137 /// when they refer multiple MIOperands inside a single one. 4138 void ARMAsmParser:: 4139 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 4140 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4141 // Create a writeback register dummy placeholder. 4142 Inst.addOperand(MCOperand::CreateImm(0)); 4143 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4144 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 4145 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4146 } 4147 4148 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 4149 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4150 /// when they refer multiple MIOperands inside a single one. 4151 void ARMAsmParser:: 4152 cvtStWriteBackRegAddrMode2(MCInst &Inst, 4153 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4154 // Create a writeback register dummy placeholder. 4155 Inst.addOperand(MCOperand::CreateImm(0)); 4156 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4157 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 4158 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4159 } 4160 4161 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4162 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4163 /// when they refer multiple MIOperands inside a single one. 4164 void ARMAsmParser:: 4165 cvtStWriteBackRegAddrMode3(MCInst &Inst, 4166 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4167 // Create a writeback register dummy placeholder. 4168 Inst.addOperand(MCOperand::CreateImm(0)); 4169 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4170 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4171 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4172 } 4173 4174 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 4175 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4176 /// when they refer multiple MIOperands inside a single one. 4177 void ARMAsmParser:: 4178 cvtLdExtTWriteBackImm(MCInst &Inst, 4179 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4180 // Rt 4181 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4182 // Create a writeback register dummy placeholder. 4183 Inst.addOperand(MCOperand::CreateImm(0)); 4184 // addr 4185 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4186 // offset 4187 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4188 // pred 4189 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4190 } 4191 4192 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 4193 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4194 /// when they refer multiple MIOperands inside a single one. 4195 void ARMAsmParser:: 4196 cvtLdExtTWriteBackReg(MCInst &Inst, 4197 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4198 // Rt 4199 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4200 // Create a writeback register dummy placeholder. 4201 Inst.addOperand(MCOperand::CreateImm(0)); 4202 // addr 4203 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4204 // offset 4205 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4206 // pred 4207 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4208 } 4209 4210 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 4211 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4212 /// when they refer multiple MIOperands inside a single one. 4213 void ARMAsmParser:: 4214 cvtStExtTWriteBackImm(MCInst &Inst, 4215 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4216 // Create a writeback register dummy placeholder. 4217 Inst.addOperand(MCOperand::CreateImm(0)); 4218 // Rt 4219 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4220 // addr 4221 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4222 // offset 4223 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4224 // pred 4225 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4226 } 4227 4228 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 4229 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4230 /// when they refer multiple MIOperands inside a single one. 4231 void ARMAsmParser:: 4232 cvtStExtTWriteBackReg(MCInst &Inst, 4233 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4234 // Create a writeback register dummy placeholder. 4235 Inst.addOperand(MCOperand::CreateImm(0)); 4236 // Rt 4237 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4238 // addr 4239 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4240 // offset 4241 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4242 // pred 4243 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4244 } 4245 4246 /// cvtLdrdPre - Convert parsed operands to MCInst. 4247 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4248 /// when they refer multiple MIOperands inside a single one. 4249 void ARMAsmParser:: 4250 cvtLdrdPre(MCInst &Inst, 4251 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4252 // Rt, Rt2 4253 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4254 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4255 // Create a writeback register dummy placeholder. 4256 Inst.addOperand(MCOperand::CreateImm(0)); 4257 // addr 4258 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4259 // pred 4260 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4261 } 4262 4263 /// cvtStrdPre - Convert parsed operands to MCInst. 4264 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4265 /// when they refer multiple MIOperands inside a single one. 4266 void ARMAsmParser:: 4267 cvtStrdPre(MCInst &Inst, 4268 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4269 // Create a writeback register dummy placeholder. 4270 Inst.addOperand(MCOperand::CreateImm(0)); 4271 // Rt, Rt2 4272 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4273 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4274 // addr 4275 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4276 // pred 4277 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4278 } 4279 4280 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4281 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4282 /// when they refer multiple MIOperands inside a single one. 4283 void ARMAsmParser:: 4284 cvtLdWriteBackRegAddrMode3(MCInst &Inst, 4285 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4286 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4287 // Create a writeback register dummy placeholder. 4288 Inst.addOperand(MCOperand::CreateImm(0)); 4289 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4290 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4291 } 4292 4293 /// cvtThumbMultiply - Convert parsed operands to MCInst. 4294 /// Needed here because the Asm Gen Matcher can't handle properly tied operands 4295 /// when they refer multiple MIOperands inside a single one. 4296 void ARMAsmParser:: 4297 cvtThumbMultiply(MCInst &Inst, 4298 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4299 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4300 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4301 // If we have a three-operand form, make sure to set Rn to be the operand 4302 // that isn't the same as Rd. 4303 unsigned RegOp = 4; 4304 if (Operands.size() == 6 && 4305 ((ARMOperand*)Operands[4])->getReg() == 4306 ((ARMOperand*)Operands[3])->getReg()) 4307 RegOp = 5; 4308 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4309 Inst.addOperand(Inst.getOperand(0)); 4310 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4311 } 4312 4313 void ARMAsmParser:: 4314 cvtVLDwbFixed(MCInst &Inst, 4315 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4316 // Vd 4317 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4318 // Create a writeback register dummy placeholder. 4319 Inst.addOperand(MCOperand::CreateImm(0)); 4320 // Vn 4321 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4322 // pred 4323 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4324 } 4325 4326 void ARMAsmParser:: 4327 cvtVLDwbRegister(MCInst &Inst, 4328 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4329 // Vd 4330 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4331 // Create a writeback register dummy placeholder. 4332 Inst.addOperand(MCOperand::CreateImm(0)); 4333 // Vn 4334 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4335 // Vm 4336 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4337 // pred 4338 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4339 } 4340 4341 void ARMAsmParser:: 4342 cvtVSTwbFixed(MCInst &Inst, 4343 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4344 // Create a writeback register dummy placeholder. 4345 Inst.addOperand(MCOperand::CreateImm(0)); 4346 // Vn 4347 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4348 // Vt 4349 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4350 // pred 4351 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4352 } 4353 4354 void ARMAsmParser:: 4355 cvtVSTwbRegister(MCInst &Inst, 4356 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4357 // Create a writeback register dummy placeholder. 4358 Inst.addOperand(MCOperand::CreateImm(0)); 4359 // Vn 4360 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4361 // Vm 4362 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4363 // Vt 4364 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4365 // pred 4366 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4367 } 4368 4369 /// Parse an ARM memory expression, return false if successful else return true 4370 /// or an error. The first token must be a '[' when called. 4371 bool ARMAsmParser:: 4372 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4373 SMLoc S, E; 4374 assert(Parser.getTok().is(AsmToken::LBrac) && 4375 "Token is not a Left Bracket"); 4376 S = Parser.getTok().getLoc(); 4377 Parser.Lex(); // Eat left bracket token. 4378 4379 const AsmToken &BaseRegTok = Parser.getTok(); 4380 int BaseRegNum = tryParseRegister(); 4381 if (BaseRegNum == -1) 4382 return Error(BaseRegTok.getLoc(), "register expected"); 4383 4384 // The next token must either be a comma, a colon or a closing bracket. 4385 const AsmToken &Tok = Parser.getTok(); 4386 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 4387 !Tok.is(AsmToken::RBrac)) 4388 return Error(Tok.getLoc(), "malformed memory operand"); 4389 4390 if (Tok.is(AsmToken::RBrac)) { 4391 E = Tok.getEndLoc(); 4392 Parser.Lex(); // Eat right bracket token. 4393 4394 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4395 0, 0, false, S, E)); 4396 4397 // If there's a pre-indexing writeback marker, '!', just add it as a token 4398 // operand. It's rather odd, but syntactically valid. 4399 if (Parser.getTok().is(AsmToken::Exclaim)) { 4400 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4401 Parser.Lex(); // Eat the '!'. 4402 } 4403 4404 return false; 4405 } 4406 4407 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 4408 "Lost colon or comma in memory operand?!"); 4409 if (Tok.is(AsmToken::Comma)) { 4410 Parser.Lex(); // Eat the comma. 4411 } 4412 4413 // If we have a ':', it's an alignment specifier. 4414 if (Parser.getTok().is(AsmToken::Colon)) { 4415 Parser.Lex(); // Eat the ':'. 4416 E = Parser.getTok().getLoc(); 4417 4418 const MCExpr *Expr; 4419 if (getParser().parseExpression(Expr)) 4420 return true; 4421 4422 // The expression has to be a constant. Memory references with relocations 4423 // don't come through here, as they use the <label> forms of the relevant 4424 // instructions. 4425 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4426 if (!CE) 4427 return Error (E, "constant expression expected"); 4428 4429 unsigned Align = 0; 4430 switch (CE->getValue()) { 4431 default: 4432 return Error(E, 4433 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4434 case 16: Align = 2; break; 4435 case 32: Align = 4; break; 4436 case 64: Align = 8; break; 4437 case 128: Align = 16; break; 4438 case 256: Align = 32; break; 4439 } 4440 4441 // Now we should have the closing ']' 4442 if (Parser.getTok().isNot(AsmToken::RBrac)) 4443 return Error(Parser.getTok().getLoc(), "']' expected"); 4444 E = Parser.getTok().getEndLoc(); 4445 Parser.Lex(); // Eat right bracket token. 4446 4447 // Don't worry about range checking the value here. That's handled by 4448 // the is*() predicates. 4449 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4450 ARM_AM::no_shift, 0, Align, 4451 false, S, E)); 4452 4453 // If there's a pre-indexing writeback marker, '!', just add it as a token 4454 // operand. 4455 if (Parser.getTok().is(AsmToken::Exclaim)) { 4456 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4457 Parser.Lex(); // Eat the '!'. 4458 } 4459 4460 return false; 4461 } 4462 4463 // If we have a '#', it's an immediate offset, else assume it's a register 4464 // offset. Be friendly and also accept a plain integer (without a leading 4465 // hash) for gas compatibility. 4466 if (Parser.getTok().is(AsmToken::Hash) || 4467 Parser.getTok().is(AsmToken::Dollar) || 4468 Parser.getTok().is(AsmToken::Integer)) { 4469 if (Parser.getTok().isNot(AsmToken::Integer)) 4470 Parser.Lex(); // Eat '#' or '$'. 4471 E = Parser.getTok().getLoc(); 4472 4473 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4474 const MCExpr *Offset; 4475 if (getParser().parseExpression(Offset)) 4476 return true; 4477 4478 // The expression has to be a constant. Memory references with relocations 4479 // don't come through here, as they use the <label> forms of the relevant 4480 // instructions. 4481 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4482 if (!CE) 4483 return Error (E, "constant expression expected"); 4484 4485 // If the constant was #-0, represent it as INT32_MIN. 4486 int32_t Val = CE->getValue(); 4487 if (isNegative && Val == 0) 4488 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4489 4490 // Now we should have the closing ']' 4491 if (Parser.getTok().isNot(AsmToken::RBrac)) 4492 return Error(Parser.getTok().getLoc(), "']' expected"); 4493 E = Parser.getTok().getEndLoc(); 4494 Parser.Lex(); // Eat right bracket token. 4495 4496 // Don't worry about range checking the value here. That's handled by 4497 // the is*() predicates. 4498 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4499 ARM_AM::no_shift, 0, 0, 4500 false, S, E)); 4501 4502 // If there's a pre-indexing writeback marker, '!', just add it as a token 4503 // operand. 4504 if (Parser.getTok().is(AsmToken::Exclaim)) { 4505 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4506 Parser.Lex(); // Eat the '!'. 4507 } 4508 4509 return false; 4510 } 4511 4512 // The register offset is optionally preceded by a '+' or '-' 4513 bool isNegative = false; 4514 if (Parser.getTok().is(AsmToken::Minus)) { 4515 isNegative = true; 4516 Parser.Lex(); // Eat the '-'. 4517 } else if (Parser.getTok().is(AsmToken::Plus)) { 4518 // Nothing to do. 4519 Parser.Lex(); // Eat the '+'. 4520 } 4521 4522 E = Parser.getTok().getLoc(); 4523 int OffsetRegNum = tryParseRegister(); 4524 if (OffsetRegNum == -1) 4525 return Error(E, "register expected"); 4526 4527 // If there's a shift operator, handle it. 4528 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4529 unsigned ShiftImm = 0; 4530 if (Parser.getTok().is(AsmToken::Comma)) { 4531 Parser.Lex(); // Eat the ','. 4532 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4533 return true; 4534 } 4535 4536 // Now we should have the closing ']' 4537 if (Parser.getTok().isNot(AsmToken::RBrac)) 4538 return Error(Parser.getTok().getLoc(), "']' expected"); 4539 E = Parser.getTok().getEndLoc(); 4540 Parser.Lex(); // Eat right bracket token. 4541 4542 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4543 ShiftType, ShiftImm, 0, isNegative, 4544 S, E)); 4545 4546 // If there's a pre-indexing writeback marker, '!', just add it as a token 4547 // operand. 4548 if (Parser.getTok().is(AsmToken::Exclaim)) { 4549 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4550 Parser.Lex(); // Eat the '!'. 4551 } 4552 4553 return false; 4554 } 4555 4556 /// parseMemRegOffsetShift - one of these two: 4557 /// ( lsl | lsr | asr | ror ) , # shift_amount 4558 /// rrx 4559 /// return true if it parses a shift otherwise it returns false. 4560 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4561 unsigned &Amount) { 4562 SMLoc Loc = Parser.getTok().getLoc(); 4563 const AsmToken &Tok = Parser.getTok(); 4564 if (Tok.isNot(AsmToken::Identifier)) 4565 return true; 4566 StringRef ShiftName = Tok.getString(); 4567 if (ShiftName == "lsl" || ShiftName == "LSL" || 4568 ShiftName == "asl" || ShiftName == "ASL") 4569 St = ARM_AM::lsl; 4570 else if (ShiftName == "lsr" || ShiftName == "LSR") 4571 St = ARM_AM::lsr; 4572 else if (ShiftName == "asr" || ShiftName == "ASR") 4573 St = ARM_AM::asr; 4574 else if (ShiftName == "ror" || ShiftName == "ROR") 4575 St = ARM_AM::ror; 4576 else if (ShiftName == "rrx" || ShiftName == "RRX") 4577 St = ARM_AM::rrx; 4578 else 4579 return Error(Loc, "illegal shift operator"); 4580 Parser.Lex(); // Eat shift type token. 4581 4582 // rrx stands alone. 4583 Amount = 0; 4584 if (St != ARM_AM::rrx) { 4585 Loc = Parser.getTok().getLoc(); 4586 // A '#' and a shift amount. 4587 const AsmToken &HashTok = Parser.getTok(); 4588 if (HashTok.isNot(AsmToken::Hash) && 4589 HashTok.isNot(AsmToken::Dollar)) 4590 return Error(HashTok.getLoc(), "'#' expected"); 4591 Parser.Lex(); // Eat hash token. 4592 4593 const MCExpr *Expr; 4594 if (getParser().parseExpression(Expr)) 4595 return true; 4596 // Range check the immediate. 4597 // lsl, ror: 0 <= imm <= 31 4598 // lsr, asr: 0 <= imm <= 32 4599 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4600 if (!CE) 4601 return Error(Loc, "shift amount must be an immediate"); 4602 int64_t Imm = CE->getValue(); 4603 if (Imm < 0 || 4604 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4605 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4606 return Error(Loc, "immediate shift value out of range"); 4607 // If <ShiftTy> #0, turn it into a no_shift. 4608 if (Imm == 0) 4609 St = ARM_AM::lsl; 4610 // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 4611 if (Imm == 32) 4612 Imm = 0; 4613 Amount = Imm; 4614 } 4615 4616 return false; 4617 } 4618 4619 /// parseFPImm - A floating point immediate expression operand. 4620 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4621 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4622 // Anything that can accept a floating point constant as an operand 4623 // needs to go through here, as the regular parseExpression is 4624 // integer only. 4625 // 4626 // This routine still creates a generic Immediate operand, containing 4627 // a bitcast of the 64-bit floating point value. The various operands 4628 // that accept floats can check whether the value is valid for them 4629 // via the standard is*() predicates. 4630 4631 SMLoc S = Parser.getTok().getLoc(); 4632 4633 if (Parser.getTok().isNot(AsmToken::Hash) && 4634 Parser.getTok().isNot(AsmToken::Dollar)) 4635 return MatchOperand_NoMatch; 4636 4637 // Disambiguate the VMOV forms that can accept an FP immediate. 4638 // vmov.f32 <sreg>, #imm 4639 // vmov.f64 <dreg>, #imm 4640 // vmov.f32 <dreg>, #imm @ vector f32x2 4641 // vmov.f32 <qreg>, #imm @ vector f32x4 4642 // 4643 // There are also the NEON VMOV instructions which expect an 4644 // integer constant. Make sure we don't try to parse an FPImm 4645 // for these: 4646 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4647 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4648 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 4649 TyOp->getToken() != ".f64")) 4650 return MatchOperand_NoMatch; 4651 4652 Parser.Lex(); // Eat '#' or '$'. 4653 4654 // Handle negation, as that still comes through as a separate token. 4655 bool isNegative = false; 4656 if (Parser.getTok().is(AsmToken::Minus)) { 4657 isNegative = true; 4658 Parser.Lex(); 4659 } 4660 const AsmToken &Tok = Parser.getTok(); 4661 SMLoc Loc = Tok.getLoc(); 4662 if (Tok.is(AsmToken::Real)) { 4663 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4664 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4665 // If we had a '-' in front, toggle the sign bit. 4666 IntVal ^= (uint64_t)isNegative << 31; 4667 Parser.Lex(); // Eat the token. 4668 Operands.push_back(ARMOperand::CreateImm( 4669 MCConstantExpr::Create(IntVal, getContext()), 4670 S, Parser.getTok().getLoc())); 4671 return MatchOperand_Success; 4672 } 4673 // Also handle plain integers. Instructions which allow floating point 4674 // immediates also allow a raw encoded 8-bit value. 4675 if (Tok.is(AsmToken::Integer)) { 4676 int64_t Val = Tok.getIntVal(); 4677 Parser.Lex(); // Eat the token. 4678 if (Val > 255 || Val < 0) { 4679 Error(Loc, "encoded floating point value out of range"); 4680 return MatchOperand_ParseFail; 4681 } 4682 double RealVal = ARM_AM::getFPImmFloat(Val); 4683 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 4684 Operands.push_back(ARMOperand::CreateImm( 4685 MCConstantExpr::Create(Val, getContext()), S, 4686 Parser.getTok().getLoc())); 4687 return MatchOperand_Success; 4688 } 4689 4690 Error(Loc, "invalid floating point immediate"); 4691 return MatchOperand_ParseFail; 4692 } 4693 4694 /// Parse a arm instruction operand. For now this parses the operand regardless 4695 /// of the mnemonic. 4696 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4697 StringRef Mnemonic) { 4698 SMLoc S, E; 4699 4700 // Check if the current operand has a custom associated parser, if so, try to 4701 // custom parse the operand, or fallback to the general approach. 4702 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4703 if (ResTy == MatchOperand_Success) 4704 return false; 4705 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4706 // there was a match, but an error occurred, in which case, just return that 4707 // the operand parsing failed. 4708 if (ResTy == MatchOperand_ParseFail) 4709 return true; 4710 4711 switch (getLexer().getKind()) { 4712 default: 4713 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4714 return true; 4715 case AsmToken::Identifier: { 4716 // If we've seen a branch mnemonic, the next operand must be a label. This 4717 // is true even if the label is a register name. So "br r1" means branch to 4718 // label "r1". 4719 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 4720 if (!ExpectLabel) { 4721 if (!tryParseRegisterWithWriteBack(Operands)) 4722 return false; 4723 int Res = tryParseShiftRegister(Operands); 4724 if (Res == 0) // success 4725 return false; 4726 else if (Res == -1) // irrecoverable error 4727 return true; 4728 // If this is VMRS, check for the apsr_nzcv operand. 4729 if (Mnemonic == "vmrs" && 4730 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4731 S = Parser.getTok().getLoc(); 4732 Parser.Lex(); 4733 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4734 return false; 4735 } 4736 } 4737 4738 // Fall though for the Identifier case that is not a register or a 4739 // special name. 4740 } 4741 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4742 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4743 case AsmToken::String: // quoted label names. 4744 case AsmToken::Dot: { // . as a branch target 4745 // This was not a register so parse other operands that start with an 4746 // identifier (like labels) as expressions and create them as immediates. 4747 const MCExpr *IdVal; 4748 S = Parser.getTok().getLoc(); 4749 if (getParser().parseExpression(IdVal)) 4750 return true; 4751 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4752 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4753 return false; 4754 } 4755 case AsmToken::LBrac: 4756 return parseMemory(Operands); 4757 case AsmToken::LCurly: 4758 return parseRegisterList(Operands); 4759 case AsmToken::Dollar: 4760 case AsmToken::Hash: { 4761 // #42 -> immediate. 4762 S = Parser.getTok().getLoc(); 4763 Parser.Lex(); 4764 4765 if (Parser.getTok().isNot(AsmToken::Colon)) { 4766 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4767 const MCExpr *ImmVal; 4768 if (getParser().parseExpression(ImmVal)) 4769 return true; 4770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4771 if (CE) { 4772 int32_t Val = CE->getValue(); 4773 if (isNegative && Val == 0) 4774 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4775 } 4776 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4777 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4778 4779 // There can be a trailing '!' on operands that we want as a separate 4780 // '!' Token operand. Handle that here. For example, the compatibilty 4781 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 4782 if (Parser.getTok().is(AsmToken::Exclaim)) { 4783 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 4784 Parser.getTok().getLoc())); 4785 Parser.Lex(); // Eat exclaim token 4786 } 4787 return false; 4788 } 4789 // w/ a ':' after the '#', it's just like a plain ':'. 4790 // FALLTHROUGH 4791 } 4792 case AsmToken::Colon: { 4793 // ":lower16:" and ":upper16:" expression prefixes 4794 // FIXME: Check it's an expression prefix, 4795 // e.g. (FOO - :lower16:BAR) isn't legal. 4796 ARMMCExpr::VariantKind RefKind; 4797 if (parsePrefix(RefKind)) 4798 return true; 4799 4800 const MCExpr *SubExprVal; 4801 if (getParser().parseExpression(SubExprVal)) 4802 return true; 4803 4804 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4805 getContext()); 4806 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4807 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4808 return false; 4809 } 4810 } 4811 } 4812 4813 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4814 // :lower16: and :upper16:. 4815 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4816 RefKind = ARMMCExpr::VK_ARM_None; 4817 4818 // :lower16: and :upper16: modifiers 4819 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4820 Parser.Lex(); // Eat ':' 4821 4822 if (getLexer().isNot(AsmToken::Identifier)) { 4823 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4824 return true; 4825 } 4826 4827 StringRef IDVal = Parser.getTok().getIdentifier(); 4828 if (IDVal == "lower16") { 4829 RefKind = ARMMCExpr::VK_ARM_LO16; 4830 } else if (IDVal == "upper16") { 4831 RefKind = ARMMCExpr::VK_ARM_HI16; 4832 } else { 4833 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4834 return true; 4835 } 4836 Parser.Lex(); 4837 4838 if (getLexer().isNot(AsmToken::Colon)) { 4839 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4840 return true; 4841 } 4842 Parser.Lex(); // Eat the last ':' 4843 return false; 4844 } 4845 4846 /// \brief Given a mnemonic, split out possible predication code and carry 4847 /// setting letters to form a canonical mnemonic and flags. 4848 // 4849 // FIXME: Would be nice to autogen this. 4850 // FIXME: This is a bit of a maze of special cases. 4851 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4852 unsigned &PredicationCode, 4853 bool &CarrySetting, 4854 unsigned &ProcessorIMod, 4855 StringRef &ITMask) { 4856 PredicationCode = ARMCC::AL; 4857 CarrySetting = false; 4858 ProcessorIMod = 0; 4859 4860 // Ignore some mnemonics we know aren't predicated forms. 4861 // 4862 // FIXME: Would be nice to autogen this. 4863 if ((Mnemonic == "movs" && isThumb()) || 4864 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4865 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4866 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4867 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4868 Mnemonic == "vaclt" || Mnemonic == "vacle" || 4869 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4870 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4871 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4872 Mnemonic == "fmuls") 4873 return Mnemonic; 4874 4875 // First, split out any predication code. Ignore mnemonics we know aren't 4876 // predicated but do have a carry-set and so weren't caught above. 4877 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4878 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4879 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4880 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4881 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4882 .Case("eq", ARMCC::EQ) 4883 .Case("ne", ARMCC::NE) 4884 .Case("hs", ARMCC::HS) 4885 .Case("cs", ARMCC::HS) 4886 .Case("lo", ARMCC::LO) 4887 .Case("cc", ARMCC::LO) 4888 .Case("mi", ARMCC::MI) 4889 .Case("pl", ARMCC::PL) 4890 .Case("vs", ARMCC::VS) 4891 .Case("vc", ARMCC::VC) 4892 .Case("hi", ARMCC::HI) 4893 .Case("ls", ARMCC::LS) 4894 .Case("ge", ARMCC::GE) 4895 .Case("lt", ARMCC::LT) 4896 .Case("gt", ARMCC::GT) 4897 .Case("le", ARMCC::LE) 4898 .Case("al", ARMCC::AL) 4899 .Default(~0U); 4900 if (CC != ~0U) { 4901 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4902 PredicationCode = CC; 4903 } 4904 } 4905 4906 // Next, determine if we have a carry setting bit. We explicitly ignore all 4907 // the instructions we know end in 's'. 4908 if (Mnemonic.endswith("s") && 4909 !(Mnemonic == "cps" || Mnemonic == "mls" || 4910 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4911 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4912 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4913 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4914 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4915 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4916 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4917 Mnemonic == "vfms" || Mnemonic == "vfnms" || 4918 (Mnemonic == "movs" && isThumb()))) { 4919 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4920 CarrySetting = true; 4921 } 4922 4923 // The "cps" instruction can have a interrupt mode operand which is glued into 4924 // the mnemonic. Check if this is the case, split it and parse the imod op 4925 if (Mnemonic.startswith("cps")) { 4926 // Split out any imod code. 4927 unsigned IMod = 4928 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4929 .Case("ie", ARM_PROC::IE) 4930 .Case("id", ARM_PROC::ID) 4931 .Default(~0U); 4932 if (IMod != ~0U) { 4933 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4934 ProcessorIMod = IMod; 4935 } 4936 } 4937 4938 // The "it" instruction has the condition mask on the end of the mnemonic. 4939 if (Mnemonic.startswith("it")) { 4940 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4941 Mnemonic = Mnemonic.slice(0, 2); 4942 } 4943 4944 return Mnemonic; 4945 } 4946 4947 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 4948 /// inclusion of carry set or predication code operands. 4949 // 4950 // FIXME: It would be nice to autogen this. 4951 void ARMAsmParser:: 4952 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4953 bool &CanAcceptPredicationCode) { 4954 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4955 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4956 Mnemonic == "add" || Mnemonic == "adc" || 4957 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4958 Mnemonic == "orr" || Mnemonic == "mvn" || 4959 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4960 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4961 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4962 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4963 Mnemonic == "mla" || Mnemonic == "smlal" || 4964 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4965 CanAcceptCarrySet = true; 4966 } else 4967 CanAcceptCarrySet = false; 4968 4969 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4970 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4971 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4972 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4973 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4974 (Mnemonic == "clrex" && !isThumb()) || 4975 (Mnemonic == "nop" && isThumbOne()) || 4976 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 4977 Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 4978 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 4979 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 4980 !isThumb()) || 4981 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 4982 CanAcceptPredicationCode = false; 4983 } else 4984 CanAcceptPredicationCode = true; 4985 4986 if (isThumb()) { 4987 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 4988 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4989 CanAcceptPredicationCode = false; 4990 } 4991 } 4992 4993 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4994 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4995 // FIXME: This is all horribly hacky. We really need a better way to deal 4996 // with optional operands like this in the matcher table. 4997 4998 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4999 // another does not. Specifically, the MOVW instruction does not. So we 5000 // special case it here and remove the defaulted (non-setting) cc_out 5001 // operand if that's the instruction we're trying to match. 5002 // 5003 // We do this as post-processing of the explicit operands rather than just 5004 // conditionally adding the cc_out in the first place because we need 5005 // to check the type of the parsed immediate operand. 5006 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 5007 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 5008 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 5009 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 5010 return true; 5011 5012 // Register-register 'add' for thumb does not have a cc_out operand 5013 // when there are only two register operands. 5014 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 5015 static_cast<ARMOperand*>(Operands[3])->isReg() && 5016 static_cast<ARMOperand*>(Operands[4])->isReg() && 5017 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 5018 return true; 5019 // Register-register 'add' for thumb does not have a cc_out operand 5020 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 5021 // have to check the immediate range here since Thumb2 has a variant 5022 // that can handle a different range and has a cc_out operand. 5023 if (((isThumb() && Mnemonic == "add") || 5024 (isThumbTwo() && Mnemonic == "sub")) && 5025 Operands.size() == 6 && 5026 static_cast<ARMOperand*>(Operands[3])->isReg() && 5027 static_cast<ARMOperand*>(Operands[4])->isReg() && 5028 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 5029 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5030 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 5031 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 5032 return true; 5033 // For Thumb2, add/sub immediate does not have a cc_out operand for the 5034 // imm0_4095 variant. That's the least-preferred variant when 5035 // selecting via the generic "add" mnemonic, so to know that we 5036 // should remove the cc_out operand, we have to explicitly check that 5037 // it's not one of the other variants. Ugh. 5038 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 5039 Operands.size() == 6 && 5040 static_cast<ARMOperand*>(Operands[3])->isReg() && 5041 static_cast<ARMOperand*>(Operands[4])->isReg() && 5042 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5043 // Nest conditions rather than one big 'if' statement for readability. 5044 // 5045 // If either register is a high reg, it's either one of the SP 5046 // variants (handled above) or a 32-bit encoding, so we just 5047 // check against T3. If the second register is the PC, this is an 5048 // alternate form of ADR, which uses encoding T4, so check for that too. 5049 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5050 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 5051 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 5052 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 5053 return false; 5054 // If both registers are low, we're in an IT block, and the immediate is 5055 // in range, we should use encoding T1 instead, which has a cc_out. 5056 if (inITBlock() && 5057 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 5058 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 5059 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 5060 return false; 5061 5062 // Otherwise, we use encoding T4, which does not have a cc_out 5063 // operand. 5064 return true; 5065 } 5066 5067 // The thumb2 multiply instruction doesn't have a CCOut register, so 5068 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 5069 // use the 16-bit encoding or not. 5070 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 5071 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5072 static_cast<ARMOperand*>(Operands[3])->isReg() && 5073 static_cast<ARMOperand*>(Operands[4])->isReg() && 5074 static_cast<ARMOperand*>(Operands[5])->isReg() && 5075 // If the registers aren't low regs, the destination reg isn't the 5076 // same as one of the source regs, or the cc_out operand is zero 5077 // outside of an IT block, we have to use the 32-bit encoding, so 5078 // remove the cc_out operand. 5079 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5080 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 5081 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 5082 !inITBlock() || 5083 (static_cast<ARMOperand*>(Operands[3])->getReg() != 5084 static_cast<ARMOperand*>(Operands[5])->getReg() && 5085 static_cast<ARMOperand*>(Operands[3])->getReg() != 5086 static_cast<ARMOperand*>(Operands[4])->getReg()))) 5087 return true; 5088 5089 // Also check the 'mul' syntax variant that doesn't specify an explicit 5090 // destination register. 5091 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 5092 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5093 static_cast<ARMOperand*>(Operands[3])->isReg() && 5094 static_cast<ARMOperand*>(Operands[4])->isReg() && 5095 // If the registers aren't low regs or the cc_out operand is zero 5096 // outside of an IT block, we have to use the 32-bit encoding, so 5097 // remove the cc_out operand. 5098 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 5099 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 5100 !inITBlock())) 5101 return true; 5102 5103 5104 5105 // Register-register 'add/sub' for thumb does not have a cc_out operand 5106 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 5107 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 5108 // right, this will result in better diagnostics (which operand is off) 5109 // anyway. 5110 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 5111 (Operands.size() == 5 || Operands.size() == 6) && 5112 static_cast<ARMOperand*>(Operands[3])->isReg() && 5113 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 5114 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 5115 (static_cast<ARMOperand*>(Operands[4])->isImm() || 5116 (Operands.size() == 6 && 5117 static_cast<ARMOperand*>(Operands[5])->isImm()))) 5118 return true; 5119 5120 return false; 5121 } 5122 5123 static bool isDataTypeToken(StringRef Tok) { 5124 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 5125 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 5126 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 5127 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 5128 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 5129 Tok == ".f" || Tok == ".d"; 5130 } 5131 5132 // FIXME: This bit should probably be handled via an explicit match class 5133 // in the .td files that matches the suffix instead of having it be 5134 // a literal string token the way it is now. 5135 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 5136 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 5137 } 5138 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, 5139 unsigned VariantID); 5140 /// Parse an arm instruction mnemonic followed by its operands. 5141 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 5142 SMLoc NameLoc, 5143 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5144 // Apply mnemonic aliases before doing anything else, as the destination 5145 // mnemnonic may include suffices and we want to handle them normally. 5146 // The generic tblgen'erated code does this later, at the start of 5147 // MatchInstructionImpl(), but that's too late for aliases that include 5148 // any sort of suffix. 5149 unsigned AvailableFeatures = getAvailableFeatures(); 5150 unsigned AssemblerDialect = getParser().getAssemblerDialect(); 5151 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 5152 5153 // First check for the ARM-specific .req directive. 5154 if (Parser.getTok().is(AsmToken::Identifier) && 5155 Parser.getTok().getIdentifier() == ".req") { 5156 parseDirectiveReq(Name, NameLoc); 5157 // We always return 'error' for this, as we're done with this 5158 // statement and don't need to match the 'instruction." 5159 return true; 5160 } 5161 5162 // Create the leading tokens for the mnemonic, split by '.' characters. 5163 size_t Start = 0, Next = Name.find('.'); 5164 StringRef Mnemonic = Name.slice(Start, Next); 5165 5166 // Split out the predication code and carry setting flag from the mnemonic. 5167 unsigned PredicationCode; 5168 unsigned ProcessorIMod; 5169 bool CarrySetting; 5170 StringRef ITMask; 5171 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5172 ProcessorIMod, ITMask); 5173 5174 // In Thumb1, only the branch (B) instruction can be predicated. 5175 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 5176 Parser.eatToEndOfStatement(); 5177 return Error(NameLoc, "conditional execution not supported in Thumb1"); 5178 } 5179 5180 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5181 5182 // Handle the IT instruction ITMask. Convert it to a bitmask. This 5183 // is the mask as it will be for the IT encoding if the conditional 5184 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5185 // where the conditional bit0 is zero, the instruction post-processing 5186 // will adjust the mask accordingly. 5187 if (Mnemonic == "it") { 5188 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5189 if (ITMask.size() > 3) { 5190 Parser.eatToEndOfStatement(); 5191 return Error(Loc, "too many conditions on IT instruction"); 5192 } 5193 unsigned Mask = 8; 5194 for (unsigned i = ITMask.size(); i != 0; --i) { 5195 char pos = ITMask[i - 1]; 5196 if (pos != 't' && pos != 'e') { 5197 Parser.eatToEndOfStatement(); 5198 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5199 } 5200 Mask >>= 1; 5201 if (ITMask[i - 1] == 't') 5202 Mask |= 8; 5203 } 5204 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5205 } 5206 5207 // FIXME: This is all a pretty gross hack. We should automatically handle 5208 // optional operands like this via tblgen. 5209 5210 // Next, add the CCOut and ConditionCode operands, if needed. 5211 // 5212 // For mnemonics which can ever incorporate a carry setting bit or predication 5213 // code, our matching model involves us always generating CCOut and 5214 // ConditionCode operands to match the mnemonic "as written" and then we let 5215 // the matcher deal with finding the right instruction or generating an 5216 // appropriate error. 5217 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5218 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 5219 5220 // If we had a carry-set on an instruction that can't do that, issue an 5221 // error. 5222 if (!CanAcceptCarrySet && CarrySetting) { 5223 Parser.eatToEndOfStatement(); 5224 return Error(NameLoc, "instruction '" + Mnemonic + 5225 "' can not set flags, but 's' suffix specified"); 5226 } 5227 // If we had a predication code on an instruction that can't do that, issue an 5228 // error. 5229 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5230 Parser.eatToEndOfStatement(); 5231 return Error(NameLoc, "instruction '" + Mnemonic + 5232 "' is not predicable, but condition code specified"); 5233 } 5234 5235 // Add the carry setting operand, if necessary. 5236 if (CanAcceptCarrySet) { 5237 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5238 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5239 Loc)); 5240 } 5241 5242 // Add the predication code operand, if necessary. 5243 if (CanAcceptPredicationCode) { 5244 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5245 CarrySetting); 5246 Operands.push_back(ARMOperand::CreateCondCode( 5247 ARMCC::CondCodes(PredicationCode), Loc)); 5248 } 5249 5250 // Add the processor imod operand, if necessary. 5251 if (ProcessorIMod) { 5252 Operands.push_back(ARMOperand::CreateImm( 5253 MCConstantExpr::Create(ProcessorIMod, getContext()), 5254 NameLoc, NameLoc)); 5255 } 5256 5257 // Add the remaining tokens in the mnemonic. 5258 while (Next != StringRef::npos) { 5259 Start = Next; 5260 Next = Name.find('.', Start + 1); 5261 StringRef ExtraToken = Name.slice(Start, Next); 5262 5263 // Some NEON instructions have an optional datatype suffix that is 5264 // completely ignored. Check for that. 5265 if (isDataTypeToken(ExtraToken) && 5266 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5267 continue; 5268 5269 if (ExtraToken != ".n") { 5270 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5271 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5272 } 5273 } 5274 5275 // Read the remaining operands. 5276 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5277 // Read the first operand. 5278 if (parseOperand(Operands, Mnemonic)) { 5279 Parser.eatToEndOfStatement(); 5280 return true; 5281 } 5282 5283 while (getLexer().is(AsmToken::Comma)) { 5284 Parser.Lex(); // Eat the comma. 5285 5286 // Parse and remember the operand. 5287 if (parseOperand(Operands, Mnemonic)) { 5288 Parser.eatToEndOfStatement(); 5289 return true; 5290 } 5291 } 5292 } 5293 5294 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5295 SMLoc Loc = getLexer().getLoc(); 5296 Parser.eatToEndOfStatement(); 5297 return Error(Loc, "unexpected token in argument list"); 5298 } 5299 5300 Parser.Lex(); // Consume the EndOfStatement 5301 5302 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5303 // do and don't have a cc_out optional-def operand. With some spot-checks 5304 // of the operand list, we can figure out which variant we're trying to 5305 // parse and adjust accordingly before actually matching. We shouldn't ever 5306 // try to remove a cc_out operand that was explicitly set on the the 5307 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5308 // table driven matcher doesn't fit well with the ARM instruction set. 5309 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5310 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5311 Operands.erase(Operands.begin() + 1); 5312 delete Op; 5313 } 5314 5315 // ARM mode 'blx' need special handling, as the register operand version 5316 // is predicable, but the label operand version is not. So, we can't rely 5317 // on the Mnemonic based checking to correctly figure out when to put 5318 // a k_CondCode operand in the list. If we're trying to match the label 5319 // version, remove the k_CondCode operand here. 5320 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5321 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5322 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5323 Operands.erase(Operands.begin() + 1); 5324 delete Op; 5325 } 5326 5327 // Adjust operands of ldrexd/strexd to MCK_GPRPair. 5328 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 5329 // a single GPRPair reg operand is used in the .td file to replace the two 5330 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 5331 // expressed as a GPRPair, so we have to manually merge them. 5332 // FIXME: We would really like to be able to tablegen'erate this. 5333 if (!isThumb() && Operands.size() > 4 && 5334 (Mnemonic == "ldrexd" || Mnemonic == "strexd")) { 5335 bool isLoad = (Mnemonic == "ldrexd"); 5336 unsigned Idx = isLoad ? 2 : 3; 5337 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]); 5338 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]); 5339 5340 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 5341 // Adjust only if Op1 and Op2 are GPRs. 5342 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) && 5343 MRC.contains(Op2->getReg())) { 5344 unsigned Reg1 = Op1->getReg(); 5345 unsigned Reg2 = Op2->getReg(); 5346 unsigned Rt = MRI->getEncodingValue(Reg1); 5347 unsigned Rt2 = MRI->getEncodingValue(Reg2); 5348 5349 // Rt2 must be Rt + 1 and Rt must be even. 5350 if (Rt + 1 != Rt2 || (Rt & 1)) { 5351 Error(Op2->getStartLoc(), isLoad ? 5352 "destination operands must be sequential" : 5353 "source operands must be sequential"); 5354 return true; 5355 } 5356 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 5357 &(MRI->getRegClass(ARM::GPRPairRegClassID))); 5358 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2); 5359 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg( 5360 NewReg, Op1->getStartLoc(), Op2->getEndLoc())); 5361 delete Op1; 5362 delete Op2; 5363 } 5364 } 5365 5366 return false; 5367 } 5368 5369 // Validate context-sensitive operand constraints. 5370 5371 // return 'true' if register list contains non-low GPR registers, 5372 // 'false' otherwise. If Reg is in the register list or is HiReg, set 5373 // 'containsReg' to true. 5374 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5375 unsigned HiReg, bool &containsReg) { 5376 containsReg = false; 5377 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5378 unsigned OpReg = Inst.getOperand(i).getReg(); 5379 if (OpReg == Reg) 5380 containsReg = true; 5381 // Anything other than a low register isn't legal here. 5382 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5383 return true; 5384 } 5385 return false; 5386 } 5387 5388 // Check if the specified regisgter is in the register list of the inst, 5389 // starting at the indicated operand number. 5390 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5391 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5392 unsigned OpReg = Inst.getOperand(i).getReg(); 5393 if (OpReg == Reg) 5394 return true; 5395 } 5396 return false; 5397 } 5398 5399 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around 5400 // the ARMInsts array) instead. Getting that here requires awkward 5401 // API changes, though. Better way? 5402 namespace llvm { 5403 extern const MCInstrDesc ARMInsts[]; 5404 } 5405 static const MCInstrDesc &getInstDesc(unsigned Opcode) { 5406 return ARMInsts[Opcode]; 5407 } 5408 5409 // FIXME: We would really like to be able to tablegen'erate this. 5410 bool ARMAsmParser:: 5411 validateInstruction(MCInst &Inst, 5412 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5413 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5414 SMLoc Loc = Operands[0]->getStartLoc(); 5415 // Check the IT block state first. 5416 // NOTE: BKPT instruction has the interesting property of being 5417 // allowed in IT blocks, but not being predicable. It just always 5418 // executes. 5419 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && 5420 Inst.getOpcode() != ARM::BKPT) { 5421 unsigned bit = 1; 5422 if (ITState.FirstCond) 5423 ITState.FirstCond = false; 5424 else 5425 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5426 // The instruction must be predicable. 5427 if (!MCID.isPredicable()) 5428 return Error(Loc, "instructions in IT block must be predicable"); 5429 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5430 unsigned ITCond = bit ? ITState.Cond : 5431 ARMCC::getOppositeCondition(ITState.Cond); 5432 if (Cond != ITCond) { 5433 // Find the condition code Operand to get its SMLoc information. 5434 SMLoc CondLoc; 5435 for (unsigned i = 1; i < Operands.size(); ++i) 5436 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5437 CondLoc = Operands[i]->getStartLoc(); 5438 return Error(CondLoc, "incorrect condition in IT block; got '" + 5439 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5440 "', but expected '" + 5441 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5442 } 5443 // Check for non-'al' condition codes outside of the IT block. 5444 } else if (isThumbTwo() && MCID.isPredicable() && 5445 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5446 ARMCC::AL && Inst.getOpcode() != ARM::tB && 5447 Inst.getOpcode() != ARM::t2B) 5448 return Error(Loc, "predicated instructions must be in IT block"); 5449 5450 switch (Inst.getOpcode()) { 5451 case ARM::LDRD: 5452 case ARM::LDRD_PRE: 5453 case ARM::LDRD_POST: { 5454 // Rt2 must be Rt + 1. 5455 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5456 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5457 if (Rt2 != Rt + 1) 5458 return Error(Operands[3]->getStartLoc(), 5459 "destination operands must be sequential"); 5460 return false; 5461 } 5462 case ARM::STRD: { 5463 // Rt2 must be Rt + 1. 5464 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5465 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5466 if (Rt2 != Rt + 1) 5467 return Error(Operands[3]->getStartLoc(), 5468 "source operands must be sequential"); 5469 return false; 5470 } 5471 case ARM::STRD_PRE: 5472 case ARM::STRD_POST: { 5473 // Rt2 must be Rt + 1. 5474 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5475 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5476 if (Rt2 != Rt + 1) 5477 return Error(Operands[3]->getStartLoc(), 5478 "source operands must be sequential"); 5479 return false; 5480 } 5481 case ARM::SBFX: 5482 case ARM::UBFX: { 5483 // width must be in range [1, 32-lsb] 5484 unsigned lsb = Inst.getOperand(2).getImm(); 5485 unsigned widthm1 = Inst.getOperand(3).getImm(); 5486 if (widthm1 >= 32 - lsb) 5487 return Error(Operands[5]->getStartLoc(), 5488 "bitfield width must be in range [1,32-lsb]"); 5489 return false; 5490 } 5491 case ARM::tLDMIA: { 5492 // If we're parsing Thumb2, the .w variant is available and handles 5493 // most cases that are normally illegal for a Thumb1 LDM 5494 // instruction. We'll make the transformation in processInstruction() 5495 // if necessary. 5496 // 5497 // Thumb LDM instructions are writeback iff the base register is not 5498 // in the register list. 5499 unsigned Rn = Inst.getOperand(0).getReg(); 5500 bool hasWritebackToken = 5501 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5502 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5503 bool listContainsBase; 5504 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5505 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5506 "registers must be in range r0-r7"); 5507 // If we should have writeback, then there should be a '!' token. 5508 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 5509 return Error(Operands[2]->getStartLoc(), 5510 "writeback operator '!' expected"); 5511 // If we should not have writeback, there must not be a '!'. This is 5512 // true even for the 32-bit wide encodings. 5513 if (listContainsBase && hasWritebackToken) 5514 return Error(Operands[3]->getStartLoc(), 5515 "writeback operator '!' not allowed when base register " 5516 "in register list"); 5517 5518 break; 5519 } 5520 case ARM::t2LDMIA_UPD: { 5521 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5522 return Error(Operands[4]->getStartLoc(), 5523 "writeback operator '!' not allowed when base register " 5524 "in register list"); 5525 break; 5526 } 5527 case ARM::tMUL: { 5528 // The second source operand must be the same register as the destination 5529 // operand. 5530 // 5531 // In this case, we must directly check the parsed operands because the 5532 // cvtThumbMultiply() function is written in such a way that it guarantees 5533 // this first statement is always true for the new Inst. Essentially, the 5534 // destination is unconditionally copied into the second source operand 5535 // without checking to see if it matches what we actually parsed. 5536 if (Operands.size() == 6 && 5537 (((ARMOperand*)Operands[3])->getReg() != 5538 ((ARMOperand*)Operands[5])->getReg()) && 5539 (((ARMOperand*)Operands[3])->getReg() != 5540 ((ARMOperand*)Operands[4])->getReg())) { 5541 return Error(Operands[3]->getStartLoc(), 5542 "destination register must match source register"); 5543 } 5544 break; 5545 } 5546 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5547 // so only issue a diagnostic for thumb1. The instructions will be 5548 // switched to the t2 encodings in processInstruction() if necessary. 5549 case ARM::tPOP: { 5550 bool listContainsBase; 5551 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 5552 !isThumbTwo()) 5553 return Error(Operands[2]->getStartLoc(), 5554 "registers must be in range r0-r7 or pc"); 5555 break; 5556 } 5557 case ARM::tPUSH: { 5558 bool listContainsBase; 5559 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 5560 !isThumbTwo()) 5561 return Error(Operands[2]->getStartLoc(), 5562 "registers must be in range r0-r7 or lr"); 5563 break; 5564 } 5565 case ARM::tSTMIA_UPD: { 5566 bool listContainsBase; 5567 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 5568 return Error(Operands[4]->getStartLoc(), 5569 "registers must be in range r0-r7"); 5570 break; 5571 } 5572 case ARM::tADDrSP: { 5573 // If the non-SP source operand and the destination operand are not the 5574 // same, we need thumb2 (for the wide encoding), or we have an error. 5575 if (!isThumbTwo() && 5576 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5577 return Error(Operands[4]->getStartLoc(), 5578 "source register must be the same as destination"); 5579 } 5580 break; 5581 } 5582 } 5583 5584 return false; 5585 } 5586 5587 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5588 switch(Opc) { 5589 default: llvm_unreachable("unexpected opcode!"); 5590 // VST1LN 5591 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5592 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5593 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5594 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5595 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5596 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5597 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5598 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5599 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5600 5601 // VST2LN 5602 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5603 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5604 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5605 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5606 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5607 5608 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5609 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5610 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5611 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5612 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5613 5614 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5615 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5616 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5617 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5618 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5619 5620 // VST3LN 5621 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5622 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5623 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5624 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5625 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5626 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5627 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5628 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5629 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5630 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5631 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5632 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5633 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5634 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5635 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5636 5637 // VST3 5638 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5639 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5640 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5641 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5642 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5643 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5644 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5645 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5646 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5647 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5648 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5649 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5650 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5651 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5652 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5653 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5654 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5655 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5656 5657 // VST4LN 5658 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5659 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5660 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5661 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5662 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5663 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5664 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5665 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5666 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5667 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5668 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5669 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5670 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5671 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5672 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5673 5674 // VST4 5675 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5676 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5677 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5678 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5679 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5680 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5681 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5682 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5683 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5684 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5685 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5686 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5687 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5688 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5689 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5690 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5691 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5692 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5693 } 5694 } 5695 5696 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5697 switch(Opc) { 5698 default: llvm_unreachable("unexpected opcode!"); 5699 // VLD1LN 5700 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5701 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5702 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5703 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5704 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5705 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5706 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5707 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5708 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5709 5710 // VLD2LN 5711 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5712 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5713 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5714 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5715 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5716 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5717 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5718 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5719 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5720 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5721 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5722 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5723 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5724 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5725 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5726 5727 // VLD3DUP 5728 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5729 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5730 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5731 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5732 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5733 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5734 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5735 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5736 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5737 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5738 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5739 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5740 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5741 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5742 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5743 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5744 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5745 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5746 5747 // VLD3LN 5748 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5749 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5750 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5751 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5752 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5753 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5754 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5755 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5756 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5757 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5758 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5759 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5760 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5761 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5762 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5763 5764 // VLD3 5765 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5766 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5767 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5768 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5769 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5770 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5771 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5772 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5773 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5774 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5775 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5776 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5777 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5778 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5779 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5780 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5781 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5782 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5783 5784 // VLD4LN 5785 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5786 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5787 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5788 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5789 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5790 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5791 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5792 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5793 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5794 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5795 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5796 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5797 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5798 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5799 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5800 5801 // VLD4DUP 5802 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5803 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5804 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5805 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5806 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5807 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5808 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5809 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5810 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5811 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5812 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5813 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5814 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5815 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5816 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5817 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5818 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5819 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5820 5821 // VLD4 5822 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5823 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5824 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5825 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5826 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5827 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5828 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5829 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5830 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5831 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5832 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5833 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5834 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 5835 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 5836 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 5837 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 5838 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 5839 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 5840 } 5841 } 5842 5843 bool ARMAsmParser:: 5844 processInstruction(MCInst &Inst, 5845 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5846 switch (Inst.getOpcode()) { 5847 // Alias for alternate form of 'ADR Rd, #imm' instruction. 5848 case ARM::ADDri: { 5849 if (Inst.getOperand(1).getReg() != ARM::PC || 5850 Inst.getOperand(5).getReg() != 0) 5851 return false; 5852 MCInst TmpInst; 5853 TmpInst.setOpcode(ARM::ADR); 5854 TmpInst.addOperand(Inst.getOperand(0)); 5855 TmpInst.addOperand(Inst.getOperand(2)); 5856 TmpInst.addOperand(Inst.getOperand(3)); 5857 TmpInst.addOperand(Inst.getOperand(4)); 5858 Inst = TmpInst; 5859 return true; 5860 } 5861 // Aliases for alternate PC+imm syntax of LDR instructions. 5862 case ARM::t2LDRpcrel: 5863 // Select the narrow version if the immediate will fit. 5864 if (Inst.getOperand(1).getImm() > 0 && 5865 Inst.getOperand(1).getImm() <= 0xff) 5866 Inst.setOpcode(ARM::tLDRpci); 5867 else 5868 Inst.setOpcode(ARM::t2LDRpci); 5869 return true; 5870 case ARM::t2LDRBpcrel: 5871 Inst.setOpcode(ARM::t2LDRBpci); 5872 return true; 5873 case ARM::t2LDRHpcrel: 5874 Inst.setOpcode(ARM::t2LDRHpci); 5875 return true; 5876 case ARM::t2LDRSBpcrel: 5877 Inst.setOpcode(ARM::t2LDRSBpci); 5878 return true; 5879 case ARM::t2LDRSHpcrel: 5880 Inst.setOpcode(ARM::t2LDRSHpci); 5881 return true; 5882 // Handle NEON VST complex aliases. 5883 case ARM::VST1LNdWB_register_Asm_8: 5884 case ARM::VST1LNdWB_register_Asm_16: 5885 case ARM::VST1LNdWB_register_Asm_32: { 5886 MCInst TmpInst; 5887 // Shuffle the operands around so the lane index operand is in the 5888 // right place. 5889 unsigned Spacing; 5890 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5891 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5892 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5893 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5894 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5895 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5896 TmpInst.addOperand(Inst.getOperand(1)); // lane 5897 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5898 TmpInst.addOperand(Inst.getOperand(6)); 5899 Inst = TmpInst; 5900 return true; 5901 } 5902 5903 case ARM::VST2LNdWB_register_Asm_8: 5904 case ARM::VST2LNdWB_register_Asm_16: 5905 case ARM::VST2LNdWB_register_Asm_32: 5906 case ARM::VST2LNqWB_register_Asm_16: 5907 case ARM::VST2LNqWB_register_Asm_32: { 5908 MCInst TmpInst; 5909 // Shuffle the operands around so the lane index operand is in the 5910 // right place. 5911 unsigned Spacing; 5912 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5913 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5914 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5915 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5916 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5917 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5918 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5919 Spacing)); 5920 TmpInst.addOperand(Inst.getOperand(1)); // lane 5921 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5922 TmpInst.addOperand(Inst.getOperand(6)); 5923 Inst = TmpInst; 5924 return true; 5925 } 5926 5927 case ARM::VST3LNdWB_register_Asm_8: 5928 case ARM::VST3LNdWB_register_Asm_16: 5929 case ARM::VST3LNdWB_register_Asm_32: 5930 case ARM::VST3LNqWB_register_Asm_16: 5931 case ARM::VST3LNqWB_register_Asm_32: { 5932 MCInst TmpInst; 5933 // Shuffle the operands around so the lane index operand is in the 5934 // right place. 5935 unsigned Spacing; 5936 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5937 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5938 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5939 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5940 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5941 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5942 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5943 Spacing)); 5944 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5945 Spacing * 2)); 5946 TmpInst.addOperand(Inst.getOperand(1)); // lane 5947 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5948 TmpInst.addOperand(Inst.getOperand(6)); 5949 Inst = TmpInst; 5950 return true; 5951 } 5952 5953 case ARM::VST4LNdWB_register_Asm_8: 5954 case ARM::VST4LNdWB_register_Asm_16: 5955 case ARM::VST4LNdWB_register_Asm_32: 5956 case ARM::VST4LNqWB_register_Asm_16: 5957 case ARM::VST4LNqWB_register_Asm_32: { 5958 MCInst TmpInst; 5959 // Shuffle the operands around so the lane index operand is in the 5960 // right place. 5961 unsigned Spacing; 5962 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5963 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5964 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5965 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5966 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5967 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5968 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5969 Spacing)); 5970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5971 Spacing * 2)); 5972 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5973 Spacing * 3)); 5974 TmpInst.addOperand(Inst.getOperand(1)); // lane 5975 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5976 TmpInst.addOperand(Inst.getOperand(6)); 5977 Inst = TmpInst; 5978 return true; 5979 } 5980 5981 case ARM::VST1LNdWB_fixed_Asm_8: 5982 case ARM::VST1LNdWB_fixed_Asm_16: 5983 case ARM::VST1LNdWB_fixed_Asm_32: { 5984 MCInst TmpInst; 5985 // Shuffle the operands around so the lane index operand is in the 5986 // right place. 5987 unsigned Spacing; 5988 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5989 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5990 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5991 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5992 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5993 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5994 TmpInst.addOperand(Inst.getOperand(1)); // lane 5995 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5996 TmpInst.addOperand(Inst.getOperand(5)); 5997 Inst = TmpInst; 5998 return true; 5999 } 6000 6001 case ARM::VST2LNdWB_fixed_Asm_8: 6002 case ARM::VST2LNdWB_fixed_Asm_16: 6003 case ARM::VST2LNdWB_fixed_Asm_32: 6004 case ARM::VST2LNqWB_fixed_Asm_16: 6005 case ARM::VST2LNqWB_fixed_Asm_32: { 6006 MCInst TmpInst; 6007 // Shuffle the operands around so the lane index operand is in the 6008 // right place. 6009 unsigned Spacing; 6010 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6011 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6012 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6013 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6014 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6015 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6016 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6017 Spacing)); 6018 TmpInst.addOperand(Inst.getOperand(1)); // lane 6019 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6020 TmpInst.addOperand(Inst.getOperand(5)); 6021 Inst = TmpInst; 6022 return true; 6023 } 6024 6025 case ARM::VST3LNdWB_fixed_Asm_8: 6026 case ARM::VST3LNdWB_fixed_Asm_16: 6027 case ARM::VST3LNdWB_fixed_Asm_32: 6028 case ARM::VST3LNqWB_fixed_Asm_16: 6029 case ARM::VST3LNqWB_fixed_Asm_32: { 6030 MCInst TmpInst; 6031 // Shuffle the operands around so the lane index operand is in the 6032 // right place. 6033 unsigned Spacing; 6034 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6035 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6036 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6037 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6038 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6039 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6040 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6041 Spacing)); 6042 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6043 Spacing * 2)); 6044 TmpInst.addOperand(Inst.getOperand(1)); // lane 6045 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6046 TmpInst.addOperand(Inst.getOperand(5)); 6047 Inst = TmpInst; 6048 return true; 6049 } 6050 6051 case ARM::VST4LNdWB_fixed_Asm_8: 6052 case ARM::VST4LNdWB_fixed_Asm_16: 6053 case ARM::VST4LNdWB_fixed_Asm_32: 6054 case ARM::VST4LNqWB_fixed_Asm_16: 6055 case ARM::VST4LNqWB_fixed_Asm_32: { 6056 MCInst TmpInst; 6057 // Shuffle the operands around so the lane index operand is in the 6058 // right place. 6059 unsigned Spacing; 6060 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6061 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6062 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6063 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6064 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6065 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6066 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6067 Spacing)); 6068 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6069 Spacing * 2)); 6070 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6071 Spacing * 3)); 6072 TmpInst.addOperand(Inst.getOperand(1)); // lane 6073 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6074 TmpInst.addOperand(Inst.getOperand(5)); 6075 Inst = TmpInst; 6076 return true; 6077 } 6078 6079 case ARM::VST1LNdAsm_8: 6080 case ARM::VST1LNdAsm_16: 6081 case ARM::VST1LNdAsm_32: { 6082 MCInst TmpInst; 6083 // Shuffle the operands around so the lane index operand is in the 6084 // right place. 6085 unsigned Spacing; 6086 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6087 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6088 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6089 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6090 TmpInst.addOperand(Inst.getOperand(1)); // lane 6091 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6092 TmpInst.addOperand(Inst.getOperand(5)); 6093 Inst = TmpInst; 6094 return true; 6095 } 6096 6097 case ARM::VST2LNdAsm_8: 6098 case ARM::VST2LNdAsm_16: 6099 case ARM::VST2LNdAsm_32: 6100 case ARM::VST2LNqAsm_16: 6101 case ARM::VST2LNqAsm_32: { 6102 MCInst TmpInst; 6103 // Shuffle the operands around so the lane index operand is in the 6104 // right place. 6105 unsigned Spacing; 6106 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6107 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6108 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6109 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6110 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6111 Spacing)); 6112 TmpInst.addOperand(Inst.getOperand(1)); // lane 6113 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6114 TmpInst.addOperand(Inst.getOperand(5)); 6115 Inst = TmpInst; 6116 return true; 6117 } 6118 6119 case ARM::VST3LNdAsm_8: 6120 case ARM::VST3LNdAsm_16: 6121 case ARM::VST3LNdAsm_32: 6122 case ARM::VST3LNqAsm_16: 6123 case ARM::VST3LNqAsm_32: { 6124 MCInst TmpInst; 6125 // Shuffle the operands around so the lane index operand is in the 6126 // right place. 6127 unsigned Spacing; 6128 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6129 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6130 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6131 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6132 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6133 Spacing)); 6134 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6135 Spacing * 2)); 6136 TmpInst.addOperand(Inst.getOperand(1)); // lane 6137 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6138 TmpInst.addOperand(Inst.getOperand(5)); 6139 Inst = TmpInst; 6140 return true; 6141 } 6142 6143 case ARM::VST4LNdAsm_8: 6144 case ARM::VST4LNdAsm_16: 6145 case ARM::VST4LNdAsm_32: 6146 case ARM::VST4LNqAsm_16: 6147 case ARM::VST4LNqAsm_32: { 6148 MCInst TmpInst; 6149 // Shuffle the operands around so the lane index operand is in the 6150 // right place. 6151 unsigned Spacing; 6152 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6153 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6154 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6155 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6156 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6157 Spacing)); 6158 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6159 Spacing * 2)); 6160 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6161 Spacing * 3)); 6162 TmpInst.addOperand(Inst.getOperand(1)); // lane 6163 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6164 TmpInst.addOperand(Inst.getOperand(5)); 6165 Inst = TmpInst; 6166 return true; 6167 } 6168 6169 // Handle NEON VLD complex aliases. 6170 case ARM::VLD1LNdWB_register_Asm_8: 6171 case ARM::VLD1LNdWB_register_Asm_16: 6172 case ARM::VLD1LNdWB_register_Asm_32: { 6173 MCInst TmpInst; 6174 // Shuffle the operands around so the lane index operand is in the 6175 // right place. 6176 unsigned Spacing; 6177 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6178 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6179 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6180 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6181 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6182 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6183 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6184 TmpInst.addOperand(Inst.getOperand(1)); // lane 6185 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6186 TmpInst.addOperand(Inst.getOperand(6)); 6187 Inst = TmpInst; 6188 return true; 6189 } 6190 6191 case ARM::VLD2LNdWB_register_Asm_8: 6192 case ARM::VLD2LNdWB_register_Asm_16: 6193 case ARM::VLD2LNdWB_register_Asm_32: 6194 case ARM::VLD2LNqWB_register_Asm_16: 6195 case ARM::VLD2LNqWB_register_Asm_32: { 6196 MCInst TmpInst; 6197 // Shuffle the operands around so the lane index operand is in the 6198 // right place. 6199 unsigned Spacing; 6200 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6201 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6202 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6203 Spacing)); 6204 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6205 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6206 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6207 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6208 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6209 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6210 Spacing)); 6211 TmpInst.addOperand(Inst.getOperand(1)); // lane 6212 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6213 TmpInst.addOperand(Inst.getOperand(6)); 6214 Inst = TmpInst; 6215 return true; 6216 } 6217 6218 case ARM::VLD3LNdWB_register_Asm_8: 6219 case ARM::VLD3LNdWB_register_Asm_16: 6220 case ARM::VLD3LNdWB_register_Asm_32: 6221 case ARM::VLD3LNqWB_register_Asm_16: 6222 case ARM::VLD3LNqWB_register_Asm_32: { 6223 MCInst TmpInst; 6224 // Shuffle the operands around so the lane index operand is in the 6225 // right place. 6226 unsigned Spacing; 6227 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6228 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6229 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6230 Spacing)); 6231 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6232 Spacing * 2)); 6233 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6234 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6235 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6236 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6237 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6238 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6239 Spacing)); 6240 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6241 Spacing * 2)); 6242 TmpInst.addOperand(Inst.getOperand(1)); // lane 6243 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6244 TmpInst.addOperand(Inst.getOperand(6)); 6245 Inst = TmpInst; 6246 return true; 6247 } 6248 6249 case ARM::VLD4LNdWB_register_Asm_8: 6250 case ARM::VLD4LNdWB_register_Asm_16: 6251 case ARM::VLD4LNdWB_register_Asm_32: 6252 case ARM::VLD4LNqWB_register_Asm_16: 6253 case ARM::VLD4LNqWB_register_Asm_32: { 6254 MCInst TmpInst; 6255 // Shuffle the operands around so the lane index operand is in the 6256 // right place. 6257 unsigned Spacing; 6258 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6259 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6260 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6261 Spacing)); 6262 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6263 Spacing * 2)); 6264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6265 Spacing * 3)); 6266 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6267 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6268 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6269 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6270 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6271 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6272 Spacing)); 6273 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6274 Spacing * 2)); 6275 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6276 Spacing * 3)); 6277 TmpInst.addOperand(Inst.getOperand(1)); // lane 6278 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6279 TmpInst.addOperand(Inst.getOperand(6)); 6280 Inst = TmpInst; 6281 return true; 6282 } 6283 6284 case ARM::VLD1LNdWB_fixed_Asm_8: 6285 case ARM::VLD1LNdWB_fixed_Asm_16: 6286 case ARM::VLD1LNdWB_fixed_Asm_32: { 6287 MCInst TmpInst; 6288 // Shuffle the operands around so the lane index operand is in the 6289 // right place. 6290 unsigned Spacing; 6291 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6292 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6293 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6294 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6295 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6296 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6297 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6298 TmpInst.addOperand(Inst.getOperand(1)); // lane 6299 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6300 TmpInst.addOperand(Inst.getOperand(5)); 6301 Inst = TmpInst; 6302 return true; 6303 } 6304 6305 case ARM::VLD2LNdWB_fixed_Asm_8: 6306 case ARM::VLD2LNdWB_fixed_Asm_16: 6307 case ARM::VLD2LNdWB_fixed_Asm_32: 6308 case ARM::VLD2LNqWB_fixed_Asm_16: 6309 case ARM::VLD2LNqWB_fixed_Asm_32: { 6310 MCInst TmpInst; 6311 // Shuffle the operands around so the lane index operand is in the 6312 // right place. 6313 unsigned Spacing; 6314 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6315 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6316 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6317 Spacing)); 6318 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6319 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6320 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6321 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6322 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6323 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6324 Spacing)); 6325 TmpInst.addOperand(Inst.getOperand(1)); // lane 6326 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6327 TmpInst.addOperand(Inst.getOperand(5)); 6328 Inst = TmpInst; 6329 return true; 6330 } 6331 6332 case ARM::VLD3LNdWB_fixed_Asm_8: 6333 case ARM::VLD3LNdWB_fixed_Asm_16: 6334 case ARM::VLD3LNdWB_fixed_Asm_32: 6335 case ARM::VLD3LNqWB_fixed_Asm_16: 6336 case ARM::VLD3LNqWB_fixed_Asm_32: { 6337 MCInst TmpInst; 6338 // Shuffle the operands around so the lane index operand is in the 6339 // right place. 6340 unsigned Spacing; 6341 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6342 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6343 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6344 Spacing)); 6345 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6346 Spacing * 2)); 6347 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6348 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6349 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6350 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6351 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6352 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6353 Spacing)); 6354 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6355 Spacing * 2)); 6356 TmpInst.addOperand(Inst.getOperand(1)); // lane 6357 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6358 TmpInst.addOperand(Inst.getOperand(5)); 6359 Inst = TmpInst; 6360 return true; 6361 } 6362 6363 case ARM::VLD4LNdWB_fixed_Asm_8: 6364 case ARM::VLD4LNdWB_fixed_Asm_16: 6365 case ARM::VLD4LNdWB_fixed_Asm_32: 6366 case ARM::VLD4LNqWB_fixed_Asm_16: 6367 case ARM::VLD4LNqWB_fixed_Asm_32: { 6368 MCInst TmpInst; 6369 // Shuffle the operands around so the lane index operand is in the 6370 // right place. 6371 unsigned Spacing; 6372 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6373 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6374 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6375 Spacing)); 6376 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6377 Spacing * 2)); 6378 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6379 Spacing * 3)); 6380 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6381 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6382 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6383 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6384 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6385 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6386 Spacing)); 6387 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6388 Spacing * 2)); 6389 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6390 Spacing * 3)); 6391 TmpInst.addOperand(Inst.getOperand(1)); // lane 6392 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6393 TmpInst.addOperand(Inst.getOperand(5)); 6394 Inst = TmpInst; 6395 return true; 6396 } 6397 6398 case ARM::VLD1LNdAsm_8: 6399 case ARM::VLD1LNdAsm_16: 6400 case ARM::VLD1LNdAsm_32: { 6401 MCInst TmpInst; 6402 // Shuffle the operands around so the lane index operand is in the 6403 // right place. 6404 unsigned Spacing; 6405 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6406 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6407 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6408 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6409 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6410 TmpInst.addOperand(Inst.getOperand(1)); // lane 6411 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6412 TmpInst.addOperand(Inst.getOperand(5)); 6413 Inst = TmpInst; 6414 return true; 6415 } 6416 6417 case ARM::VLD2LNdAsm_8: 6418 case ARM::VLD2LNdAsm_16: 6419 case ARM::VLD2LNdAsm_32: 6420 case ARM::VLD2LNqAsm_16: 6421 case ARM::VLD2LNqAsm_32: { 6422 MCInst TmpInst; 6423 // Shuffle the operands around so the lane index operand is in the 6424 // right place. 6425 unsigned Spacing; 6426 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6427 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6428 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6429 Spacing)); 6430 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6431 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6432 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6433 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6434 Spacing)); 6435 TmpInst.addOperand(Inst.getOperand(1)); // lane 6436 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6437 TmpInst.addOperand(Inst.getOperand(5)); 6438 Inst = TmpInst; 6439 return true; 6440 } 6441 6442 case ARM::VLD3LNdAsm_8: 6443 case ARM::VLD3LNdAsm_16: 6444 case ARM::VLD3LNdAsm_32: 6445 case ARM::VLD3LNqAsm_16: 6446 case ARM::VLD3LNqAsm_32: { 6447 MCInst TmpInst; 6448 // Shuffle the operands around so the lane index operand is in the 6449 // right place. 6450 unsigned Spacing; 6451 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6452 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6453 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6454 Spacing)); 6455 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6456 Spacing * 2)); 6457 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6458 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6459 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6460 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6461 Spacing)); 6462 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6463 Spacing * 2)); 6464 TmpInst.addOperand(Inst.getOperand(1)); // lane 6465 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6466 TmpInst.addOperand(Inst.getOperand(5)); 6467 Inst = TmpInst; 6468 return true; 6469 } 6470 6471 case ARM::VLD4LNdAsm_8: 6472 case ARM::VLD4LNdAsm_16: 6473 case ARM::VLD4LNdAsm_32: 6474 case ARM::VLD4LNqAsm_16: 6475 case ARM::VLD4LNqAsm_32: { 6476 MCInst TmpInst; 6477 // Shuffle the operands around so the lane index operand is in the 6478 // right place. 6479 unsigned Spacing; 6480 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6481 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6482 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6483 Spacing)); 6484 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6485 Spacing * 2)); 6486 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6487 Spacing * 3)); 6488 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6489 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6490 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6491 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6492 Spacing)); 6493 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6494 Spacing * 2)); 6495 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6496 Spacing * 3)); 6497 TmpInst.addOperand(Inst.getOperand(1)); // lane 6498 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6499 TmpInst.addOperand(Inst.getOperand(5)); 6500 Inst = TmpInst; 6501 return true; 6502 } 6503 6504 // VLD3DUP single 3-element structure to all lanes instructions. 6505 case ARM::VLD3DUPdAsm_8: 6506 case ARM::VLD3DUPdAsm_16: 6507 case ARM::VLD3DUPdAsm_32: 6508 case ARM::VLD3DUPqAsm_8: 6509 case ARM::VLD3DUPqAsm_16: 6510 case ARM::VLD3DUPqAsm_32: { 6511 MCInst TmpInst; 6512 unsigned Spacing; 6513 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6514 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6515 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6516 Spacing)); 6517 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6518 Spacing * 2)); 6519 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6520 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6521 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6522 TmpInst.addOperand(Inst.getOperand(4)); 6523 Inst = TmpInst; 6524 return true; 6525 } 6526 6527 case ARM::VLD3DUPdWB_fixed_Asm_8: 6528 case ARM::VLD3DUPdWB_fixed_Asm_16: 6529 case ARM::VLD3DUPdWB_fixed_Asm_32: 6530 case ARM::VLD3DUPqWB_fixed_Asm_8: 6531 case ARM::VLD3DUPqWB_fixed_Asm_16: 6532 case ARM::VLD3DUPqWB_fixed_Asm_32: { 6533 MCInst TmpInst; 6534 unsigned Spacing; 6535 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6536 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6537 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6538 Spacing)); 6539 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6540 Spacing * 2)); 6541 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6542 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6543 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6544 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6545 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6546 TmpInst.addOperand(Inst.getOperand(4)); 6547 Inst = TmpInst; 6548 return true; 6549 } 6550 6551 case ARM::VLD3DUPdWB_register_Asm_8: 6552 case ARM::VLD3DUPdWB_register_Asm_16: 6553 case ARM::VLD3DUPdWB_register_Asm_32: 6554 case ARM::VLD3DUPqWB_register_Asm_8: 6555 case ARM::VLD3DUPqWB_register_Asm_16: 6556 case ARM::VLD3DUPqWB_register_Asm_32: { 6557 MCInst TmpInst; 6558 unsigned Spacing; 6559 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6560 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6561 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6562 Spacing)); 6563 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6564 Spacing * 2)); 6565 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6566 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6567 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6568 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6569 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6570 TmpInst.addOperand(Inst.getOperand(5)); 6571 Inst = TmpInst; 6572 return true; 6573 } 6574 6575 // VLD3 multiple 3-element structure instructions. 6576 case ARM::VLD3dAsm_8: 6577 case ARM::VLD3dAsm_16: 6578 case ARM::VLD3dAsm_32: 6579 case ARM::VLD3qAsm_8: 6580 case ARM::VLD3qAsm_16: 6581 case ARM::VLD3qAsm_32: { 6582 MCInst TmpInst; 6583 unsigned Spacing; 6584 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6585 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6586 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6587 Spacing)); 6588 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6589 Spacing * 2)); 6590 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6591 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6592 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6593 TmpInst.addOperand(Inst.getOperand(4)); 6594 Inst = TmpInst; 6595 return true; 6596 } 6597 6598 case ARM::VLD3dWB_fixed_Asm_8: 6599 case ARM::VLD3dWB_fixed_Asm_16: 6600 case ARM::VLD3dWB_fixed_Asm_32: 6601 case ARM::VLD3qWB_fixed_Asm_8: 6602 case ARM::VLD3qWB_fixed_Asm_16: 6603 case ARM::VLD3qWB_fixed_Asm_32: { 6604 MCInst TmpInst; 6605 unsigned Spacing; 6606 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6607 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6608 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6609 Spacing)); 6610 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6611 Spacing * 2)); 6612 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6613 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6614 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6615 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6616 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6617 TmpInst.addOperand(Inst.getOperand(4)); 6618 Inst = TmpInst; 6619 return true; 6620 } 6621 6622 case ARM::VLD3dWB_register_Asm_8: 6623 case ARM::VLD3dWB_register_Asm_16: 6624 case ARM::VLD3dWB_register_Asm_32: 6625 case ARM::VLD3qWB_register_Asm_8: 6626 case ARM::VLD3qWB_register_Asm_16: 6627 case ARM::VLD3qWB_register_Asm_32: { 6628 MCInst TmpInst; 6629 unsigned Spacing; 6630 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6631 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6632 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6633 Spacing)); 6634 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6635 Spacing * 2)); 6636 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6637 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6638 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6639 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6640 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6641 TmpInst.addOperand(Inst.getOperand(5)); 6642 Inst = TmpInst; 6643 return true; 6644 } 6645 6646 // VLD4DUP single 3-element structure to all lanes instructions. 6647 case ARM::VLD4DUPdAsm_8: 6648 case ARM::VLD4DUPdAsm_16: 6649 case ARM::VLD4DUPdAsm_32: 6650 case ARM::VLD4DUPqAsm_8: 6651 case ARM::VLD4DUPqAsm_16: 6652 case ARM::VLD4DUPqAsm_32: { 6653 MCInst TmpInst; 6654 unsigned Spacing; 6655 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6656 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6657 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6658 Spacing)); 6659 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6660 Spacing * 2)); 6661 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6662 Spacing * 3)); 6663 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6664 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6665 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6666 TmpInst.addOperand(Inst.getOperand(4)); 6667 Inst = TmpInst; 6668 return true; 6669 } 6670 6671 case ARM::VLD4DUPdWB_fixed_Asm_8: 6672 case ARM::VLD4DUPdWB_fixed_Asm_16: 6673 case ARM::VLD4DUPdWB_fixed_Asm_32: 6674 case ARM::VLD4DUPqWB_fixed_Asm_8: 6675 case ARM::VLD4DUPqWB_fixed_Asm_16: 6676 case ARM::VLD4DUPqWB_fixed_Asm_32: { 6677 MCInst TmpInst; 6678 unsigned Spacing; 6679 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6680 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6681 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6682 Spacing)); 6683 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6684 Spacing * 2)); 6685 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6686 Spacing * 3)); 6687 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6688 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6689 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6690 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6691 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6692 TmpInst.addOperand(Inst.getOperand(4)); 6693 Inst = TmpInst; 6694 return true; 6695 } 6696 6697 case ARM::VLD4DUPdWB_register_Asm_8: 6698 case ARM::VLD4DUPdWB_register_Asm_16: 6699 case ARM::VLD4DUPdWB_register_Asm_32: 6700 case ARM::VLD4DUPqWB_register_Asm_8: 6701 case ARM::VLD4DUPqWB_register_Asm_16: 6702 case ARM::VLD4DUPqWB_register_Asm_32: { 6703 MCInst TmpInst; 6704 unsigned Spacing; 6705 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6706 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6707 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6708 Spacing)); 6709 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6710 Spacing * 2)); 6711 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6712 Spacing * 3)); 6713 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6714 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6715 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6716 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6717 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6718 TmpInst.addOperand(Inst.getOperand(5)); 6719 Inst = TmpInst; 6720 return true; 6721 } 6722 6723 // VLD4 multiple 4-element structure instructions. 6724 case ARM::VLD4dAsm_8: 6725 case ARM::VLD4dAsm_16: 6726 case ARM::VLD4dAsm_32: 6727 case ARM::VLD4qAsm_8: 6728 case ARM::VLD4qAsm_16: 6729 case ARM::VLD4qAsm_32: { 6730 MCInst TmpInst; 6731 unsigned Spacing; 6732 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6733 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6734 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6735 Spacing)); 6736 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6737 Spacing * 2)); 6738 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6739 Spacing * 3)); 6740 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6741 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6742 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6743 TmpInst.addOperand(Inst.getOperand(4)); 6744 Inst = TmpInst; 6745 return true; 6746 } 6747 6748 case ARM::VLD4dWB_fixed_Asm_8: 6749 case ARM::VLD4dWB_fixed_Asm_16: 6750 case ARM::VLD4dWB_fixed_Asm_32: 6751 case ARM::VLD4qWB_fixed_Asm_8: 6752 case ARM::VLD4qWB_fixed_Asm_16: 6753 case ARM::VLD4qWB_fixed_Asm_32: { 6754 MCInst TmpInst; 6755 unsigned Spacing; 6756 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6757 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6758 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6759 Spacing)); 6760 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6761 Spacing * 2)); 6762 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6763 Spacing * 3)); 6764 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6765 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6766 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6767 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6768 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6769 TmpInst.addOperand(Inst.getOperand(4)); 6770 Inst = TmpInst; 6771 return true; 6772 } 6773 6774 case ARM::VLD4dWB_register_Asm_8: 6775 case ARM::VLD4dWB_register_Asm_16: 6776 case ARM::VLD4dWB_register_Asm_32: 6777 case ARM::VLD4qWB_register_Asm_8: 6778 case ARM::VLD4qWB_register_Asm_16: 6779 case ARM::VLD4qWB_register_Asm_32: { 6780 MCInst TmpInst; 6781 unsigned Spacing; 6782 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6783 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6784 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6785 Spacing)); 6786 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6787 Spacing * 2)); 6788 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6789 Spacing * 3)); 6790 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6791 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6792 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6793 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6794 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6795 TmpInst.addOperand(Inst.getOperand(5)); 6796 Inst = TmpInst; 6797 return true; 6798 } 6799 6800 // VST3 multiple 3-element structure instructions. 6801 case ARM::VST3dAsm_8: 6802 case ARM::VST3dAsm_16: 6803 case ARM::VST3dAsm_32: 6804 case ARM::VST3qAsm_8: 6805 case ARM::VST3qAsm_16: 6806 case ARM::VST3qAsm_32: { 6807 MCInst TmpInst; 6808 unsigned Spacing; 6809 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6810 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6811 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6812 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6813 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6814 Spacing)); 6815 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6816 Spacing * 2)); 6817 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6818 TmpInst.addOperand(Inst.getOperand(4)); 6819 Inst = TmpInst; 6820 return true; 6821 } 6822 6823 case ARM::VST3dWB_fixed_Asm_8: 6824 case ARM::VST3dWB_fixed_Asm_16: 6825 case ARM::VST3dWB_fixed_Asm_32: 6826 case ARM::VST3qWB_fixed_Asm_8: 6827 case ARM::VST3qWB_fixed_Asm_16: 6828 case ARM::VST3qWB_fixed_Asm_32: { 6829 MCInst TmpInst; 6830 unsigned Spacing; 6831 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6832 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6833 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6834 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6835 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6836 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6837 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6838 Spacing)); 6839 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6840 Spacing * 2)); 6841 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6842 TmpInst.addOperand(Inst.getOperand(4)); 6843 Inst = TmpInst; 6844 return true; 6845 } 6846 6847 case ARM::VST3dWB_register_Asm_8: 6848 case ARM::VST3dWB_register_Asm_16: 6849 case ARM::VST3dWB_register_Asm_32: 6850 case ARM::VST3qWB_register_Asm_8: 6851 case ARM::VST3qWB_register_Asm_16: 6852 case ARM::VST3qWB_register_Asm_32: { 6853 MCInst TmpInst; 6854 unsigned Spacing; 6855 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6856 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6857 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6858 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6859 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6860 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6861 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6862 Spacing)); 6863 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6864 Spacing * 2)); 6865 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6866 TmpInst.addOperand(Inst.getOperand(5)); 6867 Inst = TmpInst; 6868 return true; 6869 } 6870 6871 // VST4 multiple 3-element structure instructions. 6872 case ARM::VST4dAsm_8: 6873 case ARM::VST4dAsm_16: 6874 case ARM::VST4dAsm_32: 6875 case ARM::VST4qAsm_8: 6876 case ARM::VST4qAsm_16: 6877 case ARM::VST4qAsm_32: { 6878 MCInst TmpInst; 6879 unsigned Spacing; 6880 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6881 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6882 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6883 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6884 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6885 Spacing)); 6886 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6887 Spacing * 2)); 6888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6889 Spacing * 3)); 6890 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6891 TmpInst.addOperand(Inst.getOperand(4)); 6892 Inst = TmpInst; 6893 return true; 6894 } 6895 6896 case ARM::VST4dWB_fixed_Asm_8: 6897 case ARM::VST4dWB_fixed_Asm_16: 6898 case ARM::VST4dWB_fixed_Asm_32: 6899 case ARM::VST4qWB_fixed_Asm_8: 6900 case ARM::VST4qWB_fixed_Asm_16: 6901 case ARM::VST4qWB_fixed_Asm_32: { 6902 MCInst TmpInst; 6903 unsigned Spacing; 6904 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6905 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6906 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6907 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6908 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6909 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6910 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6911 Spacing)); 6912 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6913 Spacing * 2)); 6914 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6915 Spacing * 3)); 6916 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6917 TmpInst.addOperand(Inst.getOperand(4)); 6918 Inst = TmpInst; 6919 return true; 6920 } 6921 6922 case ARM::VST4dWB_register_Asm_8: 6923 case ARM::VST4dWB_register_Asm_16: 6924 case ARM::VST4dWB_register_Asm_32: 6925 case ARM::VST4qWB_register_Asm_8: 6926 case ARM::VST4qWB_register_Asm_16: 6927 case ARM::VST4qWB_register_Asm_32: { 6928 MCInst TmpInst; 6929 unsigned Spacing; 6930 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6931 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6932 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6933 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6934 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6935 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6936 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6937 Spacing)); 6938 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6939 Spacing * 2)); 6940 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6941 Spacing * 3)); 6942 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6943 TmpInst.addOperand(Inst.getOperand(5)); 6944 Inst = TmpInst; 6945 return true; 6946 } 6947 6948 // Handle encoding choice for the shift-immediate instructions. 6949 case ARM::t2LSLri: 6950 case ARM::t2LSRri: 6951 case ARM::t2ASRri: { 6952 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6953 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6954 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 6955 !(static_cast<ARMOperand*>(Operands[3])->isToken() && 6956 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 6957 unsigned NewOpc; 6958 switch (Inst.getOpcode()) { 6959 default: llvm_unreachable("unexpected opcode"); 6960 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6961 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6962 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6963 } 6964 // The Thumb1 operands aren't in the same order. Awesome, eh? 6965 MCInst TmpInst; 6966 TmpInst.setOpcode(NewOpc); 6967 TmpInst.addOperand(Inst.getOperand(0)); 6968 TmpInst.addOperand(Inst.getOperand(5)); 6969 TmpInst.addOperand(Inst.getOperand(1)); 6970 TmpInst.addOperand(Inst.getOperand(2)); 6971 TmpInst.addOperand(Inst.getOperand(3)); 6972 TmpInst.addOperand(Inst.getOperand(4)); 6973 Inst = TmpInst; 6974 return true; 6975 } 6976 return false; 6977 } 6978 6979 // Handle the Thumb2 mode MOV complex aliases. 6980 case ARM::t2MOVsr: 6981 case ARM::t2MOVSsr: { 6982 // Which instruction to expand to depends on the CCOut operand and 6983 // whether we're in an IT block if the register operands are low 6984 // registers. 6985 bool isNarrow = false; 6986 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6987 isARMLowRegister(Inst.getOperand(1).getReg()) && 6988 isARMLowRegister(Inst.getOperand(2).getReg()) && 6989 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6990 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 6991 isNarrow = true; 6992 MCInst TmpInst; 6993 unsigned newOpc; 6994 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 6995 default: llvm_unreachable("unexpected opcode!"); 6996 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 6997 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 6998 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 6999 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 7000 } 7001 TmpInst.setOpcode(newOpc); 7002 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7003 if (isNarrow) 7004 TmpInst.addOperand(MCOperand::CreateReg( 7005 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7006 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7007 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7008 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7009 TmpInst.addOperand(Inst.getOperand(5)); 7010 if (!isNarrow) 7011 TmpInst.addOperand(MCOperand::CreateReg( 7012 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7013 Inst = TmpInst; 7014 return true; 7015 } 7016 case ARM::t2MOVsi: 7017 case ARM::t2MOVSsi: { 7018 // Which instruction to expand to depends on the CCOut operand and 7019 // whether we're in an IT block if the register operands are low 7020 // registers. 7021 bool isNarrow = false; 7022 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7023 isARMLowRegister(Inst.getOperand(1).getReg()) && 7024 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 7025 isNarrow = true; 7026 MCInst TmpInst; 7027 unsigned newOpc; 7028 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 7029 default: llvm_unreachable("unexpected opcode!"); 7030 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 7031 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 7032 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 7033 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 7034 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 7035 } 7036 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 7037 if (Amount == 32) Amount = 0; 7038 TmpInst.setOpcode(newOpc); 7039 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7040 if (isNarrow) 7041 TmpInst.addOperand(MCOperand::CreateReg( 7042 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7043 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7044 if (newOpc != ARM::t2RRX) 7045 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 7046 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7047 TmpInst.addOperand(Inst.getOperand(4)); 7048 if (!isNarrow) 7049 TmpInst.addOperand(MCOperand::CreateReg( 7050 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7051 Inst = TmpInst; 7052 return true; 7053 } 7054 // Handle the ARM mode MOV complex aliases. 7055 case ARM::ASRr: 7056 case ARM::LSRr: 7057 case ARM::LSLr: 7058 case ARM::RORr: { 7059 ARM_AM::ShiftOpc ShiftTy; 7060 switch(Inst.getOpcode()) { 7061 default: llvm_unreachable("unexpected opcode!"); 7062 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 7063 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 7064 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 7065 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 7066 } 7067 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 7068 MCInst TmpInst; 7069 TmpInst.setOpcode(ARM::MOVsr); 7070 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7071 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7072 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7073 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7074 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7075 TmpInst.addOperand(Inst.getOperand(4)); 7076 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7077 Inst = TmpInst; 7078 return true; 7079 } 7080 case ARM::ASRi: 7081 case ARM::LSRi: 7082 case ARM::LSLi: 7083 case ARM::RORi: { 7084 ARM_AM::ShiftOpc ShiftTy; 7085 switch(Inst.getOpcode()) { 7086 default: llvm_unreachable("unexpected opcode!"); 7087 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 7088 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 7089 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 7090 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 7091 } 7092 // A shift by zero is a plain MOVr, not a MOVsi. 7093 unsigned Amt = Inst.getOperand(2).getImm(); 7094 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 7095 // A shift by 32 should be encoded as 0 when permitted 7096 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 7097 Amt = 0; 7098 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 7099 MCInst TmpInst; 7100 TmpInst.setOpcode(Opc); 7101 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7102 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7103 if (Opc == ARM::MOVsi) 7104 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7105 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7106 TmpInst.addOperand(Inst.getOperand(4)); 7107 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7108 Inst = TmpInst; 7109 return true; 7110 } 7111 case ARM::RRXi: { 7112 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 7113 MCInst TmpInst; 7114 TmpInst.setOpcode(ARM::MOVsi); 7115 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7116 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7117 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7118 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7119 TmpInst.addOperand(Inst.getOperand(3)); 7120 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 7121 Inst = TmpInst; 7122 return true; 7123 } 7124 case ARM::t2LDMIA_UPD: { 7125 // If this is a load of a single register, then we should use 7126 // a post-indexed LDR instruction instead, per the ARM ARM. 7127 if (Inst.getNumOperands() != 5) 7128 return false; 7129 MCInst TmpInst; 7130 TmpInst.setOpcode(ARM::t2LDR_POST); 7131 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7132 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7133 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7134 TmpInst.addOperand(MCOperand::CreateImm(4)); 7135 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7136 TmpInst.addOperand(Inst.getOperand(3)); 7137 Inst = TmpInst; 7138 return true; 7139 } 7140 case ARM::t2STMDB_UPD: { 7141 // If this is a store of a single register, then we should use 7142 // a pre-indexed STR instruction instead, per the ARM ARM. 7143 if (Inst.getNumOperands() != 5) 7144 return false; 7145 MCInst TmpInst; 7146 TmpInst.setOpcode(ARM::t2STR_PRE); 7147 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7148 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7149 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7150 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7151 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7152 TmpInst.addOperand(Inst.getOperand(3)); 7153 Inst = TmpInst; 7154 return true; 7155 } 7156 case ARM::LDMIA_UPD: 7157 // If this is a load of a single register via a 'pop', then we should use 7158 // a post-indexed LDR instruction instead, per the ARM ARM. 7159 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 7160 Inst.getNumOperands() == 5) { 7161 MCInst TmpInst; 7162 TmpInst.setOpcode(ARM::LDR_POST_IMM); 7163 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7164 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7165 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7166 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 7167 TmpInst.addOperand(MCOperand::CreateImm(4)); 7168 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7169 TmpInst.addOperand(Inst.getOperand(3)); 7170 Inst = TmpInst; 7171 return true; 7172 } 7173 break; 7174 case ARM::STMDB_UPD: 7175 // If this is a store of a single register via a 'push', then we should use 7176 // a pre-indexed STR instruction instead, per the ARM ARM. 7177 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 7178 Inst.getNumOperands() == 5) { 7179 MCInst TmpInst; 7180 TmpInst.setOpcode(ARM::STR_PRE_IMM); 7181 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7182 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7183 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 7184 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7185 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7186 TmpInst.addOperand(Inst.getOperand(3)); 7187 Inst = TmpInst; 7188 } 7189 break; 7190 case ARM::t2ADDri12: 7191 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 7192 // mnemonic was used (not "addw"), encoding T3 is preferred. 7193 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 7194 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7195 break; 7196 Inst.setOpcode(ARM::t2ADDri); 7197 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7198 break; 7199 case ARM::t2SUBri12: 7200 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 7201 // mnemonic was used (not "subw"), encoding T3 is preferred. 7202 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 7203 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7204 break; 7205 Inst.setOpcode(ARM::t2SUBri); 7206 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7207 break; 7208 case ARM::tADDi8: 7209 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7210 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7211 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7212 // to encoding T1 if <Rd> is omitted." 7213 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7214 Inst.setOpcode(ARM::tADDi3); 7215 return true; 7216 } 7217 break; 7218 case ARM::tSUBi8: 7219 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7220 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7221 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7222 // to encoding T1 if <Rd> is omitted." 7223 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7224 Inst.setOpcode(ARM::tSUBi3); 7225 return true; 7226 } 7227 break; 7228 case ARM::t2ADDri: 7229 case ARM::t2SUBri: { 7230 // If the destination and first source operand are the same, and 7231 // the flags are compatible with the current IT status, use encoding T2 7232 // instead of T3. For compatibility with the system 'as'. Make sure the 7233 // wide encoding wasn't explicit. 7234 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7235 !isARMLowRegister(Inst.getOperand(0).getReg()) || 7236 (unsigned)Inst.getOperand(2).getImm() > 255 || 7237 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 7238 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 7239 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7240 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7241 break; 7242 MCInst TmpInst; 7243 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7244 ARM::tADDi8 : ARM::tSUBi8); 7245 TmpInst.addOperand(Inst.getOperand(0)); 7246 TmpInst.addOperand(Inst.getOperand(5)); 7247 TmpInst.addOperand(Inst.getOperand(0)); 7248 TmpInst.addOperand(Inst.getOperand(2)); 7249 TmpInst.addOperand(Inst.getOperand(3)); 7250 TmpInst.addOperand(Inst.getOperand(4)); 7251 Inst = TmpInst; 7252 return true; 7253 } 7254 case ARM::t2ADDrr: { 7255 // If the destination and first source operand are the same, and 7256 // there's no setting of the flags, use encoding T2 instead of T3. 7257 // Note that this is only for ADD, not SUB. This mirrors the system 7258 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7259 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7260 Inst.getOperand(5).getReg() != 0 || 7261 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7262 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7263 break; 7264 MCInst TmpInst; 7265 TmpInst.setOpcode(ARM::tADDhirr); 7266 TmpInst.addOperand(Inst.getOperand(0)); 7267 TmpInst.addOperand(Inst.getOperand(0)); 7268 TmpInst.addOperand(Inst.getOperand(2)); 7269 TmpInst.addOperand(Inst.getOperand(3)); 7270 TmpInst.addOperand(Inst.getOperand(4)); 7271 Inst = TmpInst; 7272 return true; 7273 } 7274 case ARM::tADDrSP: { 7275 // If the non-SP source operand and the destination operand are not the 7276 // same, we need to use the 32-bit encoding if it's available. 7277 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7278 Inst.setOpcode(ARM::t2ADDrr); 7279 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7280 return true; 7281 } 7282 break; 7283 } 7284 case ARM::tB: 7285 // A Thumb conditional branch outside of an IT block is a tBcc. 7286 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7287 Inst.setOpcode(ARM::tBcc); 7288 return true; 7289 } 7290 break; 7291 case ARM::t2B: 7292 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7293 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7294 Inst.setOpcode(ARM::t2Bcc); 7295 return true; 7296 } 7297 break; 7298 case ARM::t2Bcc: 7299 // If the conditional is AL or we're in an IT block, we really want t2B. 7300 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7301 Inst.setOpcode(ARM::t2B); 7302 return true; 7303 } 7304 break; 7305 case ARM::tBcc: 7306 // If the conditional is AL, we really want tB. 7307 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7308 Inst.setOpcode(ARM::tB); 7309 return true; 7310 } 7311 break; 7312 case ARM::tLDMIA: { 7313 // If the register list contains any high registers, or if the writeback 7314 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7315 // instead if we're in Thumb2. Otherwise, this should have generated 7316 // an error in validateInstruction(). 7317 unsigned Rn = Inst.getOperand(0).getReg(); 7318 bool hasWritebackToken = 7319 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7320 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 7321 bool listContainsBase; 7322 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7323 (!listContainsBase && !hasWritebackToken) || 7324 (listContainsBase && hasWritebackToken)) { 7325 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7326 assert (isThumbTwo()); 7327 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7328 // If we're switching to the updating version, we need to insert 7329 // the writeback tied operand. 7330 if (hasWritebackToken) 7331 Inst.insert(Inst.begin(), 7332 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7333 return true; 7334 } 7335 break; 7336 } 7337 case ARM::tSTMIA_UPD: { 7338 // If the register list contains any high registers, we need to use 7339 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7340 // should have generated an error in validateInstruction(). 7341 unsigned Rn = Inst.getOperand(0).getReg(); 7342 bool listContainsBase; 7343 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7344 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7345 assert (isThumbTwo()); 7346 Inst.setOpcode(ARM::t2STMIA_UPD); 7347 return true; 7348 } 7349 break; 7350 } 7351 case ARM::tPOP: { 7352 bool listContainsBase; 7353 // If the register list contains any high registers, we need to use 7354 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7355 // should have generated an error in validateInstruction(). 7356 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7357 return false; 7358 assert (isThumbTwo()); 7359 Inst.setOpcode(ARM::t2LDMIA_UPD); 7360 // Add the base register and writeback operands. 7361 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7362 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7363 return true; 7364 } 7365 case ARM::tPUSH: { 7366 bool listContainsBase; 7367 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7368 return false; 7369 assert (isThumbTwo()); 7370 Inst.setOpcode(ARM::t2STMDB_UPD); 7371 // Add the base register and writeback operands. 7372 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7373 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7374 return true; 7375 } 7376 case ARM::t2MOVi: { 7377 // If we can use the 16-bit encoding and the user didn't explicitly 7378 // request the 32-bit variant, transform it here. 7379 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7380 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7381 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7382 Inst.getOperand(4).getReg() == ARM::CPSR) || 7383 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7384 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7385 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7386 // The operands aren't in the same order for tMOVi8... 7387 MCInst TmpInst; 7388 TmpInst.setOpcode(ARM::tMOVi8); 7389 TmpInst.addOperand(Inst.getOperand(0)); 7390 TmpInst.addOperand(Inst.getOperand(4)); 7391 TmpInst.addOperand(Inst.getOperand(1)); 7392 TmpInst.addOperand(Inst.getOperand(2)); 7393 TmpInst.addOperand(Inst.getOperand(3)); 7394 Inst = TmpInst; 7395 return true; 7396 } 7397 break; 7398 } 7399 case ARM::t2MOVr: { 7400 // If we can use the 16-bit encoding and the user didn't explicitly 7401 // request the 32-bit variant, transform it here. 7402 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7403 isARMLowRegister(Inst.getOperand(1).getReg()) && 7404 Inst.getOperand(2).getImm() == ARMCC::AL && 7405 Inst.getOperand(4).getReg() == ARM::CPSR && 7406 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7407 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7408 // The operands aren't the same for tMOV[S]r... (no cc_out) 7409 MCInst TmpInst; 7410 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 7411 TmpInst.addOperand(Inst.getOperand(0)); 7412 TmpInst.addOperand(Inst.getOperand(1)); 7413 TmpInst.addOperand(Inst.getOperand(2)); 7414 TmpInst.addOperand(Inst.getOperand(3)); 7415 Inst = TmpInst; 7416 return true; 7417 } 7418 break; 7419 } 7420 case ARM::t2SXTH: 7421 case ARM::t2SXTB: 7422 case ARM::t2UXTH: 7423 case ARM::t2UXTB: { 7424 // If we can use the 16-bit encoding and the user didn't explicitly 7425 // request the 32-bit variant, transform it here. 7426 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7427 isARMLowRegister(Inst.getOperand(1).getReg()) && 7428 Inst.getOperand(2).getImm() == 0 && 7429 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7430 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7431 unsigned NewOpc; 7432 switch (Inst.getOpcode()) { 7433 default: llvm_unreachable("Illegal opcode!"); 7434 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7435 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7436 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7437 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 7438 } 7439 // The operands aren't the same for thumb1 (no rotate operand). 7440 MCInst TmpInst; 7441 TmpInst.setOpcode(NewOpc); 7442 TmpInst.addOperand(Inst.getOperand(0)); 7443 TmpInst.addOperand(Inst.getOperand(1)); 7444 TmpInst.addOperand(Inst.getOperand(3)); 7445 TmpInst.addOperand(Inst.getOperand(4)); 7446 Inst = TmpInst; 7447 return true; 7448 } 7449 break; 7450 } 7451 case ARM::MOVsi: { 7452 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7453 // rrx shifts and asr/lsr of #32 is encoded as 0 7454 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7455 return false; 7456 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 7457 // Shifting by zero is accepted as a vanilla 'MOVr' 7458 MCInst TmpInst; 7459 TmpInst.setOpcode(ARM::MOVr); 7460 TmpInst.addOperand(Inst.getOperand(0)); 7461 TmpInst.addOperand(Inst.getOperand(1)); 7462 TmpInst.addOperand(Inst.getOperand(3)); 7463 TmpInst.addOperand(Inst.getOperand(4)); 7464 TmpInst.addOperand(Inst.getOperand(5)); 7465 Inst = TmpInst; 7466 return true; 7467 } 7468 return false; 7469 } 7470 case ARM::ANDrsi: 7471 case ARM::ORRrsi: 7472 case ARM::EORrsi: 7473 case ARM::BICrsi: 7474 case ARM::SUBrsi: 7475 case ARM::ADDrsi: { 7476 unsigned newOpc; 7477 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 7478 if (SOpc == ARM_AM::rrx) return false; 7479 switch (Inst.getOpcode()) { 7480 default: llvm_unreachable("unexpected opcode!"); 7481 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 7482 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 7483 case ARM::EORrsi: newOpc = ARM::EORrr; break; 7484 case ARM::BICrsi: newOpc = ARM::BICrr; break; 7485 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 7486 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 7487 } 7488 // If the shift is by zero, use the non-shifted instruction definition. 7489 // The exception is for right shifts, where 0 == 32 7490 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 7491 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 7492 MCInst TmpInst; 7493 TmpInst.setOpcode(newOpc); 7494 TmpInst.addOperand(Inst.getOperand(0)); 7495 TmpInst.addOperand(Inst.getOperand(1)); 7496 TmpInst.addOperand(Inst.getOperand(2)); 7497 TmpInst.addOperand(Inst.getOperand(4)); 7498 TmpInst.addOperand(Inst.getOperand(5)); 7499 TmpInst.addOperand(Inst.getOperand(6)); 7500 Inst = TmpInst; 7501 return true; 7502 } 7503 return false; 7504 } 7505 case ARM::ITasm: 7506 case ARM::t2IT: { 7507 // The mask bits for all but the first condition are represented as 7508 // the low bit of the condition code value implies 't'. We currently 7509 // always have 1 implies 't', so XOR toggle the bits if the low bit 7510 // of the condition code is zero. 7511 MCOperand &MO = Inst.getOperand(1); 7512 unsigned Mask = MO.getImm(); 7513 unsigned OrigMask = Mask; 7514 unsigned TZ = countTrailingZeros(Mask); 7515 if ((Inst.getOperand(0).getImm() & 1) == 0) { 7516 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 7517 Mask ^= (0xE << TZ) & 0xF; 7518 } 7519 MO.setImm(Mask); 7520 7521 // Set up the IT block state according to the IT instruction we just 7522 // matched. 7523 assert(!inITBlock() && "nested IT blocks?!"); 7524 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7525 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7526 ITState.CurPosition = 0; 7527 ITState.FirstCond = true; 7528 break; 7529 } 7530 case ARM::t2LSLrr: 7531 case ARM::t2LSRrr: 7532 case ARM::t2ASRrr: 7533 case ARM::t2SBCrr: 7534 case ARM::t2RORrr: 7535 case ARM::t2BICrr: 7536 { 7537 // Assemblers should use the narrow encodings of these instructions when permissible. 7538 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7539 isARMLowRegister(Inst.getOperand(2).getReg())) && 7540 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7541 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7542 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7543 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7544 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7545 unsigned NewOpc; 7546 switch (Inst.getOpcode()) { 7547 default: llvm_unreachable("unexpected opcode"); 7548 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 7549 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 7550 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 7551 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 7552 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 7553 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 7554 } 7555 MCInst TmpInst; 7556 TmpInst.setOpcode(NewOpc); 7557 TmpInst.addOperand(Inst.getOperand(0)); 7558 TmpInst.addOperand(Inst.getOperand(5)); 7559 TmpInst.addOperand(Inst.getOperand(1)); 7560 TmpInst.addOperand(Inst.getOperand(2)); 7561 TmpInst.addOperand(Inst.getOperand(3)); 7562 TmpInst.addOperand(Inst.getOperand(4)); 7563 Inst = TmpInst; 7564 return true; 7565 } 7566 return false; 7567 } 7568 case ARM::t2ANDrr: 7569 case ARM::t2EORrr: 7570 case ARM::t2ADCrr: 7571 case ARM::t2ORRrr: 7572 { 7573 // Assemblers should use the narrow encodings of these instructions when permissible. 7574 // These instructions are special in that they are commutable, so shorter encodings 7575 // are available more often. 7576 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7577 isARMLowRegister(Inst.getOperand(2).getReg())) && 7578 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 7579 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 7580 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7581 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7582 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7583 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7584 unsigned NewOpc; 7585 switch (Inst.getOpcode()) { 7586 default: llvm_unreachable("unexpected opcode"); 7587 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 7588 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 7589 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 7590 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 7591 } 7592 MCInst TmpInst; 7593 TmpInst.setOpcode(NewOpc); 7594 TmpInst.addOperand(Inst.getOperand(0)); 7595 TmpInst.addOperand(Inst.getOperand(5)); 7596 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 7597 TmpInst.addOperand(Inst.getOperand(1)); 7598 TmpInst.addOperand(Inst.getOperand(2)); 7599 } else { 7600 TmpInst.addOperand(Inst.getOperand(2)); 7601 TmpInst.addOperand(Inst.getOperand(1)); 7602 } 7603 TmpInst.addOperand(Inst.getOperand(3)); 7604 TmpInst.addOperand(Inst.getOperand(4)); 7605 Inst = TmpInst; 7606 return true; 7607 } 7608 return false; 7609 } 7610 } 7611 return false; 7612 } 7613 7614 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 7615 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 7616 // suffix depending on whether they're in an IT block or not. 7617 unsigned Opc = Inst.getOpcode(); 7618 const MCInstrDesc &MCID = getInstDesc(Opc); 7619 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 7620 assert(MCID.hasOptionalDef() && 7621 "optionally flag setting instruction missing optional def operand"); 7622 assert(MCID.NumOperands == Inst.getNumOperands() && 7623 "operand count mismatch!"); 7624 // Find the optional-def operand (cc_out). 7625 unsigned OpNo; 7626 for (OpNo = 0; 7627 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 7628 ++OpNo) 7629 ; 7630 // If we're parsing Thumb1, reject it completely. 7631 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 7632 return Match_MnemonicFail; 7633 // If we're parsing Thumb2, which form is legal depends on whether we're 7634 // in an IT block. 7635 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7636 !inITBlock()) 7637 return Match_RequiresITBlock; 7638 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7639 inITBlock()) 7640 return Match_RequiresNotITBlock; 7641 } 7642 // Some high-register supporting Thumb1 encodings only allow both registers 7643 // to be from r0-r7 when in Thumb2. 7644 else if (Opc == ARM::tADDhirr && isThumbOne() && 7645 isARMLowRegister(Inst.getOperand(1).getReg()) && 7646 isARMLowRegister(Inst.getOperand(2).getReg())) 7647 return Match_RequiresThumb2; 7648 // Others only require ARMv6 or later. 7649 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7650 isARMLowRegister(Inst.getOperand(0).getReg()) && 7651 isARMLowRegister(Inst.getOperand(1).getReg())) 7652 return Match_RequiresV6; 7653 return Match_Success; 7654 } 7655 7656 static const char *getSubtargetFeatureName(unsigned Val); 7657 bool ARMAsmParser:: 7658 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 7659 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7660 MCStreamer &Out, unsigned &ErrorInfo, 7661 bool MatchingInlineAsm) { 7662 MCInst Inst; 7663 unsigned MatchResult; 7664 7665 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 7666 MatchingInlineAsm); 7667 switch (MatchResult) { 7668 default: break; 7669 case Match_Success: 7670 // Context sensitive operand constraints aren't handled by the matcher, 7671 // so check them here. 7672 if (validateInstruction(Inst, Operands)) { 7673 // Still progress the IT block, otherwise one wrong condition causes 7674 // nasty cascading errors. 7675 forwardITPosition(); 7676 return true; 7677 } 7678 7679 // Some instructions need post-processing to, for example, tweak which 7680 // encoding is selected. Loop on it while changes happen so the 7681 // individual transformations can chain off each other. E.g., 7682 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 7683 while (processInstruction(Inst, Operands)) 7684 ; 7685 7686 // Only move forward at the very end so that everything in validate 7687 // and process gets a consistent answer about whether we're in an IT 7688 // block. 7689 forwardITPosition(); 7690 7691 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 7692 // doesn't actually encode. 7693 if (Inst.getOpcode() == ARM::ITasm) 7694 return false; 7695 7696 Inst.setLoc(IDLoc); 7697 Out.EmitInstruction(Inst); 7698 return false; 7699 case Match_MissingFeature: { 7700 assert(ErrorInfo && "Unknown missing feature!"); 7701 // Special case the error message for the very common case where only 7702 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 7703 std::string Msg = "instruction requires:"; 7704 unsigned Mask = 1; 7705 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 7706 if (ErrorInfo & Mask) { 7707 Msg += " "; 7708 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 7709 } 7710 Mask <<= 1; 7711 } 7712 return Error(IDLoc, Msg); 7713 } 7714 case Match_InvalidOperand: { 7715 SMLoc ErrorLoc = IDLoc; 7716 if (ErrorInfo != ~0U) { 7717 if (ErrorInfo >= Operands.size()) 7718 return Error(IDLoc, "too few operands for instruction"); 7719 7720 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7721 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7722 } 7723 7724 return Error(ErrorLoc, "invalid operand for instruction"); 7725 } 7726 case Match_MnemonicFail: 7727 return Error(IDLoc, "invalid instruction", 7728 ((ARMOperand*)Operands[0])->getLocRange()); 7729 case Match_RequiresNotITBlock: 7730 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 7731 case Match_RequiresITBlock: 7732 return Error(IDLoc, "instruction only valid inside IT block"); 7733 case Match_RequiresV6: 7734 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7735 case Match_RequiresThumb2: 7736 return Error(IDLoc, "instruction variant requires Thumb2"); 7737 case Match_ImmRange0_4: { 7738 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7739 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7740 return Error(ErrorLoc, "immediate operand must be in the range [0,4]"); 7741 } 7742 case Match_ImmRange0_15: { 7743 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7744 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7745 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 7746 } 7747 } 7748 7749 llvm_unreachable("Implement any new match types added!"); 7750 } 7751 7752 /// parseDirective parses the arm specific directives 7753 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7754 StringRef IDVal = DirectiveID.getIdentifier(); 7755 if (IDVal == ".word") 7756 return parseDirectiveWord(4, DirectiveID.getLoc()); 7757 else if (IDVal == ".thumb") 7758 return parseDirectiveThumb(DirectiveID.getLoc()); 7759 else if (IDVal == ".arm") 7760 return parseDirectiveARM(DirectiveID.getLoc()); 7761 else if (IDVal == ".thumb_func") 7762 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7763 else if (IDVal == ".code") 7764 return parseDirectiveCode(DirectiveID.getLoc()); 7765 else if (IDVal == ".syntax") 7766 return parseDirectiveSyntax(DirectiveID.getLoc()); 7767 else if (IDVal == ".unreq") 7768 return parseDirectiveUnreq(DirectiveID.getLoc()); 7769 else if (IDVal == ".arch") 7770 return parseDirectiveArch(DirectiveID.getLoc()); 7771 else if (IDVal == ".eabi_attribute") 7772 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7773 else if (IDVal == ".fnstart") 7774 return parseDirectiveFnStart(DirectiveID.getLoc()); 7775 else if (IDVal == ".fnend") 7776 return parseDirectiveFnEnd(DirectiveID.getLoc()); 7777 else if (IDVal == ".cantunwind") 7778 return parseDirectiveCantUnwind(DirectiveID.getLoc()); 7779 else if (IDVal == ".personality") 7780 return parseDirectivePersonality(DirectiveID.getLoc()); 7781 else if (IDVal == ".handlerdata") 7782 return parseDirectiveHandlerData(DirectiveID.getLoc()); 7783 else if (IDVal == ".setfp") 7784 return parseDirectiveSetFP(DirectiveID.getLoc()); 7785 else if (IDVal == ".pad") 7786 return parseDirectivePad(DirectiveID.getLoc()); 7787 else if (IDVal == ".save") 7788 return parseDirectiveRegSave(DirectiveID.getLoc(), false); 7789 else if (IDVal == ".vsave") 7790 return parseDirectiveRegSave(DirectiveID.getLoc(), true); 7791 return true; 7792 } 7793 7794 /// parseDirectiveWord 7795 /// ::= .word [ expression (, expression)* ] 7796 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 7797 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7798 for (;;) { 7799 const MCExpr *Value; 7800 if (getParser().parseExpression(Value)) 7801 return true; 7802 7803 getParser().getStreamer().EmitValue(Value, Size); 7804 7805 if (getLexer().is(AsmToken::EndOfStatement)) 7806 break; 7807 7808 // FIXME: Improve diagnostic. 7809 if (getLexer().isNot(AsmToken::Comma)) 7810 return Error(L, "unexpected token in directive"); 7811 Parser.Lex(); 7812 } 7813 } 7814 7815 Parser.Lex(); 7816 return false; 7817 } 7818 7819 /// parseDirectiveThumb 7820 /// ::= .thumb 7821 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 7822 if (getLexer().isNot(AsmToken::EndOfStatement)) 7823 return Error(L, "unexpected token in directive"); 7824 Parser.Lex(); 7825 7826 if (!hasThumb()) 7827 return Error(L, "target does not support Thumb mode"); 7828 7829 if (!isThumb()) 7830 SwitchMode(); 7831 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7832 return false; 7833 } 7834 7835 /// parseDirectiveARM 7836 /// ::= .arm 7837 bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 7838 if (getLexer().isNot(AsmToken::EndOfStatement)) 7839 return Error(L, "unexpected token in directive"); 7840 Parser.Lex(); 7841 7842 if (!hasARM()) 7843 return Error(L, "target does not support ARM mode"); 7844 7845 if (isThumb()) 7846 SwitchMode(); 7847 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7848 return false; 7849 } 7850 7851 /// parseDirectiveThumbFunc 7852 /// ::= .thumbfunc symbol_name 7853 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 7854 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 7855 bool isMachO = MAI.hasSubsectionsViaSymbols(); 7856 StringRef Name; 7857 bool needFuncName = true; 7858 7859 // Darwin asm has (optionally) function name after .thumb_func direction 7860 // ELF doesn't 7861 if (isMachO) { 7862 const AsmToken &Tok = Parser.getTok(); 7863 if (Tok.isNot(AsmToken::EndOfStatement)) { 7864 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 7865 return Error(L, "unexpected token in .thumb_func directive"); 7866 Name = Tok.getIdentifier(); 7867 Parser.Lex(); // Consume the identifier token. 7868 needFuncName = false; 7869 } 7870 } 7871 7872 if (getLexer().isNot(AsmToken::EndOfStatement)) 7873 return Error(L, "unexpected token in directive"); 7874 7875 // Eat the end of statement and any blank lines that follow. 7876 while (getLexer().is(AsmToken::EndOfStatement)) 7877 Parser.Lex(); 7878 7879 // FIXME: assuming function name will be the line following .thumb_func 7880 // We really should be checking the next symbol definition even if there's 7881 // stuff in between. 7882 if (needFuncName) { 7883 Name = Parser.getTok().getIdentifier(); 7884 } 7885 7886 // Mark symbol as a thumb symbol. 7887 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 7888 getParser().getStreamer().EmitThumbFunc(Func); 7889 return false; 7890 } 7891 7892 /// parseDirectiveSyntax 7893 /// ::= .syntax unified | divided 7894 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 7895 const AsmToken &Tok = Parser.getTok(); 7896 if (Tok.isNot(AsmToken::Identifier)) 7897 return Error(L, "unexpected token in .syntax directive"); 7898 StringRef Mode = Tok.getString(); 7899 if (Mode == "unified" || Mode == "UNIFIED") 7900 Parser.Lex(); 7901 else if (Mode == "divided" || Mode == "DIVIDED") 7902 return Error(L, "'.syntax divided' arm asssembly not supported"); 7903 else 7904 return Error(L, "unrecognized syntax mode in .syntax directive"); 7905 7906 if (getLexer().isNot(AsmToken::EndOfStatement)) 7907 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7908 Parser.Lex(); 7909 7910 // TODO tell the MC streamer the mode 7911 // getParser().getStreamer().Emit???(); 7912 return false; 7913 } 7914 7915 /// parseDirectiveCode 7916 /// ::= .code 16 | 32 7917 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 7918 const AsmToken &Tok = Parser.getTok(); 7919 if (Tok.isNot(AsmToken::Integer)) 7920 return Error(L, "unexpected token in .code directive"); 7921 int64_t Val = Parser.getTok().getIntVal(); 7922 if (Val == 16) 7923 Parser.Lex(); 7924 else if (Val == 32) 7925 Parser.Lex(); 7926 else 7927 return Error(L, "invalid operand to .code directive"); 7928 7929 if (getLexer().isNot(AsmToken::EndOfStatement)) 7930 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7931 Parser.Lex(); 7932 7933 if (Val == 16) { 7934 if (!hasThumb()) 7935 return Error(L, "target does not support Thumb mode"); 7936 7937 if (!isThumb()) 7938 SwitchMode(); 7939 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7940 } else { 7941 if (!hasARM()) 7942 return Error(L, "target does not support ARM mode"); 7943 7944 if (isThumb()) 7945 SwitchMode(); 7946 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7947 } 7948 7949 return false; 7950 } 7951 7952 /// parseDirectiveReq 7953 /// ::= name .req registername 7954 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 7955 Parser.Lex(); // Eat the '.req' token. 7956 unsigned Reg; 7957 SMLoc SRegLoc, ERegLoc; 7958 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 7959 Parser.eatToEndOfStatement(); 7960 return Error(SRegLoc, "register name expected"); 7961 } 7962 7963 // Shouldn't be anything else. 7964 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7965 Parser.eatToEndOfStatement(); 7966 return Error(Parser.getTok().getLoc(), 7967 "unexpected input in .req directive."); 7968 } 7969 7970 Parser.Lex(); // Consume the EndOfStatement 7971 7972 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 7973 return Error(SRegLoc, "redefinition of '" + Name + 7974 "' does not match original."); 7975 7976 return false; 7977 } 7978 7979 /// parseDirectiveUneq 7980 /// ::= .unreq registername 7981 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 7982 if (Parser.getTok().isNot(AsmToken::Identifier)) { 7983 Parser.eatToEndOfStatement(); 7984 return Error(L, "unexpected input in .unreq directive."); 7985 } 7986 RegisterReqs.erase(Parser.getTok().getIdentifier()); 7987 Parser.Lex(); // Eat the identifier. 7988 return false; 7989 } 7990 7991 /// parseDirectiveArch 7992 /// ::= .arch token 7993 bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 7994 return true; 7995 } 7996 7997 /// parseDirectiveEabiAttr 7998 /// ::= .eabi_attribute int, int 7999 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 8000 return true; 8001 } 8002 8003 /// parseDirectiveFnStart 8004 /// ::= .fnstart 8005 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { 8006 if (FnStartLoc.isValid()) { 8007 Error(L, ".fnstart starts before the end of previous one"); 8008 Error(FnStartLoc, "previous .fnstart starts here"); 8009 return true; 8010 } 8011 8012 FnStartLoc = L; 8013 getParser().getStreamer().EmitFnStart(); 8014 return false; 8015 } 8016 8017 /// parseDirectiveFnEnd 8018 /// ::= .fnend 8019 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { 8020 // Check the ordering of unwind directives 8021 if (!FnStartLoc.isValid()) 8022 return Error(L, ".fnstart must precede .fnend directive"); 8023 8024 // Reset the unwind directives parser state 8025 resetUnwindDirectiveParserState(); 8026 8027 getParser().getStreamer().EmitFnEnd(); 8028 return false; 8029 } 8030 8031 /// parseDirectiveCantUnwind 8032 /// ::= .cantunwind 8033 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { 8034 // Check the ordering of unwind directives 8035 CantUnwindLoc = L; 8036 if (!FnStartLoc.isValid()) 8037 return Error(L, ".fnstart must precede .cantunwind directive"); 8038 if (HandlerDataLoc.isValid()) { 8039 Error(L, ".cantunwind can't be used with .handlerdata directive"); 8040 Error(HandlerDataLoc, ".handlerdata was specified here"); 8041 return true; 8042 } 8043 if (PersonalityLoc.isValid()) { 8044 Error(L, ".cantunwind can't be used with .personality directive"); 8045 Error(PersonalityLoc, ".personality was specified here"); 8046 return true; 8047 } 8048 8049 getParser().getStreamer().EmitCantUnwind(); 8050 return false; 8051 } 8052 8053 /// parseDirectivePersonality 8054 /// ::= .personality name 8055 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { 8056 // Check the ordering of unwind directives 8057 PersonalityLoc = L; 8058 if (!FnStartLoc.isValid()) 8059 return Error(L, ".fnstart must precede .personality directive"); 8060 if (CantUnwindLoc.isValid()) { 8061 Error(L, ".personality can't be used with .cantunwind directive"); 8062 Error(CantUnwindLoc, ".cantunwind was specified here"); 8063 return true; 8064 } 8065 if (HandlerDataLoc.isValid()) { 8066 Error(L, ".personality must precede .handlerdata directive"); 8067 Error(HandlerDataLoc, ".handlerdata was specified here"); 8068 return true; 8069 } 8070 8071 // Parse the name of the personality routine 8072 if (Parser.getTok().isNot(AsmToken::Identifier)) { 8073 Parser.eatToEndOfStatement(); 8074 return Error(L, "unexpected input in .personality directive."); 8075 } 8076 StringRef Name(Parser.getTok().getIdentifier()); 8077 Parser.Lex(); 8078 8079 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name); 8080 getParser().getStreamer().EmitPersonality(PR); 8081 return false; 8082 } 8083 8084 /// parseDirectiveHandlerData 8085 /// ::= .handlerdata 8086 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { 8087 // Check the ordering of unwind directives 8088 HandlerDataLoc = L; 8089 if (!FnStartLoc.isValid()) 8090 return Error(L, ".fnstart must precede .personality directive"); 8091 if (CantUnwindLoc.isValid()) { 8092 Error(L, ".handlerdata can't be used with .cantunwind directive"); 8093 Error(CantUnwindLoc, ".cantunwind was specified here"); 8094 return true; 8095 } 8096 8097 getParser().getStreamer().EmitHandlerData(); 8098 return false; 8099 } 8100 8101 /// parseDirectiveSetFP 8102 /// ::= .setfp fpreg, spreg [, offset] 8103 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { 8104 // Check the ordering of unwind directives 8105 if (!FnStartLoc.isValid()) 8106 return Error(L, ".fnstart must precede .setfp directive"); 8107 if (HandlerDataLoc.isValid()) 8108 return Error(L, ".setfp must precede .handlerdata directive"); 8109 8110 // Parse fpreg 8111 SMLoc NewFPRegLoc = Parser.getTok().getLoc(); 8112 int NewFPReg = tryParseRegister(); 8113 if (NewFPReg == -1) 8114 return Error(NewFPRegLoc, "frame pointer register expected"); 8115 8116 // Consume comma 8117 if (!Parser.getTok().is(AsmToken::Comma)) 8118 return Error(Parser.getTok().getLoc(), "comma expected"); 8119 Parser.Lex(); // skip comma 8120 8121 // Parse spreg 8122 SMLoc NewSPRegLoc = Parser.getTok().getLoc(); 8123 int NewSPReg = tryParseRegister(); 8124 if (NewSPReg == -1) 8125 return Error(NewSPRegLoc, "stack pointer register expected"); 8126 8127 if (NewSPReg != ARM::SP && NewSPReg != FPReg) 8128 return Error(NewSPRegLoc, 8129 "register should be either $sp or the latest fp register"); 8130 8131 // Update the frame pointer register 8132 FPReg = NewFPReg; 8133 8134 // Parse offset 8135 int64_t Offset = 0; 8136 if (Parser.getTok().is(AsmToken::Comma)) { 8137 Parser.Lex(); // skip comma 8138 8139 if (Parser.getTok().isNot(AsmToken::Hash) && 8140 Parser.getTok().isNot(AsmToken::Dollar)) { 8141 return Error(Parser.getTok().getLoc(), "'#' expected"); 8142 } 8143 Parser.Lex(); // skip hash token. 8144 8145 const MCExpr *OffsetExpr; 8146 SMLoc ExLoc = Parser.getTok().getLoc(); 8147 SMLoc EndLoc; 8148 if (getParser().parseExpression(OffsetExpr, EndLoc)) 8149 return Error(ExLoc, "malformed setfp offset"); 8150 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8151 if (!CE) 8152 return Error(ExLoc, "setfp offset must be an immediate"); 8153 8154 Offset = CE->getValue(); 8155 } 8156 8157 getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg), 8158 static_cast<unsigned>(NewSPReg), 8159 Offset); 8160 return false; 8161 } 8162 8163 /// parseDirective 8164 /// ::= .pad offset 8165 bool ARMAsmParser::parseDirectivePad(SMLoc L) { 8166 // Check the ordering of unwind directives 8167 if (!FnStartLoc.isValid()) 8168 return Error(L, ".fnstart must precede .pad directive"); 8169 if (HandlerDataLoc.isValid()) 8170 return Error(L, ".pad must precede .handlerdata directive"); 8171 8172 // Parse the offset 8173 if (Parser.getTok().isNot(AsmToken::Hash) && 8174 Parser.getTok().isNot(AsmToken::Dollar)) { 8175 return Error(Parser.getTok().getLoc(), "'#' expected"); 8176 } 8177 Parser.Lex(); // skip hash token. 8178 8179 const MCExpr *OffsetExpr; 8180 SMLoc ExLoc = Parser.getTok().getLoc(); 8181 SMLoc EndLoc; 8182 if (getParser().parseExpression(OffsetExpr, EndLoc)) 8183 return Error(ExLoc, "malformed pad offset"); 8184 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 8185 if (!CE) 8186 return Error(ExLoc, "pad offset must be an immediate"); 8187 8188 getParser().getStreamer().EmitPad(CE->getValue()); 8189 return false; 8190 } 8191 8192 /// parseDirectiveRegSave 8193 /// ::= .save { registers } 8194 /// ::= .vsave { registers } 8195 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { 8196 // Check the ordering of unwind directives 8197 if (!FnStartLoc.isValid()) 8198 return Error(L, ".fnstart must precede .save or .vsave directives"); 8199 if (HandlerDataLoc.isValid()) 8200 return Error(L, ".save or .vsave must precede .handlerdata directive"); 8201 8202 // Parse the register list 8203 SmallVector<MCParsedAsmOperand*, 1> Operands; 8204 if (parseRegisterList(Operands)) 8205 return true; 8206 ARMOperand *Op = (ARMOperand*)Operands[0]; 8207 if (!IsVector && !Op->isRegList()) 8208 return Error(L, ".save expects GPR registers"); 8209 if (IsVector && !Op->isDPRRegList()) 8210 return Error(L, ".vsave expects DPR registers"); 8211 8212 getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector); 8213 return false; 8214 } 8215 8216 /// Force static initialization. 8217 extern "C" void LLVMInitializeARMAsmParser() { 8218 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 8219 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 8220 } 8221 8222 #define GET_REGISTER_MATCHER 8223 #define GET_SUBTARGET_FEATURE_NAME 8224 #define GET_MATCHER_IMPLEMENTATION 8225 #include "ARMGenAsmMatcher.inc" 8226 8227 // Define this matcher function after the auto-generated include so we 8228 // have the match class enum definitions. 8229 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp, 8230 unsigned Kind) { 8231 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp); 8232 // If the kind is a token for a literal immediate, check if our asm 8233 // operand matches. This is for InstAliases which have a fixed-value 8234 // immediate in the syntax. 8235 if (Kind == MCK__35_0 && Op->isImm()) { 8236 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 8237 if (!CE) 8238 return Match_InvalidOperand; 8239 if (CE->getValue() == 0) 8240 return Match_Success; 8241 } 8242 return Match_InvalidOperand; 8243 } 8244