1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "ARMFPUName.h" 11 #include "ARMFeatures.h" 12 #include "MCTargetDesc/ARMAddressingModes.h" 13 #include "MCTargetDesc/ARMArchName.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/ADT/StringSwitch.h" 20 #include "llvm/ADT/Twine.h" 21 #include "llvm/MC/MCAsmInfo.h" 22 #include "llvm/MC/MCAssembler.h" 23 #include "llvm/MC/MCContext.h" 24 #include "llvm/MC/MCDisassembler.h" 25 #include "llvm/MC/MCELFStreamer.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/MC/MCInst.h" 28 #include "llvm/MC/MCInstrDesc.h" 29 #include "llvm/MC/MCInstrInfo.h" 30 #include "llvm/MC/MCObjectFileInfo.h" 31 #include "llvm/MC/MCParser/MCAsmLexer.h" 32 #include "llvm/MC/MCParser/MCAsmParser.h" 33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 34 #include "llvm/MC/MCRegisterInfo.h" 35 #include "llvm/MC/MCSection.h" 36 #include "llvm/MC/MCStreamer.h" 37 #include "llvm/MC/MCSubtargetInfo.h" 38 #include "llvm/MC/MCSymbol.h" 39 #include "llvm/MC/MCTargetAsmParser.h" 40 #include "llvm/Support/ARMBuildAttributes.h" 41 #include "llvm/Support/ARMEHABI.h" 42 #include "llvm/Support/COFF.h" 43 #include "llvm/Support/Debug.h" 44 #include "llvm/Support/ELF.h" 45 #include "llvm/Support/MathExtras.h" 46 #include "llvm/Support/SourceMgr.h" 47 #include "llvm/Support/TargetRegistry.h" 48 #include "llvm/Support/raw_ostream.h" 49 50 using namespace llvm; 51 52 namespace { 53 54 class ARMOperand; 55 56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 57 58 class UnwindContext { 59 MCAsmParser &Parser; 60 61 typedef SmallVector<SMLoc, 4> Locs; 62 63 Locs FnStartLocs; 64 Locs CantUnwindLocs; 65 Locs PersonalityLocs; 66 Locs PersonalityIndexLocs; 67 Locs HandlerDataLocs; 68 int FPReg; 69 70 public: 71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} 72 73 bool hasFnStart() const { return !FnStartLocs.empty(); } 74 bool cantUnwind() const { return !CantUnwindLocs.empty(); } 75 bool hasHandlerData() const { return !HandlerDataLocs.empty(); } 76 bool hasPersonality() const { 77 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); 78 } 79 80 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } 81 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } 82 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } 83 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } 84 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } 85 86 void saveFPReg(int Reg) { FPReg = Reg; } 87 int getFPReg() const { return FPReg; } 88 89 void emitFnStartLocNotes() const { 90 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); 91 FI != FE; ++FI) 92 Parser.Note(*FI, ".fnstart was specified here"); 93 } 94 void emitCantUnwindLocNotes() const { 95 for (Locs::const_iterator UI = CantUnwindLocs.begin(), 96 UE = CantUnwindLocs.end(); UI != UE; ++UI) 97 Parser.Note(*UI, ".cantunwind was specified here"); 98 } 99 void emitHandlerDataLocNotes() const { 100 for (Locs::const_iterator HI = HandlerDataLocs.begin(), 101 HE = HandlerDataLocs.end(); HI != HE; ++HI) 102 Parser.Note(*HI, ".handlerdata was specified here"); 103 } 104 void emitPersonalityLocNotes() const { 105 for (Locs::const_iterator PI = PersonalityLocs.begin(), 106 PE = PersonalityLocs.end(), 107 PII = PersonalityIndexLocs.begin(), 108 PIE = PersonalityIndexLocs.end(); 109 PI != PE || PII != PIE;) { 110 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) 111 Parser.Note(*PI++, ".personality was specified here"); 112 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) 113 Parser.Note(*PII++, ".personalityindex was specified here"); 114 else 115 llvm_unreachable(".personality and .personalityindex cannot be " 116 "at the same location"); 117 } 118 } 119 120 void reset() { 121 FnStartLocs = Locs(); 122 CantUnwindLocs = Locs(); 123 PersonalityLocs = Locs(); 124 HandlerDataLocs = Locs(); 125 PersonalityIndexLocs = Locs(); 126 FPReg = ARM::SP; 127 } 128 }; 129 130 class ARMAsmParser : public MCTargetAsmParser { 131 MCSubtargetInfo &STI; 132 MCAsmParser &Parser; 133 const MCInstrInfo &MII; 134 const MCRegisterInfo *MRI; 135 UnwindContext UC; 136 137 ARMTargetStreamer &getTargetStreamer() { 138 assert(getParser().getStreamer().getTargetStreamer() && 139 "do not have a target streamer"); 140 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); 141 return static_cast<ARMTargetStreamer &>(TS); 142 } 143 144 // Map of register aliases registers via the .req directive. 145 StringMap<unsigned> RegisterReqs; 146 147 bool NextSymbolIsThumb; 148 149 struct { 150 ARMCC::CondCodes Cond; // Condition for IT block. 151 unsigned Mask:4; // Condition mask for instructions. 152 // Starting at first 1 (from lsb). 153 // '1' condition as indicated in IT. 154 // '0' inverse of condition (else). 155 // Count of instructions in IT block is 156 // 4 - trailingzeroes(mask) 157 158 bool FirstCond; // Explicit flag for when we're parsing the 159 // First instruction in the IT block. It's 160 // implied in the mask, so needs special 161 // handling. 162 163 unsigned CurPosition; // Current position in parsing of IT 164 // block. In range [0,3]. Initialized 165 // according to count of instructions in block. 166 // ~0U if no active IT block. 167 } ITState; 168 bool inITBlock() { return ITState.CurPosition != ~0U;} 169 void forwardITPosition() { 170 if (!inITBlock()) return; 171 // Move to the next instruction in the IT block, if there is one. If not, 172 // mark the block as done. 173 unsigned TZ = countTrailingZeros(ITState.Mask); 174 if (++ITState.CurPosition == 5 - TZ) 175 ITState.CurPosition = ~0U; // Done with the IT block after this. 176 } 177 178 179 MCAsmParser &getParser() const { return Parser; } 180 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 181 182 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) { 183 return Parser.Note(L, Msg, Ranges); 184 } 185 bool Warning(SMLoc L, const Twine &Msg, 186 ArrayRef<SMRange> Ranges = None) { 187 return Parser.Warning(L, Msg, Ranges); 188 } 189 bool Error(SMLoc L, const Twine &Msg, 190 ArrayRef<SMRange> Ranges = None) { 191 return Parser.Error(L, Msg, Ranges); 192 } 193 194 int tryParseRegister(); 195 bool tryParseRegisterWithWriteBack(OperandVector &); 196 int tryParseShiftRegister(OperandVector &); 197 bool parseRegisterList(OperandVector &); 198 bool parseMemory(OperandVector &); 199 bool parseOperand(OperandVector &, StringRef Mnemonic); 200 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 201 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 202 unsigned &ShiftAmount); 203 bool parseLiteralValues(unsigned Size, SMLoc L); 204 bool parseDirectiveThumb(SMLoc L); 205 bool parseDirectiveARM(SMLoc L); 206 bool parseDirectiveThumbFunc(SMLoc L); 207 bool parseDirectiveCode(SMLoc L); 208 bool parseDirectiveSyntax(SMLoc L); 209 bool parseDirectiveReq(StringRef Name, SMLoc L); 210 bool parseDirectiveUnreq(SMLoc L); 211 bool parseDirectiveArch(SMLoc L); 212 bool parseDirectiveEabiAttr(SMLoc L); 213 bool parseDirectiveCPU(SMLoc L); 214 bool parseDirectiveFPU(SMLoc L); 215 bool parseDirectiveFnStart(SMLoc L); 216 bool parseDirectiveFnEnd(SMLoc L); 217 bool parseDirectiveCantUnwind(SMLoc L); 218 bool parseDirectivePersonality(SMLoc L); 219 bool parseDirectiveHandlerData(SMLoc L); 220 bool parseDirectiveSetFP(SMLoc L); 221 bool parseDirectivePad(SMLoc L); 222 bool parseDirectiveRegSave(SMLoc L, bool IsVector); 223 bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); 224 bool parseDirectiveLtorg(SMLoc L); 225 bool parseDirectiveEven(SMLoc L); 226 bool parseDirectivePersonalityIndex(SMLoc L); 227 bool parseDirectiveUnwindRaw(SMLoc L); 228 bool parseDirectiveTLSDescSeq(SMLoc L); 229 bool parseDirectiveMovSP(SMLoc L); 230 bool parseDirectiveObjectArch(SMLoc L); 231 bool parseDirectiveArchExtension(SMLoc L); 232 bool parseDirectiveAlign(SMLoc L); 233 bool parseDirectiveThumbSet(SMLoc L); 234 235 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 236 bool &CarrySetting, unsigned &ProcessorIMod, 237 StringRef &ITMask); 238 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 239 bool &CanAcceptCarrySet, 240 bool &CanAcceptPredicationCode); 241 242 bool isThumb() const { 243 // FIXME: Can tablegen auto-generate this? 244 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 245 } 246 bool isThumbOne() const { 247 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 248 } 249 bool isThumbTwo() const { 250 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 251 } 252 bool hasThumb() const { 253 return STI.getFeatureBits() & ARM::HasV4TOps; 254 } 255 bool hasV6Ops() const { 256 return STI.getFeatureBits() & ARM::HasV6Ops; 257 } 258 bool hasV6MOps() const { 259 return STI.getFeatureBits() & ARM::HasV6MOps; 260 } 261 bool hasV7Ops() const { 262 return STI.getFeatureBits() & ARM::HasV7Ops; 263 } 264 bool hasV8Ops() const { 265 return STI.getFeatureBits() & ARM::HasV8Ops; 266 } 267 bool hasARM() const { 268 return !(STI.getFeatureBits() & ARM::FeatureNoARM); 269 } 270 bool hasThumb2DSP() const { 271 return STI.getFeatureBits() & ARM::FeatureDSPThumb2; 272 } 273 bool hasD16() const { 274 return STI.getFeatureBits() & ARM::FeatureD16; 275 } 276 277 void SwitchMode() { 278 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 279 setAvailableFeatures(FB); 280 } 281 bool isMClass() const { 282 return STI.getFeatureBits() & ARM::FeatureMClass; 283 } 284 285 /// @name Auto-generated Match Functions 286 /// { 287 288 #define GET_ASSEMBLER_HEADER 289 #include "ARMGenAsmMatcher.inc" 290 291 /// } 292 293 OperandMatchResultTy parseITCondCode(OperandVector &); 294 OperandMatchResultTy parseCoprocNumOperand(OperandVector &); 295 OperandMatchResultTy parseCoprocRegOperand(OperandVector &); 296 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &); 297 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &); 298 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); 299 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); 300 OperandMatchResultTy parseMSRMaskOperand(OperandVector &); 301 OperandMatchResultTy parseBankedRegOperand(OperandVector &); 302 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, 303 int High); 304 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { 305 return parsePKHImm(O, "lsl", 0, 31); 306 } 307 OperandMatchResultTy parsePKHASRImm(OperandVector &O) { 308 return parsePKHImm(O, "asr", 1, 32); 309 } 310 OperandMatchResultTy parseSetEndImm(OperandVector &); 311 OperandMatchResultTy parseShifterImm(OperandVector &); 312 OperandMatchResultTy parseRotImm(OperandVector &); 313 OperandMatchResultTy parseBitfield(OperandVector &); 314 OperandMatchResultTy parsePostIdxReg(OperandVector &); 315 OperandMatchResultTy parseAM3Offset(OperandVector &); 316 OperandMatchResultTy parseFPImm(OperandVector &); 317 OperandMatchResultTy parseVectorList(OperandVector &); 318 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, 319 SMLoc &EndLoc); 320 321 // Asm Match Converter Methods 322 void cvtThumbMultiply(MCInst &Inst, const OperandVector &); 323 void cvtThumbBranches(MCInst &Inst, const OperandVector &); 324 325 bool validateInstruction(MCInst &Inst, const OperandVector &Ops); 326 bool processInstruction(MCInst &Inst, const OperandVector &Ops); 327 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); 328 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); 329 330 public: 331 enum ARMMatchResultTy { 332 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 333 Match_RequiresNotITBlock, 334 Match_RequiresV6, 335 Match_RequiresThumb2, 336 #define GET_OPERAND_DIAGNOSTIC_TYPES 337 #include "ARMGenAsmMatcher.inc" 338 339 }; 340 341 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, 342 const MCInstrInfo &MII, 343 const MCTargetOptions &Options) 344 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) { 345 MCAsmParserExtension::Initialize(_Parser); 346 347 // Cache the MCRegisterInfo. 348 MRI = getContext().getRegisterInfo(); 349 350 // Initialize the set of available features. 351 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 352 353 // Not in an ITBlock to start with. 354 ITState.CurPosition = ~0U; 355 356 NextSymbolIsThumb = false; 357 } 358 359 // Implementation of the MCTargetAsmParser interface: 360 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 361 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 362 SMLoc NameLoc, OperandVector &Operands) override; 363 bool ParseDirective(AsmToken DirectiveID) override; 364 365 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 366 unsigned Kind) override; 367 unsigned checkTargetMatchPredicate(MCInst &Inst) override; 368 369 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 370 OperandVector &Operands, MCStreamer &Out, 371 uint64_t &ErrorInfo, 372 bool MatchingInlineAsm) override; 373 void onLabelParsed(MCSymbol *Symbol) override; 374 }; 375 } // end anonymous namespace 376 377 namespace { 378 379 /// ARMOperand - Instances of this class represent a parsed ARM machine 380 /// operand. 381 class ARMOperand : public MCParsedAsmOperand { 382 enum KindTy { 383 k_CondCode, 384 k_CCOut, 385 k_ITCondMask, 386 k_CoprocNum, 387 k_CoprocReg, 388 k_CoprocOption, 389 k_Immediate, 390 k_MemBarrierOpt, 391 k_InstSyncBarrierOpt, 392 k_Memory, 393 k_PostIndexRegister, 394 k_MSRMask, 395 k_BankedReg, 396 k_ProcIFlags, 397 k_VectorIndex, 398 k_Register, 399 k_RegisterList, 400 k_DPRRegisterList, 401 k_SPRRegisterList, 402 k_VectorList, 403 k_VectorListAllLanes, 404 k_VectorListIndexed, 405 k_ShiftedRegister, 406 k_ShiftedImmediate, 407 k_ShifterImmediate, 408 k_RotateImmediate, 409 k_BitfieldDescriptor, 410 k_Token 411 } Kind; 412 413 SMLoc StartLoc, EndLoc, AlignmentLoc; 414 SmallVector<unsigned, 8> Registers; 415 416 struct CCOp { 417 ARMCC::CondCodes Val; 418 }; 419 420 struct CopOp { 421 unsigned Val; 422 }; 423 424 struct CoprocOptionOp { 425 unsigned Val; 426 }; 427 428 struct ITMaskOp { 429 unsigned Mask:4; 430 }; 431 432 struct MBOptOp { 433 ARM_MB::MemBOpt Val; 434 }; 435 436 struct ISBOptOp { 437 ARM_ISB::InstSyncBOpt Val; 438 }; 439 440 struct IFlagsOp { 441 ARM_PROC::IFlags Val; 442 }; 443 444 struct MMaskOp { 445 unsigned Val; 446 }; 447 448 struct BankedRegOp { 449 unsigned Val; 450 }; 451 452 struct TokOp { 453 const char *Data; 454 unsigned Length; 455 }; 456 457 struct RegOp { 458 unsigned RegNum; 459 }; 460 461 // A vector register list is a sequential list of 1 to 4 registers. 462 struct VectorListOp { 463 unsigned RegNum; 464 unsigned Count; 465 unsigned LaneIndex; 466 bool isDoubleSpaced; 467 }; 468 469 struct VectorIndexOp { 470 unsigned Val; 471 }; 472 473 struct ImmOp { 474 const MCExpr *Val; 475 }; 476 477 /// Combined record for all forms of ARM address expressions. 478 struct MemoryOp { 479 unsigned BaseRegNum; 480 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 481 // was specified. 482 const MCConstantExpr *OffsetImm; // Offset immediate value 483 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 484 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 485 unsigned ShiftImm; // shift for OffsetReg. 486 unsigned Alignment; // 0 = no alignment specified 487 // n = alignment in bytes (2, 4, 8, 16, or 32) 488 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 489 }; 490 491 struct PostIdxRegOp { 492 unsigned RegNum; 493 bool isAdd; 494 ARM_AM::ShiftOpc ShiftTy; 495 unsigned ShiftImm; 496 }; 497 498 struct ShifterImmOp { 499 bool isASR; 500 unsigned Imm; 501 }; 502 503 struct RegShiftedRegOp { 504 ARM_AM::ShiftOpc ShiftTy; 505 unsigned SrcReg; 506 unsigned ShiftReg; 507 unsigned ShiftImm; 508 }; 509 510 struct RegShiftedImmOp { 511 ARM_AM::ShiftOpc ShiftTy; 512 unsigned SrcReg; 513 unsigned ShiftImm; 514 }; 515 516 struct RotImmOp { 517 unsigned Imm; 518 }; 519 520 struct BitfieldOp { 521 unsigned LSB; 522 unsigned Width; 523 }; 524 525 union { 526 struct CCOp CC; 527 struct CopOp Cop; 528 struct CoprocOptionOp CoprocOption; 529 struct MBOptOp MBOpt; 530 struct ISBOptOp ISBOpt; 531 struct ITMaskOp ITMask; 532 struct IFlagsOp IFlags; 533 struct MMaskOp MMask; 534 struct BankedRegOp BankedReg; 535 struct TokOp Tok; 536 struct RegOp Reg; 537 struct VectorListOp VectorList; 538 struct VectorIndexOp VectorIndex; 539 struct ImmOp Imm; 540 struct MemoryOp Memory; 541 struct PostIdxRegOp PostIdxReg; 542 struct ShifterImmOp ShifterImm; 543 struct RegShiftedRegOp RegShiftedReg; 544 struct RegShiftedImmOp RegShiftedImm; 545 struct RotImmOp RotImm; 546 struct BitfieldOp Bitfield; 547 }; 548 549 public: 550 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 551 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 552 Kind = o.Kind; 553 StartLoc = o.StartLoc; 554 EndLoc = o.EndLoc; 555 switch (Kind) { 556 case k_CondCode: 557 CC = o.CC; 558 break; 559 case k_ITCondMask: 560 ITMask = o.ITMask; 561 break; 562 case k_Token: 563 Tok = o.Tok; 564 break; 565 case k_CCOut: 566 case k_Register: 567 Reg = o.Reg; 568 break; 569 case k_RegisterList: 570 case k_DPRRegisterList: 571 case k_SPRRegisterList: 572 Registers = o.Registers; 573 break; 574 case k_VectorList: 575 case k_VectorListAllLanes: 576 case k_VectorListIndexed: 577 VectorList = o.VectorList; 578 break; 579 case k_CoprocNum: 580 case k_CoprocReg: 581 Cop = o.Cop; 582 break; 583 case k_CoprocOption: 584 CoprocOption = o.CoprocOption; 585 break; 586 case k_Immediate: 587 Imm = o.Imm; 588 break; 589 case k_MemBarrierOpt: 590 MBOpt = o.MBOpt; 591 break; 592 case k_InstSyncBarrierOpt: 593 ISBOpt = o.ISBOpt; 594 case k_Memory: 595 Memory = o.Memory; 596 break; 597 case k_PostIndexRegister: 598 PostIdxReg = o.PostIdxReg; 599 break; 600 case k_MSRMask: 601 MMask = o.MMask; 602 break; 603 case k_BankedReg: 604 BankedReg = o.BankedReg; 605 break; 606 case k_ProcIFlags: 607 IFlags = o.IFlags; 608 break; 609 case k_ShifterImmediate: 610 ShifterImm = o.ShifterImm; 611 break; 612 case k_ShiftedRegister: 613 RegShiftedReg = o.RegShiftedReg; 614 break; 615 case k_ShiftedImmediate: 616 RegShiftedImm = o.RegShiftedImm; 617 break; 618 case k_RotateImmediate: 619 RotImm = o.RotImm; 620 break; 621 case k_BitfieldDescriptor: 622 Bitfield = o.Bitfield; 623 break; 624 case k_VectorIndex: 625 VectorIndex = o.VectorIndex; 626 break; 627 } 628 } 629 630 /// getStartLoc - Get the location of the first token of this operand. 631 SMLoc getStartLoc() const override { return StartLoc; } 632 /// getEndLoc - Get the location of the last token of this operand. 633 SMLoc getEndLoc() const override { return EndLoc; } 634 /// getLocRange - Get the range between the first and last token of this 635 /// operand. 636 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 637 638 /// getAlignmentLoc - Get the location of the Alignment token of this operand. 639 SMLoc getAlignmentLoc() const { 640 assert(Kind == k_Memory && "Invalid access!"); 641 return AlignmentLoc; 642 } 643 644 ARMCC::CondCodes getCondCode() const { 645 assert(Kind == k_CondCode && "Invalid access!"); 646 return CC.Val; 647 } 648 649 unsigned getCoproc() const { 650 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 651 return Cop.Val; 652 } 653 654 StringRef getToken() const { 655 assert(Kind == k_Token && "Invalid access!"); 656 return StringRef(Tok.Data, Tok.Length); 657 } 658 659 unsigned getReg() const override { 660 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 661 return Reg.RegNum; 662 } 663 664 const SmallVectorImpl<unsigned> &getRegList() const { 665 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 666 Kind == k_SPRRegisterList) && "Invalid access!"); 667 return Registers; 668 } 669 670 const MCExpr *getImm() const { 671 assert(isImm() && "Invalid access!"); 672 return Imm.Val; 673 } 674 675 unsigned getVectorIndex() const { 676 assert(Kind == k_VectorIndex && "Invalid access!"); 677 return VectorIndex.Val; 678 } 679 680 ARM_MB::MemBOpt getMemBarrierOpt() const { 681 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 682 return MBOpt.Val; 683 } 684 685 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { 686 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); 687 return ISBOpt.Val; 688 } 689 690 ARM_PROC::IFlags getProcIFlags() const { 691 assert(Kind == k_ProcIFlags && "Invalid access!"); 692 return IFlags.Val; 693 } 694 695 unsigned getMSRMask() const { 696 assert(Kind == k_MSRMask && "Invalid access!"); 697 return MMask.Val; 698 } 699 700 unsigned getBankedReg() const { 701 assert(Kind == k_BankedReg && "Invalid access!"); 702 return BankedReg.Val; 703 } 704 705 bool isCoprocNum() const { return Kind == k_CoprocNum; } 706 bool isCoprocReg() const { return Kind == k_CoprocReg; } 707 bool isCoprocOption() const { return Kind == k_CoprocOption; } 708 bool isCondCode() const { return Kind == k_CondCode; } 709 bool isCCOut() const { return Kind == k_CCOut; } 710 bool isITMask() const { return Kind == k_ITCondMask; } 711 bool isITCondCode() const { return Kind == k_CondCode; } 712 bool isImm() const override { return Kind == k_Immediate; } 713 // checks whether this operand is an unsigned offset which fits is a field 714 // of specified width and scaled by a specific number of bits 715 template<unsigned width, unsigned scale> 716 bool isUnsignedOffset() const { 717 if (!isImm()) return false; 718 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 719 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 720 int64_t Val = CE->getValue(); 721 int64_t Align = 1LL << scale; 722 int64_t Max = Align * ((1LL << width) - 1); 723 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); 724 } 725 return false; 726 } 727 // checks whether this operand is an signed offset which fits is a field 728 // of specified width and scaled by a specific number of bits 729 template<unsigned width, unsigned scale> 730 bool isSignedOffset() const { 731 if (!isImm()) return false; 732 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 733 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) { 734 int64_t Val = CE->getValue(); 735 int64_t Align = 1LL << scale; 736 int64_t Max = Align * ((1LL << (width-1)) - 1); 737 int64_t Min = -Align * (1LL << (width-1)); 738 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); 739 } 740 return false; 741 } 742 743 // checks whether this operand is a memory operand computed as an offset 744 // applied to PC. the offset may have 8 bits of magnitude and is represented 745 // with two bits of shift. textually it may be either [pc, #imm], #imm or 746 // relocable expression... 747 bool isThumbMemPC() const { 748 int64_t Val = 0; 749 if (isImm()) { 750 if (isa<MCSymbolRefExpr>(Imm.Val)) return true; 751 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val); 752 if (!CE) return false; 753 Val = CE->getValue(); 754 } 755 else if (isMem()) { 756 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; 757 if(Memory.BaseRegNum != ARM::PC) return false; 758 Val = Memory.OffsetImm->getValue(); 759 } 760 else return false; 761 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); 762 } 763 bool isFPImm() const { 764 if (!isImm()) return false; 765 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 766 if (!CE) return false; 767 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 768 return Val != -1; 769 } 770 bool isFBits16() const { 771 if (!isImm()) return false; 772 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 773 if (!CE) return false; 774 int64_t Value = CE->getValue(); 775 return Value >= 0 && Value <= 16; 776 } 777 bool isFBits32() const { 778 if (!isImm()) return false; 779 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 780 if (!CE) return false; 781 int64_t Value = CE->getValue(); 782 return Value >= 1 && Value <= 32; 783 } 784 bool isImm8s4() const { 785 if (!isImm()) return false; 786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 787 if (!CE) return false; 788 int64_t Value = CE->getValue(); 789 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 790 } 791 bool isImm0_1020s4() const { 792 if (!isImm()) return false; 793 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 794 if (!CE) return false; 795 int64_t Value = CE->getValue(); 796 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 797 } 798 bool isImm0_508s4() const { 799 if (!isImm()) return false; 800 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 801 if (!CE) return false; 802 int64_t Value = CE->getValue(); 803 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 804 } 805 bool isImm0_508s4Neg() const { 806 if (!isImm()) return false; 807 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 808 if (!CE) return false; 809 int64_t Value = -CE->getValue(); 810 // explicitly exclude zero. we want that to use the normal 0_508 version. 811 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 812 } 813 bool isImm0_239() const { 814 if (!isImm()) return false; 815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 816 if (!CE) return false; 817 int64_t Value = CE->getValue(); 818 return Value >= 0 && Value < 240; 819 } 820 bool isImm0_255() const { 821 if (!isImm()) return false; 822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 823 if (!CE) return false; 824 int64_t Value = CE->getValue(); 825 return Value >= 0 && Value < 256; 826 } 827 bool isImm0_4095() const { 828 if (!isImm()) return false; 829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 830 if (!CE) return false; 831 int64_t Value = CE->getValue(); 832 return Value >= 0 && Value < 4096; 833 } 834 bool isImm0_4095Neg() const { 835 if (!isImm()) return false; 836 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 837 if (!CE) return false; 838 int64_t Value = -CE->getValue(); 839 return Value > 0 && Value < 4096; 840 } 841 bool isImm0_1() const { 842 if (!isImm()) return false; 843 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 844 if (!CE) return false; 845 int64_t Value = CE->getValue(); 846 return Value >= 0 && Value < 2; 847 } 848 bool isImm0_3() const { 849 if (!isImm()) return false; 850 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 851 if (!CE) return false; 852 int64_t Value = CE->getValue(); 853 return Value >= 0 && Value < 4; 854 } 855 bool isImm0_7() const { 856 if (!isImm()) return false; 857 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 858 if (!CE) return false; 859 int64_t Value = CE->getValue(); 860 return Value >= 0 && Value < 8; 861 } 862 bool isImm0_15() const { 863 if (!isImm()) return false; 864 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 865 if (!CE) return false; 866 int64_t Value = CE->getValue(); 867 return Value >= 0 && Value < 16; 868 } 869 bool isImm0_31() const { 870 if (!isImm()) return false; 871 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 872 if (!CE) return false; 873 int64_t Value = CE->getValue(); 874 return Value >= 0 && Value < 32; 875 } 876 bool isImm0_63() const { 877 if (!isImm()) return false; 878 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 879 if (!CE) return false; 880 int64_t Value = CE->getValue(); 881 return Value >= 0 && Value < 64; 882 } 883 bool isImm8() const { 884 if (!isImm()) return false; 885 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 886 if (!CE) return false; 887 int64_t Value = CE->getValue(); 888 return Value == 8; 889 } 890 bool isImm16() const { 891 if (!isImm()) return false; 892 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 893 if (!CE) return false; 894 int64_t Value = CE->getValue(); 895 return Value == 16; 896 } 897 bool isImm32() const { 898 if (!isImm()) return false; 899 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 900 if (!CE) return false; 901 int64_t Value = CE->getValue(); 902 return Value == 32; 903 } 904 bool isShrImm8() const { 905 if (!isImm()) return false; 906 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 907 if (!CE) return false; 908 int64_t Value = CE->getValue(); 909 return Value > 0 && Value <= 8; 910 } 911 bool isShrImm16() const { 912 if (!isImm()) return false; 913 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 914 if (!CE) return false; 915 int64_t Value = CE->getValue(); 916 return Value > 0 && Value <= 16; 917 } 918 bool isShrImm32() const { 919 if (!isImm()) return false; 920 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 921 if (!CE) return false; 922 int64_t Value = CE->getValue(); 923 return Value > 0 && Value <= 32; 924 } 925 bool isShrImm64() const { 926 if (!isImm()) return false; 927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 928 if (!CE) return false; 929 int64_t Value = CE->getValue(); 930 return Value > 0 && Value <= 64; 931 } 932 bool isImm1_7() const { 933 if (!isImm()) return false; 934 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 935 if (!CE) return false; 936 int64_t Value = CE->getValue(); 937 return Value > 0 && Value < 8; 938 } 939 bool isImm1_15() const { 940 if (!isImm()) return false; 941 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 942 if (!CE) return false; 943 int64_t Value = CE->getValue(); 944 return Value > 0 && Value < 16; 945 } 946 bool isImm1_31() const { 947 if (!isImm()) return false; 948 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 949 if (!CE) return false; 950 int64_t Value = CE->getValue(); 951 return Value > 0 && Value < 32; 952 } 953 bool isImm1_16() const { 954 if (!isImm()) return false; 955 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 956 if (!CE) return false; 957 int64_t Value = CE->getValue(); 958 return Value > 0 && Value < 17; 959 } 960 bool isImm1_32() const { 961 if (!isImm()) return false; 962 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 963 if (!CE) return false; 964 int64_t Value = CE->getValue(); 965 return Value > 0 && Value < 33; 966 } 967 bool isImm0_32() const { 968 if (!isImm()) return false; 969 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 970 if (!CE) return false; 971 int64_t Value = CE->getValue(); 972 return Value >= 0 && Value < 33; 973 } 974 bool isImm0_65535() const { 975 if (!isImm()) return false; 976 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 977 if (!CE) return false; 978 int64_t Value = CE->getValue(); 979 return Value >= 0 && Value < 65536; 980 } 981 bool isImm256_65535Expr() const { 982 if (!isImm()) return false; 983 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 984 // If it's not a constant expression, it'll generate a fixup and be 985 // handled later. 986 if (!CE) return true; 987 int64_t Value = CE->getValue(); 988 return Value >= 256 && Value < 65536; 989 } 990 bool isImm0_65535Expr() const { 991 if (!isImm()) return false; 992 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 993 // If it's not a constant expression, it'll generate a fixup and be 994 // handled later. 995 if (!CE) return true; 996 int64_t Value = CE->getValue(); 997 return Value >= 0 && Value < 65536; 998 } 999 bool isImm24bit() const { 1000 if (!isImm()) return false; 1001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1002 if (!CE) return false; 1003 int64_t Value = CE->getValue(); 1004 return Value >= 0 && Value <= 0xffffff; 1005 } 1006 bool isImmThumbSR() const { 1007 if (!isImm()) return false; 1008 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1009 if (!CE) return false; 1010 int64_t Value = CE->getValue(); 1011 return Value > 0 && Value < 33; 1012 } 1013 bool isPKHLSLImm() const { 1014 if (!isImm()) return false; 1015 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1016 if (!CE) return false; 1017 int64_t Value = CE->getValue(); 1018 return Value >= 0 && Value < 32; 1019 } 1020 bool isPKHASRImm() const { 1021 if (!isImm()) return false; 1022 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1023 if (!CE) return false; 1024 int64_t Value = CE->getValue(); 1025 return Value > 0 && Value <= 32; 1026 } 1027 bool isAdrLabel() const { 1028 // If we have an immediate that's not a constant, treat it as a label 1029 // reference needing a fixup. If it is a constant, but it can't fit 1030 // into shift immediate encoding, we reject it. 1031 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 1032 else return (isARMSOImm() || isARMSOImmNeg()); 1033 } 1034 bool isARMSOImm() const { 1035 if (!isImm()) return false; 1036 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1037 if (!CE) return false; 1038 int64_t Value = CE->getValue(); 1039 return ARM_AM::getSOImmVal(Value) != -1; 1040 } 1041 bool isARMSOImmNot() const { 1042 if (!isImm()) return false; 1043 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1044 if (!CE) return false; 1045 int64_t Value = CE->getValue(); 1046 return ARM_AM::getSOImmVal(~Value) != -1; 1047 } 1048 bool isARMSOImmNeg() const { 1049 if (!isImm()) return false; 1050 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1051 if (!CE) return false; 1052 int64_t Value = CE->getValue(); 1053 // Only use this when not representable as a plain so_imm. 1054 return ARM_AM::getSOImmVal(Value) == -1 && 1055 ARM_AM::getSOImmVal(-Value) != -1; 1056 } 1057 bool isT2SOImm() const { 1058 if (!isImm()) return false; 1059 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1060 if (!CE) return false; 1061 int64_t Value = CE->getValue(); 1062 return ARM_AM::getT2SOImmVal(Value) != -1; 1063 } 1064 bool isT2SOImmNot() const { 1065 if (!isImm()) return false; 1066 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1067 if (!CE) return false; 1068 int64_t Value = CE->getValue(); 1069 return ARM_AM::getT2SOImmVal(Value) == -1 && 1070 ARM_AM::getT2SOImmVal(~Value) != -1; 1071 } 1072 bool isT2SOImmNeg() const { 1073 if (!isImm()) return false; 1074 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1075 if (!CE) return false; 1076 int64_t Value = CE->getValue(); 1077 // Only use this when not representable as a plain so_imm. 1078 return ARM_AM::getT2SOImmVal(Value) == -1 && 1079 ARM_AM::getT2SOImmVal(-Value) != -1; 1080 } 1081 bool isSetEndImm() const { 1082 if (!isImm()) return false; 1083 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1084 if (!CE) return false; 1085 int64_t Value = CE->getValue(); 1086 return Value == 1 || Value == 0; 1087 } 1088 bool isReg() const override { return Kind == k_Register; } 1089 bool isRegList() const { return Kind == k_RegisterList; } 1090 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 1091 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 1092 bool isToken() const override { return Kind == k_Token; } 1093 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 1094 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } 1095 bool isMem() const override { return Kind == k_Memory; } 1096 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 1097 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 1098 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 1099 bool isRotImm() const { return Kind == k_RotateImmediate; } 1100 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 1101 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 1102 bool isPostIdxReg() const { 1103 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 1104 } 1105 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { 1106 if (!isMem()) 1107 return false; 1108 // No offset of any kind. 1109 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && 1110 (alignOK || Memory.Alignment == Alignment); 1111 } 1112 bool isMemPCRelImm12() const { 1113 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1114 return false; 1115 // Base register must be PC. 1116 if (Memory.BaseRegNum != ARM::PC) 1117 return false; 1118 // Immediate offset in range [-4095, 4095]. 1119 if (!Memory.OffsetImm) return true; 1120 int64_t Val = Memory.OffsetImm->getValue(); 1121 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1122 } 1123 bool isAlignedMemory() const { 1124 return isMemNoOffset(true); 1125 } 1126 bool isAlignedMemoryNone() const { 1127 return isMemNoOffset(false, 0); 1128 } 1129 bool isDupAlignedMemoryNone() const { 1130 return isMemNoOffset(false, 0); 1131 } 1132 bool isAlignedMemory16() const { 1133 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1134 return true; 1135 return isMemNoOffset(false, 0); 1136 } 1137 bool isDupAlignedMemory16() const { 1138 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. 1139 return true; 1140 return isMemNoOffset(false, 0); 1141 } 1142 bool isAlignedMemory32() const { 1143 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1144 return true; 1145 return isMemNoOffset(false, 0); 1146 } 1147 bool isDupAlignedMemory32() const { 1148 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. 1149 return true; 1150 return isMemNoOffset(false, 0); 1151 } 1152 bool isAlignedMemory64() const { 1153 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1154 return true; 1155 return isMemNoOffset(false, 0); 1156 } 1157 bool isDupAlignedMemory64() const { 1158 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1159 return true; 1160 return isMemNoOffset(false, 0); 1161 } 1162 bool isAlignedMemory64or128() const { 1163 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1164 return true; 1165 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1166 return true; 1167 return isMemNoOffset(false, 0); 1168 } 1169 bool isDupAlignedMemory64or128() const { 1170 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1171 return true; 1172 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1173 return true; 1174 return isMemNoOffset(false, 0); 1175 } 1176 bool isAlignedMemory64or128or256() const { 1177 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. 1178 return true; 1179 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. 1180 return true; 1181 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32. 1182 return true; 1183 return isMemNoOffset(false, 0); 1184 } 1185 bool isAddrMode2() const { 1186 if (!isMem() || Memory.Alignment != 0) return false; 1187 // Check for register offset. 1188 if (Memory.OffsetRegNum) return true; 1189 // Immediate offset in range [-4095, 4095]. 1190 if (!Memory.OffsetImm) return true; 1191 int64_t Val = Memory.OffsetImm->getValue(); 1192 return Val > -4096 && Val < 4096; 1193 } 1194 bool isAM2OffsetImm() const { 1195 if (!isImm()) return false; 1196 // Immediate offset in range [-4095, 4095]. 1197 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1198 if (!CE) return false; 1199 int64_t Val = CE->getValue(); 1200 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096); 1201 } 1202 bool isAddrMode3() const { 1203 // If we have an immediate that's not a constant, treat it as a label 1204 // reference needing a fixup. If it is a constant, it's something else 1205 // and we reject it. 1206 if (isImm() && !isa<MCConstantExpr>(getImm())) 1207 return true; 1208 if (!isMem() || Memory.Alignment != 0) return false; 1209 // No shifts are legal for AM3. 1210 if (Memory.ShiftType != ARM_AM::no_shift) return false; 1211 // Check for register offset. 1212 if (Memory.OffsetRegNum) return true; 1213 // Immediate offset in range [-255, 255]. 1214 if (!Memory.OffsetImm) return true; 1215 int64_t Val = Memory.OffsetImm->getValue(); 1216 // The #-0 offset is encoded as INT32_MIN, and we have to check 1217 // for this too. 1218 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1219 } 1220 bool isAM3Offset() const { 1221 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 1222 return false; 1223 if (Kind == k_PostIndexRegister) 1224 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1225 // Immediate offset in range [-255, 255]. 1226 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1227 if (!CE) return false; 1228 int64_t Val = CE->getValue(); 1229 // Special case, #-0 is INT32_MIN. 1230 return (Val > -256 && Val < 256) || Val == INT32_MIN; 1231 } 1232 bool isAddrMode5() const { 1233 // If we have an immediate that's not a constant, treat it as a label 1234 // reference needing a fixup. If it is a constant, it's something else 1235 // and we reject it. 1236 if (isImm() && !isa<MCConstantExpr>(getImm())) 1237 return true; 1238 if (!isMem() || Memory.Alignment != 0) return false; 1239 // Check for register offset. 1240 if (Memory.OffsetRegNum) return false; 1241 // Immediate offset in range [-1020, 1020] and a multiple of 4. 1242 if (!Memory.OffsetImm) return true; 1243 int64_t Val = Memory.OffsetImm->getValue(); 1244 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 1245 Val == INT32_MIN; 1246 } 1247 bool isMemTBB() const { 1248 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1249 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1250 return false; 1251 return true; 1252 } 1253 bool isMemTBH() const { 1254 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1255 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 1256 Memory.Alignment != 0 ) 1257 return false; 1258 return true; 1259 } 1260 bool isMemRegOffset() const { 1261 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) 1262 return false; 1263 return true; 1264 } 1265 bool isT2MemRegOffset() const { 1266 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1267 Memory.Alignment != 0) 1268 return false; 1269 // Only lsl #{0, 1, 2, 3} allowed. 1270 if (Memory.ShiftType == ARM_AM::no_shift) 1271 return true; 1272 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 1273 return false; 1274 return true; 1275 } 1276 bool isMemThumbRR() const { 1277 // Thumb reg+reg addressing is simple. Just two registers, a base and 1278 // an offset. No shifts, negations or any other complicating factors. 1279 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative || 1280 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 1281 return false; 1282 return isARMLowRegister(Memory.BaseRegNum) && 1283 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 1284 } 1285 bool isMemThumbRIs4() const { 1286 if (!isMem() || Memory.OffsetRegNum != 0 || 1287 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1288 return false; 1289 // Immediate offset, multiple of 4 in range [0, 124]. 1290 if (!Memory.OffsetImm) return true; 1291 int64_t Val = Memory.OffsetImm->getValue(); 1292 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1293 } 1294 bool isMemThumbRIs2() const { 1295 if (!isMem() || Memory.OffsetRegNum != 0 || 1296 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1297 return false; 1298 // Immediate offset, multiple of 4 in range [0, 62]. 1299 if (!Memory.OffsetImm) return true; 1300 int64_t Val = Memory.OffsetImm->getValue(); 1301 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1302 } 1303 bool isMemThumbRIs1() const { 1304 if (!isMem() || Memory.OffsetRegNum != 0 || 1305 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1306 return false; 1307 // Immediate offset in range [0, 31]. 1308 if (!Memory.OffsetImm) return true; 1309 int64_t Val = Memory.OffsetImm->getValue(); 1310 return Val >= 0 && Val <= 31; 1311 } 1312 bool isMemThumbSPI() const { 1313 if (!isMem() || Memory.OffsetRegNum != 0 || 1314 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1315 return false; 1316 // Immediate offset, multiple of 4 in range [0, 1020]. 1317 if (!Memory.OffsetImm) return true; 1318 int64_t Val = Memory.OffsetImm->getValue(); 1319 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1320 } 1321 bool isMemImm8s4Offset() const { 1322 // If we have an immediate that's not a constant, treat it as a label 1323 // reference needing a fixup. If it is a constant, it's something else 1324 // and we reject it. 1325 if (isImm() && !isa<MCConstantExpr>(getImm())) 1326 return true; 1327 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1328 return false; 1329 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1330 if (!Memory.OffsetImm) return true; 1331 int64_t Val = Memory.OffsetImm->getValue(); 1332 // Special case, #-0 is INT32_MIN. 1333 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1334 } 1335 bool isMemImm0_1020s4Offset() const { 1336 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1337 return false; 1338 // Immediate offset a multiple of 4 in range [0, 1020]. 1339 if (!Memory.OffsetImm) return true; 1340 int64_t Val = Memory.OffsetImm->getValue(); 1341 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1342 } 1343 bool isMemImm8Offset() const { 1344 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1345 return false; 1346 // Base reg of PC isn't allowed for these encodings. 1347 if (Memory.BaseRegNum == ARM::PC) return false; 1348 // Immediate offset in range [-255, 255]. 1349 if (!Memory.OffsetImm) return true; 1350 int64_t Val = Memory.OffsetImm->getValue(); 1351 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1352 } 1353 bool isMemPosImm8Offset() const { 1354 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1355 return false; 1356 // Immediate offset in range [0, 255]. 1357 if (!Memory.OffsetImm) return true; 1358 int64_t Val = Memory.OffsetImm->getValue(); 1359 return Val >= 0 && Val < 256; 1360 } 1361 bool isMemNegImm8Offset() const { 1362 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1363 return false; 1364 // Base reg of PC isn't allowed for these encodings. 1365 if (Memory.BaseRegNum == ARM::PC) return false; 1366 // Immediate offset in range [-255, -1]. 1367 if (!Memory.OffsetImm) return false; 1368 int64_t Val = Memory.OffsetImm->getValue(); 1369 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1370 } 1371 bool isMemUImm12Offset() const { 1372 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1373 return false; 1374 // Immediate offset in range [0, 4095]. 1375 if (!Memory.OffsetImm) return true; 1376 int64_t Val = Memory.OffsetImm->getValue(); 1377 return (Val >= 0 && Val < 4096); 1378 } 1379 bool isMemImm12Offset() const { 1380 // If we have an immediate that's not a constant, treat it as a label 1381 // reference needing a fixup. If it is a constant, it's something else 1382 // and we reject it. 1383 if (isImm() && !isa<MCConstantExpr>(getImm())) 1384 return true; 1385 1386 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1387 return false; 1388 // Immediate offset in range [-4095, 4095]. 1389 if (!Memory.OffsetImm) return true; 1390 int64_t Val = Memory.OffsetImm->getValue(); 1391 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1392 } 1393 bool isPostIdxImm8() const { 1394 if (!isImm()) return false; 1395 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1396 if (!CE) return false; 1397 int64_t Val = CE->getValue(); 1398 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1399 } 1400 bool isPostIdxImm8s4() const { 1401 if (!isImm()) return false; 1402 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1403 if (!CE) return false; 1404 int64_t Val = CE->getValue(); 1405 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1406 (Val == INT32_MIN); 1407 } 1408 1409 bool isMSRMask() const { return Kind == k_MSRMask; } 1410 bool isBankedReg() const { return Kind == k_BankedReg; } 1411 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1412 1413 // NEON operands. 1414 bool isSingleSpacedVectorList() const { 1415 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1416 } 1417 bool isDoubleSpacedVectorList() const { 1418 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1419 } 1420 bool isVecListOneD() const { 1421 if (!isSingleSpacedVectorList()) return false; 1422 return VectorList.Count == 1; 1423 } 1424 1425 bool isVecListDPair() const { 1426 if (!isSingleSpacedVectorList()) return false; 1427 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1428 .contains(VectorList.RegNum)); 1429 } 1430 1431 bool isVecListThreeD() const { 1432 if (!isSingleSpacedVectorList()) return false; 1433 return VectorList.Count == 3; 1434 } 1435 1436 bool isVecListFourD() const { 1437 if (!isSingleSpacedVectorList()) return false; 1438 return VectorList.Count == 4; 1439 } 1440 1441 bool isVecListDPairSpaced() const { 1442 if (Kind != k_VectorList) return false; 1443 if (isSingleSpacedVectorList()) return false; 1444 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1445 .contains(VectorList.RegNum)); 1446 } 1447 1448 bool isVecListThreeQ() const { 1449 if (!isDoubleSpacedVectorList()) return false; 1450 return VectorList.Count == 3; 1451 } 1452 1453 bool isVecListFourQ() const { 1454 if (!isDoubleSpacedVectorList()) return false; 1455 return VectorList.Count == 4; 1456 } 1457 1458 bool isSingleSpacedVectorAllLanes() const { 1459 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1460 } 1461 bool isDoubleSpacedVectorAllLanes() const { 1462 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1463 } 1464 bool isVecListOneDAllLanes() const { 1465 if (!isSingleSpacedVectorAllLanes()) return false; 1466 return VectorList.Count == 1; 1467 } 1468 1469 bool isVecListDPairAllLanes() const { 1470 if (!isSingleSpacedVectorAllLanes()) return false; 1471 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1472 .contains(VectorList.RegNum)); 1473 } 1474 1475 bool isVecListDPairSpacedAllLanes() const { 1476 if (!isDoubleSpacedVectorAllLanes()) return false; 1477 return VectorList.Count == 2; 1478 } 1479 1480 bool isVecListThreeDAllLanes() const { 1481 if (!isSingleSpacedVectorAllLanes()) return false; 1482 return VectorList.Count == 3; 1483 } 1484 1485 bool isVecListThreeQAllLanes() const { 1486 if (!isDoubleSpacedVectorAllLanes()) return false; 1487 return VectorList.Count == 3; 1488 } 1489 1490 bool isVecListFourDAllLanes() const { 1491 if (!isSingleSpacedVectorAllLanes()) return false; 1492 return VectorList.Count == 4; 1493 } 1494 1495 bool isVecListFourQAllLanes() const { 1496 if (!isDoubleSpacedVectorAllLanes()) return false; 1497 return VectorList.Count == 4; 1498 } 1499 1500 bool isSingleSpacedVectorIndexed() const { 1501 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1502 } 1503 bool isDoubleSpacedVectorIndexed() const { 1504 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1505 } 1506 bool isVecListOneDByteIndexed() const { 1507 if (!isSingleSpacedVectorIndexed()) return false; 1508 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1509 } 1510 1511 bool isVecListOneDHWordIndexed() const { 1512 if (!isSingleSpacedVectorIndexed()) return false; 1513 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1514 } 1515 1516 bool isVecListOneDWordIndexed() const { 1517 if (!isSingleSpacedVectorIndexed()) return false; 1518 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1519 } 1520 1521 bool isVecListTwoDByteIndexed() const { 1522 if (!isSingleSpacedVectorIndexed()) return false; 1523 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1524 } 1525 1526 bool isVecListTwoDHWordIndexed() const { 1527 if (!isSingleSpacedVectorIndexed()) return false; 1528 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1529 } 1530 1531 bool isVecListTwoQWordIndexed() const { 1532 if (!isDoubleSpacedVectorIndexed()) return false; 1533 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1534 } 1535 1536 bool isVecListTwoQHWordIndexed() const { 1537 if (!isDoubleSpacedVectorIndexed()) return false; 1538 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1539 } 1540 1541 bool isVecListTwoDWordIndexed() const { 1542 if (!isSingleSpacedVectorIndexed()) return false; 1543 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1544 } 1545 1546 bool isVecListThreeDByteIndexed() const { 1547 if (!isSingleSpacedVectorIndexed()) return false; 1548 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1549 } 1550 1551 bool isVecListThreeDHWordIndexed() const { 1552 if (!isSingleSpacedVectorIndexed()) return false; 1553 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1554 } 1555 1556 bool isVecListThreeQWordIndexed() const { 1557 if (!isDoubleSpacedVectorIndexed()) return false; 1558 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1559 } 1560 1561 bool isVecListThreeQHWordIndexed() const { 1562 if (!isDoubleSpacedVectorIndexed()) return false; 1563 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1564 } 1565 1566 bool isVecListThreeDWordIndexed() const { 1567 if (!isSingleSpacedVectorIndexed()) return false; 1568 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1569 } 1570 1571 bool isVecListFourDByteIndexed() const { 1572 if (!isSingleSpacedVectorIndexed()) return false; 1573 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1574 } 1575 1576 bool isVecListFourDHWordIndexed() const { 1577 if (!isSingleSpacedVectorIndexed()) return false; 1578 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1579 } 1580 1581 bool isVecListFourQWordIndexed() const { 1582 if (!isDoubleSpacedVectorIndexed()) return false; 1583 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1584 } 1585 1586 bool isVecListFourQHWordIndexed() const { 1587 if (!isDoubleSpacedVectorIndexed()) return false; 1588 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1589 } 1590 1591 bool isVecListFourDWordIndexed() const { 1592 if (!isSingleSpacedVectorIndexed()) return false; 1593 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1594 } 1595 1596 bool isVectorIndex8() const { 1597 if (Kind != k_VectorIndex) return false; 1598 return VectorIndex.Val < 8; 1599 } 1600 bool isVectorIndex16() const { 1601 if (Kind != k_VectorIndex) return false; 1602 return VectorIndex.Val < 4; 1603 } 1604 bool isVectorIndex32() const { 1605 if (Kind != k_VectorIndex) return false; 1606 return VectorIndex.Val < 2; 1607 } 1608 1609 bool isNEONi8splat() const { 1610 if (!isImm()) return false; 1611 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1612 // Must be a constant. 1613 if (!CE) return false; 1614 int64_t Value = CE->getValue(); 1615 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1616 // value. 1617 return Value >= 0 && Value < 256; 1618 } 1619 1620 bool isNEONi16splat() const { 1621 if (isNEONByteReplicate(2)) 1622 return false; // Leave that for bytes replication and forbid by default. 1623 if (!isImm()) 1624 return false; 1625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1626 // Must be a constant. 1627 if (!CE) return false; 1628 unsigned Value = CE->getValue(); 1629 return ARM_AM::isNEONi16splat(Value); 1630 } 1631 1632 bool isNEONi16splatNot() const { 1633 if (!isImm()) 1634 return false; 1635 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1636 // Must be a constant. 1637 if (!CE) return false; 1638 unsigned Value = CE->getValue(); 1639 return ARM_AM::isNEONi16splat(~Value & 0xffff); 1640 } 1641 1642 bool isNEONi32splat() const { 1643 if (isNEONByteReplicate(4)) 1644 return false; // Leave that for bytes replication and forbid by default. 1645 if (!isImm()) 1646 return false; 1647 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1648 // Must be a constant. 1649 if (!CE) return false; 1650 unsigned Value = CE->getValue(); 1651 return ARM_AM::isNEONi32splat(Value); 1652 } 1653 1654 bool isNEONi32splatNot() const { 1655 if (!isImm()) 1656 return false; 1657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1658 // Must be a constant. 1659 if (!CE) return false; 1660 unsigned Value = CE->getValue(); 1661 return ARM_AM::isNEONi32splat(~Value); 1662 } 1663 1664 bool isNEONByteReplicate(unsigned NumBytes) const { 1665 if (!isImm()) 1666 return false; 1667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1668 // Must be a constant. 1669 if (!CE) 1670 return false; 1671 int64_t Value = CE->getValue(); 1672 if (!Value) 1673 return false; // Don't bother with zero. 1674 1675 unsigned char B = Value & 0xff; 1676 for (unsigned i = 1; i < NumBytes; ++i) { 1677 Value >>= 8; 1678 if ((Value & 0xff) != B) 1679 return false; 1680 } 1681 return true; 1682 } 1683 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); } 1684 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); } 1685 bool isNEONi32vmov() const { 1686 if (isNEONByteReplicate(4)) 1687 return false; // Let it to be classified as byte-replicate case. 1688 if (!isImm()) 1689 return false; 1690 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1691 // Must be a constant. 1692 if (!CE) 1693 return false; 1694 int64_t Value = CE->getValue(); 1695 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1696 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1697 // FIXME: This is probably wrong and a copy and paste from previous example 1698 return (Value >= 0 && Value < 256) || 1699 (Value >= 0x0100 && Value <= 0xff00) || 1700 (Value >= 0x010000 && Value <= 0xff0000) || 1701 (Value >= 0x01000000 && Value <= 0xff000000) || 1702 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1703 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1704 } 1705 bool isNEONi32vmovNeg() const { 1706 if (!isImm()) return false; 1707 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1708 // Must be a constant. 1709 if (!CE) return false; 1710 int64_t Value = ~CE->getValue(); 1711 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1712 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1713 // FIXME: This is probably wrong and a copy and paste from previous example 1714 return (Value >= 0 && Value < 256) || 1715 (Value >= 0x0100 && Value <= 0xff00) || 1716 (Value >= 0x010000 && Value <= 0xff0000) || 1717 (Value >= 0x01000000 && Value <= 0xff000000) || 1718 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1719 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1720 } 1721 1722 bool isNEONi64splat() const { 1723 if (!isImm()) return false; 1724 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1725 // Must be a constant. 1726 if (!CE) return false; 1727 uint64_t Value = CE->getValue(); 1728 // i64 value with each byte being either 0 or 0xff. 1729 for (unsigned i = 0; i < 8; ++i) 1730 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1731 return true; 1732 } 1733 1734 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1735 // Add as immediates when possible. Null MCExpr = 0. 1736 if (!Expr) 1737 Inst.addOperand(MCOperand::CreateImm(0)); 1738 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1739 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1740 else 1741 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1742 } 1743 1744 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1745 assert(N == 2 && "Invalid number of operands!"); 1746 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1747 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1748 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1749 } 1750 1751 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1752 assert(N == 1 && "Invalid number of operands!"); 1753 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1754 } 1755 1756 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1757 assert(N == 1 && "Invalid number of operands!"); 1758 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1759 } 1760 1761 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1762 assert(N == 1 && "Invalid number of operands!"); 1763 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1764 } 1765 1766 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1767 assert(N == 1 && "Invalid number of operands!"); 1768 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1769 } 1770 1771 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1772 assert(N == 1 && "Invalid number of operands!"); 1773 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1774 } 1775 1776 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1777 assert(N == 1 && "Invalid number of operands!"); 1778 Inst.addOperand(MCOperand::CreateReg(getReg())); 1779 } 1780 1781 void addRegOperands(MCInst &Inst, unsigned N) const { 1782 assert(N == 1 && "Invalid number of operands!"); 1783 Inst.addOperand(MCOperand::CreateReg(getReg())); 1784 } 1785 1786 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1787 assert(N == 3 && "Invalid number of operands!"); 1788 assert(isRegShiftedReg() && 1789 "addRegShiftedRegOperands() on non-RegShiftedReg!"); 1790 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1791 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1792 Inst.addOperand(MCOperand::CreateImm( 1793 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1794 } 1795 1796 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1797 assert(N == 2 && "Invalid number of operands!"); 1798 assert(isRegShiftedImm() && 1799 "addRegShiftedImmOperands() on non-RegShiftedImm!"); 1800 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1801 // Shift of #32 is encoded as 0 where permitted 1802 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1803 Inst.addOperand(MCOperand::CreateImm( 1804 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1805 } 1806 1807 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1808 assert(N == 1 && "Invalid number of operands!"); 1809 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1810 ShifterImm.Imm)); 1811 } 1812 1813 void addRegListOperands(MCInst &Inst, unsigned N) const { 1814 assert(N == 1 && "Invalid number of operands!"); 1815 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1816 for (SmallVectorImpl<unsigned>::const_iterator 1817 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1818 Inst.addOperand(MCOperand::CreateReg(*I)); 1819 } 1820 1821 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1822 addRegListOperands(Inst, N); 1823 } 1824 1825 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1826 addRegListOperands(Inst, N); 1827 } 1828 1829 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1830 assert(N == 1 && "Invalid number of operands!"); 1831 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1832 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1833 } 1834 1835 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1836 assert(N == 1 && "Invalid number of operands!"); 1837 // Munge the lsb/width into a bitfield mask. 1838 unsigned lsb = Bitfield.LSB; 1839 unsigned width = Bitfield.Width; 1840 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1841 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1842 (32 - (lsb + width))); 1843 Inst.addOperand(MCOperand::CreateImm(Mask)); 1844 } 1845 1846 void addImmOperands(MCInst &Inst, unsigned N) const { 1847 assert(N == 1 && "Invalid number of operands!"); 1848 addExpr(Inst, getImm()); 1849 } 1850 1851 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1852 assert(N == 1 && "Invalid number of operands!"); 1853 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1854 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1855 } 1856 1857 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1858 assert(N == 1 && "Invalid number of operands!"); 1859 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1860 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1861 } 1862 1863 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1864 assert(N == 1 && "Invalid number of operands!"); 1865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1866 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1867 Inst.addOperand(MCOperand::CreateImm(Val)); 1868 } 1869 1870 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1871 assert(N == 1 && "Invalid number of operands!"); 1872 // FIXME: We really want to scale the value here, but the LDRD/STRD 1873 // instruction don't encode operands that way yet. 1874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1875 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1876 } 1877 1878 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1879 assert(N == 1 && "Invalid number of operands!"); 1880 // The immediate is scaled by four in the encoding and is stored 1881 // in the MCInst as such. Lop off the low two bits here. 1882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1883 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1884 } 1885 1886 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1887 assert(N == 1 && "Invalid number of operands!"); 1888 // The immediate is scaled by four in the encoding and is stored 1889 // in the MCInst as such. Lop off the low two bits here. 1890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1891 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1892 } 1893 1894 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1895 assert(N == 1 && "Invalid number of operands!"); 1896 // The immediate is scaled by four in the encoding and is stored 1897 // in the MCInst as such. Lop off the low two bits here. 1898 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1899 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1900 } 1901 1902 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1903 assert(N == 1 && "Invalid number of operands!"); 1904 // The constant encodes as the immediate-1, and we store in the instruction 1905 // the bits as encoded, so subtract off one here. 1906 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1907 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1908 } 1909 1910 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1911 assert(N == 1 && "Invalid number of operands!"); 1912 // The constant encodes as the immediate-1, and we store in the instruction 1913 // the bits as encoded, so subtract off one here. 1914 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1915 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1916 } 1917 1918 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1919 assert(N == 1 && "Invalid number of operands!"); 1920 // The constant encodes as the immediate, except for 32, which encodes as 1921 // zero. 1922 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1923 unsigned Imm = CE->getValue(); 1924 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1925 } 1926 1927 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1928 assert(N == 1 && "Invalid number of operands!"); 1929 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1930 // the instruction as well. 1931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1932 int Val = CE->getValue(); 1933 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1934 } 1935 1936 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1937 assert(N == 1 && "Invalid number of operands!"); 1938 // The operand is actually a t2_so_imm, but we have its bitwise 1939 // negation in the assembly source, so twiddle it here. 1940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1941 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1942 } 1943 1944 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1945 assert(N == 1 && "Invalid number of operands!"); 1946 // The operand is actually a t2_so_imm, but we have its 1947 // negation in the assembly source, so twiddle it here. 1948 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1949 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1950 } 1951 1952 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1953 assert(N == 1 && "Invalid number of operands!"); 1954 // The operand is actually an imm0_4095, but we have its 1955 // negation in the assembly source, so twiddle it here. 1956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1957 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1958 } 1959 1960 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { 1961 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) { 1962 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2)); 1963 return; 1964 } 1965 1966 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1967 assert(SR && "Unknown value type!"); 1968 Inst.addOperand(MCOperand::CreateExpr(SR)); 1969 } 1970 1971 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { 1972 assert(N == 1 && "Invalid number of operands!"); 1973 if (isImm()) { 1974 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1975 if (CE) { 1976 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1977 return; 1978 } 1979 1980 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val); 1981 assert(SR && "Unknown value type!"); 1982 Inst.addOperand(MCOperand::CreateExpr(SR)); 1983 return; 1984 } 1985 1986 assert(isMem() && "Unknown value type!"); 1987 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!"); 1988 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue())); 1989 } 1990 1991 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1992 assert(N == 1 && "Invalid number of operands!"); 1993 // The operand is actually a so_imm, but we have its bitwise 1994 // negation in the assembly source, so twiddle it here. 1995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1996 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1997 } 1998 1999 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 2000 assert(N == 1 && "Invalid number of operands!"); 2001 // The operand is actually a so_imm, but we have its 2002 // negation in the assembly source, so twiddle it here. 2003 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2004 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 2005 } 2006 2007 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 2008 assert(N == 1 && "Invalid number of operands!"); 2009 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 2010 } 2011 2012 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { 2013 assert(N == 1 && "Invalid number of operands!"); 2014 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt()))); 2015 } 2016 2017 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 2018 assert(N == 1 && "Invalid number of operands!"); 2019 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2020 } 2021 2022 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 2023 assert(N == 1 && "Invalid number of operands!"); 2024 int32_t Imm = Memory.OffsetImm->getValue(); 2025 Inst.addOperand(MCOperand::CreateImm(Imm)); 2026 } 2027 2028 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 2029 assert(N == 1 && "Invalid number of operands!"); 2030 assert(isImm() && "Not an immediate!"); 2031 2032 // If we have an immediate that's not a constant, treat it as a label 2033 // reference needing a fixup. 2034 if (!isa<MCConstantExpr>(getImm())) { 2035 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2036 return; 2037 } 2038 2039 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2040 int Val = CE->getValue(); 2041 Inst.addOperand(MCOperand::CreateImm(Val)); 2042 } 2043 2044 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 2045 assert(N == 2 && "Invalid number of operands!"); 2046 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2047 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 2048 } 2049 2050 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 2051 addAlignedMemoryOperands(Inst, N); 2052 } 2053 2054 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { 2055 addAlignedMemoryOperands(Inst, N); 2056 } 2057 2058 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2059 addAlignedMemoryOperands(Inst, N); 2060 } 2061 2062 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { 2063 addAlignedMemoryOperands(Inst, N); 2064 } 2065 2066 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2067 addAlignedMemoryOperands(Inst, N); 2068 } 2069 2070 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { 2071 addAlignedMemoryOperands(Inst, N); 2072 } 2073 2074 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2075 addAlignedMemoryOperands(Inst, N); 2076 } 2077 2078 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { 2079 addAlignedMemoryOperands(Inst, N); 2080 } 2081 2082 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2083 addAlignedMemoryOperands(Inst, N); 2084 } 2085 2086 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { 2087 addAlignedMemoryOperands(Inst, N); 2088 } 2089 2090 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { 2091 addAlignedMemoryOperands(Inst, N); 2092 } 2093 2094 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 2095 assert(N == 3 && "Invalid number of operands!"); 2096 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2097 if (!Memory.OffsetRegNum) { 2098 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2099 // Special case for #-0 2100 if (Val == INT32_MIN) Val = 0; 2101 if (Val < 0) Val = -Val; 2102 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2103 } else { 2104 // For register offset, we encode the shift type and negation flag 2105 // here. 2106 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2107 Memory.ShiftImm, Memory.ShiftType); 2108 } 2109 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2110 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2111 Inst.addOperand(MCOperand::CreateImm(Val)); 2112 } 2113 2114 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 2115 assert(N == 2 && "Invalid number of operands!"); 2116 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2117 assert(CE && "non-constant AM2OffsetImm operand!"); 2118 int32_t Val = CE->getValue(); 2119 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2120 // Special case for #-0 2121 if (Val == INT32_MIN) Val = 0; 2122 if (Val < 0) Val = -Val; 2123 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 2124 Inst.addOperand(MCOperand::CreateReg(0)); 2125 Inst.addOperand(MCOperand::CreateImm(Val)); 2126 } 2127 2128 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 2129 assert(N == 3 && "Invalid number of operands!"); 2130 // If we have an immediate that's not a constant, treat it as a label 2131 // reference needing a fixup. If it is a constant, it's something else 2132 // and we reject it. 2133 if (isImm()) { 2134 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2135 Inst.addOperand(MCOperand::CreateReg(0)); 2136 Inst.addOperand(MCOperand::CreateImm(0)); 2137 return; 2138 } 2139 2140 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2141 if (!Memory.OffsetRegNum) { 2142 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2143 // Special case for #-0 2144 if (Val == INT32_MIN) Val = 0; 2145 if (Val < 0) Val = -Val; 2146 Val = ARM_AM::getAM3Opc(AddSub, Val); 2147 } else { 2148 // For register offset, we encode the shift type and negation flag 2149 // here. 2150 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 2151 } 2152 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2153 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2154 Inst.addOperand(MCOperand::CreateImm(Val)); 2155 } 2156 2157 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 2158 assert(N == 2 && "Invalid number of operands!"); 2159 if (Kind == k_PostIndexRegister) { 2160 int32_t Val = 2161 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 2162 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2163 Inst.addOperand(MCOperand::CreateImm(Val)); 2164 return; 2165 } 2166 2167 // Constant offset. 2168 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 2169 int32_t Val = CE->getValue(); 2170 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2171 // Special case for #-0 2172 if (Val == INT32_MIN) Val = 0; 2173 if (Val < 0) Val = -Val; 2174 Val = ARM_AM::getAM3Opc(AddSub, Val); 2175 Inst.addOperand(MCOperand::CreateReg(0)); 2176 Inst.addOperand(MCOperand::CreateImm(Val)); 2177 } 2178 2179 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 2180 assert(N == 2 && "Invalid number of operands!"); 2181 // If we have an immediate that's not a constant, treat it as a label 2182 // reference needing a fixup. If it is a constant, it's something else 2183 // and we reject it. 2184 if (isImm()) { 2185 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2186 Inst.addOperand(MCOperand::CreateImm(0)); 2187 return; 2188 } 2189 2190 // The lower two bits are always zero and as such are not encoded. 2191 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2192 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 2193 // Special case for #-0 2194 if (Val == INT32_MIN) Val = 0; 2195 if (Val < 0) Val = -Val; 2196 Val = ARM_AM::getAM5Opc(AddSub, Val); 2197 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2198 Inst.addOperand(MCOperand::CreateImm(Val)); 2199 } 2200 2201 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 2202 assert(N == 2 && "Invalid number of operands!"); 2203 // If we have an immediate that's not a constant, treat it as a label 2204 // reference needing a fixup. If it is a constant, it's something else 2205 // and we reject it. 2206 if (isImm()) { 2207 Inst.addOperand(MCOperand::CreateExpr(getImm())); 2208 Inst.addOperand(MCOperand::CreateImm(0)); 2209 return; 2210 } 2211 2212 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2213 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2214 Inst.addOperand(MCOperand::CreateImm(Val)); 2215 } 2216 2217 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 2218 assert(N == 2 && "Invalid number of operands!"); 2219 // The lower two bits are always zero and as such are not encoded. 2220 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 2221 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2222 Inst.addOperand(MCOperand::CreateImm(Val)); 2223 } 2224 2225 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2226 assert(N == 2 && "Invalid number of operands!"); 2227 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2228 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2229 Inst.addOperand(MCOperand::CreateImm(Val)); 2230 } 2231 2232 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2233 addMemImm8OffsetOperands(Inst, N); 2234 } 2235 2236 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 2237 addMemImm8OffsetOperands(Inst, N); 2238 } 2239 2240 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2241 assert(N == 2 && "Invalid number of operands!"); 2242 // If this is an immediate, it's a label reference. 2243 if (isImm()) { 2244 addExpr(Inst, getImm()); 2245 Inst.addOperand(MCOperand::CreateImm(0)); 2246 return; 2247 } 2248 2249 // Otherwise, it's a normal memory reg+offset. 2250 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2251 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2252 Inst.addOperand(MCOperand::CreateImm(Val)); 2253 } 2254 2255 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 2256 assert(N == 2 && "Invalid number of operands!"); 2257 // If this is an immediate, it's a label reference. 2258 if (isImm()) { 2259 addExpr(Inst, getImm()); 2260 Inst.addOperand(MCOperand::CreateImm(0)); 2261 return; 2262 } 2263 2264 // Otherwise, it's a normal memory reg+offset. 2265 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 2266 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2267 Inst.addOperand(MCOperand::CreateImm(Val)); 2268 } 2269 2270 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 2271 assert(N == 2 && "Invalid number of operands!"); 2272 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2273 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2274 } 2275 2276 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 2277 assert(N == 2 && "Invalid number of operands!"); 2278 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2279 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2280 } 2281 2282 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2283 assert(N == 3 && "Invalid number of operands!"); 2284 unsigned Val = 2285 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 2286 Memory.ShiftImm, Memory.ShiftType); 2287 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2288 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2289 Inst.addOperand(MCOperand::CreateImm(Val)); 2290 } 2291 2292 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 2293 assert(N == 3 && "Invalid number of operands!"); 2294 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2295 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2296 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 2297 } 2298 2299 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 2300 assert(N == 2 && "Invalid number of operands!"); 2301 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2302 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 2303 } 2304 2305 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 2306 assert(N == 2 && "Invalid number of operands!"); 2307 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2308 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2309 Inst.addOperand(MCOperand::CreateImm(Val)); 2310 } 2311 2312 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 2313 assert(N == 2 && "Invalid number of operands!"); 2314 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 2315 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2316 Inst.addOperand(MCOperand::CreateImm(Val)); 2317 } 2318 2319 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 2320 assert(N == 2 && "Invalid number of operands!"); 2321 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 2322 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2323 Inst.addOperand(MCOperand::CreateImm(Val)); 2324 } 2325 2326 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 2327 assert(N == 2 && "Invalid number of operands!"); 2328 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 2329 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 2330 Inst.addOperand(MCOperand::CreateImm(Val)); 2331 } 2332 2333 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 2334 assert(N == 1 && "Invalid number of operands!"); 2335 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2336 assert(CE && "non-constant post-idx-imm8 operand!"); 2337 int Imm = CE->getValue(); 2338 bool isAdd = Imm >= 0; 2339 if (Imm == INT32_MIN) Imm = 0; 2340 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 2341 Inst.addOperand(MCOperand::CreateImm(Imm)); 2342 } 2343 2344 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 2345 assert(N == 1 && "Invalid number of operands!"); 2346 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2347 assert(CE && "non-constant post-idx-imm8s4 operand!"); 2348 int Imm = CE->getValue(); 2349 bool isAdd = Imm >= 0; 2350 if (Imm == INT32_MIN) Imm = 0; 2351 // Immediate is scaled by 4. 2352 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 2353 Inst.addOperand(MCOperand::CreateImm(Imm)); 2354 } 2355 2356 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 2357 assert(N == 2 && "Invalid number of operands!"); 2358 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2359 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 2360 } 2361 2362 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 2363 assert(N == 2 && "Invalid number of operands!"); 2364 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 2365 // The sign, shift type, and shift amount are encoded in a single operand 2366 // using the AM2 encoding helpers. 2367 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 2368 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 2369 PostIdxReg.ShiftTy); 2370 Inst.addOperand(MCOperand::CreateImm(Imm)); 2371 } 2372 2373 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 2374 assert(N == 1 && "Invalid number of operands!"); 2375 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 2376 } 2377 2378 void addBankedRegOperands(MCInst &Inst, unsigned N) const { 2379 assert(N == 1 && "Invalid number of operands!"); 2380 Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg()))); 2381 } 2382 2383 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 2384 assert(N == 1 && "Invalid number of operands!"); 2385 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 2386 } 2387 2388 void addVecListOperands(MCInst &Inst, unsigned N) const { 2389 assert(N == 1 && "Invalid number of operands!"); 2390 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2391 } 2392 2393 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 2394 assert(N == 2 && "Invalid number of operands!"); 2395 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 2396 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 2397 } 2398 2399 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 2400 assert(N == 1 && "Invalid number of operands!"); 2401 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2402 } 2403 2404 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 2405 assert(N == 1 && "Invalid number of operands!"); 2406 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2407 } 2408 2409 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 2410 assert(N == 1 && "Invalid number of operands!"); 2411 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 2412 } 2413 2414 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 2415 assert(N == 1 && "Invalid number of operands!"); 2416 // The immediate encodes the type of constant as well as the value. 2417 // Mask in that this is an i8 splat. 2418 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2419 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 2420 } 2421 2422 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2423 assert(N == 1 && "Invalid number of operands!"); 2424 // The immediate encodes the type of constant as well as the value. 2425 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2426 unsigned Value = CE->getValue(); 2427 Value = ARM_AM::encodeNEONi16splat(Value); 2428 Inst.addOperand(MCOperand::CreateImm(Value)); 2429 } 2430 2431 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const { 2432 assert(N == 1 && "Invalid number of operands!"); 2433 // The immediate encodes the type of constant as well as the value. 2434 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2435 unsigned Value = CE->getValue(); 2436 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff); 2437 Inst.addOperand(MCOperand::CreateImm(Value)); 2438 } 2439 2440 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2441 assert(N == 1 && "Invalid number of operands!"); 2442 // The immediate encodes the type of constant as well as the value. 2443 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2444 unsigned Value = CE->getValue(); 2445 Value = ARM_AM::encodeNEONi32splat(Value); 2446 Inst.addOperand(MCOperand::CreateImm(Value)); 2447 } 2448 2449 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const { 2450 assert(N == 1 && "Invalid number of operands!"); 2451 // The immediate encodes the type of constant as well as the value. 2452 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2453 unsigned Value = CE->getValue(); 2454 Value = ARM_AM::encodeNEONi32splat(~Value); 2455 Inst.addOperand(MCOperand::CreateImm(Value)); 2456 } 2457 2458 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const { 2459 assert(N == 1 && "Invalid number of operands!"); 2460 // The immediate encodes the type of constant as well as the value. 2461 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2462 unsigned Value = CE->getValue(); 2463 assert((Inst.getOpcode() == ARM::VMOVv8i8 || 2464 Inst.getOpcode() == ARM::VMOVv16i8) && 2465 "All vmvn instructions that wants to replicate non-zero byte " 2466 "always must be replaced with VMOVv8i8 or VMOVv16i8."); 2467 unsigned B = ((~Value) & 0xff); 2468 B |= 0xe00; // cmode = 0b1110 2469 Inst.addOperand(MCOperand::CreateImm(B)); 2470 } 2471 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2472 assert(N == 1 && "Invalid number of operands!"); 2473 // The immediate encodes the type of constant as well as the value. 2474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2475 unsigned Value = CE->getValue(); 2476 if (Value >= 256 && Value <= 0xffff) 2477 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2478 else if (Value > 0xffff && Value <= 0xffffff) 2479 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2480 else if (Value > 0xffffff) 2481 Value = (Value >> 24) | 0x600; 2482 Inst.addOperand(MCOperand::CreateImm(Value)); 2483 } 2484 2485 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const { 2486 assert(N == 1 && "Invalid number of operands!"); 2487 // The immediate encodes the type of constant as well as the value. 2488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2489 unsigned Value = CE->getValue(); 2490 assert((Inst.getOpcode() == ARM::VMOVv8i8 || 2491 Inst.getOpcode() == ARM::VMOVv16i8) && 2492 "All instructions that wants to replicate non-zero byte " 2493 "always must be replaced with VMOVv8i8 or VMOVv16i8."); 2494 unsigned B = Value & 0xff; 2495 B |= 0xe00; // cmode = 0b1110 2496 Inst.addOperand(MCOperand::CreateImm(B)); 2497 } 2498 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2499 assert(N == 1 && "Invalid number of operands!"); 2500 // The immediate encodes the type of constant as well as the value. 2501 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2502 unsigned Value = ~CE->getValue(); 2503 if (Value >= 256 && Value <= 0xffff) 2504 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2505 else if (Value > 0xffff && Value <= 0xffffff) 2506 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2507 else if (Value > 0xffffff) 2508 Value = (Value >> 24) | 0x600; 2509 Inst.addOperand(MCOperand::CreateImm(Value)); 2510 } 2511 2512 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2513 assert(N == 1 && "Invalid number of operands!"); 2514 // The immediate encodes the type of constant as well as the value. 2515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2516 uint64_t Value = CE->getValue(); 2517 unsigned Imm = 0; 2518 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2519 Imm |= (Value & 1) << i; 2520 } 2521 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2522 } 2523 2524 void print(raw_ostream &OS) const override; 2525 2526 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) { 2527 auto Op = make_unique<ARMOperand>(k_ITCondMask); 2528 Op->ITMask.Mask = Mask; 2529 Op->StartLoc = S; 2530 Op->EndLoc = S; 2531 return Op; 2532 } 2533 2534 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC, 2535 SMLoc S) { 2536 auto Op = make_unique<ARMOperand>(k_CondCode); 2537 Op->CC.Val = CC; 2538 Op->StartLoc = S; 2539 Op->EndLoc = S; 2540 return Op; 2541 } 2542 2543 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) { 2544 auto Op = make_unique<ARMOperand>(k_CoprocNum); 2545 Op->Cop.Val = CopVal; 2546 Op->StartLoc = S; 2547 Op->EndLoc = S; 2548 return Op; 2549 } 2550 2551 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) { 2552 auto Op = make_unique<ARMOperand>(k_CoprocReg); 2553 Op->Cop.Val = CopVal; 2554 Op->StartLoc = S; 2555 Op->EndLoc = S; 2556 return Op; 2557 } 2558 2559 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S, 2560 SMLoc E) { 2561 auto Op = make_unique<ARMOperand>(k_CoprocOption); 2562 Op->Cop.Val = Val; 2563 Op->StartLoc = S; 2564 Op->EndLoc = E; 2565 return Op; 2566 } 2567 2568 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) { 2569 auto Op = make_unique<ARMOperand>(k_CCOut); 2570 Op->Reg.RegNum = RegNum; 2571 Op->StartLoc = S; 2572 Op->EndLoc = S; 2573 return Op; 2574 } 2575 2576 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) { 2577 auto Op = make_unique<ARMOperand>(k_Token); 2578 Op->Tok.Data = Str.data(); 2579 Op->Tok.Length = Str.size(); 2580 Op->StartLoc = S; 2581 Op->EndLoc = S; 2582 return Op; 2583 } 2584 2585 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, 2586 SMLoc E) { 2587 auto Op = make_unique<ARMOperand>(k_Register); 2588 Op->Reg.RegNum = RegNum; 2589 Op->StartLoc = S; 2590 Op->EndLoc = E; 2591 return Op; 2592 } 2593 2594 static std::unique_ptr<ARMOperand> 2595 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 2596 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, 2597 SMLoc E) { 2598 auto Op = make_unique<ARMOperand>(k_ShiftedRegister); 2599 Op->RegShiftedReg.ShiftTy = ShTy; 2600 Op->RegShiftedReg.SrcReg = SrcReg; 2601 Op->RegShiftedReg.ShiftReg = ShiftReg; 2602 Op->RegShiftedReg.ShiftImm = ShiftImm; 2603 Op->StartLoc = S; 2604 Op->EndLoc = E; 2605 return Op; 2606 } 2607 2608 static std::unique_ptr<ARMOperand> 2609 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, 2610 unsigned ShiftImm, SMLoc S, SMLoc E) { 2611 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate); 2612 Op->RegShiftedImm.ShiftTy = ShTy; 2613 Op->RegShiftedImm.SrcReg = SrcReg; 2614 Op->RegShiftedImm.ShiftImm = ShiftImm; 2615 Op->StartLoc = S; 2616 Op->EndLoc = E; 2617 return Op; 2618 } 2619 2620 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm, 2621 SMLoc S, SMLoc E) { 2622 auto Op = make_unique<ARMOperand>(k_ShifterImmediate); 2623 Op->ShifterImm.isASR = isASR; 2624 Op->ShifterImm.Imm = Imm; 2625 Op->StartLoc = S; 2626 Op->EndLoc = E; 2627 return Op; 2628 } 2629 2630 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S, 2631 SMLoc E) { 2632 auto Op = make_unique<ARMOperand>(k_RotateImmediate); 2633 Op->RotImm.Imm = Imm; 2634 Op->StartLoc = S; 2635 Op->EndLoc = E; 2636 return Op; 2637 } 2638 2639 static std::unique_ptr<ARMOperand> 2640 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) { 2641 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor); 2642 Op->Bitfield.LSB = LSB; 2643 Op->Bitfield.Width = Width; 2644 Op->StartLoc = S; 2645 Op->EndLoc = E; 2646 return Op; 2647 } 2648 2649 static std::unique_ptr<ARMOperand> 2650 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, 2651 SMLoc StartLoc, SMLoc EndLoc) { 2652 assert (Regs.size() > 0 && "RegList contains no registers?"); 2653 KindTy Kind = k_RegisterList; 2654 2655 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second)) 2656 Kind = k_DPRRegisterList; 2657 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2658 contains(Regs.front().second)) 2659 Kind = k_SPRRegisterList; 2660 2661 // Sort based on the register encoding values. 2662 array_pod_sort(Regs.begin(), Regs.end()); 2663 2664 auto Op = make_unique<ARMOperand>(Kind); 2665 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator 2666 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2667 Op->Registers.push_back(I->second); 2668 Op->StartLoc = StartLoc; 2669 Op->EndLoc = EndLoc; 2670 return Op; 2671 } 2672 2673 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum, 2674 unsigned Count, 2675 bool isDoubleSpaced, 2676 SMLoc S, SMLoc E) { 2677 auto Op = make_unique<ARMOperand>(k_VectorList); 2678 Op->VectorList.RegNum = RegNum; 2679 Op->VectorList.Count = Count; 2680 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2681 Op->StartLoc = S; 2682 Op->EndLoc = E; 2683 return Op; 2684 } 2685 2686 static std::unique_ptr<ARMOperand> 2687 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, 2688 SMLoc S, SMLoc E) { 2689 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes); 2690 Op->VectorList.RegNum = RegNum; 2691 Op->VectorList.Count = Count; 2692 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2693 Op->StartLoc = S; 2694 Op->EndLoc = E; 2695 return Op; 2696 } 2697 2698 static std::unique_ptr<ARMOperand> 2699 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, 2700 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2701 auto Op = make_unique<ARMOperand>(k_VectorListIndexed); 2702 Op->VectorList.RegNum = RegNum; 2703 Op->VectorList.Count = Count; 2704 Op->VectorList.LaneIndex = Index; 2705 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2706 Op->StartLoc = S; 2707 Op->EndLoc = E; 2708 return Op; 2709 } 2710 2711 static std::unique_ptr<ARMOperand> 2712 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) { 2713 auto Op = make_unique<ARMOperand>(k_VectorIndex); 2714 Op->VectorIndex.Val = Idx; 2715 Op->StartLoc = S; 2716 Op->EndLoc = E; 2717 return Op; 2718 } 2719 2720 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S, 2721 SMLoc E) { 2722 auto Op = make_unique<ARMOperand>(k_Immediate); 2723 Op->Imm.Val = Val; 2724 Op->StartLoc = S; 2725 Op->EndLoc = E; 2726 return Op; 2727 } 2728 2729 static std::unique_ptr<ARMOperand> 2730 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, 2731 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, 2732 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, 2733 SMLoc E, SMLoc AlignmentLoc = SMLoc()) { 2734 auto Op = make_unique<ARMOperand>(k_Memory); 2735 Op->Memory.BaseRegNum = BaseRegNum; 2736 Op->Memory.OffsetImm = OffsetImm; 2737 Op->Memory.OffsetRegNum = OffsetRegNum; 2738 Op->Memory.ShiftType = ShiftType; 2739 Op->Memory.ShiftImm = ShiftImm; 2740 Op->Memory.Alignment = Alignment; 2741 Op->Memory.isNegative = isNegative; 2742 Op->StartLoc = S; 2743 Op->EndLoc = E; 2744 Op->AlignmentLoc = AlignmentLoc; 2745 return Op; 2746 } 2747 2748 static std::unique_ptr<ARMOperand> 2749 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, 2750 unsigned ShiftImm, SMLoc S, SMLoc E) { 2751 auto Op = make_unique<ARMOperand>(k_PostIndexRegister); 2752 Op->PostIdxReg.RegNum = RegNum; 2753 Op->PostIdxReg.isAdd = isAdd; 2754 Op->PostIdxReg.ShiftTy = ShiftTy; 2755 Op->PostIdxReg.ShiftImm = ShiftImm; 2756 Op->StartLoc = S; 2757 Op->EndLoc = E; 2758 return Op; 2759 } 2760 2761 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, 2762 SMLoc S) { 2763 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt); 2764 Op->MBOpt.Val = Opt; 2765 Op->StartLoc = S; 2766 Op->EndLoc = S; 2767 return Op; 2768 } 2769 2770 static std::unique_ptr<ARMOperand> 2771 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) { 2772 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt); 2773 Op->ISBOpt.Val = Opt; 2774 Op->StartLoc = S; 2775 Op->EndLoc = S; 2776 return Op; 2777 } 2778 2779 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags, 2780 SMLoc S) { 2781 auto Op = make_unique<ARMOperand>(k_ProcIFlags); 2782 Op->IFlags.Val = IFlags; 2783 Op->StartLoc = S; 2784 Op->EndLoc = S; 2785 return Op; 2786 } 2787 2788 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) { 2789 auto Op = make_unique<ARMOperand>(k_MSRMask); 2790 Op->MMask.Val = MMask; 2791 Op->StartLoc = S; 2792 Op->EndLoc = S; 2793 return Op; 2794 } 2795 2796 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) { 2797 auto Op = make_unique<ARMOperand>(k_BankedReg); 2798 Op->BankedReg.Val = Reg; 2799 Op->StartLoc = S; 2800 Op->EndLoc = S; 2801 return Op; 2802 } 2803 }; 2804 2805 } // end anonymous namespace. 2806 2807 void ARMOperand::print(raw_ostream &OS) const { 2808 switch (Kind) { 2809 case k_CondCode: 2810 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2811 break; 2812 case k_CCOut: 2813 OS << "<ccout " << getReg() << ">"; 2814 break; 2815 case k_ITCondMask: { 2816 static const char *const MaskStr[] = { 2817 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2818 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2819 }; 2820 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2821 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2822 break; 2823 } 2824 case k_CoprocNum: 2825 OS << "<coprocessor number: " << getCoproc() << ">"; 2826 break; 2827 case k_CoprocReg: 2828 OS << "<coprocessor register: " << getCoproc() << ">"; 2829 break; 2830 case k_CoprocOption: 2831 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2832 break; 2833 case k_MSRMask: 2834 OS << "<mask: " << getMSRMask() << ">"; 2835 break; 2836 case k_BankedReg: 2837 OS << "<banked reg: " << getBankedReg() << ">"; 2838 break; 2839 case k_Immediate: 2840 getImm()->print(OS); 2841 break; 2842 case k_MemBarrierOpt: 2843 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">"; 2844 break; 2845 case k_InstSyncBarrierOpt: 2846 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">"; 2847 break; 2848 case k_Memory: 2849 OS << "<memory " 2850 << " base:" << Memory.BaseRegNum; 2851 OS << ">"; 2852 break; 2853 case k_PostIndexRegister: 2854 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2855 << PostIdxReg.RegNum; 2856 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2857 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2858 << PostIdxReg.ShiftImm; 2859 OS << ">"; 2860 break; 2861 case k_ProcIFlags: { 2862 OS << "<ARM_PROC::"; 2863 unsigned IFlags = getProcIFlags(); 2864 for (int i=2; i >= 0; --i) 2865 if (IFlags & (1 << i)) 2866 OS << ARM_PROC::IFlagsToString(1 << i); 2867 OS << ">"; 2868 break; 2869 } 2870 case k_Register: 2871 OS << "<register " << getReg() << ">"; 2872 break; 2873 case k_ShifterImmediate: 2874 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2875 << " #" << ShifterImm.Imm << ">"; 2876 break; 2877 case k_ShiftedRegister: 2878 OS << "<so_reg_reg " 2879 << RegShiftedReg.SrcReg << " " 2880 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2881 << " " << RegShiftedReg.ShiftReg << ">"; 2882 break; 2883 case k_ShiftedImmediate: 2884 OS << "<so_reg_imm " 2885 << RegShiftedImm.SrcReg << " " 2886 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2887 << " #" << RegShiftedImm.ShiftImm << ">"; 2888 break; 2889 case k_RotateImmediate: 2890 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2891 break; 2892 case k_BitfieldDescriptor: 2893 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2894 << ", width: " << Bitfield.Width << ">"; 2895 break; 2896 case k_RegisterList: 2897 case k_DPRRegisterList: 2898 case k_SPRRegisterList: { 2899 OS << "<register_list "; 2900 2901 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2902 for (SmallVectorImpl<unsigned>::const_iterator 2903 I = RegList.begin(), E = RegList.end(); I != E; ) { 2904 OS << *I; 2905 if (++I < E) OS << ", "; 2906 } 2907 2908 OS << ">"; 2909 break; 2910 } 2911 case k_VectorList: 2912 OS << "<vector_list " << VectorList.Count << " * " 2913 << VectorList.RegNum << ">"; 2914 break; 2915 case k_VectorListAllLanes: 2916 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2917 << VectorList.RegNum << ">"; 2918 break; 2919 case k_VectorListIndexed: 2920 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2921 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2922 break; 2923 case k_Token: 2924 OS << "'" << getToken() << "'"; 2925 break; 2926 case k_VectorIndex: 2927 OS << "<vectorindex " << getVectorIndex() << ">"; 2928 break; 2929 } 2930 } 2931 2932 /// @name Auto-generated Match Functions 2933 /// { 2934 2935 static unsigned MatchRegisterName(StringRef Name); 2936 2937 /// } 2938 2939 bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2940 SMLoc &StartLoc, SMLoc &EndLoc) { 2941 StartLoc = Parser.getTok().getLoc(); 2942 EndLoc = Parser.getTok().getEndLoc(); 2943 RegNo = tryParseRegister(); 2944 2945 return (RegNo == (unsigned)-1); 2946 } 2947 2948 /// Try to parse a register name. The token must be an Identifier when called, 2949 /// and if it is a register name the token is eaten and the register number is 2950 /// returned. Otherwise return -1. 2951 /// 2952 int ARMAsmParser::tryParseRegister() { 2953 const AsmToken &Tok = Parser.getTok(); 2954 if (Tok.isNot(AsmToken::Identifier)) return -1; 2955 2956 std::string lowerCase = Tok.getString().lower(); 2957 unsigned RegNum = MatchRegisterName(lowerCase); 2958 if (!RegNum) { 2959 RegNum = StringSwitch<unsigned>(lowerCase) 2960 .Case("r13", ARM::SP) 2961 .Case("r14", ARM::LR) 2962 .Case("r15", ARM::PC) 2963 .Case("ip", ARM::R12) 2964 // Additional register name aliases for 'gas' compatibility. 2965 .Case("a1", ARM::R0) 2966 .Case("a2", ARM::R1) 2967 .Case("a3", ARM::R2) 2968 .Case("a4", ARM::R3) 2969 .Case("v1", ARM::R4) 2970 .Case("v2", ARM::R5) 2971 .Case("v3", ARM::R6) 2972 .Case("v4", ARM::R7) 2973 .Case("v5", ARM::R8) 2974 .Case("v6", ARM::R9) 2975 .Case("v7", ARM::R10) 2976 .Case("v8", ARM::R11) 2977 .Case("sb", ARM::R9) 2978 .Case("sl", ARM::R10) 2979 .Case("fp", ARM::R11) 2980 .Default(0); 2981 } 2982 if (!RegNum) { 2983 // Check for aliases registered via .req. Canonicalize to lower case. 2984 // That's more consistent since register names are case insensitive, and 2985 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2986 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2987 // If no match, return failure. 2988 if (Entry == RegisterReqs.end()) 2989 return -1; 2990 Parser.Lex(); // Eat identifier token. 2991 return Entry->getValue(); 2992 } 2993 2994 // Some FPUs only have 16 D registers, so D16-D31 are invalid 2995 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31) 2996 return -1; 2997 2998 Parser.Lex(); // Eat identifier token. 2999 3000 return RegNum; 3001 } 3002 3003 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 3004 // If a recoverable error occurs, return 1. If an irrecoverable error 3005 // occurs, return -1. An irrecoverable error is one where tokens have been 3006 // consumed in the process of trying to parse the shifter (i.e., when it is 3007 // indeed a shifter operand, but malformed). 3008 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { 3009 SMLoc S = Parser.getTok().getLoc(); 3010 const AsmToken &Tok = Parser.getTok(); 3011 if (Tok.isNot(AsmToken::Identifier)) 3012 return -1; 3013 3014 std::string lowerCase = Tok.getString().lower(); 3015 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 3016 .Case("asl", ARM_AM::lsl) 3017 .Case("lsl", ARM_AM::lsl) 3018 .Case("lsr", ARM_AM::lsr) 3019 .Case("asr", ARM_AM::asr) 3020 .Case("ror", ARM_AM::ror) 3021 .Case("rrx", ARM_AM::rrx) 3022 .Default(ARM_AM::no_shift); 3023 3024 if (ShiftTy == ARM_AM::no_shift) 3025 return 1; 3026 3027 Parser.Lex(); // Eat the operator. 3028 3029 // The source register for the shift has already been added to the 3030 // operand list, so we need to pop it off and combine it into the shifted 3031 // register operand instead. 3032 std::unique_ptr<ARMOperand> PrevOp( 3033 (ARMOperand *)Operands.pop_back_val().release()); 3034 if (!PrevOp->isReg()) 3035 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 3036 int SrcReg = PrevOp->getReg(); 3037 3038 SMLoc EndLoc; 3039 int64_t Imm = 0; 3040 int ShiftReg = 0; 3041 if (ShiftTy == ARM_AM::rrx) { 3042 // RRX Doesn't have an explicit shift amount. The encoder expects 3043 // the shift register to be the same as the source register. Seems odd, 3044 // but OK. 3045 ShiftReg = SrcReg; 3046 } else { 3047 // Figure out if this is shifted by a constant or a register (for non-RRX). 3048 if (Parser.getTok().is(AsmToken::Hash) || 3049 Parser.getTok().is(AsmToken::Dollar)) { 3050 Parser.Lex(); // Eat hash. 3051 SMLoc ImmLoc = Parser.getTok().getLoc(); 3052 const MCExpr *ShiftExpr = nullptr; 3053 if (getParser().parseExpression(ShiftExpr, EndLoc)) { 3054 Error(ImmLoc, "invalid immediate shift value"); 3055 return -1; 3056 } 3057 // The expression must be evaluatable as an immediate. 3058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 3059 if (!CE) { 3060 Error(ImmLoc, "invalid immediate shift value"); 3061 return -1; 3062 } 3063 // Range check the immediate. 3064 // lsl, ror: 0 <= imm <= 31 3065 // lsr, asr: 0 <= imm <= 32 3066 Imm = CE->getValue(); 3067 if (Imm < 0 || 3068 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 3069 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 3070 Error(ImmLoc, "immediate shift value out of range"); 3071 return -1; 3072 } 3073 // shift by zero is a nop. Always send it through as lsl. 3074 // ('as' compatibility) 3075 if (Imm == 0) 3076 ShiftTy = ARM_AM::lsl; 3077 } else if (Parser.getTok().is(AsmToken::Identifier)) { 3078 SMLoc L = Parser.getTok().getLoc(); 3079 EndLoc = Parser.getTok().getEndLoc(); 3080 ShiftReg = tryParseRegister(); 3081 if (ShiftReg == -1) { 3082 Error(L, "expected immediate or register in shift operand"); 3083 return -1; 3084 } 3085 } else { 3086 Error(Parser.getTok().getLoc(), 3087 "expected immediate or register in shift operand"); 3088 return -1; 3089 } 3090 } 3091 3092 if (ShiftReg && ShiftTy != ARM_AM::rrx) 3093 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 3094 ShiftReg, Imm, 3095 S, EndLoc)); 3096 else 3097 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 3098 S, EndLoc)); 3099 3100 return 0; 3101 } 3102 3103 3104 /// Try to parse a register name. The token must be an Identifier when called. 3105 /// If it's a register, an AsmOperand is created. Another AsmOperand is created 3106 /// if there is a "writeback". 'true' if it's not a register. 3107 /// 3108 /// TODO this is likely to change to allow different register types and or to 3109 /// parse for a specific register type. 3110 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { 3111 const AsmToken &RegTok = Parser.getTok(); 3112 int RegNo = tryParseRegister(); 3113 if (RegNo == -1) 3114 return true; 3115 3116 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 3117 RegTok.getEndLoc())); 3118 3119 const AsmToken &ExclaimTok = Parser.getTok(); 3120 if (ExclaimTok.is(AsmToken::Exclaim)) { 3121 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 3122 ExclaimTok.getLoc())); 3123 Parser.Lex(); // Eat exclaim token 3124 return false; 3125 } 3126 3127 // Also check for an index operand. This is only legal for vector registers, 3128 // but that'll get caught OK in operand matching, so we don't need to 3129 // explicitly filter everything else out here. 3130 if (Parser.getTok().is(AsmToken::LBrac)) { 3131 SMLoc SIdx = Parser.getTok().getLoc(); 3132 Parser.Lex(); // Eat left bracket token. 3133 3134 const MCExpr *ImmVal; 3135 if (getParser().parseExpression(ImmVal)) 3136 return true; 3137 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 3138 if (!MCE) 3139 return TokError("immediate value expected for vector index"); 3140 3141 if (Parser.getTok().isNot(AsmToken::RBrac)) 3142 return Error(Parser.getTok().getLoc(), "']' expected"); 3143 3144 SMLoc E = Parser.getTok().getEndLoc(); 3145 Parser.Lex(); // Eat right bracket token. 3146 3147 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 3148 SIdx, E, 3149 getContext())); 3150 } 3151 3152 return false; 3153 } 3154 3155 /// MatchCoprocessorOperandName - Try to parse an coprocessor related 3156 /// instruction with a symbolic operand name. 3157 /// We accept "crN" syntax for GAS compatibility. 3158 /// <operand-name> ::= <prefix><number> 3159 /// If CoprocOp is 'c', then: 3160 /// <prefix> ::= c | cr 3161 /// If CoprocOp is 'p', then : 3162 /// <prefix> ::= p 3163 /// <number> ::= integer in range [0, 15] 3164 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 3165 // Use the same layout as the tablegen'erated register name matcher. Ugly, 3166 // but efficient. 3167 if (Name.size() < 2 || Name[0] != CoprocOp) 3168 return -1; 3169 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); 3170 3171 switch (Name.size()) { 3172 default: return -1; 3173 case 1: 3174 switch (Name[0]) { 3175 default: return -1; 3176 case '0': return 0; 3177 case '1': return 1; 3178 case '2': return 2; 3179 case '3': return 3; 3180 case '4': return 4; 3181 case '5': return 5; 3182 case '6': return 6; 3183 case '7': return 7; 3184 case '8': return 8; 3185 case '9': return 9; 3186 } 3187 case 2: 3188 if (Name[0] != '1') 3189 return -1; 3190 switch (Name[1]) { 3191 default: return -1; 3192 // CP10 and CP11 are VFP/NEON and so vector instructions should be used. 3193 // However, old cores (v5/v6) did use them in that way. 3194 case '0': return 10; 3195 case '1': return 11; 3196 case '2': return 12; 3197 case '3': return 13; 3198 case '4': return 14; 3199 case '5': return 15; 3200 } 3201 } 3202 } 3203 3204 /// parseITCondCode - Try to parse a condition code for an IT instruction. 3205 ARMAsmParser::OperandMatchResultTy 3206 ARMAsmParser::parseITCondCode(OperandVector &Operands) { 3207 SMLoc S = Parser.getTok().getLoc(); 3208 const AsmToken &Tok = Parser.getTok(); 3209 if (!Tok.is(AsmToken::Identifier)) 3210 return MatchOperand_NoMatch; 3211 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 3212 .Case("eq", ARMCC::EQ) 3213 .Case("ne", ARMCC::NE) 3214 .Case("hs", ARMCC::HS) 3215 .Case("cs", ARMCC::HS) 3216 .Case("lo", ARMCC::LO) 3217 .Case("cc", ARMCC::LO) 3218 .Case("mi", ARMCC::MI) 3219 .Case("pl", ARMCC::PL) 3220 .Case("vs", ARMCC::VS) 3221 .Case("vc", ARMCC::VC) 3222 .Case("hi", ARMCC::HI) 3223 .Case("ls", ARMCC::LS) 3224 .Case("ge", ARMCC::GE) 3225 .Case("lt", ARMCC::LT) 3226 .Case("gt", ARMCC::GT) 3227 .Case("le", ARMCC::LE) 3228 .Case("al", ARMCC::AL) 3229 .Default(~0U); 3230 if (CC == ~0U) 3231 return MatchOperand_NoMatch; 3232 Parser.Lex(); // Eat the token. 3233 3234 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 3235 3236 return MatchOperand_Success; 3237 } 3238 3239 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 3240 /// token must be an Identifier when called, and if it is a coprocessor 3241 /// number, the token is eaten and the operand is added to the operand list. 3242 ARMAsmParser::OperandMatchResultTy 3243 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { 3244 SMLoc S = Parser.getTok().getLoc(); 3245 const AsmToken &Tok = Parser.getTok(); 3246 if (Tok.isNot(AsmToken::Identifier)) 3247 return MatchOperand_NoMatch; 3248 3249 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 3250 if (Num == -1) 3251 return MatchOperand_NoMatch; 3252 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions 3253 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11)) 3254 return MatchOperand_NoMatch; 3255 3256 Parser.Lex(); // Eat identifier token. 3257 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 3258 return MatchOperand_Success; 3259 } 3260 3261 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 3262 /// token must be an Identifier when called, and if it is a coprocessor 3263 /// number, the token is eaten and the operand is added to the operand list. 3264 ARMAsmParser::OperandMatchResultTy 3265 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { 3266 SMLoc S = Parser.getTok().getLoc(); 3267 const AsmToken &Tok = Parser.getTok(); 3268 if (Tok.isNot(AsmToken::Identifier)) 3269 return MatchOperand_NoMatch; 3270 3271 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 3272 if (Reg == -1) 3273 return MatchOperand_NoMatch; 3274 3275 Parser.Lex(); // Eat identifier token. 3276 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 3277 return MatchOperand_Success; 3278 } 3279 3280 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 3281 /// coproc_option : '{' imm0_255 '}' 3282 ARMAsmParser::OperandMatchResultTy 3283 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { 3284 SMLoc S = Parser.getTok().getLoc(); 3285 3286 // If this isn't a '{', this isn't a coprocessor immediate operand. 3287 if (Parser.getTok().isNot(AsmToken::LCurly)) 3288 return MatchOperand_NoMatch; 3289 Parser.Lex(); // Eat the '{' 3290 3291 const MCExpr *Expr; 3292 SMLoc Loc = Parser.getTok().getLoc(); 3293 if (getParser().parseExpression(Expr)) { 3294 Error(Loc, "illegal expression"); 3295 return MatchOperand_ParseFail; 3296 } 3297 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3298 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 3299 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 3300 return MatchOperand_ParseFail; 3301 } 3302 int Val = CE->getValue(); 3303 3304 // Check for and consume the closing '}' 3305 if (Parser.getTok().isNot(AsmToken::RCurly)) 3306 return MatchOperand_ParseFail; 3307 SMLoc E = Parser.getTok().getEndLoc(); 3308 Parser.Lex(); // Eat the '}' 3309 3310 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 3311 return MatchOperand_Success; 3312 } 3313 3314 // For register list parsing, we need to map from raw GPR register numbering 3315 // to the enumeration values. The enumeration values aren't sorted by 3316 // register number due to our using "sp", "lr" and "pc" as canonical names. 3317 static unsigned getNextRegister(unsigned Reg) { 3318 // If this is a GPR, we need to do it manually, otherwise we can rely 3319 // on the sort ordering of the enumeration since the other reg-classes 3320 // are sane. 3321 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3322 return Reg + 1; 3323 switch(Reg) { 3324 default: llvm_unreachable("Invalid GPR number!"); 3325 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 3326 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 3327 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 3328 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 3329 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 3330 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 3331 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 3332 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 3333 } 3334 } 3335 3336 // Return the low-subreg of a given Q register. 3337 static unsigned getDRegFromQReg(unsigned QReg) { 3338 switch (QReg) { 3339 default: llvm_unreachable("expected a Q register!"); 3340 case ARM::Q0: return ARM::D0; 3341 case ARM::Q1: return ARM::D2; 3342 case ARM::Q2: return ARM::D4; 3343 case ARM::Q3: return ARM::D6; 3344 case ARM::Q4: return ARM::D8; 3345 case ARM::Q5: return ARM::D10; 3346 case ARM::Q6: return ARM::D12; 3347 case ARM::Q7: return ARM::D14; 3348 case ARM::Q8: return ARM::D16; 3349 case ARM::Q9: return ARM::D18; 3350 case ARM::Q10: return ARM::D20; 3351 case ARM::Q11: return ARM::D22; 3352 case ARM::Q12: return ARM::D24; 3353 case ARM::Q13: return ARM::D26; 3354 case ARM::Q14: return ARM::D28; 3355 case ARM::Q15: return ARM::D30; 3356 } 3357 } 3358 3359 /// Parse a register list. 3360 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) { 3361 assert(Parser.getTok().is(AsmToken::LCurly) && 3362 "Token is not a Left Curly Brace"); 3363 SMLoc S = Parser.getTok().getLoc(); 3364 Parser.Lex(); // Eat '{' token. 3365 SMLoc RegLoc = Parser.getTok().getLoc(); 3366 3367 // Check the first register in the list to see what register class 3368 // this is a list of. 3369 int Reg = tryParseRegister(); 3370 if (Reg == -1) 3371 return Error(RegLoc, "register expected"); 3372 3373 // The reglist instructions have at most 16 registers, so reserve 3374 // space for that many. 3375 int EReg = 0; 3376 SmallVector<std::pair<unsigned, unsigned>, 16> Registers; 3377 3378 // Allow Q regs and just interpret them as the two D sub-registers. 3379 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3380 Reg = getDRegFromQReg(Reg); 3381 EReg = MRI->getEncodingValue(Reg); 3382 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3383 ++Reg; 3384 } 3385 const MCRegisterClass *RC; 3386 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3387 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 3388 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 3389 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 3390 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 3391 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 3392 else 3393 return Error(RegLoc, "invalid register in register list"); 3394 3395 // Store the register. 3396 EReg = MRI->getEncodingValue(Reg); 3397 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3398 3399 // This starts immediately after the first register token in the list, 3400 // so we can see either a comma or a minus (range separator) as a legal 3401 // next token. 3402 while (Parser.getTok().is(AsmToken::Comma) || 3403 Parser.getTok().is(AsmToken::Minus)) { 3404 if (Parser.getTok().is(AsmToken::Minus)) { 3405 Parser.Lex(); // Eat the minus. 3406 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3407 int EndReg = tryParseRegister(); 3408 if (EndReg == -1) 3409 return Error(AfterMinusLoc, "register expected"); 3410 // Allow Q regs and just interpret them as the two D sub-registers. 3411 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3412 EndReg = getDRegFromQReg(EndReg) + 1; 3413 // If the register is the same as the start reg, there's nothing 3414 // more to do. 3415 if (Reg == EndReg) 3416 continue; 3417 // The register must be in the same register class as the first. 3418 if (!RC->contains(EndReg)) 3419 return Error(AfterMinusLoc, "invalid register in register list"); 3420 // Ranges must go from low to high. 3421 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) 3422 return Error(AfterMinusLoc, "bad range in register list"); 3423 3424 // Add all the registers in the range to the register list. 3425 while (Reg != EndReg) { 3426 Reg = getNextRegister(Reg); 3427 EReg = MRI->getEncodingValue(Reg); 3428 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3429 } 3430 continue; 3431 } 3432 Parser.Lex(); // Eat the comma. 3433 RegLoc = Parser.getTok().getLoc(); 3434 int OldReg = Reg; 3435 const AsmToken RegTok = Parser.getTok(); 3436 Reg = tryParseRegister(); 3437 if (Reg == -1) 3438 return Error(RegLoc, "register expected"); 3439 // Allow Q regs and just interpret them as the two D sub-registers. 3440 bool isQReg = false; 3441 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3442 Reg = getDRegFromQReg(Reg); 3443 isQReg = true; 3444 } 3445 // The register must be in the same register class as the first. 3446 if (!RC->contains(Reg)) 3447 return Error(RegLoc, "invalid register in register list"); 3448 // List must be monotonically increasing. 3449 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { 3450 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 3451 Warning(RegLoc, "register list not in ascending order"); 3452 else 3453 return Error(RegLoc, "register list not in ascending order"); 3454 } 3455 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { 3456 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 3457 ") in register list"); 3458 continue; 3459 } 3460 // VFP register lists must also be contiguous. 3461 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 3462 Reg != OldReg + 1) 3463 return Error(RegLoc, "non-contiguous register range"); 3464 EReg = MRI->getEncodingValue(Reg); 3465 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3466 if (isQReg) { 3467 EReg = MRI->getEncodingValue(++Reg); 3468 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg)); 3469 } 3470 } 3471 3472 if (Parser.getTok().isNot(AsmToken::RCurly)) 3473 return Error(Parser.getTok().getLoc(), "'}' expected"); 3474 SMLoc E = Parser.getTok().getEndLoc(); 3475 Parser.Lex(); // Eat '}' token. 3476 3477 // Push the register list operand. 3478 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 3479 3480 // The ARM system instruction variants for LDM/STM have a '^' token here. 3481 if (Parser.getTok().is(AsmToken::Caret)) { 3482 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 3483 Parser.Lex(); // Eat '^' token. 3484 } 3485 3486 return false; 3487 } 3488 3489 // Helper function to parse the lane index for vector lists. 3490 ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3491 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { 3492 Index = 0; // Always return a defined index value. 3493 if (Parser.getTok().is(AsmToken::LBrac)) { 3494 Parser.Lex(); // Eat the '['. 3495 if (Parser.getTok().is(AsmToken::RBrac)) { 3496 // "Dn[]" is the 'all lanes' syntax. 3497 LaneKind = AllLanes; 3498 EndLoc = Parser.getTok().getEndLoc(); 3499 Parser.Lex(); // Eat the ']'. 3500 return MatchOperand_Success; 3501 } 3502 3503 // There's an optional '#' token here. Normally there wouldn't be, but 3504 // inline assemble puts one in, and it's friendly to accept that. 3505 if (Parser.getTok().is(AsmToken::Hash)) 3506 Parser.Lex(); // Eat '#' or '$'. 3507 3508 const MCExpr *LaneIndex; 3509 SMLoc Loc = Parser.getTok().getLoc(); 3510 if (getParser().parseExpression(LaneIndex)) { 3511 Error(Loc, "illegal expression"); 3512 return MatchOperand_ParseFail; 3513 } 3514 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3515 if (!CE) { 3516 Error(Loc, "lane index must be empty or an integer"); 3517 return MatchOperand_ParseFail; 3518 } 3519 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3520 Error(Parser.getTok().getLoc(), "']' expected"); 3521 return MatchOperand_ParseFail; 3522 } 3523 EndLoc = Parser.getTok().getEndLoc(); 3524 Parser.Lex(); // Eat the ']'. 3525 int64_t Val = CE->getValue(); 3526 3527 // FIXME: Make this range check context sensitive for .8, .16, .32. 3528 if (Val < 0 || Val > 7) { 3529 Error(Parser.getTok().getLoc(), "lane index out of range"); 3530 return MatchOperand_ParseFail; 3531 } 3532 Index = Val; 3533 LaneKind = IndexedLane; 3534 return MatchOperand_Success; 3535 } 3536 LaneKind = NoLanes; 3537 return MatchOperand_Success; 3538 } 3539 3540 // parse a vector register list 3541 ARMAsmParser::OperandMatchResultTy 3542 ARMAsmParser::parseVectorList(OperandVector &Operands) { 3543 VectorLaneTy LaneKind; 3544 unsigned LaneIndex; 3545 SMLoc S = Parser.getTok().getLoc(); 3546 // As an extension (to match gas), support a plain D register or Q register 3547 // (without encosing curly braces) as a single or double entry list, 3548 // respectively. 3549 if (Parser.getTok().is(AsmToken::Identifier)) { 3550 SMLoc E = Parser.getTok().getEndLoc(); 3551 int Reg = tryParseRegister(); 3552 if (Reg == -1) 3553 return MatchOperand_NoMatch; 3554 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3555 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3556 if (Res != MatchOperand_Success) 3557 return Res; 3558 switch (LaneKind) { 3559 case NoLanes: 3560 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3561 break; 3562 case AllLanes: 3563 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3564 S, E)); 3565 break; 3566 case IndexedLane: 3567 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3568 LaneIndex, 3569 false, S, E)); 3570 break; 3571 } 3572 return MatchOperand_Success; 3573 } 3574 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3575 Reg = getDRegFromQReg(Reg); 3576 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); 3577 if (Res != MatchOperand_Success) 3578 return Res; 3579 switch (LaneKind) { 3580 case NoLanes: 3581 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3582 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3583 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3584 break; 3585 case AllLanes: 3586 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3587 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3588 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3589 S, E)); 3590 break; 3591 case IndexedLane: 3592 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3593 LaneIndex, 3594 false, S, E)); 3595 break; 3596 } 3597 return MatchOperand_Success; 3598 } 3599 Error(S, "vector register expected"); 3600 return MatchOperand_ParseFail; 3601 } 3602 3603 if (Parser.getTok().isNot(AsmToken::LCurly)) 3604 return MatchOperand_NoMatch; 3605 3606 Parser.Lex(); // Eat '{' token. 3607 SMLoc RegLoc = Parser.getTok().getLoc(); 3608 3609 int Reg = tryParseRegister(); 3610 if (Reg == -1) { 3611 Error(RegLoc, "register expected"); 3612 return MatchOperand_ParseFail; 3613 } 3614 unsigned Count = 1; 3615 int Spacing = 0; 3616 unsigned FirstReg = Reg; 3617 // The list is of D registers, but we also allow Q regs and just interpret 3618 // them as the two D sub-registers. 3619 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3620 FirstReg = Reg = getDRegFromQReg(Reg); 3621 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3622 // it's ambiguous with four-register single spaced. 3623 ++Reg; 3624 ++Count; 3625 } 3626 3627 SMLoc E; 3628 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) 3629 return MatchOperand_ParseFail; 3630 3631 while (Parser.getTok().is(AsmToken::Comma) || 3632 Parser.getTok().is(AsmToken::Minus)) { 3633 if (Parser.getTok().is(AsmToken::Minus)) { 3634 if (!Spacing) 3635 Spacing = 1; // Register range implies a single spaced list. 3636 else if (Spacing == 2) { 3637 Error(Parser.getTok().getLoc(), 3638 "sequential registers in double spaced list"); 3639 return MatchOperand_ParseFail; 3640 } 3641 Parser.Lex(); // Eat the minus. 3642 SMLoc AfterMinusLoc = Parser.getTok().getLoc(); 3643 int EndReg = tryParseRegister(); 3644 if (EndReg == -1) { 3645 Error(AfterMinusLoc, "register expected"); 3646 return MatchOperand_ParseFail; 3647 } 3648 // Allow Q regs and just interpret them as the two D sub-registers. 3649 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3650 EndReg = getDRegFromQReg(EndReg) + 1; 3651 // If the register is the same as the start reg, there's nothing 3652 // more to do. 3653 if (Reg == EndReg) 3654 continue; 3655 // The register must be in the same register class as the first. 3656 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3657 Error(AfterMinusLoc, "invalid register in register list"); 3658 return MatchOperand_ParseFail; 3659 } 3660 // Ranges must go from low to high. 3661 if (Reg > EndReg) { 3662 Error(AfterMinusLoc, "bad range in register list"); 3663 return MatchOperand_ParseFail; 3664 } 3665 // Parse the lane specifier if present. 3666 VectorLaneTy NextLaneKind; 3667 unsigned NextLaneIndex; 3668 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3669 MatchOperand_Success) 3670 return MatchOperand_ParseFail; 3671 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3672 Error(AfterMinusLoc, "mismatched lane index in register list"); 3673 return MatchOperand_ParseFail; 3674 } 3675 3676 // Add all the registers in the range to the register list. 3677 Count += EndReg - Reg; 3678 Reg = EndReg; 3679 continue; 3680 } 3681 Parser.Lex(); // Eat the comma. 3682 RegLoc = Parser.getTok().getLoc(); 3683 int OldReg = Reg; 3684 Reg = tryParseRegister(); 3685 if (Reg == -1) { 3686 Error(RegLoc, "register expected"); 3687 return MatchOperand_ParseFail; 3688 } 3689 // vector register lists must be contiguous. 3690 // It's OK to use the enumeration values directly here rather, as the 3691 // VFP register classes have the enum sorted properly. 3692 // 3693 // The list is of D registers, but we also allow Q regs and just interpret 3694 // them as the two D sub-registers. 3695 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3696 if (!Spacing) 3697 Spacing = 1; // Register range implies a single spaced list. 3698 else if (Spacing == 2) { 3699 Error(RegLoc, 3700 "invalid register in double-spaced list (must be 'D' register')"); 3701 return MatchOperand_ParseFail; 3702 } 3703 Reg = getDRegFromQReg(Reg); 3704 if (Reg != OldReg + 1) { 3705 Error(RegLoc, "non-contiguous register range"); 3706 return MatchOperand_ParseFail; 3707 } 3708 ++Reg; 3709 Count += 2; 3710 // Parse the lane specifier if present. 3711 VectorLaneTy NextLaneKind; 3712 unsigned NextLaneIndex; 3713 SMLoc LaneLoc = Parser.getTok().getLoc(); 3714 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != 3715 MatchOperand_Success) 3716 return MatchOperand_ParseFail; 3717 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3718 Error(LaneLoc, "mismatched lane index in register list"); 3719 return MatchOperand_ParseFail; 3720 } 3721 continue; 3722 } 3723 // Normal D register. 3724 // Figure out the register spacing (single or double) of the list if 3725 // we don't know it already. 3726 if (!Spacing) 3727 Spacing = 1 + (Reg == OldReg + 2); 3728 3729 // Just check that it's contiguous and keep going. 3730 if (Reg != OldReg + Spacing) { 3731 Error(RegLoc, "non-contiguous register range"); 3732 return MatchOperand_ParseFail; 3733 } 3734 ++Count; 3735 // Parse the lane specifier if present. 3736 VectorLaneTy NextLaneKind; 3737 unsigned NextLaneIndex; 3738 SMLoc EndLoc = Parser.getTok().getLoc(); 3739 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) 3740 return MatchOperand_ParseFail; 3741 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3742 Error(EndLoc, "mismatched lane index in register list"); 3743 return MatchOperand_ParseFail; 3744 } 3745 } 3746 3747 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3748 Error(Parser.getTok().getLoc(), "'}' expected"); 3749 return MatchOperand_ParseFail; 3750 } 3751 E = Parser.getTok().getEndLoc(); 3752 Parser.Lex(); // Eat '}' token. 3753 3754 switch (LaneKind) { 3755 case NoLanes: 3756 // Two-register operands have been converted to the 3757 // composite register classes. 3758 if (Count == 2) { 3759 const MCRegisterClass *RC = (Spacing == 1) ? 3760 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3761 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3762 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3763 } 3764 3765 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3766 (Spacing == 2), S, E)); 3767 break; 3768 case AllLanes: 3769 // Two-register operands have been converted to the 3770 // composite register classes. 3771 if (Count == 2) { 3772 const MCRegisterClass *RC = (Spacing == 1) ? 3773 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3774 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3775 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3776 } 3777 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3778 (Spacing == 2), 3779 S, E)); 3780 break; 3781 case IndexedLane: 3782 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3783 LaneIndex, 3784 (Spacing == 2), 3785 S, E)); 3786 break; 3787 } 3788 return MatchOperand_Success; 3789 } 3790 3791 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3792 ARMAsmParser::OperandMatchResultTy 3793 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { 3794 SMLoc S = Parser.getTok().getLoc(); 3795 const AsmToken &Tok = Parser.getTok(); 3796 unsigned Opt; 3797 3798 if (Tok.is(AsmToken::Identifier)) { 3799 StringRef OptStr = Tok.getString(); 3800 3801 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3802 .Case("sy", ARM_MB::SY) 3803 .Case("st", ARM_MB::ST) 3804 .Case("ld", ARM_MB::LD) 3805 .Case("sh", ARM_MB::ISH) 3806 .Case("ish", ARM_MB::ISH) 3807 .Case("shst", ARM_MB::ISHST) 3808 .Case("ishst", ARM_MB::ISHST) 3809 .Case("ishld", ARM_MB::ISHLD) 3810 .Case("nsh", ARM_MB::NSH) 3811 .Case("un", ARM_MB::NSH) 3812 .Case("nshst", ARM_MB::NSHST) 3813 .Case("nshld", ARM_MB::NSHLD) 3814 .Case("unst", ARM_MB::NSHST) 3815 .Case("osh", ARM_MB::OSH) 3816 .Case("oshst", ARM_MB::OSHST) 3817 .Case("oshld", ARM_MB::OSHLD) 3818 .Default(~0U); 3819 3820 // ishld, oshld, nshld and ld are only available from ARMv8. 3821 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || 3822 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) 3823 Opt = ~0U; 3824 3825 if (Opt == ~0U) 3826 return MatchOperand_NoMatch; 3827 3828 Parser.Lex(); // Eat identifier token. 3829 } else if (Tok.is(AsmToken::Hash) || 3830 Tok.is(AsmToken::Dollar) || 3831 Tok.is(AsmToken::Integer)) { 3832 if (Parser.getTok().isNot(AsmToken::Integer)) 3833 Parser.Lex(); // Eat '#' or '$'. 3834 SMLoc Loc = Parser.getTok().getLoc(); 3835 3836 const MCExpr *MemBarrierID; 3837 if (getParser().parseExpression(MemBarrierID)) { 3838 Error(Loc, "illegal expression"); 3839 return MatchOperand_ParseFail; 3840 } 3841 3842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3843 if (!CE) { 3844 Error(Loc, "constant expression expected"); 3845 return MatchOperand_ParseFail; 3846 } 3847 3848 int Val = CE->getValue(); 3849 if (Val & ~0xf) { 3850 Error(Loc, "immediate value out of range"); 3851 return MatchOperand_ParseFail; 3852 } 3853 3854 Opt = ARM_MB::RESERVED_0 + Val; 3855 } else 3856 return MatchOperand_ParseFail; 3857 3858 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3859 return MatchOperand_Success; 3860 } 3861 3862 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. 3863 ARMAsmParser::OperandMatchResultTy 3864 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { 3865 SMLoc S = Parser.getTok().getLoc(); 3866 const AsmToken &Tok = Parser.getTok(); 3867 unsigned Opt; 3868 3869 if (Tok.is(AsmToken::Identifier)) { 3870 StringRef OptStr = Tok.getString(); 3871 3872 if (OptStr.equals_lower("sy")) 3873 Opt = ARM_ISB::SY; 3874 else 3875 return MatchOperand_NoMatch; 3876 3877 Parser.Lex(); // Eat identifier token. 3878 } else if (Tok.is(AsmToken::Hash) || 3879 Tok.is(AsmToken::Dollar) || 3880 Tok.is(AsmToken::Integer)) { 3881 if (Parser.getTok().isNot(AsmToken::Integer)) 3882 Parser.Lex(); // Eat '#' or '$'. 3883 SMLoc Loc = Parser.getTok().getLoc(); 3884 3885 const MCExpr *ISBarrierID; 3886 if (getParser().parseExpression(ISBarrierID)) { 3887 Error(Loc, "illegal expression"); 3888 return MatchOperand_ParseFail; 3889 } 3890 3891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID); 3892 if (!CE) { 3893 Error(Loc, "constant expression expected"); 3894 return MatchOperand_ParseFail; 3895 } 3896 3897 int Val = CE->getValue(); 3898 if (Val & ~0xf) { 3899 Error(Loc, "immediate value out of range"); 3900 return MatchOperand_ParseFail; 3901 } 3902 3903 Opt = ARM_ISB::RESERVED_0 + Val; 3904 } else 3905 return MatchOperand_ParseFail; 3906 3907 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( 3908 (ARM_ISB::InstSyncBOpt)Opt, S)); 3909 return MatchOperand_Success; 3910 } 3911 3912 3913 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3914 ARMAsmParser::OperandMatchResultTy 3915 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { 3916 SMLoc S = Parser.getTok().getLoc(); 3917 const AsmToken &Tok = Parser.getTok(); 3918 if (!Tok.is(AsmToken::Identifier)) 3919 return MatchOperand_NoMatch; 3920 StringRef IFlagsStr = Tok.getString(); 3921 3922 // An iflags string of "none" is interpreted to mean that none of the AIF 3923 // bits are set. Not a terribly useful instruction, but a valid encoding. 3924 unsigned IFlags = 0; 3925 if (IFlagsStr != "none") { 3926 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3927 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3928 .Case("a", ARM_PROC::A) 3929 .Case("i", ARM_PROC::I) 3930 .Case("f", ARM_PROC::F) 3931 .Default(~0U); 3932 3933 // If some specific iflag is already set, it means that some letter is 3934 // present more than once, this is not acceptable. 3935 if (Flag == ~0U || (IFlags & Flag)) 3936 return MatchOperand_NoMatch; 3937 3938 IFlags |= Flag; 3939 } 3940 } 3941 3942 Parser.Lex(); // Eat identifier token. 3943 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3944 return MatchOperand_Success; 3945 } 3946 3947 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3948 ARMAsmParser::OperandMatchResultTy 3949 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { 3950 SMLoc S = Parser.getTok().getLoc(); 3951 const AsmToken &Tok = Parser.getTok(); 3952 if (!Tok.is(AsmToken::Identifier)) 3953 return MatchOperand_NoMatch; 3954 StringRef Mask = Tok.getString(); 3955 3956 if (isMClass()) { 3957 // See ARMv6-M 10.1.1 3958 std::string Name = Mask.lower(); 3959 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3960 // Note: in the documentation: 3961 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3962 // for MSR APSR_nzcvq. 3963 // but we do make it an alias here. This is so to get the "mask encoding" 3964 // bits correct on MSR APSR writes. 3965 // 3966 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3967 // should really only be allowed when writing a special register. Note 3968 // they get dropped in the MRS instruction reading a special register as 3969 // the SYSm field is only 8 bits. 3970 .Case("apsr", 0x800) 3971 .Case("apsr_nzcvq", 0x800) 3972 .Case("apsr_g", 0x400) 3973 .Case("apsr_nzcvqg", 0xc00) 3974 .Case("iapsr", 0x801) 3975 .Case("iapsr_nzcvq", 0x801) 3976 .Case("iapsr_g", 0x401) 3977 .Case("iapsr_nzcvqg", 0xc01) 3978 .Case("eapsr", 0x802) 3979 .Case("eapsr_nzcvq", 0x802) 3980 .Case("eapsr_g", 0x402) 3981 .Case("eapsr_nzcvqg", 0xc02) 3982 .Case("xpsr", 0x803) 3983 .Case("xpsr_nzcvq", 0x803) 3984 .Case("xpsr_g", 0x403) 3985 .Case("xpsr_nzcvqg", 0xc03) 3986 .Case("ipsr", 0x805) 3987 .Case("epsr", 0x806) 3988 .Case("iepsr", 0x807) 3989 .Case("msp", 0x808) 3990 .Case("psp", 0x809) 3991 .Case("primask", 0x810) 3992 .Case("basepri", 0x811) 3993 .Case("basepri_max", 0x812) 3994 .Case("faultmask", 0x813) 3995 .Case("control", 0x814) 3996 .Default(~0U); 3997 3998 if (FlagsVal == ~0U) 3999 return MatchOperand_NoMatch; 4000 4001 if (!hasThumb2DSP() && (FlagsVal & 0x400)) 4002 // The _g and _nzcvqg versions are only valid if the DSP extension is 4003 // available. 4004 return MatchOperand_NoMatch; 4005 4006 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 4007 // basepri, basepri_max and faultmask only valid for V7m. 4008 return MatchOperand_NoMatch; 4009 4010 Parser.Lex(); // Eat identifier token. 4011 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 4012 return MatchOperand_Success; 4013 } 4014 4015 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 4016 size_t Start = 0, Next = Mask.find('_'); 4017 StringRef Flags = ""; 4018 std::string SpecReg = Mask.slice(Start, Next).lower(); 4019 if (Next != StringRef::npos) 4020 Flags = Mask.slice(Next+1, Mask.size()); 4021 4022 // FlagsVal contains the complete mask: 4023 // 3-0: Mask 4024 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4025 unsigned FlagsVal = 0; 4026 4027 if (SpecReg == "apsr") { 4028 FlagsVal = StringSwitch<unsigned>(Flags) 4029 .Case("nzcvq", 0x8) // same as CPSR_f 4030 .Case("g", 0x4) // same as CPSR_s 4031 .Case("nzcvqg", 0xc) // same as CPSR_fs 4032 .Default(~0U); 4033 4034 if (FlagsVal == ~0U) { 4035 if (!Flags.empty()) 4036 return MatchOperand_NoMatch; 4037 else 4038 FlagsVal = 8; // No flag 4039 } 4040 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 4041 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 4042 if (Flags == "all" || Flags == "") 4043 Flags = "fc"; 4044 for (int i = 0, e = Flags.size(); i != e; ++i) { 4045 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 4046 .Case("c", 1) 4047 .Case("x", 2) 4048 .Case("s", 4) 4049 .Case("f", 8) 4050 .Default(~0U); 4051 4052 // If some specific flag is already set, it means that some letter is 4053 // present more than once, this is not acceptable. 4054 if (FlagsVal == ~0U || (FlagsVal & Flag)) 4055 return MatchOperand_NoMatch; 4056 FlagsVal |= Flag; 4057 } 4058 } else // No match for special register. 4059 return MatchOperand_NoMatch; 4060 4061 // Special register without flags is NOT equivalent to "fc" flags. 4062 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 4063 // two lines would enable gas compatibility at the expense of breaking 4064 // round-tripping. 4065 // 4066 // if (!FlagsVal) 4067 // FlagsVal = 0x9; 4068 4069 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 4070 if (SpecReg == "spsr") 4071 FlagsVal |= 16; 4072 4073 Parser.Lex(); // Eat identifier token. 4074 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 4075 return MatchOperand_Success; 4076 } 4077 4078 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for 4079 /// use in the MRS/MSR instructions added to support virtualization. 4080 ARMAsmParser::OperandMatchResultTy 4081 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { 4082 SMLoc S = Parser.getTok().getLoc(); 4083 const AsmToken &Tok = Parser.getTok(); 4084 if (!Tok.is(AsmToken::Identifier)) 4085 return MatchOperand_NoMatch; 4086 StringRef RegName = Tok.getString(); 4087 4088 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM 4089 // and bit 5 is R. 4090 unsigned Encoding = StringSwitch<unsigned>(RegName.lower()) 4091 .Case("r8_usr", 0x00) 4092 .Case("r9_usr", 0x01) 4093 .Case("r10_usr", 0x02) 4094 .Case("r11_usr", 0x03) 4095 .Case("r12_usr", 0x04) 4096 .Case("sp_usr", 0x05) 4097 .Case("lr_usr", 0x06) 4098 .Case("r8_fiq", 0x08) 4099 .Case("r9_fiq", 0x09) 4100 .Case("r10_fiq", 0x0a) 4101 .Case("r11_fiq", 0x0b) 4102 .Case("r12_fiq", 0x0c) 4103 .Case("sp_fiq", 0x0d) 4104 .Case("lr_fiq", 0x0e) 4105 .Case("lr_irq", 0x10) 4106 .Case("sp_irq", 0x11) 4107 .Case("lr_svc", 0x12) 4108 .Case("sp_svc", 0x13) 4109 .Case("lr_abt", 0x14) 4110 .Case("sp_abt", 0x15) 4111 .Case("lr_und", 0x16) 4112 .Case("sp_und", 0x17) 4113 .Case("lr_mon", 0x1c) 4114 .Case("sp_mon", 0x1d) 4115 .Case("elr_hyp", 0x1e) 4116 .Case("sp_hyp", 0x1f) 4117 .Case("spsr_fiq", 0x2e) 4118 .Case("spsr_irq", 0x30) 4119 .Case("spsr_svc", 0x32) 4120 .Case("spsr_abt", 0x34) 4121 .Case("spsr_und", 0x36) 4122 .Case("spsr_mon", 0x3c) 4123 .Case("spsr_hyp", 0x3e) 4124 .Default(~0U); 4125 4126 if (Encoding == ~0U) 4127 return MatchOperand_NoMatch; 4128 4129 Parser.Lex(); // Eat identifier token. 4130 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); 4131 return MatchOperand_Success; 4132 } 4133 4134 ARMAsmParser::OperandMatchResultTy 4135 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, 4136 int High) { 4137 const AsmToken &Tok = Parser.getTok(); 4138 if (Tok.isNot(AsmToken::Identifier)) { 4139 Error(Parser.getTok().getLoc(), Op + " operand expected."); 4140 return MatchOperand_ParseFail; 4141 } 4142 StringRef ShiftName = Tok.getString(); 4143 std::string LowerOp = Op.lower(); 4144 std::string UpperOp = Op.upper(); 4145 if (ShiftName != LowerOp && ShiftName != UpperOp) { 4146 Error(Parser.getTok().getLoc(), Op + " operand expected."); 4147 return MatchOperand_ParseFail; 4148 } 4149 Parser.Lex(); // Eat shift type token. 4150 4151 // There must be a '#' and a shift amount. 4152 if (Parser.getTok().isNot(AsmToken::Hash) && 4153 Parser.getTok().isNot(AsmToken::Dollar)) { 4154 Error(Parser.getTok().getLoc(), "'#' expected"); 4155 return MatchOperand_ParseFail; 4156 } 4157 Parser.Lex(); // Eat hash token. 4158 4159 const MCExpr *ShiftAmount; 4160 SMLoc Loc = Parser.getTok().getLoc(); 4161 SMLoc EndLoc; 4162 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4163 Error(Loc, "illegal expression"); 4164 return MatchOperand_ParseFail; 4165 } 4166 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4167 if (!CE) { 4168 Error(Loc, "constant expression expected"); 4169 return MatchOperand_ParseFail; 4170 } 4171 int Val = CE->getValue(); 4172 if (Val < Low || Val > High) { 4173 Error(Loc, "immediate value out of range"); 4174 return MatchOperand_ParseFail; 4175 } 4176 4177 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); 4178 4179 return MatchOperand_Success; 4180 } 4181 4182 ARMAsmParser::OperandMatchResultTy 4183 ARMAsmParser::parseSetEndImm(OperandVector &Operands) { 4184 const AsmToken &Tok = Parser.getTok(); 4185 SMLoc S = Tok.getLoc(); 4186 if (Tok.isNot(AsmToken::Identifier)) { 4187 Error(S, "'be' or 'le' operand expected"); 4188 return MatchOperand_ParseFail; 4189 } 4190 int Val = StringSwitch<int>(Tok.getString().lower()) 4191 .Case("be", 1) 4192 .Case("le", 0) 4193 .Default(-1); 4194 Parser.Lex(); // Eat the token. 4195 4196 if (Val == -1) { 4197 Error(S, "'be' or 'le' operand expected"); 4198 return MatchOperand_ParseFail; 4199 } 4200 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 4201 getContext()), 4202 S, Tok.getEndLoc())); 4203 return MatchOperand_Success; 4204 } 4205 4206 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 4207 /// instructions. Legal values are: 4208 /// lsl #n 'n' in [0,31] 4209 /// asr #n 'n' in [1,32] 4210 /// n == 32 encoded as n == 0. 4211 ARMAsmParser::OperandMatchResultTy 4212 ARMAsmParser::parseShifterImm(OperandVector &Operands) { 4213 const AsmToken &Tok = Parser.getTok(); 4214 SMLoc S = Tok.getLoc(); 4215 if (Tok.isNot(AsmToken::Identifier)) { 4216 Error(S, "shift operator 'asr' or 'lsl' expected"); 4217 return MatchOperand_ParseFail; 4218 } 4219 StringRef ShiftName = Tok.getString(); 4220 bool isASR; 4221 if (ShiftName == "lsl" || ShiftName == "LSL") 4222 isASR = false; 4223 else if (ShiftName == "asr" || ShiftName == "ASR") 4224 isASR = true; 4225 else { 4226 Error(S, "shift operator 'asr' or 'lsl' expected"); 4227 return MatchOperand_ParseFail; 4228 } 4229 Parser.Lex(); // Eat the operator. 4230 4231 // A '#' and a shift amount. 4232 if (Parser.getTok().isNot(AsmToken::Hash) && 4233 Parser.getTok().isNot(AsmToken::Dollar)) { 4234 Error(Parser.getTok().getLoc(), "'#' expected"); 4235 return MatchOperand_ParseFail; 4236 } 4237 Parser.Lex(); // Eat hash token. 4238 SMLoc ExLoc = Parser.getTok().getLoc(); 4239 4240 const MCExpr *ShiftAmount; 4241 SMLoc EndLoc; 4242 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4243 Error(ExLoc, "malformed shift expression"); 4244 return MatchOperand_ParseFail; 4245 } 4246 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4247 if (!CE) { 4248 Error(ExLoc, "shift amount must be an immediate"); 4249 return MatchOperand_ParseFail; 4250 } 4251 4252 int64_t Val = CE->getValue(); 4253 if (isASR) { 4254 // Shift amount must be in [1,32] 4255 if (Val < 1 || Val > 32) { 4256 Error(ExLoc, "'asr' shift amount must be in range [1,32]"); 4257 return MatchOperand_ParseFail; 4258 } 4259 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 4260 if (isThumb() && Val == 32) { 4261 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); 4262 return MatchOperand_ParseFail; 4263 } 4264 if (Val == 32) Val = 0; 4265 } else { 4266 // Shift amount must be in [1,32] 4267 if (Val < 0 || Val > 31) { 4268 Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); 4269 return MatchOperand_ParseFail; 4270 } 4271 } 4272 4273 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); 4274 4275 return MatchOperand_Success; 4276 } 4277 4278 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 4279 /// of instructions. Legal values are: 4280 /// ror #n 'n' in {0, 8, 16, 24} 4281 ARMAsmParser::OperandMatchResultTy 4282 ARMAsmParser::parseRotImm(OperandVector &Operands) { 4283 const AsmToken &Tok = Parser.getTok(); 4284 SMLoc S = Tok.getLoc(); 4285 if (Tok.isNot(AsmToken::Identifier)) 4286 return MatchOperand_NoMatch; 4287 StringRef ShiftName = Tok.getString(); 4288 if (ShiftName != "ror" && ShiftName != "ROR") 4289 return MatchOperand_NoMatch; 4290 Parser.Lex(); // Eat the operator. 4291 4292 // A '#' and a rotate amount. 4293 if (Parser.getTok().isNot(AsmToken::Hash) && 4294 Parser.getTok().isNot(AsmToken::Dollar)) { 4295 Error(Parser.getTok().getLoc(), "'#' expected"); 4296 return MatchOperand_ParseFail; 4297 } 4298 Parser.Lex(); // Eat hash token. 4299 SMLoc ExLoc = Parser.getTok().getLoc(); 4300 4301 const MCExpr *ShiftAmount; 4302 SMLoc EndLoc; 4303 if (getParser().parseExpression(ShiftAmount, EndLoc)) { 4304 Error(ExLoc, "malformed rotate expression"); 4305 return MatchOperand_ParseFail; 4306 } 4307 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 4308 if (!CE) { 4309 Error(ExLoc, "rotate amount must be an immediate"); 4310 return MatchOperand_ParseFail; 4311 } 4312 4313 int64_t Val = CE->getValue(); 4314 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 4315 // normally, zero is represented in asm by omitting the rotate operand 4316 // entirely. 4317 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 4318 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); 4319 return MatchOperand_ParseFail; 4320 } 4321 4322 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); 4323 4324 return MatchOperand_Success; 4325 } 4326 4327 ARMAsmParser::OperandMatchResultTy 4328 ARMAsmParser::parseBitfield(OperandVector &Operands) { 4329 SMLoc S = Parser.getTok().getLoc(); 4330 // The bitfield descriptor is really two operands, the LSB and the width. 4331 if (Parser.getTok().isNot(AsmToken::Hash) && 4332 Parser.getTok().isNot(AsmToken::Dollar)) { 4333 Error(Parser.getTok().getLoc(), "'#' expected"); 4334 return MatchOperand_ParseFail; 4335 } 4336 Parser.Lex(); // Eat hash token. 4337 4338 const MCExpr *LSBExpr; 4339 SMLoc E = Parser.getTok().getLoc(); 4340 if (getParser().parseExpression(LSBExpr)) { 4341 Error(E, "malformed immediate expression"); 4342 return MatchOperand_ParseFail; 4343 } 4344 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 4345 if (!CE) { 4346 Error(E, "'lsb' operand must be an immediate"); 4347 return MatchOperand_ParseFail; 4348 } 4349 4350 int64_t LSB = CE->getValue(); 4351 // The LSB must be in the range [0,31] 4352 if (LSB < 0 || LSB > 31) { 4353 Error(E, "'lsb' operand must be in the range [0,31]"); 4354 return MatchOperand_ParseFail; 4355 } 4356 E = Parser.getTok().getLoc(); 4357 4358 // Expect another immediate operand. 4359 if (Parser.getTok().isNot(AsmToken::Comma)) { 4360 Error(Parser.getTok().getLoc(), "too few operands"); 4361 return MatchOperand_ParseFail; 4362 } 4363 Parser.Lex(); // Eat hash token. 4364 if (Parser.getTok().isNot(AsmToken::Hash) && 4365 Parser.getTok().isNot(AsmToken::Dollar)) { 4366 Error(Parser.getTok().getLoc(), "'#' expected"); 4367 return MatchOperand_ParseFail; 4368 } 4369 Parser.Lex(); // Eat hash token. 4370 4371 const MCExpr *WidthExpr; 4372 SMLoc EndLoc; 4373 if (getParser().parseExpression(WidthExpr, EndLoc)) { 4374 Error(E, "malformed immediate expression"); 4375 return MatchOperand_ParseFail; 4376 } 4377 CE = dyn_cast<MCConstantExpr>(WidthExpr); 4378 if (!CE) { 4379 Error(E, "'width' operand must be an immediate"); 4380 return MatchOperand_ParseFail; 4381 } 4382 4383 int64_t Width = CE->getValue(); 4384 // The LSB must be in the range [1,32-lsb] 4385 if (Width < 1 || Width > 32 - LSB) { 4386 Error(E, "'width' operand must be in the range [1,32-lsb]"); 4387 return MatchOperand_ParseFail; 4388 } 4389 4390 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); 4391 4392 return MatchOperand_Success; 4393 } 4394 4395 ARMAsmParser::OperandMatchResultTy 4396 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { 4397 // Check for a post-index addressing register operand. Specifically: 4398 // postidx_reg := '+' register {, shift} 4399 // | '-' register {, shift} 4400 // | register {, shift} 4401 4402 // This method must return MatchOperand_NoMatch without consuming any tokens 4403 // in the case where there is no match, as other alternatives take other 4404 // parse methods. 4405 AsmToken Tok = Parser.getTok(); 4406 SMLoc S = Tok.getLoc(); 4407 bool haveEaten = false; 4408 bool isAdd = true; 4409 if (Tok.is(AsmToken::Plus)) { 4410 Parser.Lex(); // Eat the '+' token. 4411 haveEaten = true; 4412 } else if (Tok.is(AsmToken::Minus)) { 4413 Parser.Lex(); // Eat the '-' token. 4414 isAdd = false; 4415 haveEaten = true; 4416 } 4417 4418 SMLoc E = Parser.getTok().getEndLoc(); 4419 int Reg = tryParseRegister(); 4420 if (Reg == -1) { 4421 if (!haveEaten) 4422 return MatchOperand_NoMatch; 4423 Error(Parser.getTok().getLoc(), "register expected"); 4424 return MatchOperand_ParseFail; 4425 } 4426 4427 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 4428 unsigned ShiftImm = 0; 4429 if (Parser.getTok().is(AsmToken::Comma)) { 4430 Parser.Lex(); // Eat the ','. 4431 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 4432 return MatchOperand_ParseFail; 4433 4434 // FIXME: Only approximates end...may include intervening whitespace. 4435 E = Parser.getTok().getLoc(); 4436 } 4437 4438 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 4439 ShiftImm, S, E)); 4440 4441 return MatchOperand_Success; 4442 } 4443 4444 ARMAsmParser::OperandMatchResultTy 4445 ARMAsmParser::parseAM3Offset(OperandVector &Operands) { 4446 // Check for a post-index addressing register operand. Specifically: 4447 // am3offset := '+' register 4448 // | '-' register 4449 // | register 4450 // | # imm 4451 // | # + imm 4452 // | # - imm 4453 4454 // This method must return MatchOperand_NoMatch without consuming any tokens 4455 // in the case where there is no match, as other alternatives take other 4456 // parse methods. 4457 AsmToken Tok = Parser.getTok(); 4458 SMLoc S = Tok.getLoc(); 4459 4460 // Do immediates first, as we always parse those if we have a '#'. 4461 if (Parser.getTok().is(AsmToken::Hash) || 4462 Parser.getTok().is(AsmToken::Dollar)) { 4463 Parser.Lex(); // Eat '#' or '$'. 4464 // Explicitly look for a '-', as we need to encode negative zero 4465 // differently. 4466 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4467 const MCExpr *Offset; 4468 SMLoc E; 4469 if (getParser().parseExpression(Offset, E)) 4470 return MatchOperand_ParseFail; 4471 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4472 if (!CE) { 4473 Error(S, "constant expression expected"); 4474 return MatchOperand_ParseFail; 4475 } 4476 // Negative zero is encoded as the flag value INT32_MIN. 4477 int32_t Val = CE->getValue(); 4478 if (isNegative && Val == 0) 4479 Val = INT32_MIN; 4480 4481 Operands.push_back( 4482 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 4483 4484 return MatchOperand_Success; 4485 } 4486 4487 4488 bool haveEaten = false; 4489 bool isAdd = true; 4490 if (Tok.is(AsmToken::Plus)) { 4491 Parser.Lex(); // Eat the '+' token. 4492 haveEaten = true; 4493 } else if (Tok.is(AsmToken::Minus)) { 4494 Parser.Lex(); // Eat the '-' token. 4495 isAdd = false; 4496 haveEaten = true; 4497 } 4498 4499 Tok = Parser.getTok(); 4500 int Reg = tryParseRegister(); 4501 if (Reg == -1) { 4502 if (!haveEaten) 4503 return MatchOperand_NoMatch; 4504 Error(Tok.getLoc(), "register expected"); 4505 return MatchOperand_ParseFail; 4506 } 4507 4508 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 4509 0, S, Tok.getEndLoc())); 4510 4511 return MatchOperand_Success; 4512 } 4513 4514 /// Convert parsed operands to MCInst. Needed here because this instruction 4515 /// only has two register operands, but multiplication is commutative so 4516 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". 4517 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst, 4518 const OperandVector &Operands) { 4519 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); 4520 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); 4521 // If we have a three-operand form, make sure to set Rn to be the operand 4522 // that isn't the same as Rd. 4523 unsigned RegOp = 4; 4524 if (Operands.size() == 6 && 4525 ((ARMOperand &)*Operands[4]).getReg() == 4526 ((ARMOperand &)*Operands[3]).getReg()) 4527 RegOp = 5; 4528 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); 4529 Inst.addOperand(Inst.getOperand(0)); 4530 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); 4531 } 4532 4533 void ARMAsmParser::cvtThumbBranches(MCInst &Inst, 4534 const OperandVector &Operands) { 4535 int CondOp = -1, ImmOp = -1; 4536 switch(Inst.getOpcode()) { 4537 case ARM::tB: 4538 case ARM::tBcc: CondOp = 1; ImmOp = 2; break; 4539 4540 case ARM::t2B: 4541 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; 4542 4543 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches"); 4544 } 4545 // first decide whether or not the branch should be conditional 4546 // by looking at it's location relative to an IT block 4547 if(inITBlock()) { 4548 // inside an IT block we cannot have any conditional branches. any 4549 // such instructions needs to be converted to unconditional form 4550 switch(Inst.getOpcode()) { 4551 case ARM::tBcc: Inst.setOpcode(ARM::tB); break; 4552 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; 4553 } 4554 } else { 4555 // outside IT blocks we can only have unconditional branches with AL 4556 // condition code or conditional branches with non-AL condition code 4557 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); 4558 switch(Inst.getOpcode()) { 4559 case ARM::tB: 4560 case ARM::tBcc: 4561 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); 4562 break; 4563 case ARM::t2B: 4564 case ARM::t2Bcc: 4565 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); 4566 break; 4567 } 4568 } 4569 4570 // now decide on encoding size based on branch target range 4571 switch(Inst.getOpcode()) { 4572 // classify tB as either t2B or t1B based on range of immediate operand 4573 case ARM::tB: { 4574 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); 4575 if (!op.isSignedOffset<11, 1>() && isThumbTwo()) 4576 Inst.setOpcode(ARM::t2B); 4577 break; 4578 } 4579 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand 4580 case ARM::tBcc: { 4581 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); 4582 if (!op.isSignedOffset<8, 1>() && isThumbTwo()) 4583 Inst.setOpcode(ARM::t2Bcc); 4584 break; 4585 } 4586 } 4587 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); 4588 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); 4589 } 4590 4591 /// Parse an ARM memory expression, return false if successful else return true 4592 /// or an error. The first token must be a '[' when called. 4593 bool ARMAsmParser::parseMemory(OperandVector &Operands) { 4594 SMLoc S, E; 4595 assert(Parser.getTok().is(AsmToken::LBrac) && 4596 "Token is not a Left Bracket"); 4597 S = Parser.getTok().getLoc(); 4598 Parser.Lex(); // Eat left bracket token. 4599 4600 const AsmToken &BaseRegTok = Parser.getTok(); 4601 int BaseRegNum = tryParseRegister(); 4602 if (BaseRegNum == -1) 4603 return Error(BaseRegTok.getLoc(), "register expected"); 4604 4605 // The next token must either be a comma, a colon or a closing bracket. 4606 const AsmToken &Tok = Parser.getTok(); 4607 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && 4608 !Tok.is(AsmToken::RBrac)) 4609 return Error(Tok.getLoc(), "malformed memory operand"); 4610 4611 if (Tok.is(AsmToken::RBrac)) { 4612 E = Tok.getEndLoc(); 4613 Parser.Lex(); // Eat right bracket token. 4614 4615 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, 4616 ARM_AM::no_shift, 0, 0, false, 4617 S, E)); 4618 4619 // If there's a pre-indexing writeback marker, '!', just add it as a token 4620 // operand. It's rather odd, but syntactically valid. 4621 if (Parser.getTok().is(AsmToken::Exclaim)) { 4622 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4623 Parser.Lex(); // Eat the '!'. 4624 } 4625 4626 return false; 4627 } 4628 4629 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && 4630 "Lost colon or comma in memory operand?!"); 4631 if (Tok.is(AsmToken::Comma)) { 4632 Parser.Lex(); // Eat the comma. 4633 } 4634 4635 // If we have a ':', it's an alignment specifier. 4636 if (Parser.getTok().is(AsmToken::Colon)) { 4637 Parser.Lex(); // Eat the ':'. 4638 E = Parser.getTok().getLoc(); 4639 SMLoc AlignmentLoc = Tok.getLoc(); 4640 4641 const MCExpr *Expr; 4642 if (getParser().parseExpression(Expr)) 4643 return true; 4644 4645 // The expression has to be a constant. Memory references with relocations 4646 // don't come through here, as they use the <label> forms of the relevant 4647 // instructions. 4648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4649 if (!CE) 4650 return Error (E, "constant expression expected"); 4651 4652 unsigned Align = 0; 4653 switch (CE->getValue()) { 4654 default: 4655 return Error(E, 4656 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4657 case 16: Align = 2; break; 4658 case 32: Align = 4; break; 4659 case 64: Align = 8; break; 4660 case 128: Align = 16; break; 4661 case 256: Align = 32; break; 4662 } 4663 4664 // Now we should have the closing ']' 4665 if (Parser.getTok().isNot(AsmToken::RBrac)) 4666 return Error(Parser.getTok().getLoc(), "']' expected"); 4667 E = Parser.getTok().getEndLoc(); 4668 Parser.Lex(); // Eat right bracket token. 4669 4670 // Don't worry about range checking the value here. That's handled by 4671 // the is*() predicates. 4672 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, 4673 ARM_AM::no_shift, 0, Align, 4674 false, S, E, AlignmentLoc)); 4675 4676 // If there's a pre-indexing writeback marker, '!', just add it as a token 4677 // operand. 4678 if (Parser.getTok().is(AsmToken::Exclaim)) { 4679 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4680 Parser.Lex(); // Eat the '!'. 4681 } 4682 4683 return false; 4684 } 4685 4686 // If we have a '#', it's an immediate offset, else assume it's a register 4687 // offset. Be friendly and also accept a plain integer (without a leading 4688 // hash) for gas compatibility. 4689 if (Parser.getTok().is(AsmToken::Hash) || 4690 Parser.getTok().is(AsmToken::Dollar) || 4691 Parser.getTok().is(AsmToken::Integer)) { 4692 if (Parser.getTok().isNot(AsmToken::Integer)) 4693 Parser.Lex(); // Eat '#' or '$'. 4694 E = Parser.getTok().getLoc(); 4695 4696 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4697 const MCExpr *Offset; 4698 if (getParser().parseExpression(Offset)) 4699 return true; 4700 4701 // The expression has to be a constant. Memory references with relocations 4702 // don't come through here, as they use the <label> forms of the relevant 4703 // instructions. 4704 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4705 if (!CE) 4706 return Error (E, "constant expression expected"); 4707 4708 // If the constant was #-0, represent it as INT32_MIN. 4709 int32_t Val = CE->getValue(); 4710 if (isNegative && Val == 0) 4711 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4712 4713 // Now we should have the closing ']' 4714 if (Parser.getTok().isNot(AsmToken::RBrac)) 4715 return Error(Parser.getTok().getLoc(), "']' expected"); 4716 E = Parser.getTok().getEndLoc(); 4717 Parser.Lex(); // Eat right bracket token. 4718 4719 // Don't worry about range checking the value here. That's handled by 4720 // the is*() predicates. 4721 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4722 ARM_AM::no_shift, 0, 0, 4723 false, S, E)); 4724 4725 // If there's a pre-indexing writeback marker, '!', just add it as a token 4726 // operand. 4727 if (Parser.getTok().is(AsmToken::Exclaim)) { 4728 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4729 Parser.Lex(); // Eat the '!'. 4730 } 4731 4732 return false; 4733 } 4734 4735 // The register offset is optionally preceded by a '+' or '-' 4736 bool isNegative = false; 4737 if (Parser.getTok().is(AsmToken::Minus)) { 4738 isNegative = true; 4739 Parser.Lex(); // Eat the '-'. 4740 } else if (Parser.getTok().is(AsmToken::Plus)) { 4741 // Nothing to do. 4742 Parser.Lex(); // Eat the '+'. 4743 } 4744 4745 E = Parser.getTok().getLoc(); 4746 int OffsetRegNum = tryParseRegister(); 4747 if (OffsetRegNum == -1) 4748 return Error(E, "register expected"); 4749 4750 // If there's a shift operator, handle it. 4751 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4752 unsigned ShiftImm = 0; 4753 if (Parser.getTok().is(AsmToken::Comma)) { 4754 Parser.Lex(); // Eat the ','. 4755 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4756 return true; 4757 } 4758 4759 // Now we should have the closing ']' 4760 if (Parser.getTok().isNot(AsmToken::RBrac)) 4761 return Error(Parser.getTok().getLoc(), "']' expected"); 4762 E = Parser.getTok().getEndLoc(); 4763 Parser.Lex(); // Eat right bracket token. 4764 4765 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, 4766 ShiftType, ShiftImm, 0, isNegative, 4767 S, E)); 4768 4769 // If there's a pre-indexing writeback marker, '!', just add it as a token 4770 // operand. 4771 if (Parser.getTok().is(AsmToken::Exclaim)) { 4772 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4773 Parser.Lex(); // Eat the '!'. 4774 } 4775 4776 return false; 4777 } 4778 4779 /// parseMemRegOffsetShift - one of these two: 4780 /// ( lsl | lsr | asr | ror ) , # shift_amount 4781 /// rrx 4782 /// return true if it parses a shift otherwise it returns false. 4783 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4784 unsigned &Amount) { 4785 SMLoc Loc = Parser.getTok().getLoc(); 4786 const AsmToken &Tok = Parser.getTok(); 4787 if (Tok.isNot(AsmToken::Identifier)) 4788 return true; 4789 StringRef ShiftName = Tok.getString(); 4790 if (ShiftName == "lsl" || ShiftName == "LSL" || 4791 ShiftName == "asl" || ShiftName == "ASL") 4792 St = ARM_AM::lsl; 4793 else if (ShiftName == "lsr" || ShiftName == "LSR") 4794 St = ARM_AM::lsr; 4795 else if (ShiftName == "asr" || ShiftName == "ASR") 4796 St = ARM_AM::asr; 4797 else if (ShiftName == "ror" || ShiftName == "ROR") 4798 St = ARM_AM::ror; 4799 else if (ShiftName == "rrx" || ShiftName == "RRX") 4800 St = ARM_AM::rrx; 4801 else 4802 return Error(Loc, "illegal shift operator"); 4803 Parser.Lex(); // Eat shift type token. 4804 4805 // rrx stands alone. 4806 Amount = 0; 4807 if (St != ARM_AM::rrx) { 4808 Loc = Parser.getTok().getLoc(); 4809 // A '#' and a shift amount. 4810 const AsmToken &HashTok = Parser.getTok(); 4811 if (HashTok.isNot(AsmToken::Hash) && 4812 HashTok.isNot(AsmToken::Dollar)) 4813 return Error(HashTok.getLoc(), "'#' expected"); 4814 Parser.Lex(); // Eat hash token. 4815 4816 const MCExpr *Expr; 4817 if (getParser().parseExpression(Expr)) 4818 return true; 4819 // Range check the immediate. 4820 // lsl, ror: 0 <= imm <= 31 4821 // lsr, asr: 0 <= imm <= 32 4822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4823 if (!CE) 4824 return Error(Loc, "shift amount must be an immediate"); 4825 int64_t Imm = CE->getValue(); 4826 if (Imm < 0 || 4827 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4828 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4829 return Error(Loc, "immediate shift value out of range"); 4830 // If <ShiftTy> #0, turn it into a no_shift. 4831 if (Imm == 0) 4832 St = ARM_AM::lsl; 4833 // For consistency, treat lsr #32 and asr #32 as having immediate value 0. 4834 if (Imm == 32) 4835 Imm = 0; 4836 Amount = Imm; 4837 } 4838 4839 return false; 4840 } 4841 4842 /// parseFPImm - A floating point immediate expression operand. 4843 ARMAsmParser::OperandMatchResultTy 4844 ARMAsmParser::parseFPImm(OperandVector &Operands) { 4845 // Anything that can accept a floating point constant as an operand 4846 // needs to go through here, as the regular parseExpression is 4847 // integer only. 4848 // 4849 // This routine still creates a generic Immediate operand, containing 4850 // a bitcast of the 64-bit floating point value. The various operands 4851 // that accept floats can check whether the value is valid for them 4852 // via the standard is*() predicates. 4853 4854 SMLoc S = Parser.getTok().getLoc(); 4855 4856 if (Parser.getTok().isNot(AsmToken::Hash) && 4857 Parser.getTok().isNot(AsmToken::Dollar)) 4858 return MatchOperand_NoMatch; 4859 4860 // Disambiguate the VMOV forms that can accept an FP immediate. 4861 // vmov.f32 <sreg>, #imm 4862 // vmov.f64 <dreg>, #imm 4863 // vmov.f32 <dreg>, #imm @ vector f32x2 4864 // vmov.f32 <qreg>, #imm @ vector f32x4 4865 // 4866 // There are also the NEON VMOV instructions which expect an 4867 // integer constant. Make sure we don't try to parse an FPImm 4868 // for these: 4869 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4870 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); 4871 bool isVmovf = TyOp.isToken() && 4872 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64"); 4873 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); 4874 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" || 4875 Mnemonic.getToken() == "fconsts"); 4876 if (!(isVmovf || isFconst)) 4877 return MatchOperand_NoMatch; 4878 4879 Parser.Lex(); // Eat '#' or '$'. 4880 4881 // Handle negation, as that still comes through as a separate token. 4882 bool isNegative = false; 4883 if (Parser.getTok().is(AsmToken::Minus)) { 4884 isNegative = true; 4885 Parser.Lex(); 4886 } 4887 const AsmToken &Tok = Parser.getTok(); 4888 SMLoc Loc = Tok.getLoc(); 4889 if (Tok.is(AsmToken::Real) && isVmovf) { 4890 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4891 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4892 // If we had a '-' in front, toggle the sign bit. 4893 IntVal ^= (uint64_t)isNegative << 31; 4894 Parser.Lex(); // Eat the token. 4895 Operands.push_back(ARMOperand::CreateImm( 4896 MCConstantExpr::Create(IntVal, getContext()), 4897 S, Parser.getTok().getLoc())); 4898 return MatchOperand_Success; 4899 } 4900 // Also handle plain integers. Instructions which allow floating point 4901 // immediates also allow a raw encoded 8-bit value. 4902 if (Tok.is(AsmToken::Integer) && isFconst) { 4903 int64_t Val = Tok.getIntVal(); 4904 Parser.Lex(); // Eat the token. 4905 if (Val > 255 || Val < 0) { 4906 Error(Loc, "encoded floating point value out of range"); 4907 return MatchOperand_ParseFail; 4908 } 4909 float RealVal = ARM_AM::getFPImmFloat(Val); 4910 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue(); 4911 4912 Operands.push_back(ARMOperand::CreateImm( 4913 MCConstantExpr::Create(Val, getContext()), S, 4914 Parser.getTok().getLoc())); 4915 return MatchOperand_Success; 4916 } 4917 4918 Error(Loc, "invalid floating point immediate"); 4919 return MatchOperand_ParseFail; 4920 } 4921 4922 /// Parse a arm instruction operand. For now this parses the operand regardless 4923 /// of the mnemonic. 4924 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { 4925 SMLoc S, E; 4926 4927 // Check if the current operand has a custom associated parser, if so, try to 4928 // custom parse the operand, or fallback to the general approach. 4929 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4930 if (ResTy == MatchOperand_Success) 4931 return false; 4932 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4933 // there was a match, but an error occurred, in which case, just return that 4934 // the operand parsing failed. 4935 if (ResTy == MatchOperand_ParseFail) 4936 return true; 4937 4938 switch (getLexer().getKind()) { 4939 default: 4940 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4941 return true; 4942 case AsmToken::Identifier: { 4943 // If we've seen a branch mnemonic, the next operand must be a label. This 4944 // is true even if the label is a register name. So "br r1" means branch to 4945 // label "r1". 4946 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl"; 4947 if (!ExpectLabel) { 4948 if (!tryParseRegisterWithWriteBack(Operands)) 4949 return false; 4950 int Res = tryParseShiftRegister(Operands); 4951 if (Res == 0) // success 4952 return false; 4953 else if (Res == -1) // irrecoverable error 4954 return true; 4955 // If this is VMRS, check for the apsr_nzcv operand. 4956 if (Mnemonic == "vmrs" && 4957 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4958 S = Parser.getTok().getLoc(); 4959 Parser.Lex(); 4960 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4961 return false; 4962 } 4963 } 4964 4965 // Fall though for the Identifier case that is not a register or a 4966 // special name. 4967 } 4968 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4969 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4970 case AsmToken::String: // quoted label names. 4971 case AsmToken::Dot: { // . as a branch target 4972 // This was not a register so parse other operands that start with an 4973 // identifier (like labels) as expressions and create them as immediates. 4974 const MCExpr *IdVal; 4975 S = Parser.getTok().getLoc(); 4976 if (getParser().parseExpression(IdVal)) 4977 return true; 4978 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4979 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4980 return false; 4981 } 4982 case AsmToken::LBrac: 4983 return parseMemory(Operands); 4984 case AsmToken::LCurly: 4985 return parseRegisterList(Operands); 4986 case AsmToken::Dollar: 4987 case AsmToken::Hash: { 4988 // #42 -> immediate. 4989 S = Parser.getTok().getLoc(); 4990 Parser.Lex(); 4991 4992 if (Parser.getTok().isNot(AsmToken::Colon)) { 4993 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4994 const MCExpr *ImmVal; 4995 if (getParser().parseExpression(ImmVal)) 4996 return true; 4997 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4998 if (CE) { 4999 int32_t Val = CE->getValue(); 5000 if (isNegative && Val == 0) 5001 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 5002 } 5003 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5004 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 5005 5006 // There can be a trailing '!' on operands that we want as a separate 5007 // '!' Token operand. Handle that here. For example, the compatibility 5008 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'. 5009 if (Parser.getTok().is(AsmToken::Exclaim)) { 5010 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), 5011 Parser.getTok().getLoc())); 5012 Parser.Lex(); // Eat exclaim token 5013 } 5014 return false; 5015 } 5016 // w/ a ':' after the '#', it's just like a plain ':'. 5017 // FALLTHROUGH 5018 } 5019 case AsmToken::Colon: { 5020 // ":lower16:" and ":upper16:" expression prefixes 5021 // FIXME: Check it's an expression prefix, 5022 // e.g. (FOO - :lower16:BAR) isn't legal. 5023 ARMMCExpr::VariantKind RefKind; 5024 if (parsePrefix(RefKind)) 5025 return true; 5026 5027 const MCExpr *SubExprVal; 5028 if (getParser().parseExpression(SubExprVal)) 5029 return true; 5030 5031 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 5032 getContext()); 5033 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5034 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 5035 return false; 5036 } 5037 case AsmToken::Equal: { 5038 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val) 5039 return Error(Parser.getTok().getLoc(), "unexpected token in operand"); 5040 5041 Parser.Lex(); // Eat '=' 5042 const MCExpr *SubExprVal; 5043 if (getParser().parseExpression(SubExprVal)) 5044 return true; 5045 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 5046 5047 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal); 5048 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E)); 5049 return false; 5050 } 5051 } 5052 } 5053 5054 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 5055 // :lower16: and :upper16:. 5056 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 5057 RefKind = ARMMCExpr::VK_ARM_None; 5058 5059 // consume an optional '#' (GNU compatibility) 5060 if (getLexer().is(AsmToken::Hash)) 5061 Parser.Lex(); 5062 5063 // :lower16: and :upper16: modifiers 5064 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 5065 Parser.Lex(); // Eat ':' 5066 5067 if (getLexer().isNot(AsmToken::Identifier)) { 5068 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 5069 return true; 5070 } 5071 5072 StringRef IDVal = Parser.getTok().getIdentifier(); 5073 if (IDVal == "lower16") { 5074 RefKind = ARMMCExpr::VK_ARM_LO16; 5075 } else if (IDVal == "upper16") { 5076 RefKind = ARMMCExpr::VK_ARM_HI16; 5077 } else { 5078 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 5079 return true; 5080 } 5081 Parser.Lex(); 5082 5083 if (getLexer().isNot(AsmToken::Colon)) { 5084 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 5085 return true; 5086 } 5087 Parser.Lex(); // Eat the last ':' 5088 return false; 5089 } 5090 5091 /// \brief Given a mnemonic, split out possible predication code and carry 5092 /// setting letters to form a canonical mnemonic and flags. 5093 // 5094 // FIXME: Would be nice to autogen this. 5095 // FIXME: This is a bit of a maze of special cases. 5096 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 5097 unsigned &PredicationCode, 5098 bool &CarrySetting, 5099 unsigned &ProcessorIMod, 5100 StringRef &ITMask) { 5101 PredicationCode = ARMCC::AL; 5102 CarrySetting = false; 5103 ProcessorIMod = 0; 5104 5105 // Ignore some mnemonics we know aren't predicated forms. 5106 // 5107 // FIXME: Would be nice to autogen this. 5108 if ((Mnemonic == "movs" && isThumb()) || 5109 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 5110 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 5111 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 5112 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 5113 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" || 5114 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 5115 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 5116 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 5117 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || 5118 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || 5119 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" || 5120 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel")) 5121 return Mnemonic; 5122 5123 // First, split out any predication code. Ignore mnemonics we know aren't 5124 // predicated but do have a carry-set and so weren't caught above. 5125 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 5126 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 5127 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 5128 Mnemonic != "sbcs" && Mnemonic != "rscs") { 5129 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 5130 .Case("eq", ARMCC::EQ) 5131 .Case("ne", ARMCC::NE) 5132 .Case("hs", ARMCC::HS) 5133 .Case("cs", ARMCC::HS) 5134 .Case("lo", ARMCC::LO) 5135 .Case("cc", ARMCC::LO) 5136 .Case("mi", ARMCC::MI) 5137 .Case("pl", ARMCC::PL) 5138 .Case("vs", ARMCC::VS) 5139 .Case("vc", ARMCC::VC) 5140 .Case("hi", ARMCC::HI) 5141 .Case("ls", ARMCC::LS) 5142 .Case("ge", ARMCC::GE) 5143 .Case("lt", ARMCC::LT) 5144 .Case("gt", ARMCC::GT) 5145 .Case("le", ARMCC::LE) 5146 .Case("al", ARMCC::AL) 5147 .Default(~0U); 5148 if (CC != ~0U) { 5149 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 5150 PredicationCode = CC; 5151 } 5152 } 5153 5154 // Next, determine if we have a carry setting bit. We explicitly ignore all 5155 // the instructions we know end in 's'. 5156 if (Mnemonic.endswith("s") && 5157 !(Mnemonic == "cps" || Mnemonic == "mls" || 5158 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 5159 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 5160 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 5161 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 5162 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 5163 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 5164 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 5165 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || 5166 (Mnemonic == "movs" && isThumb()))) { 5167 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 5168 CarrySetting = true; 5169 } 5170 5171 // The "cps" instruction can have a interrupt mode operand which is glued into 5172 // the mnemonic. Check if this is the case, split it and parse the imod op 5173 if (Mnemonic.startswith("cps")) { 5174 // Split out any imod code. 5175 unsigned IMod = 5176 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 5177 .Case("ie", ARM_PROC::IE) 5178 .Case("id", ARM_PROC::ID) 5179 .Default(~0U); 5180 if (IMod != ~0U) { 5181 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 5182 ProcessorIMod = IMod; 5183 } 5184 } 5185 5186 // The "it" instruction has the condition mask on the end of the mnemonic. 5187 if (Mnemonic.startswith("it")) { 5188 ITMask = Mnemonic.slice(2, Mnemonic.size()); 5189 Mnemonic = Mnemonic.slice(0, 2); 5190 } 5191 5192 return Mnemonic; 5193 } 5194 5195 /// \brief Given a canonical mnemonic, determine if the instruction ever allows 5196 /// inclusion of carry set or predication code operands. 5197 // 5198 // FIXME: It would be nice to autogen this. 5199 void ARMAsmParser:: 5200 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst, 5201 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) { 5202 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 5203 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 5204 Mnemonic == "add" || Mnemonic == "adc" || 5205 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 5206 Mnemonic == "orr" || Mnemonic == "mvn" || 5207 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 5208 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 5209 Mnemonic == "vfm" || Mnemonic == "vfnm" || 5210 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 5211 Mnemonic == "mla" || Mnemonic == "smlal" || 5212 Mnemonic == "umlal" || Mnemonic == "umull"))) { 5213 CanAcceptCarrySet = true; 5214 } else 5215 CanAcceptCarrySet = false; 5216 5217 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" || 5218 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" || 5219 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" || 5220 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") || 5221 Mnemonic.startswith("vsel") || 5222 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" || 5223 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || 5224 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" || 5225 Mnemonic == "vrintm" || Mnemonic.startswith("aes") || 5226 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") || 5227 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) { 5228 // These mnemonics are never predicable 5229 CanAcceptPredicationCode = false; 5230 } else if (!isThumb()) { 5231 // Some instructions are only predicable in Thumb mode 5232 CanAcceptPredicationCode 5233 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" && 5234 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" && 5235 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" && 5236 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" && 5237 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && 5238 Mnemonic != "stc2" && Mnemonic != "stc2l" && 5239 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs"); 5240 } else if (isThumbOne()) { 5241 if (hasV6MOps()) 5242 CanAcceptPredicationCode = Mnemonic != "movs"; 5243 else 5244 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs"; 5245 } else 5246 CanAcceptPredicationCode = true; 5247 } 5248 5249 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 5250 OperandVector &Operands) { 5251 // FIXME: This is all horribly hacky. We really need a better way to deal 5252 // with optional operands like this in the matcher table. 5253 5254 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 5255 // another does not. Specifically, the MOVW instruction does not. So we 5256 // special case it here and remove the defaulted (non-setting) cc_out 5257 // operand if that's the instruction we're trying to match. 5258 // 5259 // We do this as post-processing of the explicit operands rather than just 5260 // conditionally adding the cc_out in the first place because we need 5261 // to check the type of the parsed immediate operand. 5262 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 5263 !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() && 5264 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && 5265 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 5266 return true; 5267 5268 // Register-register 'add' for thumb does not have a cc_out operand 5269 // when there are only two register operands. 5270 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 5271 static_cast<ARMOperand &>(*Operands[3]).isReg() && 5272 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5273 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) 5274 return true; 5275 // Register-register 'add' for thumb does not have a cc_out operand 5276 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 5277 // have to check the immediate range here since Thumb2 has a variant 5278 // that can handle a different range and has a cc_out operand. 5279 if (((isThumb() && Mnemonic == "add") || 5280 (isThumbTwo() && Mnemonic == "sub")) && 5281 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 5282 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5283 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && 5284 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5285 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || 5286 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) 5287 return true; 5288 // For Thumb2, add/sub immediate does not have a cc_out operand for the 5289 // imm0_4095 variant. That's the least-preferred variant when 5290 // selecting via the generic "add" mnemonic, so to know that we 5291 // should remove the cc_out operand, we have to explicitly check that 5292 // it's not one of the other variants. Ugh. 5293 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 5294 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && 5295 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5296 static_cast<ARMOperand &>(*Operands[5]).isImm()) { 5297 // Nest conditions rather than one big 'if' statement for readability. 5298 // 5299 // If both registers are low, we're in an IT block, and the immediate is 5300 // in range, we should use encoding T1 instead, which has a cc_out. 5301 if (inITBlock() && 5302 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && 5303 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && 5304 static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) 5305 return false; 5306 // Check against T3. If the second register is the PC, this is an 5307 // alternate form of ADR, which uses encoding T4, so check for that too. 5308 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && 5309 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm()) 5310 return false; 5311 5312 // Otherwise, we use encoding T4, which does not have a cc_out 5313 // operand. 5314 return true; 5315 } 5316 5317 // The thumb2 multiply instruction doesn't have a CCOut register, so 5318 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 5319 // use the 16-bit encoding or not. 5320 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 5321 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5322 static_cast<ARMOperand &>(*Operands[3]).isReg() && 5323 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5324 static_cast<ARMOperand &>(*Operands[5]).isReg() && 5325 // If the registers aren't low regs, the destination reg isn't the 5326 // same as one of the source regs, or the cc_out operand is zero 5327 // outside of an IT block, we have to use the 32-bit encoding, so 5328 // remove the cc_out operand. 5329 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 5330 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 5331 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || 5332 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != 5333 static_cast<ARMOperand &>(*Operands[5]).getReg() && 5334 static_cast<ARMOperand &>(*Operands[3]).getReg() != 5335 static_cast<ARMOperand &>(*Operands[4]).getReg()))) 5336 return true; 5337 5338 // Also check the 'mul' syntax variant that doesn't specify an explicit 5339 // destination register. 5340 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 5341 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5342 static_cast<ARMOperand &>(*Operands[3]).isReg() && 5343 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5344 // If the registers aren't low regs or the cc_out operand is zero 5345 // outside of an IT block, we have to use the 32-bit encoding, so 5346 // remove the cc_out operand. 5347 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || 5348 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || 5349 !inITBlock())) 5350 return true; 5351 5352 5353 5354 // Register-register 'add/sub' for thumb does not have a cc_out operand 5355 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 5356 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 5357 // right, this will result in better diagnostics (which operand is off) 5358 // anyway. 5359 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 5360 (Operands.size() == 5 || Operands.size() == 6) && 5361 static_cast<ARMOperand &>(*Operands[3]).isReg() && 5362 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && 5363 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && 5364 (static_cast<ARMOperand &>(*Operands[4]).isImm() || 5365 (Operands.size() == 6 && 5366 static_cast<ARMOperand &>(*Operands[5]).isImm()))) 5367 return true; 5368 5369 return false; 5370 } 5371 5372 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic, 5373 OperandVector &Operands) { 5374 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON 5375 unsigned RegIdx = 3; 5376 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") && 5377 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") { 5378 if (static_cast<ARMOperand &>(*Operands[3]).isToken() && 5379 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32") 5380 RegIdx = 4; 5381 5382 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && 5383 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( 5384 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || 5385 ARMMCRegisterClasses[ARM::QPRRegClassID].contains( 5386 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) 5387 return true; 5388 } 5389 return false; 5390 } 5391 5392 static bool isDataTypeToken(StringRef Tok) { 5393 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 5394 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 5395 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 5396 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 5397 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 5398 Tok == ".f" || Tok == ".d"; 5399 } 5400 5401 // FIXME: This bit should probably be handled via an explicit match class 5402 // in the .td files that matches the suffix instead of having it be 5403 // a literal string token the way it is now. 5404 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 5405 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 5406 } 5407 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, 5408 unsigned VariantID); 5409 5410 static bool RequiresVFPRegListValidation(StringRef Inst, 5411 bool &AcceptSinglePrecisionOnly, 5412 bool &AcceptDoublePrecisionOnly) { 5413 if (Inst.size() < 7) 5414 return false; 5415 5416 if (Inst.startswith("fldm") || Inst.startswith("fstm")) { 5417 StringRef AddressingMode = Inst.substr(4, 2); 5418 if (AddressingMode == "ia" || AddressingMode == "db" || 5419 AddressingMode == "ea" || AddressingMode == "fd") { 5420 AcceptSinglePrecisionOnly = Inst[6] == 's'; 5421 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x'; 5422 return true; 5423 } 5424 } 5425 5426 return false; 5427 } 5428 5429 /// Parse an arm instruction mnemonic followed by its operands. 5430 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 5431 SMLoc NameLoc, OperandVector &Operands) { 5432 // FIXME: Can this be done via tablegen in some fashion? 5433 bool RequireVFPRegisterListCheck; 5434 bool AcceptSinglePrecisionOnly; 5435 bool AcceptDoublePrecisionOnly; 5436 RequireVFPRegisterListCheck = 5437 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly, 5438 AcceptDoublePrecisionOnly); 5439 5440 // Apply mnemonic aliases before doing anything else, as the destination 5441 // mnemonic may include suffices and we want to handle them normally. 5442 // The generic tblgen'erated code does this later, at the start of 5443 // MatchInstructionImpl(), but that's too late for aliases that include 5444 // any sort of suffix. 5445 uint64_t AvailableFeatures = getAvailableFeatures(); 5446 unsigned AssemblerDialect = getParser().getAssemblerDialect(); 5447 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect); 5448 5449 // First check for the ARM-specific .req directive. 5450 if (Parser.getTok().is(AsmToken::Identifier) && 5451 Parser.getTok().getIdentifier() == ".req") { 5452 parseDirectiveReq(Name, NameLoc); 5453 // We always return 'error' for this, as we're done with this 5454 // statement and don't need to match the 'instruction." 5455 return true; 5456 } 5457 5458 // Create the leading tokens for the mnemonic, split by '.' characters. 5459 size_t Start = 0, Next = Name.find('.'); 5460 StringRef Mnemonic = Name.slice(Start, Next); 5461 5462 // Split out the predication code and carry setting flag from the mnemonic. 5463 unsigned PredicationCode; 5464 unsigned ProcessorIMod; 5465 bool CarrySetting; 5466 StringRef ITMask; 5467 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5468 ProcessorIMod, ITMask); 5469 5470 // In Thumb1, only the branch (B) instruction can be predicated. 5471 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 5472 Parser.eatToEndOfStatement(); 5473 return Error(NameLoc, "conditional execution not supported in Thumb1"); 5474 } 5475 5476 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5477 5478 // Handle the IT instruction ITMask. Convert it to a bitmask. This 5479 // is the mask as it will be for the IT encoding if the conditional 5480 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5481 // where the conditional bit0 is zero, the instruction post-processing 5482 // will adjust the mask accordingly. 5483 if (Mnemonic == "it") { 5484 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5485 if (ITMask.size() > 3) { 5486 Parser.eatToEndOfStatement(); 5487 return Error(Loc, "too many conditions on IT instruction"); 5488 } 5489 unsigned Mask = 8; 5490 for (unsigned i = ITMask.size(); i != 0; --i) { 5491 char pos = ITMask[i - 1]; 5492 if (pos != 't' && pos != 'e') { 5493 Parser.eatToEndOfStatement(); 5494 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5495 } 5496 Mask >>= 1; 5497 if (ITMask[i - 1] == 't') 5498 Mask |= 8; 5499 } 5500 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5501 } 5502 5503 // FIXME: This is all a pretty gross hack. We should automatically handle 5504 // optional operands like this via tblgen. 5505 5506 // Next, add the CCOut and ConditionCode operands, if needed. 5507 // 5508 // For mnemonics which can ever incorporate a carry setting bit or predication 5509 // code, our matching model involves us always generating CCOut and 5510 // ConditionCode operands to match the mnemonic "as written" and then we let 5511 // the matcher deal with finding the right instruction or generating an 5512 // appropriate error. 5513 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5514 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode); 5515 5516 // If we had a carry-set on an instruction that can't do that, issue an 5517 // error. 5518 if (!CanAcceptCarrySet && CarrySetting) { 5519 Parser.eatToEndOfStatement(); 5520 return Error(NameLoc, "instruction '" + Mnemonic + 5521 "' can not set flags, but 's' suffix specified"); 5522 } 5523 // If we had a predication code on an instruction that can't do that, issue an 5524 // error. 5525 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5526 Parser.eatToEndOfStatement(); 5527 return Error(NameLoc, "instruction '" + Mnemonic + 5528 "' is not predicable, but condition code specified"); 5529 } 5530 5531 // Add the carry setting operand, if necessary. 5532 if (CanAcceptCarrySet) { 5533 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5534 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5535 Loc)); 5536 } 5537 5538 // Add the predication code operand, if necessary. 5539 if (CanAcceptPredicationCode) { 5540 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5541 CarrySetting); 5542 Operands.push_back(ARMOperand::CreateCondCode( 5543 ARMCC::CondCodes(PredicationCode), Loc)); 5544 } 5545 5546 // Add the processor imod operand, if necessary. 5547 if (ProcessorIMod) { 5548 Operands.push_back(ARMOperand::CreateImm( 5549 MCConstantExpr::Create(ProcessorIMod, getContext()), 5550 NameLoc, NameLoc)); 5551 } else if (Mnemonic == "cps" && isMClass()) { 5552 return Error(NameLoc, "instruction 'cps' requires effect for M-class"); 5553 } 5554 5555 // Add the remaining tokens in the mnemonic. 5556 while (Next != StringRef::npos) { 5557 Start = Next; 5558 Next = Name.find('.', Start + 1); 5559 StringRef ExtraToken = Name.slice(Start, Next); 5560 5561 // Some NEON instructions have an optional datatype suffix that is 5562 // completely ignored. Check for that. 5563 if (isDataTypeToken(ExtraToken) && 5564 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5565 continue; 5566 5567 // For for ARM mode generate an error if the .n qualifier is used. 5568 if (ExtraToken == ".n" && !isThumb()) { 5569 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5570 Parser.eatToEndOfStatement(); 5571 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in " 5572 "arm mode"); 5573 } 5574 5575 // The .n qualifier is always discarded as that is what the tables 5576 // and matcher expect. In ARM mode the .w qualifier has no effect, 5577 // so discard it to avoid errors that can be caused by the matcher. 5578 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) { 5579 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5580 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5581 } 5582 } 5583 5584 // Read the remaining operands. 5585 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5586 // Read the first operand. 5587 if (parseOperand(Operands, Mnemonic)) { 5588 Parser.eatToEndOfStatement(); 5589 return true; 5590 } 5591 5592 while (getLexer().is(AsmToken::Comma)) { 5593 Parser.Lex(); // Eat the comma. 5594 5595 // Parse and remember the operand. 5596 if (parseOperand(Operands, Mnemonic)) { 5597 Parser.eatToEndOfStatement(); 5598 return true; 5599 } 5600 } 5601 } 5602 5603 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5604 SMLoc Loc = getLexer().getLoc(); 5605 Parser.eatToEndOfStatement(); 5606 return Error(Loc, "unexpected token in argument list"); 5607 } 5608 5609 Parser.Lex(); // Consume the EndOfStatement 5610 5611 if (RequireVFPRegisterListCheck) { 5612 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back()); 5613 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList()) 5614 return Error(Op.getStartLoc(), 5615 "VFP/Neon single precision register expected"); 5616 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList()) 5617 return Error(Op.getStartLoc(), 5618 "VFP/Neon double precision register expected"); 5619 } 5620 5621 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5622 // do and don't have a cc_out optional-def operand. With some spot-checks 5623 // of the operand list, we can figure out which variant we're trying to 5624 // parse and adjust accordingly before actually matching. We shouldn't ever 5625 // try to remove a cc_out operand that was explicitly set on the the 5626 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5627 // table driven matcher doesn't fit well with the ARM instruction set. 5628 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) 5629 Operands.erase(Operands.begin() + 1); 5630 5631 // Some instructions have the same mnemonic, but don't always 5632 // have a predicate. Distinguish them here and delete the 5633 // predicate if needed. 5634 if (shouldOmitPredicateOperand(Mnemonic, Operands)) 5635 Operands.erase(Operands.begin() + 1); 5636 5637 // ARM mode 'blx' need special handling, as the register operand version 5638 // is predicable, but the label operand version is not. So, we can't rely 5639 // on the Mnemonic based checking to correctly figure out when to put 5640 // a k_CondCode operand in the list. If we're trying to match the label 5641 // version, remove the k_CondCode operand here. 5642 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5643 static_cast<ARMOperand &>(*Operands[2]).isImm()) 5644 Operands.erase(Operands.begin() + 1); 5645 5646 // Adjust operands of ldrexd/strexd to MCK_GPRPair. 5647 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint, 5648 // a single GPRPair reg operand is used in the .td file to replace the two 5649 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically 5650 // expressed as a GPRPair, so we have to manually merge them. 5651 // FIXME: We would really like to be able to tablegen'erate this. 5652 if (!isThumb() && Operands.size() > 4 && 5653 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" || 5654 Mnemonic == "stlexd")) { 5655 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd"); 5656 unsigned Idx = isLoad ? 2 : 3; 5657 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); 5658 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); 5659 5660 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); 5661 // Adjust only if Op1 and Op2 are GPRs. 5662 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) && 5663 MRC.contains(Op2.getReg())) { 5664 unsigned Reg1 = Op1.getReg(); 5665 unsigned Reg2 = Op2.getReg(); 5666 unsigned Rt = MRI->getEncodingValue(Reg1); 5667 unsigned Rt2 = MRI->getEncodingValue(Reg2); 5668 5669 // Rt2 must be Rt + 1 and Rt must be even. 5670 if (Rt + 1 != Rt2 || (Rt & 1)) { 5671 Error(Op2.getStartLoc(), isLoad 5672 ? "destination operands must be sequential" 5673 : "source operands must be sequential"); 5674 return true; 5675 } 5676 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, 5677 &(MRI->getRegClass(ARM::GPRPairRegClassID))); 5678 Operands[Idx] = 5679 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); 5680 Operands.erase(Operands.begin() + Idx + 1); 5681 } 5682 } 5683 5684 // If first 2 operands of a 3 operand instruction are the same 5685 // then transform to 2 operand version of the same instruction 5686 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1' 5687 // FIXME: We would really like to be able to tablegen'erate this. 5688 if (isThumbOne() && Operands.size() == 6 && 5689 (Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" || 5690 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" || 5691 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" || 5692 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) { 5693 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); 5694 ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]); 5695 ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]); 5696 5697 // If both registers are the same then remove one of them from 5698 // the operand list. 5699 if (Op3.isReg() && Op4.isReg() && Op3.getReg() == Op4.getReg()) { 5700 // If 3rd operand (variable Op5) is a register and the instruction is adds/sub 5701 // then do not transform as the backend already handles this instruction 5702 // correctly. 5703 if (!Op5.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) { 5704 Operands.erase(Operands.begin() + 3); 5705 if (Mnemonic == "add" && !CarrySetting) { 5706 // Special case for 'add' (not 'adds') instruction must 5707 // remove the CCOut operand as well. 5708 Operands.erase(Operands.begin() + 1); 5709 } 5710 } 5711 } 5712 } 5713 5714 // If instruction is 'add' and first two register operands 5715 // use SP register, then remove one of the SP registers from 5716 // the instruction. 5717 // FIXME: We would really like to be able to tablegen'erate this. 5718 if (isThumbOne() && Operands.size() == 5 && Mnemonic == "add" && !CarrySetting) { 5719 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); 5720 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); 5721 if (Op2.isReg() && Op3.isReg() && Op2.getReg() == ARM::SP && Op3.getReg() == ARM::SP) { 5722 Operands.erase(Operands.begin() + 2); 5723 } 5724 } 5725 5726 // GNU Assembler extension (compatibility) 5727 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) { 5728 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); 5729 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); 5730 if (Op3.isMem()) { 5731 assert(Op2.isReg() && "expected register argument"); 5732 5733 unsigned SuperReg = MRI->getMatchingSuperReg( 5734 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID)); 5735 5736 assert(SuperReg && "expected register pair"); 5737 5738 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1); 5739 5740 Operands.insert( 5741 Operands.begin() + 3, 5742 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc())); 5743 } 5744 } 5745 5746 // FIXME: As said above, this is all a pretty gross hack. This instruction 5747 // does not fit with other "subs" and tblgen. 5748 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction 5749 // so the Mnemonic is the original name "subs" and delete the predicate 5750 // operand so it will match the table entry. 5751 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && 5752 static_cast<ARMOperand &>(*Operands[3]).isReg() && 5753 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && 5754 static_cast<ARMOperand &>(*Operands[4]).isReg() && 5755 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && 5756 static_cast<ARMOperand &>(*Operands[5]).isImm()) { 5757 Operands.front() = ARMOperand::CreateToken(Name, NameLoc); 5758 Operands.erase(Operands.begin() + 1); 5759 } 5760 return false; 5761 } 5762 5763 // Validate context-sensitive operand constraints. 5764 5765 // return 'true' if register list contains non-low GPR registers, 5766 // 'false' otherwise. If Reg is in the register list or is HiReg, set 5767 // 'containsReg' to true. 5768 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5769 unsigned HiReg, bool &containsReg) { 5770 containsReg = false; 5771 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5772 unsigned OpReg = Inst.getOperand(i).getReg(); 5773 if (OpReg == Reg) 5774 containsReg = true; 5775 // Anything other than a low register isn't legal here. 5776 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5777 return true; 5778 } 5779 return false; 5780 } 5781 5782 // Check if the specified regisgter is in the register list of the inst, 5783 // starting at the indicated operand number. 5784 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5785 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5786 unsigned OpReg = Inst.getOperand(i).getReg(); 5787 if (OpReg == Reg) 5788 return true; 5789 } 5790 return false; 5791 } 5792 5793 // Return true if instruction has the interesting property of being 5794 // allowed in IT blocks, but not being predicable. 5795 static bool instIsBreakpoint(const MCInst &Inst) { 5796 return Inst.getOpcode() == ARM::tBKPT || 5797 Inst.getOpcode() == ARM::BKPT || 5798 Inst.getOpcode() == ARM::tHLT || 5799 Inst.getOpcode() == ARM::HLT; 5800 5801 } 5802 5803 // FIXME: We would really like to be able to tablegen'erate this. 5804 bool ARMAsmParser::validateInstruction(MCInst &Inst, 5805 const OperandVector &Operands) { 5806 const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); 5807 SMLoc Loc = Operands[0]->getStartLoc(); 5808 5809 // Check the IT block state first. 5810 // NOTE: BKPT and HLT instructions have the interesting property of being 5811 // allowed in IT blocks, but not being predicable. They just always execute. 5812 if (inITBlock() && !instIsBreakpoint(Inst)) { 5813 unsigned Bit = 1; 5814 if (ITState.FirstCond) 5815 ITState.FirstCond = false; 5816 else 5817 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5818 // The instruction must be predicable. 5819 if (!MCID.isPredicable()) 5820 return Error(Loc, "instructions in IT block must be predicable"); 5821 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5822 unsigned ITCond = Bit ? ITState.Cond : 5823 ARMCC::getOppositeCondition(ITState.Cond); 5824 if (Cond != ITCond) { 5825 // Find the condition code Operand to get its SMLoc information. 5826 SMLoc CondLoc; 5827 for (unsigned I = 1; I < Operands.size(); ++I) 5828 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) 5829 CondLoc = Operands[I]->getStartLoc(); 5830 return Error(CondLoc, "incorrect condition in IT block; got '" + 5831 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5832 "', but expected '" + 5833 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5834 } 5835 // Check for non-'al' condition codes outside of the IT block. 5836 } else if (isThumbTwo() && MCID.isPredicable() && 5837 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5838 ARMCC::AL && Inst.getOpcode() != ARM::tBcc && 5839 Inst.getOpcode() != ARM::t2Bcc) 5840 return Error(Loc, "predicated instructions must be in IT block"); 5841 5842 const unsigned Opcode = Inst.getOpcode(); 5843 switch (Opcode) { 5844 case ARM::LDRD: 5845 case ARM::LDRD_PRE: 5846 case ARM::LDRD_POST: { 5847 const unsigned RtReg = Inst.getOperand(0).getReg(); 5848 5849 // Rt can't be R14. 5850 if (RtReg == ARM::LR) 5851 return Error(Operands[3]->getStartLoc(), 5852 "Rt can't be R14"); 5853 5854 const unsigned Rt = MRI->getEncodingValue(RtReg); 5855 // Rt must be even-numbered. 5856 if ((Rt & 1) == 1) 5857 return Error(Operands[3]->getStartLoc(), 5858 "Rt must be even-numbered"); 5859 5860 // Rt2 must be Rt + 1. 5861 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5862 if (Rt2 != Rt + 1) 5863 return Error(Operands[3]->getStartLoc(), 5864 "destination operands must be sequential"); 5865 5866 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) { 5867 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); 5868 // For addressing modes with writeback, the base register needs to be 5869 // different from the destination registers. 5870 if (Rn == Rt || Rn == Rt2) 5871 return Error(Operands[3]->getStartLoc(), 5872 "base register needs to be different from destination " 5873 "registers"); 5874 } 5875 5876 return false; 5877 } 5878 case ARM::t2LDRDi8: 5879 case ARM::t2LDRD_PRE: 5880 case ARM::t2LDRD_POST: { 5881 // Rt2 must be different from Rt. 5882 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5883 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5884 if (Rt2 == Rt) 5885 return Error(Operands[3]->getStartLoc(), 5886 "destination operands can't be identical"); 5887 return false; 5888 } 5889 case ARM::STRD: { 5890 // Rt2 must be Rt + 1. 5891 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5892 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5893 if (Rt2 != Rt + 1) 5894 return Error(Operands[3]->getStartLoc(), 5895 "source operands must be sequential"); 5896 return false; 5897 } 5898 case ARM::STRD_PRE: 5899 case ARM::STRD_POST: { 5900 // Rt2 must be Rt + 1. 5901 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5902 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5903 if (Rt2 != Rt + 1) 5904 return Error(Operands[3]->getStartLoc(), 5905 "source operands must be sequential"); 5906 return false; 5907 } 5908 case ARM::STR_PRE_IMM: 5909 case ARM::STR_PRE_REG: 5910 case ARM::STR_POST_IMM: 5911 case ARM::STR_POST_REG: 5912 case ARM::STRH_PRE: 5913 case ARM::STRH_POST: 5914 case ARM::STRB_PRE_IMM: 5915 case ARM::STRB_PRE_REG: 5916 case ARM::STRB_POST_IMM: 5917 case ARM::STRB_POST_REG: { 5918 // Rt must be different from Rn. 5919 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); 5920 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5921 5922 if (Rt == Rn) 5923 return Error(Operands[3]->getStartLoc(), 5924 "source register and base register can't be identical"); 5925 return false; 5926 } 5927 case ARM::LDR_PRE_IMM: 5928 case ARM::LDR_PRE_REG: 5929 case ARM::LDR_POST_IMM: 5930 case ARM::LDR_POST_REG: 5931 case ARM::LDRH_PRE: 5932 case ARM::LDRH_POST: 5933 case ARM::LDRSH_PRE: 5934 case ARM::LDRSH_POST: 5935 case ARM::LDRB_PRE_IMM: 5936 case ARM::LDRB_PRE_REG: 5937 case ARM::LDRB_POST_IMM: 5938 case ARM::LDRB_POST_REG: 5939 case ARM::LDRSB_PRE: 5940 case ARM::LDRSB_POST: { 5941 // Rt must be different from Rn. 5942 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); 5943 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg()); 5944 5945 if (Rt == Rn) 5946 return Error(Operands[3]->getStartLoc(), 5947 "destination register and base register can't be identical"); 5948 return false; 5949 } 5950 case ARM::SBFX: 5951 case ARM::UBFX: { 5952 // Width must be in range [1, 32-lsb]. 5953 unsigned LSB = Inst.getOperand(2).getImm(); 5954 unsigned Widthm1 = Inst.getOperand(3).getImm(); 5955 if (Widthm1 >= 32 - LSB) 5956 return Error(Operands[5]->getStartLoc(), 5957 "bitfield width must be in range [1,32-lsb]"); 5958 return false; 5959 } 5960 // Notionally handles ARM::tLDMIA_UPD too. 5961 case ARM::tLDMIA: { 5962 // If we're parsing Thumb2, the .w variant is available and handles 5963 // most cases that are normally illegal for a Thumb1 LDM instruction. 5964 // We'll make the transformation in processInstruction() if necessary. 5965 // 5966 // Thumb LDM instructions are writeback iff the base register is not 5967 // in the register list. 5968 unsigned Rn = Inst.getOperand(0).getReg(); 5969 bool HasWritebackToken = 5970 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 5971 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); 5972 bool ListContainsBase; 5973 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo()) 5974 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), 5975 "registers must be in range r0-r7"); 5976 // If we should have writeback, then there should be a '!' token. 5977 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo()) 5978 return Error(Operands[2]->getStartLoc(), 5979 "writeback operator '!' expected"); 5980 // If we should not have writeback, there must not be a '!'. This is 5981 // true even for the 32-bit wide encodings. 5982 if (ListContainsBase && HasWritebackToken) 5983 return Error(Operands[3]->getStartLoc(), 5984 "writeback operator '!' not allowed when base register " 5985 "in register list"); 5986 if (listContainsReg(Inst, 3 + HasWritebackToken, ARM::SP)) 5987 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), 5988 "SP not allowed in register list"); 5989 break; 5990 } 5991 case ARM::LDMIA_UPD: 5992 case ARM::LDMDB_UPD: 5993 case ARM::LDMIB_UPD: 5994 case ARM::LDMDA_UPD: 5995 // ARM variants loading and updating the same register are only officially 5996 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before. 5997 if (!hasV7Ops()) 5998 break; 5999 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 6000 return Error(Operands.back()->getStartLoc(), 6001 "writeback register not allowed in register list"); 6002 break; 6003 case ARM::t2LDMIA: 6004 case ARM::t2LDMDB: 6005 case ARM::t2STMIA: 6006 case ARM::t2STMDB: { 6007 if (listContainsReg(Inst, 3, ARM::SP)) 6008 return Error(Operands.back()->getStartLoc(), 6009 "SP not allowed in register list"); 6010 break; 6011 } 6012 case ARM::t2LDMIA_UPD: 6013 case ARM::t2LDMDB_UPD: 6014 case ARM::t2STMIA_UPD: 6015 case ARM::t2STMDB_UPD: { 6016 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 6017 return Error(Operands.back()->getStartLoc(), 6018 "writeback register not allowed in register list"); 6019 6020 if (listContainsReg(Inst, 4, ARM::SP)) 6021 return Error(Operands.back()->getStartLoc(), 6022 "SP not allowed in register list"); 6023 break; 6024 } 6025 case ARM::sysLDMIA_UPD: 6026 case ARM::sysLDMDA_UPD: 6027 case ARM::sysLDMDB_UPD: 6028 case ARM::sysLDMIB_UPD: 6029 if (!listContainsReg(Inst, 3, ARM::PC)) 6030 return Error(Operands[4]->getStartLoc(), 6031 "writeback register only allowed on system LDM " 6032 "if PC in register-list"); 6033 break; 6034 case ARM::sysSTMIA_UPD: 6035 case ARM::sysSTMDA_UPD: 6036 case ARM::sysSTMDB_UPD: 6037 case ARM::sysSTMIB_UPD: 6038 return Error(Operands[2]->getStartLoc(), 6039 "system STM cannot have writeback register"); 6040 case ARM::tMUL: { 6041 // The second source operand must be the same register as the destination 6042 // operand. 6043 // 6044 // In this case, we must directly check the parsed operands because the 6045 // cvtThumbMultiply() function is written in such a way that it guarantees 6046 // this first statement is always true for the new Inst. Essentially, the 6047 // destination is unconditionally copied into the second source operand 6048 // without checking to see if it matches what we actually parsed. 6049 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != 6050 ((ARMOperand &)*Operands[5]).getReg()) && 6051 (((ARMOperand &)*Operands[3]).getReg() != 6052 ((ARMOperand &)*Operands[4]).getReg())) { 6053 return Error(Operands[3]->getStartLoc(), 6054 "destination register must match source register"); 6055 } 6056 break; 6057 } 6058 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 6059 // so only issue a diagnostic for thumb1. The instructions will be 6060 // switched to the t2 encodings in processInstruction() if necessary. 6061 case ARM::tPOP: { 6062 bool ListContainsBase; 6063 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) && 6064 !isThumbTwo()) 6065 return Error(Operands[2]->getStartLoc(), 6066 "registers must be in range r0-r7 or pc"); 6067 break; 6068 } 6069 case ARM::tPUSH: { 6070 bool ListContainsBase; 6071 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) && 6072 !isThumbTwo()) 6073 return Error(Operands[2]->getStartLoc(), 6074 "registers must be in range r0-r7 or lr"); 6075 break; 6076 } 6077 case ARM::tSTMIA_UPD: { 6078 bool ListContainsBase, InvalidLowList; 6079 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(), 6080 0, ListContainsBase); 6081 if (InvalidLowList && !isThumbTwo()) 6082 return Error(Operands[4]->getStartLoc(), 6083 "registers must be in range r0-r7"); 6084 6085 // This would be converted to a 32-bit stm, but that's not valid if the 6086 // writeback register is in the list. 6087 if (InvalidLowList && ListContainsBase) 6088 return Error(Operands[4]->getStartLoc(), 6089 "writeback operator '!' not allowed when base register " 6090 "in register list"); 6091 if (listContainsReg(Inst, 4, ARM::SP) && !inITBlock()) 6092 return Error(Operands.back()->getStartLoc(), 6093 "SP not allowed in register list"); 6094 break; 6095 } 6096 case ARM::tADDrSP: { 6097 // If the non-SP source operand and the destination operand are not the 6098 // same, we need thumb2 (for the wide encoding), or we have an error. 6099 if (!isThumbTwo() && 6100 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 6101 return Error(Operands[4]->getStartLoc(), 6102 "source register must be the same as destination"); 6103 } 6104 break; 6105 } 6106 // Final range checking for Thumb unconditional branch instructions. 6107 case ARM::tB: 6108 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) 6109 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 6110 break; 6111 case ARM::t2B: { 6112 int op = (Operands[2]->isImm()) ? 2 : 3; 6113 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>()) 6114 return Error(Operands[op]->getStartLoc(), "branch target out of range"); 6115 break; 6116 } 6117 // Final range checking for Thumb conditional branch instructions. 6118 case ARM::tBcc: 6119 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) 6120 return Error(Operands[2]->getStartLoc(), "branch target out of range"); 6121 break; 6122 case ARM::t2Bcc: { 6123 int Op = (Operands[2]->isImm()) ? 2 : 3; 6124 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) 6125 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); 6126 break; 6127 } 6128 case ARM::MOVi16: 6129 case ARM::t2MOVi16: 6130 case ARM::t2MOVTi16: 6131 { 6132 // We want to avoid misleadingly allowing something like "mov r0, <symbol>" 6133 // especially when we turn it into a movw and the expression <symbol> does 6134 // not have a :lower16: or :upper16 as part of the expression. We don't 6135 // want the behavior of silently truncating, which can be unexpected and 6136 // lead to bugs that are difficult to find since this is an easy mistake 6137 // to make. 6138 int i = (Operands[3]->isImm()) ? 3 : 4; 6139 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); 6140 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()); 6141 if (CE) break; 6142 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm()); 6143 if (!E) break; 6144 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E); 6145 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 && 6146 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) 6147 return Error( 6148 Op.getStartLoc(), 6149 "immediate expression for mov requires :lower16: or :upper16"); 6150 break; 6151 } 6152 } 6153 6154 return false; 6155 } 6156 6157 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 6158 switch(Opc) { 6159 default: llvm_unreachable("unexpected opcode!"); 6160 // VST1LN 6161 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 6162 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 6163 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 6164 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 6165 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 6166 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 6167 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 6168 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 6169 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 6170 6171 // VST2LN 6172 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 6173 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 6174 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 6175 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 6176 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 6177 6178 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 6179 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 6180 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 6181 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 6182 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 6183 6184 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 6185 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 6186 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 6187 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 6188 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 6189 6190 // VST3LN 6191 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 6192 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 6193 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 6194 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 6195 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 6196 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 6197 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 6198 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 6199 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 6200 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 6201 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 6202 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 6203 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 6204 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 6205 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 6206 6207 // VST3 6208 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 6209 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 6210 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 6211 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 6212 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 6213 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 6214 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 6215 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 6216 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 6217 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 6218 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 6219 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 6220 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 6221 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 6222 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 6223 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 6224 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 6225 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 6226 6227 // VST4LN 6228 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 6229 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 6230 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 6231 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 6232 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 6233 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 6234 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 6235 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 6236 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 6237 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 6238 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 6239 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 6240 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 6241 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 6242 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 6243 6244 // VST4 6245 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 6246 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 6247 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 6248 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 6249 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 6250 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 6251 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 6252 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 6253 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 6254 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 6255 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 6256 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 6257 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 6258 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 6259 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 6260 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 6261 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 6262 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 6263 } 6264 } 6265 6266 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 6267 switch(Opc) { 6268 default: llvm_unreachable("unexpected opcode!"); 6269 // VLD1LN 6270 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 6271 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 6272 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 6273 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 6274 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 6275 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 6276 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 6277 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 6278 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 6279 6280 // VLD2LN 6281 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 6282 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 6283 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 6284 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 6285 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 6286 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 6287 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 6288 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 6289 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 6290 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 6291 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 6292 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 6293 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 6294 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 6295 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 6296 6297 // VLD3DUP 6298 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 6299 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 6300 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 6301 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 6302 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 6303 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 6304 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 6305 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 6306 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 6307 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 6308 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 6309 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 6310 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 6311 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 6312 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 6313 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 6314 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 6315 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 6316 6317 // VLD3LN 6318 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 6319 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 6320 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 6321 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 6322 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 6323 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 6324 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 6325 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 6326 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 6327 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 6328 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 6329 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 6330 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 6331 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 6332 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 6333 6334 // VLD3 6335 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 6336 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 6337 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 6338 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 6339 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 6340 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 6341 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 6342 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 6343 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 6344 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 6345 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 6346 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 6347 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 6348 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 6349 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 6350 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 6351 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 6352 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 6353 6354 // VLD4LN 6355 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 6356 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 6357 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 6358 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 6359 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 6360 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 6361 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 6362 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 6363 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 6364 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 6365 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 6366 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 6367 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 6368 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 6369 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 6370 6371 // VLD4DUP 6372 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 6373 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 6374 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 6375 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 6376 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 6377 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 6378 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 6379 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 6380 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 6381 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 6382 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 6383 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 6384 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 6385 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 6386 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 6387 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 6388 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 6389 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 6390 6391 // VLD4 6392 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 6393 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 6394 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 6395 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 6396 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 6397 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 6398 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 6399 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 6400 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 6401 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 6402 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 6403 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 6404 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 6405 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 6406 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 6407 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 6408 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 6409 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 6410 } 6411 } 6412 6413 bool ARMAsmParser::processInstruction(MCInst &Inst, 6414 const OperandVector &Operands) { 6415 switch (Inst.getOpcode()) { 6416 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction. 6417 case ARM::LDRT_POST: 6418 case ARM::LDRBT_POST: { 6419 const unsigned Opcode = 6420 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM 6421 : ARM::LDRBT_POST_IMM; 6422 MCInst TmpInst; 6423 TmpInst.setOpcode(Opcode); 6424 TmpInst.addOperand(Inst.getOperand(0)); 6425 TmpInst.addOperand(Inst.getOperand(1)); 6426 TmpInst.addOperand(Inst.getOperand(1)); 6427 TmpInst.addOperand(MCOperand::CreateReg(0)); 6428 TmpInst.addOperand(MCOperand::CreateImm(0)); 6429 TmpInst.addOperand(Inst.getOperand(2)); 6430 TmpInst.addOperand(Inst.getOperand(3)); 6431 Inst = TmpInst; 6432 return true; 6433 } 6434 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction. 6435 case ARM::STRT_POST: 6436 case ARM::STRBT_POST: { 6437 const unsigned Opcode = 6438 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM 6439 : ARM::STRBT_POST_IMM; 6440 MCInst TmpInst; 6441 TmpInst.setOpcode(Opcode); 6442 TmpInst.addOperand(Inst.getOperand(1)); 6443 TmpInst.addOperand(Inst.getOperand(0)); 6444 TmpInst.addOperand(Inst.getOperand(1)); 6445 TmpInst.addOperand(MCOperand::CreateReg(0)); 6446 TmpInst.addOperand(MCOperand::CreateImm(0)); 6447 TmpInst.addOperand(Inst.getOperand(2)); 6448 TmpInst.addOperand(Inst.getOperand(3)); 6449 Inst = TmpInst; 6450 return true; 6451 } 6452 // Alias for alternate form of 'ADR Rd, #imm' instruction. 6453 case ARM::ADDri: { 6454 if (Inst.getOperand(1).getReg() != ARM::PC || 6455 Inst.getOperand(5).getReg() != 0) 6456 return false; 6457 MCInst TmpInst; 6458 TmpInst.setOpcode(ARM::ADR); 6459 TmpInst.addOperand(Inst.getOperand(0)); 6460 TmpInst.addOperand(Inst.getOperand(2)); 6461 TmpInst.addOperand(Inst.getOperand(3)); 6462 TmpInst.addOperand(Inst.getOperand(4)); 6463 Inst = TmpInst; 6464 return true; 6465 } 6466 // Aliases for alternate PC+imm syntax of LDR instructions. 6467 case ARM::t2LDRpcrel: 6468 // Select the narrow version if the immediate will fit. 6469 if (Inst.getOperand(1).getImm() > 0 && 6470 Inst.getOperand(1).getImm() <= 0xff && 6471 !(static_cast<ARMOperand &>(*Operands[2]).isToken() && 6472 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w")) 6473 Inst.setOpcode(ARM::tLDRpci); 6474 else 6475 Inst.setOpcode(ARM::t2LDRpci); 6476 return true; 6477 case ARM::t2LDRBpcrel: 6478 Inst.setOpcode(ARM::t2LDRBpci); 6479 return true; 6480 case ARM::t2LDRHpcrel: 6481 Inst.setOpcode(ARM::t2LDRHpci); 6482 return true; 6483 case ARM::t2LDRSBpcrel: 6484 Inst.setOpcode(ARM::t2LDRSBpci); 6485 return true; 6486 case ARM::t2LDRSHpcrel: 6487 Inst.setOpcode(ARM::t2LDRSHpci); 6488 return true; 6489 // Handle NEON VST complex aliases. 6490 case ARM::VST1LNdWB_register_Asm_8: 6491 case ARM::VST1LNdWB_register_Asm_16: 6492 case ARM::VST1LNdWB_register_Asm_32: { 6493 MCInst TmpInst; 6494 // Shuffle the operands around so the lane index operand is in the 6495 // right place. 6496 unsigned Spacing; 6497 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6498 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6499 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6500 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6501 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6502 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6503 TmpInst.addOperand(Inst.getOperand(1)); // lane 6504 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6505 TmpInst.addOperand(Inst.getOperand(6)); 6506 Inst = TmpInst; 6507 return true; 6508 } 6509 6510 case ARM::VST2LNdWB_register_Asm_8: 6511 case ARM::VST2LNdWB_register_Asm_16: 6512 case ARM::VST2LNdWB_register_Asm_32: 6513 case ARM::VST2LNqWB_register_Asm_16: 6514 case ARM::VST2LNqWB_register_Asm_32: { 6515 MCInst TmpInst; 6516 // Shuffle the operands around so the lane index operand is in the 6517 // right place. 6518 unsigned Spacing; 6519 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6520 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6521 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6522 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6523 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6524 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6525 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6526 Spacing)); 6527 TmpInst.addOperand(Inst.getOperand(1)); // lane 6528 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6529 TmpInst.addOperand(Inst.getOperand(6)); 6530 Inst = TmpInst; 6531 return true; 6532 } 6533 6534 case ARM::VST3LNdWB_register_Asm_8: 6535 case ARM::VST3LNdWB_register_Asm_16: 6536 case ARM::VST3LNdWB_register_Asm_32: 6537 case ARM::VST3LNqWB_register_Asm_16: 6538 case ARM::VST3LNqWB_register_Asm_32: { 6539 MCInst TmpInst; 6540 // Shuffle the operands around so the lane index operand is in the 6541 // right place. 6542 unsigned Spacing; 6543 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6544 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6545 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6546 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6547 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6548 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6549 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6550 Spacing)); 6551 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6552 Spacing * 2)); 6553 TmpInst.addOperand(Inst.getOperand(1)); // lane 6554 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6555 TmpInst.addOperand(Inst.getOperand(6)); 6556 Inst = TmpInst; 6557 return true; 6558 } 6559 6560 case ARM::VST4LNdWB_register_Asm_8: 6561 case ARM::VST4LNdWB_register_Asm_16: 6562 case ARM::VST4LNdWB_register_Asm_32: 6563 case ARM::VST4LNqWB_register_Asm_16: 6564 case ARM::VST4LNqWB_register_Asm_32: { 6565 MCInst TmpInst; 6566 // Shuffle the operands around so the lane index operand is in the 6567 // right place. 6568 unsigned Spacing; 6569 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6570 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6571 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6572 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6573 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6574 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6575 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6576 Spacing)); 6577 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6578 Spacing * 2)); 6579 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6580 Spacing * 3)); 6581 TmpInst.addOperand(Inst.getOperand(1)); // lane 6582 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6583 TmpInst.addOperand(Inst.getOperand(6)); 6584 Inst = TmpInst; 6585 return true; 6586 } 6587 6588 case ARM::VST1LNdWB_fixed_Asm_8: 6589 case ARM::VST1LNdWB_fixed_Asm_16: 6590 case ARM::VST1LNdWB_fixed_Asm_32: { 6591 MCInst TmpInst; 6592 // Shuffle the operands around so the lane index operand is in the 6593 // right place. 6594 unsigned Spacing; 6595 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6596 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6597 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6598 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6599 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6600 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6601 TmpInst.addOperand(Inst.getOperand(1)); // lane 6602 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6603 TmpInst.addOperand(Inst.getOperand(5)); 6604 Inst = TmpInst; 6605 return true; 6606 } 6607 6608 case ARM::VST2LNdWB_fixed_Asm_8: 6609 case ARM::VST2LNdWB_fixed_Asm_16: 6610 case ARM::VST2LNdWB_fixed_Asm_32: 6611 case ARM::VST2LNqWB_fixed_Asm_16: 6612 case ARM::VST2LNqWB_fixed_Asm_32: { 6613 MCInst TmpInst; 6614 // Shuffle the operands around so the lane index operand is in the 6615 // right place. 6616 unsigned Spacing; 6617 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6618 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6619 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6620 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6621 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6622 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6623 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6624 Spacing)); 6625 TmpInst.addOperand(Inst.getOperand(1)); // lane 6626 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6627 TmpInst.addOperand(Inst.getOperand(5)); 6628 Inst = TmpInst; 6629 return true; 6630 } 6631 6632 case ARM::VST3LNdWB_fixed_Asm_8: 6633 case ARM::VST3LNdWB_fixed_Asm_16: 6634 case ARM::VST3LNdWB_fixed_Asm_32: 6635 case ARM::VST3LNqWB_fixed_Asm_16: 6636 case ARM::VST3LNqWB_fixed_Asm_32: { 6637 MCInst TmpInst; 6638 // Shuffle the operands around so the lane index operand is in the 6639 // right place. 6640 unsigned Spacing; 6641 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6642 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6643 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6644 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6645 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6646 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6647 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6648 Spacing)); 6649 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6650 Spacing * 2)); 6651 TmpInst.addOperand(Inst.getOperand(1)); // lane 6652 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6653 TmpInst.addOperand(Inst.getOperand(5)); 6654 Inst = TmpInst; 6655 return true; 6656 } 6657 6658 case ARM::VST4LNdWB_fixed_Asm_8: 6659 case ARM::VST4LNdWB_fixed_Asm_16: 6660 case ARM::VST4LNdWB_fixed_Asm_32: 6661 case ARM::VST4LNqWB_fixed_Asm_16: 6662 case ARM::VST4LNqWB_fixed_Asm_32: { 6663 MCInst TmpInst; 6664 // Shuffle the operands around so the lane index operand is in the 6665 // right place. 6666 unsigned Spacing; 6667 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6668 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6669 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6670 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6671 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6672 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6673 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6674 Spacing)); 6675 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6676 Spacing * 2)); 6677 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6678 Spacing * 3)); 6679 TmpInst.addOperand(Inst.getOperand(1)); // lane 6680 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6681 TmpInst.addOperand(Inst.getOperand(5)); 6682 Inst = TmpInst; 6683 return true; 6684 } 6685 6686 case ARM::VST1LNdAsm_8: 6687 case ARM::VST1LNdAsm_16: 6688 case ARM::VST1LNdAsm_32: { 6689 MCInst TmpInst; 6690 // Shuffle the operands around so the lane index operand is in the 6691 // right place. 6692 unsigned Spacing; 6693 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6694 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6695 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6696 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6697 TmpInst.addOperand(Inst.getOperand(1)); // lane 6698 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6699 TmpInst.addOperand(Inst.getOperand(5)); 6700 Inst = TmpInst; 6701 return true; 6702 } 6703 6704 case ARM::VST2LNdAsm_8: 6705 case ARM::VST2LNdAsm_16: 6706 case ARM::VST2LNdAsm_32: 6707 case ARM::VST2LNqAsm_16: 6708 case ARM::VST2LNqAsm_32: { 6709 MCInst TmpInst; 6710 // Shuffle the operands around so the lane index operand is in the 6711 // right place. 6712 unsigned Spacing; 6713 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6714 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6715 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6716 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6717 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6718 Spacing)); 6719 TmpInst.addOperand(Inst.getOperand(1)); // lane 6720 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6721 TmpInst.addOperand(Inst.getOperand(5)); 6722 Inst = TmpInst; 6723 return true; 6724 } 6725 6726 case ARM::VST3LNdAsm_8: 6727 case ARM::VST3LNdAsm_16: 6728 case ARM::VST3LNdAsm_32: 6729 case ARM::VST3LNqAsm_16: 6730 case ARM::VST3LNqAsm_32: { 6731 MCInst TmpInst; 6732 // Shuffle the operands around so the lane index operand is in the 6733 // right place. 6734 unsigned Spacing; 6735 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6736 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6737 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6738 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6739 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6740 Spacing)); 6741 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6742 Spacing * 2)); 6743 TmpInst.addOperand(Inst.getOperand(1)); // lane 6744 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6745 TmpInst.addOperand(Inst.getOperand(5)); 6746 Inst = TmpInst; 6747 return true; 6748 } 6749 6750 case ARM::VST4LNdAsm_8: 6751 case ARM::VST4LNdAsm_16: 6752 case ARM::VST4LNdAsm_32: 6753 case ARM::VST4LNqAsm_16: 6754 case ARM::VST4LNqAsm_32: { 6755 MCInst TmpInst; 6756 // Shuffle the operands around so the lane index operand is in the 6757 // right place. 6758 unsigned Spacing; 6759 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6760 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6761 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6762 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6763 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6764 Spacing)); 6765 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6766 Spacing * 2)); 6767 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6768 Spacing * 3)); 6769 TmpInst.addOperand(Inst.getOperand(1)); // lane 6770 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6771 TmpInst.addOperand(Inst.getOperand(5)); 6772 Inst = TmpInst; 6773 return true; 6774 } 6775 6776 // Handle NEON VLD complex aliases. 6777 case ARM::VLD1LNdWB_register_Asm_8: 6778 case ARM::VLD1LNdWB_register_Asm_16: 6779 case ARM::VLD1LNdWB_register_Asm_32: { 6780 MCInst TmpInst; 6781 // Shuffle the operands around so the lane index operand is in the 6782 // right place. 6783 unsigned Spacing; 6784 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6785 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6786 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6787 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6788 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6789 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6790 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6791 TmpInst.addOperand(Inst.getOperand(1)); // lane 6792 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6793 TmpInst.addOperand(Inst.getOperand(6)); 6794 Inst = TmpInst; 6795 return true; 6796 } 6797 6798 case ARM::VLD2LNdWB_register_Asm_8: 6799 case ARM::VLD2LNdWB_register_Asm_16: 6800 case ARM::VLD2LNdWB_register_Asm_32: 6801 case ARM::VLD2LNqWB_register_Asm_16: 6802 case ARM::VLD2LNqWB_register_Asm_32: { 6803 MCInst TmpInst; 6804 // Shuffle the operands around so the lane index operand is in the 6805 // right place. 6806 unsigned Spacing; 6807 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6808 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6809 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6810 Spacing)); 6811 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6812 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6813 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6814 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6815 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6816 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6817 Spacing)); 6818 TmpInst.addOperand(Inst.getOperand(1)); // lane 6819 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6820 TmpInst.addOperand(Inst.getOperand(6)); 6821 Inst = TmpInst; 6822 return true; 6823 } 6824 6825 case ARM::VLD3LNdWB_register_Asm_8: 6826 case ARM::VLD3LNdWB_register_Asm_16: 6827 case ARM::VLD3LNdWB_register_Asm_32: 6828 case ARM::VLD3LNqWB_register_Asm_16: 6829 case ARM::VLD3LNqWB_register_Asm_32: { 6830 MCInst TmpInst; 6831 // Shuffle the operands around so the lane index operand is in the 6832 // right place. 6833 unsigned Spacing; 6834 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6835 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6836 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6837 Spacing)); 6838 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6839 Spacing * 2)); 6840 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6841 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6842 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6843 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6844 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6845 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6846 Spacing)); 6847 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6848 Spacing * 2)); 6849 TmpInst.addOperand(Inst.getOperand(1)); // lane 6850 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6851 TmpInst.addOperand(Inst.getOperand(6)); 6852 Inst = TmpInst; 6853 return true; 6854 } 6855 6856 case ARM::VLD4LNdWB_register_Asm_8: 6857 case ARM::VLD4LNdWB_register_Asm_16: 6858 case ARM::VLD4LNdWB_register_Asm_32: 6859 case ARM::VLD4LNqWB_register_Asm_16: 6860 case ARM::VLD4LNqWB_register_Asm_32: { 6861 MCInst TmpInst; 6862 // Shuffle the operands around so the lane index operand is in the 6863 // right place. 6864 unsigned Spacing; 6865 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6866 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6867 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6868 Spacing)); 6869 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6870 Spacing * 2)); 6871 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6872 Spacing * 3)); 6873 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6874 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6875 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6876 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6877 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6878 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6879 Spacing)); 6880 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6881 Spacing * 2)); 6882 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6883 Spacing * 3)); 6884 TmpInst.addOperand(Inst.getOperand(1)); // lane 6885 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6886 TmpInst.addOperand(Inst.getOperand(6)); 6887 Inst = TmpInst; 6888 return true; 6889 } 6890 6891 case ARM::VLD1LNdWB_fixed_Asm_8: 6892 case ARM::VLD1LNdWB_fixed_Asm_16: 6893 case ARM::VLD1LNdWB_fixed_Asm_32: { 6894 MCInst TmpInst; 6895 // Shuffle the operands around so the lane index operand is in the 6896 // right place. 6897 unsigned Spacing; 6898 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6899 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6900 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6901 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6902 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6903 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6904 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6905 TmpInst.addOperand(Inst.getOperand(1)); // lane 6906 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6907 TmpInst.addOperand(Inst.getOperand(5)); 6908 Inst = TmpInst; 6909 return true; 6910 } 6911 6912 case ARM::VLD2LNdWB_fixed_Asm_8: 6913 case ARM::VLD2LNdWB_fixed_Asm_16: 6914 case ARM::VLD2LNdWB_fixed_Asm_32: 6915 case ARM::VLD2LNqWB_fixed_Asm_16: 6916 case ARM::VLD2LNqWB_fixed_Asm_32: { 6917 MCInst TmpInst; 6918 // Shuffle the operands around so the lane index operand is in the 6919 // right place. 6920 unsigned Spacing; 6921 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6922 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6923 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6924 Spacing)); 6925 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6926 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6927 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6928 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6929 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6930 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6931 Spacing)); 6932 TmpInst.addOperand(Inst.getOperand(1)); // lane 6933 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6934 TmpInst.addOperand(Inst.getOperand(5)); 6935 Inst = TmpInst; 6936 return true; 6937 } 6938 6939 case ARM::VLD3LNdWB_fixed_Asm_8: 6940 case ARM::VLD3LNdWB_fixed_Asm_16: 6941 case ARM::VLD3LNdWB_fixed_Asm_32: 6942 case ARM::VLD3LNqWB_fixed_Asm_16: 6943 case ARM::VLD3LNqWB_fixed_Asm_32: { 6944 MCInst TmpInst; 6945 // Shuffle the operands around so the lane index operand is in the 6946 // right place. 6947 unsigned Spacing; 6948 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6949 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6950 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6951 Spacing)); 6952 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6953 Spacing * 2)); 6954 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6955 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6956 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6957 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6958 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6959 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6960 Spacing)); 6961 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6962 Spacing * 2)); 6963 TmpInst.addOperand(Inst.getOperand(1)); // lane 6964 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6965 TmpInst.addOperand(Inst.getOperand(5)); 6966 Inst = TmpInst; 6967 return true; 6968 } 6969 6970 case ARM::VLD4LNdWB_fixed_Asm_8: 6971 case ARM::VLD4LNdWB_fixed_Asm_16: 6972 case ARM::VLD4LNdWB_fixed_Asm_32: 6973 case ARM::VLD4LNqWB_fixed_Asm_16: 6974 case ARM::VLD4LNqWB_fixed_Asm_32: { 6975 MCInst TmpInst; 6976 // Shuffle the operands around so the lane index operand is in the 6977 // right place. 6978 unsigned Spacing; 6979 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6980 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6981 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6982 Spacing)); 6983 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6984 Spacing * 2)); 6985 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6986 Spacing * 3)); 6987 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6988 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6989 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6990 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6991 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6992 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6993 Spacing)); 6994 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6995 Spacing * 2)); 6996 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6997 Spacing * 3)); 6998 TmpInst.addOperand(Inst.getOperand(1)); // lane 6999 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7000 TmpInst.addOperand(Inst.getOperand(5)); 7001 Inst = TmpInst; 7002 return true; 7003 } 7004 7005 case ARM::VLD1LNdAsm_8: 7006 case ARM::VLD1LNdAsm_16: 7007 case ARM::VLD1LNdAsm_32: { 7008 MCInst TmpInst; 7009 // Shuffle the operands around so the lane index operand is in the 7010 // right place. 7011 unsigned Spacing; 7012 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7013 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7014 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7015 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7016 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7017 TmpInst.addOperand(Inst.getOperand(1)); // lane 7018 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7019 TmpInst.addOperand(Inst.getOperand(5)); 7020 Inst = TmpInst; 7021 return true; 7022 } 7023 7024 case ARM::VLD2LNdAsm_8: 7025 case ARM::VLD2LNdAsm_16: 7026 case ARM::VLD2LNdAsm_32: 7027 case ARM::VLD2LNqAsm_16: 7028 case ARM::VLD2LNqAsm_32: { 7029 MCInst TmpInst; 7030 // Shuffle the operands around so the lane index operand is in the 7031 // right place. 7032 unsigned Spacing; 7033 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7034 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7035 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7036 Spacing)); 7037 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7038 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7039 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7040 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7041 Spacing)); 7042 TmpInst.addOperand(Inst.getOperand(1)); // lane 7043 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7044 TmpInst.addOperand(Inst.getOperand(5)); 7045 Inst = TmpInst; 7046 return true; 7047 } 7048 7049 case ARM::VLD3LNdAsm_8: 7050 case ARM::VLD3LNdAsm_16: 7051 case ARM::VLD3LNdAsm_32: 7052 case ARM::VLD3LNqAsm_16: 7053 case ARM::VLD3LNqAsm_32: { 7054 MCInst TmpInst; 7055 // Shuffle the operands around so the lane index operand is in the 7056 // right place. 7057 unsigned Spacing; 7058 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7059 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7060 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7061 Spacing)); 7062 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7063 Spacing * 2)); 7064 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7065 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7066 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7067 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7068 Spacing)); 7069 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7070 Spacing * 2)); 7071 TmpInst.addOperand(Inst.getOperand(1)); // lane 7072 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7073 TmpInst.addOperand(Inst.getOperand(5)); 7074 Inst = TmpInst; 7075 return true; 7076 } 7077 7078 case ARM::VLD4LNdAsm_8: 7079 case ARM::VLD4LNdAsm_16: 7080 case ARM::VLD4LNdAsm_32: 7081 case ARM::VLD4LNqAsm_16: 7082 case ARM::VLD4LNqAsm_32: { 7083 MCInst TmpInst; 7084 // Shuffle the operands around so the lane index operand is in the 7085 // right place. 7086 unsigned Spacing; 7087 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7088 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7089 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7090 Spacing)); 7091 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7092 Spacing * 2)); 7093 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7094 Spacing * 3)); 7095 TmpInst.addOperand(Inst.getOperand(2)); // Rn 7096 TmpInst.addOperand(Inst.getOperand(3)); // alignment 7097 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 7098 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7099 Spacing)); 7100 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7101 Spacing * 2)); 7102 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7103 Spacing * 3)); 7104 TmpInst.addOperand(Inst.getOperand(1)); // lane 7105 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7106 TmpInst.addOperand(Inst.getOperand(5)); 7107 Inst = TmpInst; 7108 return true; 7109 } 7110 7111 // VLD3DUP single 3-element structure to all lanes instructions. 7112 case ARM::VLD3DUPdAsm_8: 7113 case ARM::VLD3DUPdAsm_16: 7114 case ARM::VLD3DUPdAsm_32: 7115 case ARM::VLD3DUPqAsm_8: 7116 case ARM::VLD3DUPqAsm_16: 7117 case ARM::VLD3DUPqAsm_32: { 7118 MCInst TmpInst; 7119 unsigned Spacing; 7120 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7121 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7122 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7123 Spacing)); 7124 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7125 Spacing * 2)); 7126 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7127 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7128 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7129 TmpInst.addOperand(Inst.getOperand(4)); 7130 Inst = TmpInst; 7131 return true; 7132 } 7133 7134 case ARM::VLD3DUPdWB_fixed_Asm_8: 7135 case ARM::VLD3DUPdWB_fixed_Asm_16: 7136 case ARM::VLD3DUPdWB_fixed_Asm_32: 7137 case ARM::VLD3DUPqWB_fixed_Asm_8: 7138 case ARM::VLD3DUPqWB_fixed_Asm_16: 7139 case ARM::VLD3DUPqWB_fixed_Asm_32: { 7140 MCInst TmpInst; 7141 unsigned Spacing; 7142 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7143 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7144 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7145 Spacing)); 7146 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7147 Spacing * 2)); 7148 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7149 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7150 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7151 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7152 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7153 TmpInst.addOperand(Inst.getOperand(4)); 7154 Inst = TmpInst; 7155 return true; 7156 } 7157 7158 case ARM::VLD3DUPdWB_register_Asm_8: 7159 case ARM::VLD3DUPdWB_register_Asm_16: 7160 case ARM::VLD3DUPdWB_register_Asm_32: 7161 case ARM::VLD3DUPqWB_register_Asm_8: 7162 case ARM::VLD3DUPqWB_register_Asm_16: 7163 case ARM::VLD3DUPqWB_register_Asm_32: { 7164 MCInst TmpInst; 7165 unsigned Spacing; 7166 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7167 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7168 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7169 Spacing)); 7170 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7171 Spacing * 2)); 7172 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7173 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7174 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7175 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7176 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7177 TmpInst.addOperand(Inst.getOperand(5)); 7178 Inst = TmpInst; 7179 return true; 7180 } 7181 7182 // VLD3 multiple 3-element structure instructions. 7183 case ARM::VLD3dAsm_8: 7184 case ARM::VLD3dAsm_16: 7185 case ARM::VLD3dAsm_32: 7186 case ARM::VLD3qAsm_8: 7187 case ARM::VLD3qAsm_16: 7188 case ARM::VLD3qAsm_32: { 7189 MCInst TmpInst; 7190 unsigned Spacing; 7191 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7192 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7193 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7194 Spacing)); 7195 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7196 Spacing * 2)); 7197 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7198 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7199 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7200 TmpInst.addOperand(Inst.getOperand(4)); 7201 Inst = TmpInst; 7202 return true; 7203 } 7204 7205 case ARM::VLD3dWB_fixed_Asm_8: 7206 case ARM::VLD3dWB_fixed_Asm_16: 7207 case ARM::VLD3dWB_fixed_Asm_32: 7208 case ARM::VLD3qWB_fixed_Asm_8: 7209 case ARM::VLD3qWB_fixed_Asm_16: 7210 case ARM::VLD3qWB_fixed_Asm_32: { 7211 MCInst TmpInst; 7212 unsigned Spacing; 7213 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7214 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7215 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7216 Spacing)); 7217 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7218 Spacing * 2)); 7219 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7220 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7221 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7222 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7223 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7224 TmpInst.addOperand(Inst.getOperand(4)); 7225 Inst = TmpInst; 7226 return true; 7227 } 7228 7229 case ARM::VLD3dWB_register_Asm_8: 7230 case ARM::VLD3dWB_register_Asm_16: 7231 case ARM::VLD3dWB_register_Asm_32: 7232 case ARM::VLD3qWB_register_Asm_8: 7233 case ARM::VLD3qWB_register_Asm_16: 7234 case ARM::VLD3qWB_register_Asm_32: { 7235 MCInst TmpInst; 7236 unsigned Spacing; 7237 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7238 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7239 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7240 Spacing)); 7241 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7242 Spacing * 2)); 7243 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7244 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7245 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7246 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7247 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7248 TmpInst.addOperand(Inst.getOperand(5)); 7249 Inst = TmpInst; 7250 return true; 7251 } 7252 7253 // VLD4DUP single 3-element structure to all lanes instructions. 7254 case ARM::VLD4DUPdAsm_8: 7255 case ARM::VLD4DUPdAsm_16: 7256 case ARM::VLD4DUPdAsm_32: 7257 case ARM::VLD4DUPqAsm_8: 7258 case ARM::VLD4DUPqAsm_16: 7259 case ARM::VLD4DUPqAsm_32: { 7260 MCInst TmpInst; 7261 unsigned Spacing; 7262 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7263 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7265 Spacing)); 7266 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7267 Spacing * 2)); 7268 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7269 Spacing * 3)); 7270 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7271 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7272 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7273 TmpInst.addOperand(Inst.getOperand(4)); 7274 Inst = TmpInst; 7275 return true; 7276 } 7277 7278 case ARM::VLD4DUPdWB_fixed_Asm_8: 7279 case ARM::VLD4DUPdWB_fixed_Asm_16: 7280 case ARM::VLD4DUPdWB_fixed_Asm_32: 7281 case ARM::VLD4DUPqWB_fixed_Asm_8: 7282 case ARM::VLD4DUPqWB_fixed_Asm_16: 7283 case ARM::VLD4DUPqWB_fixed_Asm_32: { 7284 MCInst TmpInst; 7285 unsigned Spacing; 7286 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7287 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7288 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7289 Spacing)); 7290 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7291 Spacing * 2)); 7292 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7293 Spacing * 3)); 7294 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7295 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7296 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7297 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7298 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7299 TmpInst.addOperand(Inst.getOperand(4)); 7300 Inst = TmpInst; 7301 return true; 7302 } 7303 7304 case ARM::VLD4DUPdWB_register_Asm_8: 7305 case ARM::VLD4DUPdWB_register_Asm_16: 7306 case ARM::VLD4DUPdWB_register_Asm_32: 7307 case ARM::VLD4DUPqWB_register_Asm_8: 7308 case ARM::VLD4DUPqWB_register_Asm_16: 7309 case ARM::VLD4DUPqWB_register_Asm_32: { 7310 MCInst TmpInst; 7311 unsigned Spacing; 7312 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7313 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7314 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7315 Spacing)); 7316 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7317 Spacing * 2)); 7318 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7319 Spacing * 3)); 7320 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7321 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7322 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7323 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7324 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7325 TmpInst.addOperand(Inst.getOperand(5)); 7326 Inst = TmpInst; 7327 return true; 7328 } 7329 7330 // VLD4 multiple 4-element structure instructions. 7331 case ARM::VLD4dAsm_8: 7332 case ARM::VLD4dAsm_16: 7333 case ARM::VLD4dAsm_32: 7334 case ARM::VLD4qAsm_8: 7335 case ARM::VLD4qAsm_16: 7336 case ARM::VLD4qAsm_32: { 7337 MCInst TmpInst; 7338 unsigned Spacing; 7339 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7340 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7341 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7342 Spacing)); 7343 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7344 Spacing * 2)); 7345 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7346 Spacing * 3)); 7347 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7348 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7349 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7350 TmpInst.addOperand(Inst.getOperand(4)); 7351 Inst = TmpInst; 7352 return true; 7353 } 7354 7355 case ARM::VLD4dWB_fixed_Asm_8: 7356 case ARM::VLD4dWB_fixed_Asm_16: 7357 case ARM::VLD4dWB_fixed_Asm_32: 7358 case ARM::VLD4qWB_fixed_Asm_8: 7359 case ARM::VLD4qWB_fixed_Asm_16: 7360 case ARM::VLD4qWB_fixed_Asm_32: { 7361 MCInst TmpInst; 7362 unsigned Spacing; 7363 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7364 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7366 Spacing)); 7367 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7368 Spacing * 2)); 7369 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7370 Spacing * 3)); 7371 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7372 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7373 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7374 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7375 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7376 TmpInst.addOperand(Inst.getOperand(4)); 7377 Inst = TmpInst; 7378 return true; 7379 } 7380 7381 case ARM::VLD4dWB_register_Asm_8: 7382 case ARM::VLD4dWB_register_Asm_16: 7383 case ARM::VLD4dWB_register_Asm_32: 7384 case ARM::VLD4qWB_register_Asm_8: 7385 case ARM::VLD4qWB_register_Asm_16: 7386 case ARM::VLD4qWB_register_Asm_32: { 7387 MCInst TmpInst; 7388 unsigned Spacing; 7389 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 7390 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7391 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7392 Spacing)); 7393 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7394 Spacing * 2)); 7395 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7396 Spacing * 3)); 7397 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7398 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7399 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7400 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7401 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7402 TmpInst.addOperand(Inst.getOperand(5)); 7403 Inst = TmpInst; 7404 return true; 7405 } 7406 7407 // VST3 multiple 3-element structure instructions. 7408 case ARM::VST3dAsm_8: 7409 case ARM::VST3dAsm_16: 7410 case ARM::VST3dAsm_32: 7411 case ARM::VST3qAsm_8: 7412 case ARM::VST3qAsm_16: 7413 case ARM::VST3qAsm_32: { 7414 MCInst TmpInst; 7415 unsigned Spacing; 7416 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7417 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7418 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7419 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7420 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7421 Spacing)); 7422 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7423 Spacing * 2)); 7424 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7425 TmpInst.addOperand(Inst.getOperand(4)); 7426 Inst = TmpInst; 7427 return true; 7428 } 7429 7430 case ARM::VST3dWB_fixed_Asm_8: 7431 case ARM::VST3dWB_fixed_Asm_16: 7432 case ARM::VST3dWB_fixed_Asm_32: 7433 case ARM::VST3qWB_fixed_Asm_8: 7434 case ARM::VST3qWB_fixed_Asm_16: 7435 case ARM::VST3qWB_fixed_Asm_32: { 7436 MCInst TmpInst; 7437 unsigned Spacing; 7438 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7439 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7440 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7441 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7442 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7443 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7444 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7445 Spacing)); 7446 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7447 Spacing * 2)); 7448 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7449 TmpInst.addOperand(Inst.getOperand(4)); 7450 Inst = TmpInst; 7451 return true; 7452 } 7453 7454 case ARM::VST3dWB_register_Asm_8: 7455 case ARM::VST3dWB_register_Asm_16: 7456 case ARM::VST3dWB_register_Asm_32: 7457 case ARM::VST3qWB_register_Asm_8: 7458 case ARM::VST3qWB_register_Asm_16: 7459 case ARM::VST3qWB_register_Asm_32: { 7460 MCInst TmpInst; 7461 unsigned Spacing; 7462 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7463 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7464 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7465 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7466 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7467 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7468 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7469 Spacing)); 7470 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7471 Spacing * 2)); 7472 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7473 TmpInst.addOperand(Inst.getOperand(5)); 7474 Inst = TmpInst; 7475 return true; 7476 } 7477 7478 // VST4 multiple 3-element structure instructions. 7479 case ARM::VST4dAsm_8: 7480 case ARM::VST4dAsm_16: 7481 case ARM::VST4dAsm_32: 7482 case ARM::VST4qAsm_8: 7483 case ARM::VST4qAsm_16: 7484 case ARM::VST4qAsm_32: { 7485 MCInst TmpInst; 7486 unsigned Spacing; 7487 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7488 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7489 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7490 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7491 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7492 Spacing)); 7493 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7494 Spacing * 2)); 7495 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7496 Spacing * 3)); 7497 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7498 TmpInst.addOperand(Inst.getOperand(4)); 7499 Inst = TmpInst; 7500 return true; 7501 } 7502 7503 case ARM::VST4dWB_fixed_Asm_8: 7504 case ARM::VST4dWB_fixed_Asm_16: 7505 case ARM::VST4dWB_fixed_Asm_32: 7506 case ARM::VST4qWB_fixed_Asm_8: 7507 case ARM::VST4qWB_fixed_Asm_16: 7508 case ARM::VST4qWB_fixed_Asm_32: { 7509 MCInst TmpInst; 7510 unsigned Spacing; 7511 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7512 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7513 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7514 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7515 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 7516 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7517 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7518 Spacing)); 7519 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7520 Spacing * 2)); 7521 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7522 Spacing * 3)); 7523 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7524 TmpInst.addOperand(Inst.getOperand(4)); 7525 Inst = TmpInst; 7526 return true; 7527 } 7528 7529 case ARM::VST4dWB_register_Asm_8: 7530 case ARM::VST4dWB_register_Asm_16: 7531 case ARM::VST4dWB_register_Asm_32: 7532 case ARM::VST4qWB_register_Asm_8: 7533 case ARM::VST4qWB_register_Asm_16: 7534 case ARM::VST4qWB_register_Asm_32: { 7535 MCInst TmpInst; 7536 unsigned Spacing; 7537 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 7538 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7539 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 7540 TmpInst.addOperand(Inst.getOperand(2)); // alignment 7541 TmpInst.addOperand(Inst.getOperand(3)); // Rm 7542 TmpInst.addOperand(Inst.getOperand(0)); // Vd 7543 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7544 Spacing)); 7545 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7546 Spacing * 2)); 7547 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 7548 Spacing * 3)); 7549 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7550 TmpInst.addOperand(Inst.getOperand(5)); 7551 Inst = TmpInst; 7552 return true; 7553 } 7554 7555 // Handle encoding choice for the shift-immediate instructions. 7556 case ARM::t2LSLri: 7557 case ARM::t2LSRri: 7558 case ARM::t2ASRri: { 7559 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7560 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7561 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 7562 !(static_cast<ARMOperand &>(*Operands[3]).isToken() && 7563 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) { 7564 unsigned NewOpc; 7565 switch (Inst.getOpcode()) { 7566 default: llvm_unreachable("unexpected opcode"); 7567 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 7568 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 7569 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 7570 } 7571 // The Thumb1 operands aren't in the same order. Awesome, eh? 7572 MCInst TmpInst; 7573 TmpInst.setOpcode(NewOpc); 7574 TmpInst.addOperand(Inst.getOperand(0)); 7575 TmpInst.addOperand(Inst.getOperand(5)); 7576 TmpInst.addOperand(Inst.getOperand(1)); 7577 TmpInst.addOperand(Inst.getOperand(2)); 7578 TmpInst.addOperand(Inst.getOperand(3)); 7579 TmpInst.addOperand(Inst.getOperand(4)); 7580 Inst = TmpInst; 7581 return true; 7582 } 7583 return false; 7584 } 7585 7586 // Handle the Thumb2 mode MOV complex aliases. 7587 case ARM::t2MOVsr: 7588 case ARM::t2MOVSsr: { 7589 // Which instruction to expand to depends on the CCOut operand and 7590 // whether we're in an IT block if the register operands are low 7591 // registers. 7592 bool isNarrow = false; 7593 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7594 isARMLowRegister(Inst.getOperand(1).getReg()) && 7595 isARMLowRegister(Inst.getOperand(2).getReg()) && 7596 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7597 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 7598 isNarrow = true; 7599 MCInst TmpInst; 7600 unsigned newOpc; 7601 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 7602 default: llvm_unreachable("unexpected opcode!"); 7603 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 7604 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 7605 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 7606 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 7607 } 7608 TmpInst.setOpcode(newOpc); 7609 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7610 if (isNarrow) 7611 TmpInst.addOperand(MCOperand::CreateReg( 7612 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7613 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7614 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7615 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 7616 TmpInst.addOperand(Inst.getOperand(5)); 7617 if (!isNarrow) 7618 TmpInst.addOperand(MCOperand::CreateReg( 7619 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 7620 Inst = TmpInst; 7621 return true; 7622 } 7623 case ARM::t2MOVsi: 7624 case ARM::t2MOVSsi: { 7625 // Which instruction to expand to depends on the CCOut operand and 7626 // whether we're in an IT block if the register operands are low 7627 // registers. 7628 bool isNarrow = false; 7629 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7630 isARMLowRegister(Inst.getOperand(1).getReg()) && 7631 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 7632 isNarrow = true; 7633 MCInst TmpInst; 7634 unsigned newOpc; 7635 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 7636 default: llvm_unreachable("unexpected opcode!"); 7637 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 7638 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 7639 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 7640 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 7641 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 7642 } 7643 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 7644 if (Amount == 32) Amount = 0; 7645 TmpInst.setOpcode(newOpc); 7646 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7647 if (isNarrow) 7648 TmpInst.addOperand(MCOperand::CreateReg( 7649 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7650 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7651 if (newOpc != ARM::t2RRX) 7652 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 7653 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7654 TmpInst.addOperand(Inst.getOperand(4)); 7655 if (!isNarrow) 7656 TmpInst.addOperand(MCOperand::CreateReg( 7657 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 7658 Inst = TmpInst; 7659 return true; 7660 } 7661 // Handle the ARM mode MOV complex aliases. 7662 case ARM::ASRr: 7663 case ARM::LSRr: 7664 case ARM::LSLr: 7665 case ARM::RORr: { 7666 ARM_AM::ShiftOpc ShiftTy; 7667 switch(Inst.getOpcode()) { 7668 default: llvm_unreachable("unexpected opcode!"); 7669 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 7670 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 7671 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 7672 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 7673 } 7674 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 7675 MCInst TmpInst; 7676 TmpInst.setOpcode(ARM::MOVsr); 7677 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7678 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7679 TmpInst.addOperand(Inst.getOperand(2)); // Rm 7680 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7681 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7682 TmpInst.addOperand(Inst.getOperand(4)); 7683 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7684 Inst = TmpInst; 7685 return true; 7686 } 7687 case ARM::ASRi: 7688 case ARM::LSRi: 7689 case ARM::LSLi: 7690 case ARM::RORi: { 7691 ARM_AM::ShiftOpc ShiftTy; 7692 switch(Inst.getOpcode()) { 7693 default: llvm_unreachable("unexpected opcode!"); 7694 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 7695 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 7696 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 7697 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 7698 } 7699 // A shift by zero is a plain MOVr, not a MOVsi. 7700 unsigned Amt = Inst.getOperand(2).getImm(); 7701 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 7702 // A shift by 32 should be encoded as 0 when permitted 7703 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 7704 Amt = 0; 7705 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 7706 MCInst TmpInst; 7707 TmpInst.setOpcode(Opc); 7708 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7709 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7710 if (Opc == ARM::MOVsi) 7711 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7712 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 7713 TmpInst.addOperand(Inst.getOperand(4)); 7714 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 7715 Inst = TmpInst; 7716 return true; 7717 } 7718 case ARM::RRXi: { 7719 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 7720 MCInst TmpInst; 7721 TmpInst.setOpcode(ARM::MOVsi); 7722 TmpInst.addOperand(Inst.getOperand(0)); // Rd 7723 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7724 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 7725 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7726 TmpInst.addOperand(Inst.getOperand(3)); 7727 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 7728 Inst = TmpInst; 7729 return true; 7730 } 7731 case ARM::t2LDMIA_UPD: { 7732 // If this is a load of a single register, then we should use 7733 // a post-indexed LDR instruction instead, per the ARM ARM. 7734 if (Inst.getNumOperands() != 5) 7735 return false; 7736 MCInst TmpInst; 7737 TmpInst.setOpcode(ARM::t2LDR_POST); 7738 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7739 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7740 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7741 TmpInst.addOperand(MCOperand::CreateImm(4)); 7742 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7743 TmpInst.addOperand(Inst.getOperand(3)); 7744 Inst = TmpInst; 7745 return true; 7746 } 7747 case ARM::t2STMDB_UPD: { 7748 // If this is a store of a single register, then we should use 7749 // a pre-indexed STR instruction instead, per the ARM ARM. 7750 if (Inst.getNumOperands() != 5) 7751 return false; 7752 MCInst TmpInst; 7753 TmpInst.setOpcode(ARM::t2STR_PRE); 7754 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7755 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7756 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7757 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7758 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7759 TmpInst.addOperand(Inst.getOperand(3)); 7760 Inst = TmpInst; 7761 return true; 7762 } 7763 case ARM::LDMIA_UPD: 7764 // If this is a load of a single register via a 'pop', then we should use 7765 // a post-indexed LDR instruction instead, per the ARM ARM. 7766 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && 7767 Inst.getNumOperands() == 5) { 7768 MCInst TmpInst; 7769 TmpInst.setOpcode(ARM::LDR_POST_IMM); 7770 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7771 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7772 TmpInst.addOperand(Inst.getOperand(1)); // Rn 7773 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 7774 TmpInst.addOperand(MCOperand::CreateImm(4)); 7775 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7776 TmpInst.addOperand(Inst.getOperand(3)); 7777 Inst = TmpInst; 7778 return true; 7779 } 7780 break; 7781 case ARM::STMDB_UPD: 7782 // If this is a store of a single register via a 'push', then we should use 7783 // a pre-indexed STR instruction instead, per the ARM ARM. 7784 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && 7785 Inst.getNumOperands() == 5) { 7786 MCInst TmpInst; 7787 TmpInst.setOpcode(ARM::STR_PRE_IMM); 7788 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 7789 TmpInst.addOperand(Inst.getOperand(4)); // Rt 7790 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 7791 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7792 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7793 TmpInst.addOperand(Inst.getOperand(3)); 7794 Inst = TmpInst; 7795 } 7796 break; 7797 case ARM::t2ADDri12: 7798 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 7799 // mnemonic was used (not "addw"), encoding T3 is preferred. 7800 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" || 7801 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7802 break; 7803 Inst.setOpcode(ARM::t2ADDri); 7804 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7805 break; 7806 case ARM::t2SUBri12: 7807 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 7808 // mnemonic was used (not "subw"), encoding T3 is preferred. 7809 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" || 7810 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7811 break; 7812 Inst.setOpcode(ARM::t2SUBri); 7813 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7814 break; 7815 case ARM::tADDi8: 7816 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7817 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7818 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7819 // to encoding T1 if <Rd> is omitted." 7820 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7821 Inst.setOpcode(ARM::tADDi3); 7822 return true; 7823 } 7824 break; 7825 case ARM::tSUBi8: 7826 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7827 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7828 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7829 // to encoding T1 if <Rd> is omitted." 7830 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7831 Inst.setOpcode(ARM::tSUBi3); 7832 return true; 7833 } 7834 break; 7835 case ARM::t2ADDri: 7836 case ARM::t2SUBri: { 7837 // If the destination and first source operand are the same, and 7838 // the flags are compatible with the current IT status, use encoding T2 7839 // instead of T3. For compatibility with the system 'as'. Make sure the 7840 // wide encoding wasn't explicit. 7841 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7842 !isARMLowRegister(Inst.getOperand(0).getReg()) || 7843 (unsigned)Inst.getOperand(2).getImm() > 255 || 7844 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 7845 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 7846 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 7847 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) 7848 break; 7849 MCInst TmpInst; 7850 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7851 ARM::tADDi8 : ARM::tSUBi8); 7852 TmpInst.addOperand(Inst.getOperand(0)); 7853 TmpInst.addOperand(Inst.getOperand(5)); 7854 TmpInst.addOperand(Inst.getOperand(0)); 7855 TmpInst.addOperand(Inst.getOperand(2)); 7856 TmpInst.addOperand(Inst.getOperand(3)); 7857 TmpInst.addOperand(Inst.getOperand(4)); 7858 Inst = TmpInst; 7859 return true; 7860 } 7861 case ARM::t2ADDrr: { 7862 // If the destination and first source operand are the same, and 7863 // there's no setting of the flags, use encoding T2 instead of T3. 7864 // Note that this is only for ADD, not SUB. This mirrors the system 7865 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7866 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7867 Inst.getOperand(5).getReg() != 0 || 7868 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 7869 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) 7870 break; 7871 MCInst TmpInst; 7872 TmpInst.setOpcode(ARM::tADDhirr); 7873 TmpInst.addOperand(Inst.getOperand(0)); 7874 TmpInst.addOperand(Inst.getOperand(0)); 7875 TmpInst.addOperand(Inst.getOperand(2)); 7876 TmpInst.addOperand(Inst.getOperand(3)); 7877 TmpInst.addOperand(Inst.getOperand(4)); 7878 Inst = TmpInst; 7879 return true; 7880 } 7881 case ARM::tADDrSP: { 7882 // If the non-SP source operand and the destination operand are not the 7883 // same, we need to use the 32-bit encoding if it's available. 7884 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7885 Inst.setOpcode(ARM::t2ADDrr); 7886 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7887 return true; 7888 } 7889 break; 7890 } 7891 case ARM::tB: 7892 // A Thumb conditional branch outside of an IT block is a tBcc. 7893 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7894 Inst.setOpcode(ARM::tBcc); 7895 return true; 7896 } 7897 break; 7898 case ARM::t2B: 7899 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7900 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7901 Inst.setOpcode(ARM::t2Bcc); 7902 return true; 7903 } 7904 break; 7905 case ARM::t2Bcc: 7906 // If the conditional is AL or we're in an IT block, we really want t2B. 7907 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7908 Inst.setOpcode(ARM::t2B); 7909 return true; 7910 } 7911 break; 7912 case ARM::tBcc: 7913 // If the conditional is AL, we really want tB. 7914 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7915 Inst.setOpcode(ARM::tB); 7916 return true; 7917 } 7918 break; 7919 case ARM::tLDMIA: { 7920 // If the register list contains any high registers, or if the writeback 7921 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7922 // instead if we're in Thumb2. Otherwise, this should have generated 7923 // an error in validateInstruction(). 7924 unsigned Rn = Inst.getOperand(0).getReg(); 7925 bool hasWritebackToken = 7926 (static_cast<ARMOperand &>(*Operands[3]).isToken() && 7927 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); 7928 bool listContainsBase; 7929 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7930 (!listContainsBase && !hasWritebackToken) || 7931 (listContainsBase && hasWritebackToken)) { 7932 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7933 assert (isThumbTwo()); 7934 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7935 // If we're switching to the updating version, we need to insert 7936 // the writeback tied operand. 7937 if (hasWritebackToken) 7938 Inst.insert(Inst.begin(), 7939 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7940 return true; 7941 } 7942 break; 7943 } 7944 case ARM::tSTMIA_UPD: { 7945 // If the register list contains any high registers, we need to use 7946 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7947 // should have generated an error in validateInstruction(). 7948 unsigned Rn = Inst.getOperand(0).getReg(); 7949 bool listContainsBase; 7950 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7951 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7952 assert (isThumbTwo()); 7953 Inst.setOpcode(ARM::t2STMIA_UPD); 7954 return true; 7955 } 7956 break; 7957 } 7958 case ARM::tPOP: { 7959 bool listContainsBase; 7960 // If the register list contains any high registers, we need to use 7961 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7962 // should have generated an error in validateInstruction(). 7963 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7964 return false; 7965 assert (isThumbTwo()); 7966 Inst.setOpcode(ARM::t2LDMIA_UPD); 7967 // Add the base register and writeback operands. 7968 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7969 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7970 return true; 7971 } 7972 case ARM::tPUSH: { 7973 bool listContainsBase; 7974 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7975 return false; 7976 assert (isThumbTwo()); 7977 Inst.setOpcode(ARM::t2STMDB_UPD); 7978 // Add the base register and writeback operands. 7979 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7980 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7981 return true; 7982 } 7983 case ARM::t2MOVi: { 7984 // If we can use the 16-bit encoding and the user didn't explicitly 7985 // request the 32-bit variant, transform it here. 7986 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7987 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7988 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7989 Inst.getOperand(4).getReg() == ARM::CPSR) || 7990 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7991 (!static_cast<ARMOperand &>(*Operands[2]).isToken() || 7992 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { 7993 // The operands aren't in the same order for tMOVi8... 7994 MCInst TmpInst; 7995 TmpInst.setOpcode(ARM::tMOVi8); 7996 TmpInst.addOperand(Inst.getOperand(0)); 7997 TmpInst.addOperand(Inst.getOperand(4)); 7998 TmpInst.addOperand(Inst.getOperand(1)); 7999 TmpInst.addOperand(Inst.getOperand(2)); 8000 TmpInst.addOperand(Inst.getOperand(3)); 8001 Inst = TmpInst; 8002 return true; 8003 } 8004 break; 8005 } 8006 case ARM::t2MOVr: { 8007 // If we can use the 16-bit encoding and the user didn't explicitly 8008 // request the 32-bit variant, transform it here. 8009 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 8010 isARMLowRegister(Inst.getOperand(1).getReg()) && 8011 Inst.getOperand(2).getImm() == ARMCC::AL && 8012 Inst.getOperand(4).getReg() == ARM::CPSR && 8013 (!static_cast<ARMOperand &>(*Operands[2]).isToken() || 8014 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { 8015 // The operands aren't the same for tMOV[S]r... (no cc_out) 8016 MCInst TmpInst; 8017 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 8018 TmpInst.addOperand(Inst.getOperand(0)); 8019 TmpInst.addOperand(Inst.getOperand(1)); 8020 TmpInst.addOperand(Inst.getOperand(2)); 8021 TmpInst.addOperand(Inst.getOperand(3)); 8022 Inst = TmpInst; 8023 return true; 8024 } 8025 break; 8026 } 8027 case ARM::t2SXTH: 8028 case ARM::t2SXTB: 8029 case ARM::t2UXTH: 8030 case ARM::t2UXTB: { 8031 // If we can use the 16-bit encoding and the user didn't explicitly 8032 // request the 32-bit variant, transform it here. 8033 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 8034 isARMLowRegister(Inst.getOperand(1).getReg()) && 8035 Inst.getOperand(2).getImm() == 0 && 8036 (!static_cast<ARMOperand &>(*Operands[2]).isToken() || 8037 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { 8038 unsigned NewOpc; 8039 switch (Inst.getOpcode()) { 8040 default: llvm_unreachable("Illegal opcode!"); 8041 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 8042 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 8043 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 8044 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 8045 } 8046 // The operands aren't the same for thumb1 (no rotate operand). 8047 MCInst TmpInst; 8048 TmpInst.setOpcode(NewOpc); 8049 TmpInst.addOperand(Inst.getOperand(0)); 8050 TmpInst.addOperand(Inst.getOperand(1)); 8051 TmpInst.addOperand(Inst.getOperand(3)); 8052 TmpInst.addOperand(Inst.getOperand(4)); 8053 Inst = TmpInst; 8054 return true; 8055 } 8056 break; 8057 } 8058 case ARM::MOVsi: { 8059 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 8060 // rrx shifts and asr/lsr of #32 is encoded as 0 8061 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 8062 return false; 8063 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 8064 // Shifting by zero is accepted as a vanilla 'MOVr' 8065 MCInst TmpInst; 8066 TmpInst.setOpcode(ARM::MOVr); 8067 TmpInst.addOperand(Inst.getOperand(0)); 8068 TmpInst.addOperand(Inst.getOperand(1)); 8069 TmpInst.addOperand(Inst.getOperand(3)); 8070 TmpInst.addOperand(Inst.getOperand(4)); 8071 TmpInst.addOperand(Inst.getOperand(5)); 8072 Inst = TmpInst; 8073 return true; 8074 } 8075 return false; 8076 } 8077 case ARM::ANDrsi: 8078 case ARM::ORRrsi: 8079 case ARM::EORrsi: 8080 case ARM::BICrsi: 8081 case ARM::SUBrsi: 8082 case ARM::ADDrsi: { 8083 unsigned newOpc; 8084 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 8085 if (SOpc == ARM_AM::rrx) return false; 8086 switch (Inst.getOpcode()) { 8087 default: llvm_unreachable("unexpected opcode!"); 8088 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 8089 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 8090 case ARM::EORrsi: newOpc = ARM::EORrr; break; 8091 case ARM::BICrsi: newOpc = ARM::BICrr; break; 8092 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 8093 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 8094 } 8095 // If the shift is by zero, use the non-shifted instruction definition. 8096 // The exception is for right shifts, where 0 == 32 8097 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 8098 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 8099 MCInst TmpInst; 8100 TmpInst.setOpcode(newOpc); 8101 TmpInst.addOperand(Inst.getOperand(0)); 8102 TmpInst.addOperand(Inst.getOperand(1)); 8103 TmpInst.addOperand(Inst.getOperand(2)); 8104 TmpInst.addOperand(Inst.getOperand(4)); 8105 TmpInst.addOperand(Inst.getOperand(5)); 8106 TmpInst.addOperand(Inst.getOperand(6)); 8107 Inst = TmpInst; 8108 return true; 8109 } 8110 return false; 8111 } 8112 case ARM::ITasm: 8113 case ARM::t2IT: { 8114 // The mask bits for all but the first condition are represented as 8115 // the low bit of the condition code value implies 't'. We currently 8116 // always have 1 implies 't', so XOR toggle the bits if the low bit 8117 // of the condition code is zero. 8118 MCOperand &MO = Inst.getOperand(1); 8119 unsigned Mask = MO.getImm(); 8120 unsigned OrigMask = Mask; 8121 unsigned TZ = countTrailingZeros(Mask); 8122 if ((Inst.getOperand(0).getImm() & 1) == 0) { 8123 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 8124 Mask ^= (0xE << TZ) & 0xF; 8125 } 8126 MO.setImm(Mask); 8127 8128 // Set up the IT block state according to the IT instruction we just 8129 // matched. 8130 assert(!inITBlock() && "nested IT blocks?!"); 8131 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 8132 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 8133 ITState.CurPosition = 0; 8134 ITState.FirstCond = true; 8135 break; 8136 } 8137 case ARM::t2LSLrr: 8138 case ARM::t2LSRrr: 8139 case ARM::t2ASRrr: 8140 case ARM::t2SBCrr: 8141 case ARM::t2RORrr: 8142 case ARM::t2BICrr: 8143 { 8144 // Assemblers should use the narrow encodings of these instructions when permissible. 8145 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 8146 isARMLowRegister(Inst.getOperand(2).getReg())) && 8147 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 8148 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 8149 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 8150 (!static_cast<ARMOperand &>(*Operands[3]).isToken() || 8151 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower( 8152 ".w"))) { 8153 unsigned NewOpc; 8154 switch (Inst.getOpcode()) { 8155 default: llvm_unreachable("unexpected opcode"); 8156 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 8157 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 8158 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 8159 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 8160 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 8161 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 8162 } 8163 MCInst TmpInst; 8164 TmpInst.setOpcode(NewOpc); 8165 TmpInst.addOperand(Inst.getOperand(0)); 8166 TmpInst.addOperand(Inst.getOperand(5)); 8167 TmpInst.addOperand(Inst.getOperand(1)); 8168 TmpInst.addOperand(Inst.getOperand(2)); 8169 TmpInst.addOperand(Inst.getOperand(3)); 8170 TmpInst.addOperand(Inst.getOperand(4)); 8171 Inst = TmpInst; 8172 return true; 8173 } 8174 return false; 8175 } 8176 case ARM::t2ANDrr: 8177 case ARM::t2EORrr: 8178 case ARM::t2ADCrr: 8179 case ARM::t2ORRrr: 8180 { 8181 // Assemblers should use the narrow encodings of these instructions when permissible. 8182 // These instructions are special in that they are commutable, so shorter encodings 8183 // are available more often. 8184 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 8185 isARMLowRegister(Inst.getOperand(2).getReg())) && 8186 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 8187 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 8188 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 8189 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 8190 (!static_cast<ARMOperand &>(*Operands[3]).isToken() || 8191 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower( 8192 ".w"))) { 8193 unsigned NewOpc; 8194 switch (Inst.getOpcode()) { 8195 default: llvm_unreachable("unexpected opcode"); 8196 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 8197 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 8198 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 8199 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 8200 } 8201 MCInst TmpInst; 8202 TmpInst.setOpcode(NewOpc); 8203 TmpInst.addOperand(Inst.getOperand(0)); 8204 TmpInst.addOperand(Inst.getOperand(5)); 8205 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 8206 TmpInst.addOperand(Inst.getOperand(1)); 8207 TmpInst.addOperand(Inst.getOperand(2)); 8208 } else { 8209 TmpInst.addOperand(Inst.getOperand(2)); 8210 TmpInst.addOperand(Inst.getOperand(1)); 8211 } 8212 TmpInst.addOperand(Inst.getOperand(3)); 8213 TmpInst.addOperand(Inst.getOperand(4)); 8214 Inst = TmpInst; 8215 return true; 8216 } 8217 return false; 8218 } 8219 } 8220 return false; 8221 } 8222 8223 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 8224 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 8225 // suffix depending on whether they're in an IT block or not. 8226 unsigned Opc = Inst.getOpcode(); 8227 const MCInstrDesc &MCID = MII.get(Opc); 8228 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 8229 assert(MCID.hasOptionalDef() && 8230 "optionally flag setting instruction missing optional def operand"); 8231 assert(MCID.NumOperands == Inst.getNumOperands() && 8232 "operand count mismatch!"); 8233 // Find the optional-def operand (cc_out). 8234 unsigned OpNo; 8235 for (OpNo = 0; 8236 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 8237 ++OpNo) 8238 ; 8239 // If we're parsing Thumb1, reject it completely. 8240 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 8241 return Match_MnemonicFail; 8242 // If we're parsing Thumb2, which form is legal depends on whether we're 8243 // in an IT block. 8244 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 8245 !inITBlock()) 8246 return Match_RequiresITBlock; 8247 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 8248 inITBlock()) 8249 return Match_RequiresNotITBlock; 8250 } 8251 // Some high-register supporting Thumb1 encodings only allow both registers 8252 // to be from r0-r7 when in Thumb2. 8253 else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() && 8254 isARMLowRegister(Inst.getOperand(1).getReg()) && 8255 isARMLowRegister(Inst.getOperand(2).getReg())) 8256 return Match_RequiresThumb2; 8257 // Others only require ARMv6 or later. 8258 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 8259 isARMLowRegister(Inst.getOperand(0).getReg()) && 8260 isARMLowRegister(Inst.getOperand(1).getReg())) 8261 return Match_RequiresV6; 8262 return Match_Success; 8263 } 8264 8265 namespace llvm { 8266 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) { 8267 return true; // In an assembly source, no need to second-guess 8268 } 8269 } 8270 8271 static const char *getSubtargetFeatureName(uint64_t Val); 8272 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 8273 OperandVector &Operands, 8274 MCStreamer &Out, uint64_t &ErrorInfo, 8275 bool MatchingInlineAsm) { 8276 MCInst Inst; 8277 unsigned MatchResult; 8278 8279 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 8280 MatchingInlineAsm); 8281 switch (MatchResult) { 8282 default: break; 8283 case Match_Success: 8284 // Context sensitive operand constraints aren't handled by the matcher, 8285 // so check them here. 8286 if (validateInstruction(Inst, Operands)) { 8287 // Still progress the IT block, otherwise one wrong condition causes 8288 // nasty cascading errors. 8289 forwardITPosition(); 8290 return true; 8291 } 8292 8293 { // processInstruction() updates inITBlock state, we need to save it away 8294 bool wasInITBlock = inITBlock(); 8295 8296 // Some instructions need post-processing to, for example, tweak which 8297 // encoding is selected. Loop on it while changes happen so the 8298 // individual transformations can chain off each other. E.g., 8299 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 8300 while (processInstruction(Inst, Operands)) 8301 ; 8302 8303 // Only after the instruction is fully processed, we can validate it 8304 if (wasInITBlock && hasV8Ops() && isThumb() && 8305 !isV8EligibleForIT(&Inst)) { 8306 Warning(IDLoc, "deprecated instruction in IT block"); 8307 } 8308 } 8309 8310 // Only move forward at the very end so that everything in validate 8311 // and process gets a consistent answer about whether we're in an IT 8312 // block. 8313 forwardITPosition(); 8314 8315 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 8316 // doesn't actually encode. 8317 if (Inst.getOpcode() == ARM::ITasm) 8318 return false; 8319 8320 Inst.setLoc(IDLoc); 8321 Out.EmitInstruction(Inst, STI); 8322 return false; 8323 case Match_MissingFeature: { 8324 assert(ErrorInfo && "Unknown missing feature!"); 8325 // Special case the error message for the very common case where only 8326 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 8327 std::string Msg = "instruction requires:"; 8328 uint64_t Mask = 1; 8329 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 8330 if (ErrorInfo & Mask) { 8331 Msg += " "; 8332 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 8333 } 8334 Mask <<= 1; 8335 } 8336 return Error(IDLoc, Msg); 8337 } 8338 case Match_InvalidOperand: { 8339 SMLoc ErrorLoc = IDLoc; 8340 if (ErrorInfo != ~0ULL) { 8341 if (ErrorInfo >= Operands.size()) 8342 return Error(IDLoc, "too few operands for instruction"); 8343 8344 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); 8345 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8346 } 8347 8348 return Error(ErrorLoc, "invalid operand for instruction"); 8349 } 8350 case Match_MnemonicFail: 8351 return Error(IDLoc, "invalid instruction", 8352 ((ARMOperand &)*Operands[0]).getLocRange()); 8353 case Match_RequiresNotITBlock: 8354 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 8355 case Match_RequiresITBlock: 8356 return Error(IDLoc, "instruction only valid inside IT block"); 8357 case Match_RequiresV6: 8358 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 8359 case Match_RequiresThumb2: 8360 return Error(IDLoc, "instruction variant requires Thumb2"); 8361 case Match_ImmRange0_15: { 8362 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); 8363 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8364 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 8365 } 8366 case Match_ImmRange0_239: { 8367 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); 8368 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8369 return Error(ErrorLoc, "immediate operand must be in the range [0,239]"); 8370 } 8371 case Match_AlignedMemoryRequiresNone: 8372 case Match_DupAlignedMemoryRequiresNone: 8373 case Match_AlignedMemoryRequires16: 8374 case Match_DupAlignedMemoryRequires16: 8375 case Match_AlignedMemoryRequires32: 8376 case Match_DupAlignedMemoryRequires32: 8377 case Match_AlignedMemoryRequires64: 8378 case Match_DupAlignedMemoryRequires64: 8379 case Match_AlignedMemoryRequires64or128: 8380 case Match_DupAlignedMemoryRequires64or128: 8381 case Match_AlignedMemoryRequires64or128or256: 8382 { 8383 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc(); 8384 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 8385 switch (MatchResult) { 8386 default: 8387 llvm_unreachable("Missing Match_Aligned type"); 8388 case Match_AlignedMemoryRequiresNone: 8389 case Match_DupAlignedMemoryRequiresNone: 8390 return Error(ErrorLoc, "alignment must be omitted"); 8391 case Match_AlignedMemoryRequires16: 8392 case Match_DupAlignedMemoryRequires16: 8393 return Error(ErrorLoc, "alignment must be 16 or omitted"); 8394 case Match_AlignedMemoryRequires32: 8395 case Match_DupAlignedMemoryRequires32: 8396 return Error(ErrorLoc, "alignment must be 32 or omitted"); 8397 case Match_AlignedMemoryRequires64: 8398 case Match_DupAlignedMemoryRequires64: 8399 return Error(ErrorLoc, "alignment must be 64 or omitted"); 8400 case Match_AlignedMemoryRequires64or128: 8401 case Match_DupAlignedMemoryRequires64or128: 8402 return Error(ErrorLoc, "alignment must be 64, 128 or omitted"); 8403 case Match_AlignedMemoryRequires64or128or256: 8404 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted"); 8405 } 8406 } 8407 } 8408 8409 llvm_unreachable("Implement any new match types added!"); 8410 } 8411 8412 /// parseDirective parses the arm specific directives 8413 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 8414 const MCObjectFileInfo::Environment Format = 8415 getContext().getObjectFileInfo()->getObjectFileType(); 8416 bool IsMachO = Format == MCObjectFileInfo::IsMachO; 8417 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF; 8418 8419 StringRef IDVal = DirectiveID.getIdentifier(); 8420 if (IDVal == ".word") 8421 return parseLiteralValues(4, DirectiveID.getLoc()); 8422 else if (IDVal == ".short" || IDVal == ".hword") 8423 return parseLiteralValues(2, DirectiveID.getLoc()); 8424 else if (IDVal == ".thumb") 8425 return parseDirectiveThumb(DirectiveID.getLoc()); 8426 else if (IDVal == ".arm") 8427 return parseDirectiveARM(DirectiveID.getLoc()); 8428 else if (IDVal == ".thumb_func") 8429 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 8430 else if (IDVal == ".code") 8431 return parseDirectiveCode(DirectiveID.getLoc()); 8432 else if (IDVal == ".syntax") 8433 return parseDirectiveSyntax(DirectiveID.getLoc()); 8434 else if (IDVal == ".unreq") 8435 return parseDirectiveUnreq(DirectiveID.getLoc()); 8436 else if (IDVal == ".fnend") 8437 return parseDirectiveFnEnd(DirectiveID.getLoc()); 8438 else if (IDVal == ".cantunwind") 8439 return parseDirectiveCantUnwind(DirectiveID.getLoc()); 8440 else if (IDVal == ".personality") 8441 return parseDirectivePersonality(DirectiveID.getLoc()); 8442 else if (IDVal == ".handlerdata") 8443 return parseDirectiveHandlerData(DirectiveID.getLoc()); 8444 else if (IDVal == ".setfp") 8445 return parseDirectiveSetFP(DirectiveID.getLoc()); 8446 else if (IDVal == ".pad") 8447 return parseDirectivePad(DirectiveID.getLoc()); 8448 else if (IDVal == ".save") 8449 return parseDirectiveRegSave(DirectiveID.getLoc(), false); 8450 else if (IDVal == ".vsave") 8451 return parseDirectiveRegSave(DirectiveID.getLoc(), true); 8452 else if (IDVal == ".ltorg" || IDVal == ".pool") 8453 return parseDirectiveLtorg(DirectiveID.getLoc()); 8454 else if (IDVal == ".even") 8455 return parseDirectiveEven(DirectiveID.getLoc()); 8456 else if (IDVal == ".personalityindex") 8457 return parseDirectivePersonalityIndex(DirectiveID.getLoc()); 8458 else if (IDVal == ".unwind_raw") 8459 return parseDirectiveUnwindRaw(DirectiveID.getLoc()); 8460 else if (IDVal == ".movsp") 8461 return parseDirectiveMovSP(DirectiveID.getLoc()); 8462 else if (IDVal == ".arch_extension") 8463 return parseDirectiveArchExtension(DirectiveID.getLoc()); 8464 else if (IDVal == ".align") 8465 return parseDirectiveAlign(DirectiveID.getLoc()); 8466 else if (IDVal == ".thumb_set") 8467 return parseDirectiveThumbSet(DirectiveID.getLoc()); 8468 8469 if (!IsMachO && !IsCOFF) { 8470 if (IDVal == ".arch") 8471 return parseDirectiveArch(DirectiveID.getLoc()); 8472 else if (IDVal == ".cpu") 8473 return parseDirectiveCPU(DirectiveID.getLoc()); 8474 else if (IDVal == ".eabi_attribute") 8475 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 8476 else if (IDVal == ".fpu") 8477 return parseDirectiveFPU(DirectiveID.getLoc()); 8478 else if (IDVal == ".fnstart") 8479 return parseDirectiveFnStart(DirectiveID.getLoc()); 8480 else if (IDVal == ".inst") 8481 return parseDirectiveInst(DirectiveID.getLoc()); 8482 else if (IDVal == ".inst.n") 8483 return parseDirectiveInst(DirectiveID.getLoc(), 'n'); 8484 else if (IDVal == ".inst.w") 8485 return parseDirectiveInst(DirectiveID.getLoc(), 'w'); 8486 else if (IDVal == ".object_arch") 8487 return parseDirectiveObjectArch(DirectiveID.getLoc()); 8488 else if (IDVal == ".tlsdescseq") 8489 return parseDirectiveTLSDescSeq(DirectiveID.getLoc()); 8490 } 8491 8492 return true; 8493 } 8494 8495 /// parseLiteralValues 8496 /// ::= .hword expression [, expression]* 8497 /// ::= .short expression [, expression]* 8498 /// ::= .word expression [, expression]* 8499 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) { 8500 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8501 for (;;) { 8502 const MCExpr *Value; 8503 if (getParser().parseExpression(Value)) { 8504 Parser.eatToEndOfStatement(); 8505 return false; 8506 } 8507 8508 getParser().getStreamer().EmitValue(Value, Size); 8509 8510 if (getLexer().is(AsmToken::EndOfStatement)) 8511 break; 8512 8513 // FIXME: Improve diagnostic. 8514 if (getLexer().isNot(AsmToken::Comma)) { 8515 Error(L, "unexpected token in directive"); 8516 return false; 8517 } 8518 Parser.Lex(); 8519 } 8520 } 8521 8522 Parser.Lex(); 8523 return false; 8524 } 8525 8526 /// parseDirectiveThumb 8527 /// ::= .thumb 8528 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 8529 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8530 Error(L, "unexpected token in directive"); 8531 return false; 8532 } 8533 Parser.Lex(); 8534 8535 if (!hasThumb()) { 8536 Error(L, "target does not support Thumb mode"); 8537 return false; 8538 } 8539 8540 if (!isThumb()) 8541 SwitchMode(); 8542 8543 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 8544 return false; 8545 } 8546 8547 /// parseDirectiveARM 8548 /// ::= .arm 8549 bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 8550 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8551 Error(L, "unexpected token in directive"); 8552 return false; 8553 } 8554 Parser.Lex(); 8555 8556 if (!hasARM()) { 8557 Error(L, "target does not support ARM mode"); 8558 return false; 8559 } 8560 8561 if (isThumb()) 8562 SwitchMode(); 8563 8564 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 8565 return false; 8566 } 8567 8568 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) { 8569 if (NextSymbolIsThumb) { 8570 getParser().getStreamer().EmitThumbFunc(Symbol); 8571 NextSymbolIsThumb = false; 8572 } 8573 } 8574 8575 /// parseDirectiveThumbFunc 8576 /// ::= .thumbfunc symbol_name 8577 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 8578 const auto Format = getContext().getObjectFileInfo()->getObjectFileType(); 8579 bool IsMachO = Format == MCObjectFileInfo::IsMachO; 8580 8581 // Darwin asm has (optionally) function name after .thumb_func direction 8582 // ELF doesn't 8583 if (IsMachO) { 8584 const AsmToken &Tok = Parser.getTok(); 8585 if (Tok.isNot(AsmToken::EndOfStatement)) { 8586 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) { 8587 Error(L, "unexpected token in .thumb_func directive"); 8588 return false; 8589 } 8590 8591 MCSymbol *Func = 8592 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier()); 8593 getParser().getStreamer().EmitThumbFunc(Func); 8594 Parser.Lex(); // Consume the identifier token. 8595 return false; 8596 } 8597 } 8598 8599 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8600 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8601 Parser.eatToEndOfStatement(); 8602 return false; 8603 } 8604 8605 NextSymbolIsThumb = true; 8606 return false; 8607 } 8608 8609 /// parseDirectiveSyntax 8610 /// ::= .syntax unified | divided 8611 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 8612 const AsmToken &Tok = Parser.getTok(); 8613 if (Tok.isNot(AsmToken::Identifier)) { 8614 Error(L, "unexpected token in .syntax directive"); 8615 return false; 8616 } 8617 8618 StringRef Mode = Tok.getString(); 8619 if (Mode == "unified" || Mode == "UNIFIED") { 8620 Parser.Lex(); 8621 } else if (Mode == "divided" || Mode == "DIVIDED") { 8622 Error(L, "'.syntax divided' arm asssembly not supported"); 8623 return false; 8624 } else { 8625 Error(L, "unrecognized syntax mode in .syntax directive"); 8626 return false; 8627 } 8628 8629 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8630 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8631 return false; 8632 } 8633 Parser.Lex(); 8634 8635 // TODO tell the MC streamer the mode 8636 // getParser().getStreamer().Emit???(); 8637 return false; 8638 } 8639 8640 /// parseDirectiveCode 8641 /// ::= .code 16 | 32 8642 bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 8643 const AsmToken &Tok = Parser.getTok(); 8644 if (Tok.isNot(AsmToken::Integer)) { 8645 Error(L, "unexpected token in .code directive"); 8646 return false; 8647 } 8648 int64_t Val = Parser.getTok().getIntVal(); 8649 if (Val != 16 && Val != 32) { 8650 Error(L, "invalid operand to .code directive"); 8651 return false; 8652 } 8653 Parser.Lex(); 8654 8655 if (getLexer().isNot(AsmToken::EndOfStatement)) { 8656 Error(Parser.getTok().getLoc(), "unexpected token in directive"); 8657 return false; 8658 } 8659 Parser.Lex(); 8660 8661 if (Val == 16) { 8662 if (!hasThumb()) { 8663 Error(L, "target does not support Thumb mode"); 8664 return false; 8665 } 8666 8667 if (!isThumb()) 8668 SwitchMode(); 8669 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 8670 } else { 8671 if (!hasARM()) { 8672 Error(L, "target does not support ARM mode"); 8673 return false; 8674 } 8675 8676 if (isThumb()) 8677 SwitchMode(); 8678 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 8679 } 8680 8681 return false; 8682 } 8683 8684 /// parseDirectiveReq 8685 /// ::= name .req registername 8686 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 8687 Parser.Lex(); // Eat the '.req' token. 8688 unsigned Reg; 8689 SMLoc SRegLoc, ERegLoc; 8690 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 8691 Parser.eatToEndOfStatement(); 8692 Error(SRegLoc, "register name expected"); 8693 return false; 8694 } 8695 8696 // Shouldn't be anything else. 8697 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 8698 Parser.eatToEndOfStatement(); 8699 Error(Parser.getTok().getLoc(), "unexpected input in .req directive."); 8700 return false; 8701 } 8702 8703 Parser.Lex(); // Consume the EndOfStatement 8704 8705 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) { 8706 Error(SRegLoc, "redefinition of '" + Name + "' does not match original."); 8707 return false; 8708 } 8709 8710 return false; 8711 } 8712 8713 /// parseDirectiveUneq 8714 /// ::= .unreq registername 8715 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 8716 if (Parser.getTok().isNot(AsmToken::Identifier)) { 8717 Parser.eatToEndOfStatement(); 8718 Error(L, "unexpected input in .unreq directive."); 8719 return false; 8720 } 8721 RegisterReqs.erase(Parser.getTok().getIdentifier().lower()); 8722 Parser.Lex(); // Eat the identifier. 8723 return false; 8724 } 8725 8726 /// parseDirectiveArch 8727 /// ::= .arch token 8728 bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 8729 StringRef Arch = getParser().parseStringToEndOfStatement().trim(); 8730 8731 unsigned ID = StringSwitch<unsigned>(Arch) 8732 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \ 8733 .Case(NAME, ARM::ID) 8734 #define ARM_ARCH_ALIAS(NAME, ID) \ 8735 .Case(NAME, ARM::ID) 8736 #include "MCTargetDesc/ARMArchName.def" 8737 .Default(ARM::INVALID_ARCH); 8738 8739 if (ID == ARM::INVALID_ARCH) { 8740 Error(L, "Unknown arch name"); 8741 return false; 8742 } 8743 8744 getTargetStreamer().emitArch(ID); 8745 return false; 8746 } 8747 8748 /// parseDirectiveEabiAttr 8749 /// ::= .eabi_attribute int, int [, "str"] 8750 /// ::= .eabi_attribute Tag_name, int [, "str"] 8751 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 8752 int64_t Tag; 8753 SMLoc TagLoc; 8754 TagLoc = Parser.getTok().getLoc(); 8755 if (Parser.getTok().is(AsmToken::Identifier)) { 8756 StringRef Name = Parser.getTok().getIdentifier(); 8757 Tag = ARMBuildAttrs::AttrTypeFromString(Name); 8758 if (Tag == -1) { 8759 Error(TagLoc, "attribute name not recognised: " + Name); 8760 Parser.eatToEndOfStatement(); 8761 return false; 8762 } 8763 Parser.Lex(); 8764 } else { 8765 const MCExpr *AttrExpr; 8766 8767 TagLoc = Parser.getTok().getLoc(); 8768 if (Parser.parseExpression(AttrExpr)) { 8769 Parser.eatToEndOfStatement(); 8770 return false; 8771 } 8772 8773 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr); 8774 if (!CE) { 8775 Error(TagLoc, "expected numeric constant"); 8776 Parser.eatToEndOfStatement(); 8777 return false; 8778 } 8779 8780 Tag = CE->getValue(); 8781 } 8782 8783 if (Parser.getTok().isNot(AsmToken::Comma)) { 8784 Error(Parser.getTok().getLoc(), "comma expected"); 8785 Parser.eatToEndOfStatement(); 8786 return false; 8787 } 8788 Parser.Lex(); // skip comma 8789 8790 StringRef StringValue = ""; 8791 bool IsStringValue = false; 8792 8793 int64_t IntegerValue = 0; 8794 bool IsIntegerValue = false; 8795 8796 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name) 8797 IsStringValue = true; 8798 else if (Tag == ARMBuildAttrs::compatibility) { 8799 IsStringValue = true; 8800 IsIntegerValue = true; 8801 } else if (Tag < 32 || Tag % 2 == 0) 8802 IsIntegerValue = true; 8803 else if (Tag % 2 == 1) 8804 IsStringValue = true; 8805 else 8806 llvm_unreachable("invalid tag type"); 8807 8808 if (IsIntegerValue) { 8809 const MCExpr *ValueExpr; 8810 SMLoc ValueExprLoc = Parser.getTok().getLoc(); 8811 if (Parser.parseExpression(ValueExpr)) { 8812 Parser.eatToEndOfStatement(); 8813 return false; 8814 } 8815 8816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr); 8817 if (!CE) { 8818 Error(ValueExprLoc, "expected numeric constant"); 8819 Parser.eatToEndOfStatement(); 8820 return false; 8821 } 8822 8823 IntegerValue = CE->getValue(); 8824 } 8825 8826 if (Tag == ARMBuildAttrs::compatibility) { 8827 if (Parser.getTok().isNot(AsmToken::Comma)) 8828 IsStringValue = false; 8829 else 8830 Parser.Lex(); 8831 } 8832 8833 if (IsStringValue) { 8834 if (Parser.getTok().isNot(AsmToken::String)) { 8835 Error(Parser.getTok().getLoc(), "bad string constant"); 8836 Parser.eatToEndOfStatement(); 8837 return false; 8838 } 8839 8840 StringValue = Parser.getTok().getStringContents(); 8841 Parser.Lex(); 8842 } 8843 8844 if (IsIntegerValue && IsStringValue) { 8845 assert(Tag == ARMBuildAttrs::compatibility); 8846 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue); 8847 } else if (IsIntegerValue) 8848 getTargetStreamer().emitAttribute(Tag, IntegerValue); 8849 else if (IsStringValue) 8850 getTargetStreamer().emitTextAttribute(Tag, StringValue); 8851 return false; 8852 } 8853 8854 /// parseDirectiveCPU 8855 /// ::= .cpu str 8856 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) { 8857 StringRef CPU = getParser().parseStringToEndOfStatement().trim(); 8858 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU); 8859 return false; 8860 } 8861 8862 // FIXME: This is duplicated in getARMFPUFeatures() in 8863 // tools/clang/lib/Driver/Tools.cpp 8864 static const struct { 8865 const unsigned Fpu; 8866 const uint64_t Enabled; 8867 const uint64_t Disabled; 8868 } Fpus[] = { 8869 {ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON}, 8870 {ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON}, 8871 {ARM::VFPV3, ARM::FeatureVFP3, ARM::FeatureNEON}, 8872 {ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON}, 8873 {ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON}, 8874 {ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON}, 8875 {ARM::FPV5_D16, ARM::FeatureFPARMv8 | ARM::FeatureD16, 8876 ARM::FeatureNEON | ARM::FeatureCrypto}, 8877 {ARM::FP_ARMV8, ARM::FeatureFPARMv8, 8878 ARM::FeatureNEON | ARM::FeatureCrypto}, 8879 {ARM::NEON, ARM::FeatureNEON, 0}, 8880 {ARM::NEON_VFPV4, ARM::FeatureVFP4 | ARM::FeatureNEON, 0}, 8881 {ARM::NEON_FP_ARMV8, ARM::FeatureFPARMv8 | ARM::FeatureNEON, 8882 ARM::FeatureCrypto}, 8883 {ARM::CRYPTO_NEON_FP_ARMV8, 8884 ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, 0}, 8885 {ARM::SOFTVFP, 0, 0}, 8886 }; 8887 8888 /// parseDirectiveFPU 8889 /// ::= .fpu str 8890 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) { 8891 StringRef FPU = getParser().parseStringToEndOfStatement().trim(); 8892 8893 unsigned ID = StringSwitch<unsigned>(FPU) 8894 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID) 8895 #include "ARMFPUName.def" 8896 .Default(ARM::INVALID_FPU); 8897 8898 if (ID == ARM::INVALID_FPU) { 8899 Error(L, "Unknown FPU name"); 8900 return false; 8901 } 8902 8903 for (const auto &Fpu : Fpus) { 8904 if (Fpu.Fpu != ID) 8905 continue; 8906 8907 // Need to toggle features that should be on but are off and that 8908 // should off but are on. 8909 uint64_t Toggle = (Fpu.Enabled & ~STI.getFeatureBits()) | 8910 (Fpu.Disabled & STI.getFeatureBits()); 8911 setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle))); 8912 break; 8913 } 8914 8915 getTargetStreamer().emitFPU(ID); 8916 return false; 8917 } 8918 8919 /// parseDirectiveFnStart 8920 /// ::= .fnstart 8921 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) { 8922 if (UC.hasFnStart()) { 8923 Error(L, ".fnstart starts before the end of previous one"); 8924 UC.emitFnStartLocNotes(); 8925 return false; 8926 } 8927 8928 // Reset the unwind directives parser state 8929 UC.reset(); 8930 8931 getTargetStreamer().emitFnStart(); 8932 8933 UC.recordFnStart(L); 8934 return false; 8935 } 8936 8937 /// parseDirectiveFnEnd 8938 /// ::= .fnend 8939 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) { 8940 // Check the ordering of unwind directives 8941 if (!UC.hasFnStart()) { 8942 Error(L, ".fnstart must precede .fnend directive"); 8943 return false; 8944 } 8945 8946 // Reset the unwind directives parser state 8947 getTargetStreamer().emitFnEnd(); 8948 8949 UC.reset(); 8950 return false; 8951 } 8952 8953 /// parseDirectiveCantUnwind 8954 /// ::= .cantunwind 8955 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) { 8956 UC.recordCantUnwind(L); 8957 8958 // Check the ordering of unwind directives 8959 if (!UC.hasFnStart()) { 8960 Error(L, ".fnstart must precede .cantunwind directive"); 8961 return false; 8962 } 8963 if (UC.hasHandlerData()) { 8964 Error(L, ".cantunwind can't be used with .handlerdata directive"); 8965 UC.emitHandlerDataLocNotes(); 8966 return false; 8967 } 8968 if (UC.hasPersonality()) { 8969 Error(L, ".cantunwind can't be used with .personality directive"); 8970 UC.emitPersonalityLocNotes(); 8971 return false; 8972 } 8973 8974 getTargetStreamer().emitCantUnwind(); 8975 return false; 8976 } 8977 8978 /// parseDirectivePersonality 8979 /// ::= .personality name 8980 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) { 8981 bool HasExistingPersonality = UC.hasPersonality(); 8982 8983 UC.recordPersonality(L); 8984 8985 // Check the ordering of unwind directives 8986 if (!UC.hasFnStart()) { 8987 Error(L, ".fnstart must precede .personality directive"); 8988 return false; 8989 } 8990 if (UC.cantUnwind()) { 8991 Error(L, ".personality can't be used with .cantunwind directive"); 8992 UC.emitCantUnwindLocNotes(); 8993 return false; 8994 } 8995 if (UC.hasHandlerData()) { 8996 Error(L, ".personality must precede .handlerdata directive"); 8997 UC.emitHandlerDataLocNotes(); 8998 return false; 8999 } 9000 if (HasExistingPersonality) { 9001 Parser.eatToEndOfStatement(); 9002 Error(L, "multiple personality directives"); 9003 UC.emitPersonalityLocNotes(); 9004 return false; 9005 } 9006 9007 // Parse the name of the personality routine 9008 if (Parser.getTok().isNot(AsmToken::Identifier)) { 9009 Parser.eatToEndOfStatement(); 9010 Error(L, "unexpected input in .personality directive."); 9011 return false; 9012 } 9013 StringRef Name(Parser.getTok().getIdentifier()); 9014 Parser.Lex(); 9015 9016 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name); 9017 getTargetStreamer().emitPersonality(PR); 9018 return false; 9019 } 9020 9021 /// parseDirectiveHandlerData 9022 /// ::= .handlerdata 9023 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) { 9024 UC.recordHandlerData(L); 9025 9026 // Check the ordering of unwind directives 9027 if (!UC.hasFnStart()) { 9028 Error(L, ".fnstart must precede .personality directive"); 9029 return false; 9030 } 9031 if (UC.cantUnwind()) { 9032 Error(L, ".handlerdata can't be used with .cantunwind directive"); 9033 UC.emitCantUnwindLocNotes(); 9034 return false; 9035 } 9036 9037 getTargetStreamer().emitHandlerData(); 9038 return false; 9039 } 9040 9041 /// parseDirectiveSetFP 9042 /// ::= .setfp fpreg, spreg [, offset] 9043 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) { 9044 // Check the ordering of unwind directives 9045 if (!UC.hasFnStart()) { 9046 Error(L, ".fnstart must precede .setfp directive"); 9047 return false; 9048 } 9049 if (UC.hasHandlerData()) { 9050 Error(L, ".setfp must precede .handlerdata directive"); 9051 return false; 9052 } 9053 9054 // Parse fpreg 9055 SMLoc FPRegLoc = Parser.getTok().getLoc(); 9056 int FPReg = tryParseRegister(); 9057 if (FPReg == -1) { 9058 Error(FPRegLoc, "frame pointer register expected"); 9059 return false; 9060 } 9061 9062 // Consume comma 9063 if (Parser.getTok().isNot(AsmToken::Comma)) { 9064 Error(Parser.getTok().getLoc(), "comma expected"); 9065 return false; 9066 } 9067 Parser.Lex(); // skip comma 9068 9069 // Parse spreg 9070 SMLoc SPRegLoc = Parser.getTok().getLoc(); 9071 int SPReg = tryParseRegister(); 9072 if (SPReg == -1) { 9073 Error(SPRegLoc, "stack pointer register expected"); 9074 return false; 9075 } 9076 9077 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) { 9078 Error(SPRegLoc, "register should be either $sp or the latest fp register"); 9079 return false; 9080 } 9081 9082 // Update the frame pointer register 9083 UC.saveFPReg(FPReg); 9084 9085 // Parse offset 9086 int64_t Offset = 0; 9087 if (Parser.getTok().is(AsmToken::Comma)) { 9088 Parser.Lex(); // skip comma 9089 9090 if (Parser.getTok().isNot(AsmToken::Hash) && 9091 Parser.getTok().isNot(AsmToken::Dollar)) { 9092 Error(Parser.getTok().getLoc(), "'#' expected"); 9093 return false; 9094 } 9095 Parser.Lex(); // skip hash token. 9096 9097 const MCExpr *OffsetExpr; 9098 SMLoc ExLoc = Parser.getTok().getLoc(); 9099 SMLoc EndLoc; 9100 if (getParser().parseExpression(OffsetExpr, EndLoc)) { 9101 Error(ExLoc, "malformed setfp offset"); 9102 return false; 9103 } 9104 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9105 if (!CE) { 9106 Error(ExLoc, "setfp offset must be an immediate"); 9107 return false; 9108 } 9109 9110 Offset = CE->getValue(); 9111 } 9112 9113 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg), 9114 static_cast<unsigned>(SPReg), Offset); 9115 return false; 9116 } 9117 9118 /// parseDirective 9119 /// ::= .pad offset 9120 bool ARMAsmParser::parseDirectivePad(SMLoc L) { 9121 // Check the ordering of unwind directives 9122 if (!UC.hasFnStart()) { 9123 Error(L, ".fnstart must precede .pad directive"); 9124 return false; 9125 } 9126 if (UC.hasHandlerData()) { 9127 Error(L, ".pad must precede .handlerdata directive"); 9128 return false; 9129 } 9130 9131 // Parse the offset 9132 if (Parser.getTok().isNot(AsmToken::Hash) && 9133 Parser.getTok().isNot(AsmToken::Dollar)) { 9134 Error(Parser.getTok().getLoc(), "'#' expected"); 9135 return false; 9136 } 9137 Parser.Lex(); // skip hash token. 9138 9139 const MCExpr *OffsetExpr; 9140 SMLoc ExLoc = Parser.getTok().getLoc(); 9141 SMLoc EndLoc; 9142 if (getParser().parseExpression(OffsetExpr, EndLoc)) { 9143 Error(ExLoc, "malformed pad offset"); 9144 return false; 9145 } 9146 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9147 if (!CE) { 9148 Error(ExLoc, "pad offset must be an immediate"); 9149 return false; 9150 } 9151 9152 getTargetStreamer().emitPad(CE->getValue()); 9153 return false; 9154 } 9155 9156 /// parseDirectiveRegSave 9157 /// ::= .save { registers } 9158 /// ::= .vsave { registers } 9159 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { 9160 // Check the ordering of unwind directives 9161 if (!UC.hasFnStart()) { 9162 Error(L, ".fnstart must precede .save or .vsave directives"); 9163 return false; 9164 } 9165 if (UC.hasHandlerData()) { 9166 Error(L, ".save or .vsave must precede .handlerdata directive"); 9167 return false; 9168 } 9169 9170 // RAII object to make sure parsed operands are deleted. 9171 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; 9172 9173 // Parse the register list 9174 if (parseRegisterList(Operands)) 9175 return false; 9176 ARMOperand &Op = (ARMOperand &)*Operands[0]; 9177 if (!IsVector && !Op.isRegList()) { 9178 Error(L, ".save expects GPR registers"); 9179 return false; 9180 } 9181 if (IsVector && !Op.isDPRRegList()) { 9182 Error(L, ".vsave expects DPR registers"); 9183 return false; 9184 } 9185 9186 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector); 9187 return false; 9188 } 9189 9190 /// parseDirectiveInst 9191 /// ::= .inst opcode [, ...] 9192 /// ::= .inst.n opcode [, ...] 9193 /// ::= .inst.w opcode [, ...] 9194 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) { 9195 int Width; 9196 9197 if (isThumb()) { 9198 switch (Suffix) { 9199 case 'n': 9200 Width = 2; 9201 break; 9202 case 'w': 9203 Width = 4; 9204 break; 9205 default: 9206 Parser.eatToEndOfStatement(); 9207 Error(Loc, "cannot determine Thumb instruction size, " 9208 "use inst.n/inst.w instead"); 9209 return false; 9210 } 9211 } else { 9212 if (Suffix) { 9213 Parser.eatToEndOfStatement(); 9214 Error(Loc, "width suffixes are invalid in ARM mode"); 9215 return false; 9216 } 9217 Width = 4; 9218 } 9219 9220 if (getLexer().is(AsmToken::EndOfStatement)) { 9221 Parser.eatToEndOfStatement(); 9222 Error(Loc, "expected expression following directive"); 9223 return false; 9224 } 9225 9226 for (;;) { 9227 const MCExpr *Expr; 9228 9229 if (getParser().parseExpression(Expr)) { 9230 Error(Loc, "expected expression"); 9231 return false; 9232 } 9233 9234 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr); 9235 if (!Value) { 9236 Error(Loc, "expected constant expression"); 9237 return false; 9238 } 9239 9240 switch (Width) { 9241 case 2: 9242 if (Value->getValue() > 0xffff) { 9243 Error(Loc, "inst.n operand is too big, use inst.w instead"); 9244 return false; 9245 } 9246 break; 9247 case 4: 9248 if (Value->getValue() > 0xffffffff) { 9249 Error(Loc, 9250 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big"); 9251 return false; 9252 } 9253 break; 9254 default: 9255 llvm_unreachable("only supported widths are 2 and 4"); 9256 } 9257 9258 getTargetStreamer().emitInst(Value->getValue(), Suffix); 9259 9260 if (getLexer().is(AsmToken::EndOfStatement)) 9261 break; 9262 9263 if (getLexer().isNot(AsmToken::Comma)) { 9264 Error(Loc, "unexpected token in directive"); 9265 return false; 9266 } 9267 9268 Parser.Lex(); 9269 } 9270 9271 Parser.Lex(); 9272 return false; 9273 } 9274 9275 /// parseDirectiveLtorg 9276 /// ::= .ltorg | .pool 9277 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) { 9278 getTargetStreamer().emitCurrentConstantPool(); 9279 return false; 9280 } 9281 9282 bool ARMAsmParser::parseDirectiveEven(SMLoc L) { 9283 const MCSection *Section = getStreamer().getCurrentSection().first; 9284 9285 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9286 TokError("unexpected token in directive"); 9287 return false; 9288 } 9289 9290 if (!Section) { 9291 getStreamer().InitSections(false); 9292 Section = getStreamer().getCurrentSection().first; 9293 } 9294 9295 assert(Section && "must have section to emit alignment"); 9296 if (Section->UseCodeAlign()) 9297 getStreamer().EmitCodeAlignment(2); 9298 else 9299 getStreamer().EmitValueToAlignment(2); 9300 9301 return false; 9302 } 9303 9304 /// parseDirectivePersonalityIndex 9305 /// ::= .personalityindex index 9306 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) { 9307 bool HasExistingPersonality = UC.hasPersonality(); 9308 9309 UC.recordPersonalityIndex(L); 9310 9311 if (!UC.hasFnStart()) { 9312 Parser.eatToEndOfStatement(); 9313 Error(L, ".fnstart must precede .personalityindex directive"); 9314 return false; 9315 } 9316 if (UC.cantUnwind()) { 9317 Parser.eatToEndOfStatement(); 9318 Error(L, ".personalityindex cannot be used with .cantunwind"); 9319 UC.emitCantUnwindLocNotes(); 9320 return false; 9321 } 9322 if (UC.hasHandlerData()) { 9323 Parser.eatToEndOfStatement(); 9324 Error(L, ".personalityindex must precede .handlerdata directive"); 9325 UC.emitHandlerDataLocNotes(); 9326 return false; 9327 } 9328 if (HasExistingPersonality) { 9329 Parser.eatToEndOfStatement(); 9330 Error(L, "multiple personality directives"); 9331 UC.emitPersonalityLocNotes(); 9332 return false; 9333 } 9334 9335 const MCExpr *IndexExpression; 9336 SMLoc IndexLoc = Parser.getTok().getLoc(); 9337 if (Parser.parseExpression(IndexExpression)) { 9338 Parser.eatToEndOfStatement(); 9339 return false; 9340 } 9341 9342 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression); 9343 if (!CE) { 9344 Parser.eatToEndOfStatement(); 9345 Error(IndexLoc, "index must be a constant number"); 9346 return false; 9347 } 9348 if (CE->getValue() < 0 || 9349 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) { 9350 Parser.eatToEndOfStatement(); 9351 Error(IndexLoc, "personality routine index should be in range [0-3]"); 9352 return false; 9353 } 9354 9355 getTargetStreamer().emitPersonalityIndex(CE->getValue()); 9356 return false; 9357 } 9358 9359 /// parseDirectiveUnwindRaw 9360 /// ::= .unwind_raw offset, opcode [, opcode...] 9361 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) { 9362 if (!UC.hasFnStart()) { 9363 Parser.eatToEndOfStatement(); 9364 Error(L, ".fnstart must precede .unwind_raw directives"); 9365 return false; 9366 } 9367 9368 int64_t StackOffset; 9369 9370 const MCExpr *OffsetExpr; 9371 SMLoc OffsetLoc = getLexer().getLoc(); 9372 if (getLexer().is(AsmToken::EndOfStatement) || 9373 getParser().parseExpression(OffsetExpr)) { 9374 Error(OffsetLoc, "expected expression"); 9375 Parser.eatToEndOfStatement(); 9376 return false; 9377 } 9378 9379 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9380 if (!CE) { 9381 Error(OffsetLoc, "offset must be a constant"); 9382 Parser.eatToEndOfStatement(); 9383 return false; 9384 } 9385 9386 StackOffset = CE->getValue(); 9387 9388 if (getLexer().isNot(AsmToken::Comma)) { 9389 Error(getLexer().getLoc(), "expected comma"); 9390 Parser.eatToEndOfStatement(); 9391 return false; 9392 } 9393 Parser.Lex(); 9394 9395 SmallVector<uint8_t, 16> Opcodes; 9396 for (;;) { 9397 const MCExpr *OE; 9398 9399 SMLoc OpcodeLoc = getLexer().getLoc(); 9400 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) { 9401 Error(OpcodeLoc, "expected opcode expression"); 9402 Parser.eatToEndOfStatement(); 9403 return false; 9404 } 9405 9406 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE); 9407 if (!OC) { 9408 Error(OpcodeLoc, "opcode value must be a constant"); 9409 Parser.eatToEndOfStatement(); 9410 return false; 9411 } 9412 9413 const int64_t Opcode = OC->getValue(); 9414 if (Opcode & ~0xff) { 9415 Error(OpcodeLoc, "invalid opcode"); 9416 Parser.eatToEndOfStatement(); 9417 return false; 9418 } 9419 9420 Opcodes.push_back(uint8_t(Opcode)); 9421 9422 if (getLexer().is(AsmToken::EndOfStatement)) 9423 break; 9424 9425 if (getLexer().isNot(AsmToken::Comma)) { 9426 Error(getLexer().getLoc(), "unexpected token in directive"); 9427 Parser.eatToEndOfStatement(); 9428 return false; 9429 } 9430 9431 Parser.Lex(); 9432 } 9433 9434 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes); 9435 9436 Parser.Lex(); 9437 return false; 9438 } 9439 9440 /// parseDirectiveTLSDescSeq 9441 /// ::= .tlsdescseq tls-variable 9442 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) { 9443 if (getLexer().isNot(AsmToken::Identifier)) { 9444 TokError("expected variable after '.tlsdescseq' directive"); 9445 Parser.eatToEndOfStatement(); 9446 return false; 9447 } 9448 9449 const MCSymbolRefExpr *SRE = 9450 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(), 9451 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext()); 9452 Lex(); 9453 9454 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9455 Error(Parser.getTok().getLoc(), "unexpected token"); 9456 Parser.eatToEndOfStatement(); 9457 return false; 9458 } 9459 9460 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE); 9461 return false; 9462 } 9463 9464 /// parseDirectiveMovSP 9465 /// ::= .movsp reg [, #offset] 9466 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) { 9467 if (!UC.hasFnStart()) { 9468 Parser.eatToEndOfStatement(); 9469 Error(L, ".fnstart must precede .movsp directives"); 9470 return false; 9471 } 9472 if (UC.getFPReg() != ARM::SP) { 9473 Parser.eatToEndOfStatement(); 9474 Error(L, "unexpected .movsp directive"); 9475 return false; 9476 } 9477 9478 SMLoc SPRegLoc = Parser.getTok().getLoc(); 9479 int SPReg = tryParseRegister(); 9480 if (SPReg == -1) { 9481 Parser.eatToEndOfStatement(); 9482 Error(SPRegLoc, "register expected"); 9483 return false; 9484 } 9485 9486 if (SPReg == ARM::SP || SPReg == ARM::PC) { 9487 Parser.eatToEndOfStatement(); 9488 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive"); 9489 return false; 9490 } 9491 9492 int64_t Offset = 0; 9493 if (Parser.getTok().is(AsmToken::Comma)) { 9494 Parser.Lex(); 9495 9496 if (Parser.getTok().isNot(AsmToken::Hash)) { 9497 Error(Parser.getTok().getLoc(), "expected #constant"); 9498 Parser.eatToEndOfStatement(); 9499 return false; 9500 } 9501 Parser.Lex(); 9502 9503 const MCExpr *OffsetExpr; 9504 SMLoc OffsetLoc = Parser.getTok().getLoc(); 9505 if (Parser.parseExpression(OffsetExpr)) { 9506 Parser.eatToEndOfStatement(); 9507 Error(OffsetLoc, "malformed offset expression"); 9508 return false; 9509 } 9510 9511 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr); 9512 if (!CE) { 9513 Parser.eatToEndOfStatement(); 9514 Error(OffsetLoc, "offset must be an immediate constant"); 9515 return false; 9516 } 9517 9518 Offset = CE->getValue(); 9519 } 9520 9521 getTargetStreamer().emitMovSP(SPReg, Offset); 9522 UC.saveFPReg(SPReg); 9523 9524 return false; 9525 } 9526 9527 /// parseDirectiveObjectArch 9528 /// ::= .object_arch name 9529 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) { 9530 if (getLexer().isNot(AsmToken::Identifier)) { 9531 Error(getLexer().getLoc(), "unexpected token"); 9532 Parser.eatToEndOfStatement(); 9533 return false; 9534 } 9535 9536 StringRef Arch = Parser.getTok().getString(); 9537 SMLoc ArchLoc = Parser.getTok().getLoc(); 9538 getLexer().Lex(); 9539 9540 unsigned ID = StringSwitch<unsigned>(Arch) 9541 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \ 9542 .Case(NAME, ARM::ID) 9543 #define ARM_ARCH_ALIAS(NAME, ID) \ 9544 .Case(NAME, ARM::ID) 9545 #include "MCTargetDesc/ARMArchName.def" 9546 #undef ARM_ARCH_NAME 9547 #undef ARM_ARCH_ALIAS 9548 .Default(ARM::INVALID_ARCH); 9549 9550 if (ID == ARM::INVALID_ARCH) { 9551 Error(ArchLoc, "unknown architecture '" + Arch + "'"); 9552 Parser.eatToEndOfStatement(); 9553 return false; 9554 } 9555 9556 getTargetStreamer().emitObjectArch(ID); 9557 9558 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9559 Error(getLexer().getLoc(), "unexpected token"); 9560 Parser.eatToEndOfStatement(); 9561 } 9562 9563 return false; 9564 } 9565 9566 /// parseDirectiveAlign 9567 /// ::= .align 9568 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) { 9569 // NOTE: if this is not the end of the statement, fall back to the target 9570 // agnostic handling for this directive which will correctly handle this. 9571 if (getLexer().isNot(AsmToken::EndOfStatement)) 9572 return true; 9573 9574 // '.align' is target specifically handled to mean 2**2 byte alignment. 9575 if (getStreamer().getCurrentSection().first->UseCodeAlign()) 9576 getStreamer().EmitCodeAlignment(4, 0); 9577 else 9578 getStreamer().EmitValueToAlignment(4, 0, 1, 0); 9579 9580 return false; 9581 } 9582 9583 /// parseDirectiveThumbSet 9584 /// ::= .thumb_set name, value 9585 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) { 9586 StringRef Name; 9587 if (Parser.parseIdentifier(Name)) { 9588 TokError("expected identifier after '.thumb_set'"); 9589 Parser.eatToEndOfStatement(); 9590 return false; 9591 } 9592 9593 if (getLexer().isNot(AsmToken::Comma)) { 9594 TokError("expected comma after name '" + Name + "'"); 9595 Parser.eatToEndOfStatement(); 9596 return false; 9597 } 9598 Lex(); 9599 9600 const MCExpr *Value; 9601 if (Parser.parseExpression(Value)) { 9602 TokError("missing expression"); 9603 Parser.eatToEndOfStatement(); 9604 return false; 9605 } 9606 9607 if (getLexer().isNot(AsmToken::EndOfStatement)) { 9608 TokError("unexpected token"); 9609 Parser.eatToEndOfStatement(); 9610 return false; 9611 } 9612 Lex(); 9613 9614 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name); 9615 getTargetStreamer().emitThumbSet(Alias, Value); 9616 return false; 9617 } 9618 9619 /// Force static initialization. 9620 extern "C" void LLVMInitializeARMAsmParser() { 9621 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget); 9622 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget); 9623 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget); 9624 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget); 9625 } 9626 9627 #define GET_REGISTER_MATCHER 9628 #define GET_SUBTARGET_FEATURE_NAME 9629 #define GET_MATCHER_IMPLEMENTATION 9630 #include "ARMGenAsmMatcher.inc" 9631 9632 static const struct { 9633 const char *Name; 9634 const unsigned ArchCheck; 9635 const uint64_t Features; 9636 } Extensions[] = { 9637 { "crc", Feature_HasV8, ARM::FeatureCRC }, 9638 { "crypto", Feature_HasV8, 9639 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 }, 9640 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 }, 9641 { "idiv", Feature_HasV7 | Feature_IsNotMClass, 9642 ARM::FeatureHWDiv | ARM::FeatureHWDivARM }, 9643 // FIXME: iWMMXT not supported 9644 { "iwmmxt", Feature_None, 0 }, 9645 // FIXME: iWMMXT2 not supported 9646 { "iwmmxt2", Feature_None, 0 }, 9647 // FIXME: Maverick not supported 9648 { "maverick", Feature_None, 0 }, 9649 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP }, 9650 // FIXME: ARMv6-m OS Extensions feature not checked 9651 { "os", Feature_None, 0 }, 9652 // FIXME: Also available in ARMv6-K 9653 { "sec", Feature_HasV7, ARM::FeatureTrustZone }, 9654 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 }, 9655 // FIXME: Only available in A-class, isel not predicated 9656 { "virt", Feature_HasV7, ARM::FeatureVirtualization }, 9657 // FIXME: xscale not supported 9658 { "xscale", Feature_None, 0 }, 9659 }; 9660 9661 /// parseDirectiveArchExtension 9662 /// ::= .arch_extension [no]feature 9663 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) { 9664 if (getLexer().isNot(AsmToken::Identifier)) { 9665 Error(getLexer().getLoc(), "unexpected token"); 9666 Parser.eatToEndOfStatement(); 9667 return false; 9668 } 9669 9670 StringRef Name = Parser.getTok().getString(); 9671 SMLoc ExtLoc = Parser.getTok().getLoc(); 9672 getLexer().Lex(); 9673 9674 bool EnableFeature = true; 9675 if (Name.startswith_lower("no")) { 9676 EnableFeature = false; 9677 Name = Name.substr(2); 9678 } 9679 9680 for (const auto &Extension : Extensions) { 9681 if (Extension.Name != Name) 9682 continue; 9683 9684 if (!Extension.Features) 9685 report_fatal_error("unsupported architectural extension: " + Name); 9686 9687 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) { 9688 Error(ExtLoc, "architectural extension '" + Name + "' is not " 9689 "allowed for the current base architecture"); 9690 return false; 9691 } 9692 9693 uint64_t ToggleFeatures = EnableFeature 9694 ? (~STI.getFeatureBits() & Extension.Features) 9695 : ( STI.getFeatureBits() & Extension.Features); 9696 uint64_t Features = 9697 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures)); 9698 setAvailableFeatures(Features); 9699 return false; 9700 } 9701 9702 Error(ExtLoc, "unknown architectural extension: " + Name); 9703 Parser.eatToEndOfStatement(); 9704 return false; 9705 } 9706 9707 // Define this matcher function after the auto-generated include so we 9708 // have the match class enum definitions. 9709 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 9710 unsigned Kind) { 9711 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp); 9712 // If the kind is a token for a literal immediate, check if our asm 9713 // operand matches. This is for InstAliases which have a fixed-value 9714 // immediate in the syntax. 9715 switch (Kind) { 9716 default: break; 9717 case MCK__35_0: 9718 if (Op.isImm()) 9719 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm())) 9720 if (CE->getValue() == 0) 9721 return Match_Success; 9722 break; 9723 case MCK_ARMSOImm: 9724 if (Op.isImm()) { 9725 const MCExpr *SOExpr = Op.getImm(); 9726 int64_t Value; 9727 if (!SOExpr->EvaluateAsAbsolute(Value)) 9728 return Match_Success; 9729 assert((Value >= INT32_MIN && Value <= UINT32_MAX) && 9730 "expression value must be representable in 32 bits"); 9731 } 9732 break; 9733 case MCK_GPRPair: 9734 if (Op.isReg() && 9735 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg())) 9736 return Match_Success; 9737 break; 9738 } 9739 return Match_InvalidOperand; 9740 } 9741