1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELF.h"
26 #include "llvm/MC/MCELFStreamer.h"
27 #include "llvm/MC/MCELFSymbolFlags.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCObjectFileInfo.h"
33 #include "llvm/MC/MCParser/MCAsmLexer.h"
34 #include "llvm/MC/MCParser/MCAsmParser.h"
35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/MC/MCSection.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSubtargetInfo.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/MC/MCTargetAsmParser.h"
42 #include "llvm/Support/ARMBuildAttributes.h"
43 #include "llvm/Support/ARMEHABI.h"
44 #include "llvm/Support/COFF.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ELF.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/SourceMgr.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
51 
52 using namespace llvm;
53 
54 namespace {
55 
56 class ARMOperand;
57 
58 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
59 
60 class UnwindContext {
61   MCAsmParser &Parser;
62 
63   typedef SmallVector<SMLoc, 4> Locs;
64 
65   Locs FnStartLocs;
66   Locs CantUnwindLocs;
67   Locs PersonalityLocs;
68   Locs PersonalityIndexLocs;
69   Locs HandlerDataLocs;
70   int FPReg;
71 
72 public:
73   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
74 
75   bool hasFnStart() const { return !FnStartLocs.empty(); }
76   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
77   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
78   bool hasPersonality() const {
79     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
80   }
81 
82   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
83   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
84   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
85   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
86   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
87 
88   void saveFPReg(int Reg) { FPReg = Reg; }
89   int getFPReg() const { return FPReg; }
90 
91   void emitFnStartLocNotes() const {
92     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
93          FI != FE; ++FI)
94       Parser.Note(*FI, ".fnstart was specified here");
95   }
96   void emitCantUnwindLocNotes() const {
97     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
98                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
99       Parser.Note(*UI, ".cantunwind was specified here");
100   }
101   void emitHandlerDataLocNotes() const {
102     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
103                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
104       Parser.Note(*HI, ".handlerdata was specified here");
105   }
106   void emitPersonalityLocNotes() const {
107     for (Locs::const_iterator PI = PersonalityLocs.begin(),
108                               PE = PersonalityLocs.end(),
109                               PII = PersonalityIndexLocs.begin(),
110                               PIE = PersonalityIndexLocs.end();
111          PI != PE || PII != PIE;) {
112       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
113         Parser.Note(*PI++, ".personality was specified here");
114       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
115         Parser.Note(*PII++, ".personalityindex was specified here");
116       else
117         llvm_unreachable(".personality and .personalityindex cannot be "
118                          "at the same location");
119     }
120   }
121 
122   void reset() {
123     FnStartLocs = Locs();
124     CantUnwindLocs = Locs();
125     PersonalityLocs = Locs();
126     HandlerDataLocs = Locs();
127     PersonalityIndexLocs = Locs();
128     FPReg = ARM::SP;
129   }
130 };
131 
132 class ARMAsmParser : public MCTargetAsmParser {
133   MCSubtargetInfo &STI;
134   MCAsmParser &Parser;
135   const MCInstrInfo &MII;
136   const MCRegisterInfo *MRI;
137   UnwindContext UC;
138 
139   ARMTargetStreamer &getTargetStreamer() {
140     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
141     return static_cast<ARMTargetStreamer &>(TS);
142   }
143 
144   // Map of register aliases registers via the .req directive.
145   StringMap<unsigned> RegisterReqs;
146 
147   bool NextSymbolIsThumb;
148 
149   struct {
150     ARMCC::CondCodes Cond;    // Condition for IT block.
151     unsigned Mask:4;          // Condition mask for instructions.
152                               // Starting at first 1 (from lsb).
153                               //   '1'  condition as indicated in IT.
154                               //   '0'  inverse of condition (else).
155                               // Count of instructions in IT block is
156                               // 4 - trailingzeroes(mask)
157 
158     bool FirstCond;           // Explicit flag for when we're parsing the
159                               // First instruction in the IT block. It's
160                               // implied in the mask, so needs special
161                               // handling.
162 
163     unsigned CurPosition;     // Current position in parsing of IT
164                               // block. In range [0,3]. Initialized
165                               // according to count of instructions in block.
166                               // ~0U if no active IT block.
167   } ITState;
168   bool inITBlock() { return ITState.CurPosition != ~0U;}
169   void forwardITPosition() {
170     if (!inITBlock()) return;
171     // Move to the next instruction in the IT block, if there is one. If not,
172     // mark the block as done.
173     unsigned TZ = countTrailingZeros(ITState.Mask);
174     if (++ITState.CurPosition == 5 - TZ)
175       ITState.CurPosition = ~0U; // Done with the IT block after this.
176   }
177 
178 
179   MCAsmParser &getParser() const { return Parser; }
180   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
181 
182   void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
183     return Parser.Note(L, Msg, Ranges);
184   }
185   bool Warning(SMLoc L, const Twine &Msg,
186                ArrayRef<SMRange> Ranges = None) {
187     return Parser.Warning(L, Msg, Ranges);
188   }
189   bool Error(SMLoc L, const Twine &Msg,
190              ArrayRef<SMRange> Ranges = None) {
191     return Parser.Error(L, Msg, Ranges);
192   }
193 
194   int tryParseRegister();
195   bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
196   int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
197   bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
198   bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
199   bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
200   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
201   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
202                               unsigned &ShiftAmount);
203   bool parseLiteralValues(unsigned Size, SMLoc L);
204   bool parseDirectiveThumb(SMLoc L);
205   bool parseDirectiveARM(SMLoc L);
206   bool parseDirectiveThumbFunc(SMLoc L);
207   bool parseDirectiveCode(SMLoc L);
208   bool parseDirectiveSyntax(SMLoc L);
209   bool parseDirectiveReq(StringRef Name, SMLoc L);
210   bool parseDirectiveUnreq(SMLoc L);
211   bool parseDirectiveArch(SMLoc L);
212   bool parseDirectiveEabiAttr(SMLoc L);
213   bool parseDirectiveCPU(SMLoc L);
214   bool parseDirectiveFPU(SMLoc L);
215   bool parseDirectiveFnStart(SMLoc L);
216   bool parseDirectiveFnEnd(SMLoc L);
217   bool parseDirectiveCantUnwind(SMLoc L);
218   bool parseDirectivePersonality(SMLoc L);
219   bool parseDirectiveHandlerData(SMLoc L);
220   bool parseDirectiveSetFP(SMLoc L);
221   bool parseDirectivePad(SMLoc L);
222   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
223   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
224   bool parseDirectiveLtorg(SMLoc L);
225   bool parseDirectiveEven(SMLoc L);
226   bool parseDirectivePersonalityIndex(SMLoc L);
227   bool parseDirectiveUnwindRaw(SMLoc L);
228   bool parseDirectiveTLSDescSeq(SMLoc L);
229   bool parseDirectiveMovSP(SMLoc L);
230   bool parseDirectiveObjectArch(SMLoc L);
231   bool parseDirectiveArchExtension(SMLoc L);
232   bool parseDirectiveAlign(SMLoc L);
233   bool parseDirectiveThumbSet(SMLoc L);
234 
235   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
236                           bool &CarrySetting, unsigned &ProcessorIMod,
237                           StringRef &ITMask);
238   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
239                              bool &CanAcceptCarrySet,
240                              bool &CanAcceptPredicationCode);
241 
242   bool isThumb() const {
243     // FIXME: Can tablegen auto-generate this?
244     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
245   }
246   bool isThumbOne() const {
247     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
248   }
249   bool isThumbTwo() const {
250     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
251   }
252   bool hasThumb() const {
253     return STI.getFeatureBits() & ARM::HasV4TOps;
254   }
255   bool hasV6Ops() const {
256     return STI.getFeatureBits() & ARM::HasV6Ops;
257   }
258   bool hasV6MOps() const {
259     return STI.getFeatureBits() & ARM::HasV6MOps;
260   }
261   bool hasV7Ops() const {
262     return STI.getFeatureBits() & ARM::HasV7Ops;
263   }
264   bool hasV8Ops() const {
265     return STI.getFeatureBits() & ARM::HasV8Ops;
266   }
267   bool hasARM() const {
268     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
269   }
270 
271   void SwitchMode() {
272     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
273     setAvailableFeatures(FB);
274   }
275   bool isMClass() const {
276     return STI.getFeatureBits() & ARM::FeatureMClass;
277   }
278 
279   /// @name Auto-generated Match Functions
280   /// {
281 
282 #define GET_ASSEMBLER_HEADER
283 #include "ARMGenAsmMatcher.inc"
284 
285   /// }
286 
287   OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
288   OperandMatchResultTy parseCoprocNumOperand(
289     SmallVectorImpl<MCParsedAsmOperand*>&);
290   OperandMatchResultTy parseCoprocRegOperand(
291     SmallVectorImpl<MCParsedAsmOperand*>&);
292   OperandMatchResultTy parseCoprocOptionOperand(
293     SmallVectorImpl<MCParsedAsmOperand*>&);
294   OperandMatchResultTy parseMemBarrierOptOperand(
295     SmallVectorImpl<MCParsedAsmOperand*>&);
296   OperandMatchResultTy parseInstSyncBarrierOptOperand(
297     SmallVectorImpl<MCParsedAsmOperand*>&);
298   OperandMatchResultTy parseProcIFlagsOperand(
299     SmallVectorImpl<MCParsedAsmOperand*>&);
300   OperandMatchResultTy parseMSRMaskOperand(
301     SmallVectorImpl<MCParsedAsmOperand*>&);
302   OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
303                                    StringRef Op, int Low, int High);
304   OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
305     return parsePKHImm(O, "lsl", 0, 31);
306   }
307   OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
308     return parsePKHImm(O, "asr", 1, 32);
309   }
310   OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
311   OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
312   OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
313   OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
314   OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
315   OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
316   OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
317   OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
318   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
319                                        SMLoc &EndLoc);
320 
321   // Asm Match Converter Methods
322   void cvtThumbMultiply(MCInst &Inst,
323                         const SmallVectorImpl<MCParsedAsmOperand*> &);
324   void cvtThumbBranches(MCInst &Inst,
325                         const SmallVectorImpl<MCParsedAsmOperand*> &);
326 
327   bool validateInstruction(MCInst &Inst,
328                            const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
329   bool processInstruction(MCInst &Inst,
330                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
331   bool shouldOmitCCOutOperand(StringRef Mnemonic,
332                               SmallVectorImpl<MCParsedAsmOperand*> &Operands);
333   bool shouldOmitPredicateOperand(StringRef Mnemonic,
334                               SmallVectorImpl<MCParsedAsmOperand*> &Operands);
335 public:
336   enum ARMMatchResultTy {
337     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
338     Match_RequiresNotITBlock,
339     Match_RequiresV6,
340     Match_RequiresThumb2,
341 #define GET_OPERAND_DIAGNOSTIC_TYPES
342 #include "ARMGenAsmMatcher.inc"
343 
344   };
345 
346   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
347                const MCInstrInfo &MII,
348                const MCTargetOptions &Options)
349       : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
350     MCAsmParserExtension::Initialize(_Parser);
351 
352     // Cache the MCRegisterInfo.
353     MRI = getContext().getRegisterInfo();
354 
355     // Initialize the set of available features.
356     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
357 
358     // Not in an ITBlock to start with.
359     ITState.CurPosition = ~0U;
360 
361     NextSymbolIsThumb = false;
362   }
363 
364   // Implementation of the MCTargetAsmParser interface:
365   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
366   bool
367   ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
368                    SMLoc NameLoc,
369                    SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
370   bool ParseDirective(AsmToken DirectiveID) override;
371 
372   unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
373                                       unsigned Kind) override;
374   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
375 
376   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
377                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
378                                MCStreamer &Out, unsigned &ErrorInfo,
379                                bool MatchingInlineAsm) override;
380   void onLabelParsed(MCSymbol *Symbol) override;
381 };
382 } // end anonymous namespace
383 
384 namespace {
385 
386 /// ARMOperand - Instances of this class represent a parsed ARM machine
387 /// operand.
388 class ARMOperand : public MCParsedAsmOperand {
389   enum KindTy {
390     k_CondCode,
391     k_CCOut,
392     k_ITCondMask,
393     k_CoprocNum,
394     k_CoprocReg,
395     k_CoprocOption,
396     k_Immediate,
397     k_MemBarrierOpt,
398     k_InstSyncBarrierOpt,
399     k_Memory,
400     k_PostIndexRegister,
401     k_MSRMask,
402     k_ProcIFlags,
403     k_VectorIndex,
404     k_Register,
405     k_RegisterList,
406     k_DPRRegisterList,
407     k_SPRRegisterList,
408     k_VectorList,
409     k_VectorListAllLanes,
410     k_VectorListIndexed,
411     k_ShiftedRegister,
412     k_ShiftedImmediate,
413     k_ShifterImmediate,
414     k_RotateImmediate,
415     k_BitfieldDescriptor,
416     k_Token
417   } Kind;
418 
419   SMLoc StartLoc, EndLoc, AlignmentLoc;
420   SmallVector<unsigned, 8> Registers;
421 
422   struct CCOp {
423     ARMCC::CondCodes Val;
424   };
425 
426   struct CopOp {
427     unsigned Val;
428   };
429 
430   struct CoprocOptionOp {
431     unsigned Val;
432   };
433 
434   struct ITMaskOp {
435     unsigned Mask:4;
436   };
437 
438   struct MBOptOp {
439     ARM_MB::MemBOpt Val;
440   };
441 
442   struct ISBOptOp {
443     ARM_ISB::InstSyncBOpt Val;
444   };
445 
446   struct IFlagsOp {
447     ARM_PROC::IFlags Val;
448   };
449 
450   struct MMaskOp {
451     unsigned Val;
452   };
453 
454   struct TokOp {
455     const char *Data;
456     unsigned Length;
457   };
458 
459   struct RegOp {
460     unsigned RegNum;
461   };
462 
463   // A vector register list is a sequential list of 1 to 4 registers.
464   struct VectorListOp {
465     unsigned RegNum;
466     unsigned Count;
467     unsigned LaneIndex;
468     bool isDoubleSpaced;
469   };
470 
471   struct VectorIndexOp {
472     unsigned Val;
473   };
474 
475   struct ImmOp {
476     const MCExpr *Val;
477   };
478 
479   /// Combined record for all forms of ARM address expressions.
480   struct MemoryOp {
481     unsigned BaseRegNum;
482     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
483     // was specified.
484     const MCConstantExpr *OffsetImm;  // Offset immediate value
485     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
486     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
487     unsigned ShiftImm;        // shift for OffsetReg.
488     unsigned Alignment;       // 0 = no alignment specified
489     // n = alignment in bytes (2, 4, 8, 16, or 32)
490     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
491   };
492 
493   struct PostIdxRegOp {
494     unsigned RegNum;
495     bool isAdd;
496     ARM_AM::ShiftOpc ShiftTy;
497     unsigned ShiftImm;
498   };
499 
500   struct ShifterImmOp {
501     bool isASR;
502     unsigned Imm;
503   };
504 
505   struct RegShiftedRegOp {
506     ARM_AM::ShiftOpc ShiftTy;
507     unsigned SrcReg;
508     unsigned ShiftReg;
509     unsigned ShiftImm;
510   };
511 
512   struct RegShiftedImmOp {
513     ARM_AM::ShiftOpc ShiftTy;
514     unsigned SrcReg;
515     unsigned ShiftImm;
516   };
517 
518   struct RotImmOp {
519     unsigned Imm;
520   };
521 
522   struct BitfieldOp {
523     unsigned LSB;
524     unsigned Width;
525   };
526 
527   union {
528     struct CCOp CC;
529     struct CopOp Cop;
530     struct CoprocOptionOp CoprocOption;
531     struct MBOptOp MBOpt;
532     struct ISBOptOp ISBOpt;
533     struct ITMaskOp ITMask;
534     struct IFlagsOp IFlags;
535     struct MMaskOp MMask;
536     struct TokOp Tok;
537     struct RegOp Reg;
538     struct VectorListOp VectorList;
539     struct VectorIndexOp VectorIndex;
540     struct ImmOp Imm;
541     struct MemoryOp Memory;
542     struct PostIdxRegOp PostIdxReg;
543     struct ShifterImmOp ShifterImm;
544     struct RegShiftedRegOp RegShiftedReg;
545     struct RegShiftedImmOp RegShiftedImm;
546     struct RotImmOp RotImm;
547     struct BitfieldOp Bitfield;
548   };
549 
550   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
551 public:
552   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
553     Kind = o.Kind;
554     StartLoc = o.StartLoc;
555     EndLoc = o.EndLoc;
556     switch (Kind) {
557     case k_CondCode:
558       CC = o.CC;
559       break;
560     case k_ITCondMask:
561       ITMask = o.ITMask;
562       break;
563     case k_Token:
564       Tok = o.Tok;
565       break;
566     case k_CCOut:
567     case k_Register:
568       Reg = o.Reg;
569       break;
570     case k_RegisterList:
571     case k_DPRRegisterList:
572     case k_SPRRegisterList:
573       Registers = o.Registers;
574       break;
575     case k_VectorList:
576     case k_VectorListAllLanes:
577     case k_VectorListIndexed:
578       VectorList = o.VectorList;
579       break;
580     case k_CoprocNum:
581     case k_CoprocReg:
582       Cop = o.Cop;
583       break;
584     case k_CoprocOption:
585       CoprocOption = o.CoprocOption;
586       break;
587     case k_Immediate:
588       Imm = o.Imm;
589       break;
590     case k_MemBarrierOpt:
591       MBOpt = o.MBOpt;
592       break;
593     case k_InstSyncBarrierOpt:
594       ISBOpt = o.ISBOpt;
595     case k_Memory:
596       Memory = o.Memory;
597       break;
598     case k_PostIndexRegister:
599       PostIdxReg = o.PostIdxReg;
600       break;
601     case k_MSRMask:
602       MMask = o.MMask;
603       break;
604     case k_ProcIFlags:
605       IFlags = o.IFlags;
606       break;
607     case k_ShifterImmediate:
608       ShifterImm = o.ShifterImm;
609       break;
610     case k_ShiftedRegister:
611       RegShiftedReg = o.RegShiftedReg;
612       break;
613     case k_ShiftedImmediate:
614       RegShiftedImm = o.RegShiftedImm;
615       break;
616     case k_RotateImmediate:
617       RotImm = o.RotImm;
618       break;
619     case k_BitfieldDescriptor:
620       Bitfield = o.Bitfield;
621       break;
622     case k_VectorIndex:
623       VectorIndex = o.VectorIndex;
624       break;
625     }
626   }
627 
628   /// getStartLoc - Get the location of the first token of this operand.
629   SMLoc getStartLoc() const override { return StartLoc; }
630   /// getEndLoc - Get the location of the last token of this operand.
631   SMLoc getEndLoc() const override { return EndLoc; }
632   /// getLocRange - Get the range between the first and last token of this
633   /// operand.
634   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
635 
636   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
637   SMLoc getAlignmentLoc() const {
638     assert(Kind == k_Memory && "Invalid access!");
639     return AlignmentLoc;
640   }
641 
642   ARMCC::CondCodes getCondCode() const {
643     assert(Kind == k_CondCode && "Invalid access!");
644     return CC.Val;
645   }
646 
647   unsigned getCoproc() const {
648     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
649     return Cop.Val;
650   }
651 
652   StringRef getToken() const {
653     assert(Kind == k_Token && "Invalid access!");
654     return StringRef(Tok.Data, Tok.Length);
655   }
656 
657   unsigned getReg() const override {
658     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
659     return Reg.RegNum;
660   }
661 
662   const SmallVectorImpl<unsigned> &getRegList() const {
663     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
664             Kind == k_SPRRegisterList) && "Invalid access!");
665     return Registers;
666   }
667 
668   const MCExpr *getImm() const {
669     assert(isImm() && "Invalid access!");
670     return Imm.Val;
671   }
672 
673   unsigned getVectorIndex() const {
674     assert(Kind == k_VectorIndex && "Invalid access!");
675     return VectorIndex.Val;
676   }
677 
678   ARM_MB::MemBOpt getMemBarrierOpt() const {
679     assert(Kind == k_MemBarrierOpt && "Invalid access!");
680     return MBOpt.Val;
681   }
682 
683   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
684     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
685     return ISBOpt.Val;
686   }
687 
688   ARM_PROC::IFlags getProcIFlags() const {
689     assert(Kind == k_ProcIFlags && "Invalid access!");
690     return IFlags.Val;
691   }
692 
693   unsigned getMSRMask() const {
694     assert(Kind == k_MSRMask && "Invalid access!");
695     return MMask.Val;
696   }
697 
698   bool isCoprocNum() const { return Kind == k_CoprocNum; }
699   bool isCoprocReg() const { return Kind == k_CoprocReg; }
700   bool isCoprocOption() const { return Kind == k_CoprocOption; }
701   bool isCondCode() const { return Kind == k_CondCode; }
702   bool isCCOut() const { return Kind == k_CCOut; }
703   bool isITMask() const { return Kind == k_ITCondMask; }
704   bool isITCondCode() const { return Kind == k_CondCode; }
705   bool isImm() const override { return Kind == k_Immediate; }
706   // checks whether this operand is an unsigned offset which fits is a field
707   // of specified width and scaled by a specific number of bits
708   template<unsigned width, unsigned scale>
709   bool isUnsignedOffset() const {
710     if (!isImm()) return false;
711     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
712     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
713       int64_t Val = CE->getValue();
714       int64_t Align = 1LL << scale;
715       int64_t Max = Align * ((1LL << width) - 1);
716       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
717     }
718     return false;
719   }
720   // checks whether this operand is an signed offset which fits is a field
721   // of specified width and scaled by a specific number of bits
722   template<unsigned width, unsigned scale>
723   bool isSignedOffset() const {
724     if (!isImm()) return false;
725     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
726     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
727       int64_t Val = CE->getValue();
728       int64_t Align = 1LL << scale;
729       int64_t Max = Align * ((1LL << (width-1)) - 1);
730       int64_t Min = -Align * (1LL << (width-1));
731       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
732     }
733     return false;
734   }
735 
736   // checks whether this operand is a memory operand computed as an offset
737   // applied to PC. the offset may have 8 bits of magnitude and is represented
738   // with two bits of shift. textually it may be either [pc, #imm], #imm or
739   // relocable expression...
740   bool isThumbMemPC() const {
741     int64_t Val = 0;
742     if (isImm()) {
743       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
744       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
745       if (!CE) return false;
746       Val = CE->getValue();
747     }
748     else if (isMem()) {
749       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
750       if(Memory.BaseRegNum != ARM::PC) return false;
751       Val = Memory.OffsetImm->getValue();
752     }
753     else return false;
754     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
755   }
756   bool isFPImm() const {
757     if (!isImm()) return false;
758     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
759     if (!CE) return false;
760     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
761     return Val != -1;
762   }
763   bool isFBits16() const {
764     if (!isImm()) return false;
765     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
766     if (!CE) return false;
767     int64_t Value = CE->getValue();
768     return Value >= 0 && Value <= 16;
769   }
770   bool isFBits32() const {
771     if (!isImm()) return false;
772     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
773     if (!CE) return false;
774     int64_t Value = CE->getValue();
775     return Value >= 1 && Value <= 32;
776   }
777   bool isImm8s4() const {
778     if (!isImm()) return false;
779     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
780     if (!CE) return false;
781     int64_t Value = CE->getValue();
782     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
783   }
784   bool isImm0_1020s4() const {
785     if (!isImm()) return false;
786     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
787     if (!CE) return false;
788     int64_t Value = CE->getValue();
789     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
790   }
791   bool isImm0_508s4() const {
792     if (!isImm()) return false;
793     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
794     if (!CE) return false;
795     int64_t Value = CE->getValue();
796     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
797   }
798   bool isImm0_508s4Neg() const {
799     if (!isImm()) return false;
800     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
801     if (!CE) return false;
802     int64_t Value = -CE->getValue();
803     // explicitly exclude zero. we want that to use the normal 0_508 version.
804     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
805   }
806   bool isImm0_239() const {
807     if (!isImm()) return false;
808     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
809     if (!CE) return false;
810     int64_t Value = CE->getValue();
811     return Value >= 0 && Value < 240;
812   }
813   bool isImm0_255() const {
814     if (!isImm()) return false;
815     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816     if (!CE) return false;
817     int64_t Value = CE->getValue();
818     return Value >= 0 && Value < 256;
819   }
820   bool isImm0_4095() const {
821     if (!isImm()) return false;
822     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823     if (!CE) return false;
824     int64_t Value = CE->getValue();
825     return Value >= 0 && Value < 4096;
826   }
827   bool isImm0_4095Neg() const {
828     if (!isImm()) return false;
829     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
830     if (!CE) return false;
831     int64_t Value = -CE->getValue();
832     return Value > 0 && Value < 4096;
833   }
834   bool isImm0_1() const {
835     if (!isImm()) return false;
836     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
837     if (!CE) return false;
838     int64_t Value = CE->getValue();
839     return Value >= 0 && Value < 2;
840   }
841   bool isImm0_3() const {
842     if (!isImm()) return false;
843     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
844     if (!CE) return false;
845     int64_t Value = CE->getValue();
846     return Value >= 0 && Value < 4;
847   }
848   bool isImm0_7() const {
849     if (!isImm()) return false;
850     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
851     if (!CE) return false;
852     int64_t Value = CE->getValue();
853     return Value >= 0 && Value < 8;
854   }
855   bool isImm0_15() const {
856     if (!isImm()) return false;
857     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
858     if (!CE) return false;
859     int64_t Value = CE->getValue();
860     return Value >= 0 && Value < 16;
861   }
862   bool isImm0_31() const {
863     if (!isImm()) return false;
864     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
865     if (!CE) return false;
866     int64_t Value = CE->getValue();
867     return Value >= 0 && Value < 32;
868   }
869   bool isImm0_63() const {
870     if (!isImm()) return false;
871     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
872     if (!CE) return false;
873     int64_t Value = CE->getValue();
874     return Value >= 0 && Value < 64;
875   }
876   bool isImm8() const {
877     if (!isImm()) return false;
878     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
879     if (!CE) return false;
880     int64_t Value = CE->getValue();
881     return Value == 8;
882   }
883   bool isImm16() const {
884     if (!isImm()) return false;
885     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
886     if (!CE) return false;
887     int64_t Value = CE->getValue();
888     return Value == 16;
889   }
890   bool isImm32() const {
891     if (!isImm()) return false;
892     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
893     if (!CE) return false;
894     int64_t Value = CE->getValue();
895     return Value == 32;
896   }
897   bool isShrImm8() const {
898     if (!isImm()) return false;
899     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
900     if (!CE) return false;
901     int64_t Value = CE->getValue();
902     return Value > 0 && Value <= 8;
903   }
904   bool isShrImm16() const {
905     if (!isImm()) return false;
906     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
907     if (!CE) return false;
908     int64_t Value = CE->getValue();
909     return Value > 0 && Value <= 16;
910   }
911   bool isShrImm32() const {
912     if (!isImm()) return false;
913     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
914     if (!CE) return false;
915     int64_t Value = CE->getValue();
916     return Value > 0 && Value <= 32;
917   }
918   bool isShrImm64() const {
919     if (!isImm()) return false;
920     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
921     if (!CE) return false;
922     int64_t Value = CE->getValue();
923     return Value > 0 && Value <= 64;
924   }
925   bool isImm1_7() const {
926     if (!isImm()) return false;
927     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
928     if (!CE) return false;
929     int64_t Value = CE->getValue();
930     return Value > 0 && Value < 8;
931   }
932   bool isImm1_15() const {
933     if (!isImm()) return false;
934     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
935     if (!CE) return false;
936     int64_t Value = CE->getValue();
937     return Value > 0 && Value < 16;
938   }
939   bool isImm1_31() const {
940     if (!isImm()) return false;
941     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
942     if (!CE) return false;
943     int64_t Value = CE->getValue();
944     return Value > 0 && Value < 32;
945   }
946   bool isImm1_16() const {
947     if (!isImm()) return false;
948     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
949     if (!CE) return false;
950     int64_t Value = CE->getValue();
951     return Value > 0 && Value < 17;
952   }
953   bool isImm1_32() const {
954     if (!isImm()) return false;
955     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
956     if (!CE) return false;
957     int64_t Value = CE->getValue();
958     return Value > 0 && Value < 33;
959   }
960   bool isImm0_32() const {
961     if (!isImm()) return false;
962     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
963     if (!CE) return false;
964     int64_t Value = CE->getValue();
965     return Value >= 0 && Value < 33;
966   }
967   bool isImm0_65535() const {
968     if (!isImm()) return false;
969     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
970     if (!CE) return false;
971     int64_t Value = CE->getValue();
972     return Value >= 0 && Value < 65536;
973   }
974   bool isImm256_65535Expr() const {
975     if (!isImm()) return false;
976     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
977     // If it's not a constant expression, it'll generate a fixup and be
978     // handled later.
979     if (!CE) return true;
980     int64_t Value = CE->getValue();
981     return Value >= 256 && Value < 65536;
982   }
983   bool isImm0_65535Expr() const {
984     if (!isImm()) return false;
985     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
986     // If it's not a constant expression, it'll generate a fixup and be
987     // handled later.
988     if (!CE) return true;
989     int64_t Value = CE->getValue();
990     return Value >= 0 && Value < 65536;
991   }
992   bool isImm24bit() const {
993     if (!isImm()) return false;
994     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
995     if (!CE) return false;
996     int64_t Value = CE->getValue();
997     return Value >= 0 && Value <= 0xffffff;
998   }
999   bool isImmThumbSR() const {
1000     if (!isImm()) return false;
1001     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1002     if (!CE) return false;
1003     int64_t Value = CE->getValue();
1004     return Value > 0 && Value < 33;
1005   }
1006   bool isPKHLSLImm() const {
1007     if (!isImm()) return false;
1008     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1009     if (!CE) return false;
1010     int64_t Value = CE->getValue();
1011     return Value >= 0 && Value < 32;
1012   }
1013   bool isPKHASRImm() const {
1014     if (!isImm()) return false;
1015     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1016     if (!CE) return false;
1017     int64_t Value = CE->getValue();
1018     return Value > 0 && Value <= 32;
1019   }
1020   bool isAdrLabel() const {
1021     // If we have an immediate that's not a constant, treat it as a label
1022     // reference needing a fixup. If it is a constant, but it can't fit
1023     // into shift immediate encoding, we reject it.
1024     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1025     else return (isARMSOImm() || isARMSOImmNeg());
1026   }
1027   bool isARMSOImm() const {
1028     if (!isImm()) return false;
1029     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1030     if (!CE) return false;
1031     int64_t Value = CE->getValue();
1032     return ARM_AM::getSOImmVal(Value) != -1;
1033   }
1034   bool isARMSOImmNot() const {
1035     if (!isImm()) return false;
1036     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1037     if (!CE) return false;
1038     int64_t Value = CE->getValue();
1039     return ARM_AM::getSOImmVal(~Value) != -1;
1040   }
1041   bool isARMSOImmNeg() const {
1042     if (!isImm()) return false;
1043     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1044     if (!CE) return false;
1045     int64_t Value = CE->getValue();
1046     // Only use this when not representable as a plain so_imm.
1047     return ARM_AM::getSOImmVal(Value) == -1 &&
1048       ARM_AM::getSOImmVal(-Value) != -1;
1049   }
1050   bool isT2SOImm() const {
1051     if (!isImm()) return false;
1052     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1053     if (!CE) return false;
1054     int64_t Value = CE->getValue();
1055     return ARM_AM::getT2SOImmVal(Value) != -1;
1056   }
1057   bool isT2SOImmNot() const {
1058     if (!isImm()) return false;
1059     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1060     if (!CE) return false;
1061     int64_t Value = CE->getValue();
1062     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1063       ARM_AM::getT2SOImmVal(~Value) != -1;
1064   }
1065   bool isT2SOImmNeg() const {
1066     if (!isImm()) return false;
1067     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1068     if (!CE) return false;
1069     int64_t Value = CE->getValue();
1070     // Only use this when not representable as a plain so_imm.
1071     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1072       ARM_AM::getT2SOImmVal(-Value) != -1;
1073   }
1074   bool isSetEndImm() const {
1075     if (!isImm()) return false;
1076     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1077     if (!CE) return false;
1078     int64_t Value = CE->getValue();
1079     return Value == 1 || Value == 0;
1080   }
1081   bool isReg() const override { return Kind == k_Register; }
1082   bool isRegList() const { return Kind == k_RegisterList; }
1083   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1084   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1085   bool isToken() const override { return Kind == k_Token; }
1086   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1087   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1088   bool isMem() const override { return Kind == k_Memory; }
1089   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1090   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1091   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1092   bool isRotImm() const { return Kind == k_RotateImmediate; }
1093   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1094   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1095   bool isPostIdxReg() const {
1096     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1097   }
1098   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1099     if (!isMem())
1100       return false;
1101     // No offset of any kind.
1102     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1103      (alignOK || Memory.Alignment == Alignment);
1104   }
1105   bool isMemPCRelImm12() const {
1106     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1107       return false;
1108     // Base register must be PC.
1109     if (Memory.BaseRegNum != ARM::PC)
1110       return false;
1111     // Immediate offset in range [-4095, 4095].
1112     if (!Memory.OffsetImm) return true;
1113     int64_t Val = Memory.OffsetImm->getValue();
1114     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1115   }
1116   bool isAlignedMemory() const {
1117     return isMemNoOffset(true);
1118   }
1119   bool isAlignedMemoryNone() const {
1120     return isMemNoOffset(false, 0);
1121   }
1122   bool isDupAlignedMemoryNone() const {
1123     return isMemNoOffset(false, 0);
1124   }
1125   bool isAlignedMemory16() const {
1126     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1127       return true;
1128     return isMemNoOffset(false, 0);
1129   }
1130   bool isDupAlignedMemory16() const {
1131     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1132       return true;
1133     return isMemNoOffset(false, 0);
1134   }
1135   bool isAlignedMemory32() const {
1136     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1137       return true;
1138     return isMemNoOffset(false, 0);
1139   }
1140   bool isDupAlignedMemory32() const {
1141     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1142       return true;
1143     return isMemNoOffset(false, 0);
1144   }
1145   bool isAlignedMemory64() const {
1146     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1147       return true;
1148     return isMemNoOffset(false, 0);
1149   }
1150   bool isDupAlignedMemory64() const {
1151     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1152       return true;
1153     return isMemNoOffset(false, 0);
1154   }
1155   bool isAlignedMemory64or128() const {
1156     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1157       return true;
1158     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1159       return true;
1160     return isMemNoOffset(false, 0);
1161   }
1162   bool isDupAlignedMemory64or128() const {
1163     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1164       return true;
1165     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1166       return true;
1167     return isMemNoOffset(false, 0);
1168   }
1169   bool isAlignedMemory64or128or256() const {
1170     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1171       return true;
1172     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1173       return true;
1174     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1175       return true;
1176     return isMemNoOffset(false, 0);
1177   }
1178   bool isAddrMode2() const {
1179     if (!isMem() || Memory.Alignment != 0) return false;
1180     // Check for register offset.
1181     if (Memory.OffsetRegNum) return true;
1182     // Immediate offset in range [-4095, 4095].
1183     if (!Memory.OffsetImm) return true;
1184     int64_t Val = Memory.OffsetImm->getValue();
1185     return Val > -4096 && Val < 4096;
1186   }
1187   bool isAM2OffsetImm() const {
1188     if (!isImm()) return false;
1189     // Immediate offset in range [-4095, 4095].
1190     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1191     if (!CE) return false;
1192     int64_t Val = CE->getValue();
1193     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1194   }
1195   bool isAddrMode3() const {
1196     // If we have an immediate that's not a constant, treat it as a label
1197     // reference needing a fixup. If it is a constant, it's something else
1198     // and we reject it.
1199     if (isImm() && !isa<MCConstantExpr>(getImm()))
1200       return true;
1201     if (!isMem() || Memory.Alignment != 0) return false;
1202     // No shifts are legal for AM3.
1203     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1204     // Check for register offset.
1205     if (Memory.OffsetRegNum) return true;
1206     // Immediate offset in range [-255, 255].
1207     if (!Memory.OffsetImm) return true;
1208     int64_t Val = Memory.OffsetImm->getValue();
1209     // The #-0 offset is encoded as INT32_MIN, and we have to check
1210     // for this too.
1211     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1212   }
1213   bool isAM3Offset() const {
1214     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1215       return false;
1216     if (Kind == k_PostIndexRegister)
1217       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1218     // Immediate offset in range [-255, 255].
1219     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1220     if (!CE) return false;
1221     int64_t Val = CE->getValue();
1222     // Special case, #-0 is INT32_MIN.
1223     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1224   }
1225   bool isAddrMode5() const {
1226     // If we have an immediate that's not a constant, treat it as a label
1227     // reference needing a fixup. If it is a constant, it's something else
1228     // and we reject it.
1229     if (isImm() && !isa<MCConstantExpr>(getImm()))
1230       return true;
1231     if (!isMem() || Memory.Alignment != 0) return false;
1232     // Check for register offset.
1233     if (Memory.OffsetRegNum) return false;
1234     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1235     if (!Memory.OffsetImm) return true;
1236     int64_t Val = Memory.OffsetImm->getValue();
1237     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1238       Val == INT32_MIN;
1239   }
1240   bool isMemTBB() const {
1241     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1242         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1243       return false;
1244     return true;
1245   }
1246   bool isMemTBH() const {
1247     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1248         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1249         Memory.Alignment != 0 )
1250       return false;
1251     return true;
1252   }
1253   bool isMemRegOffset() const {
1254     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1255       return false;
1256     return true;
1257   }
1258   bool isT2MemRegOffset() const {
1259     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1260         Memory.Alignment != 0)
1261       return false;
1262     // Only lsl #{0, 1, 2, 3} allowed.
1263     if (Memory.ShiftType == ARM_AM::no_shift)
1264       return true;
1265     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1266       return false;
1267     return true;
1268   }
1269   bool isMemThumbRR() const {
1270     // Thumb reg+reg addressing is simple. Just two registers, a base and
1271     // an offset. No shifts, negations or any other complicating factors.
1272     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1273         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1274       return false;
1275     return isARMLowRegister(Memory.BaseRegNum) &&
1276       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1277   }
1278   bool isMemThumbRIs4() const {
1279     if (!isMem() || Memory.OffsetRegNum != 0 ||
1280         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1281       return false;
1282     // Immediate offset, multiple of 4 in range [0, 124].
1283     if (!Memory.OffsetImm) return true;
1284     int64_t Val = Memory.OffsetImm->getValue();
1285     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1286   }
1287   bool isMemThumbRIs2() const {
1288     if (!isMem() || Memory.OffsetRegNum != 0 ||
1289         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1290       return false;
1291     // Immediate offset, multiple of 4 in range [0, 62].
1292     if (!Memory.OffsetImm) return true;
1293     int64_t Val = Memory.OffsetImm->getValue();
1294     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1295   }
1296   bool isMemThumbRIs1() const {
1297     if (!isMem() || Memory.OffsetRegNum != 0 ||
1298         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1299       return false;
1300     // Immediate offset in range [0, 31].
1301     if (!Memory.OffsetImm) return true;
1302     int64_t Val = Memory.OffsetImm->getValue();
1303     return Val >= 0 && Val <= 31;
1304   }
1305   bool isMemThumbSPI() const {
1306     if (!isMem() || Memory.OffsetRegNum != 0 ||
1307         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1308       return false;
1309     // Immediate offset, multiple of 4 in range [0, 1020].
1310     if (!Memory.OffsetImm) return true;
1311     int64_t Val = Memory.OffsetImm->getValue();
1312     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1313   }
1314   bool isMemImm8s4Offset() const {
1315     // If we have an immediate that's not a constant, treat it as a label
1316     // reference needing a fixup. If it is a constant, it's something else
1317     // and we reject it.
1318     if (isImm() && !isa<MCConstantExpr>(getImm()))
1319       return true;
1320     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1321       return false;
1322     // Immediate offset a multiple of 4 in range [-1020, 1020].
1323     if (!Memory.OffsetImm) return true;
1324     int64_t Val = Memory.OffsetImm->getValue();
1325     // Special case, #-0 is INT32_MIN.
1326     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1327   }
1328   bool isMemImm0_1020s4Offset() const {
1329     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1330       return false;
1331     // Immediate offset a multiple of 4 in range [0, 1020].
1332     if (!Memory.OffsetImm) return true;
1333     int64_t Val = Memory.OffsetImm->getValue();
1334     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1335   }
1336   bool isMemImm8Offset() const {
1337     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1338       return false;
1339     // Base reg of PC isn't allowed for these encodings.
1340     if (Memory.BaseRegNum == ARM::PC) return false;
1341     // Immediate offset in range [-255, 255].
1342     if (!Memory.OffsetImm) return true;
1343     int64_t Val = Memory.OffsetImm->getValue();
1344     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1345   }
1346   bool isMemPosImm8Offset() const {
1347     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1348       return false;
1349     // Immediate offset in range [0, 255].
1350     if (!Memory.OffsetImm) return true;
1351     int64_t Val = Memory.OffsetImm->getValue();
1352     return Val >= 0 && Val < 256;
1353   }
1354   bool isMemNegImm8Offset() const {
1355     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1356       return false;
1357     // Base reg of PC isn't allowed for these encodings.
1358     if (Memory.BaseRegNum == ARM::PC) return false;
1359     // Immediate offset in range [-255, -1].
1360     if (!Memory.OffsetImm) return false;
1361     int64_t Val = Memory.OffsetImm->getValue();
1362     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1363   }
1364   bool isMemUImm12Offset() const {
1365     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1366       return false;
1367     // Immediate offset in range [0, 4095].
1368     if (!Memory.OffsetImm) return true;
1369     int64_t Val = Memory.OffsetImm->getValue();
1370     return (Val >= 0 && Val < 4096);
1371   }
1372   bool isMemImm12Offset() const {
1373     // If we have an immediate that's not a constant, treat it as a label
1374     // reference needing a fixup. If it is a constant, it's something else
1375     // and we reject it.
1376     if (isImm() && !isa<MCConstantExpr>(getImm()))
1377       return true;
1378 
1379     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1380       return false;
1381     // Immediate offset in range [-4095, 4095].
1382     if (!Memory.OffsetImm) return true;
1383     int64_t Val = Memory.OffsetImm->getValue();
1384     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1385   }
1386   bool isPostIdxImm8() const {
1387     if (!isImm()) return false;
1388     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1389     if (!CE) return false;
1390     int64_t Val = CE->getValue();
1391     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1392   }
1393   bool isPostIdxImm8s4() const {
1394     if (!isImm()) return false;
1395     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1396     if (!CE) return false;
1397     int64_t Val = CE->getValue();
1398     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1399       (Val == INT32_MIN);
1400   }
1401 
1402   bool isMSRMask() const { return Kind == k_MSRMask; }
1403   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1404 
1405   // NEON operands.
1406   bool isSingleSpacedVectorList() const {
1407     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1408   }
1409   bool isDoubleSpacedVectorList() const {
1410     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1411   }
1412   bool isVecListOneD() const {
1413     if (!isSingleSpacedVectorList()) return false;
1414     return VectorList.Count == 1;
1415   }
1416 
1417   bool isVecListDPair() const {
1418     if (!isSingleSpacedVectorList()) return false;
1419     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1420               .contains(VectorList.RegNum));
1421   }
1422 
1423   bool isVecListThreeD() const {
1424     if (!isSingleSpacedVectorList()) return false;
1425     return VectorList.Count == 3;
1426   }
1427 
1428   bool isVecListFourD() const {
1429     if (!isSingleSpacedVectorList()) return false;
1430     return VectorList.Count == 4;
1431   }
1432 
1433   bool isVecListDPairSpaced() const {
1434     if (Kind != k_VectorList) return false;
1435     if (isSingleSpacedVectorList()) return false;
1436     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1437               .contains(VectorList.RegNum));
1438   }
1439 
1440   bool isVecListThreeQ() const {
1441     if (!isDoubleSpacedVectorList()) return false;
1442     return VectorList.Count == 3;
1443   }
1444 
1445   bool isVecListFourQ() const {
1446     if (!isDoubleSpacedVectorList()) return false;
1447     return VectorList.Count == 4;
1448   }
1449 
1450   bool isSingleSpacedVectorAllLanes() const {
1451     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1452   }
1453   bool isDoubleSpacedVectorAllLanes() const {
1454     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1455   }
1456   bool isVecListOneDAllLanes() const {
1457     if (!isSingleSpacedVectorAllLanes()) return false;
1458     return VectorList.Count == 1;
1459   }
1460 
1461   bool isVecListDPairAllLanes() const {
1462     if (!isSingleSpacedVectorAllLanes()) return false;
1463     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1464               .contains(VectorList.RegNum));
1465   }
1466 
1467   bool isVecListDPairSpacedAllLanes() const {
1468     if (!isDoubleSpacedVectorAllLanes()) return false;
1469     return VectorList.Count == 2;
1470   }
1471 
1472   bool isVecListThreeDAllLanes() const {
1473     if (!isSingleSpacedVectorAllLanes()) return false;
1474     return VectorList.Count == 3;
1475   }
1476 
1477   bool isVecListThreeQAllLanes() const {
1478     if (!isDoubleSpacedVectorAllLanes()) return false;
1479     return VectorList.Count == 3;
1480   }
1481 
1482   bool isVecListFourDAllLanes() const {
1483     if (!isSingleSpacedVectorAllLanes()) return false;
1484     return VectorList.Count == 4;
1485   }
1486 
1487   bool isVecListFourQAllLanes() const {
1488     if (!isDoubleSpacedVectorAllLanes()) return false;
1489     return VectorList.Count == 4;
1490   }
1491 
1492   bool isSingleSpacedVectorIndexed() const {
1493     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1494   }
1495   bool isDoubleSpacedVectorIndexed() const {
1496     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1497   }
1498   bool isVecListOneDByteIndexed() const {
1499     if (!isSingleSpacedVectorIndexed()) return false;
1500     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1501   }
1502 
1503   bool isVecListOneDHWordIndexed() const {
1504     if (!isSingleSpacedVectorIndexed()) return false;
1505     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1506   }
1507 
1508   bool isVecListOneDWordIndexed() const {
1509     if (!isSingleSpacedVectorIndexed()) return false;
1510     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1511   }
1512 
1513   bool isVecListTwoDByteIndexed() const {
1514     if (!isSingleSpacedVectorIndexed()) return false;
1515     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1516   }
1517 
1518   bool isVecListTwoDHWordIndexed() const {
1519     if (!isSingleSpacedVectorIndexed()) return false;
1520     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1521   }
1522 
1523   bool isVecListTwoQWordIndexed() const {
1524     if (!isDoubleSpacedVectorIndexed()) return false;
1525     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1526   }
1527 
1528   bool isVecListTwoQHWordIndexed() const {
1529     if (!isDoubleSpacedVectorIndexed()) return false;
1530     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1531   }
1532 
1533   bool isVecListTwoDWordIndexed() const {
1534     if (!isSingleSpacedVectorIndexed()) return false;
1535     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1536   }
1537 
1538   bool isVecListThreeDByteIndexed() const {
1539     if (!isSingleSpacedVectorIndexed()) return false;
1540     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1541   }
1542 
1543   bool isVecListThreeDHWordIndexed() const {
1544     if (!isSingleSpacedVectorIndexed()) return false;
1545     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1546   }
1547 
1548   bool isVecListThreeQWordIndexed() const {
1549     if (!isDoubleSpacedVectorIndexed()) return false;
1550     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1551   }
1552 
1553   bool isVecListThreeQHWordIndexed() const {
1554     if (!isDoubleSpacedVectorIndexed()) return false;
1555     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1556   }
1557 
1558   bool isVecListThreeDWordIndexed() const {
1559     if (!isSingleSpacedVectorIndexed()) return false;
1560     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1561   }
1562 
1563   bool isVecListFourDByteIndexed() const {
1564     if (!isSingleSpacedVectorIndexed()) return false;
1565     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1566   }
1567 
1568   bool isVecListFourDHWordIndexed() const {
1569     if (!isSingleSpacedVectorIndexed()) return false;
1570     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1571   }
1572 
1573   bool isVecListFourQWordIndexed() const {
1574     if (!isDoubleSpacedVectorIndexed()) return false;
1575     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1576   }
1577 
1578   bool isVecListFourQHWordIndexed() const {
1579     if (!isDoubleSpacedVectorIndexed()) return false;
1580     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1581   }
1582 
1583   bool isVecListFourDWordIndexed() const {
1584     if (!isSingleSpacedVectorIndexed()) return false;
1585     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1586   }
1587 
1588   bool isVectorIndex8() const {
1589     if (Kind != k_VectorIndex) return false;
1590     return VectorIndex.Val < 8;
1591   }
1592   bool isVectorIndex16() const {
1593     if (Kind != k_VectorIndex) return false;
1594     return VectorIndex.Val < 4;
1595   }
1596   bool isVectorIndex32() const {
1597     if (Kind != k_VectorIndex) return false;
1598     return VectorIndex.Val < 2;
1599   }
1600 
1601   bool isNEONi8splat() const {
1602     if (!isImm()) return false;
1603     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1604     // Must be a constant.
1605     if (!CE) return false;
1606     int64_t Value = CE->getValue();
1607     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1608     // value.
1609     return Value >= 0 && Value < 256;
1610   }
1611 
1612   bool isNEONi16splat() const {
1613     if (!isImm()) return false;
1614     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1615     // Must be a constant.
1616     if (!CE) return false;
1617     int64_t Value = CE->getValue();
1618     // i16 value in the range [0,255] or [0x0100, 0xff00]
1619     return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1620   }
1621 
1622   bool isNEONi32splat() const {
1623     if (!isImm()) return false;
1624     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1625     // Must be a constant.
1626     if (!CE) return false;
1627     int64_t Value = CE->getValue();
1628     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1629     return (Value >= 0 && Value < 256) ||
1630       (Value >= 0x0100 && Value <= 0xff00) ||
1631       (Value >= 0x010000 && Value <= 0xff0000) ||
1632       (Value >= 0x01000000 && Value <= 0xff000000);
1633   }
1634 
1635   bool isNEONi32vmov() const {
1636     if (!isImm()) return false;
1637     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1638     // Must be a constant.
1639     if (!CE) return false;
1640     int64_t Value = CE->getValue();
1641     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1642     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1643     return (Value >= 0 && Value < 256) ||
1644       (Value >= 0x0100 && Value <= 0xff00) ||
1645       (Value >= 0x010000 && Value <= 0xff0000) ||
1646       (Value >= 0x01000000 && Value <= 0xff000000) ||
1647       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1648       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1649   }
1650   bool isNEONi32vmovNeg() const {
1651     if (!isImm()) return false;
1652     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1653     // Must be a constant.
1654     if (!CE) return false;
1655     int64_t Value = ~CE->getValue();
1656     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1657     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1658     return (Value >= 0 && Value < 256) ||
1659       (Value >= 0x0100 && Value <= 0xff00) ||
1660       (Value >= 0x010000 && Value <= 0xff0000) ||
1661       (Value >= 0x01000000 && Value <= 0xff000000) ||
1662       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1663       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1664   }
1665 
1666   bool isNEONi64splat() const {
1667     if (!isImm()) return false;
1668     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1669     // Must be a constant.
1670     if (!CE) return false;
1671     uint64_t Value = CE->getValue();
1672     // i64 value with each byte being either 0 or 0xff.
1673     for (unsigned i = 0; i < 8; ++i)
1674       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1675     return true;
1676   }
1677 
1678   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1679     // Add as immediates when possible.  Null MCExpr = 0.
1680     if (Expr == 0)
1681       Inst.addOperand(MCOperand::CreateImm(0));
1682     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1683       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1684     else
1685       Inst.addOperand(MCOperand::CreateExpr(Expr));
1686   }
1687 
1688   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1689     assert(N == 2 && "Invalid number of operands!");
1690     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1691     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1692     Inst.addOperand(MCOperand::CreateReg(RegNum));
1693   }
1694 
1695   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1696     assert(N == 1 && "Invalid number of operands!");
1697     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1698   }
1699 
1700   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1701     assert(N == 1 && "Invalid number of operands!");
1702     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1703   }
1704 
1705   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1706     assert(N == 1 && "Invalid number of operands!");
1707     Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1708   }
1709 
1710   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1711     assert(N == 1 && "Invalid number of operands!");
1712     Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1713   }
1714 
1715   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1716     assert(N == 1 && "Invalid number of operands!");
1717     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1718   }
1719 
1720   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1721     assert(N == 1 && "Invalid number of operands!");
1722     Inst.addOperand(MCOperand::CreateReg(getReg()));
1723   }
1724 
1725   void addRegOperands(MCInst &Inst, unsigned N) const {
1726     assert(N == 1 && "Invalid number of operands!");
1727     Inst.addOperand(MCOperand::CreateReg(getReg()));
1728   }
1729 
1730   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1731     assert(N == 3 && "Invalid number of operands!");
1732     assert(isRegShiftedReg() &&
1733            "addRegShiftedRegOperands() on non-RegShiftedReg!");
1734     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1735     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1736     Inst.addOperand(MCOperand::CreateImm(
1737       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1738   }
1739 
1740   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1741     assert(N == 2 && "Invalid number of operands!");
1742     assert(isRegShiftedImm() &&
1743            "addRegShiftedImmOperands() on non-RegShiftedImm!");
1744     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1745     // Shift of #32 is encoded as 0 where permitted
1746     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1747     Inst.addOperand(MCOperand::CreateImm(
1748       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1749   }
1750 
1751   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1752     assert(N == 1 && "Invalid number of operands!");
1753     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1754                                          ShifterImm.Imm));
1755   }
1756 
1757   void addRegListOperands(MCInst &Inst, unsigned N) const {
1758     assert(N == 1 && "Invalid number of operands!");
1759     const SmallVectorImpl<unsigned> &RegList = getRegList();
1760     for (SmallVectorImpl<unsigned>::const_iterator
1761            I = RegList.begin(), E = RegList.end(); I != E; ++I)
1762       Inst.addOperand(MCOperand::CreateReg(*I));
1763   }
1764 
1765   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1766     addRegListOperands(Inst, N);
1767   }
1768 
1769   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1770     addRegListOperands(Inst, N);
1771   }
1772 
1773   void addRotImmOperands(MCInst &Inst, unsigned N) const {
1774     assert(N == 1 && "Invalid number of operands!");
1775     // Encoded as val>>3. The printer handles display as 8, 16, 24.
1776     Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1777   }
1778 
1779   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1780     assert(N == 1 && "Invalid number of operands!");
1781     // Munge the lsb/width into a bitfield mask.
1782     unsigned lsb = Bitfield.LSB;
1783     unsigned width = Bitfield.Width;
1784     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1785     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1786                       (32 - (lsb + width)));
1787     Inst.addOperand(MCOperand::CreateImm(Mask));
1788   }
1789 
1790   void addImmOperands(MCInst &Inst, unsigned N) const {
1791     assert(N == 1 && "Invalid number of operands!");
1792     addExpr(Inst, getImm());
1793   }
1794 
1795   void addFBits16Operands(MCInst &Inst, unsigned N) const {
1796     assert(N == 1 && "Invalid number of operands!");
1797     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1798     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1799   }
1800 
1801   void addFBits32Operands(MCInst &Inst, unsigned N) const {
1802     assert(N == 1 && "Invalid number of operands!");
1803     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1804     Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1805   }
1806 
1807   void addFPImmOperands(MCInst &Inst, unsigned N) const {
1808     assert(N == 1 && "Invalid number of operands!");
1809     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1810     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1811     Inst.addOperand(MCOperand::CreateImm(Val));
1812   }
1813 
1814   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1815     assert(N == 1 && "Invalid number of operands!");
1816     // FIXME: We really want to scale the value here, but the LDRD/STRD
1817     // instruction don't encode operands that way yet.
1818     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1819     Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1820   }
1821 
1822   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1823     assert(N == 1 && "Invalid number of operands!");
1824     // The immediate is scaled by four in the encoding and is stored
1825     // in the MCInst as such. Lop off the low two bits here.
1826     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1827     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1828   }
1829 
1830   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1831     assert(N == 1 && "Invalid number of operands!");
1832     // The immediate is scaled by four in the encoding and is stored
1833     // in the MCInst as such. Lop off the low two bits here.
1834     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1835     Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1836   }
1837 
1838   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1839     assert(N == 1 && "Invalid number of operands!");
1840     // The immediate is scaled by four in the encoding and is stored
1841     // in the MCInst as such. Lop off the low two bits here.
1842     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1843     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1844   }
1845 
1846   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1847     assert(N == 1 && "Invalid number of operands!");
1848     // The constant encodes as the immediate-1, and we store in the instruction
1849     // the bits as encoded, so subtract off one here.
1850     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1851     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1852   }
1853 
1854   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1855     assert(N == 1 && "Invalid number of operands!");
1856     // The constant encodes as the immediate-1, and we store in the instruction
1857     // the bits as encoded, so subtract off one here.
1858     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1859     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1860   }
1861 
1862   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1863     assert(N == 1 && "Invalid number of operands!");
1864     // The constant encodes as the immediate, except for 32, which encodes as
1865     // zero.
1866     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1867     unsigned Imm = CE->getValue();
1868     Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1869   }
1870 
1871   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1872     assert(N == 1 && "Invalid number of operands!");
1873     // An ASR value of 32 encodes as 0, so that's how we want to add it to
1874     // the instruction as well.
1875     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1876     int Val = CE->getValue();
1877     Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1878   }
1879 
1880   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1881     assert(N == 1 && "Invalid number of operands!");
1882     // The operand is actually a t2_so_imm, but we have its bitwise
1883     // negation in the assembly source, so twiddle it here.
1884     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1885     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1886   }
1887 
1888   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1889     assert(N == 1 && "Invalid number of operands!");
1890     // The operand is actually a t2_so_imm, but we have its
1891     // negation in the assembly source, so twiddle it here.
1892     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1893     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1894   }
1895 
1896   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1897     assert(N == 1 && "Invalid number of operands!");
1898     // The operand is actually an imm0_4095, but we have its
1899     // negation in the assembly source, so twiddle it here.
1900     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1901     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1902   }
1903 
1904   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1905     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1906       Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1907       return;
1908     }
1909 
1910     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1911     assert(SR && "Unknown value type!");
1912     Inst.addOperand(MCOperand::CreateExpr(SR));
1913   }
1914 
1915   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1916     assert(N == 1 && "Invalid number of operands!");
1917     if (isImm()) {
1918       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1919       if (CE) {
1920         Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1921         return;
1922       }
1923 
1924       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1925       assert(SR && "Unknown value type!");
1926       Inst.addOperand(MCOperand::CreateExpr(SR));
1927       return;
1928     }
1929 
1930     assert(isMem()  && "Unknown value type!");
1931     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1932     Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1933   }
1934 
1935   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1936     assert(N == 1 && "Invalid number of operands!");
1937     // The operand is actually a so_imm, but we have its bitwise
1938     // negation in the assembly source, so twiddle it here.
1939     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1940     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1941   }
1942 
1943   void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1944     assert(N == 1 && "Invalid number of operands!");
1945     // The operand is actually a so_imm, but we have its
1946     // negation in the assembly source, so twiddle it here.
1947     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1948     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1949   }
1950 
1951   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1952     assert(N == 1 && "Invalid number of operands!");
1953     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1954   }
1955 
1956   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1957     assert(N == 1 && "Invalid number of operands!");
1958     Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1959   }
1960 
1961   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1962     assert(N == 1 && "Invalid number of operands!");
1963     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1964   }
1965 
1966   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1967     assert(N == 1 && "Invalid number of operands!");
1968     int32_t Imm = Memory.OffsetImm->getValue();
1969     Inst.addOperand(MCOperand::CreateImm(Imm));
1970   }
1971 
1972   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1973     assert(N == 1 && "Invalid number of operands!");
1974     assert(isImm() && "Not an immediate!");
1975 
1976     // If we have an immediate that's not a constant, treat it as a label
1977     // reference needing a fixup.
1978     if (!isa<MCConstantExpr>(getImm())) {
1979       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1980       return;
1981     }
1982 
1983     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1984     int Val = CE->getValue();
1985     Inst.addOperand(MCOperand::CreateImm(Val));
1986   }
1987 
1988   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1989     assert(N == 2 && "Invalid number of operands!");
1990     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1991     Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1992   }
1993 
1994   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1995     addAlignedMemoryOperands(Inst, N);
1996   }
1997 
1998   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1999     addAlignedMemoryOperands(Inst, N);
2000   }
2001 
2002   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2003     addAlignedMemoryOperands(Inst, N);
2004   }
2005 
2006   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2007     addAlignedMemoryOperands(Inst, N);
2008   }
2009 
2010   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2011     addAlignedMemoryOperands(Inst, N);
2012   }
2013 
2014   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2015     addAlignedMemoryOperands(Inst, N);
2016   }
2017 
2018   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2019     addAlignedMemoryOperands(Inst, N);
2020   }
2021 
2022   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2023     addAlignedMemoryOperands(Inst, N);
2024   }
2025 
2026   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2027     addAlignedMemoryOperands(Inst, N);
2028   }
2029 
2030   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2031     addAlignedMemoryOperands(Inst, N);
2032   }
2033 
2034   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2035     addAlignedMemoryOperands(Inst, N);
2036   }
2037 
2038   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2039     assert(N == 3 && "Invalid number of operands!");
2040     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2041     if (!Memory.OffsetRegNum) {
2042       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2043       // Special case for #-0
2044       if (Val == INT32_MIN) Val = 0;
2045       if (Val < 0) Val = -Val;
2046       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2047     } else {
2048       // For register offset, we encode the shift type and negation flag
2049       // here.
2050       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2051                               Memory.ShiftImm, Memory.ShiftType);
2052     }
2053     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2054     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2055     Inst.addOperand(MCOperand::CreateImm(Val));
2056   }
2057 
2058   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2059     assert(N == 2 && "Invalid number of operands!");
2060     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2061     assert(CE && "non-constant AM2OffsetImm operand!");
2062     int32_t Val = CE->getValue();
2063     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2064     // Special case for #-0
2065     if (Val == INT32_MIN) Val = 0;
2066     if (Val < 0) Val = -Val;
2067     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2068     Inst.addOperand(MCOperand::CreateReg(0));
2069     Inst.addOperand(MCOperand::CreateImm(Val));
2070   }
2071 
2072   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2073     assert(N == 3 && "Invalid number of operands!");
2074     // If we have an immediate that's not a constant, treat it as a label
2075     // reference needing a fixup. If it is a constant, it's something else
2076     // and we reject it.
2077     if (isImm()) {
2078       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2079       Inst.addOperand(MCOperand::CreateReg(0));
2080       Inst.addOperand(MCOperand::CreateImm(0));
2081       return;
2082     }
2083 
2084     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2085     if (!Memory.OffsetRegNum) {
2086       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2087       // Special case for #-0
2088       if (Val == INT32_MIN) Val = 0;
2089       if (Val < 0) Val = -Val;
2090       Val = ARM_AM::getAM3Opc(AddSub, Val);
2091     } else {
2092       // For register offset, we encode the shift type and negation flag
2093       // here.
2094       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2095     }
2096     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2097     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2098     Inst.addOperand(MCOperand::CreateImm(Val));
2099   }
2100 
2101   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2102     assert(N == 2 && "Invalid number of operands!");
2103     if (Kind == k_PostIndexRegister) {
2104       int32_t Val =
2105         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2106       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2107       Inst.addOperand(MCOperand::CreateImm(Val));
2108       return;
2109     }
2110 
2111     // Constant offset.
2112     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2113     int32_t Val = CE->getValue();
2114     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2115     // Special case for #-0
2116     if (Val == INT32_MIN) Val = 0;
2117     if (Val < 0) Val = -Val;
2118     Val = ARM_AM::getAM3Opc(AddSub, Val);
2119     Inst.addOperand(MCOperand::CreateReg(0));
2120     Inst.addOperand(MCOperand::CreateImm(Val));
2121   }
2122 
2123   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2124     assert(N == 2 && "Invalid number of operands!");
2125     // If we have an immediate that's not a constant, treat it as a label
2126     // reference needing a fixup. If it is a constant, it's something else
2127     // and we reject it.
2128     if (isImm()) {
2129       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2130       Inst.addOperand(MCOperand::CreateImm(0));
2131       return;
2132     }
2133 
2134     // The lower two bits are always zero and as such are not encoded.
2135     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2136     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2137     // Special case for #-0
2138     if (Val == INT32_MIN) Val = 0;
2139     if (Val < 0) Val = -Val;
2140     Val = ARM_AM::getAM5Opc(AddSub, Val);
2141     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2142     Inst.addOperand(MCOperand::CreateImm(Val));
2143   }
2144 
2145   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2146     assert(N == 2 && "Invalid number of operands!");
2147     // If we have an immediate that's not a constant, treat it as a label
2148     // reference needing a fixup. If it is a constant, it's something else
2149     // and we reject it.
2150     if (isImm()) {
2151       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2152       Inst.addOperand(MCOperand::CreateImm(0));
2153       return;
2154     }
2155 
2156     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2157     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2158     Inst.addOperand(MCOperand::CreateImm(Val));
2159   }
2160 
2161   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2162     assert(N == 2 && "Invalid number of operands!");
2163     // The lower two bits are always zero and as such are not encoded.
2164     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2165     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2166     Inst.addOperand(MCOperand::CreateImm(Val));
2167   }
2168 
2169   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2170     assert(N == 2 && "Invalid number of operands!");
2171     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2172     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2173     Inst.addOperand(MCOperand::CreateImm(Val));
2174   }
2175 
2176   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2177     addMemImm8OffsetOperands(Inst, N);
2178   }
2179 
2180   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2181     addMemImm8OffsetOperands(Inst, N);
2182   }
2183 
2184   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2185     assert(N == 2 && "Invalid number of operands!");
2186     // If this is an immediate, it's a label reference.
2187     if (isImm()) {
2188       addExpr(Inst, getImm());
2189       Inst.addOperand(MCOperand::CreateImm(0));
2190       return;
2191     }
2192 
2193     // Otherwise, it's a normal memory reg+offset.
2194     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2195     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2196     Inst.addOperand(MCOperand::CreateImm(Val));
2197   }
2198 
2199   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2200     assert(N == 2 && "Invalid number of operands!");
2201     // If this is an immediate, it's a label reference.
2202     if (isImm()) {
2203       addExpr(Inst, getImm());
2204       Inst.addOperand(MCOperand::CreateImm(0));
2205       return;
2206     }
2207 
2208     // Otherwise, it's a normal memory reg+offset.
2209     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2210     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2211     Inst.addOperand(MCOperand::CreateImm(Val));
2212   }
2213 
2214   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2215     assert(N == 2 && "Invalid number of operands!");
2216     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2217     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2218   }
2219 
2220   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2221     assert(N == 2 && "Invalid number of operands!");
2222     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2223     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2224   }
2225 
2226   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2227     assert(N == 3 && "Invalid number of operands!");
2228     unsigned Val =
2229       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2230                         Memory.ShiftImm, Memory.ShiftType);
2231     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2232     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2233     Inst.addOperand(MCOperand::CreateImm(Val));
2234   }
2235 
2236   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2237     assert(N == 3 && "Invalid number of operands!");
2238     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2239     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2240     Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2241   }
2242 
2243   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2244     assert(N == 2 && "Invalid number of operands!");
2245     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2246     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2247   }
2248 
2249   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2250     assert(N == 2 && "Invalid number of operands!");
2251     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2252     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2253     Inst.addOperand(MCOperand::CreateImm(Val));
2254   }
2255 
2256   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2257     assert(N == 2 && "Invalid number of operands!");
2258     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2259     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2260     Inst.addOperand(MCOperand::CreateImm(Val));
2261   }
2262 
2263   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2264     assert(N == 2 && "Invalid number of operands!");
2265     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2266     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2267     Inst.addOperand(MCOperand::CreateImm(Val));
2268   }
2269 
2270   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2271     assert(N == 2 && "Invalid number of operands!");
2272     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2273     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2274     Inst.addOperand(MCOperand::CreateImm(Val));
2275   }
2276 
2277   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2278     assert(N == 1 && "Invalid number of operands!");
2279     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2280     assert(CE && "non-constant post-idx-imm8 operand!");
2281     int Imm = CE->getValue();
2282     bool isAdd = Imm >= 0;
2283     if (Imm == INT32_MIN) Imm = 0;
2284     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2285     Inst.addOperand(MCOperand::CreateImm(Imm));
2286   }
2287 
2288   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2289     assert(N == 1 && "Invalid number of operands!");
2290     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2291     assert(CE && "non-constant post-idx-imm8s4 operand!");
2292     int Imm = CE->getValue();
2293     bool isAdd = Imm >= 0;
2294     if (Imm == INT32_MIN) Imm = 0;
2295     // Immediate is scaled by 4.
2296     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2297     Inst.addOperand(MCOperand::CreateImm(Imm));
2298   }
2299 
2300   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2301     assert(N == 2 && "Invalid number of operands!");
2302     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2303     Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2304   }
2305 
2306   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2307     assert(N == 2 && "Invalid number of operands!");
2308     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2309     // The sign, shift type, and shift amount are encoded in a single operand
2310     // using the AM2 encoding helpers.
2311     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2312     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2313                                      PostIdxReg.ShiftTy);
2314     Inst.addOperand(MCOperand::CreateImm(Imm));
2315   }
2316 
2317   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2318     assert(N == 1 && "Invalid number of operands!");
2319     Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2320   }
2321 
2322   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2323     assert(N == 1 && "Invalid number of operands!");
2324     Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2325   }
2326 
2327   void addVecListOperands(MCInst &Inst, unsigned N) const {
2328     assert(N == 1 && "Invalid number of operands!");
2329     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2330   }
2331 
2332   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2333     assert(N == 2 && "Invalid number of operands!");
2334     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2335     Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2336   }
2337 
2338   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2339     assert(N == 1 && "Invalid number of operands!");
2340     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2341   }
2342 
2343   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2344     assert(N == 1 && "Invalid number of operands!");
2345     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2346   }
2347 
2348   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2349     assert(N == 1 && "Invalid number of operands!");
2350     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2351   }
2352 
2353   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2354     assert(N == 1 && "Invalid number of operands!");
2355     // The immediate encodes the type of constant as well as the value.
2356     // Mask in that this is an i8 splat.
2357     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2358     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2359   }
2360 
2361   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2362     assert(N == 1 && "Invalid number of operands!");
2363     // The immediate encodes the type of constant as well as the value.
2364     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2365     unsigned Value = CE->getValue();
2366     if (Value >= 256)
2367       Value = (Value >> 8) | 0xa00;
2368     else
2369       Value |= 0x800;
2370     Inst.addOperand(MCOperand::CreateImm(Value));
2371   }
2372 
2373   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2374     assert(N == 1 && "Invalid number of operands!");
2375     // The immediate encodes the type of constant as well as the value.
2376     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2377     unsigned Value = CE->getValue();
2378     if (Value >= 256 && Value <= 0xff00)
2379       Value = (Value >> 8) | 0x200;
2380     else if (Value > 0xffff && Value <= 0xff0000)
2381       Value = (Value >> 16) | 0x400;
2382     else if (Value > 0xffffff)
2383       Value = (Value >> 24) | 0x600;
2384     Inst.addOperand(MCOperand::CreateImm(Value));
2385   }
2386 
2387   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2388     assert(N == 1 && "Invalid number of operands!");
2389     // The immediate encodes the type of constant as well as the value.
2390     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2391     unsigned Value = CE->getValue();
2392     if (Value >= 256 && Value <= 0xffff)
2393       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2394     else if (Value > 0xffff && Value <= 0xffffff)
2395       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2396     else if (Value > 0xffffff)
2397       Value = (Value >> 24) | 0x600;
2398     Inst.addOperand(MCOperand::CreateImm(Value));
2399   }
2400 
2401   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2402     assert(N == 1 && "Invalid number of operands!");
2403     // The immediate encodes the type of constant as well as the value.
2404     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2405     unsigned Value = ~CE->getValue();
2406     if (Value >= 256 && Value <= 0xffff)
2407       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2408     else if (Value > 0xffff && Value <= 0xffffff)
2409       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2410     else if (Value > 0xffffff)
2411       Value = (Value >> 24) | 0x600;
2412     Inst.addOperand(MCOperand::CreateImm(Value));
2413   }
2414 
2415   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2416     assert(N == 1 && "Invalid number of operands!");
2417     // The immediate encodes the type of constant as well as the value.
2418     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2419     uint64_t Value = CE->getValue();
2420     unsigned Imm = 0;
2421     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2422       Imm |= (Value & 1) << i;
2423     }
2424     Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2425   }
2426 
2427   void print(raw_ostream &OS) const override;
2428 
2429   static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2430     ARMOperand *Op = new ARMOperand(k_ITCondMask);
2431     Op->ITMask.Mask = Mask;
2432     Op->StartLoc = S;
2433     Op->EndLoc = S;
2434     return Op;
2435   }
2436 
2437   static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2438     ARMOperand *Op = new ARMOperand(k_CondCode);
2439     Op->CC.Val = CC;
2440     Op->StartLoc = S;
2441     Op->EndLoc = S;
2442     return Op;
2443   }
2444 
2445   static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2446     ARMOperand *Op = new ARMOperand(k_CoprocNum);
2447     Op->Cop.Val = CopVal;
2448     Op->StartLoc = S;
2449     Op->EndLoc = S;
2450     return Op;
2451   }
2452 
2453   static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2454     ARMOperand *Op = new ARMOperand(k_CoprocReg);
2455     Op->Cop.Val = CopVal;
2456     Op->StartLoc = S;
2457     Op->EndLoc = S;
2458     return Op;
2459   }
2460 
2461   static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2462     ARMOperand *Op = new ARMOperand(k_CoprocOption);
2463     Op->Cop.Val = Val;
2464     Op->StartLoc = S;
2465     Op->EndLoc = E;
2466     return Op;
2467   }
2468 
2469   static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2470     ARMOperand *Op = new ARMOperand(k_CCOut);
2471     Op->Reg.RegNum = RegNum;
2472     Op->StartLoc = S;
2473     Op->EndLoc = S;
2474     return Op;
2475   }
2476 
2477   static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2478     ARMOperand *Op = new ARMOperand(k_Token);
2479     Op->Tok.Data = Str.data();
2480     Op->Tok.Length = Str.size();
2481     Op->StartLoc = S;
2482     Op->EndLoc = S;
2483     return Op;
2484   }
2485 
2486   static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2487     ARMOperand *Op = new ARMOperand(k_Register);
2488     Op->Reg.RegNum = RegNum;
2489     Op->StartLoc = S;
2490     Op->EndLoc = E;
2491     return Op;
2492   }
2493 
2494   static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2495                                            unsigned SrcReg,
2496                                            unsigned ShiftReg,
2497                                            unsigned ShiftImm,
2498                                            SMLoc S, SMLoc E) {
2499     ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2500     Op->RegShiftedReg.ShiftTy = ShTy;
2501     Op->RegShiftedReg.SrcReg = SrcReg;
2502     Op->RegShiftedReg.ShiftReg = ShiftReg;
2503     Op->RegShiftedReg.ShiftImm = ShiftImm;
2504     Op->StartLoc = S;
2505     Op->EndLoc = E;
2506     return Op;
2507   }
2508 
2509   static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2510                                             unsigned SrcReg,
2511                                             unsigned ShiftImm,
2512                                             SMLoc S, SMLoc E) {
2513     ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2514     Op->RegShiftedImm.ShiftTy = ShTy;
2515     Op->RegShiftedImm.SrcReg = SrcReg;
2516     Op->RegShiftedImm.ShiftImm = ShiftImm;
2517     Op->StartLoc = S;
2518     Op->EndLoc = E;
2519     return Op;
2520   }
2521 
2522   static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2523                                    SMLoc S, SMLoc E) {
2524     ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2525     Op->ShifterImm.isASR = isASR;
2526     Op->ShifterImm.Imm = Imm;
2527     Op->StartLoc = S;
2528     Op->EndLoc = E;
2529     return Op;
2530   }
2531 
2532   static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2533     ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2534     Op->RotImm.Imm = Imm;
2535     Op->StartLoc = S;
2536     Op->EndLoc = E;
2537     return Op;
2538   }
2539 
2540   static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2541                                     SMLoc S, SMLoc E) {
2542     ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2543     Op->Bitfield.LSB = LSB;
2544     Op->Bitfield.Width = Width;
2545     Op->StartLoc = S;
2546     Op->EndLoc = E;
2547     return Op;
2548   }
2549 
2550   static ARMOperand *
2551   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2552                 SMLoc StartLoc, SMLoc EndLoc) {
2553     assert (Regs.size() > 0 && "RegList contains no registers?");
2554     KindTy Kind = k_RegisterList;
2555 
2556     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2557       Kind = k_DPRRegisterList;
2558     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2559              contains(Regs.front().second))
2560       Kind = k_SPRRegisterList;
2561 
2562     // Sort based on the register encoding values.
2563     array_pod_sort(Regs.begin(), Regs.end());
2564 
2565     ARMOperand *Op = new ARMOperand(Kind);
2566     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2567            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2568       Op->Registers.push_back(I->second);
2569     Op->StartLoc = StartLoc;
2570     Op->EndLoc = EndLoc;
2571     return Op;
2572   }
2573 
2574   static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2575                                       bool isDoubleSpaced, SMLoc S, SMLoc E) {
2576     ARMOperand *Op = new ARMOperand(k_VectorList);
2577     Op->VectorList.RegNum = RegNum;
2578     Op->VectorList.Count = Count;
2579     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2580     Op->StartLoc = S;
2581     Op->EndLoc = E;
2582     return Op;
2583   }
2584 
2585   static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2586                                               bool isDoubleSpaced,
2587                                               SMLoc S, SMLoc E) {
2588     ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2589     Op->VectorList.RegNum = RegNum;
2590     Op->VectorList.Count = Count;
2591     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2592     Op->StartLoc = S;
2593     Op->EndLoc = E;
2594     return Op;
2595   }
2596 
2597   static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2598                                              unsigned Index,
2599                                              bool isDoubleSpaced,
2600                                              SMLoc S, SMLoc E) {
2601     ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2602     Op->VectorList.RegNum = RegNum;
2603     Op->VectorList.Count = Count;
2604     Op->VectorList.LaneIndex = Index;
2605     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2606     Op->StartLoc = S;
2607     Op->EndLoc = E;
2608     return Op;
2609   }
2610 
2611   static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2612                                        MCContext &Ctx) {
2613     ARMOperand *Op = new ARMOperand(k_VectorIndex);
2614     Op->VectorIndex.Val = Idx;
2615     Op->StartLoc = S;
2616     Op->EndLoc = E;
2617     return Op;
2618   }
2619 
2620   static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2621     ARMOperand *Op = new ARMOperand(k_Immediate);
2622     Op->Imm.Val = Val;
2623     Op->StartLoc = S;
2624     Op->EndLoc = E;
2625     return Op;
2626   }
2627 
2628   static ARMOperand *CreateMem(unsigned BaseRegNum,
2629                                const MCConstantExpr *OffsetImm,
2630                                unsigned OffsetRegNum,
2631                                ARM_AM::ShiftOpc ShiftType,
2632                                unsigned ShiftImm,
2633                                unsigned Alignment,
2634                                bool isNegative,
2635                                SMLoc S, SMLoc E,
2636                                SMLoc AlignmentLoc = SMLoc()) {
2637     ARMOperand *Op = new ARMOperand(k_Memory);
2638     Op->Memory.BaseRegNum = BaseRegNum;
2639     Op->Memory.OffsetImm = OffsetImm;
2640     Op->Memory.OffsetRegNum = OffsetRegNum;
2641     Op->Memory.ShiftType = ShiftType;
2642     Op->Memory.ShiftImm = ShiftImm;
2643     Op->Memory.Alignment = Alignment;
2644     Op->Memory.isNegative = isNegative;
2645     Op->StartLoc = S;
2646     Op->EndLoc = E;
2647     Op->AlignmentLoc = AlignmentLoc;
2648     return Op;
2649   }
2650 
2651   static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2652                                       ARM_AM::ShiftOpc ShiftTy,
2653                                       unsigned ShiftImm,
2654                                       SMLoc S, SMLoc E) {
2655     ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2656     Op->PostIdxReg.RegNum = RegNum;
2657     Op->PostIdxReg.isAdd = isAdd;
2658     Op->PostIdxReg.ShiftTy = ShiftTy;
2659     Op->PostIdxReg.ShiftImm = ShiftImm;
2660     Op->StartLoc = S;
2661     Op->EndLoc = E;
2662     return Op;
2663   }
2664 
2665   static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2666     ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2667     Op->MBOpt.Val = Opt;
2668     Op->StartLoc = S;
2669     Op->EndLoc = S;
2670     return Op;
2671   }
2672 
2673   static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2674                                               SMLoc S) {
2675     ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2676     Op->ISBOpt.Val = Opt;
2677     Op->StartLoc = S;
2678     Op->EndLoc = S;
2679     return Op;
2680   }
2681 
2682   static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2683     ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2684     Op->IFlags.Val = IFlags;
2685     Op->StartLoc = S;
2686     Op->EndLoc = S;
2687     return Op;
2688   }
2689 
2690   static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2691     ARMOperand *Op = new ARMOperand(k_MSRMask);
2692     Op->MMask.Val = MMask;
2693     Op->StartLoc = S;
2694     Op->EndLoc = S;
2695     return Op;
2696   }
2697 };
2698 
2699 } // end anonymous namespace.
2700 
2701 void ARMOperand::print(raw_ostream &OS) const {
2702   switch (Kind) {
2703   case k_CondCode:
2704     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2705     break;
2706   case k_CCOut:
2707     OS << "<ccout " << getReg() << ">";
2708     break;
2709   case k_ITCondMask: {
2710     static const char *const MaskStr[] = {
2711       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2712       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2713     };
2714     assert((ITMask.Mask & 0xf) == ITMask.Mask);
2715     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2716     break;
2717   }
2718   case k_CoprocNum:
2719     OS << "<coprocessor number: " << getCoproc() << ">";
2720     break;
2721   case k_CoprocReg:
2722     OS << "<coprocessor register: " << getCoproc() << ">";
2723     break;
2724   case k_CoprocOption:
2725     OS << "<coprocessor option: " << CoprocOption.Val << ">";
2726     break;
2727   case k_MSRMask:
2728     OS << "<mask: " << getMSRMask() << ">";
2729     break;
2730   case k_Immediate:
2731     getImm()->print(OS);
2732     break;
2733   case k_MemBarrierOpt:
2734     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2735     break;
2736   case k_InstSyncBarrierOpt:
2737     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2738     break;
2739   case k_Memory:
2740     OS << "<memory "
2741        << " base:" << Memory.BaseRegNum;
2742     OS << ">";
2743     break;
2744   case k_PostIndexRegister:
2745     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2746        << PostIdxReg.RegNum;
2747     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2748       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2749          << PostIdxReg.ShiftImm;
2750     OS << ">";
2751     break;
2752   case k_ProcIFlags: {
2753     OS << "<ARM_PROC::";
2754     unsigned IFlags = getProcIFlags();
2755     for (int i=2; i >= 0; --i)
2756       if (IFlags & (1 << i))
2757         OS << ARM_PROC::IFlagsToString(1 << i);
2758     OS << ">";
2759     break;
2760   }
2761   case k_Register:
2762     OS << "<register " << getReg() << ">";
2763     break;
2764   case k_ShifterImmediate:
2765     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2766        << " #" << ShifterImm.Imm << ">";
2767     break;
2768   case k_ShiftedRegister:
2769     OS << "<so_reg_reg "
2770        << RegShiftedReg.SrcReg << " "
2771        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2772        << " " << RegShiftedReg.ShiftReg << ">";
2773     break;
2774   case k_ShiftedImmediate:
2775     OS << "<so_reg_imm "
2776        << RegShiftedImm.SrcReg << " "
2777        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2778        << " #" << RegShiftedImm.ShiftImm << ">";
2779     break;
2780   case k_RotateImmediate:
2781     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2782     break;
2783   case k_BitfieldDescriptor:
2784     OS << "<bitfield " << "lsb: " << Bitfield.LSB
2785        << ", width: " << Bitfield.Width << ">";
2786     break;
2787   case k_RegisterList:
2788   case k_DPRRegisterList:
2789   case k_SPRRegisterList: {
2790     OS << "<register_list ";
2791 
2792     const SmallVectorImpl<unsigned> &RegList = getRegList();
2793     for (SmallVectorImpl<unsigned>::const_iterator
2794            I = RegList.begin(), E = RegList.end(); I != E; ) {
2795       OS << *I;
2796       if (++I < E) OS << ", ";
2797     }
2798 
2799     OS << ">";
2800     break;
2801   }
2802   case k_VectorList:
2803     OS << "<vector_list " << VectorList.Count << " * "
2804        << VectorList.RegNum << ">";
2805     break;
2806   case k_VectorListAllLanes:
2807     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2808        << VectorList.RegNum << ">";
2809     break;
2810   case k_VectorListIndexed:
2811     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2812        << VectorList.Count << " * " << VectorList.RegNum << ">";
2813     break;
2814   case k_Token:
2815     OS << "'" << getToken() << "'";
2816     break;
2817   case k_VectorIndex:
2818     OS << "<vectorindex " << getVectorIndex() << ">";
2819     break;
2820   }
2821 }
2822 
2823 /// @name Auto-generated Match Functions
2824 /// {
2825 
2826 static unsigned MatchRegisterName(StringRef Name);
2827 
2828 /// }
2829 
2830 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2831                                  SMLoc &StartLoc, SMLoc &EndLoc) {
2832   StartLoc = Parser.getTok().getLoc();
2833   EndLoc = Parser.getTok().getEndLoc();
2834   RegNo = tryParseRegister();
2835 
2836   return (RegNo == (unsigned)-1);
2837 }
2838 
2839 /// Try to parse a register name.  The token must be an Identifier when called,
2840 /// and if it is a register name the token is eaten and the register number is
2841 /// returned.  Otherwise return -1.
2842 ///
2843 int ARMAsmParser::tryParseRegister() {
2844   const AsmToken &Tok = Parser.getTok();
2845   if (Tok.isNot(AsmToken::Identifier)) return -1;
2846 
2847   std::string lowerCase = Tok.getString().lower();
2848   unsigned RegNum = MatchRegisterName(lowerCase);
2849   if (!RegNum) {
2850     RegNum = StringSwitch<unsigned>(lowerCase)
2851       .Case("r13", ARM::SP)
2852       .Case("r14", ARM::LR)
2853       .Case("r15", ARM::PC)
2854       .Case("ip", ARM::R12)
2855       // Additional register name aliases for 'gas' compatibility.
2856       .Case("a1", ARM::R0)
2857       .Case("a2", ARM::R1)
2858       .Case("a3", ARM::R2)
2859       .Case("a4", ARM::R3)
2860       .Case("v1", ARM::R4)
2861       .Case("v2", ARM::R5)
2862       .Case("v3", ARM::R6)
2863       .Case("v4", ARM::R7)
2864       .Case("v5", ARM::R8)
2865       .Case("v6", ARM::R9)
2866       .Case("v7", ARM::R10)
2867       .Case("v8", ARM::R11)
2868       .Case("sb", ARM::R9)
2869       .Case("sl", ARM::R10)
2870       .Case("fp", ARM::R11)
2871       .Default(0);
2872   }
2873   if (!RegNum) {
2874     // Check for aliases registered via .req. Canonicalize to lower case.
2875     // That's more consistent since register names are case insensitive, and
2876     // it's how the original entry was passed in from MC/MCParser/AsmParser.
2877     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2878     // If no match, return failure.
2879     if (Entry == RegisterReqs.end())
2880       return -1;
2881     Parser.Lex(); // Eat identifier token.
2882     return Entry->getValue();
2883   }
2884 
2885   Parser.Lex(); // Eat identifier token.
2886 
2887   return RegNum;
2888 }
2889 
2890 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2891 // If a recoverable error occurs, return 1. If an irrecoverable error
2892 // occurs, return -1. An irrecoverable error is one where tokens have been
2893 // consumed in the process of trying to parse the shifter (i.e., when it is
2894 // indeed a shifter operand, but malformed).
2895 int ARMAsmParser::tryParseShiftRegister(
2896                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2897   SMLoc S = Parser.getTok().getLoc();
2898   const AsmToken &Tok = Parser.getTok();
2899   if (Tok.isNot(AsmToken::Identifier))
2900     return -1;
2901 
2902   std::string lowerCase = Tok.getString().lower();
2903   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2904       .Case("asl", ARM_AM::lsl)
2905       .Case("lsl", ARM_AM::lsl)
2906       .Case("lsr", ARM_AM::lsr)
2907       .Case("asr", ARM_AM::asr)
2908       .Case("ror", ARM_AM::ror)
2909       .Case("rrx", ARM_AM::rrx)
2910       .Default(ARM_AM::no_shift);
2911 
2912   if (ShiftTy == ARM_AM::no_shift)
2913     return 1;
2914 
2915   Parser.Lex(); // Eat the operator.
2916 
2917   // The source register for the shift has already been added to the
2918   // operand list, so we need to pop it off and combine it into the shifted
2919   // register operand instead.
2920   std::unique_ptr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2921   if (!PrevOp->isReg())
2922     return Error(PrevOp->getStartLoc(), "shift must be of a register");
2923   int SrcReg = PrevOp->getReg();
2924 
2925   SMLoc EndLoc;
2926   int64_t Imm = 0;
2927   int ShiftReg = 0;
2928   if (ShiftTy == ARM_AM::rrx) {
2929     // RRX Doesn't have an explicit shift amount. The encoder expects
2930     // the shift register to be the same as the source register. Seems odd,
2931     // but OK.
2932     ShiftReg = SrcReg;
2933   } else {
2934     // Figure out if this is shifted by a constant or a register (for non-RRX).
2935     if (Parser.getTok().is(AsmToken::Hash) ||
2936         Parser.getTok().is(AsmToken::Dollar)) {
2937       Parser.Lex(); // Eat hash.
2938       SMLoc ImmLoc = Parser.getTok().getLoc();
2939       const MCExpr *ShiftExpr = 0;
2940       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2941         Error(ImmLoc, "invalid immediate shift value");
2942         return -1;
2943       }
2944       // The expression must be evaluatable as an immediate.
2945       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2946       if (!CE) {
2947         Error(ImmLoc, "invalid immediate shift value");
2948         return -1;
2949       }
2950       // Range check the immediate.
2951       // lsl, ror: 0 <= imm <= 31
2952       // lsr, asr: 0 <= imm <= 32
2953       Imm = CE->getValue();
2954       if (Imm < 0 ||
2955           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2956           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2957         Error(ImmLoc, "immediate shift value out of range");
2958         return -1;
2959       }
2960       // shift by zero is a nop. Always send it through as lsl.
2961       // ('as' compatibility)
2962       if (Imm == 0)
2963         ShiftTy = ARM_AM::lsl;
2964     } else if (Parser.getTok().is(AsmToken::Identifier)) {
2965       SMLoc L = Parser.getTok().getLoc();
2966       EndLoc = Parser.getTok().getEndLoc();
2967       ShiftReg = tryParseRegister();
2968       if (ShiftReg == -1) {
2969         Error (L, "expected immediate or register in shift operand");
2970         return -1;
2971       }
2972     } else {
2973       Error (Parser.getTok().getLoc(),
2974                     "expected immediate or register in shift operand");
2975       return -1;
2976     }
2977   }
2978 
2979   if (ShiftReg && ShiftTy != ARM_AM::rrx)
2980     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2981                                                          ShiftReg, Imm,
2982                                                          S, EndLoc));
2983   else
2984     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2985                                                           S, EndLoc));
2986 
2987   return 0;
2988 }
2989 
2990 
2991 /// Try to parse a register name.  The token must be an Identifier when called.
2992 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2993 /// if there is a "writeback". 'true' if it's not a register.
2994 ///
2995 /// TODO this is likely to change to allow different register types and or to
2996 /// parse for a specific register type.
2997 bool ARMAsmParser::
2998 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2999   const AsmToken &RegTok = Parser.getTok();
3000   int RegNo = tryParseRegister();
3001   if (RegNo == -1)
3002     return true;
3003 
3004   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3005                                            RegTok.getEndLoc()));
3006 
3007   const AsmToken &ExclaimTok = Parser.getTok();
3008   if (ExclaimTok.is(AsmToken::Exclaim)) {
3009     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3010                                                ExclaimTok.getLoc()));
3011     Parser.Lex(); // Eat exclaim token
3012     return false;
3013   }
3014 
3015   // Also check for an index operand. This is only legal for vector registers,
3016   // but that'll get caught OK in operand matching, so we don't need to
3017   // explicitly filter everything else out here.
3018   if (Parser.getTok().is(AsmToken::LBrac)) {
3019     SMLoc SIdx = Parser.getTok().getLoc();
3020     Parser.Lex(); // Eat left bracket token.
3021 
3022     const MCExpr *ImmVal;
3023     if (getParser().parseExpression(ImmVal))
3024       return true;
3025     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3026     if (!MCE)
3027       return TokError("immediate value expected for vector index");
3028 
3029     if (Parser.getTok().isNot(AsmToken::RBrac))
3030       return Error(Parser.getTok().getLoc(), "']' expected");
3031 
3032     SMLoc E = Parser.getTok().getEndLoc();
3033     Parser.Lex(); // Eat right bracket token.
3034 
3035     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3036                                                      SIdx, E,
3037                                                      getContext()));
3038   }
3039 
3040   return false;
3041 }
3042 
3043 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3044 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
3045 /// "c5", ...
3046 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3047   // Use the same layout as the tablegen'erated register name matcher. Ugly,
3048   // but efficient.
3049   switch (Name.size()) {
3050   default: return -1;
3051   case 2:
3052     if (Name[0] != CoprocOp)
3053       return -1;
3054     switch (Name[1]) {
3055     default:  return -1;
3056     case '0': return 0;
3057     case '1': return 1;
3058     case '2': return 2;
3059     case '3': return 3;
3060     case '4': return 4;
3061     case '5': return 5;
3062     case '6': return 6;
3063     case '7': return 7;
3064     case '8': return 8;
3065     case '9': return 9;
3066     }
3067   case 3:
3068     if (Name[0] != CoprocOp || Name[1] != '1')
3069       return -1;
3070     switch (Name[2]) {
3071     default:  return -1;
3072     // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
3073     case '0': return CoprocOp == 'p'? -1: 10;
3074     case '1': return CoprocOp == 'p'? -1: 11;
3075     case '2': return 12;
3076     case '3': return 13;
3077     case '4': return 14;
3078     case '5': return 15;
3079     }
3080   }
3081 }
3082 
3083 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3084 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3085 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3086   SMLoc S = Parser.getTok().getLoc();
3087   const AsmToken &Tok = Parser.getTok();
3088   if (!Tok.is(AsmToken::Identifier))
3089     return MatchOperand_NoMatch;
3090   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3091     .Case("eq", ARMCC::EQ)
3092     .Case("ne", ARMCC::NE)
3093     .Case("hs", ARMCC::HS)
3094     .Case("cs", ARMCC::HS)
3095     .Case("lo", ARMCC::LO)
3096     .Case("cc", ARMCC::LO)
3097     .Case("mi", ARMCC::MI)
3098     .Case("pl", ARMCC::PL)
3099     .Case("vs", ARMCC::VS)
3100     .Case("vc", ARMCC::VC)
3101     .Case("hi", ARMCC::HI)
3102     .Case("ls", ARMCC::LS)
3103     .Case("ge", ARMCC::GE)
3104     .Case("lt", ARMCC::LT)
3105     .Case("gt", ARMCC::GT)
3106     .Case("le", ARMCC::LE)
3107     .Case("al", ARMCC::AL)
3108     .Default(~0U);
3109   if (CC == ~0U)
3110     return MatchOperand_NoMatch;
3111   Parser.Lex(); // Eat the token.
3112 
3113   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3114 
3115   return MatchOperand_Success;
3116 }
3117 
3118 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3119 /// token must be an Identifier when called, and if it is a coprocessor
3120 /// number, the token is eaten and the operand is added to the operand list.
3121 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3122 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3123   SMLoc S = Parser.getTok().getLoc();
3124   const AsmToken &Tok = Parser.getTok();
3125   if (Tok.isNot(AsmToken::Identifier))
3126     return MatchOperand_NoMatch;
3127 
3128   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3129   if (Num == -1)
3130     return MatchOperand_NoMatch;
3131 
3132   Parser.Lex(); // Eat identifier token.
3133   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3134   return MatchOperand_Success;
3135 }
3136 
3137 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3138 /// token must be an Identifier when called, and if it is a coprocessor
3139 /// number, the token is eaten and the operand is added to the operand list.
3140 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3141 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3142   SMLoc S = Parser.getTok().getLoc();
3143   const AsmToken &Tok = Parser.getTok();
3144   if (Tok.isNot(AsmToken::Identifier))
3145     return MatchOperand_NoMatch;
3146 
3147   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3148   if (Reg == -1)
3149     return MatchOperand_NoMatch;
3150 
3151   Parser.Lex(); // Eat identifier token.
3152   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3153   return MatchOperand_Success;
3154 }
3155 
3156 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3157 /// coproc_option : '{' imm0_255 '}'
3158 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3159 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3160   SMLoc S = Parser.getTok().getLoc();
3161 
3162   // If this isn't a '{', this isn't a coprocessor immediate operand.
3163   if (Parser.getTok().isNot(AsmToken::LCurly))
3164     return MatchOperand_NoMatch;
3165   Parser.Lex(); // Eat the '{'
3166 
3167   const MCExpr *Expr;
3168   SMLoc Loc = Parser.getTok().getLoc();
3169   if (getParser().parseExpression(Expr)) {
3170     Error(Loc, "illegal expression");
3171     return MatchOperand_ParseFail;
3172   }
3173   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3174   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3175     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3176     return MatchOperand_ParseFail;
3177   }
3178   int Val = CE->getValue();
3179 
3180   // Check for and consume the closing '}'
3181   if (Parser.getTok().isNot(AsmToken::RCurly))
3182     return MatchOperand_ParseFail;
3183   SMLoc E = Parser.getTok().getEndLoc();
3184   Parser.Lex(); // Eat the '}'
3185 
3186   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3187   return MatchOperand_Success;
3188 }
3189 
3190 // For register list parsing, we need to map from raw GPR register numbering
3191 // to the enumeration values. The enumeration values aren't sorted by
3192 // register number due to our using "sp", "lr" and "pc" as canonical names.
3193 static unsigned getNextRegister(unsigned Reg) {
3194   // If this is a GPR, we need to do it manually, otherwise we can rely
3195   // on the sort ordering of the enumeration since the other reg-classes
3196   // are sane.
3197   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3198     return Reg + 1;
3199   switch(Reg) {
3200   default: llvm_unreachable("Invalid GPR number!");
3201   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3202   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3203   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3204   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3205   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3206   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3207   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3208   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3209   }
3210 }
3211 
3212 // Return the low-subreg of a given Q register.
3213 static unsigned getDRegFromQReg(unsigned QReg) {
3214   switch (QReg) {
3215   default: llvm_unreachable("expected a Q register!");
3216   case ARM::Q0:  return ARM::D0;
3217   case ARM::Q1:  return ARM::D2;
3218   case ARM::Q2:  return ARM::D4;
3219   case ARM::Q3:  return ARM::D6;
3220   case ARM::Q4:  return ARM::D8;
3221   case ARM::Q5:  return ARM::D10;
3222   case ARM::Q6:  return ARM::D12;
3223   case ARM::Q7:  return ARM::D14;
3224   case ARM::Q8:  return ARM::D16;
3225   case ARM::Q9:  return ARM::D18;
3226   case ARM::Q10: return ARM::D20;
3227   case ARM::Q11: return ARM::D22;
3228   case ARM::Q12: return ARM::D24;
3229   case ARM::Q13: return ARM::D26;
3230   case ARM::Q14: return ARM::D28;
3231   case ARM::Q15: return ARM::D30;
3232   }
3233 }
3234 
3235 /// Parse a register list.
3236 bool ARMAsmParser::
3237 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3238   assert(Parser.getTok().is(AsmToken::LCurly) &&
3239          "Token is not a Left Curly Brace");
3240   SMLoc S = Parser.getTok().getLoc();
3241   Parser.Lex(); // Eat '{' token.
3242   SMLoc RegLoc = Parser.getTok().getLoc();
3243 
3244   // Check the first register in the list to see what register class
3245   // this is a list of.
3246   int Reg = tryParseRegister();
3247   if (Reg == -1)
3248     return Error(RegLoc, "register expected");
3249 
3250   // The reglist instructions have at most 16 registers, so reserve
3251   // space for that many.
3252   int EReg = 0;
3253   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3254 
3255   // Allow Q regs and just interpret them as the two D sub-registers.
3256   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3257     Reg = getDRegFromQReg(Reg);
3258     EReg = MRI->getEncodingValue(Reg);
3259     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3260     ++Reg;
3261   }
3262   const MCRegisterClass *RC;
3263   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3264     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3265   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3266     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3267   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3268     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3269   else
3270     return Error(RegLoc, "invalid register in register list");
3271 
3272   // Store the register.
3273   EReg = MRI->getEncodingValue(Reg);
3274   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3275 
3276   // This starts immediately after the first register token in the list,
3277   // so we can see either a comma or a minus (range separator) as a legal
3278   // next token.
3279   while (Parser.getTok().is(AsmToken::Comma) ||
3280          Parser.getTok().is(AsmToken::Minus)) {
3281     if (Parser.getTok().is(AsmToken::Minus)) {
3282       Parser.Lex(); // Eat the minus.
3283       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3284       int EndReg = tryParseRegister();
3285       if (EndReg == -1)
3286         return Error(AfterMinusLoc, "register expected");
3287       // Allow Q regs and just interpret them as the two D sub-registers.
3288       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3289         EndReg = getDRegFromQReg(EndReg) + 1;
3290       // If the register is the same as the start reg, there's nothing
3291       // more to do.
3292       if (Reg == EndReg)
3293         continue;
3294       // The register must be in the same register class as the first.
3295       if (!RC->contains(EndReg))
3296         return Error(AfterMinusLoc, "invalid register in register list");
3297       // Ranges must go from low to high.
3298       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3299         return Error(AfterMinusLoc, "bad range in register list");
3300 
3301       // Add all the registers in the range to the register list.
3302       while (Reg != EndReg) {
3303         Reg = getNextRegister(Reg);
3304         EReg = MRI->getEncodingValue(Reg);
3305         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3306       }
3307       continue;
3308     }
3309     Parser.Lex(); // Eat the comma.
3310     RegLoc = Parser.getTok().getLoc();
3311     int OldReg = Reg;
3312     const AsmToken RegTok = Parser.getTok();
3313     Reg = tryParseRegister();
3314     if (Reg == -1)
3315       return Error(RegLoc, "register expected");
3316     // Allow Q regs and just interpret them as the two D sub-registers.
3317     bool isQReg = false;
3318     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3319       Reg = getDRegFromQReg(Reg);
3320       isQReg = true;
3321     }
3322     // The register must be in the same register class as the first.
3323     if (!RC->contains(Reg))
3324       return Error(RegLoc, "invalid register in register list");
3325     // List must be monotonically increasing.
3326     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3327       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3328         Warning(RegLoc, "register list not in ascending order");
3329       else
3330         return Error(RegLoc, "register list not in ascending order");
3331     }
3332     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3333       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3334               ") in register list");
3335       continue;
3336     }
3337     // VFP register lists must also be contiguous.
3338     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3339         Reg != OldReg + 1)
3340       return Error(RegLoc, "non-contiguous register range");
3341     EReg = MRI->getEncodingValue(Reg);
3342     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3343     if (isQReg) {
3344       EReg = MRI->getEncodingValue(++Reg);
3345       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3346     }
3347   }
3348 
3349   if (Parser.getTok().isNot(AsmToken::RCurly))
3350     return Error(Parser.getTok().getLoc(), "'}' expected");
3351   SMLoc E = Parser.getTok().getEndLoc();
3352   Parser.Lex(); // Eat '}' token.
3353 
3354   // Push the register list operand.
3355   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3356 
3357   // The ARM system instruction variants for LDM/STM have a '^' token here.
3358   if (Parser.getTok().is(AsmToken::Caret)) {
3359     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3360     Parser.Lex(); // Eat '^' token.
3361   }
3362 
3363   return false;
3364 }
3365 
3366 // Helper function to parse the lane index for vector lists.
3367 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3368 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3369   Index = 0; // Always return a defined index value.
3370   if (Parser.getTok().is(AsmToken::LBrac)) {
3371     Parser.Lex(); // Eat the '['.
3372     if (Parser.getTok().is(AsmToken::RBrac)) {
3373       // "Dn[]" is the 'all lanes' syntax.
3374       LaneKind = AllLanes;
3375       EndLoc = Parser.getTok().getEndLoc();
3376       Parser.Lex(); // Eat the ']'.
3377       return MatchOperand_Success;
3378     }
3379 
3380     // There's an optional '#' token here. Normally there wouldn't be, but
3381     // inline assemble puts one in, and it's friendly to accept that.
3382     if (Parser.getTok().is(AsmToken::Hash))
3383       Parser.Lex(); // Eat '#' or '$'.
3384 
3385     const MCExpr *LaneIndex;
3386     SMLoc Loc = Parser.getTok().getLoc();
3387     if (getParser().parseExpression(LaneIndex)) {
3388       Error(Loc, "illegal expression");
3389       return MatchOperand_ParseFail;
3390     }
3391     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3392     if (!CE) {
3393       Error(Loc, "lane index must be empty or an integer");
3394       return MatchOperand_ParseFail;
3395     }
3396     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3397       Error(Parser.getTok().getLoc(), "']' expected");
3398       return MatchOperand_ParseFail;
3399     }
3400     EndLoc = Parser.getTok().getEndLoc();
3401     Parser.Lex(); // Eat the ']'.
3402     int64_t Val = CE->getValue();
3403 
3404     // FIXME: Make this range check context sensitive for .8, .16, .32.
3405     if (Val < 0 || Val > 7) {
3406       Error(Parser.getTok().getLoc(), "lane index out of range");
3407       return MatchOperand_ParseFail;
3408     }
3409     Index = Val;
3410     LaneKind = IndexedLane;
3411     return MatchOperand_Success;
3412   }
3413   LaneKind = NoLanes;
3414   return MatchOperand_Success;
3415 }
3416 
3417 // parse a vector register list
3418 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3419 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3420   VectorLaneTy LaneKind;
3421   unsigned LaneIndex;
3422   SMLoc S = Parser.getTok().getLoc();
3423   // As an extension (to match gas), support a plain D register or Q register
3424   // (without encosing curly braces) as a single or double entry list,
3425   // respectively.
3426   if (Parser.getTok().is(AsmToken::Identifier)) {
3427     SMLoc E = Parser.getTok().getEndLoc();
3428     int Reg = tryParseRegister();
3429     if (Reg == -1)
3430       return MatchOperand_NoMatch;
3431     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3432       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3433       if (Res != MatchOperand_Success)
3434         return Res;
3435       switch (LaneKind) {
3436       case NoLanes:
3437         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3438         break;
3439       case AllLanes:
3440         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3441                                                                 S, E));
3442         break;
3443       case IndexedLane:
3444         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3445                                                                LaneIndex,
3446                                                                false, S, E));
3447         break;
3448       }
3449       return MatchOperand_Success;
3450     }
3451     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3452       Reg = getDRegFromQReg(Reg);
3453       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3454       if (Res != MatchOperand_Success)
3455         return Res;
3456       switch (LaneKind) {
3457       case NoLanes:
3458         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3459                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3460         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3461         break;
3462       case AllLanes:
3463         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3464                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3465         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3466                                                                 S, E));
3467         break;
3468       case IndexedLane:
3469         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3470                                                                LaneIndex,
3471                                                                false, S, E));
3472         break;
3473       }
3474       return MatchOperand_Success;
3475     }
3476     Error(S, "vector register expected");
3477     return MatchOperand_ParseFail;
3478   }
3479 
3480   if (Parser.getTok().isNot(AsmToken::LCurly))
3481     return MatchOperand_NoMatch;
3482 
3483   Parser.Lex(); // Eat '{' token.
3484   SMLoc RegLoc = Parser.getTok().getLoc();
3485 
3486   int Reg = tryParseRegister();
3487   if (Reg == -1) {
3488     Error(RegLoc, "register expected");
3489     return MatchOperand_ParseFail;
3490   }
3491   unsigned Count = 1;
3492   int Spacing = 0;
3493   unsigned FirstReg = Reg;
3494   // The list is of D registers, but we also allow Q regs and just interpret
3495   // them as the two D sub-registers.
3496   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3497     FirstReg = Reg = getDRegFromQReg(Reg);
3498     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3499                  // it's ambiguous with four-register single spaced.
3500     ++Reg;
3501     ++Count;
3502   }
3503 
3504   SMLoc E;
3505   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3506     return MatchOperand_ParseFail;
3507 
3508   while (Parser.getTok().is(AsmToken::Comma) ||
3509          Parser.getTok().is(AsmToken::Minus)) {
3510     if (Parser.getTok().is(AsmToken::Minus)) {
3511       if (!Spacing)
3512         Spacing = 1; // Register range implies a single spaced list.
3513       else if (Spacing == 2) {
3514         Error(Parser.getTok().getLoc(),
3515               "sequential registers in double spaced list");
3516         return MatchOperand_ParseFail;
3517       }
3518       Parser.Lex(); // Eat the minus.
3519       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3520       int EndReg = tryParseRegister();
3521       if (EndReg == -1) {
3522         Error(AfterMinusLoc, "register expected");
3523         return MatchOperand_ParseFail;
3524       }
3525       // Allow Q regs and just interpret them as the two D sub-registers.
3526       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3527         EndReg = getDRegFromQReg(EndReg) + 1;
3528       // If the register is the same as the start reg, there's nothing
3529       // more to do.
3530       if (Reg == EndReg)
3531         continue;
3532       // The register must be in the same register class as the first.
3533       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3534         Error(AfterMinusLoc, "invalid register in register list");
3535         return MatchOperand_ParseFail;
3536       }
3537       // Ranges must go from low to high.
3538       if (Reg > EndReg) {
3539         Error(AfterMinusLoc, "bad range in register list");
3540         return MatchOperand_ParseFail;
3541       }
3542       // Parse the lane specifier if present.
3543       VectorLaneTy NextLaneKind;
3544       unsigned NextLaneIndex;
3545       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3546           MatchOperand_Success)
3547         return MatchOperand_ParseFail;
3548       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3549         Error(AfterMinusLoc, "mismatched lane index in register list");
3550         return MatchOperand_ParseFail;
3551       }
3552 
3553       // Add all the registers in the range to the register list.
3554       Count += EndReg - Reg;
3555       Reg = EndReg;
3556       continue;
3557     }
3558     Parser.Lex(); // Eat the comma.
3559     RegLoc = Parser.getTok().getLoc();
3560     int OldReg = Reg;
3561     Reg = tryParseRegister();
3562     if (Reg == -1) {
3563       Error(RegLoc, "register expected");
3564       return MatchOperand_ParseFail;
3565     }
3566     // vector register lists must be contiguous.
3567     // It's OK to use the enumeration values directly here rather, as the
3568     // VFP register classes have the enum sorted properly.
3569     //
3570     // The list is of D registers, but we also allow Q regs and just interpret
3571     // them as the two D sub-registers.
3572     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3573       if (!Spacing)
3574         Spacing = 1; // Register range implies a single spaced list.
3575       else if (Spacing == 2) {
3576         Error(RegLoc,
3577               "invalid register in double-spaced list (must be 'D' register')");
3578         return MatchOperand_ParseFail;
3579       }
3580       Reg = getDRegFromQReg(Reg);
3581       if (Reg != OldReg + 1) {
3582         Error(RegLoc, "non-contiguous register range");
3583         return MatchOperand_ParseFail;
3584       }
3585       ++Reg;
3586       Count += 2;
3587       // Parse the lane specifier if present.
3588       VectorLaneTy NextLaneKind;
3589       unsigned NextLaneIndex;
3590       SMLoc LaneLoc = Parser.getTok().getLoc();
3591       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3592           MatchOperand_Success)
3593         return MatchOperand_ParseFail;
3594       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3595         Error(LaneLoc, "mismatched lane index in register list");
3596         return MatchOperand_ParseFail;
3597       }
3598       continue;
3599     }
3600     // Normal D register.
3601     // Figure out the register spacing (single or double) of the list if
3602     // we don't know it already.
3603     if (!Spacing)
3604       Spacing = 1 + (Reg == OldReg + 2);
3605 
3606     // Just check that it's contiguous and keep going.
3607     if (Reg != OldReg + Spacing) {
3608       Error(RegLoc, "non-contiguous register range");
3609       return MatchOperand_ParseFail;
3610     }
3611     ++Count;
3612     // Parse the lane specifier if present.
3613     VectorLaneTy NextLaneKind;
3614     unsigned NextLaneIndex;
3615     SMLoc EndLoc = Parser.getTok().getLoc();
3616     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3617       return MatchOperand_ParseFail;
3618     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3619       Error(EndLoc, "mismatched lane index in register list");
3620       return MatchOperand_ParseFail;
3621     }
3622   }
3623 
3624   if (Parser.getTok().isNot(AsmToken::RCurly)) {
3625     Error(Parser.getTok().getLoc(), "'}' expected");
3626     return MatchOperand_ParseFail;
3627   }
3628   E = Parser.getTok().getEndLoc();
3629   Parser.Lex(); // Eat '}' token.
3630 
3631   switch (LaneKind) {
3632   case NoLanes:
3633     // Two-register operands have been converted to the
3634     // composite register classes.
3635     if (Count == 2) {
3636       const MCRegisterClass *RC = (Spacing == 1) ?
3637         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3638         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3639       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3640     }
3641 
3642     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3643                                                     (Spacing == 2), S, E));
3644     break;
3645   case AllLanes:
3646     // Two-register operands have been converted to the
3647     // composite register classes.
3648     if (Count == 2) {
3649       const MCRegisterClass *RC = (Spacing == 1) ?
3650         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3651         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3652       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3653     }
3654     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3655                                                             (Spacing == 2),
3656                                                             S, E));
3657     break;
3658   case IndexedLane:
3659     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3660                                                            LaneIndex,
3661                                                            (Spacing == 2),
3662                                                            S, E));
3663     break;
3664   }
3665   return MatchOperand_Success;
3666 }
3667 
3668 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3669 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3670 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3671   SMLoc S = Parser.getTok().getLoc();
3672   const AsmToken &Tok = Parser.getTok();
3673   unsigned Opt;
3674 
3675   if (Tok.is(AsmToken::Identifier)) {
3676     StringRef OptStr = Tok.getString();
3677 
3678     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3679       .Case("sy",    ARM_MB::SY)
3680       .Case("st",    ARM_MB::ST)
3681       .Case("ld",    ARM_MB::LD)
3682       .Case("sh",    ARM_MB::ISH)
3683       .Case("ish",   ARM_MB::ISH)
3684       .Case("shst",  ARM_MB::ISHST)
3685       .Case("ishst", ARM_MB::ISHST)
3686       .Case("ishld", ARM_MB::ISHLD)
3687       .Case("nsh",   ARM_MB::NSH)
3688       .Case("un",    ARM_MB::NSH)
3689       .Case("nshst", ARM_MB::NSHST)
3690       .Case("nshld", ARM_MB::NSHLD)
3691       .Case("unst",  ARM_MB::NSHST)
3692       .Case("osh",   ARM_MB::OSH)
3693       .Case("oshst", ARM_MB::OSHST)
3694       .Case("oshld", ARM_MB::OSHLD)
3695       .Default(~0U);
3696 
3697     // ishld, oshld, nshld and ld are only available from ARMv8.
3698     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3699                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3700       Opt = ~0U;
3701 
3702     if (Opt == ~0U)
3703       return MatchOperand_NoMatch;
3704 
3705     Parser.Lex(); // Eat identifier token.
3706   } else if (Tok.is(AsmToken::Hash) ||
3707              Tok.is(AsmToken::Dollar) ||
3708              Tok.is(AsmToken::Integer)) {
3709     if (Parser.getTok().isNot(AsmToken::Integer))
3710       Parser.Lex(); // Eat '#' or '$'.
3711     SMLoc Loc = Parser.getTok().getLoc();
3712 
3713     const MCExpr *MemBarrierID;
3714     if (getParser().parseExpression(MemBarrierID)) {
3715       Error(Loc, "illegal expression");
3716       return MatchOperand_ParseFail;
3717     }
3718 
3719     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3720     if (!CE) {
3721       Error(Loc, "constant expression expected");
3722       return MatchOperand_ParseFail;
3723     }
3724 
3725     int Val = CE->getValue();
3726     if (Val & ~0xf) {
3727       Error(Loc, "immediate value out of range");
3728       return MatchOperand_ParseFail;
3729     }
3730 
3731     Opt = ARM_MB::RESERVED_0 + Val;
3732   } else
3733     return MatchOperand_ParseFail;
3734 
3735   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3736   return MatchOperand_Success;
3737 }
3738 
3739 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3740 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3741 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3742   SMLoc S = Parser.getTok().getLoc();
3743   const AsmToken &Tok = Parser.getTok();
3744   unsigned Opt;
3745 
3746   if (Tok.is(AsmToken::Identifier)) {
3747     StringRef OptStr = Tok.getString();
3748 
3749     if (OptStr.equals_lower("sy"))
3750       Opt = ARM_ISB::SY;
3751     else
3752       return MatchOperand_NoMatch;
3753 
3754     Parser.Lex(); // Eat identifier token.
3755   } else if (Tok.is(AsmToken::Hash) ||
3756              Tok.is(AsmToken::Dollar) ||
3757              Tok.is(AsmToken::Integer)) {
3758     if (Parser.getTok().isNot(AsmToken::Integer))
3759       Parser.Lex(); // Eat '#' or '$'.
3760     SMLoc Loc = Parser.getTok().getLoc();
3761 
3762     const MCExpr *ISBarrierID;
3763     if (getParser().parseExpression(ISBarrierID)) {
3764       Error(Loc, "illegal expression");
3765       return MatchOperand_ParseFail;
3766     }
3767 
3768     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3769     if (!CE) {
3770       Error(Loc, "constant expression expected");
3771       return MatchOperand_ParseFail;
3772     }
3773 
3774     int Val = CE->getValue();
3775     if (Val & ~0xf) {
3776       Error(Loc, "immediate value out of range");
3777       return MatchOperand_ParseFail;
3778     }
3779 
3780     Opt = ARM_ISB::RESERVED_0 + Val;
3781   } else
3782     return MatchOperand_ParseFail;
3783 
3784   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3785           (ARM_ISB::InstSyncBOpt)Opt, S));
3786   return MatchOperand_Success;
3787 }
3788 
3789 
3790 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3791 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3792 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3793   SMLoc S = Parser.getTok().getLoc();
3794   const AsmToken &Tok = Parser.getTok();
3795   if (!Tok.is(AsmToken::Identifier))
3796     return MatchOperand_NoMatch;
3797   StringRef IFlagsStr = Tok.getString();
3798 
3799   // An iflags string of "none" is interpreted to mean that none of the AIF
3800   // bits are set.  Not a terribly useful instruction, but a valid encoding.
3801   unsigned IFlags = 0;
3802   if (IFlagsStr != "none") {
3803         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3804       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3805         .Case("a", ARM_PROC::A)
3806         .Case("i", ARM_PROC::I)
3807         .Case("f", ARM_PROC::F)
3808         .Default(~0U);
3809 
3810       // If some specific iflag is already set, it means that some letter is
3811       // present more than once, this is not acceptable.
3812       if (Flag == ~0U || (IFlags & Flag))
3813         return MatchOperand_NoMatch;
3814 
3815       IFlags |= Flag;
3816     }
3817   }
3818 
3819   Parser.Lex(); // Eat identifier token.
3820   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3821   return MatchOperand_Success;
3822 }
3823 
3824 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3825 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3826 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3827   SMLoc S = Parser.getTok().getLoc();
3828   const AsmToken &Tok = Parser.getTok();
3829   if (!Tok.is(AsmToken::Identifier))
3830     return MatchOperand_NoMatch;
3831   StringRef Mask = Tok.getString();
3832 
3833   if (isMClass()) {
3834     // See ARMv6-M 10.1.1
3835     std::string Name = Mask.lower();
3836     unsigned FlagsVal = StringSwitch<unsigned>(Name)
3837       // Note: in the documentation:
3838       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3839       //  for MSR APSR_nzcvq.
3840       // but we do make it an alias here.  This is so to get the "mask encoding"
3841       // bits correct on MSR APSR writes.
3842       //
3843       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3844       // should really only be allowed when writing a special register.  Note
3845       // they get dropped in the MRS instruction reading a special register as
3846       // the SYSm field is only 8 bits.
3847       //
3848       // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3849       // includes the DSP extension but that is not checked.
3850       .Case("apsr", 0x800)
3851       .Case("apsr_nzcvq", 0x800)
3852       .Case("apsr_g", 0x400)
3853       .Case("apsr_nzcvqg", 0xc00)
3854       .Case("iapsr", 0x801)
3855       .Case("iapsr_nzcvq", 0x801)
3856       .Case("iapsr_g", 0x401)
3857       .Case("iapsr_nzcvqg", 0xc01)
3858       .Case("eapsr", 0x802)
3859       .Case("eapsr_nzcvq", 0x802)
3860       .Case("eapsr_g", 0x402)
3861       .Case("eapsr_nzcvqg", 0xc02)
3862       .Case("xpsr", 0x803)
3863       .Case("xpsr_nzcvq", 0x803)
3864       .Case("xpsr_g", 0x403)
3865       .Case("xpsr_nzcvqg", 0xc03)
3866       .Case("ipsr", 0x805)
3867       .Case("epsr", 0x806)
3868       .Case("iepsr", 0x807)
3869       .Case("msp", 0x808)
3870       .Case("psp", 0x809)
3871       .Case("primask", 0x810)
3872       .Case("basepri", 0x811)
3873       .Case("basepri_max", 0x812)
3874       .Case("faultmask", 0x813)
3875       .Case("control", 0x814)
3876       .Default(~0U);
3877 
3878     if (FlagsVal == ~0U)
3879       return MatchOperand_NoMatch;
3880 
3881     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3882       // basepri, basepri_max and faultmask only valid for V7m.
3883       return MatchOperand_NoMatch;
3884 
3885     Parser.Lex(); // Eat identifier token.
3886     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3887     return MatchOperand_Success;
3888   }
3889 
3890   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3891   size_t Start = 0, Next = Mask.find('_');
3892   StringRef Flags = "";
3893   std::string SpecReg = Mask.slice(Start, Next).lower();
3894   if (Next != StringRef::npos)
3895     Flags = Mask.slice(Next+1, Mask.size());
3896 
3897   // FlagsVal contains the complete mask:
3898   // 3-0: Mask
3899   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3900   unsigned FlagsVal = 0;
3901 
3902   if (SpecReg == "apsr") {
3903     FlagsVal = StringSwitch<unsigned>(Flags)
3904     .Case("nzcvq",  0x8) // same as CPSR_f
3905     .Case("g",      0x4) // same as CPSR_s
3906     .Case("nzcvqg", 0xc) // same as CPSR_fs
3907     .Default(~0U);
3908 
3909     if (FlagsVal == ~0U) {
3910       if (!Flags.empty())
3911         return MatchOperand_NoMatch;
3912       else
3913         FlagsVal = 8; // No flag
3914     }
3915   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3916     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3917     if (Flags == "all" || Flags == "")
3918       Flags = "fc";
3919     for (int i = 0, e = Flags.size(); i != e; ++i) {
3920       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3921       .Case("c", 1)
3922       .Case("x", 2)
3923       .Case("s", 4)
3924       .Case("f", 8)
3925       .Default(~0U);
3926 
3927       // If some specific flag is already set, it means that some letter is
3928       // present more than once, this is not acceptable.
3929       if (FlagsVal == ~0U || (FlagsVal & Flag))
3930         return MatchOperand_NoMatch;
3931       FlagsVal |= Flag;
3932     }
3933   } else // No match for special register.
3934     return MatchOperand_NoMatch;
3935 
3936   // Special register without flags is NOT equivalent to "fc" flags.
3937   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3938   // two lines would enable gas compatibility at the expense of breaking
3939   // round-tripping.
3940   //
3941   // if (!FlagsVal)
3942   //  FlagsVal = 0x9;
3943 
3944   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3945   if (SpecReg == "spsr")
3946     FlagsVal |= 16;
3947 
3948   Parser.Lex(); // Eat identifier token.
3949   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3950   return MatchOperand_Success;
3951 }
3952 
3953 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3954 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3955             int Low, int High) {
3956   const AsmToken &Tok = Parser.getTok();
3957   if (Tok.isNot(AsmToken::Identifier)) {
3958     Error(Parser.getTok().getLoc(), Op + " operand expected.");
3959     return MatchOperand_ParseFail;
3960   }
3961   StringRef ShiftName = Tok.getString();
3962   std::string LowerOp = Op.lower();
3963   std::string UpperOp = Op.upper();
3964   if (ShiftName != LowerOp && ShiftName != UpperOp) {
3965     Error(Parser.getTok().getLoc(), Op + " operand expected.");
3966     return MatchOperand_ParseFail;
3967   }
3968   Parser.Lex(); // Eat shift type token.
3969 
3970   // There must be a '#' and a shift amount.
3971   if (Parser.getTok().isNot(AsmToken::Hash) &&
3972       Parser.getTok().isNot(AsmToken::Dollar)) {
3973     Error(Parser.getTok().getLoc(), "'#' expected");
3974     return MatchOperand_ParseFail;
3975   }
3976   Parser.Lex(); // Eat hash token.
3977 
3978   const MCExpr *ShiftAmount;
3979   SMLoc Loc = Parser.getTok().getLoc();
3980   SMLoc EndLoc;
3981   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3982     Error(Loc, "illegal expression");
3983     return MatchOperand_ParseFail;
3984   }
3985   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3986   if (!CE) {
3987     Error(Loc, "constant expression expected");
3988     return MatchOperand_ParseFail;
3989   }
3990   int Val = CE->getValue();
3991   if (Val < Low || Val > High) {
3992     Error(Loc, "immediate value out of range");
3993     return MatchOperand_ParseFail;
3994   }
3995 
3996   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3997 
3998   return MatchOperand_Success;
3999 }
4000 
4001 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4002 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4003   const AsmToken &Tok = Parser.getTok();
4004   SMLoc S = Tok.getLoc();
4005   if (Tok.isNot(AsmToken::Identifier)) {
4006     Error(S, "'be' or 'le' operand expected");
4007     return MatchOperand_ParseFail;
4008   }
4009   int Val = StringSwitch<int>(Tok.getString().lower())
4010     .Case("be", 1)
4011     .Case("le", 0)
4012     .Default(-1);
4013   Parser.Lex(); // Eat the token.
4014 
4015   if (Val == -1) {
4016     Error(S, "'be' or 'le' operand expected");
4017     return MatchOperand_ParseFail;
4018   }
4019   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4020                                                                   getContext()),
4021                                            S, Tok.getEndLoc()));
4022   return MatchOperand_Success;
4023 }
4024 
4025 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4026 /// instructions. Legal values are:
4027 ///     lsl #n  'n' in [0,31]
4028 ///     asr #n  'n' in [1,32]
4029 ///             n == 32 encoded as n == 0.
4030 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4031 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4032   const AsmToken &Tok = Parser.getTok();
4033   SMLoc S = Tok.getLoc();
4034   if (Tok.isNot(AsmToken::Identifier)) {
4035     Error(S, "shift operator 'asr' or 'lsl' expected");
4036     return MatchOperand_ParseFail;
4037   }
4038   StringRef ShiftName = Tok.getString();
4039   bool isASR;
4040   if (ShiftName == "lsl" || ShiftName == "LSL")
4041     isASR = false;
4042   else if (ShiftName == "asr" || ShiftName == "ASR")
4043     isASR = true;
4044   else {
4045     Error(S, "shift operator 'asr' or 'lsl' expected");
4046     return MatchOperand_ParseFail;
4047   }
4048   Parser.Lex(); // Eat the operator.
4049 
4050   // A '#' and a shift amount.
4051   if (Parser.getTok().isNot(AsmToken::Hash) &&
4052       Parser.getTok().isNot(AsmToken::Dollar)) {
4053     Error(Parser.getTok().getLoc(), "'#' expected");
4054     return MatchOperand_ParseFail;
4055   }
4056   Parser.Lex(); // Eat hash token.
4057   SMLoc ExLoc = Parser.getTok().getLoc();
4058 
4059   const MCExpr *ShiftAmount;
4060   SMLoc EndLoc;
4061   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4062     Error(ExLoc, "malformed shift expression");
4063     return MatchOperand_ParseFail;
4064   }
4065   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4066   if (!CE) {
4067     Error(ExLoc, "shift amount must be an immediate");
4068     return MatchOperand_ParseFail;
4069   }
4070 
4071   int64_t Val = CE->getValue();
4072   if (isASR) {
4073     // Shift amount must be in [1,32]
4074     if (Val < 1 || Val > 32) {
4075       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4076       return MatchOperand_ParseFail;
4077     }
4078     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4079     if (isThumb() && Val == 32) {
4080       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4081       return MatchOperand_ParseFail;
4082     }
4083     if (Val == 32) Val = 0;
4084   } else {
4085     // Shift amount must be in [1,32]
4086     if (Val < 0 || Val > 31) {
4087       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4088       return MatchOperand_ParseFail;
4089     }
4090   }
4091 
4092   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4093 
4094   return MatchOperand_Success;
4095 }
4096 
4097 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4098 /// of instructions. Legal values are:
4099 ///     ror #n  'n' in {0, 8, 16, 24}
4100 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4101 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4102   const AsmToken &Tok = Parser.getTok();
4103   SMLoc S = Tok.getLoc();
4104   if (Tok.isNot(AsmToken::Identifier))
4105     return MatchOperand_NoMatch;
4106   StringRef ShiftName = Tok.getString();
4107   if (ShiftName != "ror" && ShiftName != "ROR")
4108     return MatchOperand_NoMatch;
4109   Parser.Lex(); // Eat the operator.
4110 
4111   // A '#' and a rotate amount.
4112   if (Parser.getTok().isNot(AsmToken::Hash) &&
4113       Parser.getTok().isNot(AsmToken::Dollar)) {
4114     Error(Parser.getTok().getLoc(), "'#' expected");
4115     return MatchOperand_ParseFail;
4116   }
4117   Parser.Lex(); // Eat hash token.
4118   SMLoc ExLoc = Parser.getTok().getLoc();
4119 
4120   const MCExpr *ShiftAmount;
4121   SMLoc EndLoc;
4122   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4123     Error(ExLoc, "malformed rotate expression");
4124     return MatchOperand_ParseFail;
4125   }
4126   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4127   if (!CE) {
4128     Error(ExLoc, "rotate amount must be an immediate");
4129     return MatchOperand_ParseFail;
4130   }
4131 
4132   int64_t Val = CE->getValue();
4133   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4134   // normally, zero is represented in asm by omitting the rotate operand
4135   // entirely.
4136   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4137     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4138     return MatchOperand_ParseFail;
4139   }
4140 
4141   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4142 
4143   return MatchOperand_Success;
4144 }
4145 
4146 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4147 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4148   SMLoc S = Parser.getTok().getLoc();
4149   // The bitfield descriptor is really two operands, the LSB and the width.
4150   if (Parser.getTok().isNot(AsmToken::Hash) &&
4151       Parser.getTok().isNot(AsmToken::Dollar)) {
4152     Error(Parser.getTok().getLoc(), "'#' expected");
4153     return MatchOperand_ParseFail;
4154   }
4155   Parser.Lex(); // Eat hash token.
4156 
4157   const MCExpr *LSBExpr;
4158   SMLoc E = Parser.getTok().getLoc();
4159   if (getParser().parseExpression(LSBExpr)) {
4160     Error(E, "malformed immediate expression");
4161     return MatchOperand_ParseFail;
4162   }
4163   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4164   if (!CE) {
4165     Error(E, "'lsb' operand must be an immediate");
4166     return MatchOperand_ParseFail;
4167   }
4168 
4169   int64_t LSB = CE->getValue();
4170   // The LSB must be in the range [0,31]
4171   if (LSB < 0 || LSB > 31) {
4172     Error(E, "'lsb' operand must be in the range [0,31]");
4173     return MatchOperand_ParseFail;
4174   }
4175   E = Parser.getTok().getLoc();
4176 
4177   // Expect another immediate operand.
4178   if (Parser.getTok().isNot(AsmToken::Comma)) {
4179     Error(Parser.getTok().getLoc(), "too few operands");
4180     return MatchOperand_ParseFail;
4181   }
4182   Parser.Lex(); // Eat hash token.
4183   if (Parser.getTok().isNot(AsmToken::Hash) &&
4184       Parser.getTok().isNot(AsmToken::Dollar)) {
4185     Error(Parser.getTok().getLoc(), "'#' expected");
4186     return MatchOperand_ParseFail;
4187   }
4188   Parser.Lex(); // Eat hash token.
4189 
4190   const MCExpr *WidthExpr;
4191   SMLoc EndLoc;
4192   if (getParser().parseExpression(WidthExpr, EndLoc)) {
4193     Error(E, "malformed immediate expression");
4194     return MatchOperand_ParseFail;
4195   }
4196   CE = dyn_cast<MCConstantExpr>(WidthExpr);
4197   if (!CE) {
4198     Error(E, "'width' operand must be an immediate");
4199     return MatchOperand_ParseFail;
4200   }
4201 
4202   int64_t Width = CE->getValue();
4203   // The LSB must be in the range [1,32-lsb]
4204   if (Width < 1 || Width > 32 - LSB) {
4205     Error(E, "'width' operand must be in the range [1,32-lsb]");
4206     return MatchOperand_ParseFail;
4207   }
4208 
4209   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4210 
4211   return MatchOperand_Success;
4212 }
4213 
4214 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4215 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4216   // Check for a post-index addressing register operand. Specifically:
4217   // postidx_reg := '+' register {, shift}
4218   //              | '-' register {, shift}
4219   //              | register {, shift}
4220 
4221   // This method must return MatchOperand_NoMatch without consuming any tokens
4222   // in the case where there is no match, as other alternatives take other
4223   // parse methods.
4224   AsmToken Tok = Parser.getTok();
4225   SMLoc S = Tok.getLoc();
4226   bool haveEaten = false;
4227   bool isAdd = true;
4228   if (Tok.is(AsmToken::Plus)) {
4229     Parser.Lex(); // Eat the '+' token.
4230     haveEaten = true;
4231   } else if (Tok.is(AsmToken::Minus)) {
4232     Parser.Lex(); // Eat the '-' token.
4233     isAdd = false;
4234     haveEaten = true;
4235   }
4236 
4237   SMLoc E = Parser.getTok().getEndLoc();
4238   int Reg = tryParseRegister();
4239   if (Reg == -1) {
4240     if (!haveEaten)
4241       return MatchOperand_NoMatch;
4242     Error(Parser.getTok().getLoc(), "register expected");
4243     return MatchOperand_ParseFail;
4244   }
4245 
4246   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4247   unsigned ShiftImm = 0;
4248   if (Parser.getTok().is(AsmToken::Comma)) {
4249     Parser.Lex(); // Eat the ','.
4250     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4251       return MatchOperand_ParseFail;
4252 
4253     // FIXME: Only approximates end...may include intervening whitespace.
4254     E = Parser.getTok().getLoc();
4255   }
4256 
4257   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4258                                                   ShiftImm, S, E));
4259 
4260   return MatchOperand_Success;
4261 }
4262 
4263 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4264 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4265   // Check for a post-index addressing register operand. Specifically:
4266   // am3offset := '+' register
4267   //              | '-' register
4268   //              | register
4269   //              | # imm
4270   //              | # + imm
4271   //              | # - imm
4272 
4273   // This method must return MatchOperand_NoMatch without consuming any tokens
4274   // in the case where there is no match, as other alternatives take other
4275   // parse methods.
4276   AsmToken Tok = Parser.getTok();
4277   SMLoc S = Tok.getLoc();
4278 
4279   // Do immediates first, as we always parse those if we have a '#'.
4280   if (Parser.getTok().is(AsmToken::Hash) ||
4281       Parser.getTok().is(AsmToken::Dollar)) {
4282     Parser.Lex(); // Eat '#' or '$'.
4283     // Explicitly look for a '-', as we need to encode negative zero
4284     // differently.
4285     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4286     const MCExpr *Offset;
4287     SMLoc E;
4288     if (getParser().parseExpression(Offset, E))
4289       return MatchOperand_ParseFail;
4290     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4291     if (!CE) {
4292       Error(S, "constant expression expected");
4293       return MatchOperand_ParseFail;
4294     }
4295     // Negative zero is encoded as the flag value INT32_MIN.
4296     int32_t Val = CE->getValue();
4297     if (isNegative && Val == 0)
4298       Val = INT32_MIN;
4299 
4300     Operands.push_back(
4301       ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4302 
4303     return MatchOperand_Success;
4304   }
4305 
4306 
4307   bool haveEaten = false;
4308   bool isAdd = true;
4309   if (Tok.is(AsmToken::Plus)) {
4310     Parser.Lex(); // Eat the '+' token.
4311     haveEaten = true;
4312   } else if (Tok.is(AsmToken::Minus)) {
4313     Parser.Lex(); // Eat the '-' token.
4314     isAdd = false;
4315     haveEaten = true;
4316   }
4317 
4318   Tok = Parser.getTok();
4319   int Reg = tryParseRegister();
4320   if (Reg == -1) {
4321     if (!haveEaten)
4322       return MatchOperand_NoMatch;
4323     Error(Tok.getLoc(), "register expected");
4324     return MatchOperand_ParseFail;
4325   }
4326 
4327   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4328                                                   0, S, Tok.getEndLoc()));
4329 
4330   return MatchOperand_Success;
4331 }
4332 
4333 /// Convert parsed operands to MCInst.  Needed here because this instruction
4334 /// only has two register operands, but multiplication is commutative so
4335 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4336 void ARMAsmParser::
4337 cvtThumbMultiply(MCInst &Inst,
4338            const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4339   ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4340   ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4341   // If we have a three-operand form, make sure to set Rn to be the operand
4342   // that isn't the same as Rd.
4343   unsigned RegOp = 4;
4344   if (Operands.size() == 6 &&
4345       ((ARMOperand*)Operands[4])->getReg() ==
4346         ((ARMOperand*)Operands[3])->getReg())
4347     RegOp = 5;
4348   ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4349   Inst.addOperand(Inst.getOperand(0));
4350   ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4351 }
4352 
4353 void ARMAsmParser::
4354 cvtThumbBranches(MCInst &Inst,
4355            const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4356   int CondOp = -1, ImmOp = -1;
4357   switch(Inst.getOpcode()) {
4358     case ARM::tB:
4359     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4360 
4361     case ARM::t2B:
4362     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4363 
4364     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4365   }
4366   // first decide whether or not the branch should be conditional
4367   // by looking at it's location relative to an IT block
4368   if(inITBlock()) {
4369     // inside an IT block we cannot have any conditional branches. any
4370     // such instructions needs to be converted to unconditional form
4371     switch(Inst.getOpcode()) {
4372       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4373       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4374     }
4375   } else {
4376     // outside IT blocks we can only have unconditional branches with AL
4377     // condition code or conditional branches with non-AL condition code
4378     unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4379     switch(Inst.getOpcode()) {
4380       case ARM::tB:
4381       case ARM::tBcc:
4382         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4383         break;
4384       case ARM::t2B:
4385       case ARM::t2Bcc:
4386         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4387         break;
4388     }
4389   }
4390 
4391   // now decide on encoding size based on branch target range
4392   switch(Inst.getOpcode()) {
4393     // classify tB as either t2B or t1B based on range of immediate operand
4394     case ARM::tB: {
4395       ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4396       if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4397         Inst.setOpcode(ARM::t2B);
4398       break;
4399     }
4400     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4401     case ARM::tBcc: {
4402       ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4403       if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4404         Inst.setOpcode(ARM::t2Bcc);
4405       break;
4406     }
4407   }
4408   ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4409   ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4410 }
4411 
4412 /// Parse an ARM memory expression, return false if successful else return true
4413 /// or an error.  The first token must be a '[' when called.
4414 bool ARMAsmParser::
4415 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4416   SMLoc S, E;
4417   assert(Parser.getTok().is(AsmToken::LBrac) &&
4418          "Token is not a Left Bracket");
4419   S = Parser.getTok().getLoc();
4420   Parser.Lex(); // Eat left bracket token.
4421 
4422   const AsmToken &BaseRegTok = Parser.getTok();
4423   int BaseRegNum = tryParseRegister();
4424   if (BaseRegNum == -1)
4425     return Error(BaseRegTok.getLoc(), "register expected");
4426 
4427   // The next token must either be a comma, a colon or a closing bracket.
4428   const AsmToken &Tok = Parser.getTok();
4429   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4430       !Tok.is(AsmToken::RBrac))
4431     return Error(Tok.getLoc(), "malformed memory operand");
4432 
4433   if (Tok.is(AsmToken::RBrac)) {
4434     E = Tok.getEndLoc();
4435     Parser.Lex(); // Eat right bracket token.
4436 
4437     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4438                                              0, 0, false, S, E));
4439 
4440     // If there's a pre-indexing writeback marker, '!', just add it as a token
4441     // operand. It's rather odd, but syntactically valid.
4442     if (Parser.getTok().is(AsmToken::Exclaim)) {
4443       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4444       Parser.Lex(); // Eat the '!'.
4445     }
4446 
4447     return false;
4448   }
4449 
4450   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4451          "Lost colon or comma in memory operand?!");
4452   if (Tok.is(AsmToken::Comma)) {
4453     Parser.Lex(); // Eat the comma.
4454   }
4455 
4456   // If we have a ':', it's an alignment specifier.
4457   if (Parser.getTok().is(AsmToken::Colon)) {
4458     Parser.Lex(); // Eat the ':'.
4459     E = Parser.getTok().getLoc();
4460     SMLoc AlignmentLoc = Tok.getLoc();
4461 
4462     const MCExpr *Expr;
4463     if (getParser().parseExpression(Expr))
4464      return true;
4465 
4466     // The expression has to be a constant. Memory references with relocations
4467     // don't come through here, as they use the <label> forms of the relevant
4468     // instructions.
4469     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4470     if (!CE)
4471       return Error (E, "constant expression expected");
4472 
4473     unsigned Align = 0;
4474     switch (CE->getValue()) {
4475     default:
4476       return Error(E,
4477                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4478     case 16:  Align = 2; break;
4479     case 32:  Align = 4; break;
4480     case 64:  Align = 8; break;
4481     case 128: Align = 16; break;
4482     case 256: Align = 32; break;
4483     }
4484 
4485     // Now we should have the closing ']'
4486     if (Parser.getTok().isNot(AsmToken::RBrac))
4487       return Error(Parser.getTok().getLoc(), "']' expected");
4488     E = Parser.getTok().getEndLoc();
4489     Parser.Lex(); // Eat right bracket token.
4490 
4491     // Don't worry about range checking the value here. That's handled by
4492     // the is*() predicates.
4493     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4494                                              ARM_AM::no_shift, 0, Align,
4495                                              false, S, E, AlignmentLoc));
4496 
4497     // If there's a pre-indexing writeback marker, '!', just add it as a token
4498     // operand.
4499     if (Parser.getTok().is(AsmToken::Exclaim)) {
4500       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4501       Parser.Lex(); // Eat the '!'.
4502     }
4503 
4504     return false;
4505   }
4506 
4507   // If we have a '#', it's an immediate offset, else assume it's a register
4508   // offset. Be friendly and also accept a plain integer (without a leading
4509   // hash) for gas compatibility.
4510   if (Parser.getTok().is(AsmToken::Hash) ||
4511       Parser.getTok().is(AsmToken::Dollar) ||
4512       Parser.getTok().is(AsmToken::Integer)) {
4513     if (Parser.getTok().isNot(AsmToken::Integer))
4514       Parser.Lex(); // Eat '#' or '$'.
4515     E = Parser.getTok().getLoc();
4516 
4517     bool isNegative = getParser().getTok().is(AsmToken::Minus);
4518     const MCExpr *Offset;
4519     if (getParser().parseExpression(Offset))
4520      return true;
4521 
4522     // The expression has to be a constant. Memory references with relocations
4523     // don't come through here, as they use the <label> forms of the relevant
4524     // instructions.
4525     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4526     if (!CE)
4527       return Error (E, "constant expression expected");
4528 
4529     // If the constant was #-0, represent it as INT32_MIN.
4530     int32_t Val = CE->getValue();
4531     if (isNegative && Val == 0)
4532       CE = MCConstantExpr::Create(INT32_MIN, getContext());
4533 
4534     // Now we should have the closing ']'
4535     if (Parser.getTok().isNot(AsmToken::RBrac))
4536       return Error(Parser.getTok().getLoc(), "']' expected");
4537     E = Parser.getTok().getEndLoc();
4538     Parser.Lex(); // Eat right bracket token.
4539 
4540     // Don't worry about range checking the value here. That's handled by
4541     // the is*() predicates.
4542     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4543                                              ARM_AM::no_shift, 0, 0,
4544                                              false, S, E));
4545 
4546     // If there's a pre-indexing writeback marker, '!', just add it as a token
4547     // operand.
4548     if (Parser.getTok().is(AsmToken::Exclaim)) {
4549       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4550       Parser.Lex(); // Eat the '!'.
4551     }
4552 
4553     return false;
4554   }
4555 
4556   // The register offset is optionally preceded by a '+' or '-'
4557   bool isNegative = false;
4558   if (Parser.getTok().is(AsmToken::Minus)) {
4559     isNegative = true;
4560     Parser.Lex(); // Eat the '-'.
4561   } else if (Parser.getTok().is(AsmToken::Plus)) {
4562     // Nothing to do.
4563     Parser.Lex(); // Eat the '+'.
4564   }
4565 
4566   E = Parser.getTok().getLoc();
4567   int OffsetRegNum = tryParseRegister();
4568   if (OffsetRegNum == -1)
4569     return Error(E, "register expected");
4570 
4571   // If there's a shift operator, handle it.
4572   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4573   unsigned ShiftImm = 0;
4574   if (Parser.getTok().is(AsmToken::Comma)) {
4575     Parser.Lex(); // Eat the ','.
4576     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4577       return true;
4578   }
4579 
4580   // Now we should have the closing ']'
4581   if (Parser.getTok().isNot(AsmToken::RBrac))
4582     return Error(Parser.getTok().getLoc(), "']' expected");
4583   E = Parser.getTok().getEndLoc();
4584   Parser.Lex(); // Eat right bracket token.
4585 
4586   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4587                                            ShiftType, ShiftImm, 0, isNegative,
4588                                            S, E));
4589 
4590   // If there's a pre-indexing writeback marker, '!', just add it as a token
4591   // operand.
4592   if (Parser.getTok().is(AsmToken::Exclaim)) {
4593     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4594     Parser.Lex(); // Eat the '!'.
4595   }
4596 
4597   return false;
4598 }
4599 
4600 /// parseMemRegOffsetShift - one of these two:
4601 ///   ( lsl | lsr | asr | ror ) , # shift_amount
4602 ///   rrx
4603 /// return true if it parses a shift otherwise it returns false.
4604 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4605                                           unsigned &Amount) {
4606   SMLoc Loc = Parser.getTok().getLoc();
4607   const AsmToken &Tok = Parser.getTok();
4608   if (Tok.isNot(AsmToken::Identifier))
4609     return true;
4610   StringRef ShiftName = Tok.getString();
4611   if (ShiftName == "lsl" || ShiftName == "LSL" ||
4612       ShiftName == "asl" || ShiftName == "ASL")
4613     St = ARM_AM::lsl;
4614   else if (ShiftName == "lsr" || ShiftName == "LSR")
4615     St = ARM_AM::lsr;
4616   else if (ShiftName == "asr" || ShiftName == "ASR")
4617     St = ARM_AM::asr;
4618   else if (ShiftName == "ror" || ShiftName == "ROR")
4619     St = ARM_AM::ror;
4620   else if (ShiftName == "rrx" || ShiftName == "RRX")
4621     St = ARM_AM::rrx;
4622   else
4623     return Error(Loc, "illegal shift operator");
4624   Parser.Lex(); // Eat shift type token.
4625 
4626   // rrx stands alone.
4627   Amount = 0;
4628   if (St != ARM_AM::rrx) {
4629     Loc = Parser.getTok().getLoc();
4630     // A '#' and a shift amount.
4631     const AsmToken &HashTok = Parser.getTok();
4632     if (HashTok.isNot(AsmToken::Hash) &&
4633         HashTok.isNot(AsmToken::Dollar))
4634       return Error(HashTok.getLoc(), "'#' expected");
4635     Parser.Lex(); // Eat hash token.
4636 
4637     const MCExpr *Expr;
4638     if (getParser().parseExpression(Expr))
4639       return true;
4640     // Range check the immediate.
4641     // lsl, ror: 0 <= imm <= 31
4642     // lsr, asr: 0 <= imm <= 32
4643     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4644     if (!CE)
4645       return Error(Loc, "shift amount must be an immediate");
4646     int64_t Imm = CE->getValue();
4647     if (Imm < 0 ||
4648         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4649         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4650       return Error(Loc, "immediate shift value out of range");
4651     // If <ShiftTy> #0, turn it into a no_shift.
4652     if (Imm == 0)
4653       St = ARM_AM::lsl;
4654     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4655     if (Imm == 32)
4656       Imm = 0;
4657     Amount = Imm;
4658   }
4659 
4660   return false;
4661 }
4662 
4663 /// parseFPImm - A floating point immediate expression operand.
4664 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4665 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4666   // Anything that can accept a floating point constant as an operand
4667   // needs to go through here, as the regular parseExpression is
4668   // integer only.
4669   //
4670   // This routine still creates a generic Immediate operand, containing
4671   // a bitcast of the 64-bit floating point value. The various operands
4672   // that accept floats can check whether the value is valid for them
4673   // via the standard is*() predicates.
4674 
4675   SMLoc S = Parser.getTok().getLoc();
4676 
4677   if (Parser.getTok().isNot(AsmToken::Hash) &&
4678       Parser.getTok().isNot(AsmToken::Dollar))
4679     return MatchOperand_NoMatch;
4680 
4681   // Disambiguate the VMOV forms that can accept an FP immediate.
4682   // vmov.f32 <sreg>, #imm
4683   // vmov.f64 <dreg>, #imm
4684   // vmov.f32 <dreg>, #imm  @ vector f32x2
4685   // vmov.f32 <qreg>, #imm  @ vector f32x4
4686   //
4687   // There are also the NEON VMOV instructions which expect an
4688   // integer constant. Make sure we don't try to parse an FPImm
4689   // for these:
4690   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4691   ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4692   bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4693                                      TyOp->getToken() == ".f64");
4694   ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]);
4695   bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4696                                           Mnemonic->getToken() == "fconsts");
4697   if (!(isVmovf || isFconst))
4698     return MatchOperand_NoMatch;
4699 
4700   Parser.Lex(); // Eat '#' or '$'.
4701 
4702   // Handle negation, as that still comes through as a separate token.
4703   bool isNegative = false;
4704   if (Parser.getTok().is(AsmToken::Minus)) {
4705     isNegative = true;
4706     Parser.Lex();
4707   }
4708   const AsmToken &Tok = Parser.getTok();
4709   SMLoc Loc = Tok.getLoc();
4710   if (Tok.is(AsmToken::Real) && isVmovf) {
4711     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4712     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4713     // If we had a '-' in front, toggle the sign bit.
4714     IntVal ^= (uint64_t)isNegative << 31;
4715     Parser.Lex(); // Eat the token.
4716     Operands.push_back(ARMOperand::CreateImm(
4717           MCConstantExpr::Create(IntVal, getContext()),
4718           S, Parser.getTok().getLoc()));
4719     return MatchOperand_Success;
4720   }
4721   // Also handle plain integers. Instructions which allow floating point
4722   // immediates also allow a raw encoded 8-bit value.
4723   if (Tok.is(AsmToken::Integer) && isFconst) {
4724     int64_t Val = Tok.getIntVal();
4725     Parser.Lex(); // Eat the token.
4726     if (Val > 255 || Val < 0) {
4727       Error(Loc, "encoded floating point value out of range");
4728       return MatchOperand_ParseFail;
4729     }
4730     float RealVal = ARM_AM::getFPImmFloat(Val);
4731     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4732 
4733     Operands.push_back(ARMOperand::CreateImm(
4734         MCConstantExpr::Create(Val, getContext()), S,
4735         Parser.getTok().getLoc()));
4736     return MatchOperand_Success;
4737   }
4738 
4739   Error(Loc, "invalid floating point immediate");
4740   return MatchOperand_ParseFail;
4741 }
4742 
4743 /// Parse a arm instruction operand.  For now this parses the operand regardless
4744 /// of the mnemonic.
4745 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4746                                 StringRef Mnemonic) {
4747   SMLoc S, E;
4748 
4749   // Check if the current operand has a custom associated parser, if so, try to
4750   // custom parse the operand, or fallback to the general approach.
4751   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4752   if (ResTy == MatchOperand_Success)
4753     return false;
4754   // If there wasn't a custom match, try the generic matcher below. Otherwise,
4755   // there was a match, but an error occurred, in which case, just return that
4756   // the operand parsing failed.
4757   if (ResTy == MatchOperand_ParseFail)
4758     return true;
4759 
4760   switch (getLexer().getKind()) {
4761   default:
4762     Error(Parser.getTok().getLoc(), "unexpected token in operand");
4763     return true;
4764   case AsmToken::Identifier: {
4765     // If we've seen a branch mnemonic, the next operand must be a label.  This
4766     // is true even if the label is a register name.  So "br r1" means branch to
4767     // label "r1".
4768     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4769     if (!ExpectLabel) {
4770       if (!tryParseRegisterWithWriteBack(Operands))
4771         return false;
4772       int Res = tryParseShiftRegister(Operands);
4773       if (Res == 0) // success
4774         return false;
4775       else if (Res == -1) // irrecoverable error
4776         return true;
4777       // If this is VMRS, check for the apsr_nzcv operand.
4778       if (Mnemonic == "vmrs" &&
4779           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4780         S = Parser.getTok().getLoc();
4781         Parser.Lex();
4782         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4783         return false;
4784       }
4785     }
4786 
4787     // Fall though for the Identifier case that is not a register or a
4788     // special name.
4789   }
4790   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4791   case AsmToken::Integer: // things like 1f and 2b as a branch targets
4792   case AsmToken::String:  // quoted label names.
4793   case AsmToken::Dot: {   // . as a branch target
4794     // This was not a register so parse other operands that start with an
4795     // identifier (like labels) as expressions and create them as immediates.
4796     const MCExpr *IdVal;
4797     S = Parser.getTok().getLoc();
4798     if (getParser().parseExpression(IdVal))
4799       return true;
4800     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4801     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4802     return false;
4803   }
4804   case AsmToken::LBrac:
4805     return parseMemory(Operands);
4806   case AsmToken::LCurly:
4807     return parseRegisterList(Operands);
4808   case AsmToken::Dollar:
4809   case AsmToken::Hash: {
4810     // #42 -> immediate.
4811     S = Parser.getTok().getLoc();
4812     Parser.Lex();
4813 
4814     if (Parser.getTok().isNot(AsmToken::Colon)) {
4815       bool isNegative = Parser.getTok().is(AsmToken::Minus);
4816       const MCExpr *ImmVal;
4817       if (getParser().parseExpression(ImmVal))
4818         return true;
4819       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4820       if (CE) {
4821         int32_t Val = CE->getValue();
4822         if (isNegative && Val == 0)
4823           ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4824       }
4825       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4826       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4827 
4828       // There can be a trailing '!' on operands that we want as a separate
4829       // '!' Token operand. Handle that here. For example, the compatibility
4830       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4831       if (Parser.getTok().is(AsmToken::Exclaim)) {
4832         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4833                                                    Parser.getTok().getLoc()));
4834         Parser.Lex(); // Eat exclaim token
4835       }
4836       return false;
4837     }
4838     // w/ a ':' after the '#', it's just like a plain ':'.
4839     // FALLTHROUGH
4840   }
4841   case AsmToken::Colon: {
4842     // ":lower16:" and ":upper16:" expression prefixes
4843     // FIXME: Check it's an expression prefix,
4844     // e.g. (FOO - :lower16:BAR) isn't legal.
4845     ARMMCExpr::VariantKind RefKind;
4846     if (parsePrefix(RefKind))
4847       return true;
4848 
4849     const MCExpr *SubExprVal;
4850     if (getParser().parseExpression(SubExprVal))
4851       return true;
4852 
4853     const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4854                                               getContext());
4855     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4856     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4857     return false;
4858   }
4859   case AsmToken::Equal: {
4860     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4861       return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4862 
4863     Parser.Lex(); // Eat '='
4864     const MCExpr *SubExprVal;
4865     if (getParser().parseExpression(SubExprVal))
4866       return true;
4867     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4868 
4869     const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4870     Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4871     return false;
4872   }
4873   }
4874 }
4875 
4876 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4877 //  :lower16: and :upper16:.
4878 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4879   RefKind = ARMMCExpr::VK_ARM_None;
4880 
4881   // consume an optional '#' (GNU compatibility)
4882   if (getLexer().is(AsmToken::Hash))
4883     Parser.Lex();
4884 
4885   // :lower16: and :upper16: modifiers
4886   assert(getLexer().is(AsmToken::Colon) && "expected a :");
4887   Parser.Lex(); // Eat ':'
4888 
4889   if (getLexer().isNot(AsmToken::Identifier)) {
4890     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4891     return true;
4892   }
4893 
4894   StringRef IDVal = Parser.getTok().getIdentifier();
4895   if (IDVal == "lower16") {
4896     RefKind = ARMMCExpr::VK_ARM_LO16;
4897   } else if (IDVal == "upper16") {
4898     RefKind = ARMMCExpr::VK_ARM_HI16;
4899   } else {
4900     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4901     return true;
4902   }
4903   Parser.Lex();
4904 
4905   if (getLexer().isNot(AsmToken::Colon)) {
4906     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4907     return true;
4908   }
4909   Parser.Lex(); // Eat the last ':'
4910   return false;
4911 }
4912 
4913 /// \brief Given a mnemonic, split out possible predication code and carry
4914 /// setting letters to form a canonical mnemonic and flags.
4915 //
4916 // FIXME: Would be nice to autogen this.
4917 // FIXME: This is a bit of a maze of special cases.
4918 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4919                                       unsigned &PredicationCode,
4920                                       bool &CarrySetting,
4921                                       unsigned &ProcessorIMod,
4922                                       StringRef &ITMask) {
4923   PredicationCode = ARMCC::AL;
4924   CarrySetting = false;
4925   ProcessorIMod = 0;
4926 
4927   // Ignore some mnemonics we know aren't predicated forms.
4928   //
4929   // FIXME: Would be nice to autogen this.
4930   if ((Mnemonic == "movs" && isThumb()) ||
4931       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4932       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4933       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4934       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4935       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
4936       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4937       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4938       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4939       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4940       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
4941       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4942       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4943     return Mnemonic;
4944 
4945   // First, split out any predication code. Ignore mnemonics we know aren't
4946   // predicated but do have a carry-set and so weren't caught above.
4947   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4948       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4949       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4950       Mnemonic != "sbcs" && Mnemonic != "rscs") {
4951     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4952       .Case("eq", ARMCC::EQ)
4953       .Case("ne", ARMCC::NE)
4954       .Case("hs", ARMCC::HS)
4955       .Case("cs", ARMCC::HS)
4956       .Case("lo", ARMCC::LO)
4957       .Case("cc", ARMCC::LO)
4958       .Case("mi", ARMCC::MI)
4959       .Case("pl", ARMCC::PL)
4960       .Case("vs", ARMCC::VS)
4961       .Case("vc", ARMCC::VC)
4962       .Case("hi", ARMCC::HI)
4963       .Case("ls", ARMCC::LS)
4964       .Case("ge", ARMCC::GE)
4965       .Case("lt", ARMCC::LT)
4966       .Case("gt", ARMCC::GT)
4967       .Case("le", ARMCC::LE)
4968       .Case("al", ARMCC::AL)
4969       .Default(~0U);
4970     if (CC != ~0U) {
4971       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4972       PredicationCode = CC;
4973     }
4974   }
4975 
4976   // Next, determine if we have a carry setting bit. We explicitly ignore all
4977   // the instructions we know end in 's'.
4978   if (Mnemonic.endswith("s") &&
4979       !(Mnemonic == "cps" || Mnemonic == "mls" ||
4980         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4981         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4982         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4983         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4984         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4985         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4986         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4987         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
4988         (Mnemonic == "movs" && isThumb()))) {
4989     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4990     CarrySetting = true;
4991   }
4992 
4993   // The "cps" instruction can have a interrupt mode operand which is glued into
4994   // the mnemonic. Check if this is the case, split it and parse the imod op
4995   if (Mnemonic.startswith("cps")) {
4996     // Split out any imod code.
4997     unsigned IMod =
4998       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4999       .Case("ie", ARM_PROC::IE)
5000       .Case("id", ARM_PROC::ID)
5001       .Default(~0U);
5002     if (IMod != ~0U) {
5003       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5004       ProcessorIMod = IMod;
5005     }
5006   }
5007 
5008   // The "it" instruction has the condition mask on the end of the mnemonic.
5009   if (Mnemonic.startswith("it")) {
5010     ITMask = Mnemonic.slice(2, Mnemonic.size());
5011     Mnemonic = Mnemonic.slice(0, 2);
5012   }
5013 
5014   return Mnemonic;
5015 }
5016 
5017 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5018 /// inclusion of carry set or predication code operands.
5019 //
5020 // FIXME: It would be nice to autogen this.
5021 void ARMAsmParser::
5022 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5023                      bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5024   if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5025       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5026       Mnemonic == "add" || Mnemonic == "adc" ||
5027       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5028       Mnemonic == "orr" || Mnemonic == "mvn" ||
5029       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5030       Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5031       Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5032       (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5033                       Mnemonic == "mla" || Mnemonic == "smlal" ||
5034                       Mnemonic == "umlal" || Mnemonic == "umull"))) {
5035     CanAcceptCarrySet = true;
5036   } else
5037     CanAcceptCarrySet = false;
5038 
5039   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5040       Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
5041       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
5042       Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
5043       Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5044       Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5045       Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5046       Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5047       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5048       (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5049     // These mnemonics are never predicable
5050     CanAcceptPredicationCode = false;
5051   } else if (!isThumb()) {
5052     // Some instructions are only predicable in Thumb mode
5053     CanAcceptPredicationCode
5054       = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5055         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5056         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5057         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5058         Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5059         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5060         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5061   } else if (isThumbOne()) {
5062     if (hasV6MOps())
5063       CanAcceptPredicationCode = Mnemonic != "movs";
5064     else
5065       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5066   } else
5067     CanAcceptPredicationCode = true;
5068 }
5069 
5070 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5071                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5072   // FIXME: This is all horribly hacky. We really need a better way to deal
5073   // with optional operands like this in the matcher table.
5074 
5075   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5076   // another does not. Specifically, the MOVW instruction does not. So we
5077   // special case it here and remove the defaulted (non-setting) cc_out
5078   // operand if that's the instruction we're trying to match.
5079   //
5080   // We do this as post-processing of the explicit operands rather than just
5081   // conditionally adding the cc_out in the first place because we need
5082   // to check the type of the parsed immediate operand.
5083   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5084       !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5085       static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5086       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5087     return true;
5088 
5089   // Register-register 'add' for thumb does not have a cc_out operand
5090   // when there are only two register operands.
5091   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5092       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5093       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5094       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5095     return true;
5096   // Register-register 'add' for thumb does not have a cc_out operand
5097   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5098   // have to check the immediate range here since Thumb2 has a variant
5099   // that can handle a different range and has a cc_out operand.
5100   if (((isThumb() && Mnemonic == "add") ||
5101        (isThumbTwo() && Mnemonic == "sub")) &&
5102       Operands.size() == 6 &&
5103       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5104       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5105       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5106       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5107       ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5108        static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5109     return true;
5110   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5111   // imm0_4095 variant. That's the least-preferred variant when
5112   // selecting via the generic "add" mnemonic, so to know that we
5113   // should remove the cc_out operand, we have to explicitly check that
5114   // it's not one of the other variants. Ugh.
5115   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5116       Operands.size() == 6 &&
5117       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5118       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5119       static_cast<ARMOperand*>(Operands[5])->isImm()) {
5120     // Nest conditions rather than one big 'if' statement for readability.
5121     //
5122     // If both registers are low, we're in an IT block, and the immediate is
5123     // in range, we should use encoding T1 instead, which has a cc_out.
5124     if (inITBlock() &&
5125         isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5126         isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5127         static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5128       return false;
5129     // Check against T3. If the second register is the PC, this is an
5130     // alternate form of ADR, which uses encoding T4, so check for that too.
5131     if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5132         static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5133       return false;
5134 
5135     // Otherwise, we use encoding T4, which does not have a cc_out
5136     // operand.
5137     return true;
5138   }
5139 
5140   // The thumb2 multiply instruction doesn't have a CCOut register, so
5141   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5142   // use the 16-bit encoding or not.
5143   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5144       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5145       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5146       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5147       static_cast<ARMOperand*>(Operands[5])->isReg() &&
5148       // If the registers aren't low regs, the destination reg isn't the
5149       // same as one of the source regs, or the cc_out operand is zero
5150       // outside of an IT block, we have to use the 32-bit encoding, so
5151       // remove the cc_out operand.
5152       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5153        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5154        !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5155        !inITBlock() ||
5156        (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5157         static_cast<ARMOperand*>(Operands[5])->getReg() &&
5158         static_cast<ARMOperand*>(Operands[3])->getReg() !=
5159         static_cast<ARMOperand*>(Operands[4])->getReg())))
5160     return true;
5161 
5162   // Also check the 'mul' syntax variant that doesn't specify an explicit
5163   // destination register.
5164   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5165       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5166       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5167       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5168       // If the registers aren't low regs  or the cc_out operand is zero
5169       // outside of an IT block, we have to use the 32-bit encoding, so
5170       // remove the cc_out operand.
5171       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5172        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5173        !inITBlock()))
5174     return true;
5175 
5176 
5177 
5178   // Register-register 'add/sub' for thumb does not have a cc_out operand
5179   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5180   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5181   // right, this will result in better diagnostics (which operand is off)
5182   // anyway.
5183   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5184       (Operands.size() == 5 || Operands.size() == 6) &&
5185       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5186       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5187       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5188       (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5189        (Operands.size() == 6 &&
5190         static_cast<ARMOperand*>(Operands[5])->isImm())))
5191     return true;
5192 
5193   return false;
5194 }
5195 
5196 bool ARMAsmParser::shouldOmitPredicateOperand(
5197     StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5198   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5199   unsigned RegIdx = 3;
5200   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5201       static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5202     if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5203         static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5204       RegIdx = 4;
5205 
5206     if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5207         (ARMMCRegisterClasses[ARM::DPRRegClassID]
5208              .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5209          ARMMCRegisterClasses[ARM::QPRRegClassID]
5210              .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5211       return true;
5212   }
5213   return false;
5214 }
5215 
5216 static bool isDataTypeToken(StringRef Tok) {
5217   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5218     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5219     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5220     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5221     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5222     Tok == ".f" || Tok == ".d";
5223 }
5224 
5225 // FIXME: This bit should probably be handled via an explicit match class
5226 // in the .td files that matches the suffix instead of having it be
5227 // a literal string token the way it is now.
5228 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5229   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5230 }
5231 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5232                                  unsigned VariantID);
5233 
5234 static bool RequiresVFPRegListValidation(StringRef Inst,
5235                                          bool &AcceptSinglePrecisionOnly,
5236                                          bool &AcceptDoublePrecisionOnly) {
5237   if (Inst.size() < 7)
5238     return false;
5239 
5240   if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5241     StringRef AddressingMode = Inst.substr(4, 2);
5242     if (AddressingMode == "ia" || AddressingMode == "db" ||
5243         AddressingMode == "ea" || AddressingMode == "fd") {
5244       AcceptSinglePrecisionOnly = Inst[6] == 's';
5245       AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5246       return true;
5247     }
5248   }
5249 
5250   return false;
5251 }
5252 
5253 /// Parse an arm instruction mnemonic followed by its operands.
5254 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5255                                     SMLoc NameLoc,
5256                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5257   // FIXME: Can this be done via tablegen in some fashion?
5258   bool RequireVFPRegisterListCheck;
5259   bool AcceptSinglePrecisionOnly;
5260   bool AcceptDoublePrecisionOnly;
5261   RequireVFPRegisterListCheck =
5262     RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5263                                  AcceptDoublePrecisionOnly);
5264 
5265   // Apply mnemonic aliases before doing anything else, as the destination
5266   // mnemonic may include suffices and we want to handle them normally.
5267   // The generic tblgen'erated code does this later, at the start of
5268   // MatchInstructionImpl(), but that's too late for aliases that include
5269   // any sort of suffix.
5270   unsigned AvailableFeatures = getAvailableFeatures();
5271   unsigned AssemblerDialect = getParser().getAssemblerDialect();
5272   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5273 
5274   // First check for the ARM-specific .req directive.
5275   if (Parser.getTok().is(AsmToken::Identifier) &&
5276       Parser.getTok().getIdentifier() == ".req") {
5277     parseDirectiveReq(Name, NameLoc);
5278     // We always return 'error' for this, as we're done with this
5279     // statement and don't need to match the 'instruction."
5280     return true;
5281   }
5282 
5283   // Create the leading tokens for the mnemonic, split by '.' characters.
5284   size_t Start = 0, Next = Name.find('.');
5285   StringRef Mnemonic = Name.slice(Start, Next);
5286 
5287   // Split out the predication code and carry setting flag from the mnemonic.
5288   unsigned PredicationCode;
5289   unsigned ProcessorIMod;
5290   bool CarrySetting;
5291   StringRef ITMask;
5292   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5293                            ProcessorIMod, ITMask);
5294 
5295   // In Thumb1, only the branch (B) instruction can be predicated.
5296   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5297     Parser.eatToEndOfStatement();
5298     return Error(NameLoc, "conditional execution not supported in Thumb1");
5299   }
5300 
5301   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5302 
5303   // Handle the IT instruction ITMask. Convert it to a bitmask. This
5304   // is the mask as it will be for the IT encoding if the conditional
5305   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5306   // where the conditional bit0 is zero, the instruction post-processing
5307   // will adjust the mask accordingly.
5308   if (Mnemonic == "it") {
5309     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5310     if (ITMask.size() > 3) {
5311       Parser.eatToEndOfStatement();
5312       return Error(Loc, "too many conditions on IT instruction");
5313     }
5314     unsigned Mask = 8;
5315     for (unsigned i = ITMask.size(); i != 0; --i) {
5316       char pos = ITMask[i - 1];
5317       if (pos != 't' && pos != 'e') {
5318         Parser.eatToEndOfStatement();
5319         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5320       }
5321       Mask >>= 1;
5322       if (ITMask[i - 1] == 't')
5323         Mask |= 8;
5324     }
5325     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5326   }
5327 
5328   // FIXME: This is all a pretty gross hack. We should automatically handle
5329   // optional operands like this via tblgen.
5330 
5331   // Next, add the CCOut and ConditionCode operands, if needed.
5332   //
5333   // For mnemonics which can ever incorporate a carry setting bit or predication
5334   // code, our matching model involves us always generating CCOut and
5335   // ConditionCode operands to match the mnemonic "as written" and then we let
5336   // the matcher deal with finding the right instruction or generating an
5337   // appropriate error.
5338   bool CanAcceptCarrySet, CanAcceptPredicationCode;
5339   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5340 
5341   // If we had a carry-set on an instruction that can't do that, issue an
5342   // error.
5343   if (!CanAcceptCarrySet && CarrySetting) {
5344     Parser.eatToEndOfStatement();
5345     return Error(NameLoc, "instruction '" + Mnemonic +
5346                  "' can not set flags, but 's' suffix specified");
5347   }
5348   // If we had a predication code on an instruction that can't do that, issue an
5349   // error.
5350   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5351     Parser.eatToEndOfStatement();
5352     return Error(NameLoc, "instruction '" + Mnemonic +
5353                  "' is not predicable, but condition code specified");
5354   }
5355 
5356   // Add the carry setting operand, if necessary.
5357   if (CanAcceptCarrySet) {
5358     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5359     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5360                                                Loc));
5361   }
5362 
5363   // Add the predication code operand, if necessary.
5364   if (CanAcceptPredicationCode) {
5365     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5366                                       CarrySetting);
5367     Operands.push_back(ARMOperand::CreateCondCode(
5368                          ARMCC::CondCodes(PredicationCode), Loc));
5369   }
5370 
5371   // Add the processor imod operand, if necessary.
5372   if (ProcessorIMod) {
5373     Operands.push_back(ARMOperand::CreateImm(
5374           MCConstantExpr::Create(ProcessorIMod, getContext()),
5375                                  NameLoc, NameLoc));
5376   }
5377 
5378   // Add the remaining tokens in the mnemonic.
5379   while (Next != StringRef::npos) {
5380     Start = Next;
5381     Next = Name.find('.', Start + 1);
5382     StringRef ExtraToken = Name.slice(Start, Next);
5383 
5384     // Some NEON instructions have an optional datatype suffix that is
5385     // completely ignored. Check for that.
5386     if (isDataTypeToken(ExtraToken) &&
5387         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5388       continue;
5389 
5390     // For for ARM mode generate an error if the .n qualifier is used.
5391     if (ExtraToken == ".n" && !isThumb()) {
5392       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5393       Parser.eatToEndOfStatement();
5394       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5395                    "arm mode");
5396     }
5397 
5398     // The .n qualifier is always discarded as that is what the tables
5399     // and matcher expect.  In ARM mode the .w qualifier has no effect,
5400     // so discard it to avoid errors that can be caused by the matcher.
5401     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5402       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5403       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5404     }
5405   }
5406 
5407   // Read the remaining operands.
5408   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5409     // Read the first operand.
5410     if (parseOperand(Operands, Mnemonic)) {
5411       Parser.eatToEndOfStatement();
5412       return true;
5413     }
5414 
5415     while (getLexer().is(AsmToken::Comma)) {
5416       Parser.Lex();  // Eat the comma.
5417 
5418       // Parse and remember the operand.
5419       if (parseOperand(Operands, Mnemonic)) {
5420         Parser.eatToEndOfStatement();
5421         return true;
5422       }
5423     }
5424   }
5425 
5426   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5427     SMLoc Loc = getLexer().getLoc();
5428     Parser.eatToEndOfStatement();
5429     return Error(Loc, "unexpected token in argument list");
5430   }
5431 
5432   Parser.Lex(); // Consume the EndOfStatement
5433 
5434   if (RequireVFPRegisterListCheck) {
5435     ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5436     if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5437       return Error(Op->getStartLoc(),
5438                    "VFP/Neon single precision register expected");
5439     if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5440       return Error(Op->getStartLoc(),
5441                    "VFP/Neon double precision register expected");
5442   }
5443 
5444   // Some instructions, mostly Thumb, have forms for the same mnemonic that
5445   // do and don't have a cc_out optional-def operand. With some spot-checks
5446   // of the operand list, we can figure out which variant we're trying to
5447   // parse and adjust accordingly before actually matching. We shouldn't ever
5448   // try to remove a cc_out operand that was explicitly set on the the
5449   // mnemonic, of course (CarrySetting == true). Reason number #317 the
5450   // table driven matcher doesn't fit well with the ARM instruction set.
5451   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5452     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5453     Operands.erase(Operands.begin() + 1);
5454     delete Op;
5455   }
5456 
5457   // Some instructions have the same mnemonic, but don't always
5458   // have a predicate. Distinguish them here and delete the
5459   // predicate if needed.
5460   if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5461     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5462     Operands.erase(Operands.begin() + 1);
5463     delete Op;
5464   }
5465 
5466   // ARM mode 'blx' need special handling, as the register operand version
5467   // is predicable, but the label operand version is not. So, we can't rely
5468   // on the Mnemonic based checking to correctly figure out when to put
5469   // a k_CondCode operand in the list. If we're trying to match the label
5470   // version, remove the k_CondCode operand here.
5471   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5472       static_cast<ARMOperand*>(Operands[2])->isImm()) {
5473     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5474     Operands.erase(Operands.begin() + 1);
5475     delete Op;
5476   }
5477 
5478   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5479   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5480   // a single GPRPair reg operand is used in the .td file to replace the two
5481   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5482   // expressed as a GPRPair, so we have to manually merge them.
5483   // FIXME: We would really like to be able to tablegen'erate this.
5484   if (!isThumb() && Operands.size() > 4 &&
5485       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5486        Mnemonic == "stlexd")) {
5487     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5488     unsigned Idx = isLoad ? 2 : 3;
5489     ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5490     ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5491 
5492     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5493     // Adjust only if Op1 and Op2 are GPRs.
5494     if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5495         MRC.contains(Op2->getReg())) {
5496       unsigned Reg1 = Op1->getReg();
5497       unsigned Reg2 = Op2->getReg();
5498       unsigned Rt = MRI->getEncodingValue(Reg1);
5499       unsigned Rt2 = MRI->getEncodingValue(Reg2);
5500 
5501       // Rt2 must be Rt + 1 and Rt must be even.
5502       if (Rt + 1 != Rt2 || (Rt & 1)) {
5503         Error(Op2->getStartLoc(), isLoad ?
5504             "destination operands must be sequential" :
5505             "source operands must be sequential");
5506         return true;
5507       }
5508       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5509           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5510       Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5511       Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5512             NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5513       delete Op1;
5514       delete Op2;
5515     }
5516   }
5517 
5518   // GNU Assembler extension (compatibility)
5519   if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5520     ARMOperand *Op2 = static_cast<ARMOperand *>(Operands[2]);
5521     ARMOperand *Op3 = static_cast<ARMOperand *>(Operands[3]);
5522     if (Op3->isMem()) {
5523       assert(Op2->isReg() && "expected register argument");
5524 
5525       unsigned SuperReg = MRI->getMatchingSuperReg(
5526           Op2->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5527 
5528       assert(SuperReg && "expected register pair");
5529 
5530       unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5531 
5532       Operands.insert(Operands.begin() + 3,
5533                       ARMOperand::CreateReg(PairedReg,
5534                                             Op2->getStartLoc(),
5535                                             Op2->getEndLoc()));
5536     }
5537   }
5538 
5539   // FIXME: As said above, this is all a pretty gross hack.  This instruction
5540   // does not fit with other "subs" and tblgen.
5541   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5542   // so the Mnemonic is the original name "subs" and delete the predicate
5543   // operand so it will match the table entry.
5544   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5545       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5546       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5547       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5548       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5549       static_cast<ARMOperand*>(Operands[5])->isImm()) {
5550     ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5551     Operands.erase(Operands.begin());
5552     delete Op0;
5553     Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5554 
5555     ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5556     Operands.erase(Operands.begin() + 1);
5557     delete Op1;
5558   }
5559   return false;
5560 }
5561 
5562 // Validate context-sensitive operand constraints.
5563 
5564 // return 'true' if register list contains non-low GPR registers,
5565 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5566 // 'containsReg' to true.
5567 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5568                                  unsigned HiReg, bool &containsReg) {
5569   containsReg = false;
5570   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5571     unsigned OpReg = Inst.getOperand(i).getReg();
5572     if (OpReg == Reg)
5573       containsReg = true;
5574     // Anything other than a low register isn't legal here.
5575     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5576       return true;
5577   }
5578   return false;
5579 }
5580 
5581 // Check if the specified regisgter is in the register list of the inst,
5582 // starting at the indicated operand number.
5583 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5584   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5585     unsigned OpReg = Inst.getOperand(i).getReg();
5586     if (OpReg == Reg)
5587       return true;
5588   }
5589   return false;
5590 }
5591 
5592 // Return true if instruction has the interesting property of being
5593 // allowed in IT blocks, but not being predicable.
5594 static bool instIsBreakpoint(const MCInst &Inst) {
5595     return Inst.getOpcode() == ARM::tBKPT ||
5596            Inst.getOpcode() == ARM::BKPT ||
5597            Inst.getOpcode() == ARM::tHLT ||
5598            Inst.getOpcode() == ARM::HLT;
5599 
5600 }
5601 
5602 // FIXME: We would really like to be able to tablegen'erate this.
5603 bool ARMAsmParser::
5604 validateInstruction(MCInst &Inst,
5605                     const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5606   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5607   SMLoc Loc = Operands[0]->getStartLoc();
5608 
5609   // Check the IT block state first.
5610   // NOTE: BKPT and HLT instructions have the interesting property of being
5611   // allowed in IT blocks, but not being predicable. They just always execute.
5612   if (inITBlock() && !instIsBreakpoint(Inst)) {
5613     unsigned Bit = 1;
5614     if (ITState.FirstCond)
5615       ITState.FirstCond = false;
5616     else
5617       Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5618     // The instruction must be predicable.
5619     if (!MCID.isPredicable())
5620       return Error(Loc, "instructions in IT block must be predicable");
5621     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5622     unsigned ITCond = Bit ? ITState.Cond :
5623       ARMCC::getOppositeCondition(ITState.Cond);
5624     if (Cond != ITCond) {
5625       // Find the condition code Operand to get its SMLoc information.
5626       SMLoc CondLoc;
5627       for (unsigned I = 1; I < Operands.size(); ++I)
5628         if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5629           CondLoc = Operands[I]->getStartLoc();
5630       return Error(CondLoc, "incorrect condition in IT block; got '" +
5631                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5632                    "', but expected '" +
5633                    ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5634     }
5635   // Check for non-'al' condition codes outside of the IT block.
5636   } else if (isThumbTwo() && MCID.isPredicable() &&
5637              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5638              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5639              Inst.getOpcode() != ARM::t2Bcc)
5640     return Error(Loc, "predicated instructions must be in IT block");
5641 
5642   const unsigned Opcode = Inst.getOpcode();
5643   switch (Opcode) {
5644   case ARM::LDRD:
5645   case ARM::LDRD_PRE:
5646   case ARM::LDRD_POST: {
5647     const unsigned RtReg = Inst.getOperand(0).getReg();
5648 
5649     // Rt can't be R14.
5650     if (RtReg == ARM::LR)
5651       return Error(Operands[3]->getStartLoc(),
5652                    "Rt can't be R14");
5653 
5654     const unsigned Rt = MRI->getEncodingValue(RtReg);
5655     // Rt must be even-numbered.
5656     if ((Rt & 1) == 1)
5657       return Error(Operands[3]->getStartLoc(),
5658                    "Rt must be even-numbered");
5659 
5660     // Rt2 must be Rt + 1.
5661     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5662     if (Rt2 != Rt + 1)
5663       return Error(Operands[3]->getStartLoc(),
5664                    "destination operands must be sequential");
5665 
5666     if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5667       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5668       // For addressing modes with writeback, the base register needs to be
5669       // different from the destination registers.
5670       if (Rn == Rt || Rn == Rt2)
5671         return Error(Operands[3]->getStartLoc(),
5672                      "base register needs to be different from destination "
5673                      "registers");
5674     }
5675 
5676     return false;
5677   }
5678   case ARM::t2LDRDi8:
5679   case ARM::t2LDRD_PRE:
5680   case ARM::t2LDRD_POST: {
5681     // Rt2 must be different from Rt.
5682     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5683     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5684     if (Rt2 == Rt)
5685       return Error(Operands[3]->getStartLoc(),
5686                    "destination operands can't be identical");
5687     return false;
5688   }
5689   case ARM::STRD: {
5690     // Rt2 must be Rt + 1.
5691     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5692     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5693     if (Rt2 != Rt + 1)
5694       return Error(Operands[3]->getStartLoc(),
5695                    "source operands must be sequential");
5696     return false;
5697   }
5698   case ARM::STRD_PRE:
5699   case ARM::STRD_POST: {
5700     // Rt2 must be Rt + 1.
5701     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5702     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5703     if (Rt2 != Rt + 1)
5704       return Error(Operands[3]->getStartLoc(),
5705                    "source operands must be sequential");
5706     return false;
5707   }
5708   case ARM::SBFX:
5709   case ARM::UBFX: {
5710     // Width must be in range [1, 32-lsb].
5711     unsigned LSB = Inst.getOperand(2).getImm();
5712     unsigned Widthm1 = Inst.getOperand(3).getImm();
5713     if (Widthm1 >= 32 - LSB)
5714       return Error(Operands[5]->getStartLoc(),
5715                    "bitfield width must be in range [1,32-lsb]");
5716     return false;
5717   }
5718   // Notionally handles ARM::tLDMIA_UPD too.
5719   case ARM::tLDMIA: {
5720     // If we're parsing Thumb2, the .w variant is available and handles
5721     // most cases that are normally illegal for a Thumb1 LDM instruction.
5722     // We'll make the transformation in processInstruction() if necessary.
5723     //
5724     // Thumb LDM instructions are writeback iff the base register is not
5725     // in the register list.
5726     unsigned Rn = Inst.getOperand(0).getReg();
5727     bool HasWritebackToken =
5728       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5729        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5730     bool ListContainsBase;
5731     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5732       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5733                    "registers must be in range r0-r7");
5734     // If we should have writeback, then there should be a '!' token.
5735     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5736       return Error(Operands[2]->getStartLoc(),
5737                    "writeback operator '!' expected");
5738     // If we should not have writeback, there must not be a '!'. This is
5739     // true even for the 32-bit wide encodings.
5740     if (ListContainsBase && HasWritebackToken)
5741       return Error(Operands[3]->getStartLoc(),
5742                    "writeback operator '!' not allowed when base register "
5743                    "in register list");
5744 
5745     break;
5746   }
5747   case ARM::LDMIA_UPD:
5748   case ARM::LDMDB_UPD:
5749   case ARM::LDMIB_UPD:
5750   case ARM::LDMDA_UPD:
5751     // ARM variants loading and updating the same register are only officially
5752     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5753     if (!hasV7Ops())
5754       break;
5755     // Fallthrough
5756   case ARM::t2LDMIA_UPD:
5757   case ARM::t2LDMDB_UPD:
5758   case ARM::t2STMIA_UPD:
5759   case ARM::t2STMDB_UPD: {
5760     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5761       return Error(Operands.back()->getStartLoc(),
5762                    "writeback register not allowed in register list");
5763     break;
5764   }
5765   case ARM::sysLDMIA_UPD:
5766   case ARM::sysLDMDA_UPD:
5767   case ARM::sysLDMDB_UPD:
5768   case ARM::sysLDMIB_UPD:
5769     if (!listContainsReg(Inst, 3, ARM::PC))
5770       return Error(Operands[4]->getStartLoc(),
5771                    "writeback register only allowed on system LDM "
5772                    "if PC in register-list");
5773     break;
5774   case ARM::sysSTMIA_UPD:
5775   case ARM::sysSTMDA_UPD:
5776   case ARM::sysSTMDB_UPD:
5777   case ARM::sysSTMIB_UPD:
5778     return Error(Operands[2]->getStartLoc(),
5779                  "system STM cannot have writeback register");
5780   case ARM::tMUL: {
5781     // The second source operand must be the same register as the destination
5782     // operand.
5783     //
5784     // In this case, we must directly check the parsed operands because the
5785     // cvtThumbMultiply() function is written in such a way that it guarantees
5786     // this first statement is always true for the new Inst.  Essentially, the
5787     // destination is unconditionally copied into the second source operand
5788     // without checking to see if it matches what we actually parsed.
5789     if (Operands.size() == 6 &&
5790         (((ARMOperand*)Operands[3])->getReg() !=
5791          ((ARMOperand*)Operands[5])->getReg()) &&
5792         (((ARMOperand*)Operands[3])->getReg() !=
5793          ((ARMOperand*)Operands[4])->getReg())) {
5794       return Error(Operands[3]->getStartLoc(),
5795                    "destination register must match source register");
5796     }
5797     break;
5798   }
5799   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5800   // so only issue a diagnostic for thumb1. The instructions will be
5801   // switched to the t2 encodings in processInstruction() if necessary.
5802   case ARM::tPOP: {
5803     bool ListContainsBase;
5804     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5805         !isThumbTwo())
5806       return Error(Operands[2]->getStartLoc(),
5807                    "registers must be in range r0-r7 or pc");
5808     break;
5809   }
5810   case ARM::tPUSH: {
5811     bool ListContainsBase;
5812     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5813         !isThumbTwo())
5814       return Error(Operands[2]->getStartLoc(),
5815                    "registers must be in range r0-r7 or lr");
5816     break;
5817   }
5818   case ARM::tSTMIA_UPD: {
5819     bool ListContainsBase, InvalidLowList;
5820     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5821                                           0, ListContainsBase);
5822     if (InvalidLowList && !isThumbTwo())
5823       return Error(Operands[4]->getStartLoc(),
5824                    "registers must be in range r0-r7");
5825 
5826     // This would be converted to a 32-bit stm, but that's not valid if the
5827     // writeback register is in the list.
5828     if (InvalidLowList && ListContainsBase)
5829       return Error(Operands[4]->getStartLoc(),
5830                    "writeback operator '!' not allowed when base register "
5831                    "in register list");
5832     break;
5833   }
5834   case ARM::tADDrSP: {
5835     // If the non-SP source operand and the destination operand are not the
5836     // same, we need thumb2 (for the wide encoding), or we have an error.
5837     if (!isThumbTwo() &&
5838         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5839       return Error(Operands[4]->getStartLoc(),
5840                    "source register must be the same as destination");
5841     }
5842     break;
5843   }
5844   // Final range checking for Thumb unconditional branch instructions.
5845   case ARM::tB:
5846     if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5847       return Error(Operands[2]->getStartLoc(), "branch target out of range");
5848     break;
5849   case ARM::t2B: {
5850     int op = (Operands[2]->isImm()) ? 2 : 3;
5851     if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5852       return Error(Operands[op]->getStartLoc(), "branch target out of range");
5853     break;
5854   }
5855   // Final range checking for Thumb conditional branch instructions.
5856   case ARM::tBcc:
5857     if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5858       return Error(Operands[2]->getStartLoc(), "branch target out of range");
5859     break;
5860   case ARM::t2Bcc: {
5861     int Op = (Operands[2]->isImm()) ? 2 : 3;
5862     if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5863       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5864     break;
5865   }
5866   case ARM::MOVi16:
5867   case ARM::t2MOVi16:
5868   case ARM::t2MOVTi16:
5869     {
5870     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
5871     // especially when we turn it into a movw and the expression <symbol> does
5872     // not have a :lower16: or :upper16 as part of the expression.  We don't
5873     // want the behavior of silently truncating, which can be unexpected and
5874     // lead to bugs that are difficult to find since this is an easy mistake
5875     // to make.
5876     int i = (Operands[3]->isImm()) ? 3 : 4;
5877     ARMOperand *Op = static_cast<ARMOperand*>(Operands[i]);
5878     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5879     if (CE) break;
5880     const MCExpr *E = dyn_cast<MCExpr>(Op->getImm());
5881     if (!E) break;
5882     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
5883     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
5884                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) {
5885       return Error(Op->getStartLoc(),
5886 	     "immediate expression for mov requires :lower16: or :upper16");
5887       break;
5888     }
5889     }
5890   }
5891 
5892   return false;
5893 }
5894 
5895 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5896   switch(Opc) {
5897   default: llvm_unreachable("unexpected opcode!");
5898   // VST1LN
5899   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5900   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5901   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5902   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5903   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5904   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5905   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5906   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5907   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5908 
5909   // VST2LN
5910   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5911   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5912   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5913   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5914   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5915 
5916   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5917   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5918   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5919   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5920   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5921 
5922   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5923   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5924   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5925   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5926   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5927 
5928   // VST3LN
5929   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5930   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5931   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5932   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5933   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5934   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5935   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5936   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5937   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5938   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5939   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5940   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5941   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5942   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5943   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5944 
5945   // VST3
5946   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5947   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5948   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5949   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5950   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5951   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5952   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5953   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5954   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5955   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5956   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5957   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5958   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5959   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5960   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5961   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5962   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5963   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5964 
5965   // VST4LN
5966   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5967   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5968   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5969   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5970   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5971   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5972   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5973   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5974   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5975   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5976   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5977   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5978   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5979   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5980   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5981 
5982   // VST4
5983   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5984   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5985   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5986   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5987   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5988   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5989   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5990   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5991   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5992   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5993   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5994   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5995   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5996   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5997   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5998   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5999   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6000   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6001   }
6002 }
6003 
6004 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6005   switch(Opc) {
6006   default: llvm_unreachable("unexpected opcode!");
6007   // VLD1LN
6008   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6009   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6010   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6011   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6012   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6013   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6014   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
6015   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6016   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6017 
6018   // VLD2LN
6019   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6020   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6021   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6022   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6023   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6024   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6025   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6026   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6027   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6028   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6029   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
6030   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6031   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6032   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6033   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6034 
6035   // VLD3DUP
6036   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6037   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6038   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6039   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6040   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6041   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6042   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6043   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6044   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6045   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6046   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6047   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6048   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
6049   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6050   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6051   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6052   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6053   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6054 
6055   // VLD3LN
6056   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6057   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6058   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6059   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6060   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6061   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6062   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6063   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6064   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6065   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6066   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
6067   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6068   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6069   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6070   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6071 
6072   // VLD3
6073   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6074   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6075   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6076   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6077   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6078   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6079   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6080   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6081   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6082   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6083   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6084   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6085   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
6086   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6087   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6088   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
6089   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6090   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6091 
6092   // VLD4LN
6093   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6094   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6095   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6096   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6097   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6098   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6099   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6100   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6101   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6102   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6103   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
6104   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6105   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6106   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6107   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6108 
6109   // VLD4DUP
6110   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6111   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6112   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6113   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6114   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6115   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6116   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6117   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6118   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6119   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6120   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6121   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6122   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
6123   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6124   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6125   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6126   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6127   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6128 
6129   // VLD4
6130   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6131   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6132   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6133   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6134   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6135   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6136   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6137   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6138   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6139   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6140   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6141   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6142   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
6143   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6144   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6145   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
6146   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6147   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6148   }
6149 }
6150 
6151 bool ARMAsmParser::
6152 processInstruction(MCInst &Inst,
6153                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6154   switch (Inst.getOpcode()) {
6155   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6156   case ARM::LDRT_POST:
6157   case ARM::LDRBT_POST: {
6158     const unsigned Opcode =
6159       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6160                                            : ARM::LDRBT_POST_IMM;
6161     MCInst TmpInst;
6162     TmpInst.setOpcode(Opcode);
6163     TmpInst.addOperand(Inst.getOperand(0));
6164     TmpInst.addOperand(Inst.getOperand(1));
6165     TmpInst.addOperand(Inst.getOperand(1));
6166     TmpInst.addOperand(MCOperand::CreateReg(0));
6167     TmpInst.addOperand(MCOperand::CreateImm(0));
6168     TmpInst.addOperand(Inst.getOperand(2));
6169     TmpInst.addOperand(Inst.getOperand(3));
6170     Inst = TmpInst;
6171     return true;
6172   }
6173   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6174   case ARM::STRT_POST:
6175   case ARM::STRBT_POST: {
6176     const unsigned Opcode =
6177       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6178                                            : ARM::STRBT_POST_IMM;
6179     MCInst TmpInst;
6180     TmpInst.setOpcode(Opcode);
6181     TmpInst.addOperand(Inst.getOperand(1));
6182     TmpInst.addOperand(Inst.getOperand(0));
6183     TmpInst.addOperand(Inst.getOperand(1));
6184     TmpInst.addOperand(MCOperand::CreateReg(0));
6185     TmpInst.addOperand(MCOperand::CreateImm(0));
6186     TmpInst.addOperand(Inst.getOperand(2));
6187     TmpInst.addOperand(Inst.getOperand(3));
6188     Inst = TmpInst;
6189     return true;
6190   }
6191   // Alias for alternate form of 'ADR Rd, #imm' instruction.
6192   case ARM::ADDri: {
6193     if (Inst.getOperand(1).getReg() != ARM::PC ||
6194         Inst.getOperand(5).getReg() != 0)
6195       return false;
6196     MCInst TmpInst;
6197     TmpInst.setOpcode(ARM::ADR);
6198     TmpInst.addOperand(Inst.getOperand(0));
6199     TmpInst.addOperand(Inst.getOperand(2));
6200     TmpInst.addOperand(Inst.getOperand(3));
6201     TmpInst.addOperand(Inst.getOperand(4));
6202     Inst = TmpInst;
6203     return true;
6204   }
6205   // Aliases for alternate PC+imm syntax of LDR instructions.
6206   case ARM::t2LDRpcrel:
6207     // Select the narrow version if the immediate will fit.
6208     if (Inst.getOperand(1).getImm() > 0 &&
6209         Inst.getOperand(1).getImm() <= 0xff &&
6210         !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6211          static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6212       Inst.setOpcode(ARM::tLDRpci);
6213     else
6214       Inst.setOpcode(ARM::t2LDRpci);
6215     return true;
6216   case ARM::t2LDRBpcrel:
6217     Inst.setOpcode(ARM::t2LDRBpci);
6218     return true;
6219   case ARM::t2LDRHpcrel:
6220     Inst.setOpcode(ARM::t2LDRHpci);
6221     return true;
6222   case ARM::t2LDRSBpcrel:
6223     Inst.setOpcode(ARM::t2LDRSBpci);
6224     return true;
6225   case ARM::t2LDRSHpcrel:
6226     Inst.setOpcode(ARM::t2LDRSHpci);
6227     return true;
6228   // Handle NEON VST complex aliases.
6229   case ARM::VST1LNdWB_register_Asm_8:
6230   case ARM::VST1LNdWB_register_Asm_16:
6231   case ARM::VST1LNdWB_register_Asm_32: {
6232     MCInst TmpInst;
6233     // Shuffle the operands around so the lane index operand is in the
6234     // right place.
6235     unsigned Spacing;
6236     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6237     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6238     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6239     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6240     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6241     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6242     TmpInst.addOperand(Inst.getOperand(1)); // lane
6243     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6244     TmpInst.addOperand(Inst.getOperand(6));
6245     Inst = TmpInst;
6246     return true;
6247   }
6248 
6249   case ARM::VST2LNdWB_register_Asm_8:
6250   case ARM::VST2LNdWB_register_Asm_16:
6251   case ARM::VST2LNdWB_register_Asm_32:
6252   case ARM::VST2LNqWB_register_Asm_16:
6253   case ARM::VST2LNqWB_register_Asm_32: {
6254     MCInst TmpInst;
6255     // Shuffle the operands around so the lane index operand is in the
6256     // right place.
6257     unsigned Spacing;
6258     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6259     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6260     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6261     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6262     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6263     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6264     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6265                                             Spacing));
6266     TmpInst.addOperand(Inst.getOperand(1)); // lane
6267     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6268     TmpInst.addOperand(Inst.getOperand(6));
6269     Inst = TmpInst;
6270     return true;
6271   }
6272 
6273   case ARM::VST3LNdWB_register_Asm_8:
6274   case ARM::VST3LNdWB_register_Asm_16:
6275   case ARM::VST3LNdWB_register_Asm_32:
6276   case ARM::VST3LNqWB_register_Asm_16:
6277   case ARM::VST3LNqWB_register_Asm_32: {
6278     MCInst TmpInst;
6279     // Shuffle the operands around so the lane index operand is in the
6280     // right place.
6281     unsigned Spacing;
6282     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6283     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6284     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6285     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6286     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6287     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6288     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6289                                             Spacing));
6290     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6291                                             Spacing * 2));
6292     TmpInst.addOperand(Inst.getOperand(1)); // lane
6293     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6294     TmpInst.addOperand(Inst.getOperand(6));
6295     Inst = TmpInst;
6296     return true;
6297   }
6298 
6299   case ARM::VST4LNdWB_register_Asm_8:
6300   case ARM::VST4LNdWB_register_Asm_16:
6301   case ARM::VST4LNdWB_register_Asm_32:
6302   case ARM::VST4LNqWB_register_Asm_16:
6303   case ARM::VST4LNqWB_register_Asm_32: {
6304     MCInst TmpInst;
6305     // Shuffle the operands around so the lane index operand is in the
6306     // right place.
6307     unsigned Spacing;
6308     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6309     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6310     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6311     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6312     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6313     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6314     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6315                                             Spacing));
6316     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6317                                             Spacing * 2));
6318     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6319                                             Spacing * 3));
6320     TmpInst.addOperand(Inst.getOperand(1)); // lane
6321     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6322     TmpInst.addOperand(Inst.getOperand(6));
6323     Inst = TmpInst;
6324     return true;
6325   }
6326 
6327   case ARM::VST1LNdWB_fixed_Asm_8:
6328   case ARM::VST1LNdWB_fixed_Asm_16:
6329   case ARM::VST1LNdWB_fixed_Asm_32: {
6330     MCInst TmpInst;
6331     // Shuffle the operands around so the lane index operand is in the
6332     // right place.
6333     unsigned Spacing;
6334     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6335     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6336     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6337     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6338     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6339     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6340     TmpInst.addOperand(Inst.getOperand(1)); // lane
6341     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6342     TmpInst.addOperand(Inst.getOperand(5));
6343     Inst = TmpInst;
6344     return true;
6345   }
6346 
6347   case ARM::VST2LNdWB_fixed_Asm_8:
6348   case ARM::VST2LNdWB_fixed_Asm_16:
6349   case ARM::VST2LNdWB_fixed_Asm_32:
6350   case ARM::VST2LNqWB_fixed_Asm_16:
6351   case ARM::VST2LNqWB_fixed_Asm_32: {
6352     MCInst TmpInst;
6353     // Shuffle the operands around so the lane index operand is in the
6354     // right place.
6355     unsigned Spacing;
6356     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6357     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6358     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6359     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6360     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6361     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6362     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6363                                             Spacing));
6364     TmpInst.addOperand(Inst.getOperand(1)); // lane
6365     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6366     TmpInst.addOperand(Inst.getOperand(5));
6367     Inst = TmpInst;
6368     return true;
6369   }
6370 
6371   case ARM::VST3LNdWB_fixed_Asm_8:
6372   case ARM::VST3LNdWB_fixed_Asm_16:
6373   case ARM::VST3LNdWB_fixed_Asm_32:
6374   case ARM::VST3LNqWB_fixed_Asm_16:
6375   case ARM::VST3LNqWB_fixed_Asm_32: {
6376     MCInst TmpInst;
6377     // Shuffle the operands around so the lane index operand is in the
6378     // right place.
6379     unsigned Spacing;
6380     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6381     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6382     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6383     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6384     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6385     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6386     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6387                                             Spacing));
6388     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6389                                             Spacing * 2));
6390     TmpInst.addOperand(Inst.getOperand(1)); // lane
6391     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6392     TmpInst.addOperand(Inst.getOperand(5));
6393     Inst = TmpInst;
6394     return true;
6395   }
6396 
6397   case ARM::VST4LNdWB_fixed_Asm_8:
6398   case ARM::VST4LNdWB_fixed_Asm_16:
6399   case ARM::VST4LNdWB_fixed_Asm_32:
6400   case ARM::VST4LNqWB_fixed_Asm_16:
6401   case ARM::VST4LNqWB_fixed_Asm_32: {
6402     MCInst TmpInst;
6403     // Shuffle the operands around so the lane index operand is in the
6404     // right place.
6405     unsigned Spacing;
6406     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6407     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6408     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6409     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6410     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6411     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6412     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6413                                             Spacing));
6414     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6415                                             Spacing * 2));
6416     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6417                                             Spacing * 3));
6418     TmpInst.addOperand(Inst.getOperand(1)); // lane
6419     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6420     TmpInst.addOperand(Inst.getOperand(5));
6421     Inst = TmpInst;
6422     return true;
6423   }
6424 
6425   case ARM::VST1LNdAsm_8:
6426   case ARM::VST1LNdAsm_16:
6427   case ARM::VST1LNdAsm_32: {
6428     MCInst TmpInst;
6429     // Shuffle the operands around so the lane index operand is in the
6430     // right place.
6431     unsigned Spacing;
6432     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6433     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6434     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6435     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6436     TmpInst.addOperand(Inst.getOperand(1)); // lane
6437     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6438     TmpInst.addOperand(Inst.getOperand(5));
6439     Inst = TmpInst;
6440     return true;
6441   }
6442 
6443   case ARM::VST2LNdAsm_8:
6444   case ARM::VST2LNdAsm_16:
6445   case ARM::VST2LNdAsm_32:
6446   case ARM::VST2LNqAsm_16:
6447   case ARM::VST2LNqAsm_32: {
6448     MCInst TmpInst;
6449     // Shuffle the operands around so the lane index operand is in the
6450     // right place.
6451     unsigned Spacing;
6452     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6453     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6454     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6455     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6456     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6457                                             Spacing));
6458     TmpInst.addOperand(Inst.getOperand(1)); // lane
6459     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6460     TmpInst.addOperand(Inst.getOperand(5));
6461     Inst = TmpInst;
6462     return true;
6463   }
6464 
6465   case ARM::VST3LNdAsm_8:
6466   case ARM::VST3LNdAsm_16:
6467   case ARM::VST3LNdAsm_32:
6468   case ARM::VST3LNqAsm_16:
6469   case ARM::VST3LNqAsm_32: {
6470     MCInst TmpInst;
6471     // Shuffle the operands around so the lane index operand is in the
6472     // right place.
6473     unsigned Spacing;
6474     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6475     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6476     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6477     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6478     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6479                                             Spacing));
6480     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6481                                             Spacing * 2));
6482     TmpInst.addOperand(Inst.getOperand(1)); // lane
6483     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6484     TmpInst.addOperand(Inst.getOperand(5));
6485     Inst = TmpInst;
6486     return true;
6487   }
6488 
6489   case ARM::VST4LNdAsm_8:
6490   case ARM::VST4LNdAsm_16:
6491   case ARM::VST4LNdAsm_32:
6492   case ARM::VST4LNqAsm_16:
6493   case ARM::VST4LNqAsm_32: {
6494     MCInst TmpInst;
6495     // Shuffle the operands around so the lane index operand is in the
6496     // right place.
6497     unsigned Spacing;
6498     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6499     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6500     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6501     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6502     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6503                                             Spacing));
6504     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6505                                             Spacing * 2));
6506     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6507                                             Spacing * 3));
6508     TmpInst.addOperand(Inst.getOperand(1)); // lane
6509     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6510     TmpInst.addOperand(Inst.getOperand(5));
6511     Inst = TmpInst;
6512     return true;
6513   }
6514 
6515   // Handle NEON VLD complex aliases.
6516   case ARM::VLD1LNdWB_register_Asm_8:
6517   case ARM::VLD1LNdWB_register_Asm_16:
6518   case ARM::VLD1LNdWB_register_Asm_32: {
6519     MCInst TmpInst;
6520     // Shuffle the operands around so the lane index operand is in the
6521     // right place.
6522     unsigned Spacing;
6523     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6524     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6525     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6526     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6527     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6528     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6529     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6530     TmpInst.addOperand(Inst.getOperand(1)); // lane
6531     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6532     TmpInst.addOperand(Inst.getOperand(6));
6533     Inst = TmpInst;
6534     return true;
6535   }
6536 
6537   case ARM::VLD2LNdWB_register_Asm_8:
6538   case ARM::VLD2LNdWB_register_Asm_16:
6539   case ARM::VLD2LNdWB_register_Asm_32:
6540   case ARM::VLD2LNqWB_register_Asm_16:
6541   case ARM::VLD2LNqWB_register_Asm_32: {
6542     MCInst TmpInst;
6543     // Shuffle the operands around so the lane index operand is in the
6544     // right place.
6545     unsigned Spacing;
6546     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6547     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6548     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6549                                             Spacing));
6550     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6551     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6552     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6553     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6554     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6555     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6556                                             Spacing));
6557     TmpInst.addOperand(Inst.getOperand(1)); // lane
6558     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6559     TmpInst.addOperand(Inst.getOperand(6));
6560     Inst = TmpInst;
6561     return true;
6562   }
6563 
6564   case ARM::VLD3LNdWB_register_Asm_8:
6565   case ARM::VLD3LNdWB_register_Asm_16:
6566   case ARM::VLD3LNdWB_register_Asm_32:
6567   case ARM::VLD3LNqWB_register_Asm_16:
6568   case ARM::VLD3LNqWB_register_Asm_32: {
6569     MCInst TmpInst;
6570     // Shuffle the operands around so the lane index operand is in the
6571     // right place.
6572     unsigned Spacing;
6573     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6574     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6575     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6576                                             Spacing));
6577     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6578                                             Spacing * 2));
6579     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6580     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6581     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6582     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6583     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6584     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6585                                             Spacing));
6586     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6587                                             Spacing * 2));
6588     TmpInst.addOperand(Inst.getOperand(1)); // lane
6589     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6590     TmpInst.addOperand(Inst.getOperand(6));
6591     Inst = TmpInst;
6592     return true;
6593   }
6594 
6595   case ARM::VLD4LNdWB_register_Asm_8:
6596   case ARM::VLD4LNdWB_register_Asm_16:
6597   case ARM::VLD4LNdWB_register_Asm_32:
6598   case ARM::VLD4LNqWB_register_Asm_16:
6599   case ARM::VLD4LNqWB_register_Asm_32: {
6600     MCInst TmpInst;
6601     // Shuffle the operands around so the lane index operand is in the
6602     // right place.
6603     unsigned Spacing;
6604     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6605     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6606     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6607                                             Spacing));
6608     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6609                                             Spacing * 2));
6610     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6611                                             Spacing * 3));
6612     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6613     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6614     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6615     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6616     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6617     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6618                                             Spacing));
6619     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6620                                             Spacing * 2));
6621     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6622                                             Spacing * 3));
6623     TmpInst.addOperand(Inst.getOperand(1)); // lane
6624     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6625     TmpInst.addOperand(Inst.getOperand(6));
6626     Inst = TmpInst;
6627     return true;
6628   }
6629 
6630   case ARM::VLD1LNdWB_fixed_Asm_8:
6631   case ARM::VLD1LNdWB_fixed_Asm_16:
6632   case ARM::VLD1LNdWB_fixed_Asm_32: {
6633     MCInst TmpInst;
6634     // Shuffle the operands around so the lane index operand is in the
6635     // right place.
6636     unsigned Spacing;
6637     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6638     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6639     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6640     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6641     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6642     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6643     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6644     TmpInst.addOperand(Inst.getOperand(1)); // lane
6645     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6646     TmpInst.addOperand(Inst.getOperand(5));
6647     Inst = TmpInst;
6648     return true;
6649   }
6650 
6651   case ARM::VLD2LNdWB_fixed_Asm_8:
6652   case ARM::VLD2LNdWB_fixed_Asm_16:
6653   case ARM::VLD2LNdWB_fixed_Asm_32:
6654   case ARM::VLD2LNqWB_fixed_Asm_16:
6655   case ARM::VLD2LNqWB_fixed_Asm_32: {
6656     MCInst TmpInst;
6657     // Shuffle the operands around so the lane index operand is in the
6658     // right place.
6659     unsigned Spacing;
6660     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6661     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6662     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6663                                             Spacing));
6664     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6665     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6666     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6667     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6668     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6669     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670                                             Spacing));
6671     TmpInst.addOperand(Inst.getOperand(1)); // lane
6672     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6673     TmpInst.addOperand(Inst.getOperand(5));
6674     Inst = TmpInst;
6675     return true;
6676   }
6677 
6678   case ARM::VLD3LNdWB_fixed_Asm_8:
6679   case ARM::VLD3LNdWB_fixed_Asm_16:
6680   case ARM::VLD3LNdWB_fixed_Asm_32:
6681   case ARM::VLD3LNqWB_fixed_Asm_16:
6682   case ARM::VLD3LNqWB_fixed_Asm_32: {
6683     MCInst TmpInst;
6684     // Shuffle the operands around so the lane index operand is in the
6685     // right place.
6686     unsigned Spacing;
6687     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6688     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6689     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6690                                             Spacing));
6691     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6692                                             Spacing * 2));
6693     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6694     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6695     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6696     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6697     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6698     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6699                                             Spacing));
6700     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6701                                             Spacing * 2));
6702     TmpInst.addOperand(Inst.getOperand(1)); // lane
6703     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6704     TmpInst.addOperand(Inst.getOperand(5));
6705     Inst = TmpInst;
6706     return true;
6707   }
6708 
6709   case ARM::VLD4LNdWB_fixed_Asm_8:
6710   case ARM::VLD4LNdWB_fixed_Asm_16:
6711   case ARM::VLD4LNdWB_fixed_Asm_32:
6712   case ARM::VLD4LNqWB_fixed_Asm_16:
6713   case ARM::VLD4LNqWB_fixed_Asm_32: {
6714     MCInst TmpInst;
6715     // Shuffle the operands around so the lane index operand is in the
6716     // right place.
6717     unsigned Spacing;
6718     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6719     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6720     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6721                                             Spacing));
6722     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6723                                             Spacing * 2));
6724     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6725                                             Spacing * 3));
6726     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6727     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6728     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6729     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6730     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6731     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6732                                             Spacing));
6733     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6734                                             Spacing * 2));
6735     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6736                                             Spacing * 3));
6737     TmpInst.addOperand(Inst.getOperand(1)); // lane
6738     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6739     TmpInst.addOperand(Inst.getOperand(5));
6740     Inst = TmpInst;
6741     return true;
6742   }
6743 
6744   case ARM::VLD1LNdAsm_8:
6745   case ARM::VLD1LNdAsm_16:
6746   case ARM::VLD1LNdAsm_32: {
6747     MCInst TmpInst;
6748     // Shuffle the operands around so the lane index operand is in the
6749     // right place.
6750     unsigned Spacing;
6751     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6752     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6753     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6754     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6755     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6756     TmpInst.addOperand(Inst.getOperand(1)); // lane
6757     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6758     TmpInst.addOperand(Inst.getOperand(5));
6759     Inst = TmpInst;
6760     return true;
6761   }
6762 
6763   case ARM::VLD2LNdAsm_8:
6764   case ARM::VLD2LNdAsm_16:
6765   case ARM::VLD2LNdAsm_32:
6766   case ARM::VLD2LNqAsm_16:
6767   case ARM::VLD2LNqAsm_32: {
6768     MCInst TmpInst;
6769     // Shuffle the operands around so the lane index operand is in the
6770     // right place.
6771     unsigned Spacing;
6772     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6773     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6774     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6775                                             Spacing));
6776     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6777     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6778     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6779     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6780                                             Spacing));
6781     TmpInst.addOperand(Inst.getOperand(1)); // lane
6782     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6783     TmpInst.addOperand(Inst.getOperand(5));
6784     Inst = TmpInst;
6785     return true;
6786   }
6787 
6788   case ARM::VLD3LNdAsm_8:
6789   case ARM::VLD3LNdAsm_16:
6790   case ARM::VLD3LNdAsm_32:
6791   case ARM::VLD3LNqAsm_16:
6792   case ARM::VLD3LNqAsm_32: {
6793     MCInst TmpInst;
6794     // Shuffle the operands around so the lane index operand is in the
6795     // right place.
6796     unsigned Spacing;
6797     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6798     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6799     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6800                                             Spacing));
6801     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6802                                             Spacing * 2));
6803     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6804     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6805     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6806     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6807                                             Spacing));
6808     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6809                                             Spacing * 2));
6810     TmpInst.addOperand(Inst.getOperand(1)); // lane
6811     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6812     TmpInst.addOperand(Inst.getOperand(5));
6813     Inst = TmpInst;
6814     return true;
6815   }
6816 
6817   case ARM::VLD4LNdAsm_8:
6818   case ARM::VLD4LNdAsm_16:
6819   case ARM::VLD4LNdAsm_32:
6820   case ARM::VLD4LNqAsm_16:
6821   case ARM::VLD4LNqAsm_32: {
6822     MCInst TmpInst;
6823     // Shuffle the operands around so the lane index operand is in the
6824     // right place.
6825     unsigned Spacing;
6826     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6827     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6828     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6829                                             Spacing));
6830     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6831                                             Spacing * 2));
6832     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6833                                             Spacing * 3));
6834     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6835     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6836     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6837     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6838                                             Spacing));
6839     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6840                                             Spacing * 2));
6841     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6842                                             Spacing * 3));
6843     TmpInst.addOperand(Inst.getOperand(1)); // lane
6844     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6845     TmpInst.addOperand(Inst.getOperand(5));
6846     Inst = TmpInst;
6847     return true;
6848   }
6849 
6850   // VLD3DUP single 3-element structure to all lanes instructions.
6851   case ARM::VLD3DUPdAsm_8:
6852   case ARM::VLD3DUPdAsm_16:
6853   case ARM::VLD3DUPdAsm_32:
6854   case ARM::VLD3DUPqAsm_8:
6855   case ARM::VLD3DUPqAsm_16:
6856   case ARM::VLD3DUPqAsm_32: {
6857     MCInst TmpInst;
6858     unsigned Spacing;
6859     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6860     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6861     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6862                                             Spacing));
6863     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6864                                             Spacing * 2));
6865     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6866     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6867     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6868     TmpInst.addOperand(Inst.getOperand(4));
6869     Inst = TmpInst;
6870     return true;
6871   }
6872 
6873   case ARM::VLD3DUPdWB_fixed_Asm_8:
6874   case ARM::VLD3DUPdWB_fixed_Asm_16:
6875   case ARM::VLD3DUPdWB_fixed_Asm_32:
6876   case ARM::VLD3DUPqWB_fixed_Asm_8:
6877   case ARM::VLD3DUPqWB_fixed_Asm_16:
6878   case ARM::VLD3DUPqWB_fixed_Asm_32: {
6879     MCInst TmpInst;
6880     unsigned Spacing;
6881     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6882     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6883     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6884                                             Spacing));
6885     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6886                                             Spacing * 2));
6887     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6888     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6889     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6890     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6891     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6892     TmpInst.addOperand(Inst.getOperand(4));
6893     Inst = TmpInst;
6894     return true;
6895   }
6896 
6897   case ARM::VLD3DUPdWB_register_Asm_8:
6898   case ARM::VLD3DUPdWB_register_Asm_16:
6899   case ARM::VLD3DUPdWB_register_Asm_32:
6900   case ARM::VLD3DUPqWB_register_Asm_8:
6901   case ARM::VLD3DUPqWB_register_Asm_16:
6902   case ARM::VLD3DUPqWB_register_Asm_32: {
6903     MCInst TmpInst;
6904     unsigned Spacing;
6905     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6906     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6907     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6908                                             Spacing));
6909     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6910                                             Spacing * 2));
6911     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6912     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6913     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6914     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6915     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6916     TmpInst.addOperand(Inst.getOperand(5));
6917     Inst = TmpInst;
6918     return true;
6919   }
6920 
6921   // VLD3 multiple 3-element structure instructions.
6922   case ARM::VLD3dAsm_8:
6923   case ARM::VLD3dAsm_16:
6924   case ARM::VLD3dAsm_32:
6925   case ARM::VLD3qAsm_8:
6926   case ARM::VLD3qAsm_16:
6927   case ARM::VLD3qAsm_32: {
6928     MCInst TmpInst;
6929     unsigned Spacing;
6930     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6931     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6932     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6933                                             Spacing));
6934     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6935                                             Spacing * 2));
6936     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6937     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6938     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6939     TmpInst.addOperand(Inst.getOperand(4));
6940     Inst = TmpInst;
6941     return true;
6942   }
6943 
6944   case ARM::VLD3dWB_fixed_Asm_8:
6945   case ARM::VLD3dWB_fixed_Asm_16:
6946   case ARM::VLD3dWB_fixed_Asm_32:
6947   case ARM::VLD3qWB_fixed_Asm_8:
6948   case ARM::VLD3qWB_fixed_Asm_16:
6949   case ARM::VLD3qWB_fixed_Asm_32: {
6950     MCInst TmpInst;
6951     unsigned Spacing;
6952     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6953     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6954     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6955                                             Spacing));
6956     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6957                                             Spacing * 2));
6958     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6959     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6960     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6961     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6962     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6963     TmpInst.addOperand(Inst.getOperand(4));
6964     Inst = TmpInst;
6965     return true;
6966   }
6967 
6968   case ARM::VLD3dWB_register_Asm_8:
6969   case ARM::VLD3dWB_register_Asm_16:
6970   case ARM::VLD3dWB_register_Asm_32:
6971   case ARM::VLD3qWB_register_Asm_8:
6972   case ARM::VLD3qWB_register_Asm_16:
6973   case ARM::VLD3qWB_register_Asm_32: {
6974     MCInst TmpInst;
6975     unsigned Spacing;
6976     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6977     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6978     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6979                                             Spacing));
6980     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6981                                             Spacing * 2));
6982     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6983     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6984     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6985     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6986     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6987     TmpInst.addOperand(Inst.getOperand(5));
6988     Inst = TmpInst;
6989     return true;
6990   }
6991 
6992   // VLD4DUP single 3-element structure to all lanes instructions.
6993   case ARM::VLD4DUPdAsm_8:
6994   case ARM::VLD4DUPdAsm_16:
6995   case ARM::VLD4DUPdAsm_32:
6996   case ARM::VLD4DUPqAsm_8:
6997   case ARM::VLD4DUPqAsm_16:
6998   case ARM::VLD4DUPqAsm_32: {
6999     MCInst TmpInst;
7000     unsigned Spacing;
7001     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7002     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7003     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7004                                             Spacing));
7005     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7006                                             Spacing * 2));
7007     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7008                                             Spacing * 3));
7009     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7010     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7011     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7012     TmpInst.addOperand(Inst.getOperand(4));
7013     Inst = TmpInst;
7014     return true;
7015   }
7016 
7017   case ARM::VLD4DUPdWB_fixed_Asm_8:
7018   case ARM::VLD4DUPdWB_fixed_Asm_16:
7019   case ARM::VLD4DUPdWB_fixed_Asm_32:
7020   case ARM::VLD4DUPqWB_fixed_Asm_8:
7021   case ARM::VLD4DUPqWB_fixed_Asm_16:
7022   case ARM::VLD4DUPqWB_fixed_Asm_32: {
7023     MCInst TmpInst;
7024     unsigned Spacing;
7025     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7026     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7027     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7028                                             Spacing));
7029     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7030                                             Spacing * 2));
7031     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7032                                             Spacing * 3));
7033     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7034     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7035     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7036     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7037     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7038     TmpInst.addOperand(Inst.getOperand(4));
7039     Inst = TmpInst;
7040     return true;
7041   }
7042 
7043   case ARM::VLD4DUPdWB_register_Asm_8:
7044   case ARM::VLD4DUPdWB_register_Asm_16:
7045   case ARM::VLD4DUPdWB_register_Asm_32:
7046   case ARM::VLD4DUPqWB_register_Asm_8:
7047   case ARM::VLD4DUPqWB_register_Asm_16:
7048   case ARM::VLD4DUPqWB_register_Asm_32: {
7049     MCInst TmpInst;
7050     unsigned Spacing;
7051     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7052     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7053     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7054                                             Spacing));
7055     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7056                                             Spacing * 2));
7057     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7058                                             Spacing * 3));
7059     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7060     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7061     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7062     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7063     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7064     TmpInst.addOperand(Inst.getOperand(5));
7065     Inst = TmpInst;
7066     return true;
7067   }
7068 
7069   // VLD4 multiple 4-element structure instructions.
7070   case ARM::VLD4dAsm_8:
7071   case ARM::VLD4dAsm_16:
7072   case ARM::VLD4dAsm_32:
7073   case ARM::VLD4qAsm_8:
7074   case ARM::VLD4qAsm_16:
7075   case ARM::VLD4qAsm_32: {
7076     MCInst TmpInst;
7077     unsigned Spacing;
7078     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7079     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7080     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7081                                             Spacing));
7082     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7083                                             Spacing * 2));
7084     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7085                                             Spacing * 3));
7086     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7087     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7088     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7089     TmpInst.addOperand(Inst.getOperand(4));
7090     Inst = TmpInst;
7091     return true;
7092   }
7093 
7094   case ARM::VLD4dWB_fixed_Asm_8:
7095   case ARM::VLD4dWB_fixed_Asm_16:
7096   case ARM::VLD4dWB_fixed_Asm_32:
7097   case ARM::VLD4qWB_fixed_Asm_8:
7098   case ARM::VLD4qWB_fixed_Asm_16:
7099   case ARM::VLD4qWB_fixed_Asm_32: {
7100     MCInst TmpInst;
7101     unsigned Spacing;
7102     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7103     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7104     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7105                                             Spacing));
7106     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7107                                             Spacing * 2));
7108     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7109                                             Spacing * 3));
7110     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7111     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7112     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7113     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7114     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7115     TmpInst.addOperand(Inst.getOperand(4));
7116     Inst = TmpInst;
7117     return true;
7118   }
7119 
7120   case ARM::VLD4dWB_register_Asm_8:
7121   case ARM::VLD4dWB_register_Asm_16:
7122   case ARM::VLD4dWB_register_Asm_32:
7123   case ARM::VLD4qWB_register_Asm_8:
7124   case ARM::VLD4qWB_register_Asm_16:
7125   case ARM::VLD4qWB_register_Asm_32: {
7126     MCInst TmpInst;
7127     unsigned Spacing;
7128     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7129     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7130     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7131                                             Spacing));
7132     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7133                                             Spacing * 2));
7134     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7135                                             Spacing * 3));
7136     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7137     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7138     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7139     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7140     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7141     TmpInst.addOperand(Inst.getOperand(5));
7142     Inst = TmpInst;
7143     return true;
7144   }
7145 
7146   // VST3 multiple 3-element structure instructions.
7147   case ARM::VST3dAsm_8:
7148   case ARM::VST3dAsm_16:
7149   case ARM::VST3dAsm_32:
7150   case ARM::VST3qAsm_8:
7151   case ARM::VST3qAsm_16:
7152   case ARM::VST3qAsm_32: {
7153     MCInst TmpInst;
7154     unsigned Spacing;
7155     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7156     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7157     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7158     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7159     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7160                                             Spacing));
7161     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7162                                             Spacing * 2));
7163     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7164     TmpInst.addOperand(Inst.getOperand(4));
7165     Inst = TmpInst;
7166     return true;
7167   }
7168 
7169   case ARM::VST3dWB_fixed_Asm_8:
7170   case ARM::VST3dWB_fixed_Asm_16:
7171   case ARM::VST3dWB_fixed_Asm_32:
7172   case ARM::VST3qWB_fixed_Asm_8:
7173   case ARM::VST3qWB_fixed_Asm_16:
7174   case ARM::VST3qWB_fixed_Asm_32: {
7175     MCInst TmpInst;
7176     unsigned Spacing;
7177     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7178     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7179     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7180     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7181     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7182     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7183     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7184                                             Spacing));
7185     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7186                                             Spacing * 2));
7187     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7188     TmpInst.addOperand(Inst.getOperand(4));
7189     Inst = TmpInst;
7190     return true;
7191   }
7192 
7193   case ARM::VST3dWB_register_Asm_8:
7194   case ARM::VST3dWB_register_Asm_16:
7195   case ARM::VST3dWB_register_Asm_32:
7196   case ARM::VST3qWB_register_Asm_8:
7197   case ARM::VST3qWB_register_Asm_16:
7198   case ARM::VST3qWB_register_Asm_32: {
7199     MCInst TmpInst;
7200     unsigned Spacing;
7201     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7202     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7203     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7204     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7205     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7206     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7207     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7208                                             Spacing));
7209     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7210                                             Spacing * 2));
7211     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7212     TmpInst.addOperand(Inst.getOperand(5));
7213     Inst = TmpInst;
7214     return true;
7215   }
7216 
7217   // VST4 multiple 3-element structure instructions.
7218   case ARM::VST4dAsm_8:
7219   case ARM::VST4dAsm_16:
7220   case ARM::VST4dAsm_32:
7221   case ARM::VST4qAsm_8:
7222   case ARM::VST4qAsm_16:
7223   case ARM::VST4qAsm_32: {
7224     MCInst TmpInst;
7225     unsigned Spacing;
7226     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7227     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7228     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7229     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7230     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7231                                             Spacing));
7232     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7233                                             Spacing * 2));
7234     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7235                                             Spacing * 3));
7236     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7237     TmpInst.addOperand(Inst.getOperand(4));
7238     Inst = TmpInst;
7239     return true;
7240   }
7241 
7242   case ARM::VST4dWB_fixed_Asm_8:
7243   case ARM::VST4dWB_fixed_Asm_16:
7244   case ARM::VST4dWB_fixed_Asm_32:
7245   case ARM::VST4qWB_fixed_Asm_8:
7246   case ARM::VST4qWB_fixed_Asm_16:
7247   case ARM::VST4qWB_fixed_Asm_32: {
7248     MCInst TmpInst;
7249     unsigned Spacing;
7250     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7251     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7252     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7253     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7254     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7255     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7256     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7257                                             Spacing));
7258     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7259                                             Spacing * 2));
7260     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7261                                             Spacing * 3));
7262     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7263     TmpInst.addOperand(Inst.getOperand(4));
7264     Inst = TmpInst;
7265     return true;
7266   }
7267 
7268   case ARM::VST4dWB_register_Asm_8:
7269   case ARM::VST4dWB_register_Asm_16:
7270   case ARM::VST4dWB_register_Asm_32:
7271   case ARM::VST4qWB_register_Asm_8:
7272   case ARM::VST4qWB_register_Asm_16:
7273   case ARM::VST4qWB_register_Asm_32: {
7274     MCInst TmpInst;
7275     unsigned Spacing;
7276     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7277     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7278     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7279     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7280     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7281     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7282     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7283                                             Spacing));
7284     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7285                                             Spacing * 2));
7286     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7287                                             Spacing * 3));
7288     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7289     TmpInst.addOperand(Inst.getOperand(5));
7290     Inst = TmpInst;
7291     return true;
7292   }
7293 
7294   // Handle encoding choice for the shift-immediate instructions.
7295   case ARM::t2LSLri:
7296   case ARM::t2LSRri:
7297   case ARM::t2ASRri: {
7298     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7299         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7300         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7301         !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7302          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7303       unsigned NewOpc;
7304       switch (Inst.getOpcode()) {
7305       default: llvm_unreachable("unexpected opcode");
7306       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7307       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7308       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7309       }
7310       // The Thumb1 operands aren't in the same order. Awesome, eh?
7311       MCInst TmpInst;
7312       TmpInst.setOpcode(NewOpc);
7313       TmpInst.addOperand(Inst.getOperand(0));
7314       TmpInst.addOperand(Inst.getOperand(5));
7315       TmpInst.addOperand(Inst.getOperand(1));
7316       TmpInst.addOperand(Inst.getOperand(2));
7317       TmpInst.addOperand(Inst.getOperand(3));
7318       TmpInst.addOperand(Inst.getOperand(4));
7319       Inst = TmpInst;
7320       return true;
7321     }
7322     return false;
7323   }
7324 
7325   // Handle the Thumb2 mode MOV complex aliases.
7326   case ARM::t2MOVsr:
7327   case ARM::t2MOVSsr: {
7328     // Which instruction to expand to depends on the CCOut operand and
7329     // whether we're in an IT block if the register operands are low
7330     // registers.
7331     bool isNarrow = false;
7332     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7333         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7334         isARMLowRegister(Inst.getOperand(2).getReg()) &&
7335         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7336         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7337       isNarrow = true;
7338     MCInst TmpInst;
7339     unsigned newOpc;
7340     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7341     default: llvm_unreachable("unexpected opcode!");
7342     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7343     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7344     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7345     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7346     }
7347     TmpInst.setOpcode(newOpc);
7348     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7349     if (isNarrow)
7350       TmpInst.addOperand(MCOperand::CreateReg(
7351           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7352     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7353     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7354     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7355     TmpInst.addOperand(Inst.getOperand(5));
7356     if (!isNarrow)
7357       TmpInst.addOperand(MCOperand::CreateReg(
7358           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7359     Inst = TmpInst;
7360     return true;
7361   }
7362   case ARM::t2MOVsi:
7363   case ARM::t2MOVSsi: {
7364     // Which instruction to expand to depends on the CCOut operand and
7365     // whether we're in an IT block if the register operands are low
7366     // registers.
7367     bool isNarrow = false;
7368     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7369         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7370         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7371       isNarrow = true;
7372     MCInst TmpInst;
7373     unsigned newOpc;
7374     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7375     default: llvm_unreachable("unexpected opcode!");
7376     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7377     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7378     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7379     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7380     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7381     }
7382     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7383     if (Amount == 32) Amount = 0;
7384     TmpInst.setOpcode(newOpc);
7385     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7386     if (isNarrow)
7387       TmpInst.addOperand(MCOperand::CreateReg(
7388           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7389     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7390     if (newOpc != ARM::t2RRX)
7391       TmpInst.addOperand(MCOperand::CreateImm(Amount));
7392     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7393     TmpInst.addOperand(Inst.getOperand(4));
7394     if (!isNarrow)
7395       TmpInst.addOperand(MCOperand::CreateReg(
7396           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7397     Inst = TmpInst;
7398     return true;
7399   }
7400   // Handle the ARM mode MOV complex aliases.
7401   case ARM::ASRr:
7402   case ARM::LSRr:
7403   case ARM::LSLr:
7404   case ARM::RORr: {
7405     ARM_AM::ShiftOpc ShiftTy;
7406     switch(Inst.getOpcode()) {
7407     default: llvm_unreachable("unexpected opcode!");
7408     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7409     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7410     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7411     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7412     }
7413     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7414     MCInst TmpInst;
7415     TmpInst.setOpcode(ARM::MOVsr);
7416     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7417     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7418     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7419     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7420     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7421     TmpInst.addOperand(Inst.getOperand(4));
7422     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7423     Inst = TmpInst;
7424     return true;
7425   }
7426   case ARM::ASRi:
7427   case ARM::LSRi:
7428   case ARM::LSLi:
7429   case ARM::RORi: {
7430     ARM_AM::ShiftOpc ShiftTy;
7431     switch(Inst.getOpcode()) {
7432     default: llvm_unreachable("unexpected opcode!");
7433     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7434     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7435     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7436     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7437     }
7438     // A shift by zero is a plain MOVr, not a MOVsi.
7439     unsigned Amt = Inst.getOperand(2).getImm();
7440     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7441     // A shift by 32 should be encoded as 0 when permitted
7442     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7443       Amt = 0;
7444     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7445     MCInst TmpInst;
7446     TmpInst.setOpcode(Opc);
7447     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7448     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7449     if (Opc == ARM::MOVsi)
7450       TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7451     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7452     TmpInst.addOperand(Inst.getOperand(4));
7453     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7454     Inst = TmpInst;
7455     return true;
7456   }
7457   case ARM::RRXi: {
7458     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7459     MCInst TmpInst;
7460     TmpInst.setOpcode(ARM::MOVsi);
7461     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7462     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7463     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7464     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7465     TmpInst.addOperand(Inst.getOperand(3));
7466     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7467     Inst = TmpInst;
7468     return true;
7469   }
7470   case ARM::t2LDMIA_UPD: {
7471     // If this is a load of a single register, then we should use
7472     // a post-indexed LDR instruction instead, per the ARM ARM.
7473     if (Inst.getNumOperands() != 5)
7474       return false;
7475     MCInst TmpInst;
7476     TmpInst.setOpcode(ARM::t2LDR_POST);
7477     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7478     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7479     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7480     TmpInst.addOperand(MCOperand::CreateImm(4));
7481     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7482     TmpInst.addOperand(Inst.getOperand(3));
7483     Inst = TmpInst;
7484     return true;
7485   }
7486   case ARM::t2STMDB_UPD: {
7487     // If this is a store of a single register, then we should use
7488     // a pre-indexed STR instruction instead, per the ARM ARM.
7489     if (Inst.getNumOperands() != 5)
7490       return false;
7491     MCInst TmpInst;
7492     TmpInst.setOpcode(ARM::t2STR_PRE);
7493     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7494     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7495     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7496     TmpInst.addOperand(MCOperand::CreateImm(-4));
7497     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7498     TmpInst.addOperand(Inst.getOperand(3));
7499     Inst = TmpInst;
7500     return true;
7501   }
7502   case ARM::LDMIA_UPD:
7503     // If this is a load of a single register via a 'pop', then we should use
7504     // a post-indexed LDR instruction instead, per the ARM ARM.
7505     if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7506         Inst.getNumOperands() == 5) {
7507       MCInst TmpInst;
7508       TmpInst.setOpcode(ARM::LDR_POST_IMM);
7509       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7510       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7511       TmpInst.addOperand(Inst.getOperand(1)); // Rn
7512       TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7513       TmpInst.addOperand(MCOperand::CreateImm(4));
7514       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7515       TmpInst.addOperand(Inst.getOperand(3));
7516       Inst = TmpInst;
7517       return true;
7518     }
7519     break;
7520   case ARM::STMDB_UPD:
7521     // If this is a store of a single register via a 'push', then we should use
7522     // a pre-indexed STR instruction instead, per the ARM ARM.
7523     if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7524         Inst.getNumOperands() == 5) {
7525       MCInst TmpInst;
7526       TmpInst.setOpcode(ARM::STR_PRE_IMM);
7527       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7528       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7529       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7530       TmpInst.addOperand(MCOperand::CreateImm(-4));
7531       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7532       TmpInst.addOperand(Inst.getOperand(3));
7533       Inst = TmpInst;
7534     }
7535     break;
7536   case ARM::t2ADDri12:
7537     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7538     // mnemonic was used (not "addw"), encoding T3 is preferred.
7539     if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7540         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7541       break;
7542     Inst.setOpcode(ARM::t2ADDri);
7543     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7544     break;
7545   case ARM::t2SUBri12:
7546     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7547     // mnemonic was used (not "subw"), encoding T3 is preferred.
7548     if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7549         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7550       break;
7551     Inst.setOpcode(ARM::t2SUBri);
7552     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7553     break;
7554   case ARM::tADDi8:
7555     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7556     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7557     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7558     // to encoding T1 if <Rd> is omitted."
7559     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7560       Inst.setOpcode(ARM::tADDi3);
7561       return true;
7562     }
7563     break;
7564   case ARM::tSUBi8:
7565     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7566     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7567     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7568     // to encoding T1 if <Rd> is omitted."
7569     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7570       Inst.setOpcode(ARM::tSUBi3);
7571       return true;
7572     }
7573     break;
7574   case ARM::t2ADDri:
7575   case ARM::t2SUBri: {
7576     // If the destination and first source operand are the same, and
7577     // the flags are compatible with the current IT status, use encoding T2
7578     // instead of T3. For compatibility with the system 'as'. Make sure the
7579     // wide encoding wasn't explicit.
7580     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7581         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7582         (unsigned)Inst.getOperand(2).getImm() > 255 ||
7583         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7584         (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7585         (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7586          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7587       break;
7588     MCInst TmpInst;
7589     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7590                       ARM::tADDi8 : ARM::tSUBi8);
7591     TmpInst.addOperand(Inst.getOperand(0));
7592     TmpInst.addOperand(Inst.getOperand(5));
7593     TmpInst.addOperand(Inst.getOperand(0));
7594     TmpInst.addOperand(Inst.getOperand(2));
7595     TmpInst.addOperand(Inst.getOperand(3));
7596     TmpInst.addOperand(Inst.getOperand(4));
7597     Inst = TmpInst;
7598     return true;
7599   }
7600   case ARM::t2ADDrr: {
7601     // If the destination and first source operand are the same, and
7602     // there's no setting of the flags, use encoding T2 instead of T3.
7603     // Note that this is only for ADD, not SUB. This mirrors the system
7604     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7605     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7606         Inst.getOperand(5).getReg() != 0 ||
7607         (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7608          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7609       break;
7610     MCInst TmpInst;
7611     TmpInst.setOpcode(ARM::tADDhirr);
7612     TmpInst.addOperand(Inst.getOperand(0));
7613     TmpInst.addOperand(Inst.getOperand(0));
7614     TmpInst.addOperand(Inst.getOperand(2));
7615     TmpInst.addOperand(Inst.getOperand(3));
7616     TmpInst.addOperand(Inst.getOperand(4));
7617     Inst = TmpInst;
7618     return true;
7619   }
7620   case ARM::tADDrSP: {
7621     // If the non-SP source operand and the destination operand are not the
7622     // same, we need to use the 32-bit encoding if it's available.
7623     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7624       Inst.setOpcode(ARM::t2ADDrr);
7625       Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7626       return true;
7627     }
7628     break;
7629   }
7630   case ARM::tB:
7631     // A Thumb conditional branch outside of an IT block is a tBcc.
7632     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7633       Inst.setOpcode(ARM::tBcc);
7634       return true;
7635     }
7636     break;
7637   case ARM::t2B:
7638     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7639     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7640       Inst.setOpcode(ARM::t2Bcc);
7641       return true;
7642     }
7643     break;
7644   case ARM::t2Bcc:
7645     // If the conditional is AL or we're in an IT block, we really want t2B.
7646     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7647       Inst.setOpcode(ARM::t2B);
7648       return true;
7649     }
7650     break;
7651   case ARM::tBcc:
7652     // If the conditional is AL, we really want tB.
7653     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7654       Inst.setOpcode(ARM::tB);
7655       return true;
7656     }
7657     break;
7658   case ARM::tLDMIA: {
7659     // If the register list contains any high registers, or if the writeback
7660     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7661     // instead if we're in Thumb2. Otherwise, this should have generated
7662     // an error in validateInstruction().
7663     unsigned Rn = Inst.getOperand(0).getReg();
7664     bool hasWritebackToken =
7665       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7666        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7667     bool listContainsBase;
7668     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7669         (!listContainsBase && !hasWritebackToken) ||
7670         (listContainsBase && hasWritebackToken)) {
7671       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7672       assert (isThumbTwo());
7673       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7674       // If we're switching to the updating version, we need to insert
7675       // the writeback tied operand.
7676       if (hasWritebackToken)
7677         Inst.insert(Inst.begin(),
7678                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7679       return true;
7680     }
7681     break;
7682   }
7683   case ARM::tSTMIA_UPD: {
7684     // If the register list contains any high registers, we need to use
7685     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7686     // should have generated an error in validateInstruction().
7687     unsigned Rn = Inst.getOperand(0).getReg();
7688     bool listContainsBase;
7689     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7690       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7691       assert (isThumbTwo());
7692       Inst.setOpcode(ARM::t2STMIA_UPD);
7693       return true;
7694     }
7695     break;
7696   }
7697   case ARM::tPOP: {
7698     bool listContainsBase;
7699     // If the register list contains any high registers, we need to use
7700     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7701     // should have generated an error in validateInstruction().
7702     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7703       return false;
7704     assert (isThumbTwo());
7705     Inst.setOpcode(ARM::t2LDMIA_UPD);
7706     // Add the base register and writeback operands.
7707     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7708     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7709     return true;
7710   }
7711   case ARM::tPUSH: {
7712     bool listContainsBase;
7713     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7714       return false;
7715     assert (isThumbTwo());
7716     Inst.setOpcode(ARM::t2STMDB_UPD);
7717     // Add the base register and writeback operands.
7718     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7719     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7720     return true;
7721   }
7722   case ARM::t2MOVi: {
7723     // If we can use the 16-bit encoding and the user didn't explicitly
7724     // request the 32-bit variant, transform it here.
7725     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7726         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7727         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7728          Inst.getOperand(4).getReg() == ARM::CPSR) ||
7729         (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7730         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7731          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7732       // The operands aren't in the same order for tMOVi8...
7733       MCInst TmpInst;
7734       TmpInst.setOpcode(ARM::tMOVi8);
7735       TmpInst.addOperand(Inst.getOperand(0));
7736       TmpInst.addOperand(Inst.getOperand(4));
7737       TmpInst.addOperand(Inst.getOperand(1));
7738       TmpInst.addOperand(Inst.getOperand(2));
7739       TmpInst.addOperand(Inst.getOperand(3));
7740       Inst = TmpInst;
7741       return true;
7742     }
7743     break;
7744   }
7745   case ARM::t2MOVr: {
7746     // If we can use the 16-bit encoding and the user didn't explicitly
7747     // request the 32-bit variant, transform it here.
7748     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7749         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7750         Inst.getOperand(2).getImm() == ARMCC::AL &&
7751         Inst.getOperand(4).getReg() == ARM::CPSR &&
7752         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7753          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7754       // The operands aren't the same for tMOV[S]r... (no cc_out)
7755       MCInst TmpInst;
7756       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7757       TmpInst.addOperand(Inst.getOperand(0));
7758       TmpInst.addOperand(Inst.getOperand(1));
7759       TmpInst.addOperand(Inst.getOperand(2));
7760       TmpInst.addOperand(Inst.getOperand(3));
7761       Inst = TmpInst;
7762       return true;
7763     }
7764     break;
7765   }
7766   case ARM::t2SXTH:
7767   case ARM::t2SXTB:
7768   case ARM::t2UXTH:
7769   case ARM::t2UXTB: {
7770     // If we can use the 16-bit encoding and the user didn't explicitly
7771     // request the 32-bit variant, transform it here.
7772     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7773         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7774         Inst.getOperand(2).getImm() == 0 &&
7775         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7776          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7777       unsigned NewOpc;
7778       switch (Inst.getOpcode()) {
7779       default: llvm_unreachable("Illegal opcode!");
7780       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7781       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7782       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7783       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7784       }
7785       // The operands aren't the same for thumb1 (no rotate operand).
7786       MCInst TmpInst;
7787       TmpInst.setOpcode(NewOpc);
7788       TmpInst.addOperand(Inst.getOperand(0));
7789       TmpInst.addOperand(Inst.getOperand(1));
7790       TmpInst.addOperand(Inst.getOperand(3));
7791       TmpInst.addOperand(Inst.getOperand(4));
7792       Inst = TmpInst;
7793       return true;
7794     }
7795     break;
7796   }
7797   case ARM::MOVsi: {
7798     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7799     // rrx shifts and asr/lsr of #32 is encoded as 0
7800     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7801       return false;
7802     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7803       // Shifting by zero is accepted as a vanilla 'MOVr'
7804       MCInst TmpInst;
7805       TmpInst.setOpcode(ARM::MOVr);
7806       TmpInst.addOperand(Inst.getOperand(0));
7807       TmpInst.addOperand(Inst.getOperand(1));
7808       TmpInst.addOperand(Inst.getOperand(3));
7809       TmpInst.addOperand(Inst.getOperand(4));
7810       TmpInst.addOperand(Inst.getOperand(5));
7811       Inst = TmpInst;
7812       return true;
7813     }
7814     return false;
7815   }
7816   case ARM::ANDrsi:
7817   case ARM::ORRrsi:
7818   case ARM::EORrsi:
7819   case ARM::BICrsi:
7820   case ARM::SUBrsi:
7821   case ARM::ADDrsi: {
7822     unsigned newOpc;
7823     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7824     if (SOpc == ARM_AM::rrx) return false;
7825     switch (Inst.getOpcode()) {
7826     default: llvm_unreachable("unexpected opcode!");
7827     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7828     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7829     case ARM::EORrsi: newOpc = ARM::EORrr; break;
7830     case ARM::BICrsi: newOpc = ARM::BICrr; break;
7831     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7832     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7833     }
7834     // If the shift is by zero, use the non-shifted instruction definition.
7835     // The exception is for right shifts, where 0 == 32
7836     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7837         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7838       MCInst TmpInst;
7839       TmpInst.setOpcode(newOpc);
7840       TmpInst.addOperand(Inst.getOperand(0));
7841       TmpInst.addOperand(Inst.getOperand(1));
7842       TmpInst.addOperand(Inst.getOperand(2));
7843       TmpInst.addOperand(Inst.getOperand(4));
7844       TmpInst.addOperand(Inst.getOperand(5));
7845       TmpInst.addOperand(Inst.getOperand(6));
7846       Inst = TmpInst;
7847       return true;
7848     }
7849     return false;
7850   }
7851   case ARM::ITasm:
7852   case ARM::t2IT: {
7853     // The mask bits for all but the first condition are represented as
7854     // the low bit of the condition code value implies 't'. We currently
7855     // always have 1 implies 't', so XOR toggle the bits if the low bit
7856     // of the condition code is zero.
7857     MCOperand &MO = Inst.getOperand(1);
7858     unsigned Mask = MO.getImm();
7859     unsigned OrigMask = Mask;
7860     unsigned TZ = countTrailingZeros(Mask);
7861     if ((Inst.getOperand(0).getImm() & 1) == 0) {
7862       assert(Mask && TZ <= 3 && "illegal IT mask value!");
7863       Mask ^= (0xE << TZ) & 0xF;
7864     }
7865     MO.setImm(Mask);
7866 
7867     // Set up the IT block state according to the IT instruction we just
7868     // matched.
7869     assert(!inITBlock() && "nested IT blocks?!");
7870     ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7871     ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7872     ITState.CurPosition = 0;
7873     ITState.FirstCond = true;
7874     break;
7875   }
7876   case ARM::t2LSLrr:
7877   case ARM::t2LSRrr:
7878   case ARM::t2ASRrr:
7879   case ARM::t2SBCrr:
7880   case ARM::t2RORrr:
7881   case ARM::t2BICrr:
7882   {
7883     // Assemblers should use the narrow encodings of these instructions when permissible.
7884     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7885          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7886         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7887         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7888          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7889         (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7890          !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7891       unsigned NewOpc;
7892       switch (Inst.getOpcode()) {
7893         default: llvm_unreachable("unexpected opcode");
7894         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7895         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7896         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7897         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7898         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7899         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7900       }
7901       MCInst TmpInst;
7902       TmpInst.setOpcode(NewOpc);
7903       TmpInst.addOperand(Inst.getOperand(0));
7904       TmpInst.addOperand(Inst.getOperand(5));
7905       TmpInst.addOperand(Inst.getOperand(1));
7906       TmpInst.addOperand(Inst.getOperand(2));
7907       TmpInst.addOperand(Inst.getOperand(3));
7908       TmpInst.addOperand(Inst.getOperand(4));
7909       Inst = TmpInst;
7910       return true;
7911     }
7912     return false;
7913   }
7914   case ARM::t2ANDrr:
7915   case ARM::t2EORrr:
7916   case ARM::t2ADCrr:
7917   case ARM::t2ORRrr:
7918   {
7919     // Assemblers should use the narrow encodings of these instructions when permissible.
7920     // These instructions are special in that they are commutable, so shorter encodings
7921     // are available more often.
7922     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7923          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7924         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7925          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7926         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7927          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7928         (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7929          !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7930       unsigned NewOpc;
7931       switch (Inst.getOpcode()) {
7932         default: llvm_unreachable("unexpected opcode");
7933         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7934         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7935         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7936         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7937       }
7938       MCInst TmpInst;
7939       TmpInst.setOpcode(NewOpc);
7940       TmpInst.addOperand(Inst.getOperand(0));
7941       TmpInst.addOperand(Inst.getOperand(5));
7942       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7943         TmpInst.addOperand(Inst.getOperand(1));
7944         TmpInst.addOperand(Inst.getOperand(2));
7945       } else {
7946         TmpInst.addOperand(Inst.getOperand(2));
7947         TmpInst.addOperand(Inst.getOperand(1));
7948       }
7949       TmpInst.addOperand(Inst.getOperand(3));
7950       TmpInst.addOperand(Inst.getOperand(4));
7951       Inst = TmpInst;
7952       return true;
7953     }
7954     return false;
7955   }
7956   }
7957   return false;
7958 }
7959 
7960 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7961   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7962   // suffix depending on whether they're in an IT block or not.
7963   unsigned Opc = Inst.getOpcode();
7964   const MCInstrDesc &MCID = MII.get(Opc);
7965   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7966     assert(MCID.hasOptionalDef() &&
7967            "optionally flag setting instruction missing optional def operand");
7968     assert(MCID.NumOperands == Inst.getNumOperands() &&
7969            "operand count mismatch!");
7970     // Find the optional-def operand (cc_out).
7971     unsigned OpNo;
7972     for (OpNo = 0;
7973          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7974          ++OpNo)
7975       ;
7976     // If we're parsing Thumb1, reject it completely.
7977     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7978       return Match_MnemonicFail;
7979     // If we're parsing Thumb2, which form is legal depends on whether we're
7980     // in an IT block.
7981     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7982         !inITBlock())
7983       return Match_RequiresITBlock;
7984     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7985         inITBlock())
7986       return Match_RequiresNotITBlock;
7987   }
7988   // Some high-register supporting Thumb1 encodings only allow both registers
7989   // to be from r0-r7 when in Thumb2.
7990   else if (Opc == ARM::tADDhirr && isThumbOne() &&
7991            isARMLowRegister(Inst.getOperand(1).getReg()) &&
7992            isARMLowRegister(Inst.getOperand(2).getReg()))
7993     return Match_RequiresThumb2;
7994   // Others only require ARMv6 or later.
7995   else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7996            isARMLowRegister(Inst.getOperand(0).getReg()) &&
7997            isARMLowRegister(Inst.getOperand(1).getReg()))
7998     return Match_RequiresV6;
7999   return Match_Success;
8000 }
8001 
8002 namespace llvm {
8003 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8004   return true; // In an assembly source, no need to second-guess
8005 }
8006 }
8007 
8008 static const char *getSubtargetFeatureName(unsigned Val);
8009 bool ARMAsmParser::
8010 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8011                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
8012                         MCStreamer &Out, unsigned &ErrorInfo,
8013                         bool MatchingInlineAsm) {
8014   MCInst Inst;
8015   unsigned MatchResult;
8016 
8017   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8018                                      MatchingInlineAsm);
8019   switch (MatchResult) {
8020   default: break;
8021   case Match_Success:
8022     // Context sensitive operand constraints aren't handled by the matcher,
8023     // so check them here.
8024     if (validateInstruction(Inst, Operands)) {
8025       // Still progress the IT block, otherwise one wrong condition causes
8026       // nasty cascading errors.
8027       forwardITPosition();
8028       return true;
8029     }
8030 
8031     { // processInstruction() updates inITBlock state, we need to save it away
8032       bool wasInITBlock = inITBlock();
8033 
8034       // Some instructions need post-processing to, for example, tweak which
8035       // encoding is selected. Loop on it while changes happen so the
8036       // individual transformations can chain off each other. E.g.,
8037       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8038       while (processInstruction(Inst, Operands))
8039         ;
8040 
8041       // Only after the instruction is fully processed, we can validate it
8042       if (wasInITBlock && hasV8Ops() && isThumb() &&
8043           !isV8EligibleForIT(&Inst)) {
8044         Warning(IDLoc, "deprecated instruction in IT block");
8045       }
8046     }
8047 
8048     // Only move forward at the very end so that everything in validate
8049     // and process gets a consistent answer about whether we're in an IT
8050     // block.
8051     forwardITPosition();
8052 
8053     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8054     // doesn't actually encode.
8055     if (Inst.getOpcode() == ARM::ITasm)
8056       return false;
8057 
8058     Inst.setLoc(IDLoc);
8059     Out.EmitInstruction(Inst, STI);
8060     return false;
8061   case Match_MissingFeature: {
8062     assert(ErrorInfo && "Unknown missing feature!");
8063     // Special case the error message for the very common case where only
8064     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8065     std::string Msg = "instruction requires:";
8066     unsigned Mask = 1;
8067     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8068       if (ErrorInfo & Mask) {
8069         Msg += " ";
8070         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8071       }
8072       Mask <<= 1;
8073     }
8074     return Error(IDLoc, Msg);
8075   }
8076   case Match_InvalidOperand: {
8077     SMLoc ErrorLoc = IDLoc;
8078     if (ErrorInfo != ~0U) {
8079       if (ErrorInfo >= Operands.size())
8080         return Error(IDLoc, "too few operands for instruction");
8081 
8082       ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8083       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8084     }
8085 
8086     return Error(ErrorLoc, "invalid operand for instruction");
8087   }
8088   case Match_MnemonicFail:
8089     return Error(IDLoc, "invalid instruction",
8090                  ((ARMOperand*)Operands[0])->getLocRange());
8091   case Match_RequiresNotITBlock:
8092     return Error(IDLoc, "flag setting instruction only valid outside IT block");
8093   case Match_RequiresITBlock:
8094     return Error(IDLoc, "instruction only valid inside IT block");
8095   case Match_RequiresV6:
8096     return Error(IDLoc, "instruction variant requires ARMv6 or later");
8097   case Match_RequiresThumb2:
8098     return Error(IDLoc, "instruction variant requires Thumb2");
8099   case Match_ImmRange0_15: {
8100     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8101     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8102     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8103   }
8104   case Match_ImmRange0_239: {
8105     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8106     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8107     return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8108   }
8109   case Match_AlignedMemoryRequiresNone:
8110   case Match_DupAlignedMemoryRequiresNone:
8111   case Match_AlignedMemoryRequires16:
8112   case Match_DupAlignedMemoryRequires16:
8113   case Match_AlignedMemoryRequires32:
8114   case Match_DupAlignedMemoryRequires32:
8115   case Match_AlignedMemoryRequires64:
8116   case Match_DupAlignedMemoryRequires64:
8117   case Match_AlignedMemoryRequires64or128:
8118   case Match_DupAlignedMemoryRequires64or128:
8119   case Match_AlignedMemoryRequires64or128or256:
8120   {
8121     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getAlignmentLoc();
8122     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8123     switch (MatchResult) {
8124       default:
8125         llvm_unreachable("Missing Match_Aligned type");
8126       case Match_AlignedMemoryRequiresNone:
8127       case Match_DupAlignedMemoryRequiresNone:
8128         return Error(ErrorLoc, "alignment must be omitted");
8129       case Match_AlignedMemoryRequires16:
8130       case Match_DupAlignedMemoryRequires16:
8131         return Error(ErrorLoc, "alignment must be 16 or omitted");
8132       case Match_AlignedMemoryRequires32:
8133       case Match_DupAlignedMemoryRequires32:
8134         return Error(ErrorLoc, "alignment must be 32 or omitted");
8135       case Match_AlignedMemoryRequires64:
8136       case Match_DupAlignedMemoryRequires64:
8137         return Error(ErrorLoc, "alignment must be 64 or omitted");
8138       case Match_AlignedMemoryRequires64or128:
8139       case Match_DupAlignedMemoryRequires64or128:
8140         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8141       case Match_AlignedMemoryRequires64or128or256:
8142         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8143     }
8144   }
8145   }
8146 
8147   llvm_unreachable("Implement any new match types added!");
8148 }
8149 
8150 /// parseDirective parses the arm specific directives
8151 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8152   const MCObjectFileInfo::Environment Format =
8153     getContext().getObjectFileInfo()->getObjectFileType();
8154   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8155 
8156   StringRef IDVal = DirectiveID.getIdentifier();
8157   if (IDVal == ".word")
8158     return parseLiteralValues(4, DirectiveID.getLoc());
8159   else if (IDVal == ".short" || IDVal == ".hword")
8160     return parseLiteralValues(2, DirectiveID.getLoc());
8161   else if (IDVal == ".thumb")
8162     return parseDirectiveThumb(DirectiveID.getLoc());
8163   else if (IDVal == ".arm")
8164     return parseDirectiveARM(DirectiveID.getLoc());
8165   else if (IDVal == ".thumb_func")
8166     return parseDirectiveThumbFunc(DirectiveID.getLoc());
8167   else if (IDVal == ".code")
8168     return parseDirectiveCode(DirectiveID.getLoc());
8169   else if (IDVal == ".syntax")
8170     return parseDirectiveSyntax(DirectiveID.getLoc());
8171   else if (IDVal == ".unreq")
8172     return parseDirectiveUnreq(DirectiveID.getLoc());
8173   else if (IDVal == ".fnend")
8174     return parseDirectiveFnEnd(DirectiveID.getLoc());
8175   else if (IDVal == ".cantunwind")
8176     return parseDirectiveCantUnwind(DirectiveID.getLoc());
8177   else if (IDVal == ".personality")
8178     return parseDirectivePersonality(DirectiveID.getLoc());
8179   else if (IDVal == ".handlerdata")
8180     return parseDirectiveHandlerData(DirectiveID.getLoc());
8181   else if (IDVal == ".setfp")
8182     return parseDirectiveSetFP(DirectiveID.getLoc());
8183   else if (IDVal == ".pad")
8184     return parseDirectivePad(DirectiveID.getLoc());
8185   else if (IDVal == ".save")
8186     return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8187   else if (IDVal == ".vsave")
8188     return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8189   else if (IDVal == ".ltorg" || IDVal == ".pool")
8190     return parseDirectiveLtorg(DirectiveID.getLoc());
8191   else if (IDVal == ".even")
8192     return parseDirectiveEven(DirectiveID.getLoc());
8193   else if (IDVal == ".personalityindex")
8194     return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8195   else if (IDVal == ".unwind_raw")
8196     return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8197   else if (IDVal == ".movsp")
8198     return parseDirectiveMovSP(DirectiveID.getLoc());
8199   else if (IDVal == ".arch_extension")
8200     return parseDirectiveArchExtension(DirectiveID.getLoc());
8201   else if (IDVal == ".align")
8202     return parseDirectiveAlign(DirectiveID.getLoc());
8203   else if (IDVal == ".thumb_set")
8204     return parseDirectiveThumbSet(DirectiveID.getLoc());
8205 
8206   if (!IsMachO) {
8207     if (IDVal == ".arch")
8208       return parseDirectiveArch(DirectiveID.getLoc());
8209     else if (IDVal == ".cpu")
8210       return parseDirectiveCPU(DirectiveID.getLoc());
8211     else if (IDVal == ".eabi_attribute")
8212       return parseDirectiveEabiAttr(DirectiveID.getLoc());
8213     else if (IDVal == ".fpu")
8214       return parseDirectiveFPU(DirectiveID.getLoc());
8215     else if (IDVal == ".fnstart")
8216       return parseDirectiveFnStart(DirectiveID.getLoc());
8217     else if (IDVal == ".inst")
8218       return parseDirectiveInst(DirectiveID.getLoc());
8219     else if (IDVal == ".inst.n")
8220       return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8221     else if (IDVal == ".inst.w")
8222       return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8223     else if (IDVal == ".object_arch")
8224       return parseDirectiveObjectArch(DirectiveID.getLoc());
8225     else if (IDVal == ".tlsdescseq")
8226       return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8227   }
8228 
8229   return true;
8230 }
8231 
8232 /// parseLiteralValues
8233 ///  ::= .hword expression [, expression]*
8234 ///  ::= .short expression [, expression]*
8235 ///  ::= .word expression [, expression]*
8236 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8237   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8238     for (;;) {
8239       const MCExpr *Value;
8240       if (getParser().parseExpression(Value)) {
8241         Parser.eatToEndOfStatement();
8242         return false;
8243       }
8244 
8245       getParser().getStreamer().EmitValue(Value, Size);
8246 
8247       if (getLexer().is(AsmToken::EndOfStatement))
8248         break;
8249 
8250       // FIXME: Improve diagnostic.
8251       if (getLexer().isNot(AsmToken::Comma)) {
8252         Error(L, "unexpected token in directive");
8253         return false;
8254       }
8255       Parser.Lex();
8256     }
8257   }
8258 
8259   Parser.Lex();
8260   return false;
8261 }
8262 
8263 /// parseDirectiveThumb
8264 ///  ::= .thumb
8265 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8266   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8267     Error(L, "unexpected token in directive");
8268     return false;
8269   }
8270   Parser.Lex();
8271 
8272   if (!hasThumb()) {
8273     Error(L, "target does not support Thumb mode");
8274     return false;
8275   }
8276 
8277   if (!isThumb())
8278     SwitchMode();
8279 
8280   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8281   return false;
8282 }
8283 
8284 /// parseDirectiveARM
8285 ///  ::= .arm
8286 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8287   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8288     Error(L, "unexpected token in directive");
8289     return false;
8290   }
8291   Parser.Lex();
8292 
8293   if (!hasARM()) {
8294     Error(L, "target does not support ARM mode");
8295     return false;
8296   }
8297 
8298   if (isThumb())
8299     SwitchMode();
8300 
8301   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8302   return false;
8303 }
8304 
8305 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8306   if (NextSymbolIsThumb) {
8307     getParser().getStreamer().EmitThumbFunc(Symbol);
8308     NextSymbolIsThumb = false;
8309     return;
8310   }
8311 
8312   if (!isThumb())
8313     return;
8314 
8315   const MCObjectFileInfo::Environment Format =
8316     getContext().getObjectFileInfo()->getObjectFileType();
8317   switch (Format) {
8318   case MCObjectFileInfo::IsCOFF: {
8319     const MCSymbolData &SD =
8320       getParser().getStreamer().getOrCreateSymbolData(Symbol);
8321     char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
8322     if (SD.getFlags() & (Type << COFF::SF_TypeShift))
8323       getParser().getStreamer().EmitThumbFunc(Symbol);
8324     break;
8325   }
8326   case MCObjectFileInfo::IsELF: {
8327     const MCSymbolData &SD =
8328       getParser().getStreamer().getOrCreateSymbolData(Symbol);
8329     if (MCELF::GetType(SD) & (ELF::STT_FUNC << ELF_STT_Shift))
8330       getParser().getStreamer().EmitThumbFunc(Symbol);
8331     break;
8332   }
8333   case MCObjectFileInfo::IsMachO:
8334     break;
8335   }
8336 }
8337 
8338 /// parseDirectiveThumbFunc
8339 ///  ::= .thumbfunc symbol_name
8340 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8341   const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8342   bool isMachO = MAI->hasSubsectionsViaSymbols();
8343 
8344   // Darwin asm has (optionally) function name after .thumb_func direction
8345   // ELF doesn't
8346   if (isMachO) {
8347     const AsmToken &Tok = Parser.getTok();
8348     if (Tok.isNot(AsmToken::EndOfStatement)) {
8349       if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8350         Error(L, "unexpected token in .thumb_func directive");
8351         return false;
8352       }
8353 
8354       MCSymbol *Func =
8355           getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8356       getParser().getStreamer().EmitThumbFunc(Func);
8357       Parser.Lex(); // Consume the identifier token.
8358       return false;
8359     }
8360   }
8361 
8362   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8363     Error(L, "unexpected token in directive");
8364     return false;
8365   }
8366 
8367   NextSymbolIsThumb = true;
8368   return false;
8369 }
8370 
8371 /// parseDirectiveSyntax
8372 ///  ::= .syntax unified | divided
8373 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8374   const AsmToken &Tok = Parser.getTok();
8375   if (Tok.isNot(AsmToken::Identifier)) {
8376     Error(L, "unexpected token in .syntax directive");
8377     return false;
8378   }
8379 
8380   StringRef Mode = Tok.getString();
8381   if (Mode == "unified" || Mode == "UNIFIED") {
8382     Parser.Lex();
8383   } else if (Mode == "divided" || Mode == "DIVIDED") {
8384     Error(L, "'.syntax divided' arm asssembly not supported");
8385     return false;
8386   } else {
8387     Error(L, "unrecognized syntax mode in .syntax directive");
8388     return false;
8389   }
8390 
8391   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8392     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8393     return false;
8394   }
8395   Parser.Lex();
8396 
8397   // TODO tell the MC streamer the mode
8398   // getParser().getStreamer().Emit???();
8399   return false;
8400 }
8401 
8402 /// parseDirectiveCode
8403 ///  ::= .code 16 | 32
8404 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8405   const AsmToken &Tok = Parser.getTok();
8406   if (Tok.isNot(AsmToken::Integer)) {
8407     Error(L, "unexpected token in .code directive");
8408     return false;
8409   }
8410   int64_t Val = Parser.getTok().getIntVal();
8411   if (Val != 16 && Val != 32) {
8412     Error(L, "invalid operand to .code directive");
8413     return false;
8414   }
8415   Parser.Lex();
8416 
8417   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8418     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8419     return false;
8420   }
8421   Parser.Lex();
8422 
8423   if (Val == 16) {
8424     if (!hasThumb()) {
8425       Error(L, "target does not support Thumb mode");
8426       return false;
8427     }
8428 
8429     if (!isThumb())
8430       SwitchMode();
8431     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8432   } else {
8433     if (!hasARM()) {
8434       Error(L, "target does not support ARM mode");
8435       return false;
8436     }
8437 
8438     if (isThumb())
8439       SwitchMode();
8440     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8441   }
8442 
8443   return false;
8444 }
8445 
8446 /// parseDirectiveReq
8447 ///  ::= name .req registername
8448 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8449   Parser.Lex(); // Eat the '.req' token.
8450   unsigned Reg;
8451   SMLoc SRegLoc, ERegLoc;
8452   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8453     Parser.eatToEndOfStatement();
8454     Error(SRegLoc, "register name expected");
8455     return false;
8456   }
8457 
8458   // Shouldn't be anything else.
8459   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8460     Parser.eatToEndOfStatement();
8461     Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8462     return false;
8463   }
8464 
8465   Parser.Lex(); // Consume the EndOfStatement
8466 
8467   if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8468     Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8469     return false;
8470   }
8471 
8472   return false;
8473 }
8474 
8475 /// parseDirectiveUneq
8476 ///  ::= .unreq registername
8477 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8478   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8479     Parser.eatToEndOfStatement();
8480     Error(L, "unexpected input in .unreq directive.");
8481     return false;
8482   }
8483   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8484   Parser.Lex(); // Eat the identifier.
8485   return false;
8486 }
8487 
8488 /// parseDirectiveArch
8489 ///  ::= .arch token
8490 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8491   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8492 
8493   unsigned ID = StringSwitch<unsigned>(Arch)
8494 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8495     .Case(NAME, ARM::ID)
8496 #define ARM_ARCH_ALIAS(NAME, ID) \
8497     .Case(NAME, ARM::ID)
8498 #include "MCTargetDesc/ARMArchName.def"
8499     .Default(ARM::INVALID_ARCH);
8500 
8501   if (ID == ARM::INVALID_ARCH) {
8502     Error(L, "Unknown arch name");
8503     return false;
8504   }
8505 
8506   getTargetStreamer().emitArch(ID);
8507   return false;
8508 }
8509 
8510 /// parseDirectiveEabiAttr
8511 ///  ::= .eabi_attribute int, int [, "str"]
8512 ///  ::= .eabi_attribute Tag_name, int [, "str"]
8513 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8514   int64_t Tag;
8515   SMLoc TagLoc;
8516   TagLoc = Parser.getTok().getLoc();
8517   if (Parser.getTok().is(AsmToken::Identifier)) {
8518     StringRef Name = Parser.getTok().getIdentifier();
8519     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8520     if (Tag == -1) {
8521       Error(TagLoc, "attribute name not recognised: " + Name);
8522       Parser.eatToEndOfStatement();
8523       return false;
8524     }
8525     Parser.Lex();
8526   } else {
8527     const MCExpr *AttrExpr;
8528 
8529     TagLoc = Parser.getTok().getLoc();
8530     if (Parser.parseExpression(AttrExpr)) {
8531       Parser.eatToEndOfStatement();
8532       return false;
8533     }
8534 
8535     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8536     if (!CE) {
8537       Error(TagLoc, "expected numeric constant");
8538       Parser.eatToEndOfStatement();
8539       return false;
8540     }
8541 
8542     Tag = CE->getValue();
8543   }
8544 
8545   if (Parser.getTok().isNot(AsmToken::Comma)) {
8546     Error(Parser.getTok().getLoc(), "comma expected");
8547     Parser.eatToEndOfStatement();
8548     return false;
8549   }
8550   Parser.Lex(); // skip comma
8551 
8552   StringRef StringValue = "";
8553   bool IsStringValue = false;
8554 
8555   int64_t IntegerValue = 0;
8556   bool IsIntegerValue = false;
8557 
8558   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8559     IsStringValue = true;
8560   else if (Tag == ARMBuildAttrs::compatibility) {
8561     IsStringValue = true;
8562     IsIntegerValue = true;
8563   } else if (Tag < 32 || Tag % 2 == 0)
8564     IsIntegerValue = true;
8565   else if (Tag % 2 == 1)
8566     IsStringValue = true;
8567   else
8568     llvm_unreachable("invalid tag type");
8569 
8570   if (IsIntegerValue) {
8571     const MCExpr *ValueExpr;
8572     SMLoc ValueExprLoc = Parser.getTok().getLoc();
8573     if (Parser.parseExpression(ValueExpr)) {
8574       Parser.eatToEndOfStatement();
8575       return false;
8576     }
8577 
8578     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8579     if (!CE) {
8580       Error(ValueExprLoc, "expected numeric constant");
8581       Parser.eatToEndOfStatement();
8582       return false;
8583     }
8584 
8585     IntegerValue = CE->getValue();
8586   }
8587 
8588   if (Tag == ARMBuildAttrs::compatibility) {
8589     if (Parser.getTok().isNot(AsmToken::Comma))
8590       IsStringValue = false;
8591     else
8592       Parser.Lex();
8593   }
8594 
8595   if (IsStringValue) {
8596     if (Parser.getTok().isNot(AsmToken::String)) {
8597       Error(Parser.getTok().getLoc(), "bad string constant");
8598       Parser.eatToEndOfStatement();
8599       return false;
8600     }
8601 
8602     StringValue = Parser.getTok().getStringContents();
8603     Parser.Lex();
8604   }
8605 
8606   if (IsIntegerValue && IsStringValue) {
8607     assert(Tag == ARMBuildAttrs::compatibility);
8608     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8609   } else if (IsIntegerValue)
8610     getTargetStreamer().emitAttribute(Tag, IntegerValue);
8611   else if (IsStringValue)
8612     getTargetStreamer().emitTextAttribute(Tag, StringValue);
8613   return false;
8614 }
8615 
8616 /// parseDirectiveCPU
8617 ///  ::= .cpu str
8618 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8619   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8620   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8621   return false;
8622 }
8623 
8624 /// parseDirectiveFPU
8625 ///  ::= .fpu str
8626 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8627   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8628 
8629   unsigned ID = StringSwitch<unsigned>(FPU)
8630 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8631 #include "ARMFPUName.def"
8632     .Default(ARM::INVALID_FPU);
8633 
8634   if (ID == ARM::INVALID_FPU) {
8635     Error(L, "Unknown FPU name");
8636     return false;
8637   }
8638 
8639   getTargetStreamer().emitFPU(ID);
8640   return false;
8641 }
8642 
8643 /// parseDirectiveFnStart
8644 ///  ::= .fnstart
8645 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8646   if (UC.hasFnStart()) {
8647     Error(L, ".fnstart starts before the end of previous one");
8648     UC.emitFnStartLocNotes();
8649     return false;
8650   }
8651 
8652   // Reset the unwind directives parser state
8653   UC.reset();
8654 
8655   getTargetStreamer().emitFnStart();
8656 
8657   UC.recordFnStart(L);
8658   return false;
8659 }
8660 
8661 /// parseDirectiveFnEnd
8662 ///  ::= .fnend
8663 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8664   // Check the ordering of unwind directives
8665   if (!UC.hasFnStart()) {
8666     Error(L, ".fnstart must precede .fnend directive");
8667     return false;
8668   }
8669 
8670   // Reset the unwind directives parser state
8671   getTargetStreamer().emitFnEnd();
8672 
8673   UC.reset();
8674   return false;
8675 }
8676 
8677 /// parseDirectiveCantUnwind
8678 ///  ::= .cantunwind
8679 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8680   UC.recordCantUnwind(L);
8681 
8682   // Check the ordering of unwind directives
8683   if (!UC.hasFnStart()) {
8684     Error(L, ".fnstart must precede .cantunwind directive");
8685     return false;
8686   }
8687   if (UC.hasHandlerData()) {
8688     Error(L, ".cantunwind can't be used with .handlerdata directive");
8689     UC.emitHandlerDataLocNotes();
8690     return false;
8691   }
8692   if (UC.hasPersonality()) {
8693     Error(L, ".cantunwind can't be used with .personality directive");
8694     UC.emitPersonalityLocNotes();
8695     return false;
8696   }
8697 
8698   getTargetStreamer().emitCantUnwind();
8699   return false;
8700 }
8701 
8702 /// parseDirectivePersonality
8703 ///  ::= .personality name
8704 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8705   bool HasExistingPersonality = UC.hasPersonality();
8706 
8707   UC.recordPersonality(L);
8708 
8709   // Check the ordering of unwind directives
8710   if (!UC.hasFnStart()) {
8711     Error(L, ".fnstart must precede .personality directive");
8712     return false;
8713   }
8714   if (UC.cantUnwind()) {
8715     Error(L, ".personality can't be used with .cantunwind directive");
8716     UC.emitCantUnwindLocNotes();
8717     return false;
8718   }
8719   if (UC.hasHandlerData()) {
8720     Error(L, ".personality must precede .handlerdata directive");
8721     UC.emitHandlerDataLocNotes();
8722     return false;
8723   }
8724   if (HasExistingPersonality) {
8725     Parser.eatToEndOfStatement();
8726     Error(L, "multiple personality directives");
8727     UC.emitPersonalityLocNotes();
8728     return false;
8729   }
8730 
8731   // Parse the name of the personality routine
8732   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8733     Parser.eatToEndOfStatement();
8734     Error(L, "unexpected input in .personality directive.");
8735     return false;
8736   }
8737   StringRef Name(Parser.getTok().getIdentifier());
8738   Parser.Lex();
8739 
8740   MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8741   getTargetStreamer().emitPersonality(PR);
8742   return false;
8743 }
8744 
8745 /// parseDirectiveHandlerData
8746 ///  ::= .handlerdata
8747 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8748   UC.recordHandlerData(L);
8749 
8750   // Check the ordering of unwind directives
8751   if (!UC.hasFnStart()) {
8752     Error(L, ".fnstart must precede .personality directive");
8753     return false;
8754   }
8755   if (UC.cantUnwind()) {
8756     Error(L, ".handlerdata can't be used with .cantunwind directive");
8757     UC.emitCantUnwindLocNotes();
8758     return false;
8759   }
8760 
8761   getTargetStreamer().emitHandlerData();
8762   return false;
8763 }
8764 
8765 /// parseDirectiveSetFP
8766 ///  ::= .setfp fpreg, spreg [, offset]
8767 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8768   // Check the ordering of unwind directives
8769   if (!UC.hasFnStart()) {
8770     Error(L, ".fnstart must precede .setfp directive");
8771     return false;
8772   }
8773   if (UC.hasHandlerData()) {
8774     Error(L, ".setfp must precede .handlerdata directive");
8775     return false;
8776   }
8777 
8778   // Parse fpreg
8779   SMLoc FPRegLoc = Parser.getTok().getLoc();
8780   int FPReg = tryParseRegister();
8781   if (FPReg == -1) {
8782     Error(FPRegLoc, "frame pointer register expected");
8783     return false;
8784   }
8785 
8786   // Consume comma
8787   if (Parser.getTok().isNot(AsmToken::Comma)) {
8788     Error(Parser.getTok().getLoc(), "comma expected");
8789     return false;
8790   }
8791   Parser.Lex(); // skip comma
8792 
8793   // Parse spreg
8794   SMLoc SPRegLoc = Parser.getTok().getLoc();
8795   int SPReg = tryParseRegister();
8796   if (SPReg == -1) {
8797     Error(SPRegLoc, "stack pointer register expected");
8798     return false;
8799   }
8800 
8801   if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8802     Error(SPRegLoc, "register should be either $sp or the latest fp register");
8803     return false;
8804   }
8805 
8806   // Update the frame pointer register
8807   UC.saveFPReg(FPReg);
8808 
8809   // Parse offset
8810   int64_t Offset = 0;
8811   if (Parser.getTok().is(AsmToken::Comma)) {
8812     Parser.Lex(); // skip comma
8813 
8814     if (Parser.getTok().isNot(AsmToken::Hash) &&
8815         Parser.getTok().isNot(AsmToken::Dollar)) {
8816       Error(Parser.getTok().getLoc(), "'#' expected");
8817       return false;
8818     }
8819     Parser.Lex(); // skip hash token.
8820 
8821     const MCExpr *OffsetExpr;
8822     SMLoc ExLoc = Parser.getTok().getLoc();
8823     SMLoc EndLoc;
8824     if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8825       Error(ExLoc, "malformed setfp offset");
8826       return false;
8827     }
8828     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8829     if (!CE) {
8830       Error(ExLoc, "setfp offset must be an immediate");
8831       return false;
8832     }
8833 
8834     Offset = CE->getValue();
8835   }
8836 
8837   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8838                                 static_cast<unsigned>(SPReg), Offset);
8839   return false;
8840 }
8841 
8842 /// parseDirective
8843 ///  ::= .pad offset
8844 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8845   // Check the ordering of unwind directives
8846   if (!UC.hasFnStart()) {
8847     Error(L, ".fnstart must precede .pad directive");
8848     return false;
8849   }
8850   if (UC.hasHandlerData()) {
8851     Error(L, ".pad must precede .handlerdata directive");
8852     return false;
8853   }
8854 
8855   // Parse the offset
8856   if (Parser.getTok().isNot(AsmToken::Hash) &&
8857       Parser.getTok().isNot(AsmToken::Dollar)) {
8858     Error(Parser.getTok().getLoc(), "'#' expected");
8859     return false;
8860   }
8861   Parser.Lex(); // skip hash token.
8862 
8863   const MCExpr *OffsetExpr;
8864   SMLoc ExLoc = Parser.getTok().getLoc();
8865   SMLoc EndLoc;
8866   if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8867     Error(ExLoc, "malformed pad offset");
8868     return false;
8869   }
8870   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8871   if (!CE) {
8872     Error(ExLoc, "pad offset must be an immediate");
8873     return false;
8874   }
8875 
8876   getTargetStreamer().emitPad(CE->getValue());
8877   return false;
8878 }
8879 
8880 /// parseDirectiveRegSave
8881 ///  ::= .save  { registers }
8882 ///  ::= .vsave { registers }
8883 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8884   // Check the ordering of unwind directives
8885   if (!UC.hasFnStart()) {
8886     Error(L, ".fnstart must precede .save or .vsave directives");
8887     return false;
8888   }
8889   if (UC.hasHandlerData()) {
8890     Error(L, ".save or .vsave must precede .handlerdata directive");
8891     return false;
8892   }
8893 
8894   // RAII object to make sure parsed operands are deleted.
8895   struct CleanupObject {
8896     SmallVector<MCParsedAsmOperand *, 1> Operands;
8897     ~CleanupObject() {
8898       for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8899         delete Operands[I];
8900     }
8901   } CO;
8902 
8903   // Parse the register list
8904   if (parseRegisterList(CO.Operands))
8905     return false;
8906   ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8907   if (!IsVector && !Op->isRegList()) {
8908     Error(L, ".save expects GPR registers");
8909     return false;
8910   }
8911   if (IsVector && !Op->isDPRRegList()) {
8912     Error(L, ".vsave expects DPR registers");
8913     return false;
8914   }
8915 
8916   getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8917   return false;
8918 }
8919 
8920 /// parseDirectiveInst
8921 ///  ::= .inst opcode [, ...]
8922 ///  ::= .inst.n opcode [, ...]
8923 ///  ::= .inst.w opcode [, ...]
8924 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8925   int Width;
8926 
8927   if (isThumb()) {
8928     switch (Suffix) {
8929     case 'n':
8930       Width = 2;
8931       break;
8932     case 'w':
8933       Width = 4;
8934       break;
8935     default:
8936       Parser.eatToEndOfStatement();
8937       Error(Loc, "cannot determine Thumb instruction size, "
8938                  "use inst.n/inst.w instead");
8939       return false;
8940     }
8941   } else {
8942     if (Suffix) {
8943       Parser.eatToEndOfStatement();
8944       Error(Loc, "width suffixes are invalid in ARM mode");
8945       return false;
8946     }
8947     Width = 4;
8948   }
8949 
8950   if (getLexer().is(AsmToken::EndOfStatement)) {
8951     Parser.eatToEndOfStatement();
8952     Error(Loc, "expected expression following directive");
8953     return false;
8954   }
8955 
8956   for (;;) {
8957     const MCExpr *Expr;
8958 
8959     if (getParser().parseExpression(Expr)) {
8960       Error(Loc, "expected expression");
8961       return false;
8962     }
8963 
8964     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8965     if (!Value) {
8966       Error(Loc, "expected constant expression");
8967       return false;
8968     }
8969 
8970     switch (Width) {
8971     case 2:
8972       if (Value->getValue() > 0xffff) {
8973         Error(Loc, "inst.n operand is too big, use inst.w instead");
8974         return false;
8975       }
8976       break;
8977     case 4:
8978       if (Value->getValue() > 0xffffffff) {
8979         Error(Loc,
8980               StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8981         return false;
8982       }
8983       break;
8984     default:
8985       llvm_unreachable("only supported widths are 2 and 4");
8986     }
8987 
8988     getTargetStreamer().emitInst(Value->getValue(), Suffix);
8989 
8990     if (getLexer().is(AsmToken::EndOfStatement))
8991       break;
8992 
8993     if (getLexer().isNot(AsmToken::Comma)) {
8994       Error(Loc, "unexpected token in directive");
8995       return false;
8996     }
8997 
8998     Parser.Lex();
8999   }
9000 
9001   Parser.Lex();
9002   return false;
9003 }
9004 
9005 /// parseDirectiveLtorg
9006 ///  ::= .ltorg | .pool
9007 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9008   getTargetStreamer().emitCurrentConstantPool();
9009   return false;
9010 }
9011 
9012 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9013   const MCSection *Section = getStreamer().getCurrentSection().first;
9014 
9015   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9016     TokError("unexpected token in directive");
9017     return false;
9018   }
9019 
9020   if (!Section) {
9021     getStreamer().InitSections();
9022     Section = getStreamer().getCurrentSection().first;
9023   }
9024 
9025   assert(Section && "must have section to emit alignment");
9026   if (Section->UseCodeAlign())
9027     getStreamer().EmitCodeAlignment(2);
9028   else
9029     getStreamer().EmitValueToAlignment(2);
9030 
9031   return false;
9032 }
9033 
9034 /// parseDirectivePersonalityIndex
9035 ///   ::= .personalityindex index
9036 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9037   bool HasExistingPersonality = UC.hasPersonality();
9038 
9039   UC.recordPersonalityIndex(L);
9040 
9041   if (!UC.hasFnStart()) {
9042     Parser.eatToEndOfStatement();
9043     Error(L, ".fnstart must precede .personalityindex directive");
9044     return false;
9045   }
9046   if (UC.cantUnwind()) {
9047     Parser.eatToEndOfStatement();
9048     Error(L, ".personalityindex cannot be used with .cantunwind");
9049     UC.emitCantUnwindLocNotes();
9050     return false;
9051   }
9052   if (UC.hasHandlerData()) {
9053     Parser.eatToEndOfStatement();
9054     Error(L, ".personalityindex must precede .handlerdata directive");
9055     UC.emitHandlerDataLocNotes();
9056     return false;
9057   }
9058   if (HasExistingPersonality) {
9059     Parser.eatToEndOfStatement();
9060     Error(L, "multiple personality directives");
9061     UC.emitPersonalityLocNotes();
9062     return false;
9063   }
9064 
9065   const MCExpr *IndexExpression;
9066   SMLoc IndexLoc = Parser.getTok().getLoc();
9067   if (Parser.parseExpression(IndexExpression)) {
9068     Parser.eatToEndOfStatement();
9069     return false;
9070   }
9071 
9072   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9073   if (!CE) {
9074     Parser.eatToEndOfStatement();
9075     Error(IndexLoc, "index must be a constant number");
9076     return false;
9077   }
9078   if (CE->getValue() < 0 ||
9079       CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9080     Parser.eatToEndOfStatement();
9081     Error(IndexLoc, "personality routine index should be in range [0-3]");
9082     return false;
9083   }
9084 
9085   getTargetStreamer().emitPersonalityIndex(CE->getValue());
9086   return false;
9087 }
9088 
9089 /// parseDirectiveUnwindRaw
9090 ///   ::= .unwind_raw offset, opcode [, opcode...]
9091 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9092   if (!UC.hasFnStart()) {
9093     Parser.eatToEndOfStatement();
9094     Error(L, ".fnstart must precede .unwind_raw directives");
9095     return false;
9096   }
9097 
9098   int64_t StackOffset;
9099 
9100   const MCExpr *OffsetExpr;
9101   SMLoc OffsetLoc = getLexer().getLoc();
9102   if (getLexer().is(AsmToken::EndOfStatement) ||
9103       getParser().parseExpression(OffsetExpr)) {
9104     Error(OffsetLoc, "expected expression");
9105     Parser.eatToEndOfStatement();
9106     return false;
9107   }
9108 
9109   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9110   if (!CE) {
9111     Error(OffsetLoc, "offset must be a constant");
9112     Parser.eatToEndOfStatement();
9113     return false;
9114   }
9115 
9116   StackOffset = CE->getValue();
9117 
9118   if (getLexer().isNot(AsmToken::Comma)) {
9119     Error(getLexer().getLoc(), "expected comma");
9120     Parser.eatToEndOfStatement();
9121     return false;
9122   }
9123   Parser.Lex();
9124 
9125   SmallVector<uint8_t, 16> Opcodes;
9126   for (;;) {
9127     const MCExpr *OE;
9128 
9129     SMLoc OpcodeLoc = getLexer().getLoc();
9130     if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9131       Error(OpcodeLoc, "expected opcode expression");
9132       Parser.eatToEndOfStatement();
9133       return false;
9134     }
9135 
9136     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9137     if (!OC) {
9138       Error(OpcodeLoc, "opcode value must be a constant");
9139       Parser.eatToEndOfStatement();
9140       return false;
9141     }
9142 
9143     const int64_t Opcode = OC->getValue();
9144     if (Opcode & ~0xff) {
9145       Error(OpcodeLoc, "invalid opcode");
9146       Parser.eatToEndOfStatement();
9147       return false;
9148     }
9149 
9150     Opcodes.push_back(uint8_t(Opcode));
9151 
9152     if (getLexer().is(AsmToken::EndOfStatement))
9153       break;
9154 
9155     if (getLexer().isNot(AsmToken::Comma)) {
9156       Error(getLexer().getLoc(), "unexpected token in directive");
9157       Parser.eatToEndOfStatement();
9158       return false;
9159     }
9160 
9161     Parser.Lex();
9162   }
9163 
9164   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9165 
9166   Parser.Lex();
9167   return false;
9168 }
9169 
9170 /// parseDirectiveTLSDescSeq
9171 ///   ::= .tlsdescseq tls-variable
9172 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9173   if (getLexer().isNot(AsmToken::Identifier)) {
9174     TokError("expected variable after '.tlsdescseq' directive");
9175     Parser.eatToEndOfStatement();
9176     return false;
9177   }
9178 
9179   const MCSymbolRefExpr *SRE =
9180     MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9181                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9182   Lex();
9183 
9184   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9185     Error(Parser.getTok().getLoc(), "unexpected token");
9186     Parser.eatToEndOfStatement();
9187     return false;
9188   }
9189 
9190   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9191   return false;
9192 }
9193 
9194 /// parseDirectiveMovSP
9195 ///  ::= .movsp reg [, #offset]
9196 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9197   if (!UC.hasFnStart()) {
9198     Parser.eatToEndOfStatement();
9199     Error(L, ".fnstart must precede .movsp directives");
9200     return false;
9201   }
9202   if (UC.getFPReg() != ARM::SP) {
9203     Parser.eatToEndOfStatement();
9204     Error(L, "unexpected .movsp directive");
9205     return false;
9206   }
9207 
9208   SMLoc SPRegLoc = Parser.getTok().getLoc();
9209   int SPReg = tryParseRegister();
9210   if (SPReg == -1) {
9211     Parser.eatToEndOfStatement();
9212     Error(SPRegLoc, "register expected");
9213     return false;
9214   }
9215 
9216   if (SPReg == ARM::SP || SPReg == ARM::PC) {
9217     Parser.eatToEndOfStatement();
9218     Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9219     return false;
9220   }
9221 
9222   int64_t Offset = 0;
9223   if (Parser.getTok().is(AsmToken::Comma)) {
9224     Parser.Lex();
9225 
9226     if (Parser.getTok().isNot(AsmToken::Hash)) {
9227       Error(Parser.getTok().getLoc(), "expected #constant");
9228       Parser.eatToEndOfStatement();
9229       return false;
9230     }
9231     Parser.Lex();
9232 
9233     const MCExpr *OffsetExpr;
9234     SMLoc OffsetLoc = Parser.getTok().getLoc();
9235     if (Parser.parseExpression(OffsetExpr)) {
9236       Parser.eatToEndOfStatement();
9237       Error(OffsetLoc, "malformed offset expression");
9238       return false;
9239     }
9240 
9241     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9242     if (!CE) {
9243       Parser.eatToEndOfStatement();
9244       Error(OffsetLoc, "offset must be an immediate constant");
9245       return false;
9246     }
9247 
9248     Offset = CE->getValue();
9249   }
9250 
9251   getTargetStreamer().emitMovSP(SPReg, Offset);
9252   UC.saveFPReg(SPReg);
9253 
9254   return false;
9255 }
9256 
9257 /// parseDirectiveObjectArch
9258 ///   ::= .object_arch name
9259 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9260   if (getLexer().isNot(AsmToken::Identifier)) {
9261     Error(getLexer().getLoc(), "unexpected token");
9262     Parser.eatToEndOfStatement();
9263     return false;
9264   }
9265 
9266   StringRef Arch = Parser.getTok().getString();
9267   SMLoc ArchLoc = Parser.getTok().getLoc();
9268   getLexer().Lex();
9269 
9270   unsigned ID = StringSwitch<unsigned>(Arch)
9271 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9272     .Case(NAME, ARM::ID)
9273 #define ARM_ARCH_ALIAS(NAME, ID) \
9274     .Case(NAME, ARM::ID)
9275 #include "MCTargetDesc/ARMArchName.def"
9276 #undef ARM_ARCH_NAME
9277 #undef ARM_ARCH_ALIAS
9278     .Default(ARM::INVALID_ARCH);
9279 
9280   if (ID == ARM::INVALID_ARCH) {
9281     Error(ArchLoc, "unknown architecture '" + Arch + "'");
9282     Parser.eatToEndOfStatement();
9283     return false;
9284   }
9285 
9286   getTargetStreamer().emitObjectArch(ID);
9287 
9288   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9289     Error(getLexer().getLoc(), "unexpected token");
9290     Parser.eatToEndOfStatement();
9291   }
9292 
9293   return false;
9294 }
9295 
9296 /// parseDirectiveAlign
9297 ///   ::= .align
9298 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9299   // NOTE: if this is not the end of the statement, fall back to the target
9300   // agnostic handling for this directive which will correctly handle this.
9301   if (getLexer().isNot(AsmToken::EndOfStatement))
9302     return true;
9303 
9304   // '.align' is target specifically handled to mean 2**2 byte alignment.
9305   if (getStreamer().getCurrentSection().first->UseCodeAlign())
9306     getStreamer().EmitCodeAlignment(4, 0);
9307   else
9308     getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9309 
9310   return false;
9311 }
9312 
9313 /// parseDirectiveThumbSet
9314 ///  ::= .thumb_set name, value
9315 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9316   StringRef Name;
9317   if (Parser.parseIdentifier(Name)) {
9318     TokError("expected identifier after '.thumb_set'");
9319     Parser.eatToEndOfStatement();
9320     return false;
9321   }
9322 
9323   if (getLexer().isNot(AsmToken::Comma)) {
9324     TokError("expected comma after name '" + Name + "'");
9325     Parser.eatToEndOfStatement();
9326     return false;
9327   }
9328   Lex();
9329 
9330   const MCExpr *Value;
9331   if (Parser.parseExpression(Value)) {
9332     TokError("missing expression");
9333     Parser.eatToEndOfStatement();
9334     return false;
9335   }
9336 
9337   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9338     TokError("unexpected token");
9339     Parser.eatToEndOfStatement();
9340     return false;
9341   }
9342   Lex();
9343 
9344   MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9345   if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Value)) {
9346     MCSymbol *Sym = getContext().LookupSymbol(SRE->getSymbol().getName());
9347     if (!Sym->isDefined()) {
9348       getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
9349       getStreamer().EmitAssignment(Alias, Value);
9350       return false;
9351     }
9352 
9353     const MCObjectFileInfo::Environment Format =
9354       getContext().getObjectFileInfo()->getObjectFileType();
9355     switch (Format) {
9356     case MCObjectFileInfo::IsCOFF: {
9357       char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
9358       getStreamer().EmitCOFFSymbolType(Type);
9359       // .set values are always local in COFF
9360       getStreamer().EmitSymbolAttribute(Alias, MCSA_Local);
9361       break;
9362     }
9363     case MCObjectFileInfo::IsELF:
9364       getStreamer().EmitSymbolAttribute(Alias, MCSA_ELF_TypeFunction);
9365       break;
9366     case MCObjectFileInfo::IsMachO:
9367       break;
9368     }
9369   }
9370 
9371   // FIXME: set the function as being a thumb function via the assembler
9372   getStreamer().EmitThumbFunc(Alias);
9373   getStreamer().EmitAssignment(Alias, Value);
9374 
9375   return false;
9376 }
9377 
9378 /// Force static initialization.
9379 extern "C" void LLVMInitializeARMAsmParser() {
9380   RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9381   RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9382   RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9383   RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9384 }
9385 
9386 #define GET_REGISTER_MATCHER
9387 #define GET_SUBTARGET_FEATURE_NAME
9388 #define GET_MATCHER_IMPLEMENTATION
9389 #include "ARMGenAsmMatcher.inc"
9390 
9391 static const struct ExtMapEntry {
9392   const char *Extension;
9393   const unsigned ArchCheck;
9394   const uint64_t Features;
9395 } Extensions[] = {
9396   { "crc", Feature_HasV8, ARM::FeatureCRC },
9397   { "crypto",  Feature_HasV8,
9398     ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9399   { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9400   { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9401     ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9402   // FIXME: iWMMXT not supported
9403   { "iwmmxt", Feature_None, 0 },
9404   // FIXME: iWMMXT2 not supported
9405   { "iwmmxt2", Feature_None, 0 },
9406   // FIXME: Maverick not supported
9407   { "maverick", Feature_None, 0 },
9408   { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9409   // FIXME: ARMv6-m OS Extensions feature not checked
9410   { "os", Feature_None, 0 },
9411   // FIXME: Also available in ARMv6-K
9412   { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9413   { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9414   // FIXME: Only available in A-class, isel not predicated
9415   { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9416   // FIXME: xscale not supported
9417   { "xscale", Feature_None, 0 },
9418 };
9419 
9420 /// parseDirectiveArchExtension
9421 ///   ::= .arch_extension [no]feature
9422 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9423   if (getLexer().isNot(AsmToken::Identifier)) {
9424     Error(getLexer().getLoc(), "unexpected token");
9425     Parser.eatToEndOfStatement();
9426     return false;
9427   }
9428 
9429   StringRef Extension = Parser.getTok().getString();
9430   SMLoc ExtLoc = Parser.getTok().getLoc();
9431   getLexer().Lex();
9432 
9433   bool EnableFeature = true;
9434   if (Extension.startswith_lower("no")) {
9435     EnableFeature = false;
9436     Extension = Extension.substr(2);
9437   }
9438 
9439   for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) {
9440     if (Extensions[EI].Extension != Extension)
9441       continue;
9442 
9443     unsigned FB = getAvailableFeatures();
9444     if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
9445       Error(ExtLoc, "architectural extension '" + Extension + "' is not "
9446             "allowed for the current base architecture");
9447       return false;
9448     }
9449 
9450     if (!Extensions[EI].Features)
9451       report_fatal_error("unsupported architectural extension: " + Extension);
9452 
9453     if (EnableFeature)
9454       FB |= ComputeAvailableFeatures(Extensions[EI].Features);
9455     else
9456       FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
9457 
9458     setAvailableFeatures(FB);
9459     return false;
9460   }
9461 
9462   Error(ExtLoc, "unknown architectural extension: " + Extension);
9463   Parser.eatToEndOfStatement();
9464   return false;
9465 }
9466 
9467 // Define this matcher function after the auto-generated include so we
9468 // have the match class enum definitions.
9469 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9470                                                   unsigned Kind) {
9471   ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
9472   // If the kind is a token for a literal immediate, check if our asm
9473   // operand matches. This is for InstAliases which have a fixed-value
9474   // immediate in the syntax.
9475   switch (Kind) {
9476   default: break;
9477   case MCK__35_0:
9478     if (Op->isImm())
9479       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()))
9480         if (CE->getValue() == 0)
9481           return Match_Success;
9482     break;
9483   case MCK_ARMSOImm:
9484     if (Op->isImm()) {
9485       const MCExpr *SOExpr = Op->getImm();
9486       int64_t Value;
9487       if (!SOExpr->EvaluateAsAbsolute(Value))
9488         return Match_Success;
9489       assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
9490              "expression value must be representiable in 32 bits");
9491     }
9492     break;
9493   case MCK_GPRPair:
9494     if (Op->isReg() &&
9495         MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9496       return Match_Success;
9497     break;
9498   }
9499   return Match_InvalidOperand;
9500 }
9501