1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
49 
50 using namespace llvm;
51 
52 namespace {
53 
54 class ARMOperand;
55 
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
57 
58 class UnwindContext {
59   MCAsmParser &Parser;
60 
61   typedef SmallVector<SMLoc, 4> Locs;
62 
63   Locs FnStartLocs;
64   Locs CantUnwindLocs;
65   Locs PersonalityLocs;
66   Locs PersonalityIndexLocs;
67   Locs HandlerDataLocs;
68   int FPReg;
69 
70 public:
71   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
72 
73   bool hasFnStart() const { return !FnStartLocs.empty(); }
74   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76   bool hasPersonality() const {
77     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
78   }
79 
80   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
85 
86   void saveFPReg(int Reg) { FPReg = Reg; }
87   int getFPReg() const { return FPReg; }
88 
89   void emitFnStartLocNotes() const {
90     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
91          FI != FE; ++FI)
92       Parser.Note(*FI, ".fnstart was specified here");
93   }
94   void emitCantUnwindLocNotes() const {
95     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
97       Parser.Note(*UI, ".cantunwind was specified here");
98   }
99   void emitHandlerDataLocNotes() const {
100     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
102       Parser.Note(*HI, ".handlerdata was specified here");
103   }
104   void emitPersonalityLocNotes() const {
105     for (Locs::const_iterator PI = PersonalityLocs.begin(),
106                               PE = PersonalityLocs.end(),
107                               PII = PersonalityIndexLocs.begin(),
108                               PIE = PersonalityIndexLocs.end();
109          PI != PE || PII != PIE;) {
110       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111         Parser.Note(*PI++, ".personality was specified here");
112       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113         Parser.Note(*PII++, ".personalityindex was specified here");
114       else
115         llvm_unreachable(".personality and .personalityindex cannot be "
116                          "at the same location");
117     }
118   }
119 
120   void reset() {
121     FnStartLocs = Locs();
122     CantUnwindLocs = Locs();
123     PersonalityLocs = Locs();
124     HandlerDataLocs = Locs();
125     PersonalityIndexLocs = Locs();
126     FPReg = ARM::SP;
127   }
128 };
129 
130 class ARMAsmParser : public MCTargetAsmParser {
131   MCSubtargetInfo &STI;
132   MCAsmParser &Parser;
133   const MCInstrInfo &MII;
134   const MCRegisterInfo *MRI;
135   UnwindContext UC;
136 
137   ARMTargetStreamer &getTargetStreamer() {
138     assert(getParser().getStreamer().getTargetStreamer() &&
139            "do not have a target streamer");
140     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
141     return static_cast<ARMTargetStreamer &>(TS);
142   }
143 
144   // Map of register aliases registers via the .req directive.
145   StringMap<unsigned> RegisterReqs;
146 
147   bool NextSymbolIsThumb;
148 
149   struct {
150     ARMCC::CondCodes Cond;    // Condition for IT block.
151     unsigned Mask:4;          // Condition mask for instructions.
152                               // Starting at first 1 (from lsb).
153                               //   '1'  condition as indicated in IT.
154                               //   '0'  inverse of condition (else).
155                               // Count of instructions in IT block is
156                               // 4 - trailingzeroes(mask)
157 
158     bool FirstCond;           // Explicit flag for when we're parsing the
159                               // First instruction in the IT block. It's
160                               // implied in the mask, so needs special
161                               // handling.
162 
163     unsigned CurPosition;     // Current position in parsing of IT
164                               // block. In range [0,3]. Initialized
165                               // according to count of instructions in block.
166                               // ~0U if no active IT block.
167   } ITState;
168   bool inITBlock() { return ITState.CurPosition != ~0U;}
169   void forwardITPosition() {
170     if (!inITBlock()) return;
171     // Move to the next instruction in the IT block, if there is one. If not,
172     // mark the block as done.
173     unsigned TZ = countTrailingZeros(ITState.Mask);
174     if (++ITState.CurPosition == 5 - TZ)
175       ITState.CurPosition = ~0U; // Done with the IT block after this.
176   }
177 
178 
179   MCAsmParser &getParser() const { return Parser; }
180   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
181 
182   void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
183     return Parser.Note(L, Msg, Ranges);
184   }
185   bool Warning(SMLoc L, const Twine &Msg,
186                ArrayRef<SMRange> Ranges = None) {
187     return Parser.Warning(L, Msg, Ranges);
188   }
189   bool Error(SMLoc L, const Twine &Msg,
190              ArrayRef<SMRange> Ranges = None) {
191     return Parser.Error(L, Msg, Ranges);
192   }
193 
194   int tryParseRegister();
195   bool tryParseRegisterWithWriteBack(OperandVector &);
196   int tryParseShiftRegister(OperandVector &);
197   bool parseRegisterList(OperandVector &);
198   bool parseMemory(OperandVector &);
199   bool parseOperand(OperandVector &, StringRef Mnemonic);
200   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
201   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
202                               unsigned &ShiftAmount);
203   bool parseLiteralValues(unsigned Size, SMLoc L);
204   bool parseDirectiveThumb(SMLoc L);
205   bool parseDirectiveARM(SMLoc L);
206   bool parseDirectiveThumbFunc(SMLoc L);
207   bool parseDirectiveCode(SMLoc L);
208   bool parseDirectiveSyntax(SMLoc L);
209   bool parseDirectiveReq(StringRef Name, SMLoc L);
210   bool parseDirectiveUnreq(SMLoc L);
211   bool parseDirectiveArch(SMLoc L);
212   bool parseDirectiveEabiAttr(SMLoc L);
213   bool parseDirectiveCPU(SMLoc L);
214   bool parseDirectiveFPU(SMLoc L);
215   bool parseDirectiveFnStart(SMLoc L);
216   bool parseDirectiveFnEnd(SMLoc L);
217   bool parseDirectiveCantUnwind(SMLoc L);
218   bool parseDirectivePersonality(SMLoc L);
219   bool parseDirectiveHandlerData(SMLoc L);
220   bool parseDirectiveSetFP(SMLoc L);
221   bool parseDirectivePad(SMLoc L);
222   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
223   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
224   bool parseDirectiveLtorg(SMLoc L);
225   bool parseDirectiveEven(SMLoc L);
226   bool parseDirectivePersonalityIndex(SMLoc L);
227   bool parseDirectiveUnwindRaw(SMLoc L);
228   bool parseDirectiveTLSDescSeq(SMLoc L);
229   bool parseDirectiveMovSP(SMLoc L);
230   bool parseDirectiveObjectArch(SMLoc L);
231   bool parseDirectiveArchExtension(SMLoc L);
232   bool parseDirectiveAlign(SMLoc L);
233   bool parseDirectiveThumbSet(SMLoc L);
234 
235   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
236                           bool &CarrySetting, unsigned &ProcessorIMod,
237                           StringRef &ITMask);
238   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
239                              bool &CanAcceptCarrySet,
240                              bool &CanAcceptPredicationCode);
241 
242   bool isThumb() const {
243     // FIXME: Can tablegen auto-generate this?
244     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
245   }
246   bool isThumbOne() const {
247     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
248   }
249   bool isThumbTwo() const {
250     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
251   }
252   bool hasThumb() const {
253     return STI.getFeatureBits() & ARM::HasV4TOps;
254   }
255   bool hasV6Ops() const {
256     return STI.getFeatureBits() & ARM::HasV6Ops;
257   }
258   bool hasV6MOps() const {
259     return STI.getFeatureBits() & ARM::HasV6MOps;
260   }
261   bool hasV7Ops() const {
262     return STI.getFeatureBits() & ARM::HasV7Ops;
263   }
264   bool hasV8Ops() const {
265     return STI.getFeatureBits() & ARM::HasV8Ops;
266   }
267   bool hasARM() const {
268     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
269   }
270   bool hasThumb2DSP() const {
271     return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
272   }
273 
274   void SwitchMode() {
275     uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
276     setAvailableFeatures(FB);
277   }
278   bool isMClass() const {
279     return STI.getFeatureBits() & ARM::FeatureMClass;
280   }
281 
282   /// @name Auto-generated Match Functions
283   /// {
284 
285 #define GET_ASSEMBLER_HEADER
286 #include "ARMGenAsmMatcher.inc"
287 
288   /// }
289 
290   OperandMatchResultTy parseITCondCode(OperandVector &);
291   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
292   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
293   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
294   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
295   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
296   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
297   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
298   OperandMatchResultTy parseBankedRegOperand(OperandVector &);
299   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
300                                    int High);
301   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
302     return parsePKHImm(O, "lsl", 0, 31);
303   }
304   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
305     return parsePKHImm(O, "asr", 1, 32);
306   }
307   OperandMatchResultTy parseSetEndImm(OperandVector &);
308   OperandMatchResultTy parseShifterImm(OperandVector &);
309   OperandMatchResultTy parseRotImm(OperandVector &);
310   OperandMatchResultTy parseBitfield(OperandVector &);
311   OperandMatchResultTy parsePostIdxReg(OperandVector &);
312   OperandMatchResultTy parseAM3Offset(OperandVector &);
313   OperandMatchResultTy parseFPImm(OperandVector &);
314   OperandMatchResultTy parseVectorList(OperandVector &);
315   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
316                                        SMLoc &EndLoc);
317 
318   // Asm Match Converter Methods
319   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
320   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
321 
322   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
323   bool processInstruction(MCInst &Inst, const OperandVector &Ops);
324   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
325   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
326 
327 public:
328   enum ARMMatchResultTy {
329     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
330     Match_RequiresNotITBlock,
331     Match_RequiresV6,
332     Match_RequiresThumb2,
333 #define GET_OPERAND_DIAGNOSTIC_TYPES
334 #include "ARMGenAsmMatcher.inc"
335 
336   };
337 
338   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
339                const MCInstrInfo &MII,
340                const MCTargetOptions &Options)
341       : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
342     MCAsmParserExtension::Initialize(_Parser);
343 
344     // Cache the MCRegisterInfo.
345     MRI = getContext().getRegisterInfo();
346 
347     // Initialize the set of available features.
348     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
349 
350     // Not in an ITBlock to start with.
351     ITState.CurPosition = ~0U;
352 
353     NextSymbolIsThumb = false;
354   }
355 
356   // Implementation of the MCTargetAsmParser interface:
357   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
358   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
359                         SMLoc NameLoc, OperandVector &Operands) override;
360   bool ParseDirective(AsmToken DirectiveID) override;
361 
362   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
363                                       unsigned Kind) override;
364   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
365 
366   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
367                                OperandVector &Operands, MCStreamer &Out,
368                                uint64_t &ErrorInfo,
369                                bool MatchingInlineAsm) override;
370   void onLabelParsed(MCSymbol *Symbol) override;
371 };
372 } // end anonymous namespace
373 
374 namespace {
375 
376 /// ARMOperand - Instances of this class represent a parsed ARM machine
377 /// operand.
378 class ARMOperand : public MCParsedAsmOperand {
379   enum KindTy {
380     k_CondCode,
381     k_CCOut,
382     k_ITCondMask,
383     k_CoprocNum,
384     k_CoprocReg,
385     k_CoprocOption,
386     k_Immediate,
387     k_MemBarrierOpt,
388     k_InstSyncBarrierOpt,
389     k_Memory,
390     k_PostIndexRegister,
391     k_MSRMask,
392     k_BankedReg,
393     k_ProcIFlags,
394     k_VectorIndex,
395     k_Register,
396     k_RegisterList,
397     k_DPRRegisterList,
398     k_SPRRegisterList,
399     k_VectorList,
400     k_VectorListAllLanes,
401     k_VectorListIndexed,
402     k_ShiftedRegister,
403     k_ShiftedImmediate,
404     k_ShifterImmediate,
405     k_RotateImmediate,
406     k_BitfieldDescriptor,
407     k_Token
408   } Kind;
409 
410   SMLoc StartLoc, EndLoc, AlignmentLoc;
411   SmallVector<unsigned, 8> Registers;
412 
413   struct CCOp {
414     ARMCC::CondCodes Val;
415   };
416 
417   struct CopOp {
418     unsigned Val;
419   };
420 
421   struct CoprocOptionOp {
422     unsigned Val;
423   };
424 
425   struct ITMaskOp {
426     unsigned Mask:4;
427   };
428 
429   struct MBOptOp {
430     ARM_MB::MemBOpt Val;
431   };
432 
433   struct ISBOptOp {
434     ARM_ISB::InstSyncBOpt Val;
435   };
436 
437   struct IFlagsOp {
438     ARM_PROC::IFlags Val;
439   };
440 
441   struct MMaskOp {
442     unsigned Val;
443   };
444 
445   struct BankedRegOp {
446     unsigned Val;
447   };
448 
449   struct TokOp {
450     const char *Data;
451     unsigned Length;
452   };
453 
454   struct RegOp {
455     unsigned RegNum;
456   };
457 
458   // A vector register list is a sequential list of 1 to 4 registers.
459   struct VectorListOp {
460     unsigned RegNum;
461     unsigned Count;
462     unsigned LaneIndex;
463     bool isDoubleSpaced;
464   };
465 
466   struct VectorIndexOp {
467     unsigned Val;
468   };
469 
470   struct ImmOp {
471     const MCExpr *Val;
472   };
473 
474   /// Combined record for all forms of ARM address expressions.
475   struct MemoryOp {
476     unsigned BaseRegNum;
477     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
478     // was specified.
479     const MCConstantExpr *OffsetImm;  // Offset immediate value
480     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
481     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
482     unsigned ShiftImm;        // shift for OffsetReg.
483     unsigned Alignment;       // 0 = no alignment specified
484     // n = alignment in bytes (2, 4, 8, 16, or 32)
485     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
486   };
487 
488   struct PostIdxRegOp {
489     unsigned RegNum;
490     bool isAdd;
491     ARM_AM::ShiftOpc ShiftTy;
492     unsigned ShiftImm;
493   };
494 
495   struct ShifterImmOp {
496     bool isASR;
497     unsigned Imm;
498   };
499 
500   struct RegShiftedRegOp {
501     ARM_AM::ShiftOpc ShiftTy;
502     unsigned SrcReg;
503     unsigned ShiftReg;
504     unsigned ShiftImm;
505   };
506 
507   struct RegShiftedImmOp {
508     ARM_AM::ShiftOpc ShiftTy;
509     unsigned SrcReg;
510     unsigned ShiftImm;
511   };
512 
513   struct RotImmOp {
514     unsigned Imm;
515   };
516 
517   struct BitfieldOp {
518     unsigned LSB;
519     unsigned Width;
520   };
521 
522   union {
523     struct CCOp CC;
524     struct CopOp Cop;
525     struct CoprocOptionOp CoprocOption;
526     struct MBOptOp MBOpt;
527     struct ISBOptOp ISBOpt;
528     struct ITMaskOp ITMask;
529     struct IFlagsOp IFlags;
530     struct MMaskOp MMask;
531     struct BankedRegOp BankedReg;
532     struct TokOp Tok;
533     struct RegOp Reg;
534     struct VectorListOp VectorList;
535     struct VectorIndexOp VectorIndex;
536     struct ImmOp Imm;
537     struct MemoryOp Memory;
538     struct PostIdxRegOp PostIdxReg;
539     struct ShifterImmOp ShifterImm;
540     struct RegShiftedRegOp RegShiftedReg;
541     struct RegShiftedImmOp RegShiftedImm;
542     struct RotImmOp RotImm;
543     struct BitfieldOp Bitfield;
544   };
545 
546 public:
547   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
548   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
549     Kind = o.Kind;
550     StartLoc = o.StartLoc;
551     EndLoc = o.EndLoc;
552     switch (Kind) {
553     case k_CondCode:
554       CC = o.CC;
555       break;
556     case k_ITCondMask:
557       ITMask = o.ITMask;
558       break;
559     case k_Token:
560       Tok = o.Tok;
561       break;
562     case k_CCOut:
563     case k_Register:
564       Reg = o.Reg;
565       break;
566     case k_RegisterList:
567     case k_DPRRegisterList:
568     case k_SPRRegisterList:
569       Registers = o.Registers;
570       break;
571     case k_VectorList:
572     case k_VectorListAllLanes:
573     case k_VectorListIndexed:
574       VectorList = o.VectorList;
575       break;
576     case k_CoprocNum:
577     case k_CoprocReg:
578       Cop = o.Cop;
579       break;
580     case k_CoprocOption:
581       CoprocOption = o.CoprocOption;
582       break;
583     case k_Immediate:
584       Imm = o.Imm;
585       break;
586     case k_MemBarrierOpt:
587       MBOpt = o.MBOpt;
588       break;
589     case k_InstSyncBarrierOpt:
590       ISBOpt = o.ISBOpt;
591     case k_Memory:
592       Memory = o.Memory;
593       break;
594     case k_PostIndexRegister:
595       PostIdxReg = o.PostIdxReg;
596       break;
597     case k_MSRMask:
598       MMask = o.MMask;
599       break;
600     case k_BankedReg:
601       BankedReg = o.BankedReg;
602       break;
603     case k_ProcIFlags:
604       IFlags = o.IFlags;
605       break;
606     case k_ShifterImmediate:
607       ShifterImm = o.ShifterImm;
608       break;
609     case k_ShiftedRegister:
610       RegShiftedReg = o.RegShiftedReg;
611       break;
612     case k_ShiftedImmediate:
613       RegShiftedImm = o.RegShiftedImm;
614       break;
615     case k_RotateImmediate:
616       RotImm = o.RotImm;
617       break;
618     case k_BitfieldDescriptor:
619       Bitfield = o.Bitfield;
620       break;
621     case k_VectorIndex:
622       VectorIndex = o.VectorIndex;
623       break;
624     }
625   }
626 
627   /// getStartLoc - Get the location of the first token of this operand.
628   SMLoc getStartLoc() const override { return StartLoc; }
629   /// getEndLoc - Get the location of the last token of this operand.
630   SMLoc getEndLoc() const override { return EndLoc; }
631   /// getLocRange - Get the range between the first and last token of this
632   /// operand.
633   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
634 
635   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
636   SMLoc getAlignmentLoc() const {
637     assert(Kind == k_Memory && "Invalid access!");
638     return AlignmentLoc;
639   }
640 
641   ARMCC::CondCodes getCondCode() const {
642     assert(Kind == k_CondCode && "Invalid access!");
643     return CC.Val;
644   }
645 
646   unsigned getCoproc() const {
647     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
648     return Cop.Val;
649   }
650 
651   StringRef getToken() const {
652     assert(Kind == k_Token && "Invalid access!");
653     return StringRef(Tok.Data, Tok.Length);
654   }
655 
656   unsigned getReg() const override {
657     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
658     return Reg.RegNum;
659   }
660 
661   const SmallVectorImpl<unsigned> &getRegList() const {
662     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
663             Kind == k_SPRRegisterList) && "Invalid access!");
664     return Registers;
665   }
666 
667   const MCExpr *getImm() const {
668     assert(isImm() && "Invalid access!");
669     return Imm.Val;
670   }
671 
672   unsigned getVectorIndex() const {
673     assert(Kind == k_VectorIndex && "Invalid access!");
674     return VectorIndex.Val;
675   }
676 
677   ARM_MB::MemBOpt getMemBarrierOpt() const {
678     assert(Kind == k_MemBarrierOpt && "Invalid access!");
679     return MBOpt.Val;
680   }
681 
682   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
683     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
684     return ISBOpt.Val;
685   }
686 
687   ARM_PROC::IFlags getProcIFlags() const {
688     assert(Kind == k_ProcIFlags && "Invalid access!");
689     return IFlags.Val;
690   }
691 
692   unsigned getMSRMask() const {
693     assert(Kind == k_MSRMask && "Invalid access!");
694     return MMask.Val;
695   }
696 
697   unsigned getBankedReg() const {
698     assert(Kind == k_BankedReg && "Invalid access!");
699     return BankedReg.Val;
700   }
701 
702   bool isCoprocNum() const { return Kind == k_CoprocNum; }
703   bool isCoprocReg() const { return Kind == k_CoprocReg; }
704   bool isCoprocOption() const { return Kind == k_CoprocOption; }
705   bool isCondCode() const { return Kind == k_CondCode; }
706   bool isCCOut() const { return Kind == k_CCOut; }
707   bool isITMask() const { return Kind == k_ITCondMask; }
708   bool isITCondCode() const { return Kind == k_CondCode; }
709   bool isImm() const override { return Kind == k_Immediate; }
710   // checks whether this operand is an unsigned offset which fits is a field
711   // of specified width and scaled by a specific number of bits
712   template<unsigned width, unsigned scale>
713   bool isUnsignedOffset() const {
714     if (!isImm()) return false;
715     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
716     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
717       int64_t Val = CE->getValue();
718       int64_t Align = 1LL << scale;
719       int64_t Max = Align * ((1LL << width) - 1);
720       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
721     }
722     return false;
723   }
724   // checks whether this operand is an signed offset which fits is a field
725   // of specified width and scaled by a specific number of bits
726   template<unsigned width, unsigned scale>
727   bool isSignedOffset() const {
728     if (!isImm()) return false;
729     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
730     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
731       int64_t Val = CE->getValue();
732       int64_t Align = 1LL << scale;
733       int64_t Max = Align * ((1LL << (width-1)) - 1);
734       int64_t Min = -Align * (1LL << (width-1));
735       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
736     }
737     return false;
738   }
739 
740   // checks whether this operand is a memory operand computed as an offset
741   // applied to PC. the offset may have 8 bits of magnitude and is represented
742   // with two bits of shift. textually it may be either [pc, #imm], #imm or
743   // relocable expression...
744   bool isThumbMemPC() const {
745     int64_t Val = 0;
746     if (isImm()) {
747       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
748       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
749       if (!CE) return false;
750       Val = CE->getValue();
751     }
752     else if (isMem()) {
753       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
754       if(Memory.BaseRegNum != ARM::PC) return false;
755       Val = Memory.OffsetImm->getValue();
756     }
757     else return false;
758     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
759   }
760   bool isFPImm() const {
761     if (!isImm()) return false;
762     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
763     if (!CE) return false;
764     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
765     return Val != -1;
766   }
767   bool isFBits16() const {
768     if (!isImm()) return false;
769     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
770     if (!CE) return false;
771     int64_t Value = CE->getValue();
772     return Value >= 0 && Value <= 16;
773   }
774   bool isFBits32() const {
775     if (!isImm()) return false;
776     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
777     if (!CE) return false;
778     int64_t Value = CE->getValue();
779     return Value >= 1 && Value <= 32;
780   }
781   bool isImm8s4() const {
782     if (!isImm()) return false;
783     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
784     if (!CE) return false;
785     int64_t Value = CE->getValue();
786     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
787   }
788   bool isImm0_1020s4() const {
789     if (!isImm()) return false;
790     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
791     if (!CE) return false;
792     int64_t Value = CE->getValue();
793     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
794   }
795   bool isImm0_508s4() const {
796     if (!isImm()) return false;
797     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
798     if (!CE) return false;
799     int64_t Value = CE->getValue();
800     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
801   }
802   bool isImm0_508s4Neg() const {
803     if (!isImm()) return false;
804     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
805     if (!CE) return false;
806     int64_t Value = -CE->getValue();
807     // explicitly exclude zero. we want that to use the normal 0_508 version.
808     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
809   }
810   bool isImm0_239() const {
811     if (!isImm()) return false;
812     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813     if (!CE) return false;
814     int64_t Value = CE->getValue();
815     return Value >= 0 && Value < 240;
816   }
817   bool isImm0_255() const {
818     if (!isImm()) return false;
819     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
820     if (!CE) return false;
821     int64_t Value = CE->getValue();
822     return Value >= 0 && Value < 256;
823   }
824   bool isImm0_4095() const {
825     if (!isImm()) return false;
826     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
827     if (!CE) return false;
828     int64_t Value = CE->getValue();
829     return Value >= 0 && Value < 4096;
830   }
831   bool isImm0_4095Neg() const {
832     if (!isImm()) return false;
833     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
834     if (!CE) return false;
835     int64_t Value = -CE->getValue();
836     return Value > 0 && Value < 4096;
837   }
838   bool isImm0_1() const {
839     if (!isImm()) return false;
840     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
841     if (!CE) return false;
842     int64_t Value = CE->getValue();
843     return Value >= 0 && Value < 2;
844   }
845   bool isImm0_3() const {
846     if (!isImm()) return false;
847     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848     if (!CE) return false;
849     int64_t Value = CE->getValue();
850     return Value >= 0 && Value < 4;
851   }
852   bool isImm0_7() const {
853     if (!isImm()) return false;
854     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855     if (!CE) return false;
856     int64_t Value = CE->getValue();
857     return Value >= 0 && Value < 8;
858   }
859   bool isImm0_15() const {
860     if (!isImm()) return false;
861     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862     if (!CE) return false;
863     int64_t Value = CE->getValue();
864     return Value >= 0 && Value < 16;
865   }
866   bool isImm0_31() const {
867     if (!isImm()) return false;
868     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
869     if (!CE) return false;
870     int64_t Value = CE->getValue();
871     return Value >= 0 && Value < 32;
872   }
873   bool isImm0_63() const {
874     if (!isImm()) return false;
875     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876     if (!CE) return false;
877     int64_t Value = CE->getValue();
878     return Value >= 0 && Value < 64;
879   }
880   bool isImm8() const {
881     if (!isImm()) return false;
882     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883     if (!CE) return false;
884     int64_t Value = CE->getValue();
885     return Value == 8;
886   }
887   bool isImm16() const {
888     if (!isImm()) return false;
889     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
890     if (!CE) return false;
891     int64_t Value = CE->getValue();
892     return Value == 16;
893   }
894   bool isImm32() const {
895     if (!isImm()) return false;
896     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897     if (!CE) return false;
898     int64_t Value = CE->getValue();
899     return Value == 32;
900   }
901   bool isShrImm8() const {
902     if (!isImm()) return false;
903     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
904     if (!CE) return false;
905     int64_t Value = CE->getValue();
906     return Value > 0 && Value <= 8;
907   }
908   bool isShrImm16() const {
909     if (!isImm()) return false;
910     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911     if (!CE) return false;
912     int64_t Value = CE->getValue();
913     return Value > 0 && Value <= 16;
914   }
915   bool isShrImm32() const {
916     if (!isImm()) return false;
917     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918     if (!CE) return false;
919     int64_t Value = CE->getValue();
920     return Value > 0 && Value <= 32;
921   }
922   bool isShrImm64() const {
923     if (!isImm()) return false;
924     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925     if (!CE) return false;
926     int64_t Value = CE->getValue();
927     return Value > 0 && Value <= 64;
928   }
929   bool isImm1_7() const {
930     if (!isImm()) return false;
931     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
932     if (!CE) return false;
933     int64_t Value = CE->getValue();
934     return Value > 0 && Value < 8;
935   }
936   bool isImm1_15() const {
937     if (!isImm()) return false;
938     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
939     if (!CE) return false;
940     int64_t Value = CE->getValue();
941     return Value > 0 && Value < 16;
942   }
943   bool isImm1_31() const {
944     if (!isImm()) return false;
945     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
946     if (!CE) return false;
947     int64_t Value = CE->getValue();
948     return Value > 0 && Value < 32;
949   }
950   bool isImm1_16() const {
951     if (!isImm()) return false;
952     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
953     if (!CE) return false;
954     int64_t Value = CE->getValue();
955     return Value > 0 && Value < 17;
956   }
957   bool isImm1_32() const {
958     if (!isImm()) return false;
959     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960     if (!CE) return false;
961     int64_t Value = CE->getValue();
962     return Value > 0 && Value < 33;
963   }
964   bool isImm0_32() const {
965     if (!isImm()) return false;
966     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
967     if (!CE) return false;
968     int64_t Value = CE->getValue();
969     return Value >= 0 && Value < 33;
970   }
971   bool isImm0_65535() const {
972     if (!isImm()) return false;
973     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
974     if (!CE) return false;
975     int64_t Value = CE->getValue();
976     return Value >= 0 && Value < 65536;
977   }
978   bool isImm256_65535Expr() const {
979     if (!isImm()) return false;
980     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
981     // If it's not a constant expression, it'll generate a fixup and be
982     // handled later.
983     if (!CE) return true;
984     int64_t Value = CE->getValue();
985     return Value >= 256 && Value < 65536;
986   }
987   bool isImm0_65535Expr() const {
988     if (!isImm()) return false;
989     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
990     // If it's not a constant expression, it'll generate a fixup and be
991     // handled later.
992     if (!CE) return true;
993     int64_t Value = CE->getValue();
994     return Value >= 0 && Value < 65536;
995   }
996   bool isImm24bit() const {
997     if (!isImm()) return false;
998     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999     if (!CE) return false;
1000     int64_t Value = CE->getValue();
1001     return Value >= 0 && Value <= 0xffffff;
1002   }
1003   bool isImmThumbSR() const {
1004     if (!isImm()) return false;
1005     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1006     if (!CE) return false;
1007     int64_t Value = CE->getValue();
1008     return Value > 0 && Value < 33;
1009   }
1010   bool isPKHLSLImm() const {
1011     if (!isImm()) return false;
1012     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1013     if (!CE) return false;
1014     int64_t Value = CE->getValue();
1015     return Value >= 0 && Value < 32;
1016   }
1017   bool isPKHASRImm() const {
1018     if (!isImm()) return false;
1019     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1020     if (!CE) return false;
1021     int64_t Value = CE->getValue();
1022     return Value > 0 && Value <= 32;
1023   }
1024   bool isAdrLabel() const {
1025     // If we have an immediate that's not a constant, treat it as a label
1026     // reference needing a fixup. If it is a constant, but it can't fit
1027     // into shift immediate encoding, we reject it.
1028     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1029     else return (isARMSOImm() || isARMSOImmNeg());
1030   }
1031   bool isARMSOImm() const {
1032     if (!isImm()) return false;
1033     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034     if (!CE) return false;
1035     int64_t Value = CE->getValue();
1036     return ARM_AM::getSOImmVal(Value) != -1;
1037   }
1038   bool isARMSOImmNot() const {
1039     if (!isImm()) return false;
1040     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041     if (!CE) return false;
1042     int64_t Value = CE->getValue();
1043     return ARM_AM::getSOImmVal(~Value) != -1;
1044   }
1045   bool isARMSOImmNeg() const {
1046     if (!isImm()) return false;
1047     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048     if (!CE) return false;
1049     int64_t Value = CE->getValue();
1050     // Only use this when not representable as a plain so_imm.
1051     return ARM_AM::getSOImmVal(Value) == -1 &&
1052       ARM_AM::getSOImmVal(-Value) != -1;
1053   }
1054   bool isT2SOImm() const {
1055     if (!isImm()) return false;
1056     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1057     if (!CE) return false;
1058     int64_t Value = CE->getValue();
1059     return ARM_AM::getT2SOImmVal(Value) != -1;
1060   }
1061   bool isT2SOImmNot() const {
1062     if (!isImm()) return false;
1063     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1064     if (!CE) return false;
1065     int64_t Value = CE->getValue();
1066     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1067       ARM_AM::getT2SOImmVal(~Value) != -1;
1068   }
1069   bool isT2SOImmNeg() const {
1070     if (!isImm()) return false;
1071     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1072     if (!CE) return false;
1073     int64_t Value = CE->getValue();
1074     // Only use this when not representable as a plain so_imm.
1075     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1076       ARM_AM::getT2SOImmVal(-Value) != -1;
1077   }
1078   bool isSetEndImm() const {
1079     if (!isImm()) return false;
1080     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1081     if (!CE) return false;
1082     int64_t Value = CE->getValue();
1083     return Value == 1 || Value == 0;
1084   }
1085   bool isReg() const override { return Kind == k_Register; }
1086   bool isRegList() const { return Kind == k_RegisterList; }
1087   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1088   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1089   bool isToken() const override { return Kind == k_Token; }
1090   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1091   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1092   bool isMem() const override { return Kind == k_Memory; }
1093   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1094   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1095   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1096   bool isRotImm() const { return Kind == k_RotateImmediate; }
1097   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1098   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1099   bool isPostIdxReg() const {
1100     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1101   }
1102   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1103     if (!isMem())
1104       return false;
1105     // No offset of any kind.
1106     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1107      (alignOK || Memory.Alignment == Alignment);
1108   }
1109   bool isMemPCRelImm12() const {
1110     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1111       return false;
1112     // Base register must be PC.
1113     if (Memory.BaseRegNum != ARM::PC)
1114       return false;
1115     // Immediate offset in range [-4095, 4095].
1116     if (!Memory.OffsetImm) return true;
1117     int64_t Val = Memory.OffsetImm->getValue();
1118     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1119   }
1120   bool isAlignedMemory() const {
1121     return isMemNoOffset(true);
1122   }
1123   bool isAlignedMemoryNone() const {
1124     return isMemNoOffset(false, 0);
1125   }
1126   bool isDupAlignedMemoryNone() const {
1127     return isMemNoOffset(false, 0);
1128   }
1129   bool isAlignedMemory16() const {
1130     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1131       return true;
1132     return isMemNoOffset(false, 0);
1133   }
1134   bool isDupAlignedMemory16() const {
1135     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1136       return true;
1137     return isMemNoOffset(false, 0);
1138   }
1139   bool isAlignedMemory32() const {
1140     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1141       return true;
1142     return isMemNoOffset(false, 0);
1143   }
1144   bool isDupAlignedMemory32() const {
1145     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1146       return true;
1147     return isMemNoOffset(false, 0);
1148   }
1149   bool isAlignedMemory64() const {
1150     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1151       return true;
1152     return isMemNoOffset(false, 0);
1153   }
1154   bool isDupAlignedMemory64() const {
1155     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1156       return true;
1157     return isMemNoOffset(false, 0);
1158   }
1159   bool isAlignedMemory64or128() const {
1160     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1161       return true;
1162     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1163       return true;
1164     return isMemNoOffset(false, 0);
1165   }
1166   bool isDupAlignedMemory64or128() const {
1167     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1168       return true;
1169     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1170       return true;
1171     return isMemNoOffset(false, 0);
1172   }
1173   bool isAlignedMemory64or128or256() const {
1174     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1175       return true;
1176     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1177       return true;
1178     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1179       return true;
1180     return isMemNoOffset(false, 0);
1181   }
1182   bool isAddrMode2() const {
1183     if (!isMem() || Memory.Alignment != 0) return false;
1184     // Check for register offset.
1185     if (Memory.OffsetRegNum) return true;
1186     // Immediate offset in range [-4095, 4095].
1187     if (!Memory.OffsetImm) return true;
1188     int64_t Val = Memory.OffsetImm->getValue();
1189     return Val > -4096 && Val < 4096;
1190   }
1191   bool isAM2OffsetImm() const {
1192     if (!isImm()) return false;
1193     // Immediate offset in range [-4095, 4095].
1194     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1195     if (!CE) return false;
1196     int64_t Val = CE->getValue();
1197     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1198   }
1199   bool isAddrMode3() const {
1200     // If we have an immediate that's not a constant, treat it as a label
1201     // reference needing a fixup. If it is a constant, it's something else
1202     // and we reject it.
1203     if (isImm() && !isa<MCConstantExpr>(getImm()))
1204       return true;
1205     if (!isMem() || Memory.Alignment != 0) return false;
1206     // No shifts are legal for AM3.
1207     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1208     // Check for register offset.
1209     if (Memory.OffsetRegNum) return true;
1210     // Immediate offset in range [-255, 255].
1211     if (!Memory.OffsetImm) return true;
1212     int64_t Val = Memory.OffsetImm->getValue();
1213     // The #-0 offset is encoded as INT32_MIN, and we have to check
1214     // for this too.
1215     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1216   }
1217   bool isAM3Offset() const {
1218     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1219       return false;
1220     if (Kind == k_PostIndexRegister)
1221       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1222     // Immediate offset in range [-255, 255].
1223     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224     if (!CE) return false;
1225     int64_t Val = CE->getValue();
1226     // Special case, #-0 is INT32_MIN.
1227     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1228   }
1229   bool isAddrMode5() const {
1230     // If we have an immediate that's not a constant, treat it as a label
1231     // reference needing a fixup. If it is a constant, it's something else
1232     // and we reject it.
1233     if (isImm() && !isa<MCConstantExpr>(getImm()))
1234       return true;
1235     if (!isMem() || Memory.Alignment != 0) return false;
1236     // Check for register offset.
1237     if (Memory.OffsetRegNum) return false;
1238     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1239     if (!Memory.OffsetImm) return true;
1240     int64_t Val = Memory.OffsetImm->getValue();
1241     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1242       Val == INT32_MIN;
1243   }
1244   bool isMemTBB() const {
1245     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1246         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1247       return false;
1248     return true;
1249   }
1250   bool isMemTBH() const {
1251     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1252         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1253         Memory.Alignment != 0 )
1254       return false;
1255     return true;
1256   }
1257   bool isMemRegOffset() const {
1258     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1259       return false;
1260     return true;
1261   }
1262   bool isT2MemRegOffset() const {
1263     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1264         Memory.Alignment != 0)
1265       return false;
1266     // Only lsl #{0, 1, 2, 3} allowed.
1267     if (Memory.ShiftType == ARM_AM::no_shift)
1268       return true;
1269     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1270       return false;
1271     return true;
1272   }
1273   bool isMemThumbRR() const {
1274     // Thumb reg+reg addressing is simple. Just two registers, a base and
1275     // an offset. No shifts, negations or any other complicating factors.
1276     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1277         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1278       return false;
1279     return isARMLowRegister(Memory.BaseRegNum) &&
1280       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1281   }
1282   bool isMemThumbRIs4() const {
1283     if (!isMem() || Memory.OffsetRegNum != 0 ||
1284         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1285       return false;
1286     // Immediate offset, multiple of 4 in range [0, 124].
1287     if (!Memory.OffsetImm) return true;
1288     int64_t Val = Memory.OffsetImm->getValue();
1289     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1290   }
1291   bool isMemThumbRIs2() const {
1292     if (!isMem() || Memory.OffsetRegNum != 0 ||
1293         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1294       return false;
1295     // Immediate offset, multiple of 4 in range [0, 62].
1296     if (!Memory.OffsetImm) return true;
1297     int64_t Val = Memory.OffsetImm->getValue();
1298     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1299   }
1300   bool isMemThumbRIs1() const {
1301     if (!isMem() || Memory.OffsetRegNum != 0 ||
1302         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1303       return false;
1304     // Immediate offset in range [0, 31].
1305     if (!Memory.OffsetImm) return true;
1306     int64_t Val = Memory.OffsetImm->getValue();
1307     return Val >= 0 && Val <= 31;
1308   }
1309   bool isMemThumbSPI() const {
1310     if (!isMem() || Memory.OffsetRegNum != 0 ||
1311         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1312       return false;
1313     // Immediate offset, multiple of 4 in range [0, 1020].
1314     if (!Memory.OffsetImm) return true;
1315     int64_t Val = Memory.OffsetImm->getValue();
1316     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1317   }
1318   bool isMemImm8s4Offset() const {
1319     // If we have an immediate that's not a constant, treat it as a label
1320     // reference needing a fixup. If it is a constant, it's something else
1321     // and we reject it.
1322     if (isImm() && !isa<MCConstantExpr>(getImm()))
1323       return true;
1324     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1325       return false;
1326     // Immediate offset a multiple of 4 in range [-1020, 1020].
1327     if (!Memory.OffsetImm) return true;
1328     int64_t Val = Memory.OffsetImm->getValue();
1329     // Special case, #-0 is INT32_MIN.
1330     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1331   }
1332   bool isMemImm0_1020s4Offset() const {
1333     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1334       return false;
1335     // Immediate offset a multiple of 4 in range [0, 1020].
1336     if (!Memory.OffsetImm) return true;
1337     int64_t Val = Memory.OffsetImm->getValue();
1338     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1339   }
1340   bool isMemImm8Offset() const {
1341     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1342       return false;
1343     // Base reg of PC isn't allowed for these encodings.
1344     if (Memory.BaseRegNum == ARM::PC) return false;
1345     // Immediate offset in range [-255, 255].
1346     if (!Memory.OffsetImm) return true;
1347     int64_t Val = Memory.OffsetImm->getValue();
1348     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1349   }
1350   bool isMemPosImm8Offset() const {
1351     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1352       return false;
1353     // Immediate offset in range [0, 255].
1354     if (!Memory.OffsetImm) return true;
1355     int64_t Val = Memory.OffsetImm->getValue();
1356     return Val >= 0 && Val < 256;
1357   }
1358   bool isMemNegImm8Offset() const {
1359     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1360       return false;
1361     // Base reg of PC isn't allowed for these encodings.
1362     if (Memory.BaseRegNum == ARM::PC) return false;
1363     // Immediate offset in range [-255, -1].
1364     if (!Memory.OffsetImm) return false;
1365     int64_t Val = Memory.OffsetImm->getValue();
1366     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1367   }
1368   bool isMemUImm12Offset() const {
1369     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1370       return false;
1371     // Immediate offset in range [0, 4095].
1372     if (!Memory.OffsetImm) return true;
1373     int64_t Val = Memory.OffsetImm->getValue();
1374     return (Val >= 0 && Val < 4096);
1375   }
1376   bool isMemImm12Offset() const {
1377     // If we have an immediate that's not a constant, treat it as a label
1378     // reference needing a fixup. If it is a constant, it's something else
1379     // and we reject it.
1380     if (isImm() && !isa<MCConstantExpr>(getImm()))
1381       return true;
1382 
1383     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1384       return false;
1385     // Immediate offset in range [-4095, 4095].
1386     if (!Memory.OffsetImm) return true;
1387     int64_t Val = Memory.OffsetImm->getValue();
1388     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1389   }
1390   bool isPostIdxImm8() const {
1391     if (!isImm()) return false;
1392     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1393     if (!CE) return false;
1394     int64_t Val = CE->getValue();
1395     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1396   }
1397   bool isPostIdxImm8s4() const {
1398     if (!isImm()) return false;
1399     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1400     if (!CE) return false;
1401     int64_t Val = CE->getValue();
1402     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1403       (Val == INT32_MIN);
1404   }
1405 
1406   bool isMSRMask() const { return Kind == k_MSRMask; }
1407   bool isBankedReg() const { return Kind == k_BankedReg; }
1408   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1409 
1410   // NEON operands.
1411   bool isSingleSpacedVectorList() const {
1412     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1413   }
1414   bool isDoubleSpacedVectorList() const {
1415     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1416   }
1417   bool isVecListOneD() const {
1418     if (!isSingleSpacedVectorList()) return false;
1419     return VectorList.Count == 1;
1420   }
1421 
1422   bool isVecListDPair() const {
1423     if (!isSingleSpacedVectorList()) return false;
1424     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1425               .contains(VectorList.RegNum));
1426   }
1427 
1428   bool isVecListThreeD() const {
1429     if (!isSingleSpacedVectorList()) return false;
1430     return VectorList.Count == 3;
1431   }
1432 
1433   bool isVecListFourD() const {
1434     if (!isSingleSpacedVectorList()) return false;
1435     return VectorList.Count == 4;
1436   }
1437 
1438   bool isVecListDPairSpaced() const {
1439     if (Kind != k_VectorList) return false;
1440     if (isSingleSpacedVectorList()) return false;
1441     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1442               .contains(VectorList.RegNum));
1443   }
1444 
1445   bool isVecListThreeQ() const {
1446     if (!isDoubleSpacedVectorList()) return false;
1447     return VectorList.Count == 3;
1448   }
1449 
1450   bool isVecListFourQ() const {
1451     if (!isDoubleSpacedVectorList()) return false;
1452     return VectorList.Count == 4;
1453   }
1454 
1455   bool isSingleSpacedVectorAllLanes() const {
1456     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1457   }
1458   bool isDoubleSpacedVectorAllLanes() const {
1459     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1460   }
1461   bool isVecListOneDAllLanes() const {
1462     if (!isSingleSpacedVectorAllLanes()) return false;
1463     return VectorList.Count == 1;
1464   }
1465 
1466   bool isVecListDPairAllLanes() const {
1467     if (!isSingleSpacedVectorAllLanes()) return false;
1468     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1469               .contains(VectorList.RegNum));
1470   }
1471 
1472   bool isVecListDPairSpacedAllLanes() const {
1473     if (!isDoubleSpacedVectorAllLanes()) return false;
1474     return VectorList.Count == 2;
1475   }
1476 
1477   bool isVecListThreeDAllLanes() const {
1478     if (!isSingleSpacedVectorAllLanes()) return false;
1479     return VectorList.Count == 3;
1480   }
1481 
1482   bool isVecListThreeQAllLanes() const {
1483     if (!isDoubleSpacedVectorAllLanes()) return false;
1484     return VectorList.Count == 3;
1485   }
1486 
1487   bool isVecListFourDAllLanes() const {
1488     if (!isSingleSpacedVectorAllLanes()) return false;
1489     return VectorList.Count == 4;
1490   }
1491 
1492   bool isVecListFourQAllLanes() const {
1493     if (!isDoubleSpacedVectorAllLanes()) return false;
1494     return VectorList.Count == 4;
1495   }
1496 
1497   bool isSingleSpacedVectorIndexed() const {
1498     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1499   }
1500   bool isDoubleSpacedVectorIndexed() const {
1501     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1502   }
1503   bool isVecListOneDByteIndexed() const {
1504     if (!isSingleSpacedVectorIndexed()) return false;
1505     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1506   }
1507 
1508   bool isVecListOneDHWordIndexed() const {
1509     if (!isSingleSpacedVectorIndexed()) return false;
1510     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1511   }
1512 
1513   bool isVecListOneDWordIndexed() const {
1514     if (!isSingleSpacedVectorIndexed()) return false;
1515     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1516   }
1517 
1518   bool isVecListTwoDByteIndexed() const {
1519     if (!isSingleSpacedVectorIndexed()) return false;
1520     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1521   }
1522 
1523   bool isVecListTwoDHWordIndexed() const {
1524     if (!isSingleSpacedVectorIndexed()) return false;
1525     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1526   }
1527 
1528   bool isVecListTwoQWordIndexed() const {
1529     if (!isDoubleSpacedVectorIndexed()) return false;
1530     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1531   }
1532 
1533   bool isVecListTwoQHWordIndexed() const {
1534     if (!isDoubleSpacedVectorIndexed()) return false;
1535     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1536   }
1537 
1538   bool isVecListTwoDWordIndexed() const {
1539     if (!isSingleSpacedVectorIndexed()) return false;
1540     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1541   }
1542 
1543   bool isVecListThreeDByteIndexed() const {
1544     if (!isSingleSpacedVectorIndexed()) return false;
1545     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1546   }
1547 
1548   bool isVecListThreeDHWordIndexed() const {
1549     if (!isSingleSpacedVectorIndexed()) return false;
1550     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1551   }
1552 
1553   bool isVecListThreeQWordIndexed() const {
1554     if (!isDoubleSpacedVectorIndexed()) return false;
1555     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1556   }
1557 
1558   bool isVecListThreeQHWordIndexed() const {
1559     if (!isDoubleSpacedVectorIndexed()) return false;
1560     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1561   }
1562 
1563   bool isVecListThreeDWordIndexed() const {
1564     if (!isSingleSpacedVectorIndexed()) return false;
1565     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1566   }
1567 
1568   bool isVecListFourDByteIndexed() const {
1569     if (!isSingleSpacedVectorIndexed()) return false;
1570     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1571   }
1572 
1573   bool isVecListFourDHWordIndexed() const {
1574     if (!isSingleSpacedVectorIndexed()) return false;
1575     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1576   }
1577 
1578   bool isVecListFourQWordIndexed() const {
1579     if (!isDoubleSpacedVectorIndexed()) return false;
1580     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1581   }
1582 
1583   bool isVecListFourQHWordIndexed() const {
1584     if (!isDoubleSpacedVectorIndexed()) return false;
1585     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1586   }
1587 
1588   bool isVecListFourDWordIndexed() const {
1589     if (!isSingleSpacedVectorIndexed()) return false;
1590     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1591   }
1592 
1593   bool isVectorIndex8() const {
1594     if (Kind != k_VectorIndex) return false;
1595     return VectorIndex.Val < 8;
1596   }
1597   bool isVectorIndex16() const {
1598     if (Kind != k_VectorIndex) return false;
1599     return VectorIndex.Val < 4;
1600   }
1601   bool isVectorIndex32() const {
1602     if (Kind != k_VectorIndex) return false;
1603     return VectorIndex.Val < 2;
1604   }
1605 
1606   bool isNEONi8splat() const {
1607     if (!isImm()) return false;
1608     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1609     // Must be a constant.
1610     if (!CE) return false;
1611     int64_t Value = CE->getValue();
1612     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1613     // value.
1614     return Value >= 0 && Value < 256;
1615   }
1616 
1617   bool isNEONi16splat() const {
1618     if (isNEONByteReplicate(2))
1619       return false; // Leave that for bytes replication and forbid by default.
1620     if (!isImm())
1621       return false;
1622     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1623     // Must be a constant.
1624     if (!CE) return false;
1625     unsigned Value = CE->getValue();
1626     return ARM_AM::isNEONi16splat(Value);
1627   }
1628 
1629   bool isNEONi16splatNot() const {
1630     if (!isImm())
1631       return false;
1632     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1633     // Must be a constant.
1634     if (!CE) return false;
1635     unsigned Value = CE->getValue();
1636     return ARM_AM::isNEONi16splat(~Value & 0xffff);
1637   }
1638 
1639   bool isNEONi32splat() const {
1640     if (isNEONByteReplicate(4))
1641       return false; // Leave that for bytes replication and forbid by default.
1642     if (!isImm())
1643       return false;
1644     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1645     // Must be a constant.
1646     if (!CE) return false;
1647     unsigned Value = CE->getValue();
1648     return ARM_AM::isNEONi32splat(Value);
1649   }
1650 
1651   bool isNEONi32splatNot() const {
1652     if (!isImm())
1653       return false;
1654     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1655     // Must be a constant.
1656     if (!CE) return false;
1657     unsigned Value = CE->getValue();
1658     return ARM_AM::isNEONi32splat(~Value);
1659   }
1660 
1661   bool isNEONByteReplicate(unsigned NumBytes) const {
1662     if (!isImm())
1663       return false;
1664     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1665     // Must be a constant.
1666     if (!CE)
1667       return false;
1668     int64_t Value = CE->getValue();
1669     if (!Value)
1670       return false; // Don't bother with zero.
1671 
1672     unsigned char B = Value & 0xff;
1673     for (unsigned i = 1; i < NumBytes; ++i) {
1674       Value >>= 8;
1675       if ((Value & 0xff) != B)
1676         return false;
1677     }
1678     return true;
1679   }
1680   bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1681   bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1682   bool isNEONi32vmov() const {
1683     if (isNEONByteReplicate(4))
1684       return false; // Let it to be classified as byte-replicate case.
1685     if (!isImm())
1686       return false;
1687     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1688     // Must be a constant.
1689     if (!CE)
1690       return false;
1691     int64_t Value = CE->getValue();
1692     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1693     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1694     // FIXME: This is probably wrong and a copy and paste from previous example
1695     return (Value >= 0 && Value < 256) ||
1696       (Value >= 0x0100 && Value <= 0xff00) ||
1697       (Value >= 0x010000 && Value <= 0xff0000) ||
1698       (Value >= 0x01000000 && Value <= 0xff000000) ||
1699       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1700       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1701   }
1702   bool isNEONi32vmovNeg() const {
1703     if (!isImm()) return false;
1704     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1705     // Must be a constant.
1706     if (!CE) return false;
1707     int64_t Value = ~CE->getValue();
1708     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1709     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1710     // FIXME: This is probably wrong and a copy and paste from previous example
1711     return (Value >= 0 && Value < 256) ||
1712       (Value >= 0x0100 && Value <= 0xff00) ||
1713       (Value >= 0x010000 && Value <= 0xff0000) ||
1714       (Value >= 0x01000000 && Value <= 0xff000000) ||
1715       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1716       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1717   }
1718 
1719   bool isNEONi64splat() const {
1720     if (!isImm()) return false;
1721     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1722     // Must be a constant.
1723     if (!CE) return false;
1724     uint64_t Value = CE->getValue();
1725     // i64 value with each byte being either 0 or 0xff.
1726     for (unsigned i = 0; i < 8; ++i)
1727       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1728     return true;
1729   }
1730 
1731   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1732     // Add as immediates when possible.  Null MCExpr = 0.
1733     if (!Expr)
1734       Inst.addOperand(MCOperand::CreateImm(0));
1735     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1736       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1737     else
1738       Inst.addOperand(MCOperand::CreateExpr(Expr));
1739   }
1740 
1741   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1742     assert(N == 2 && "Invalid number of operands!");
1743     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1744     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1745     Inst.addOperand(MCOperand::CreateReg(RegNum));
1746   }
1747 
1748   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1749     assert(N == 1 && "Invalid number of operands!");
1750     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1751   }
1752 
1753   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1754     assert(N == 1 && "Invalid number of operands!");
1755     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1756   }
1757 
1758   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1759     assert(N == 1 && "Invalid number of operands!");
1760     Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1761   }
1762 
1763   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1764     assert(N == 1 && "Invalid number of operands!");
1765     Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1766   }
1767 
1768   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1769     assert(N == 1 && "Invalid number of operands!");
1770     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1771   }
1772 
1773   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1774     assert(N == 1 && "Invalid number of operands!");
1775     Inst.addOperand(MCOperand::CreateReg(getReg()));
1776   }
1777 
1778   void addRegOperands(MCInst &Inst, unsigned N) const {
1779     assert(N == 1 && "Invalid number of operands!");
1780     Inst.addOperand(MCOperand::CreateReg(getReg()));
1781   }
1782 
1783   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1784     assert(N == 3 && "Invalid number of operands!");
1785     assert(isRegShiftedReg() &&
1786            "addRegShiftedRegOperands() on non-RegShiftedReg!");
1787     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1788     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1789     Inst.addOperand(MCOperand::CreateImm(
1790       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1791   }
1792 
1793   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1794     assert(N == 2 && "Invalid number of operands!");
1795     assert(isRegShiftedImm() &&
1796            "addRegShiftedImmOperands() on non-RegShiftedImm!");
1797     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1798     // Shift of #32 is encoded as 0 where permitted
1799     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1800     Inst.addOperand(MCOperand::CreateImm(
1801       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1802   }
1803 
1804   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1805     assert(N == 1 && "Invalid number of operands!");
1806     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1807                                          ShifterImm.Imm));
1808   }
1809 
1810   void addRegListOperands(MCInst &Inst, unsigned N) const {
1811     assert(N == 1 && "Invalid number of operands!");
1812     const SmallVectorImpl<unsigned> &RegList = getRegList();
1813     for (SmallVectorImpl<unsigned>::const_iterator
1814            I = RegList.begin(), E = RegList.end(); I != E; ++I)
1815       Inst.addOperand(MCOperand::CreateReg(*I));
1816   }
1817 
1818   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1819     addRegListOperands(Inst, N);
1820   }
1821 
1822   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1823     addRegListOperands(Inst, N);
1824   }
1825 
1826   void addRotImmOperands(MCInst &Inst, unsigned N) const {
1827     assert(N == 1 && "Invalid number of operands!");
1828     // Encoded as val>>3. The printer handles display as 8, 16, 24.
1829     Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1830   }
1831 
1832   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1833     assert(N == 1 && "Invalid number of operands!");
1834     // Munge the lsb/width into a bitfield mask.
1835     unsigned lsb = Bitfield.LSB;
1836     unsigned width = Bitfield.Width;
1837     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1838     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1839                       (32 - (lsb + width)));
1840     Inst.addOperand(MCOperand::CreateImm(Mask));
1841   }
1842 
1843   void addImmOperands(MCInst &Inst, unsigned N) const {
1844     assert(N == 1 && "Invalid number of operands!");
1845     addExpr(Inst, getImm());
1846   }
1847 
1848   void addFBits16Operands(MCInst &Inst, unsigned N) const {
1849     assert(N == 1 && "Invalid number of operands!");
1850     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1851     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1852   }
1853 
1854   void addFBits32Operands(MCInst &Inst, unsigned N) const {
1855     assert(N == 1 && "Invalid number of operands!");
1856     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1857     Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1858   }
1859 
1860   void addFPImmOperands(MCInst &Inst, unsigned N) const {
1861     assert(N == 1 && "Invalid number of operands!");
1862     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1863     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1864     Inst.addOperand(MCOperand::CreateImm(Val));
1865   }
1866 
1867   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1868     assert(N == 1 && "Invalid number of operands!");
1869     // FIXME: We really want to scale the value here, but the LDRD/STRD
1870     // instruction don't encode operands that way yet.
1871     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1872     Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1873   }
1874 
1875   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1876     assert(N == 1 && "Invalid number of operands!");
1877     // The immediate is scaled by four in the encoding and is stored
1878     // in the MCInst as such. Lop off the low two bits here.
1879     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1880     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1881   }
1882 
1883   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1884     assert(N == 1 && "Invalid number of operands!");
1885     // The immediate is scaled by four in the encoding and is stored
1886     // in the MCInst as such. Lop off the low two bits here.
1887     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1888     Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1889   }
1890 
1891   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1892     assert(N == 1 && "Invalid number of operands!");
1893     // The immediate is scaled by four in the encoding and is stored
1894     // in the MCInst as such. Lop off the low two bits here.
1895     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1896     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1897   }
1898 
1899   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1900     assert(N == 1 && "Invalid number of operands!");
1901     // The constant encodes as the immediate-1, and we store in the instruction
1902     // the bits as encoded, so subtract off one here.
1903     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1904     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1905   }
1906 
1907   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1908     assert(N == 1 && "Invalid number of operands!");
1909     // The constant encodes as the immediate-1, and we store in the instruction
1910     // the bits as encoded, so subtract off one here.
1911     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1912     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1913   }
1914 
1915   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1916     assert(N == 1 && "Invalid number of operands!");
1917     // The constant encodes as the immediate, except for 32, which encodes as
1918     // zero.
1919     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1920     unsigned Imm = CE->getValue();
1921     Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1922   }
1923 
1924   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1925     assert(N == 1 && "Invalid number of operands!");
1926     // An ASR value of 32 encodes as 0, so that's how we want to add it to
1927     // the instruction as well.
1928     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1929     int Val = CE->getValue();
1930     Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1931   }
1932 
1933   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1934     assert(N == 1 && "Invalid number of operands!");
1935     // The operand is actually a t2_so_imm, but we have its bitwise
1936     // negation in the assembly source, so twiddle it here.
1937     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1938     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1939   }
1940 
1941   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1942     assert(N == 1 && "Invalid number of operands!");
1943     // The operand is actually a t2_so_imm, but we have its
1944     // negation in the assembly source, so twiddle it here.
1945     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1946     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1947   }
1948 
1949   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1950     assert(N == 1 && "Invalid number of operands!");
1951     // The operand is actually an imm0_4095, but we have its
1952     // negation in the assembly source, so twiddle it here.
1953     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1954     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1955   }
1956 
1957   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1958     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1959       Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1960       return;
1961     }
1962 
1963     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1964     assert(SR && "Unknown value type!");
1965     Inst.addOperand(MCOperand::CreateExpr(SR));
1966   }
1967 
1968   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1969     assert(N == 1 && "Invalid number of operands!");
1970     if (isImm()) {
1971       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1972       if (CE) {
1973         Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1974         return;
1975       }
1976 
1977       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1978       assert(SR && "Unknown value type!");
1979       Inst.addOperand(MCOperand::CreateExpr(SR));
1980       return;
1981     }
1982 
1983     assert(isMem()  && "Unknown value type!");
1984     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1985     Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1986   }
1987 
1988   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1989     assert(N == 1 && "Invalid number of operands!");
1990     // The operand is actually a so_imm, but we have its bitwise
1991     // negation in the assembly source, so twiddle it here.
1992     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1993     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1994   }
1995 
1996   void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1997     assert(N == 1 && "Invalid number of operands!");
1998     // The operand is actually a so_imm, but we have its
1999     // negation in the assembly source, so twiddle it here.
2000     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2001     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
2002   }
2003 
2004   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2005     assert(N == 1 && "Invalid number of operands!");
2006     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
2007   }
2008 
2009   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2010     assert(N == 1 && "Invalid number of operands!");
2011     Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
2012   }
2013 
2014   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2015     assert(N == 1 && "Invalid number of operands!");
2016     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2017   }
2018 
2019   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2020     assert(N == 1 && "Invalid number of operands!");
2021     int32_t Imm = Memory.OffsetImm->getValue();
2022     Inst.addOperand(MCOperand::CreateImm(Imm));
2023   }
2024 
2025   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2026     assert(N == 1 && "Invalid number of operands!");
2027     assert(isImm() && "Not an immediate!");
2028 
2029     // If we have an immediate that's not a constant, treat it as a label
2030     // reference needing a fixup.
2031     if (!isa<MCConstantExpr>(getImm())) {
2032       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2033       return;
2034     }
2035 
2036     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2037     int Val = CE->getValue();
2038     Inst.addOperand(MCOperand::CreateImm(Val));
2039   }
2040 
2041   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2042     assert(N == 2 && "Invalid number of operands!");
2043     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2044     Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2045   }
2046 
2047   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2048     addAlignedMemoryOperands(Inst, N);
2049   }
2050 
2051   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2052     addAlignedMemoryOperands(Inst, N);
2053   }
2054 
2055   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2056     addAlignedMemoryOperands(Inst, N);
2057   }
2058 
2059   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2060     addAlignedMemoryOperands(Inst, N);
2061   }
2062 
2063   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2064     addAlignedMemoryOperands(Inst, N);
2065   }
2066 
2067   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2068     addAlignedMemoryOperands(Inst, N);
2069   }
2070 
2071   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2072     addAlignedMemoryOperands(Inst, N);
2073   }
2074 
2075   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2076     addAlignedMemoryOperands(Inst, N);
2077   }
2078 
2079   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2080     addAlignedMemoryOperands(Inst, N);
2081   }
2082 
2083   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2084     addAlignedMemoryOperands(Inst, N);
2085   }
2086 
2087   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2088     addAlignedMemoryOperands(Inst, N);
2089   }
2090 
2091   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2092     assert(N == 3 && "Invalid number of operands!");
2093     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2094     if (!Memory.OffsetRegNum) {
2095       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2096       // Special case for #-0
2097       if (Val == INT32_MIN) Val = 0;
2098       if (Val < 0) Val = -Val;
2099       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2100     } else {
2101       // For register offset, we encode the shift type and negation flag
2102       // here.
2103       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2104                               Memory.ShiftImm, Memory.ShiftType);
2105     }
2106     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2107     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2108     Inst.addOperand(MCOperand::CreateImm(Val));
2109   }
2110 
2111   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2112     assert(N == 2 && "Invalid number of operands!");
2113     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2114     assert(CE && "non-constant AM2OffsetImm operand!");
2115     int32_t Val = CE->getValue();
2116     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2117     // Special case for #-0
2118     if (Val == INT32_MIN) Val = 0;
2119     if (Val < 0) Val = -Val;
2120     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2121     Inst.addOperand(MCOperand::CreateReg(0));
2122     Inst.addOperand(MCOperand::CreateImm(Val));
2123   }
2124 
2125   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2126     assert(N == 3 && "Invalid number of operands!");
2127     // If we have an immediate that's not a constant, treat it as a label
2128     // reference needing a fixup. If it is a constant, it's something else
2129     // and we reject it.
2130     if (isImm()) {
2131       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2132       Inst.addOperand(MCOperand::CreateReg(0));
2133       Inst.addOperand(MCOperand::CreateImm(0));
2134       return;
2135     }
2136 
2137     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2138     if (!Memory.OffsetRegNum) {
2139       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2140       // Special case for #-0
2141       if (Val == INT32_MIN) Val = 0;
2142       if (Val < 0) Val = -Val;
2143       Val = ARM_AM::getAM3Opc(AddSub, Val);
2144     } else {
2145       // For register offset, we encode the shift type and negation flag
2146       // here.
2147       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2148     }
2149     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2150     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2151     Inst.addOperand(MCOperand::CreateImm(Val));
2152   }
2153 
2154   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2155     assert(N == 2 && "Invalid number of operands!");
2156     if (Kind == k_PostIndexRegister) {
2157       int32_t Val =
2158         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2159       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2160       Inst.addOperand(MCOperand::CreateImm(Val));
2161       return;
2162     }
2163 
2164     // Constant offset.
2165     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2166     int32_t Val = CE->getValue();
2167     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2168     // Special case for #-0
2169     if (Val == INT32_MIN) Val = 0;
2170     if (Val < 0) Val = -Val;
2171     Val = ARM_AM::getAM3Opc(AddSub, Val);
2172     Inst.addOperand(MCOperand::CreateReg(0));
2173     Inst.addOperand(MCOperand::CreateImm(Val));
2174   }
2175 
2176   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2177     assert(N == 2 && "Invalid number of operands!");
2178     // If we have an immediate that's not a constant, treat it as a label
2179     // reference needing a fixup. If it is a constant, it's something else
2180     // and we reject it.
2181     if (isImm()) {
2182       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2183       Inst.addOperand(MCOperand::CreateImm(0));
2184       return;
2185     }
2186 
2187     // The lower two bits are always zero and as such are not encoded.
2188     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2189     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2190     // Special case for #-0
2191     if (Val == INT32_MIN) Val = 0;
2192     if (Val < 0) Val = -Val;
2193     Val = ARM_AM::getAM5Opc(AddSub, Val);
2194     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2195     Inst.addOperand(MCOperand::CreateImm(Val));
2196   }
2197 
2198   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2199     assert(N == 2 && "Invalid number of operands!");
2200     // If we have an immediate that's not a constant, treat it as a label
2201     // reference needing a fixup. If it is a constant, it's something else
2202     // and we reject it.
2203     if (isImm()) {
2204       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2205       Inst.addOperand(MCOperand::CreateImm(0));
2206       return;
2207     }
2208 
2209     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2210     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2211     Inst.addOperand(MCOperand::CreateImm(Val));
2212   }
2213 
2214   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2215     assert(N == 2 && "Invalid number of operands!");
2216     // The lower two bits are always zero and as such are not encoded.
2217     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2218     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2219     Inst.addOperand(MCOperand::CreateImm(Val));
2220   }
2221 
2222   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2223     assert(N == 2 && "Invalid number of operands!");
2224     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2225     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2226     Inst.addOperand(MCOperand::CreateImm(Val));
2227   }
2228 
2229   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2230     addMemImm8OffsetOperands(Inst, N);
2231   }
2232 
2233   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2234     addMemImm8OffsetOperands(Inst, N);
2235   }
2236 
2237   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2238     assert(N == 2 && "Invalid number of operands!");
2239     // If this is an immediate, it's a label reference.
2240     if (isImm()) {
2241       addExpr(Inst, getImm());
2242       Inst.addOperand(MCOperand::CreateImm(0));
2243       return;
2244     }
2245 
2246     // Otherwise, it's a normal memory reg+offset.
2247     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2248     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2249     Inst.addOperand(MCOperand::CreateImm(Val));
2250   }
2251 
2252   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2253     assert(N == 2 && "Invalid number of operands!");
2254     // If this is an immediate, it's a label reference.
2255     if (isImm()) {
2256       addExpr(Inst, getImm());
2257       Inst.addOperand(MCOperand::CreateImm(0));
2258       return;
2259     }
2260 
2261     // Otherwise, it's a normal memory reg+offset.
2262     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2263     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2264     Inst.addOperand(MCOperand::CreateImm(Val));
2265   }
2266 
2267   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2268     assert(N == 2 && "Invalid number of operands!");
2269     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2270     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2271   }
2272 
2273   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2274     assert(N == 2 && "Invalid number of operands!");
2275     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2276     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2277   }
2278 
2279   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2280     assert(N == 3 && "Invalid number of operands!");
2281     unsigned Val =
2282       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2283                         Memory.ShiftImm, Memory.ShiftType);
2284     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2285     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2286     Inst.addOperand(MCOperand::CreateImm(Val));
2287   }
2288 
2289   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2290     assert(N == 3 && "Invalid number of operands!");
2291     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2292     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2293     Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2294   }
2295 
2296   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2297     assert(N == 2 && "Invalid number of operands!");
2298     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2299     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2300   }
2301 
2302   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2303     assert(N == 2 && "Invalid number of operands!");
2304     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2305     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2306     Inst.addOperand(MCOperand::CreateImm(Val));
2307   }
2308 
2309   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2310     assert(N == 2 && "Invalid number of operands!");
2311     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2312     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2313     Inst.addOperand(MCOperand::CreateImm(Val));
2314   }
2315 
2316   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2317     assert(N == 2 && "Invalid number of operands!");
2318     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2319     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2320     Inst.addOperand(MCOperand::CreateImm(Val));
2321   }
2322 
2323   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2324     assert(N == 2 && "Invalid number of operands!");
2325     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2326     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2327     Inst.addOperand(MCOperand::CreateImm(Val));
2328   }
2329 
2330   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2331     assert(N == 1 && "Invalid number of operands!");
2332     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2333     assert(CE && "non-constant post-idx-imm8 operand!");
2334     int Imm = CE->getValue();
2335     bool isAdd = Imm >= 0;
2336     if (Imm == INT32_MIN) Imm = 0;
2337     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2338     Inst.addOperand(MCOperand::CreateImm(Imm));
2339   }
2340 
2341   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2342     assert(N == 1 && "Invalid number of operands!");
2343     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2344     assert(CE && "non-constant post-idx-imm8s4 operand!");
2345     int Imm = CE->getValue();
2346     bool isAdd = Imm >= 0;
2347     if (Imm == INT32_MIN) Imm = 0;
2348     // Immediate is scaled by 4.
2349     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2350     Inst.addOperand(MCOperand::CreateImm(Imm));
2351   }
2352 
2353   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2354     assert(N == 2 && "Invalid number of operands!");
2355     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2356     Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2357   }
2358 
2359   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2360     assert(N == 2 && "Invalid number of operands!");
2361     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2362     // The sign, shift type, and shift amount are encoded in a single operand
2363     // using the AM2 encoding helpers.
2364     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2365     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2366                                      PostIdxReg.ShiftTy);
2367     Inst.addOperand(MCOperand::CreateImm(Imm));
2368   }
2369 
2370   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2371     assert(N == 1 && "Invalid number of operands!");
2372     Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2373   }
2374 
2375   void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2376     assert(N == 1 && "Invalid number of operands!");
2377     Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2378   }
2379 
2380   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2381     assert(N == 1 && "Invalid number of operands!");
2382     Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2383   }
2384 
2385   void addVecListOperands(MCInst &Inst, unsigned N) const {
2386     assert(N == 1 && "Invalid number of operands!");
2387     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2388   }
2389 
2390   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2391     assert(N == 2 && "Invalid number of operands!");
2392     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2393     Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2394   }
2395 
2396   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2397     assert(N == 1 && "Invalid number of operands!");
2398     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2399   }
2400 
2401   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2402     assert(N == 1 && "Invalid number of operands!");
2403     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2404   }
2405 
2406   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2407     assert(N == 1 && "Invalid number of operands!");
2408     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2409   }
2410 
2411   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2412     assert(N == 1 && "Invalid number of operands!");
2413     // The immediate encodes the type of constant as well as the value.
2414     // Mask in that this is an i8 splat.
2415     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2416     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2417   }
2418 
2419   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2420     assert(N == 1 && "Invalid number of operands!");
2421     // The immediate encodes the type of constant as well as the value.
2422     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2423     unsigned Value = CE->getValue();
2424     Value = ARM_AM::encodeNEONi16splat(Value);
2425     Inst.addOperand(MCOperand::CreateImm(Value));
2426   }
2427 
2428   void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2429     assert(N == 1 && "Invalid number of operands!");
2430     // The immediate encodes the type of constant as well as the value.
2431     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2432     unsigned Value = CE->getValue();
2433     Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2434     Inst.addOperand(MCOperand::CreateImm(Value));
2435   }
2436 
2437   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2438     assert(N == 1 && "Invalid number of operands!");
2439     // The immediate encodes the type of constant as well as the value.
2440     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2441     unsigned Value = CE->getValue();
2442     Value = ARM_AM::encodeNEONi32splat(Value);
2443     Inst.addOperand(MCOperand::CreateImm(Value));
2444   }
2445 
2446   void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2447     assert(N == 1 && "Invalid number of operands!");
2448     // The immediate encodes the type of constant as well as the value.
2449     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2450     unsigned Value = CE->getValue();
2451     Value = ARM_AM::encodeNEONi32splat(~Value);
2452     Inst.addOperand(MCOperand::CreateImm(Value));
2453   }
2454 
2455   void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2456     assert(N == 1 && "Invalid number of operands!");
2457     // The immediate encodes the type of constant as well as the value.
2458     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2459     unsigned Value = CE->getValue();
2460     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2461             Inst.getOpcode() == ARM::VMOVv16i8) &&
2462            "All vmvn instructions that wants to replicate non-zero byte "
2463            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2464     unsigned B = ((~Value) & 0xff);
2465     B |= 0xe00; // cmode = 0b1110
2466     Inst.addOperand(MCOperand::CreateImm(B));
2467   }
2468   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2469     assert(N == 1 && "Invalid number of operands!");
2470     // The immediate encodes the type of constant as well as the value.
2471     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2472     unsigned Value = CE->getValue();
2473     if (Value >= 256 && Value <= 0xffff)
2474       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2475     else if (Value > 0xffff && Value <= 0xffffff)
2476       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2477     else if (Value > 0xffffff)
2478       Value = (Value >> 24) | 0x600;
2479     Inst.addOperand(MCOperand::CreateImm(Value));
2480   }
2481 
2482   void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2483     assert(N == 1 && "Invalid number of operands!");
2484     // The immediate encodes the type of constant as well as the value.
2485     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2486     unsigned Value = CE->getValue();
2487     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2488             Inst.getOpcode() == ARM::VMOVv16i8) &&
2489            "All instructions that wants to replicate non-zero byte "
2490            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2491     unsigned B = Value & 0xff;
2492     B |= 0xe00; // cmode = 0b1110
2493     Inst.addOperand(MCOperand::CreateImm(B));
2494   }
2495   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2496     assert(N == 1 && "Invalid number of operands!");
2497     // The immediate encodes the type of constant as well as the value.
2498     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2499     unsigned Value = ~CE->getValue();
2500     if (Value >= 256 && Value <= 0xffff)
2501       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2502     else if (Value > 0xffff && Value <= 0xffffff)
2503       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2504     else if (Value > 0xffffff)
2505       Value = (Value >> 24) | 0x600;
2506     Inst.addOperand(MCOperand::CreateImm(Value));
2507   }
2508 
2509   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2510     assert(N == 1 && "Invalid number of operands!");
2511     // The immediate encodes the type of constant as well as the value.
2512     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2513     uint64_t Value = CE->getValue();
2514     unsigned Imm = 0;
2515     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2516       Imm |= (Value & 1) << i;
2517     }
2518     Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2519   }
2520 
2521   void print(raw_ostream &OS) const override;
2522 
2523   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2524     auto Op = make_unique<ARMOperand>(k_ITCondMask);
2525     Op->ITMask.Mask = Mask;
2526     Op->StartLoc = S;
2527     Op->EndLoc = S;
2528     return Op;
2529   }
2530 
2531   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2532                                                     SMLoc S) {
2533     auto Op = make_unique<ARMOperand>(k_CondCode);
2534     Op->CC.Val = CC;
2535     Op->StartLoc = S;
2536     Op->EndLoc = S;
2537     return Op;
2538   }
2539 
2540   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2541     auto Op = make_unique<ARMOperand>(k_CoprocNum);
2542     Op->Cop.Val = CopVal;
2543     Op->StartLoc = S;
2544     Op->EndLoc = S;
2545     return Op;
2546   }
2547 
2548   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2549     auto Op = make_unique<ARMOperand>(k_CoprocReg);
2550     Op->Cop.Val = CopVal;
2551     Op->StartLoc = S;
2552     Op->EndLoc = S;
2553     return Op;
2554   }
2555 
2556   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2557                                                         SMLoc E) {
2558     auto Op = make_unique<ARMOperand>(k_CoprocOption);
2559     Op->Cop.Val = Val;
2560     Op->StartLoc = S;
2561     Op->EndLoc = E;
2562     return Op;
2563   }
2564 
2565   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2566     auto Op = make_unique<ARMOperand>(k_CCOut);
2567     Op->Reg.RegNum = RegNum;
2568     Op->StartLoc = S;
2569     Op->EndLoc = S;
2570     return Op;
2571   }
2572 
2573   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2574     auto Op = make_unique<ARMOperand>(k_Token);
2575     Op->Tok.Data = Str.data();
2576     Op->Tok.Length = Str.size();
2577     Op->StartLoc = S;
2578     Op->EndLoc = S;
2579     return Op;
2580   }
2581 
2582   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2583                                                SMLoc E) {
2584     auto Op = make_unique<ARMOperand>(k_Register);
2585     Op->Reg.RegNum = RegNum;
2586     Op->StartLoc = S;
2587     Op->EndLoc = E;
2588     return Op;
2589   }
2590 
2591   static std::unique_ptr<ARMOperand>
2592   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2593                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2594                         SMLoc E) {
2595     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2596     Op->RegShiftedReg.ShiftTy = ShTy;
2597     Op->RegShiftedReg.SrcReg = SrcReg;
2598     Op->RegShiftedReg.ShiftReg = ShiftReg;
2599     Op->RegShiftedReg.ShiftImm = ShiftImm;
2600     Op->StartLoc = S;
2601     Op->EndLoc = E;
2602     return Op;
2603   }
2604 
2605   static std::unique_ptr<ARMOperand>
2606   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2607                          unsigned ShiftImm, SMLoc S, SMLoc E) {
2608     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2609     Op->RegShiftedImm.ShiftTy = ShTy;
2610     Op->RegShiftedImm.SrcReg = SrcReg;
2611     Op->RegShiftedImm.ShiftImm = ShiftImm;
2612     Op->StartLoc = S;
2613     Op->EndLoc = E;
2614     return Op;
2615   }
2616 
2617   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2618                                                       SMLoc S, SMLoc E) {
2619     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2620     Op->ShifterImm.isASR = isASR;
2621     Op->ShifterImm.Imm = Imm;
2622     Op->StartLoc = S;
2623     Op->EndLoc = E;
2624     return Op;
2625   }
2626 
2627   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2628                                                   SMLoc E) {
2629     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2630     Op->RotImm.Imm = Imm;
2631     Op->StartLoc = S;
2632     Op->EndLoc = E;
2633     return Op;
2634   }
2635 
2636   static std::unique_ptr<ARMOperand>
2637   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2638     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2639     Op->Bitfield.LSB = LSB;
2640     Op->Bitfield.Width = Width;
2641     Op->StartLoc = S;
2642     Op->EndLoc = E;
2643     return Op;
2644   }
2645 
2646   static std::unique_ptr<ARMOperand>
2647   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2648                 SMLoc StartLoc, SMLoc EndLoc) {
2649     assert (Regs.size() > 0 && "RegList contains no registers?");
2650     KindTy Kind = k_RegisterList;
2651 
2652     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2653       Kind = k_DPRRegisterList;
2654     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2655              contains(Regs.front().second))
2656       Kind = k_SPRRegisterList;
2657 
2658     // Sort based on the register encoding values.
2659     array_pod_sort(Regs.begin(), Regs.end());
2660 
2661     auto Op = make_unique<ARMOperand>(Kind);
2662     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2663            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2664       Op->Registers.push_back(I->second);
2665     Op->StartLoc = StartLoc;
2666     Op->EndLoc = EndLoc;
2667     return Op;
2668   }
2669 
2670   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2671                                                       unsigned Count,
2672                                                       bool isDoubleSpaced,
2673                                                       SMLoc S, SMLoc E) {
2674     auto Op = make_unique<ARMOperand>(k_VectorList);
2675     Op->VectorList.RegNum = RegNum;
2676     Op->VectorList.Count = Count;
2677     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2678     Op->StartLoc = S;
2679     Op->EndLoc = E;
2680     return Op;
2681   }
2682 
2683   static std::unique_ptr<ARMOperand>
2684   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2685                            SMLoc S, SMLoc E) {
2686     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2687     Op->VectorList.RegNum = RegNum;
2688     Op->VectorList.Count = Count;
2689     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2690     Op->StartLoc = S;
2691     Op->EndLoc = E;
2692     return Op;
2693   }
2694 
2695   static std::unique_ptr<ARMOperand>
2696   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2697                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
2698     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2699     Op->VectorList.RegNum = RegNum;
2700     Op->VectorList.Count = Count;
2701     Op->VectorList.LaneIndex = Index;
2702     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2703     Op->StartLoc = S;
2704     Op->EndLoc = E;
2705     return Op;
2706   }
2707 
2708   static std::unique_ptr<ARMOperand>
2709   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2710     auto Op = make_unique<ARMOperand>(k_VectorIndex);
2711     Op->VectorIndex.Val = Idx;
2712     Op->StartLoc = S;
2713     Op->EndLoc = E;
2714     return Op;
2715   }
2716 
2717   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2718                                                SMLoc E) {
2719     auto Op = make_unique<ARMOperand>(k_Immediate);
2720     Op->Imm.Val = Val;
2721     Op->StartLoc = S;
2722     Op->EndLoc = E;
2723     return Op;
2724   }
2725 
2726   static std::unique_ptr<ARMOperand>
2727   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2728             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2729             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2730             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2731     auto Op = make_unique<ARMOperand>(k_Memory);
2732     Op->Memory.BaseRegNum = BaseRegNum;
2733     Op->Memory.OffsetImm = OffsetImm;
2734     Op->Memory.OffsetRegNum = OffsetRegNum;
2735     Op->Memory.ShiftType = ShiftType;
2736     Op->Memory.ShiftImm = ShiftImm;
2737     Op->Memory.Alignment = Alignment;
2738     Op->Memory.isNegative = isNegative;
2739     Op->StartLoc = S;
2740     Op->EndLoc = E;
2741     Op->AlignmentLoc = AlignmentLoc;
2742     return Op;
2743   }
2744 
2745   static std::unique_ptr<ARMOperand>
2746   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2747                    unsigned ShiftImm, SMLoc S, SMLoc E) {
2748     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2749     Op->PostIdxReg.RegNum = RegNum;
2750     Op->PostIdxReg.isAdd = isAdd;
2751     Op->PostIdxReg.ShiftTy = ShiftTy;
2752     Op->PostIdxReg.ShiftImm = ShiftImm;
2753     Op->StartLoc = S;
2754     Op->EndLoc = E;
2755     return Op;
2756   }
2757 
2758   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2759                                                          SMLoc S) {
2760     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2761     Op->MBOpt.Val = Opt;
2762     Op->StartLoc = S;
2763     Op->EndLoc = S;
2764     return Op;
2765   }
2766 
2767   static std::unique_ptr<ARMOperand>
2768   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2769     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2770     Op->ISBOpt.Val = Opt;
2771     Op->StartLoc = S;
2772     Op->EndLoc = S;
2773     return Op;
2774   }
2775 
2776   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2777                                                       SMLoc S) {
2778     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2779     Op->IFlags.Val = IFlags;
2780     Op->StartLoc = S;
2781     Op->EndLoc = S;
2782     return Op;
2783   }
2784 
2785   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2786     auto Op = make_unique<ARMOperand>(k_MSRMask);
2787     Op->MMask.Val = MMask;
2788     Op->StartLoc = S;
2789     Op->EndLoc = S;
2790     return Op;
2791   }
2792 
2793   static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2794     auto Op = make_unique<ARMOperand>(k_BankedReg);
2795     Op->BankedReg.Val = Reg;
2796     Op->StartLoc = S;
2797     Op->EndLoc = S;
2798     return Op;
2799   }
2800 };
2801 
2802 } // end anonymous namespace.
2803 
2804 void ARMOperand::print(raw_ostream &OS) const {
2805   switch (Kind) {
2806   case k_CondCode:
2807     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2808     break;
2809   case k_CCOut:
2810     OS << "<ccout " << getReg() << ">";
2811     break;
2812   case k_ITCondMask: {
2813     static const char *const MaskStr[] = {
2814       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2815       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2816     };
2817     assert((ITMask.Mask & 0xf) == ITMask.Mask);
2818     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2819     break;
2820   }
2821   case k_CoprocNum:
2822     OS << "<coprocessor number: " << getCoproc() << ">";
2823     break;
2824   case k_CoprocReg:
2825     OS << "<coprocessor register: " << getCoproc() << ">";
2826     break;
2827   case k_CoprocOption:
2828     OS << "<coprocessor option: " << CoprocOption.Val << ">";
2829     break;
2830   case k_MSRMask:
2831     OS << "<mask: " << getMSRMask() << ">";
2832     break;
2833   case k_BankedReg:
2834     OS << "<banked reg: " << getBankedReg() << ">";
2835     break;
2836   case k_Immediate:
2837     getImm()->print(OS);
2838     break;
2839   case k_MemBarrierOpt:
2840     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2841     break;
2842   case k_InstSyncBarrierOpt:
2843     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2844     break;
2845   case k_Memory:
2846     OS << "<memory "
2847        << " base:" << Memory.BaseRegNum;
2848     OS << ">";
2849     break;
2850   case k_PostIndexRegister:
2851     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2852        << PostIdxReg.RegNum;
2853     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2854       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2855          << PostIdxReg.ShiftImm;
2856     OS << ">";
2857     break;
2858   case k_ProcIFlags: {
2859     OS << "<ARM_PROC::";
2860     unsigned IFlags = getProcIFlags();
2861     for (int i=2; i >= 0; --i)
2862       if (IFlags & (1 << i))
2863         OS << ARM_PROC::IFlagsToString(1 << i);
2864     OS << ">";
2865     break;
2866   }
2867   case k_Register:
2868     OS << "<register " << getReg() << ">";
2869     break;
2870   case k_ShifterImmediate:
2871     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2872        << " #" << ShifterImm.Imm << ">";
2873     break;
2874   case k_ShiftedRegister:
2875     OS << "<so_reg_reg "
2876        << RegShiftedReg.SrcReg << " "
2877        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2878        << " " << RegShiftedReg.ShiftReg << ">";
2879     break;
2880   case k_ShiftedImmediate:
2881     OS << "<so_reg_imm "
2882        << RegShiftedImm.SrcReg << " "
2883        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2884        << " #" << RegShiftedImm.ShiftImm << ">";
2885     break;
2886   case k_RotateImmediate:
2887     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2888     break;
2889   case k_BitfieldDescriptor:
2890     OS << "<bitfield " << "lsb: " << Bitfield.LSB
2891        << ", width: " << Bitfield.Width << ">";
2892     break;
2893   case k_RegisterList:
2894   case k_DPRRegisterList:
2895   case k_SPRRegisterList: {
2896     OS << "<register_list ";
2897 
2898     const SmallVectorImpl<unsigned> &RegList = getRegList();
2899     for (SmallVectorImpl<unsigned>::const_iterator
2900            I = RegList.begin(), E = RegList.end(); I != E; ) {
2901       OS << *I;
2902       if (++I < E) OS << ", ";
2903     }
2904 
2905     OS << ">";
2906     break;
2907   }
2908   case k_VectorList:
2909     OS << "<vector_list " << VectorList.Count << " * "
2910        << VectorList.RegNum << ">";
2911     break;
2912   case k_VectorListAllLanes:
2913     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2914        << VectorList.RegNum << ">";
2915     break;
2916   case k_VectorListIndexed:
2917     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2918        << VectorList.Count << " * " << VectorList.RegNum << ">";
2919     break;
2920   case k_Token:
2921     OS << "'" << getToken() << "'";
2922     break;
2923   case k_VectorIndex:
2924     OS << "<vectorindex " << getVectorIndex() << ">";
2925     break;
2926   }
2927 }
2928 
2929 /// @name Auto-generated Match Functions
2930 /// {
2931 
2932 static unsigned MatchRegisterName(StringRef Name);
2933 
2934 /// }
2935 
2936 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2937                                  SMLoc &StartLoc, SMLoc &EndLoc) {
2938   StartLoc = Parser.getTok().getLoc();
2939   EndLoc = Parser.getTok().getEndLoc();
2940   RegNo = tryParseRegister();
2941 
2942   return (RegNo == (unsigned)-1);
2943 }
2944 
2945 /// Try to parse a register name.  The token must be an Identifier when called,
2946 /// and if it is a register name the token is eaten and the register number is
2947 /// returned.  Otherwise return -1.
2948 ///
2949 int ARMAsmParser::tryParseRegister() {
2950   const AsmToken &Tok = Parser.getTok();
2951   if (Tok.isNot(AsmToken::Identifier)) return -1;
2952 
2953   std::string lowerCase = Tok.getString().lower();
2954   unsigned RegNum = MatchRegisterName(lowerCase);
2955   if (!RegNum) {
2956     RegNum = StringSwitch<unsigned>(lowerCase)
2957       .Case("r13", ARM::SP)
2958       .Case("r14", ARM::LR)
2959       .Case("r15", ARM::PC)
2960       .Case("ip", ARM::R12)
2961       // Additional register name aliases for 'gas' compatibility.
2962       .Case("a1", ARM::R0)
2963       .Case("a2", ARM::R1)
2964       .Case("a3", ARM::R2)
2965       .Case("a4", ARM::R3)
2966       .Case("v1", ARM::R4)
2967       .Case("v2", ARM::R5)
2968       .Case("v3", ARM::R6)
2969       .Case("v4", ARM::R7)
2970       .Case("v5", ARM::R8)
2971       .Case("v6", ARM::R9)
2972       .Case("v7", ARM::R10)
2973       .Case("v8", ARM::R11)
2974       .Case("sb", ARM::R9)
2975       .Case("sl", ARM::R10)
2976       .Case("fp", ARM::R11)
2977       .Default(0);
2978   }
2979   if (!RegNum) {
2980     // Check for aliases registered via .req. Canonicalize to lower case.
2981     // That's more consistent since register names are case insensitive, and
2982     // it's how the original entry was passed in from MC/MCParser/AsmParser.
2983     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2984     // If no match, return failure.
2985     if (Entry == RegisterReqs.end())
2986       return -1;
2987     Parser.Lex(); // Eat identifier token.
2988     return Entry->getValue();
2989   }
2990 
2991   Parser.Lex(); // Eat identifier token.
2992 
2993   return RegNum;
2994 }
2995 
2996 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2997 // If a recoverable error occurs, return 1. If an irrecoverable error
2998 // occurs, return -1. An irrecoverable error is one where tokens have been
2999 // consumed in the process of trying to parse the shifter (i.e., when it is
3000 // indeed a shifter operand, but malformed).
3001 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3002   SMLoc S = Parser.getTok().getLoc();
3003   const AsmToken &Tok = Parser.getTok();
3004   if (Tok.isNot(AsmToken::Identifier))
3005     return -1;
3006 
3007   std::string lowerCase = Tok.getString().lower();
3008   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3009       .Case("asl", ARM_AM::lsl)
3010       .Case("lsl", ARM_AM::lsl)
3011       .Case("lsr", ARM_AM::lsr)
3012       .Case("asr", ARM_AM::asr)
3013       .Case("ror", ARM_AM::ror)
3014       .Case("rrx", ARM_AM::rrx)
3015       .Default(ARM_AM::no_shift);
3016 
3017   if (ShiftTy == ARM_AM::no_shift)
3018     return 1;
3019 
3020   Parser.Lex(); // Eat the operator.
3021 
3022   // The source register for the shift has already been added to the
3023   // operand list, so we need to pop it off and combine it into the shifted
3024   // register operand instead.
3025   std::unique_ptr<ARMOperand> PrevOp(
3026       (ARMOperand *)Operands.pop_back_val().release());
3027   if (!PrevOp->isReg())
3028     return Error(PrevOp->getStartLoc(), "shift must be of a register");
3029   int SrcReg = PrevOp->getReg();
3030 
3031   SMLoc EndLoc;
3032   int64_t Imm = 0;
3033   int ShiftReg = 0;
3034   if (ShiftTy == ARM_AM::rrx) {
3035     // RRX Doesn't have an explicit shift amount. The encoder expects
3036     // the shift register to be the same as the source register. Seems odd,
3037     // but OK.
3038     ShiftReg = SrcReg;
3039   } else {
3040     // Figure out if this is shifted by a constant or a register (for non-RRX).
3041     if (Parser.getTok().is(AsmToken::Hash) ||
3042         Parser.getTok().is(AsmToken::Dollar)) {
3043       Parser.Lex(); // Eat hash.
3044       SMLoc ImmLoc = Parser.getTok().getLoc();
3045       const MCExpr *ShiftExpr = nullptr;
3046       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3047         Error(ImmLoc, "invalid immediate shift value");
3048         return -1;
3049       }
3050       // The expression must be evaluatable as an immediate.
3051       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3052       if (!CE) {
3053         Error(ImmLoc, "invalid immediate shift value");
3054         return -1;
3055       }
3056       // Range check the immediate.
3057       // lsl, ror: 0 <= imm <= 31
3058       // lsr, asr: 0 <= imm <= 32
3059       Imm = CE->getValue();
3060       if (Imm < 0 ||
3061           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3062           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3063         Error(ImmLoc, "immediate shift value out of range");
3064         return -1;
3065       }
3066       // shift by zero is a nop. Always send it through as lsl.
3067       // ('as' compatibility)
3068       if (Imm == 0)
3069         ShiftTy = ARM_AM::lsl;
3070     } else if (Parser.getTok().is(AsmToken::Identifier)) {
3071       SMLoc L = Parser.getTok().getLoc();
3072       EndLoc = Parser.getTok().getEndLoc();
3073       ShiftReg = tryParseRegister();
3074       if (ShiftReg == -1) {
3075         Error(L, "expected immediate or register in shift operand");
3076         return -1;
3077       }
3078     } else {
3079       Error(Parser.getTok().getLoc(),
3080             "expected immediate or register in shift operand");
3081       return -1;
3082     }
3083   }
3084 
3085   if (ShiftReg && ShiftTy != ARM_AM::rrx)
3086     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3087                                                          ShiftReg, Imm,
3088                                                          S, EndLoc));
3089   else
3090     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3091                                                           S, EndLoc));
3092 
3093   return 0;
3094 }
3095 
3096 
3097 /// Try to parse a register name.  The token must be an Identifier when called.
3098 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3099 /// if there is a "writeback". 'true' if it's not a register.
3100 ///
3101 /// TODO this is likely to change to allow different register types and or to
3102 /// parse for a specific register type.
3103 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3104   const AsmToken &RegTok = Parser.getTok();
3105   int RegNo = tryParseRegister();
3106   if (RegNo == -1)
3107     return true;
3108 
3109   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3110                                            RegTok.getEndLoc()));
3111 
3112   const AsmToken &ExclaimTok = Parser.getTok();
3113   if (ExclaimTok.is(AsmToken::Exclaim)) {
3114     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3115                                                ExclaimTok.getLoc()));
3116     Parser.Lex(); // Eat exclaim token
3117     return false;
3118   }
3119 
3120   // Also check for an index operand. This is only legal for vector registers,
3121   // but that'll get caught OK in operand matching, so we don't need to
3122   // explicitly filter everything else out here.
3123   if (Parser.getTok().is(AsmToken::LBrac)) {
3124     SMLoc SIdx = Parser.getTok().getLoc();
3125     Parser.Lex(); // Eat left bracket token.
3126 
3127     const MCExpr *ImmVal;
3128     if (getParser().parseExpression(ImmVal))
3129       return true;
3130     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3131     if (!MCE)
3132       return TokError("immediate value expected for vector index");
3133 
3134     if (Parser.getTok().isNot(AsmToken::RBrac))
3135       return Error(Parser.getTok().getLoc(), "']' expected");
3136 
3137     SMLoc E = Parser.getTok().getEndLoc();
3138     Parser.Lex(); // Eat right bracket token.
3139 
3140     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3141                                                      SIdx, E,
3142                                                      getContext()));
3143   }
3144 
3145   return false;
3146 }
3147 
3148 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3149 /// instruction with a symbolic operand name.
3150 /// We accept "crN" syntax for GAS compatibility.
3151 /// <operand-name> ::= <prefix><number>
3152 /// If CoprocOp is 'c', then:
3153 ///   <prefix> ::= c | cr
3154 /// If CoprocOp is 'p', then :
3155 ///   <prefix> ::= p
3156 /// <number> ::= integer in range [0, 15]
3157 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3158   // Use the same layout as the tablegen'erated register name matcher. Ugly,
3159   // but efficient.
3160   if (Name.size() < 2 || Name[0] != CoprocOp)
3161     return -1;
3162   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3163 
3164   switch (Name.size()) {
3165   default: return -1;
3166   case 1:
3167     switch (Name[0]) {
3168     default:  return -1;
3169     case '0': return 0;
3170     case '1': return 1;
3171     case '2': return 2;
3172     case '3': return 3;
3173     case '4': return 4;
3174     case '5': return 5;
3175     case '6': return 6;
3176     case '7': return 7;
3177     case '8': return 8;
3178     case '9': return 9;
3179     }
3180   case 2:
3181     if (Name[0] != '1')
3182       return -1;
3183     switch (Name[1]) {
3184     default:  return -1;
3185     // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3186     // However, old cores (v5/v6) did use them in that way.
3187     case '0': return 10;
3188     case '1': return 11;
3189     case '2': return 12;
3190     case '3': return 13;
3191     case '4': return 14;
3192     case '5': return 15;
3193     }
3194   }
3195 }
3196 
3197 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3198 ARMAsmParser::OperandMatchResultTy
3199 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3200   SMLoc S = Parser.getTok().getLoc();
3201   const AsmToken &Tok = Parser.getTok();
3202   if (!Tok.is(AsmToken::Identifier))
3203     return MatchOperand_NoMatch;
3204   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3205     .Case("eq", ARMCC::EQ)
3206     .Case("ne", ARMCC::NE)
3207     .Case("hs", ARMCC::HS)
3208     .Case("cs", ARMCC::HS)
3209     .Case("lo", ARMCC::LO)
3210     .Case("cc", ARMCC::LO)
3211     .Case("mi", ARMCC::MI)
3212     .Case("pl", ARMCC::PL)
3213     .Case("vs", ARMCC::VS)
3214     .Case("vc", ARMCC::VC)
3215     .Case("hi", ARMCC::HI)
3216     .Case("ls", ARMCC::LS)
3217     .Case("ge", ARMCC::GE)
3218     .Case("lt", ARMCC::LT)
3219     .Case("gt", ARMCC::GT)
3220     .Case("le", ARMCC::LE)
3221     .Case("al", ARMCC::AL)
3222     .Default(~0U);
3223   if (CC == ~0U)
3224     return MatchOperand_NoMatch;
3225   Parser.Lex(); // Eat the token.
3226 
3227   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3228 
3229   return MatchOperand_Success;
3230 }
3231 
3232 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3233 /// token must be an Identifier when called, and if it is a coprocessor
3234 /// number, the token is eaten and the operand is added to the operand list.
3235 ARMAsmParser::OperandMatchResultTy
3236 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3237   SMLoc S = Parser.getTok().getLoc();
3238   const AsmToken &Tok = Parser.getTok();
3239   if (Tok.isNot(AsmToken::Identifier))
3240     return MatchOperand_NoMatch;
3241 
3242   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3243   if (Num == -1)
3244     return MatchOperand_NoMatch;
3245   // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3246   if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3247     return MatchOperand_NoMatch;
3248 
3249   Parser.Lex(); // Eat identifier token.
3250   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3251   return MatchOperand_Success;
3252 }
3253 
3254 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3255 /// token must be an Identifier when called, and if it is a coprocessor
3256 /// number, the token is eaten and the operand is added to the operand list.
3257 ARMAsmParser::OperandMatchResultTy
3258 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3259   SMLoc S = Parser.getTok().getLoc();
3260   const AsmToken &Tok = Parser.getTok();
3261   if (Tok.isNot(AsmToken::Identifier))
3262     return MatchOperand_NoMatch;
3263 
3264   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3265   if (Reg == -1)
3266     return MatchOperand_NoMatch;
3267 
3268   Parser.Lex(); // Eat identifier token.
3269   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3270   return MatchOperand_Success;
3271 }
3272 
3273 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3274 /// coproc_option : '{' imm0_255 '}'
3275 ARMAsmParser::OperandMatchResultTy
3276 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3277   SMLoc S = Parser.getTok().getLoc();
3278 
3279   // If this isn't a '{', this isn't a coprocessor immediate operand.
3280   if (Parser.getTok().isNot(AsmToken::LCurly))
3281     return MatchOperand_NoMatch;
3282   Parser.Lex(); // Eat the '{'
3283 
3284   const MCExpr *Expr;
3285   SMLoc Loc = Parser.getTok().getLoc();
3286   if (getParser().parseExpression(Expr)) {
3287     Error(Loc, "illegal expression");
3288     return MatchOperand_ParseFail;
3289   }
3290   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3291   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3292     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3293     return MatchOperand_ParseFail;
3294   }
3295   int Val = CE->getValue();
3296 
3297   // Check for and consume the closing '}'
3298   if (Parser.getTok().isNot(AsmToken::RCurly))
3299     return MatchOperand_ParseFail;
3300   SMLoc E = Parser.getTok().getEndLoc();
3301   Parser.Lex(); // Eat the '}'
3302 
3303   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3304   return MatchOperand_Success;
3305 }
3306 
3307 // For register list parsing, we need to map from raw GPR register numbering
3308 // to the enumeration values. The enumeration values aren't sorted by
3309 // register number due to our using "sp", "lr" and "pc" as canonical names.
3310 static unsigned getNextRegister(unsigned Reg) {
3311   // If this is a GPR, we need to do it manually, otherwise we can rely
3312   // on the sort ordering of the enumeration since the other reg-classes
3313   // are sane.
3314   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3315     return Reg + 1;
3316   switch(Reg) {
3317   default: llvm_unreachable("Invalid GPR number!");
3318   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3319   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3320   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3321   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3322   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3323   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3324   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3325   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3326   }
3327 }
3328 
3329 // Return the low-subreg of a given Q register.
3330 static unsigned getDRegFromQReg(unsigned QReg) {
3331   switch (QReg) {
3332   default: llvm_unreachable("expected a Q register!");
3333   case ARM::Q0:  return ARM::D0;
3334   case ARM::Q1:  return ARM::D2;
3335   case ARM::Q2:  return ARM::D4;
3336   case ARM::Q3:  return ARM::D6;
3337   case ARM::Q4:  return ARM::D8;
3338   case ARM::Q5:  return ARM::D10;
3339   case ARM::Q6:  return ARM::D12;
3340   case ARM::Q7:  return ARM::D14;
3341   case ARM::Q8:  return ARM::D16;
3342   case ARM::Q9:  return ARM::D18;
3343   case ARM::Q10: return ARM::D20;
3344   case ARM::Q11: return ARM::D22;
3345   case ARM::Q12: return ARM::D24;
3346   case ARM::Q13: return ARM::D26;
3347   case ARM::Q14: return ARM::D28;
3348   case ARM::Q15: return ARM::D30;
3349   }
3350 }
3351 
3352 /// Parse a register list.
3353 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3354   assert(Parser.getTok().is(AsmToken::LCurly) &&
3355          "Token is not a Left Curly Brace");
3356   SMLoc S = Parser.getTok().getLoc();
3357   Parser.Lex(); // Eat '{' token.
3358   SMLoc RegLoc = Parser.getTok().getLoc();
3359 
3360   // Check the first register in the list to see what register class
3361   // this is a list of.
3362   int Reg = tryParseRegister();
3363   if (Reg == -1)
3364     return Error(RegLoc, "register expected");
3365 
3366   // The reglist instructions have at most 16 registers, so reserve
3367   // space for that many.
3368   int EReg = 0;
3369   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3370 
3371   // Allow Q regs and just interpret them as the two D sub-registers.
3372   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3373     Reg = getDRegFromQReg(Reg);
3374     EReg = MRI->getEncodingValue(Reg);
3375     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3376     ++Reg;
3377   }
3378   const MCRegisterClass *RC;
3379   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3380     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3381   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3382     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3383   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3384     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3385   else
3386     return Error(RegLoc, "invalid register in register list");
3387 
3388   // Store the register.
3389   EReg = MRI->getEncodingValue(Reg);
3390   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3391 
3392   // This starts immediately after the first register token in the list,
3393   // so we can see either a comma or a minus (range separator) as a legal
3394   // next token.
3395   while (Parser.getTok().is(AsmToken::Comma) ||
3396          Parser.getTok().is(AsmToken::Minus)) {
3397     if (Parser.getTok().is(AsmToken::Minus)) {
3398       Parser.Lex(); // Eat the minus.
3399       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3400       int EndReg = tryParseRegister();
3401       if (EndReg == -1)
3402         return Error(AfterMinusLoc, "register expected");
3403       // Allow Q regs and just interpret them as the two D sub-registers.
3404       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3405         EndReg = getDRegFromQReg(EndReg) + 1;
3406       // If the register is the same as the start reg, there's nothing
3407       // more to do.
3408       if (Reg == EndReg)
3409         continue;
3410       // The register must be in the same register class as the first.
3411       if (!RC->contains(EndReg))
3412         return Error(AfterMinusLoc, "invalid register in register list");
3413       // Ranges must go from low to high.
3414       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3415         return Error(AfterMinusLoc, "bad range in register list");
3416 
3417       // Add all the registers in the range to the register list.
3418       while (Reg != EndReg) {
3419         Reg = getNextRegister(Reg);
3420         EReg = MRI->getEncodingValue(Reg);
3421         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3422       }
3423       continue;
3424     }
3425     Parser.Lex(); // Eat the comma.
3426     RegLoc = Parser.getTok().getLoc();
3427     int OldReg = Reg;
3428     const AsmToken RegTok = Parser.getTok();
3429     Reg = tryParseRegister();
3430     if (Reg == -1)
3431       return Error(RegLoc, "register expected");
3432     // Allow Q regs and just interpret them as the two D sub-registers.
3433     bool isQReg = false;
3434     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3435       Reg = getDRegFromQReg(Reg);
3436       isQReg = true;
3437     }
3438     // The register must be in the same register class as the first.
3439     if (!RC->contains(Reg))
3440       return Error(RegLoc, "invalid register in register list");
3441     // List must be monotonically increasing.
3442     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3443       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3444         Warning(RegLoc, "register list not in ascending order");
3445       else
3446         return Error(RegLoc, "register list not in ascending order");
3447     }
3448     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3449       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3450               ") in register list");
3451       continue;
3452     }
3453     // VFP register lists must also be contiguous.
3454     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3455         Reg != OldReg + 1)
3456       return Error(RegLoc, "non-contiguous register range");
3457     EReg = MRI->getEncodingValue(Reg);
3458     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3459     if (isQReg) {
3460       EReg = MRI->getEncodingValue(++Reg);
3461       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3462     }
3463   }
3464 
3465   if (Parser.getTok().isNot(AsmToken::RCurly))
3466     return Error(Parser.getTok().getLoc(), "'}' expected");
3467   SMLoc E = Parser.getTok().getEndLoc();
3468   Parser.Lex(); // Eat '}' token.
3469 
3470   // Push the register list operand.
3471   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3472 
3473   // The ARM system instruction variants for LDM/STM have a '^' token here.
3474   if (Parser.getTok().is(AsmToken::Caret)) {
3475     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3476     Parser.Lex(); // Eat '^' token.
3477   }
3478 
3479   return false;
3480 }
3481 
3482 // Helper function to parse the lane index for vector lists.
3483 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3484 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3485   Index = 0; // Always return a defined index value.
3486   if (Parser.getTok().is(AsmToken::LBrac)) {
3487     Parser.Lex(); // Eat the '['.
3488     if (Parser.getTok().is(AsmToken::RBrac)) {
3489       // "Dn[]" is the 'all lanes' syntax.
3490       LaneKind = AllLanes;
3491       EndLoc = Parser.getTok().getEndLoc();
3492       Parser.Lex(); // Eat the ']'.
3493       return MatchOperand_Success;
3494     }
3495 
3496     // There's an optional '#' token here. Normally there wouldn't be, but
3497     // inline assemble puts one in, and it's friendly to accept that.
3498     if (Parser.getTok().is(AsmToken::Hash))
3499       Parser.Lex(); // Eat '#' or '$'.
3500 
3501     const MCExpr *LaneIndex;
3502     SMLoc Loc = Parser.getTok().getLoc();
3503     if (getParser().parseExpression(LaneIndex)) {
3504       Error(Loc, "illegal expression");
3505       return MatchOperand_ParseFail;
3506     }
3507     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3508     if (!CE) {
3509       Error(Loc, "lane index must be empty or an integer");
3510       return MatchOperand_ParseFail;
3511     }
3512     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3513       Error(Parser.getTok().getLoc(), "']' expected");
3514       return MatchOperand_ParseFail;
3515     }
3516     EndLoc = Parser.getTok().getEndLoc();
3517     Parser.Lex(); // Eat the ']'.
3518     int64_t Val = CE->getValue();
3519 
3520     // FIXME: Make this range check context sensitive for .8, .16, .32.
3521     if (Val < 0 || Val > 7) {
3522       Error(Parser.getTok().getLoc(), "lane index out of range");
3523       return MatchOperand_ParseFail;
3524     }
3525     Index = Val;
3526     LaneKind = IndexedLane;
3527     return MatchOperand_Success;
3528   }
3529   LaneKind = NoLanes;
3530   return MatchOperand_Success;
3531 }
3532 
3533 // parse a vector register list
3534 ARMAsmParser::OperandMatchResultTy
3535 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3536   VectorLaneTy LaneKind;
3537   unsigned LaneIndex;
3538   SMLoc S = Parser.getTok().getLoc();
3539   // As an extension (to match gas), support a plain D register or Q register
3540   // (without encosing curly braces) as a single or double entry list,
3541   // respectively.
3542   if (Parser.getTok().is(AsmToken::Identifier)) {
3543     SMLoc E = Parser.getTok().getEndLoc();
3544     int Reg = tryParseRegister();
3545     if (Reg == -1)
3546       return MatchOperand_NoMatch;
3547     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3548       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3549       if (Res != MatchOperand_Success)
3550         return Res;
3551       switch (LaneKind) {
3552       case NoLanes:
3553         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3554         break;
3555       case AllLanes:
3556         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3557                                                                 S, E));
3558         break;
3559       case IndexedLane:
3560         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3561                                                                LaneIndex,
3562                                                                false, S, E));
3563         break;
3564       }
3565       return MatchOperand_Success;
3566     }
3567     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3568       Reg = getDRegFromQReg(Reg);
3569       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3570       if (Res != MatchOperand_Success)
3571         return Res;
3572       switch (LaneKind) {
3573       case NoLanes:
3574         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3575                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3576         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3577         break;
3578       case AllLanes:
3579         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3580                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3581         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3582                                                                 S, E));
3583         break;
3584       case IndexedLane:
3585         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3586                                                                LaneIndex,
3587                                                                false, S, E));
3588         break;
3589       }
3590       return MatchOperand_Success;
3591     }
3592     Error(S, "vector register expected");
3593     return MatchOperand_ParseFail;
3594   }
3595 
3596   if (Parser.getTok().isNot(AsmToken::LCurly))
3597     return MatchOperand_NoMatch;
3598 
3599   Parser.Lex(); // Eat '{' token.
3600   SMLoc RegLoc = Parser.getTok().getLoc();
3601 
3602   int Reg = tryParseRegister();
3603   if (Reg == -1) {
3604     Error(RegLoc, "register expected");
3605     return MatchOperand_ParseFail;
3606   }
3607   unsigned Count = 1;
3608   int Spacing = 0;
3609   unsigned FirstReg = Reg;
3610   // The list is of D registers, but we also allow Q regs and just interpret
3611   // them as the two D sub-registers.
3612   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3613     FirstReg = Reg = getDRegFromQReg(Reg);
3614     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3615                  // it's ambiguous with four-register single spaced.
3616     ++Reg;
3617     ++Count;
3618   }
3619 
3620   SMLoc E;
3621   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3622     return MatchOperand_ParseFail;
3623 
3624   while (Parser.getTok().is(AsmToken::Comma) ||
3625          Parser.getTok().is(AsmToken::Minus)) {
3626     if (Parser.getTok().is(AsmToken::Minus)) {
3627       if (!Spacing)
3628         Spacing = 1; // Register range implies a single spaced list.
3629       else if (Spacing == 2) {
3630         Error(Parser.getTok().getLoc(),
3631               "sequential registers in double spaced list");
3632         return MatchOperand_ParseFail;
3633       }
3634       Parser.Lex(); // Eat the minus.
3635       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3636       int EndReg = tryParseRegister();
3637       if (EndReg == -1) {
3638         Error(AfterMinusLoc, "register expected");
3639         return MatchOperand_ParseFail;
3640       }
3641       // Allow Q regs and just interpret them as the two D sub-registers.
3642       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3643         EndReg = getDRegFromQReg(EndReg) + 1;
3644       // If the register is the same as the start reg, there's nothing
3645       // more to do.
3646       if (Reg == EndReg)
3647         continue;
3648       // The register must be in the same register class as the first.
3649       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3650         Error(AfterMinusLoc, "invalid register in register list");
3651         return MatchOperand_ParseFail;
3652       }
3653       // Ranges must go from low to high.
3654       if (Reg > EndReg) {
3655         Error(AfterMinusLoc, "bad range in register list");
3656         return MatchOperand_ParseFail;
3657       }
3658       // Parse the lane specifier if present.
3659       VectorLaneTy NextLaneKind;
3660       unsigned NextLaneIndex;
3661       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3662           MatchOperand_Success)
3663         return MatchOperand_ParseFail;
3664       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3665         Error(AfterMinusLoc, "mismatched lane index in register list");
3666         return MatchOperand_ParseFail;
3667       }
3668 
3669       // Add all the registers in the range to the register list.
3670       Count += EndReg - Reg;
3671       Reg = EndReg;
3672       continue;
3673     }
3674     Parser.Lex(); // Eat the comma.
3675     RegLoc = Parser.getTok().getLoc();
3676     int OldReg = Reg;
3677     Reg = tryParseRegister();
3678     if (Reg == -1) {
3679       Error(RegLoc, "register expected");
3680       return MatchOperand_ParseFail;
3681     }
3682     // vector register lists must be contiguous.
3683     // It's OK to use the enumeration values directly here rather, as the
3684     // VFP register classes have the enum sorted properly.
3685     //
3686     // The list is of D registers, but we also allow Q regs and just interpret
3687     // them as the two D sub-registers.
3688     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3689       if (!Spacing)
3690         Spacing = 1; // Register range implies a single spaced list.
3691       else if (Spacing == 2) {
3692         Error(RegLoc,
3693               "invalid register in double-spaced list (must be 'D' register')");
3694         return MatchOperand_ParseFail;
3695       }
3696       Reg = getDRegFromQReg(Reg);
3697       if (Reg != OldReg + 1) {
3698         Error(RegLoc, "non-contiguous register range");
3699         return MatchOperand_ParseFail;
3700       }
3701       ++Reg;
3702       Count += 2;
3703       // Parse the lane specifier if present.
3704       VectorLaneTy NextLaneKind;
3705       unsigned NextLaneIndex;
3706       SMLoc LaneLoc = Parser.getTok().getLoc();
3707       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3708           MatchOperand_Success)
3709         return MatchOperand_ParseFail;
3710       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3711         Error(LaneLoc, "mismatched lane index in register list");
3712         return MatchOperand_ParseFail;
3713       }
3714       continue;
3715     }
3716     // Normal D register.
3717     // Figure out the register spacing (single or double) of the list if
3718     // we don't know it already.
3719     if (!Spacing)
3720       Spacing = 1 + (Reg == OldReg + 2);
3721 
3722     // Just check that it's contiguous and keep going.
3723     if (Reg != OldReg + Spacing) {
3724       Error(RegLoc, "non-contiguous register range");
3725       return MatchOperand_ParseFail;
3726     }
3727     ++Count;
3728     // Parse the lane specifier if present.
3729     VectorLaneTy NextLaneKind;
3730     unsigned NextLaneIndex;
3731     SMLoc EndLoc = Parser.getTok().getLoc();
3732     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3733       return MatchOperand_ParseFail;
3734     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3735       Error(EndLoc, "mismatched lane index in register list");
3736       return MatchOperand_ParseFail;
3737     }
3738   }
3739 
3740   if (Parser.getTok().isNot(AsmToken::RCurly)) {
3741     Error(Parser.getTok().getLoc(), "'}' expected");
3742     return MatchOperand_ParseFail;
3743   }
3744   E = Parser.getTok().getEndLoc();
3745   Parser.Lex(); // Eat '}' token.
3746 
3747   switch (LaneKind) {
3748   case NoLanes:
3749     // Two-register operands have been converted to the
3750     // composite register classes.
3751     if (Count == 2) {
3752       const MCRegisterClass *RC = (Spacing == 1) ?
3753         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3754         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3755       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3756     }
3757 
3758     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3759                                                     (Spacing == 2), S, E));
3760     break;
3761   case AllLanes:
3762     // Two-register operands have been converted to the
3763     // composite register classes.
3764     if (Count == 2) {
3765       const MCRegisterClass *RC = (Spacing == 1) ?
3766         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3767         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3768       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3769     }
3770     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3771                                                             (Spacing == 2),
3772                                                             S, E));
3773     break;
3774   case IndexedLane:
3775     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3776                                                            LaneIndex,
3777                                                            (Spacing == 2),
3778                                                            S, E));
3779     break;
3780   }
3781   return MatchOperand_Success;
3782 }
3783 
3784 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3785 ARMAsmParser::OperandMatchResultTy
3786 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3787   SMLoc S = Parser.getTok().getLoc();
3788   const AsmToken &Tok = Parser.getTok();
3789   unsigned Opt;
3790 
3791   if (Tok.is(AsmToken::Identifier)) {
3792     StringRef OptStr = Tok.getString();
3793 
3794     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3795       .Case("sy",    ARM_MB::SY)
3796       .Case("st",    ARM_MB::ST)
3797       .Case("ld",    ARM_MB::LD)
3798       .Case("sh",    ARM_MB::ISH)
3799       .Case("ish",   ARM_MB::ISH)
3800       .Case("shst",  ARM_MB::ISHST)
3801       .Case("ishst", ARM_MB::ISHST)
3802       .Case("ishld", ARM_MB::ISHLD)
3803       .Case("nsh",   ARM_MB::NSH)
3804       .Case("un",    ARM_MB::NSH)
3805       .Case("nshst", ARM_MB::NSHST)
3806       .Case("nshld", ARM_MB::NSHLD)
3807       .Case("unst",  ARM_MB::NSHST)
3808       .Case("osh",   ARM_MB::OSH)
3809       .Case("oshst", ARM_MB::OSHST)
3810       .Case("oshld", ARM_MB::OSHLD)
3811       .Default(~0U);
3812 
3813     // ishld, oshld, nshld and ld are only available from ARMv8.
3814     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3815                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3816       Opt = ~0U;
3817 
3818     if (Opt == ~0U)
3819       return MatchOperand_NoMatch;
3820 
3821     Parser.Lex(); // Eat identifier token.
3822   } else if (Tok.is(AsmToken::Hash) ||
3823              Tok.is(AsmToken::Dollar) ||
3824              Tok.is(AsmToken::Integer)) {
3825     if (Parser.getTok().isNot(AsmToken::Integer))
3826       Parser.Lex(); // Eat '#' or '$'.
3827     SMLoc Loc = Parser.getTok().getLoc();
3828 
3829     const MCExpr *MemBarrierID;
3830     if (getParser().parseExpression(MemBarrierID)) {
3831       Error(Loc, "illegal expression");
3832       return MatchOperand_ParseFail;
3833     }
3834 
3835     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3836     if (!CE) {
3837       Error(Loc, "constant expression expected");
3838       return MatchOperand_ParseFail;
3839     }
3840 
3841     int Val = CE->getValue();
3842     if (Val & ~0xf) {
3843       Error(Loc, "immediate value out of range");
3844       return MatchOperand_ParseFail;
3845     }
3846 
3847     Opt = ARM_MB::RESERVED_0 + Val;
3848   } else
3849     return MatchOperand_ParseFail;
3850 
3851   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3852   return MatchOperand_Success;
3853 }
3854 
3855 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3856 ARMAsmParser::OperandMatchResultTy
3857 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3858   SMLoc S = Parser.getTok().getLoc();
3859   const AsmToken &Tok = Parser.getTok();
3860   unsigned Opt;
3861 
3862   if (Tok.is(AsmToken::Identifier)) {
3863     StringRef OptStr = Tok.getString();
3864 
3865     if (OptStr.equals_lower("sy"))
3866       Opt = ARM_ISB::SY;
3867     else
3868       return MatchOperand_NoMatch;
3869 
3870     Parser.Lex(); // Eat identifier token.
3871   } else if (Tok.is(AsmToken::Hash) ||
3872              Tok.is(AsmToken::Dollar) ||
3873              Tok.is(AsmToken::Integer)) {
3874     if (Parser.getTok().isNot(AsmToken::Integer))
3875       Parser.Lex(); // Eat '#' or '$'.
3876     SMLoc Loc = Parser.getTok().getLoc();
3877 
3878     const MCExpr *ISBarrierID;
3879     if (getParser().parseExpression(ISBarrierID)) {
3880       Error(Loc, "illegal expression");
3881       return MatchOperand_ParseFail;
3882     }
3883 
3884     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3885     if (!CE) {
3886       Error(Loc, "constant expression expected");
3887       return MatchOperand_ParseFail;
3888     }
3889 
3890     int Val = CE->getValue();
3891     if (Val & ~0xf) {
3892       Error(Loc, "immediate value out of range");
3893       return MatchOperand_ParseFail;
3894     }
3895 
3896     Opt = ARM_ISB::RESERVED_0 + Val;
3897   } else
3898     return MatchOperand_ParseFail;
3899 
3900   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3901           (ARM_ISB::InstSyncBOpt)Opt, S));
3902   return MatchOperand_Success;
3903 }
3904 
3905 
3906 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3907 ARMAsmParser::OperandMatchResultTy
3908 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3909   SMLoc S = Parser.getTok().getLoc();
3910   const AsmToken &Tok = Parser.getTok();
3911   if (!Tok.is(AsmToken::Identifier))
3912     return MatchOperand_NoMatch;
3913   StringRef IFlagsStr = Tok.getString();
3914 
3915   // An iflags string of "none" is interpreted to mean that none of the AIF
3916   // bits are set.  Not a terribly useful instruction, but a valid encoding.
3917   unsigned IFlags = 0;
3918   if (IFlagsStr != "none") {
3919         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3920       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3921         .Case("a", ARM_PROC::A)
3922         .Case("i", ARM_PROC::I)
3923         .Case("f", ARM_PROC::F)
3924         .Default(~0U);
3925 
3926       // If some specific iflag is already set, it means that some letter is
3927       // present more than once, this is not acceptable.
3928       if (Flag == ~0U || (IFlags & Flag))
3929         return MatchOperand_NoMatch;
3930 
3931       IFlags |= Flag;
3932     }
3933   }
3934 
3935   Parser.Lex(); // Eat identifier token.
3936   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3937   return MatchOperand_Success;
3938 }
3939 
3940 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3941 ARMAsmParser::OperandMatchResultTy
3942 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3943   SMLoc S = Parser.getTok().getLoc();
3944   const AsmToken &Tok = Parser.getTok();
3945   if (!Tok.is(AsmToken::Identifier))
3946     return MatchOperand_NoMatch;
3947   StringRef Mask = Tok.getString();
3948 
3949   if (isMClass()) {
3950     // See ARMv6-M 10.1.1
3951     std::string Name = Mask.lower();
3952     unsigned FlagsVal = StringSwitch<unsigned>(Name)
3953       // Note: in the documentation:
3954       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3955       //  for MSR APSR_nzcvq.
3956       // but we do make it an alias here.  This is so to get the "mask encoding"
3957       // bits correct on MSR APSR writes.
3958       //
3959       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3960       // should really only be allowed when writing a special register.  Note
3961       // they get dropped in the MRS instruction reading a special register as
3962       // the SYSm field is only 8 bits.
3963       .Case("apsr", 0x800)
3964       .Case("apsr_nzcvq", 0x800)
3965       .Case("apsr_g", 0x400)
3966       .Case("apsr_nzcvqg", 0xc00)
3967       .Case("iapsr", 0x801)
3968       .Case("iapsr_nzcvq", 0x801)
3969       .Case("iapsr_g", 0x401)
3970       .Case("iapsr_nzcvqg", 0xc01)
3971       .Case("eapsr", 0x802)
3972       .Case("eapsr_nzcvq", 0x802)
3973       .Case("eapsr_g", 0x402)
3974       .Case("eapsr_nzcvqg", 0xc02)
3975       .Case("xpsr", 0x803)
3976       .Case("xpsr_nzcvq", 0x803)
3977       .Case("xpsr_g", 0x403)
3978       .Case("xpsr_nzcvqg", 0xc03)
3979       .Case("ipsr", 0x805)
3980       .Case("epsr", 0x806)
3981       .Case("iepsr", 0x807)
3982       .Case("msp", 0x808)
3983       .Case("psp", 0x809)
3984       .Case("primask", 0x810)
3985       .Case("basepri", 0x811)
3986       .Case("basepri_max", 0x812)
3987       .Case("faultmask", 0x813)
3988       .Case("control", 0x814)
3989       .Default(~0U);
3990 
3991     if (FlagsVal == ~0U)
3992       return MatchOperand_NoMatch;
3993 
3994     if (!hasThumb2DSP() && (FlagsVal & 0x400))
3995       // The _g and _nzcvqg versions are only valid if the DSP extension is
3996       // available.
3997       return MatchOperand_NoMatch;
3998 
3999     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4000       // basepri, basepri_max and faultmask only valid for V7m.
4001       return MatchOperand_NoMatch;
4002 
4003     Parser.Lex(); // Eat identifier token.
4004     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4005     return MatchOperand_Success;
4006   }
4007 
4008   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4009   size_t Start = 0, Next = Mask.find('_');
4010   StringRef Flags = "";
4011   std::string SpecReg = Mask.slice(Start, Next).lower();
4012   if (Next != StringRef::npos)
4013     Flags = Mask.slice(Next+1, Mask.size());
4014 
4015   // FlagsVal contains the complete mask:
4016   // 3-0: Mask
4017   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4018   unsigned FlagsVal = 0;
4019 
4020   if (SpecReg == "apsr") {
4021     FlagsVal = StringSwitch<unsigned>(Flags)
4022     .Case("nzcvq",  0x8) // same as CPSR_f
4023     .Case("g",      0x4) // same as CPSR_s
4024     .Case("nzcvqg", 0xc) // same as CPSR_fs
4025     .Default(~0U);
4026 
4027     if (FlagsVal == ~0U) {
4028       if (!Flags.empty())
4029         return MatchOperand_NoMatch;
4030       else
4031         FlagsVal = 8; // No flag
4032     }
4033   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4034     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4035     if (Flags == "all" || Flags == "")
4036       Flags = "fc";
4037     for (int i = 0, e = Flags.size(); i != e; ++i) {
4038       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4039       .Case("c", 1)
4040       .Case("x", 2)
4041       .Case("s", 4)
4042       .Case("f", 8)
4043       .Default(~0U);
4044 
4045       // If some specific flag is already set, it means that some letter is
4046       // present more than once, this is not acceptable.
4047       if (FlagsVal == ~0U || (FlagsVal & Flag))
4048         return MatchOperand_NoMatch;
4049       FlagsVal |= Flag;
4050     }
4051   } else // No match for special register.
4052     return MatchOperand_NoMatch;
4053 
4054   // Special register without flags is NOT equivalent to "fc" flags.
4055   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
4056   // two lines would enable gas compatibility at the expense of breaking
4057   // round-tripping.
4058   //
4059   // if (!FlagsVal)
4060   //  FlagsVal = 0x9;
4061 
4062   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4063   if (SpecReg == "spsr")
4064     FlagsVal |= 16;
4065 
4066   Parser.Lex(); // Eat identifier token.
4067   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4068   return MatchOperand_Success;
4069 }
4070 
4071 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4072 /// use in the MRS/MSR instructions added to support virtualization.
4073 ARMAsmParser::OperandMatchResultTy
4074 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4075   SMLoc S = Parser.getTok().getLoc();
4076   const AsmToken &Tok = Parser.getTok();
4077   if (!Tok.is(AsmToken::Identifier))
4078     return MatchOperand_NoMatch;
4079   StringRef RegName = Tok.getString();
4080 
4081   // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4082   // and bit 5 is R.
4083   unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4084                           .Case("r8_usr", 0x00)
4085                           .Case("r9_usr", 0x01)
4086                           .Case("r10_usr", 0x02)
4087                           .Case("r11_usr", 0x03)
4088                           .Case("r12_usr", 0x04)
4089                           .Case("sp_usr", 0x05)
4090                           .Case("lr_usr", 0x06)
4091                           .Case("r8_fiq", 0x08)
4092                           .Case("r9_fiq", 0x09)
4093                           .Case("r10_fiq", 0x0a)
4094                           .Case("r11_fiq", 0x0b)
4095                           .Case("r12_fiq", 0x0c)
4096                           .Case("sp_fiq", 0x0d)
4097                           .Case("lr_fiq", 0x0e)
4098                           .Case("lr_irq", 0x10)
4099                           .Case("sp_irq", 0x11)
4100                           .Case("lr_svc", 0x12)
4101                           .Case("sp_svc", 0x13)
4102                           .Case("lr_abt", 0x14)
4103                           .Case("sp_abt", 0x15)
4104                           .Case("lr_und", 0x16)
4105                           .Case("sp_und", 0x17)
4106                           .Case("lr_mon", 0x1c)
4107                           .Case("sp_mon", 0x1d)
4108                           .Case("elr_hyp", 0x1e)
4109                           .Case("sp_hyp", 0x1f)
4110                           .Case("spsr_fiq", 0x2e)
4111                           .Case("spsr_irq", 0x30)
4112                           .Case("spsr_svc", 0x32)
4113                           .Case("spsr_abt", 0x34)
4114                           .Case("spsr_und", 0x36)
4115                           .Case("spsr_mon", 0x3c)
4116                           .Case("spsr_hyp", 0x3e)
4117                           .Default(~0U);
4118 
4119   if (Encoding == ~0U)
4120     return MatchOperand_NoMatch;
4121 
4122   Parser.Lex(); // Eat identifier token.
4123   Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4124   return MatchOperand_Success;
4125 }
4126 
4127 ARMAsmParser::OperandMatchResultTy
4128 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4129                           int High) {
4130   const AsmToken &Tok = Parser.getTok();
4131   if (Tok.isNot(AsmToken::Identifier)) {
4132     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4133     return MatchOperand_ParseFail;
4134   }
4135   StringRef ShiftName = Tok.getString();
4136   std::string LowerOp = Op.lower();
4137   std::string UpperOp = Op.upper();
4138   if (ShiftName != LowerOp && ShiftName != UpperOp) {
4139     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4140     return MatchOperand_ParseFail;
4141   }
4142   Parser.Lex(); // Eat shift type token.
4143 
4144   // There must be a '#' and a shift amount.
4145   if (Parser.getTok().isNot(AsmToken::Hash) &&
4146       Parser.getTok().isNot(AsmToken::Dollar)) {
4147     Error(Parser.getTok().getLoc(), "'#' expected");
4148     return MatchOperand_ParseFail;
4149   }
4150   Parser.Lex(); // Eat hash token.
4151 
4152   const MCExpr *ShiftAmount;
4153   SMLoc Loc = Parser.getTok().getLoc();
4154   SMLoc EndLoc;
4155   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4156     Error(Loc, "illegal expression");
4157     return MatchOperand_ParseFail;
4158   }
4159   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4160   if (!CE) {
4161     Error(Loc, "constant expression expected");
4162     return MatchOperand_ParseFail;
4163   }
4164   int Val = CE->getValue();
4165   if (Val < Low || Val > High) {
4166     Error(Loc, "immediate value out of range");
4167     return MatchOperand_ParseFail;
4168   }
4169 
4170   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4171 
4172   return MatchOperand_Success;
4173 }
4174 
4175 ARMAsmParser::OperandMatchResultTy
4176 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4177   const AsmToken &Tok = Parser.getTok();
4178   SMLoc S = Tok.getLoc();
4179   if (Tok.isNot(AsmToken::Identifier)) {
4180     Error(S, "'be' or 'le' operand expected");
4181     return MatchOperand_ParseFail;
4182   }
4183   int Val = StringSwitch<int>(Tok.getString().lower())
4184     .Case("be", 1)
4185     .Case("le", 0)
4186     .Default(-1);
4187   Parser.Lex(); // Eat the token.
4188 
4189   if (Val == -1) {
4190     Error(S, "'be' or 'le' operand expected");
4191     return MatchOperand_ParseFail;
4192   }
4193   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4194                                                                   getContext()),
4195                                            S, Tok.getEndLoc()));
4196   return MatchOperand_Success;
4197 }
4198 
4199 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4200 /// instructions. Legal values are:
4201 ///     lsl #n  'n' in [0,31]
4202 ///     asr #n  'n' in [1,32]
4203 ///             n == 32 encoded as n == 0.
4204 ARMAsmParser::OperandMatchResultTy
4205 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4206   const AsmToken &Tok = Parser.getTok();
4207   SMLoc S = Tok.getLoc();
4208   if (Tok.isNot(AsmToken::Identifier)) {
4209     Error(S, "shift operator 'asr' or 'lsl' expected");
4210     return MatchOperand_ParseFail;
4211   }
4212   StringRef ShiftName = Tok.getString();
4213   bool isASR;
4214   if (ShiftName == "lsl" || ShiftName == "LSL")
4215     isASR = false;
4216   else if (ShiftName == "asr" || ShiftName == "ASR")
4217     isASR = true;
4218   else {
4219     Error(S, "shift operator 'asr' or 'lsl' expected");
4220     return MatchOperand_ParseFail;
4221   }
4222   Parser.Lex(); // Eat the operator.
4223 
4224   // A '#' and a shift amount.
4225   if (Parser.getTok().isNot(AsmToken::Hash) &&
4226       Parser.getTok().isNot(AsmToken::Dollar)) {
4227     Error(Parser.getTok().getLoc(), "'#' expected");
4228     return MatchOperand_ParseFail;
4229   }
4230   Parser.Lex(); // Eat hash token.
4231   SMLoc ExLoc = Parser.getTok().getLoc();
4232 
4233   const MCExpr *ShiftAmount;
4234   SMLoc EndLoc;
4235   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4236     Error(ExLoc, "malformed shift expression");
4237     return MatchOperand_ParseFail;
4238   }
4239   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4240   if (!CE) {
4241     Error(ExLoc, "shift amount must be an immediate");
4242     return MatchOperand_ParseFail;
4243   }
4244 
4245   int64_t Val = CE->getValue();
4246   if (isASR) {
4247     // Shift amount must be in [1,32]
4248     if (Val < 1 || Val > 32) {
4249       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4250       return MatchOperand_ParseFail;
4251     }
4252     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4253     if (isThumb() && Val == 32) {
4254       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4255       return MatchOperand_ParseFail;
4256     }
4257     if (Val == 32) Val = 0;
4258   } else {
4259     // Shift amount must be in [1,32]
4260     if (Val < 0 || Val > 31) {
4261       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4262       return MatchOperand_ParseFail;
4263     }
4264   }
4265 
4266   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4267 
4268   return MatchOperand_Success;
4269 }
4270 
4271 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4272 /// of instructions. Legal values are:
4273 ///     ror #n  'n' in {0, 8, 16, 24}
4274 ARMAsmParser::OperandMatchResultTy
4275 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4276   const AsmToken &Tok = Parser.getTok();
4277   SMLoc S = Tok.getLoc();
4278   if (Tok.isNot(AsmToken::Identifier))
4279     return MatchOperand_NoMatch;
4280   StringRef ShiftName = Tok.getString();
4281   if (ShiftName != "ror" && ShiftName != "ROR")
4282     return MatchOperand_NoMatch;
4283   Parser.Lex(); // Eat the operator.
4284 
4285   // A '#' and a rotate amount.
4286   if (Parser.getTok().isNot(AsmToken::Hash) &&
4287       Parser.getTok().isNot(AsmToken::Dollar)) {
4288     Error(Parser.getTok().getLoc(), "'#' expected");
4289     return MatchOperand_ParseFail;
4290   }
4291   Parser.Lex(); // Eat hash token.
4292   SMLoc ExLoc = Parser.getTok().getLoc();
4293 
4294   const MCExpr *ShiftAmount;
4295   SMLoc EndLoc;
4296   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4297     Error(ExLoc, "malformed rotate expression");
4298     return MatchOperand_ParseFail;
4299   }
4300   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4301   if (!CE) {
4302     Error(ExLoc, "rotate amount must be an immediate");
4303     return MatchOperand_ParseFail;
4304   }
4305 
4306   int64_t Val = CE->getValue();
4307   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4308   // normally, zero is represented in asm by omitting the rotate operand
4309   // entirely.
4310   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4311     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4312     return MatchOperand_ParseFail;
4313   }
4314 
4315   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4316 
4317   return MatchOperand_Success;
4318 }
4319 
4320 ARMAsmParser::OperandMatchResultTy
4321 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4322   SMLoc S = Parser.getTok().getLoc();
4323   // The bitfield descriptor is really two operands, the LSB and the width.
4324   if (Parser.getTok().isNot(AsmToken::Hash) &&
4325       Parser.getTok().isNot(AsmToken::Dollar)) {
4326     Error(Parser.getTok().getLoc(), "'#' expected");
4327     return MatchOperand_ParseFail;
4328   }
4329   Parser.Lex(); // Eat hash token.
4330 
4331   const MCExpr *LSBExpr;
4332   SMLoc E = Parser.getTok().getLoc();
4333   if (getParser().parseExpression(LSBExpr)) {
4334     Error(E, "malformed immediate expression");
4335     return MatchOperand_ParseFail;
4336   }
4337   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4338   if (!CE) {
4339     Error(E, "'lsb' operand must be an immediate");
4340     return MatchOperand_ParseFail;
4341   }
4342 
4343   int64_t LSB = CE->getValue();
4344   // The LSB must be in the range [0,31]
4345   if (LSB < 0 || LSB > 31) {
4346     Error(E, "'lsb' operand must be in the range [0,31]");
4347     return MatchOperand_ParseFail;
4348   }
4349   E = Parser.getTok().getLoc();
4350 
4351   // Expect another immediate operand.
4352   if (Parser.getTok().isNot(AsmToken::Comma)) {
4353     Error(Parser.getTok().getLoc(), "too few operands");
4354     return MatchOperand_ParseFail;
4355   }
4356   Parser.Lex(); // Eat hash token.
4357   if (Parser.getTok().isNot(AsmToken::Hash) &&
4358       Parser.getTok().isNot(AsmToken::Dollar)) {
4359     Error(Parser.getTok().getLoc(), "'#' expected");
4360     return MatchOperand_ParseFail;
4361   }
4362   Parser.Lex(); // Eat hash token.
4363 
4364   const MCExpr *WidthExpr;
4365   SMLoc EndLoc;
4366   if (getParser().parseExpression(WidthExpr, EndLoc)) {
4367     Error(E, "malformed immediate expression");
4368     return MatchOperand_ParseFail;
4369   }
4370   CE = dyn_cast<MCConstantExpr>(WidthExpr);
4371   if (!CE) {
4372     Error(E, "'width' operand must be an immediate");
4373     return MatchOperand_ParseFail;
4374   }
4375 
4376   int64_t Width = CE->getValue();
4377   // The LSB must be in the range [1,32-lsb]
4378   if (Width < 1 || Width > 32 - LSB) {
4379     Error(E, "'width' operand must be in the range [1,32-lsb]");
4380     return MatchOperand_ParseFail;
4381   }
4382 
4383   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4384 
4385   return MatchOperand_Success;
4386 }
4387 
4388 ARMAsmParser::OperandMatchResultTy
4389 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4390   // Check for a post-index addressing register operand. Specifically:
4391   // postidx_reg := '+' register {, shift}
4392   //              | '-' register {, shift}
4393   //              | register {, shift}
4394 
4395   // This method must return MatchOperand_NoMatch without consuming any tokens
4396   // in the case where there is no match, as other alternatives take other
4397   // parse methods.
4398   AsmToken Tok = Parser.getTok();
4399   SMLoc S = Tok.getLoc();
4400   bool haveEaten = false;
4401   bool isAdd = true;
4402   if (Tok.is(AsmToken::Plus)) {
4403     Parser.Lex(); // Eat the '+' token.
4404     haveEaten = true;
4405   } else if (Tok.is(AsmToken::Minus)) {
4406     Parser.Lex(); // Eat the '-' token.
4407     isAdd = false;
4408     haveEaten = true;
4409   }
4410 
4411   SMLoc E = Parser.getTok().getEndLoc();
4412   int Reg = tryParseRegister();
4413   if (Reg == -1) {
4414     if (!haveEaten)
4415       return MatchOperand_NoMatch;
4416     Error(Parser.getTok().getLoc(), "register expected");
4417     return MatchOperand_ParseFail;
4418   }
4419 
4420   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4421   unsigned ShiftImm = 0;
4422   if (Parser.getTok().is(AsmToken::Comma)) {
4423     Parser.Lex(); // Eat the ','.
4424     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4425       return MatchOperand_ParseFail;
4426 
4427     // FIXME: Only approximates end...may include intervening whitespace.
4428     E = Parser.getTok().getLoc();
4429   }
4430 
4431   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4432                                                   ShiftImm, S, E));
4433 
4434   return MatchOperand_Success;
4435 }
4436 
4437 ARMAsmParser::OperandMatchResultTy
4438 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4439   // Check for a post-index addressing register operand. Specifically:
4440   // am3offset := '+' register
4441   //              | '-' register
4442   //              | register
4443   //              | # imm
4444   //              | # + imm
4445   //              | # - imm
4446 
4447   // This method must return MatchOperand_NoMatch without consuming any tokens
4448   // in the case where there is no match, as other alternatives take other
4449   // parse methods.
4450   AsmToken Tok = Parser.getTok();
4451   SMLoc S = Tok.getLoc();
4452 
4453   // Do immediates first, as we always parse those if we have a '#'.
4454   if (Parser.getTok().is(AsmToken::Hash) ||
4455       Parser.getTok().is(AsmToken::Dollar)) {
4456     Parser.Lex(); // Eat '#' or '$'.
4457     // Explicitly look for a '-', as we need to encode negative zero
4458     // differently.
4459     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4460     const MCExpr *Offset;
4461     SMLoc E;
4462     if (getParser().parseExpression(Offset, E))
4463       return MatchOperand_ParseFail;
4464     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4465     if (!CE) {
4466       Error(S, "constant expression expected");
4467       return MatchOperand_ParseFail;
4468     }
4469     // Negative zero is encoded as the flag value INT32_MIN.
4470     int32_t Val = CE->getValue();
4471     if (isNegative && Val == 0)
4472       Val = INT32_MIN;
4473 
4474     Operands.push_back(
4475       ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4476 
4477     return MatchOperand_Success;
4478   }
4479 
4480 
4481   bool haveEaten = false;
4482   bool isAdd = true;
4483   if (Tok.is(AsmToken::Plus)) {
4484     Parser.Lex(); // Eat the '+' token.
4485     haveEaten = true;
4486   } else if (Tok.is(AsmToken::Minus)) {
4487     Parser.Lex(); // Eat the '-' token.
4488     isAdd = false;
4489     haveEaten = true;
4490   }
4491 
4492   Tok = Parser.getTok();
4493   int Reg = tryParseRegister();
4494   if (Reg == -1) {
4495     if (!haveEaten)
4496       return MatchOperand_NoMatch;
4497     Error(Tok.getLoc(), "register expected");
4498     return MatchOperand_ParseFail;
4499   }
4500 
4501   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4502                                                   0, S, Tok.getEndLoc()));
4503 
4504   return MatchOperand_Success;
4505 }
4506 
4507 /// Convert parsed operands to MCInst.  Needed here because this instruction
4508 /// only has two register operands, but multiplication is commutative so
4509 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4510 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4511                                     const OperandVector &Operands) {
4512   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4513   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4514   // If we have a three-operand form, make sure to set Rn to be the operand
4515   // that isn't the same as Rd.
4516   unsigned RegOp = 4;
4517   if (Operands.size() == 6 &&
4518       ((ARMOperand &)*Operands[4]).getReg() ==
4519           ((ARMOperand &)*Operands[3]).getReg())
4520     RegOp = 5;
4521   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4522   Inst.addOperand(Inst.getOperand(0));
4523   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4524 }
4525 
4526 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4527                                     const OperandVector &Operands) {
4528   int CondOp = -1, ImmOp = -1;
4529   switch(Inst.getOpcode()) {
4530     case ARM::tB:
4531     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4532 
4533     case ARM::t2B:
4534     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4535 
4536     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4537   }
4538   // first decide whether or not the branch should be conditional
4539   // by looking at it's location relative to an IT block
4540   if(inITBlock()) {
4541     // inside an IT block we cannot have any conditional branches. any
4542     // such instructions needs to be converted to unconditional form
4543     switch(Inst.getOpcode()) {
4544       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4545       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4546     }
4547   } else {
4548     // outside IT blocks we can only have unconditional branches with AL
4549     // condition code or conditional branches with non-AL condition code
4550     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4551     switch(Inst.getOpcode()) {
4552       case ARM::tB:
4553       case ARM::tBcc:
4554         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4555         break;
4556       case ARM::t2B:
4557       case ARM::t2Bcc:
4558         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4559         break;
4560     }
4561   }
4562 
4563   // now decide on encoding size based on branch target range
4564   switch(Inst.getOpcode()) {
4565     // classify tB as either t2B or t1B based on range of immediate operand
4566     case ARM::tB: {
4567       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4568       if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4569         Inst.setOpcode(ARM::t2B);
4570       break;
4571     }
4572     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4573     case ARM::tBcc: {
4574       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4575       if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4576         Inst.setOpcode(ARM::t2Bcc);
4577       break;
4578     }
4579   }
4580   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4581   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4582 }
4583 
4584 /// Parse an ARM memory expression, return false if successful else return true
4585 /// or an error.  The first token must be a '[' when called.
4586 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4587   SMLoc S, E;
4588   assert(Parser.getTok().is(AsmToken::LBrac) &&
4589          "Token is not a Left Bracket");
4590   S = Parser.getTok().getLoc();
4591   Parser.Lex(); // Eat left bracket token.
4592 
4593   const AsmToken &BaseRegTok = Parser.getTok();
4594   int BaseRegNum = tryParseRegister();
4595   if (BaseRegNum == -1)
4596     return Error(BaseRegTok.getLoc(), "register expected");
4597 
4598   // The next token must either be a comma, a colon or a closing bracket.
4599   const AsmToken &Tok = Parser.getTok();
4600   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4601       !Tok.is(AsmToken::RBrac))
4602     return Error(Tok.getLoc(), "malformed memory operand");
4603 
4604   if (Tok.is(AsmToken::RBrac)) {
4605     E = Tok.getEndLoc();
4606     Parser.Lex(); // Eat right bracket token.
4607 
4608     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4609                                              ARM_AM::no_shift, 0, 0, false,
4610                                              S, E));
4611 
4612     // If there's a pre-indexing writeback marker, '!', just add it as a token
4613     // operand. It's rather odd, but syntactically valid.
4614     if (Parser.getTok().is(AsmToken::Exclaim)) {
4615       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4616       Parser.Lex(); // Eat the '!'.
4617     }
4618 
4619     return false;
4620   }
4621 
4622   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4623          "Lost colon or comma in memory operand?!");
4624   if (Tok.is(AsmToken::Comma)) {
4625     Parser.Lex(); // Eat the comma.
4626   }
4627 
4628   // If we have a ':', it's an alignment specifier.
4629   if (Parser.getTok().is(AsmToken::Colon)) {
4630     Parser.Lex(); // Eat the ':'.
4631     E = Parser.getTok().getLoc();
4632     SMLoc AlignmentLoc = Tok.getLoc();
4633 
4634     const MCExpr *Expr;
4635     if (getParser().parseExpression(Expr))
4636      return true;
4637 
4638     // The expression has to be a constant. Memory references with relocations
4639     // don't come through here, as they use the <label> forms of the relevant
4640     // instructions.
4641     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4642     if (!CE)
4643       return Error (E, "constant expression expected");
4644 
4645     unsigned Align = 0;
4646     switch (CE->getValue()) {
4647     default:
4648       return Error(E,
4649                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4650     case 16:  Align = 2; break;
4651     case 32:  Align = 4; break;
4652     case 64:  Align = 8; break;
4653     case 128: Align = 16; break;
4654     case 256: Align = 32; break;
4655     }
4656 
4657     // Now we should have the closing ']'
4658     if (Parser.getTok().isNot(AsmToken::RBrac))
4659       return Error(Parser.getTok().getLoc(), "']' expected");
4660     E = Parser.getTok().getEndLoc();
4661     Parser.Lex(); // Eat right bracket token.
4662 
4663     // Don't worry about range checking the value here. That's handled by
4664     // the is*() predicates.
4665     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4666                                              ARM_AM::no_shift, 0, Align,
4667                                              false, S, E, AlignmentLoc));
4668 
4669     // If there's a pre-indexing writeback marker, '!', just add it as a token
4670     // operand.
4671     if (Parser.getTok().is(AsmToken::Exclaim)) {
4672       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4673       Parser.Lex(); // Eat the '!'.
4674     }
4675 
4676     return false;
4677   }
4678 
4679   // If we have a '#', it's an immediate offset, else assume it's a register
4680   // offset. Be friendly and also accept a plain integer (without a leading
4681   // hash) for gas compatibility.
4682   if (Parser.getTok().is(AsmToken::Hash) ||
4683       Parser.getTok().is(AsmToken::Dollar) ||
4684       Parser.getTok().is(AsmToken::Integer)) {
4685     if (Parser.getTok().isNot(AsmToken::Integer))
4686       Parser.Lex(); // Eat '#' or '$'.
4687     E = Parser.getTok().getLoc();
4688 
4689     bool isNegative = getParser().getTok().is(AsmToken::Minus);
4690     const MCExpr *Offset;
4691     if (getParser().parseExpression(Offset))
4692      return true;
4693 
4694     // The expression has to be a constant. Memory references with relocations
4695     // don't come through here, as they use the <label> forms of the relevant
4696     // instructions.
4697     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4698     if (!CE)
4699       return Error (E, "constant expression expected");
4700 
4701     // If the constant was #-0, represent it as INT32_MIN.
4702     int32_t Val = CE->getValue();
4703     if (isNegative && Val == 0)
4704       CE = MCConstantExpr::Create(INT32_MIN, getContext());
4705 
4706     // Now we should have the closing ']'
4707     if (Parser.getTok().isNot(AsmToken::RBrac))
4708       return Error(Parser.getTok().getLoc(), "']' expected");
4709     E = Parser.getTok().getEndLoc();
4710     Parser.Lex(); // Eat right bracket token.
4711 
4712     // Don't worry about range checking the value here. That's handled by
4713     // the is*() predicates.
4714     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4715                                              ARM_AM::no_shift, 0, 0,
4716                                              false, S, E));
4717 
4718     // If there's a pre-indexing writeback marker, '!', just add it as a token
4719     // operand.
4720     if (Parser.getTok().is(AsmToken::Exclaim)) {
4721       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4722       Parser.Lex(); // Eat the '!'.
4723     }
4724 
4725     return false;
4726   }
4727 
4728   // The register offset is optionally preceded by a '+' or '-'
4729   bool isNegative = false;
4730   if (Parser.getTok().is(AsmToken::Minus)) {
4731     isNegative = true;
4732     Parser.Lex(); // Eat the '-'.
4733   } else if (Parser.getTok().is(AsmToken::Plus)) {
4734     // Nothing to do.
4735     Parser.Lex(); // Eat the '+'.
4736   }
4737 
4738   E = Parser.getTok().getLoc();
4739   int OffsetRegNum = tryParseRegister();
4740   if (OffsetRegNum == -1)
4741     return Error(E, "register expected");
4742 
4743   // If there's a shift operator, handle it.
4744   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4745   unsigned ShiftImm = 0;
4746   if (Parser.getTok().is(AsmToken::Comma)) {
4747     Parser.Lex(); // Eat the ','.
4748     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4749       return true;
4750   }
4751 
4752   // Now we should have the closing ']'
4753   if (Parser.getTok().isNot(AsmToken::RBrac))
4754     return Error(Parser.getTok().getLoc(), "']' expected");
4755   E = Parser.getTok().getEndLoc();
4756   Parser.Lex(); // Eat right bracket token.
4757 
4758   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4759                                            ShiftType, ShiftImm, 0, isNegative,
4760                                            S, E));
4761 
4762   // If there's a pre-indexing writeback marker, '!', just add it as a token
4763   // operand.
4764   if (Parser.getTok().is(AsmToken::Exclaim)) {
4765     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4766     Parser.Lex(); // Eat the '!'.
4767   }
4768 
4769   return false;
4770 }
4771 
4772 /// parseMemRegOffsetShift - one of these two:
4773 ///   ( lsl | lsr | asr | ror ) , # shift_amount
4774 ///   rrx
4775 /// return true if it parses a shift otherwise it returns false.
4776 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4777                                           unsigned &Amount) {
4778   SMLoc Loc = Parser.getTok().getLoc();
4779   const AsmToken &Tok = Parser.getTok();
4780   if (Tok.isNot(AsmToken::Identifier))
4781     return true;
4782   StringRef ShiftName = Tok.getString();
4783   if (ShiftName == "lsl" || ShiftName == "LSL" ||
4784       ShiftName == "asl" || ShiftName == "ASL")
4785     St = ARM_AM::lsl;
4786   else if (ShiftName == "lsr" || ShiftName == "LSR")
4787     St = ARM_AM::lsr;
4788   else if (ShiftName == "asr" || ShiftName == "ASR")
4789     St = ARM_AM::asr;
4790   else if (ShiftName == "ror" || ShiftName == "ROR")
4791     St = ARM_AM::ror;
4792   else if (ShiftName == "rrx" || ShiftName == "RRX")
4793     St = ARM_AM::rrx;
4794   else
4795     return Error(Loc, "illegal shift operator");
4796   Parser.Lex(); // Eat shift type token.
4797 
4798   // rrx stands alone.
4799   Amount = 0;
4800   if (St != ARM_AM::rrx) {
4801     Loc = Parser.getTok().getLoc();
4802     // A '#' and a shift amount.
4803     const AsmToken &HashTok = Parser.getTok();
4804     if (HashTok.isNot(AsmToken::Hash) &&
4805         HashTok.isNot(AsmToken::Dollar))
4806       return Error(HashTok.getLoc(), "'#' expected");
4807     Parser.Lex(); // Eat hash token.
4808 
4809     const MCExpr *Expr;
4810     if (getParser().parseExpression(Expr))
4811       return true;
4812     // Range check the immediate.
4813     // lsl, ror: 0 <= imm <= 31
4814     // lsr, asr: 0 <= imm <= 32
4815     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4816     if (!CE)
4817       return Error(Loc, "shift amount must be an immediate");
4818     int64_t Imm = CE->getValue();
4819     if (Imm < 0 ||
4820         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4821         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4822       return Error(Loc, "immediate shift value out of range");
4823     // If <ShiftTy> #0, turn it into a no_shift.
4824     if (Imm == 0)
4825       St = ARM_AM::lsl;
4826     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4827     if (Imm == 32)
4828       Imm = 0;
4829     Amount = Imm;
4830   }
4831 
4832   return false;
4833 }
4834 
4835 /// parseFPImm - A floating point immediate expression operand.
4836 ARMAsmParser::OperandMatchResultTy
4837 ARMAsmParser::parseFPImm(OperandVector &Operands) {
4838   // Anything that can accept a floating point constant as an operand
4839   // needs to go through here, as the regular parseExpression is
4840   // integer only.
4841   //
4842   // This routine still creates a generic Immediate operand, containing
4843   // a bitcast of the 64-bit floating point value. The various operands
4844   // that accept floats can check whether the value is valid for them
4845   // via the standard is*() predicates.
4846 
4847   SMLoc S = Parser.getTok().getLoc();
4848 
4849   if (Parser.getTok().isNot(AsmToken::Hash) &&
4850       Parser.getTok().isNot(AsmToken::Dollar))
4851     return MatchOperand_NoMatch;
4852 
4853   // Disambiguate the VMOV forms that can accept an FP immediate.
4854   // vmov.f32 <sreg>, #imm
4855   // vmov.f64 <dreg>, #imm
4856   // vmov.f32 <dreg>, #imm  @ vector f32x2
4857   // vmov.f32 <qreg>, #imm  @ vector f32x4
4858   //
4859   // There are also the NEON VMOV instructions which expect an
4860   // integer constant. Make sure we don't try to parse an FPImm
4861   // for these:
4862   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4863   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
4864   bool isVmovf = TyOp.isToken() &&
4865                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
4866   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
4867   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
4868                                          Mnemonic.getToken() == "fconsts");
4869   if (!(isVmovf || isFconst))
4870     return MatchOperand_NoMatch;
4871 
4872   Parser.Lex(); // Eat '#' or '$'.
4873 
4874   // Handle negation, as that still comes through as a separate token.
4875   bool isNegative = false;
4876   if (Parser.getTok().is(AsmToken::Minus)) {
4877     isNegative = true;
4878     Parser.Lex();
4879   }
4880   const AsmToken &Tok = Parser.getTok();
4881   SMLoc Loc = Tok.getLoc();
4882   if (Tok.is(AsmToken::Real) && isVmovf) {
4883     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4884     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4885     // If we had a '-' in front, toggle the sign bit.
4886     IntVal ^= (uint64_t)isNegative << 31;
4887     Parser.Lex(); // Eat the token.
4888     Operands.push_back(ARMOperand::CreateImm(
4889           MCConstantExpr::Create(IntVal, getContext()),
4890           S, Parser.getTok().getLoc()));
4891     return MatchOperand_Success;
4892   }
4893   // Also handle plain integers. Instructions which allow floating point
4894   // immediates also allow a raw encoded 8-bit value.
4895   if (Tok.is(AsmToken::Integer) && isFconst) {
4896     int64_t Val = Tok.getIntVal();
4897     Parser.Lex(); // Eat the token.
4898     if (Val > 255 || Val < 0) {
4899       Error(Loc, "encoded floating point value out of range");
4900       return MatchOperand_ParseFail;
4901     }
4902     float RealVal = ARM_AM::getFPImmFloat(Val);
4903     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4904 
4905     Operands.push_back(ARMOperand::CreateImm(
4906         MCConstantExpr::Create(Val, getContext()), S,
4907         Parser.getTok().getLoc()));
4908     return MatchOperand_Success;
4909   }
4910 
4911   Error(Loc, "invalid floating point immediate");
4912   return MatchOperand_ParseFail;
4913 }
4914 
4915 /// Parse a arm instruction operand.  For now this parses the operand regardless
4916 /// of the mnemonic.
4917 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
4918   SMLoc S, E;
4919 
4920   // Check if the current operand has a custom associated parser, if so, try to
4921   // custom parse the operand, or fallback to the general approach.
4922   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4923   if (ResTy == MatchOperand_Success)
4924     return false;
4925   // If there wasn't a custom match, try the generic matcher below. Otherwise,
4926   // there was a match, but an error occurred, in which case, just return that
4927   // the operand parsing failed.
4928   if (ResTy == MatchOperand_ParseFail)
4929     return true;
4930 
4931   switch (getLexer().getKind()) {
4932   default:
4933     Error(Parser.getTok().getLoc(), "unexpected token in operand");
4934     return true;
4935   case AsmToken::Identifier: {
4936     // If we've seen a branch mnemonic, the next operand must be a label.  This
4937     // is true even if the label is a register name.  So "br r1" means branch to
4938     // label "r1".
4939     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4940     if (!ExpectLabel) {
4941       if (!tryParseRegisterWithWriteBack(Operands))
4942         return false;
4943       int Res = tryParseShiftRegister(Operands);
4944       if (Res == 0) // success
4945         return false;
4946       else if (Res == -1) // irrecoverable error
4947         return true;
4948       // If this is VMRS, check for the apsr_nzcv operand.
4949       if (Mnemonic == "vmrs" &&
4950           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4951         S = Parser.getTok().getLoc();
4952         Parser.Lex();
4953         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4954         return false;
4955       }
4956     }
4957 
4958     // Fall though for the Identifier case that is not a register or a
4959     // special name.
4960   }
4961   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4962   case AsmToken::Integer: // things like 1f and 2b as a branch targets
4963   case AsmToken::String:  // quoted label names.
4964   case AsmToken::Dot: {   // . as a branch target
4965     // This was not a register so parse other operands that start with an
4966     // identifier (like labels) as expressions and create them as immediates.
4967     const MCExpr *IdVal;
4968     S = Parser.getTok().getLoc();
4969     if (getParser().parseExpression(IdVal))
4970       return true;
4971     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4972     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4973     return false;
4974   }
4975   case AsmToken::LBrac:
4976     return parseMemory(Operands);
4977   case AsmToken::LCurly:
4978     return parseRegisterList(Operands);
4979   case AsmToken::Dollar:
4980   case AsmToken::Hash: {
4981     // #42 -> immediate.
4982     S = Parser.getTok().getLoc();
4983     Parser.Lex();
4984 
4985     if (Parser.getTok().isNot(AsmToken::Colon)) {
4986       bool isNegative = Parser.getTok().is(AsmToken::Minus);
4987       const MCExpr *ImmVal;
4988       if (getParser().parseExpression(ImmVal))
4989         return true;
4990       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4991       if (CE) {
4992         int32_t Val = CE->getValue();
4993         if (isNegative && Val == 0)
4994           ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4995       }
4996       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4997       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4998 
4999       // There can be a trailing '!' on operands that we want as a separate
5000       // '!' Token operand. Handle that here. For example, the compatibility
5001       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5002       if (Parser.getTok().is(AsmToken::Exclaim)) {
5003         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5004                                                    Parser.getTok().getLoc()));
5005         Parser.Lex(); // Eat exclaim token
5006       }
5007       return false;
5008     }
5009     // w/ a ':' after the '#', it's just like a plain ':'.
5010     // FALLTHROUGH
5011   }
5012   case AsmToken::Colon: {
5013     // ":lower16:" and ":upper16:" expression prefixes
5014     // FIXME: Check it's an expression prefix,
5015     // e.g. (FOO - :lower16:BAR) isn't legal.
5016     ARMMCExpr::VariantKind RefKind;
5017     if (parsePrefix(RefKind))
5018       return true;
5019 
5020     const MCExpr *SubExprVal;
5021     if (getParser().parseExpression(SubExprVal))
5022       return true;
5023 
5024     const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
5025                                               getContext());
5026     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5027     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5028     return false;
5029   }
5030   case AsmToken::Equal: {
5031     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5032       return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5033 
5034     Parser.Lex(); // Eat '='
5035     const MCExpr *SubExprVal;
5036     if (getParser().parseExpression(SubExprVal))
5037       return true;
5038     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5039 
5040     const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5041     Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5042     return false;
5043   }
5044   }
5045 }
5046 
5047 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5048 //  :lower16: and :upper16:.
5049 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5050   RefKind = ARMMCExpr::VK_ARM_None;
5051 
5052   // consume an optional '#' (GNU compatibility)
5053   if (getLexer().is(AsmToken::Hash))
5054     Parser.Lex();
5055 
5056   // :lower16: and :upper16: modifiers
5057   assert(getLexer().is(AsmToken::Colon) && "expected a :");
5058   Parser.Lex(); // Eat ':'
5059 
5060   if (getLexer().isNot(AsmToken::Identifier)) {
5061     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5062     return true;
5063   }
5064 
5065   StringRef IDVal = Parser.getTok().getIdentifier();
5066   if (IDVal == "lower16") {
5067     RefKind = ARMMCExpr::VK_ARM_LO16;
5068   } else if (IDVal == "upper16") {
5069     RefKind = ARMMCExpr::VK_ARM_HI16;
5070   } else {
5071     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5072     return true;
5073   }
5074   Parser.Lex();
5075 
5076   if (getLexer().isNot(AsmToken::Colon)) {
5077     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5078     return true;
5079   }
5080   Parser.Lex(); // Eat the last ':'
5081   return false;
5082 }
5083 
5084 /// \brief Given a mnemonic, split out possible predication code and carry
5085 /// setting letters to form a canonical mnemonic and flags.
5086 //
5087 // FIXME: Would be nice to autogen this.
5088 // FIXME: This is a bit of a maze of special cases.
5089 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5090                                       unsigned &PredicationCode,
5091                                       bool &CarrySetting,
5092                                       unsigned &ProcessorIMod,
5093                                       StringRef &ITMask) {
5094   PredicationCode = ARMCC::AL;
5095   CarrySetting = false;
5096   ProcessorIMod = 0;
5097 
5098   // Ignore some mnemonics we know aren't predicated forms.
5099   //
5100   // FIXME: Would be nice to autogen this.
5101   if ((Mnemonic == "movs" && isThumb()) ||
5102       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
5103       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
5104       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
5105       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
5106       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
5107       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
5108       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
5109       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5110       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5111       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
5112       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5113       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
5114     return Mnemonic;
5115 
5116   // First, split out any predication code. Ignore mnemonics we know aren't
5117   // predicated but do have a carry-set and so weren't caught above.
5118   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5119       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5120       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5121       Mnemonic != "sbcs" && Mnemonic != "rscs") {
5122     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5123       .Case("eq", ARMCC::EQ)
5124       .Case("ne", ARMCC::NE)
5125       .Case("hs", ARMCC::HS)
5126       .Case("cs", ARMCC::HS)
5127       .Case("lo", ARMCC::LO)
5128       .Case("cc", ARMCC::LO)
5129       .Case("mi", ARMCC::MI)
5130       .Case("pl", ARMCC::PL)
5131       .Case("vs", ARMCC::VS)
5132       .Case("vc", ARMCC::VC)
5133       .Case("hi", ARMCC::HI)
5134       .Case("ls", ARMCC::LS)
5135       .Case("ge", ARMCC::GE)
5136       .Case("lt", ARMCC::LT)
5137       .Case("gt", ARMCC::GT)
5138       .Case("le", ARMCC::LE)
5139       .Case("al", ARMCC::AL)
5140       .Default(~0U);
5141     if (CC != ~0U) {
5142       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5143       PredicationCode = CC;
5144     }
5145   }
5146 
5147   // Next, determine if we have a carry setting bit. We explicitly ignore all
5148   // the instructions we know end in 's'.
5149   if (Mnemonic.endswith("s") &&
5150       !(Mnemonic == "cps" || Mnemonic == "mls" ||
5151         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5152         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5153         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5154         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5155         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5156         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5157         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5158         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5159         (Mnemonic == "movs" && isThumb()))) {
5160     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5161     CarrySetting = true;
5162   }
5163 
5164   // The "cps" instruction can have a interrupt mode operand which is glued into
5165   // the mnemonic. Check if this is the case, split it and parse the imod op
5166   if (Mnemonic.startswith("cps")) {
5167     // Split out any imod code.
5168     unsigned IMod =
5169       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5170       .Case("ie", ARM_PROC::IE)
5171       .Case("id", ARM_PROC::ID)
5172       .Default(~0U);
5173     if (IMod != ~0U) {
5174       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5175       ProcessorIMod = IMod;
5176     }
5177   }
5178 
5179   // The "it" instruction has the condition mask on the end of the mnemonic.
5180   if (Mnemonic.startswith("it")) {
5181     ITMask = Mnemonic.slice(2, Mnemonic.size());
5182     Mnemonic = Mnemonic.slice(0, 2);
5183   }
5184 
5185   return Mnemonic;
5186 }
5187 
5188 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5189 /// inclusion of carry set or predication code operands.
5190 //
5191 // FIXME: It would be nice to autogen this.
5192 void ARMAsmParser::
5193 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5194                      bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5195   if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5196       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5197       Mnemonic == "add" || Mnemonic == "adc" ||
5198       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5199       Mnemonic == "orr" || Mnemonic == "mvn" ||
5200       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5201       Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5202       Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5203       (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5204                       Mnemonic == "mla" || Mnemonic == "smlal" ||
5205                       Mnemonic == "umlal" || Mnemonic == "umull"))) {
5206     CanAcceptCarrySet = true;
5207   } else
5208     CanAcceptCarrySet = false;
5209 
5210   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5211       Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
5212       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5213       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5214       Mnemonic.startswith("vsel") ||
5215       Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5216       Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5217       Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5218       Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5219       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5220       (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5221     // These mnemonics are never predicable
5222     CanAcceptPredicationCode = false;
5223   } else if (!isThumb()) {
5224     // Some instructions are only predicable in Thumb mode
5225     CanAcceptPredicationCode
5226       = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5227         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5228         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5229         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5230         Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5231         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5232         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5233   } else if (isThumbOne()) {
5234     if (hasV6MOps())
5235       CanAcceptPredicationCode = Mnemonic != "movs";
5236     else
5237       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5238   } else
5239     CanAcceptPredicationCode = true;
5240 }
5241 
5242 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5243                                           OperandVector &Operands) {
5244   // FIXME: This is all horribly hacky. We really need a better way to deal
5245   // with optional operands like this in the matcher table.
5246 
5247   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5248   // another does not. Specifically, the MOVW instruction does not. So we
5249   // special case it here and remove the defaulted (non-setting) cc_out
5250   // operand if that's the instruction we're trying to match.
5251   //
5252   // We do this as post-processing of the explicit operands rather than just
5253   // conditionally adding the cc_out in the first place because we need
5254   // to check the type of the parsed immediate operand.
5255   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5256       !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() &&
5257       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5258       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5259     return true;
5260 
5261   // Register-register 'add' for thumb does not have a cc_out operand
5262   // when there are only two register operands.
5263   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5264       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5265       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5266       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5267     return true;
5268   // Register-register 'add' for thumb does not have a cc_out operand
5269   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5270   // have to check the immediate range here since Thumb2 has a variant
5271   // that can handle a different range and has a cc_out operand.
5272   if (((isThumb() && Mnemonic == "add") ||
5273        (isThumbTwo() && Mnemonic == "sub")) &&
5274       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5275       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5276       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5277       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5278       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5279        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5280     return true;
5281   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5282   // imm0_4095 variant. That's the least-preferred variant when
5283   // selecting via the generic "add" mnemonic, so to know that we
5284   // should remove the cc_out operand, we have to explicitly check that
5285   // it's not one of the other variants. Ugh.
5286   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5287       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5288       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5289       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5290     // Nest conditions rather than one big 'if' statement for readability.
5291     //
5292     // If both registers are low, we're in an IT block, and the immediate is
5293     // in range, we should use encoding T1 instead, which has a cc_out.
5294     if (inITBlock() &&
5295         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5296         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5297         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5298       return false;
5299     // Check against T3. If the second register is the PC, this is an
5300     // alternate form of ADR, which uses encoding T4, so check for that too.
5301     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5302         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5303       return false;
5304 
5305     // Otherwise, we use encoding T4, which does not have a cc_out
5306     // operand.
5307     return true;
5308   }
5309 
5310   // The thumb2 multiply instruction doesn't have a CCOut register, so
5311   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5312   // use the 16-bit encoding or not.
5313   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5314       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5315       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5316       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5317       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5318       // If the registers aren't low regs, the destination reg isn't the
5319       // same as one of the source regs, or the cc_out operand is zero
5320       // outside of an IT block, we have to use the 32-bit encoding, so
5321       // remove the cc_out operand.
5322       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5323        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5324        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5325        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5326                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5327                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5328                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
5329     return true;
5330 
5331   // Also check the 'mul' syntax variant that doesn't specify an explicit
5332   // destination register.
5333   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5334       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5335       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5336       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5337       // If the registers aren't low regs  or the cc_out operand is zero
5338       // outside of an IT block, we have to use the 32-bit encoding, so
5339       // remove the cc_out operand.
5340       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5341        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5342        !inITBlock()))
5343     return true;
5344 
5345 
5346 
5347   // Register-register 'add/sub' for thumb does not have a cc_out operand
5348   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5349   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5350   // right, this will result in better diagnostics (which operand is off)
5351   // anyway.
5352   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5353       (Operands.size() == 5 || Operands.size() == 6) &&
5354       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5355       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5356       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5357       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5358        (Operands.size() == 6 &&
5359         static_cast<ARMOperand &>(*Operands[5]).isImm())))
5360     return true;
5361 
5362   return false;
5363 }
5364 
5365 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5366                                               OperandVector &Operands) {
5367   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5368   unsigned RegIdx = 3;
5369   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5370       static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5371     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5372         static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5373       RegIdx = 4;
5374 
5375     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5376         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5377              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5378          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5379              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5380       return true;
5381   }
5382   return false;
5383 }
5384 
5385 static bool isDataTypeToken(StringRef Tok) {
5386   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5387     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5388     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5389     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5390     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5391     Tok == ".f" || Tok == ".d";
5392 }
5393 
5394 // FIXME: This bit should probably be handled via an explicit match class
5395 // in the .td files that matches the suffix instead of having it be
5396 // a literal string token the way it is now.
5397 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5398   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5399 }
5400 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5401                                  unsigned VariantID);
5402 
5403 static bool RequiresVFPRegListValidation(StringRef Inst,
5404                                          bool &AcceptSinglePrecisionOnly,
5405                                          bool &AcceptDoublePrecisionOnly) {
5406   if (Inst.size() < 7)
5407     return false;
5408 
5409   if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5410     StringRef AddressingMode = Inst.substr(4, 2);
5411     if (AddressingMode == "ia" || AddressingMode == "db" ||
5412         AddressingMode == "ea" || AddressingMode == "fd") {
5413       AcceptSinglePrecisionOnly = Inst[6] == 's';
5414       AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5415       return true;
5416     }
5417   }
5418 
5419   return false;
5420 }
5421 
5422 /// Parse an arm instruction mnemonic followed by its operands.
5423 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5424                                     SMLoc NameLoc, OperandVector &Operands) {
5425   // FIXME: Can this be done via tablegen in some fashion?
5426   bool RequireVFPRegisterListCheck;
5427   bool AcceptSinglePrecisionOnly;
5428   bool AcceptDoublePrecisionOnly;
5429   RequireVFPRegisterListCheck =
5430     RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5431                                  AcceptDoublePrecisionOnly);
5432 
5433   // Apply mnemonic aliases before doing anything else, as the destination
5434   // mnemonic may include suffices and we want to handle them normally.
5435   // The generic tblgen'erated code does this later, at the start of
5436   // MatchInstructionImpl(), but that's too late for aliases that include
5437   // any sort of suffix.
5438   uint64_t AvailableFeatures = getAvailableFeatures();
5439   unsigned AssemblerDialect = getParser().getAssemblerDialect();
5440   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5441 
5442   // First check for the ARM-specific .req directive.
5443   if (Parser.getTok().is(AsmToken::Identifier) &&
5444       Parser.getTok().getIdentifier() == ".req") {
5445     parseDirectiveReq(Name, NameLoc);
5446     // We always return 'error' for this, as we're done with this
5447     // statement and don't need to match the 'instruction."
5448     return true;
5449   }
5450 
5451   // Create the leading tokens for the mnemonic, split by '.' characters.
5452   size_t Start = 0, Next = Name.find('.');
5453   StringRef Mnemonic = Name.slice(Start, Next);
5454 
5455   // Split out the predication code and carry setting flag from the mnemonic.
5456   unsigned PredicationCode;
5457   unsigned ProcessorIMod;
5458   bool CarrySetting;
5459   StringRef ITMask;
5460   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5461                            ProcessorIMod, ITMask);
5462 
5463   // In Thumb1, only the branch (B) instruction can be predicated.
5464   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5465     Parser.eatToEndOfStatement();
5466     return Error(NameLoc, "conditional execution not supported in Thumb1");
5467   }
5468 
5469   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5470 
5471   // Handle the IT instruction ITMask. Convert it to a bitmask. This
5472   // is the mask as it will be for the IT encoding if the conditional
5473   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5474   // where the conditional bit0 is zero, the instruction post-processing
5475   // will adjust the mask accordingly.
5476   if (Mnemonic == "it") {
5477     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5478     if (ITMask.size() > 3) {
5479       Parser.eatToEndOfStatement();
5480       return Error(Loc, "too many conditions on IT instruction");
5481     }
5482     unsigned Mask = 8;
5483     for (unsigned i = ITMask.size(); i != 0; --i) {
5484       char pos = ITMask[i - 1];
5485       if (pos != 't' && pos != 'e') {
5486         Parser.eatToEndOfStatement();
5487         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5488       }
5489       Mask >>= 1;
5490       if (ITMask[i - 1] == 't')
5491         Mask |= 8;
5492     }
5493     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5494   }
5495 
5496   // FIXME: This is all a pretty gross hack. We should automatically handle
5497   // optional operands like this via tblgen.
5498 
5499   // Next, add the CCOut and ConditionCode operands, if needed.
5500   //
5501   // For mnemonics which can ever incorporate a carry setting bit or predication
5502   // code, our matching model involves us always generating CCOut and
5503   // ConditionCode operands to match the mnemonic "as written" and then we let
5504   // the matcher deal with finding the right instruction or generating an
5505   // appropriate error.
5506   bool CanAcceptCarrySet, CanAcceptPredicationCode;
5507   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5508 
5509   // If we had a carry-set on an instruction that can't do that, issue an
5510   // error.
5511   if (!CanAcceptCarrySet && CarrySetting) {
5512     Parser.eatToEndOfStatement();
5513     return Error(NameLoc, "instruction '" + Mnemonic +
5514                  "' can not set flags, but 's' suffix specified");
5515   }
5516   // If we had a predication code on an instruction that can't do that, issue an
5517   // error.
5518   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5519     Parser.eatToEndOfStatement();
5520     return Error(NameLoc, "instruction '" + Mnemonic +
5521                  "' is not predicable, but condition code specified");
5522   }
5523 
5524   // Add the carry setting operand, if necessary.
5525   if (CanAcceptCarrySet) {
5526     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5527     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5528                                                Loc));
5529   }
5530 
5531   // Add the predication code operand, if necessary.
5532   if (CanAcceptPredicationCode) {
5533     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5534                                       CarrySetting);
5535     Operands.push_back(ARMOperand::CreateCondCode(
5536                          ARMCC::CondCodes(PredicationCode), Loc));
5537   }
5538 
5539   // Add the processor imod operand, if necessary.
5540   if (ProcessorIMod) {
5541     Operands.push_back(ARMOperand::CreateImm(
5542           MCConstantExpr::Create(ProcessorIMod, getContext()),
5543                                  NameLoc, NameLoc));
5544   } else if (Mnemonic == "cps" && isMClass()) {
5545     return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5546   }
5547 
5548   // Add the remaining tokens in the mnemonic.
5549   while (Next != StringRef::npos) {
5550     Start = Next;
5551     Next = Name.find('.', Start + 1);
5552     StringRef ExtraToken = Name.slice(Start, Next);
5553 
5554     // Some NEON instructions have an optional datatype suffix that is
5555     // completely ignored. Check for that.
5556     if (isDataTypeToken(ExtraToken) &&
5557         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5558       continue;
5559 
5560     // For for ARM mode generate an error if the .n qualifier is used.
5561     if (ExtraToken == ".n" && !isThumb()) {
5562       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5563       Parser.eatToEndOfStatement();
5564       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5565                    "arm mode");
5566     }
5567 
5568     // The .n qualifier is always discarded as that is what the tables
5569     // and matcher expect.  In ARM mode the .w qualifier has no effect,
5570     // so discard it to avoid errors that can be caused by the matcher.
5571     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5572       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5573       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5574     }
5575   }
5576 
5577   // Read the remaining operands.
5578   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5579     // Read the first operand.
5580     if (parseOperand(Operands, Mnemonic)) {
5581       Parser.eatToEndOfStatement();
5582       return true;
5583     }
5584 
5585     while (getLexer().is(AsmToken::Comma)) {
5586       Parser.Lex();  // Eat the comma.
5587 
5588       // Parse and remember the operand.
5589       if (parseOperand(Operands, Mnemonic)) {
5590         Parser.eatToEndOfStatement();
5591         return true;
5592       }
5593     }
5594   }
5595 
5596   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5597     SMLoc Loc = getLexer().getLoc();
5598     Parser.eatToEndOfStatement();
5599     return Error(Loc, "unexpected token in argument list");
5600   }
5601 
5602   Parser.Lex(); // Consume the EndOfStatement
5603 
5604   if (RequireVFPRegisterListCheck) {
5605     ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5606     if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5607       return Error(Op.getStartLoc(),
5608                    "VFP/Neon single precision register expected");
5609     if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5610       return Error(Op.getStartLoc(),
5611                    "VFP/Neon double precision register expected");
5612   }
5613 
5614   // Some instructions, mostly Thumb, have forms for the same mnemonic that
5615   // do and don't have a cc_out optional-def operand. With some spot-checks
5616   // of the operand list, we can figure out which variant we're trying to
5617   // parse and adjust accordingly before actually matching. We shouldn't ever
5618   // try to remove a cc_out operand that was explicitly set on the the
5619   // mnemonic, of course (CarrySetting == true). Reason number #317 the
5620   // table driven matcher doesn't fit well with the ARM instruction set.
5621   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5622     Operands.erase(Operands.begin() + 1);
5623 
5624   // Some instructions have the same mnemonic, but don't always
5625   // have a predicate. Distinguish them here and delete the
5626   // predicate if needed.
5627   if (shouldOmitPredicateOperand(Mnemonic, Operands))
5628     Operands.erase(Operands.begin() + 1);
5629 
5630   // ARM mode 'blx' need special handling, as the register operand version
5631   // is predicable, but the label operand version is not. So, we can't rely
5632   // on the Mnemonic based checking to correctly figure out when to put
5633   // a k_CondCode operand in the list. If we're trying to match the label
5634   // version, remove the k_CondCode operand here.
5635   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5636       static_cast<ARMOperand &>(*Operands[2]).isImm())
5637     Operands.erase(Operands.begin() + 1);
5638 
5639   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5640   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5641   // a single GPRPair reg operand is used in the .td file to replace the two
5642   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5643   // expressed as a GPRPair, so we have to manually merge them.
5644   // FIXME: We would really like to be able to tablegen'erate this.
5645   if (!isThumb() && Operands.size() > 4 &&
5646       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5647        Mnemonic == "stlexd")) {
5648     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5649     unsigned Idx = isLoad ? 2 : 3;
5650     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5651     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5652 
5653     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5654     // Adjust only if Op1 and Op2 are GPRs.
5655     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5656         MRC.contains(Op2.getReg())) {
5657       unsigned Reg1 = Op1.getReg();
5658       unsigned Reg2 = Op2.getReg();
5659       unsigned Rt = MRI->getEncodingValue(Reg1);
5660       unsigned Rt2 = MRI->getEncodingValue(Reg2);
5661 
5662       // Rt2 must be Rt + 1 and Rt must be even.
5663       if (Rt + 1 != Rt2 || (Rt & 1)) {
5664         Error(Op2.getStartLoc(), isLoad
5665                                      ? "destination operands must be sequential"
5666                                      : "source operands must be sequential");
5667         return true;
5668       }
5669       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5670           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5671       Operands[Idx] =
5672           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5673       Operands.erase(Operands.begin() + Idx + 1);
5674     }
5675   }
5676 
5677   // If first 2 operands of a 3 operand instruction are the same
5678   // then transform to 2 operand version of the same instruction
5679   // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5680   // FIXME: We would really like to be able to tablegen'erate this.
5681   if (isThumbOne() && Operands.size() == 6 &&
5682        (Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5683         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5684         Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5685         Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) {
5686       ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5687       ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5688       ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5689 
5690       // If both registers are the same then remove one of them from
5691       // the operand list.
5692       if (Op3.isReg() && Op4.isReg() && Op3.getReg() == Op4.getReg()) {
5693           // If 3rd operand (variable Op5) is a register and the instruction is adds/sub
5694           // then do not transform as the backend already handles this instruction
5695           // correctly.
5696           if (!Op5.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) {
5697               Operands.erase(Operands.begin() + 3);
5698               if (Mnemonic == "add" && !CarrySetting) {
5699                   // Special case for 'add' (not 'adds') instruction must
5700                   // remove the CCOut operand as well.
5701                   Operands.erase(Operands.begin() + 1);
5702               }
5703           }
5704       }
5705   }
5706 
5707   // If instruction is 'add' and first two register operands
5708   // use SP register, then remove one of the SP registers from
5709   // the instruction.
5710   // FIXME: We would really like to be able to tablegen'erate this.
5711   if (isThumbOne() && Operands.size() == 5 && Mnemonic == "add" && !CarrySetting) {
5712       ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5713       ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5714       if (Op2.isReg() && Op3.isReg() && Op2.getReg() == ARM::SP && Op3.getReg() == ARM::SP) {
5715           Operands.erase(Operands.begin() + 2);
5716       }
5717   }
5718 
5719   // GNU Assembler extension (compatibility)
5720   if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5721     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5722     ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5723     if (Op3.isMem()) {
5724       assert(Op2.isReg() && "expected register argument");
5725 
5726       unsigned SuperReg = MRI->getMatchingSuperReg(
5727           Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5728 
5729       assert(SuperReg && "expected register pair");
5730 
5731       unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5732 
5733       Operands.insert(
5734           Operands.begin() + 3,
5735           ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5736     }
5737   }
5738 
5739   // FIXME: As said above, this is all a pretty gross hack.  This instruction
5740   // does not fit with other "subs" and tblgen.
5741   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5742   // so the Mnemonic is the original name "subs" and delete the predicate
5743   // operand so it will match the table entry.
5744   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5745       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5746       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5747       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5748       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5749       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5750     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5751     Operands.erase(Operands.begin() + 1);
5752   }
5753   return false;
5754 }
5755 
5756 // Validate context-sensitive operand constraints.
5757 
5758 // return 'true' if register list contains non-low GPR registers,
5759 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5760 // 'containsReg' to true.
5761 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5762                                  unsigned HiReg, bool &containsReg) {
5763   containsReg = false;
5764   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5765     unsigned OpReg = Inst.getOperand(i).getReg();
5766     if (OpReg == Reg)
5767       containsReg = true;
5768     // Anything other than a low register isn't legal here.
5769     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5770       return true;
5771   }
5772   return false;
5773 }
5774 
5775 // Check if the specified regisgter is in the register list of the inst,
5776 // starting at the indicated operand number.
5777 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5778   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5779     unsigned OpReg = Inst.getOperand(i).getReg();
5780     if (OpReg == Reg)
5781       return true;
5782   }
5783   return false;
5784 }
5785 
5786 // Return true if instruction has the interesting property of being
5787 // allowed in IT blocks, but not being predicable.
5788 static bool instIsBreakpoint(const MCInst &Inst) {
5789     return Inst.getOpcode() == ARM::tBKPT ||
5790            Inst.getOpcode() == ARM::BKPT ||
5791            Inst.getOpcode() == ARM::tHLT ||
5792            Inst.getOpcode() == ARM::HLT;
5793 
5794 }
5795 
5796 // FIXME: We would really like to be able to tablegen'erate this.
5797 bool ARMAsmParser::validateInstruction(MCInst &Inst,
5798                                        const OperandVector &Operands) {
5799   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5800   SMLoc Loc = Operands[0]->getStartLoc();
5801 
5802   // Check the IT block state first.
5803   // NOTE: BKPT and HLT instructions have the interesting property of being
5804   // allowed in IT blocks, but not being predicable. They just always execute.
5805   if (inITBlock() && !instIsBreakpoint(Inst)) {
5806     unsigned Bit = 1;
5807     if (ITState.FirstCond)
5808       ITState.FirstCond = false;
5809     else
5810       Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5811     // The instruction must be predicable.
5812     if (!MCID.isPredicable())
5813       return Error(Loc, "instructions in IT block must be predicable");
5814     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5815     unsigned ITCond = Bit ? ITState.Cond :
5816       ARMCC::getOppositeCondition(ITState.Cond);
5817     if (Cond != ITCond) {
5818       // Find the condition code Operand to get its SMLoc information.
5819       SMLoc CondLoc;
5820       for (unsigned I = 1; I < Operands.size(); ++I)
5821         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
5822           CondLoc = Operands[I]->getStartLoc();
5823       return Error(CondLoc, "incorrect condition in IT block; got '" +
5824                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5825                    "', but expected '" +
5826                    ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5827     }
5828   // Check for non-'al' condition codes outside of the IT block.
5829   } else if (isThumbTwo() && MCID.isPredicable() &&
5830              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5831              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5832              Inst.getOpcode() != ARM::t2Bcc)
5833     return Error(Loc, "predicated instructions must be in IT block");
5834 
5835   const unsigned Opcode = Inst.getOpcode();
5836   switch (Opcode) {
5837   case ARM::LDRD:
5838   case ARM::LDRD_PRE:
5839   case ARM::LDRD_POST: {
5840     const unsigned RtReg = Inst.getOperand(0).getReg();
5841 
5842     // Rt can't be R14.
5843     if (RtReg == ARM::LR)
5844       return Error(Operands[3]->getStartLoc(),
5845                    "Rt can't be R14");
5846 
5847     const unsigned Rt = MRI->getEncodingValue(RtReg);
5848     // Rt must be even-numbered.
5849     if ((Rt & 1) == 1)
5850       return Error(Operands[3]->getStartLoc(),
5851                    "Rt must be even-numbered");
5852 
5853     // Rt2 must be Rt + 1.
5854     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5855     if (Rt2 != Rt + 1)
5856       return Error(Operands[3]->getStartLoc(),
5857                    "destination operands must be sequential");
5858 
5859     if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5860       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5861       // For addressing modes with writeback, the base register needs to be
5862       // different from the destination registers.
5863       if (Rn == Rt || Rn == Rt2)
5864         return Error(Operands[3]->getStartLoc(),
5865                      "base register needs to be different from destination "
5866                      "registers");
5867     }
5868 
5869     return false;
5870   }
5871   case ARM::t2LDRDi8:
5872   case ARM::t2LDRD_PRE:
5873   case ARM::t2LDRD_POST: {
5874     // Rt2 must be different from Rt.
5875     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5876     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5877     if (Rt2 == Rt)
5878       return Error(Operands[3]->getStartLoc(),
5879                    "destination operands can't be identical");
5880     return false;
5881   }
5882   case ARM::STRD: {
5883     // Rt2 must be Rt + 1.
5884     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5885     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5886     if (Rt2 != Rt + 1)
5887       return Error(Operands[3]->getStartLoc(),
5888                    "source operands must be sequential");
5889     return false;
5890   }
5891   case ARM::STRD_PRE:
5892   case ARM::STRD_POST: {
5893     // Rt2 must be Rt + 1.
5894     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5895     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5896     if (Rt2 != Rt + 1)
5897       return Error(Operands[3]->getStartLoc(),
5898                    "source operands must be sequential");
5899     return false;
5900   }
5901   case ARM::STR_PRE_IMM:
5902   case ARM::STR_PRE_REG:
5903   case ARM::STR_POST_IMM:
5904   case ARM::STR_POST_REG:
5905   case ARM::STRH_PRE:
5906   case ARM::STRH_POST:
5907   case ARM::STRB_PRE_IMM:
5908   case ARM::STRB_PRE_REG:
5909   case ARM::STRB_POST_IMM:
5910   case ARM::STRB_POST_REG: {
5911     // Rt must be different from Rn.
5912     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5913     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5914 
5915     if (Rt == Rn)
5916       return Error(Operands[3]->getStartLoc(),
5917                    "source register and base register can't be identical");
5918     return false;
5919   }
5920   case ARM::LDR_PRE_IMM:
5921   case ARM::LDR_PRE_REG:
5922   case ARM::LDR_POST_IMM:
5923   case ARM::LDR_POST_REG:
5924   case ARM::LDRH_PRE:
5925   case ARM::LDRH_POST:
5926   case ARM::LDRSH_PRE:
5927   case ARM::LDRSH_POST:
5928   case ARM::LDRB_PRE_IMM:
5929   case ARM::LDRB_PRE_REG:
5930   case ARM::LDRB_POST_IMM:
5931   case ARM::LDRB_POST_REG:
5932   case ARM::LDRSB_PRE:
5933   case ARM::LDRSB_POST: {
5934     // Rt must be different from Rn.
5935     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5936     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5937 
5938     if (Rt == Rn)
5939       return Error(Operands[3]->getStartLoc(),
5940                    "destination register and base register can't be identical");
5941     return false;
5942   }
5943   case ARM::SBFX:
5944   case ARM::UBFX: {
5945     // Width must be in range [1, 32-lsb].
5946     unsigned LSB = Inst.getOperand(2).getImm();
5947     unsigned Widthm1 = Inst.getOperand(3).getImm();
5948     if (Widthm1 >= 32 - LSB)
5949       return Error(Operands[5]->getStartLoc(),
5950                    "bitfield width must be in range [1,32-lsb]");
5951     return false;
5952   }
5953   // Notionally handles ARM::tLDMIA_UPD too.
5954   case ARM::tLDMIA: {
5955     // If we're parsing Thumb2, the .w variant is available and handles
5956     // most cases that are normally illegal for a Thumb1 LDM instruction.
5957     // We'll make the transformation in processInstruction() if necessary.
5958     //
5959     // Thumb LDM instructions are writeback iff the base register is not
5960     // in the register list.
5961     unsigned Rn = Inst.getOperand(0).getReg();
5962     bool HasWritebackToken =
5963         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5964          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
5965     bool ListContainsBase;
5966     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5967       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5968                    "registers must be in range r0-r7");
5969     // If we should have writeback, then there should be a '!' token.
5970     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5971       return Error(Operands[2]->getStartLoc(),
5972                    "writeback operator '!' expected");
5973     // If we should not have writeback, there must not be a '!'. This is
5974     // true even for the 32-bit wide encodings.
5975     if (ListContainsBase && HasWritebackToken)
5976       return Error(Operands[3]->getStartLoc(),
5977                    "writeback operator '!' not allowed when base register "
5978                    "in register list");
5979 
5980     break;
5981   }
5982   case ARM::LDMIA_UPD:
5983   case ARM::LDMDB_UPD:
5984   case ARM::LDMIB_UPD:
5985   case ARM::LDMDA_UPD:
5986     // ARM variants loading and updating the same register are only officially
5987     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5988     if (!hasV7Ops())
5989       break;
5990     // Fallthrough
5991   case ARM::t2LDMIA_UPD:
5992   case ARM::t2LDMDB_UPD:
5993   case ARM::t2STMIA_UPD:
5994   case ARM::t2STMDB_UPD: {
5995     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5996       return Error(Operands.back()->getStartLoc(),
5997                    "writeback register not allowed in register list");
5998     break;
5999   }
6000   case ARM::sysLDMIA_UPD:
6001   case ARM::sysLDMDA_UPD:
6002   case ARM::sysLDMDB_UPD:
6003   case ARM::sysLDMIB_UPD:
6004     if (!listContainsReg(Inst, 3, ARM::PC))
6005       return Error(Operands[4]->getStartLoc(),
6006                    "writeback register only allowed on system LDM "
6007                    "if PC in register-list");
6008     break;
6009   case ARM::sysSTMIA_UPD:
6010   case ARM::sysSTMDA_UPD:
6011   case ARM::sysSTMDB_UPD:
6012   case ARM::sysSTMIB_UPD:
6013     return Error(Operands[2]->getStartLoc(),
6014                  "system STM cannot have writeback register");
6015   case ARM::tMUL: {
6016     // The second source operand must be the same register as the destination
6017     // operand.
6018     //
6019     // In this case, we must directly check the parsed operands because the
6020     // cvtThumbMultiply() function is written in such a way that it guarantees
6021     // this first statement is always true for the new Inst.  Essentially, the
6022     // destination is unconditionally copied into the second source operand
6023     // without checking to see if it matches what we actually parsed.
6024     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6025                                  ((ARMOperand &)*Operands[5]).getReg()) &&
6026         (((ARMOperand &)*Operands[3]).getReg() !=
6027          ((ARMOperand &)*Operands[4]).getReg())) {
6028       return Error(Operands[3]->getStartLoc(),
6029                    "destination register must match source register");
6030     }
6031     break;
6032   }
6033   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6034   // so only issue a diagnostic for thumb1. The instructions will be
6035   // switched to the t2 encodings in processInstruction() if necessary.
6036   case ARM::tPOP: {
6037     bool ListContainsBase;
6038     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6039         !isThumbTwo())
6040       return Error(Operands[2]->getStartLoc(),
6041                    "registers must be in range r0-r7 or pc");
6042     break;
6043   }
6044   case ARM::tPUSH: {
6045     bool ListContainsBase;
6046     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6047         !isThumbTwo())
6048       return Error(Operands[2]->getStartLoc(),
6049                    "registers must be in range r0-r7 or lr");
6050     break;
6051   }
6052   case ARM::tSTMIA_UPD: {
6053     bool ListContainsBase, InvalidLowList;
6054     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6055                                           0, ListContainsBase);
6056     if (InvalidLowList && !isThumbTwo())
6057       return Error(Operands[4]->getStartLoc(),
6058                    "registers must be in range r0-r7");
6059 
6060     // This would be converted to a 32-bit stm, but that's not valid if the
6061     // writeback register is in the list.
6062     if (InvalidLowList && ListContainsBase)
6063       return Error(Operands[4]->getStartLoc(),
6064                    "writeback operator '!' not allowed when base register "
6065                    "in register list");
6066     break;
6067   }
6068   case ARM::tADDrSP: {
6069     // If the non-SP source operand and the destination operand are not the
6070     // same, we need thumb2 (for the wide encoding), or we have an error.
6071     if (!isThumbTwo() &&
6072         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6073       return Error(Operands[4]->getStartLoc(),
6074                    "source register must be the same as destination");
6075     }
6076     break;
6077   }
6078   // Final range checking for Thumb unconditional branch instructions.
6079   case ARM::tB:
6080     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6081       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6082     break;
6083   case ARM::t2B: {
6084     int op = (Operands[2]->isImm()) ? 2 : 3;
6085     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6086       return Error(Operands[op]->getStartLoc(), "branch target out of range");
6087     break;
6088   }
6089   // Final range checking for Thumb conditional branch instructions.
6090   case ARM::tBcc:
6091     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6092       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6093     break;
6094   case ARM::t2Bcc: {
6095     int Op = (Operands[2]->isImm()) ? 2 : 3;
6096     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6097       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6098     break;
6099   }
6100   case ARM::MOVi16:
6101   case ARM::t2MOVi16:
6102   case ARM::t2MOVTi16:
6103     {
6104     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6105     // especially when we turn it into a movw and the expression <symbol> does
6106     // not have a :lower16: or :upper16 as part of the expression.  We don't
6107     // want the behavior of silently truncating, which can be unexpected and
6108     // lead to bugs that are difficult to find since this is an easy mistake
6109     // to make.
6110     int i = (Operands[3]->isImm()) ? 3 : 4;
6111     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6112     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6113     if (CE) break;
6114     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6115     if (!E) break;
6116     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6117     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6118                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6119       return Error(
6120           Op.getStartLoc(),
6121           "immediate expression for mov requires :lower16: or :upper16");
6122     break;
6123   }
6124   }
6125 
6126   return false;
6127 }
6128 
6129 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6130   switch(Opc) {
6131   default: llvm_unreachable("unexpected opcode!");
6132   // VST1LN
6133   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6134   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6135   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6136   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6137   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6138   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6139   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
6140   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6141   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6142 
6143   // VST2LN
6144   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6145   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6146   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6147   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6148   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6149 
6150   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6151   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6152   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6153   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6154   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6155 
6156   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
6157   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6158   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6159   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6160   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6161 
6162   // VST3LN
6163   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6164   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6165   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6166   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6167   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6168   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6169   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6170   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6171   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6172   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6173   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
6174   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6175   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6176   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6177   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6178 
6179   // VST3
6180   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6181   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6182   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6183   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6184   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6185   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6186   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6187   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6188   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6189   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6190   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6191   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6192   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
6193   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6194   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6195   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
6196   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6197   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6198 
6199   // VST4LN
6200   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6201   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6202   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6203   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6204   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6205   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6206   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6207   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6208   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6209   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6210   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
6211   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6212   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6213   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6214   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6215 
6216   // VST4
6217   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6218   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6219   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6220   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6221   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6222   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6223   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6224   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6225   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6226   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6227   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6228   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6229   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
6230   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6231   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6232   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
6233   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6234   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6235   }
6236 }
6237 
6238 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6239   switch(Opc) {
6240   default: llvm_unreachable("unexpected opcode!");
6241   // VLD1LN
6242   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6243   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6244   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6245   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6246   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6247   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6248   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
6249   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6250   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6251 
6252   // VLD2LN
6253   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6254   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6255   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6256   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6257   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6258   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6259   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6260   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6261   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6262   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6263   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
6264   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6265   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6266   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6267   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6268 
6269   // VLD3DUP
6270   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6271   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6272   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6273   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6274   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6275   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6276   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6277   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6278   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6279   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6280   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6281   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6282   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
6283   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6284   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6285   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6286   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6287   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6288 
6289   // VLD3LN
6290   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6291   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6292   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6293   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6294   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6295   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6296   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6297   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6298   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6299   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6300   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
6301   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6302   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6303   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6304   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6305 
6306   // VLD3
6307   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6308   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6309   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6310   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6311   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6312   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6313   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6314   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6315   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6316   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6317   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6318   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6319   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
6320   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6321   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6322   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
6323   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6324   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6325 
6326   // VLD4LN
6327   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6328   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6329   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6330   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6331   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6332   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6333   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6334   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6335   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6336   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6337   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
6338   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6339   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6340   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6341   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6342 
6343   // VLD4DUP
6344   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6345   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6346   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6347   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6348   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6349   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6350   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6351   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6352   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6353   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6354   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6355   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6356   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
6357   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6358   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6359   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6360   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6361   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6362 
6363   // VLD4
6364   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6365   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6366   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6367   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6368   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6369   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6370   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6371   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6372   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6373   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6374   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6375   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6376   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
6377   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6378   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6379   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
6380   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6381   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6382   }
6383 }
6384 
6385 bool ARMAsmParser::processInstruction(MCInst &Inst,
6386                                       const OperandVector &Operands) {
6387   switch (Inst.getOpcode()) {
6388   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6389   case ARM::LDRT_POST:
6390   case ARM::LDRBT_POST: {
6391     const unsigned Opcode =
6392       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6393                                            : ARM::LDRBT_POST_IMM;
6394     MCInst TmpInst;
6395     TmpInst.setOpcode(Opcode);
6396     TmpInst.addOperand(Inst.getOperand(0));
6397     TmpInst.addOperand(Inst.getOperand(1));
6398     TmpInst.addOperand(Inst.getOperand(1));
6399     TmpInst.addOperand(MCOperand::CreateReg(0));
6400     TmpInst.addOperand(MCOperand::CreateImm(0));
6401     TmpInst.addOperand(Inst.getOperand(2));
6402     TmpInst.addOperand(Inst.getOperand(3));
6403     Inst = TmpInst;
6404     return true;
6405   }
6406   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6407   case ARM::STRT_POST:
6408   case ARM::STRBT_POST: {
6409     const unsigned Opcode =
6410       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6411                                            : ARM::STRBT_POST_IMM;
6412     MCInst TmpInst;
6413     TmpInst.setOpcode(Opcode);
6414     TmpInst.addOperand(Inst.getOperand(1));
6415     TmpInst.addOperand(Inst.getOperand(0));
6416     TmpInst.addOperand(Inst.getOperand(1));
6417     TmpInst.addOperand(MCOperand::CreateReg(0));
6418     TmpInst.addOperand(MCOperand::CreateImm(0));
6419     TmpInst.addOperand(Inst.getOperand(2));
6420     TmpInst.addOperand(Inst.getOperand(3));
6421     Inst = TmpInst;
6422     return true;
6423   }
6424   // Alias for alternate form of 'ADR Rd, #imm' instruction.
6425   case ARM::ADDri: {
6426     if (Inst.getOperand(1).getReg() != ARM::PC ||
6427         Inst.getOperand(5).getReg() != 0)
6428       return false;
6429     MCInst TmpInst;
6430     TmpInst.setOpcode(ARM::ADR);
6431     TmpInst.addOperand(Inst.getOperand(0));
6432     TmpInst.addOperand(Inst.getOperand(2));
6433     TmpInst.addOperand(Inst.getOperand(3));
6434     TmpInst.addOperand(Inst.getOperand(4));
6435     Inst = TmpInst;
6436     return true;
6437   }
6438   // Aliases for alternate PC+imm syntax of LDR instructions.
6439   case ARM::t2LDRpcrel:
6440     // Select the narrow version if the immediate will fit.
6441     if (Inst.getOperand(1).getImm() > 0 &&
6442         Inst.getOperand(1).getImm() <= 0xff &&
6443         !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6444           static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6445       Inst.setOpcode(ARM::tLDRpci);
6446     else
6447       Inst.setOpcode(ARM::t2LDRpci);
6448     return true;
6449   case ARM::t2LDRBpcrel:
6450     Inst.setOpcode(ARM::t2LDRBpci);
6451     return true;
6452   case ARM::t2LDRHpcrel:
6453     Inst.setOpcode(ARM::t2LDRHpci);
6454     return true;
6455   case ARM::t2LDRSBpcrel:
6456     Inst.setOpcode(ARM::t2LDRSBpci);
6457     return true;
6458   case ARM::t2LDRSHpcrel:
6459     Inst.setOpcode(ARM::t2LDRSHpci);
6460     return true;
6461   // Handle NEON VST complex aliases.
6462   case ARM::VST1LNdWB_register_Asm_8:
6463   case ARM::VST1LNdWB_register_Asm_16:
6464   case ARM::VST1LNdWB_register_Asm_32: {
6465     MCInst TmpInst;
6466     // Shuffle the operands around so the lane index operand is in the
6467     // right place.
6468     unsigned Spacing;
6469     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6470     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6471     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6472     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6473     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6474     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6475     TmpInst.addOperand(Inst.getOperand(1)); // lane
6476     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6477     TmpInst.addOperand(Inst.getOperand(6));
6478     Inst = TmpInst;
6479     return true;
6480   }
6481 
6482   case ARM::VST2LNdWB_register_Asm_8:
6483   case ARM::VST2LNdWB_register_Asm_16:
6484   case ARM::VST2LNdWB_register_Asm_32:
6485   case ARM::VST2LNqWB_register_Asm_16:
6486   case ARM::VST2LNqWB_register_Asm_32: {
6487     MCInst TmpInst;
6488     // Shuffle the operands around so the lane index operand is in the
6489     // right place.
6490     unsigned Spacing;
6491     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6492     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6493     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6494     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6495     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6496     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6497     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6498                                             Spacing));
6499     TmpInst.addOperand(Inst.getOperand(1)); // lane
6500     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6501     TmpInst.addOperand(Inst.getOperand(6));
6502     Inst = TmpInst;
6503     return true;
6504   }
6505 
6506   case ARM::VST3LNdWB_register_Asm_8:
6507   case ARM::VST3LNdWB_register_Asm_16:
6508   case ARM::VST3LNdWB_register_Asm_32:
6509   case ARM::VST3LNqWB_register_Asm_16:
6510   case ARM::VST3LNqWB_register_Asm_32: {
6511     MCInst TmpInst;
6512     // Shuffle the operands around so the lane index operand is in the
6513     // right place.
6514     unsigned Spacing;
6515     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6516     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6517     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6518     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6519     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6520     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6521     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6522                                             Spacing));
6523     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6524                                             Spacing * 2));
6525     TmpInst.addOperand(Inst.getOperand(1)); // lane
6526     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6527     TmpInst.addOperand(Inst.getOperand(6));
6528     Inst = TmpInst;
6529     return true;
6530   }
6531 
6532   case ARM::VST4LNdWB_register_Asm_8:
6533   case ARM::VST4LNdWB_register_Asm_16:
6534   case ARM::VST4LNdWB_register_Asm_32:
6535   case ARM::VST4LNqWB_register_Asm_16:
6536   case ARM::VST4LNqWB_register_Asm_32: {
6537     MCInst TmpInst;
6538     // Shuffle the operands around so the lane index operand is in the
6539     // right place.
6540     unsigned Spacing;
6541     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6542     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6543     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6544     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6545     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6546     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6547     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6548                                             Spacing));
6549     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6550                                             Spacing * 2));
6551     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6552                                             Spacing * 3));
6553     TmpInst.addOperand(Inst.getOperand(1)); // lane
6554     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6555     TmpInst.addOperand(Inst.getOperand(6));
6556     Inst = TmpInst;
6557     return true;
6558   }
6559 
6560   case ARM::VST1LNdWB_fixed_Asm_8:
6561   case ARM::VST1LNdWB_fixed_Asm_16:
6562   case ARM::VST1LNdWB_fixed_Asm_32: {
6563     MCInst TmpInst;
6564     // Shuffle the operands around so the lane index operand is in the
6565     // right place.
6566     unsigned Spacing;
6567     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6568     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6569     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6570     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6571     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6572     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6573     TmpInst.addOperand(Inst.getOperand(1)); // lane
6574     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6575     TmpInst.addOperand(Inst.getOperand(5));
6576     Inst = TmpInst;
6577     return true;
6578   }
6579 
6580   case ARM::VST2LNdWB_fixed_Asm_8:
6581   case ARM::VST2LNdWB_fixed_Asm_16:
6582   case ARM::VST2LNdWB_fixed_Asm_32:
6583   case ARM::VST2LNqWB_fixed_Asm_16:
6584   case ARM::VST2LNqWB_fixed_Asm_32: {
6585     MCInst TmpInst;
6586     // Shuffle the operands around so the lane index operand is in the
6587     // right place.
6588     unsigned Spacing;
6589     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6590     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6591     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6592     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6593     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6594     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6595     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6596                                             Spacing));
6597     TmpInst.addOperand(Inst.getOperand(1)); // lane
6598     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6599     TmpInst.addOperand(Inst.getOperand(5));
6600     Inst = TmpInst;
6601     return true;
6602   }
6603 
6604   case ARM::VST3LNdWB_fixed_Asm_8:
6605   case ARM::VST3LNdWB_fixed_Asm_16:
6606   case ARM::VST3LNdWB_fixed_Asm_32:
6607   case ARM::VST3LNqWB_fixed_Asm_16:
6608   case ARM::VST3LNqWB_fixed_Asm_32: {
6609     MCInst TmpInst;
6610     // Shuffle the operands around so the lane index operand is in the
6611     // right place.
6612     unsigned Spacing;
6613     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6614     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6615     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6616     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6617     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6618     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6619     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6620                                             Spacing));
6621     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6622                                             Spacing * 2));
6623     TmpInst.addOperand(Inst.getOperand(1)); // lane
6624     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6625     TmpInst.addOperand(Inst.getOperand(5));
6626     Inst = TmpInst;
6627     return true;
6628   }
6629 
6630   case ARM::VST4LNdWB_fixed_Asm_8:
6631   case ARM::VST4LNdWB_fixed_Asm_16:
6632   case ARM::VST4LNdWB_fixed_Asm_32:
6633   case ARM::VST4LNqWB_fixed_Asm_16:
6634   case ARM::VST4LNqWB_fixed_Asm_32: {
6635     MCInst TmpInst;
6636     // Shuffle the operands around so the lane index operand is in the
6637     // right place.
6638     unsigned Spacing;
6639     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6640     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6641     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6642     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6643     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6644     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6645     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6646                                             Spacing));
6647     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6648                                             Spacing * 2));
6649     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6650                                             Spacing * 3));
6651     TmpInst.addOperand(Inst.getOperand(1)); // lane
6652     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6653     TmpInst.addOperand(Inst.getOperand(5));
6654     Inst = TmpInst;
6655     return true;
6656   }
6657 
6658   case ARM::VST1LNdAsm_8:
6659   case ARM::VST1LNdAsm_16:
6660   case ARM::VST1LNdAsm_32: {
6661     MCInst TmpInst;
6662     // Shuffle the operands around so the lane index operand is in the
6663     // right place.
6664     unsigned Spacing;
6665     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6666     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6667     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6668     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6669     TmpInst.addOperand(Inst.getOperand(1)); // lane
6670     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6671     TmpInst.addOperand(Inst.getOperand(5));
6672     Inst = TmpInst;
6673     return true;
6674   }
6675 
6676   case ARM::VST2LNdAsm_8:
6677   case ARM::VST2LNdAsm_16:
6678   case ARM::VST2LNdAsm_32:
6679   case ARM::VST2LNqAsm_16:
6680   case ARM::VST2LNqAsm_32: {
6681     MCInst TmpInst;
6682     // Shuffle the operands around so the lane index operand is in the
6683     // right place.
6684     unsigned Spacing;
6685     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6686     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6687     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6688     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6689     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6690                                             Spacing));
6691     TmpInst.addOperand(Inst.getOperand(1)); // lane
6692     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6693     TmpInst.addOperand(Inst.getOperand(5));
6694     Inst = TmpInst;
6695     return true;
6696   }
6697 
6698   case ARM::VST3LNdAsm_8:
6699   case ARM::VST3LNdAsm_16:
6700   case ARM::VST3LNdAsm_32:
6701   case ARM::VST3LNqAsm_16:
6702   case ARM::VST3LNqAsm_32: {
6703     MCInst TmpInst;
6704     // Shuffle the operands around so the lane index operand is in the
6705     // right place.
6706     unsigned Spacing;
6707     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6708     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6709     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6710     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6711     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6712                                             Spacing));
6713     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6714                                             Spacing * 2));
6715     TmpInst.addOperand(Inst.getOperand(1)); // lane
6716     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6717     TmpInst.addOperand(Inst.getOperand(5));
6718     Inst = TmpInst;
6719     return true;
6720   }
6721 
6722   case ARM::VST4LNdAsm_8:
6723   case ARM::VST4LNdAsm_16:
6724   case ARM::VST4LNdAsm_32:
6725   case ARM::VST4LNqAsm_16:
6726   case ARM::VST4LNqAsm_32: {
6727     MCInst TmpInst;
6728     // Shuffle the operands around so the lane index operand is in the
6729     // right place.
6730     unsigned Spacing;
6731     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6732     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6733     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6734     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6735     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6736                                             Spacing));
6737     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6738                                             Spacing * 2));
6739     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6740                                             Spacing * 3));
6741     TmpInst.addOperand(Inst.getOperand(1)); // lane
6742     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6743     TmpInst.addOperand(Inst.getOperand(5));
6744     Inst = TmpInst;
6745     return true;
6746   }
6747 
6748   // Handle NEON VLD complex aliases.
6749   case ARM::VLD1LNdWB_register_Asm_8:
6750   case ARM::VLD1LNdWB_register_Asm_16:
6751   case ARM::VLD1LNdWB_register_Asm_32: {
6752     MCInst TmpInst;
6753     // Shuffle the operands around so the lane index operand is in the
6754     // right place.
6755     unsigned Spacing;
6756     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6757     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6758     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6759     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6760     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6761     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6762     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6763     TmpInst.addOperand(Inst.getOperand(1)); // lane
6764     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6765     TmpInst.addOperand(Inst.getOperand(6));
6766     Inst = TmpInst;
6767     return true;
6768   }
6769 
6770   case ARM::VLD2LNdWB_register_Asm_8:
6771   case ARM::VLD2LNdWB_register_Asm_16:
6772   case ARM::VLD2LNdWB_register_Asm_32:
6773   case ARM::VLD2LNqWB_register_Asm_16:
6774   case ARM::VLD2LNqWB_register_Asm_32: {
6775     MCInst TmpInst;
6776     // Shuffle the operands around so the lane index operand is in the
6777     // right place.
6778     unsigned Spacing;
6779     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6780     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6781     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6782                                             Spacing));
6783     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6784     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6785     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6786     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6787     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6788     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6789                                             Spacing));
6790     TmpInst.addOperand(Inst.getOperand(1)); // lane
6791     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6792     TmpInst.addOperand(Inst.getOperand(6));
6793     Inst = TmpInst;
6794     return true;
6795   }
6796 
6797   case ARM::VLD3LNdWB_register_Asm_8:
6798   case ARM::VLD3LNdWB_register_Asm_16:
6799   case ARM::VLD3LNdWB_register_Asm_32:
6800   case ARM::VLD3LNqWB_register_Asm_16:
6801   case ARM::VLD3LNqWB_register_Asm_32: {
6802     MCInst TmpInst;
6803     // Shuffle the operands around so the lane index operand is in the
6804     // right place.
6805     unsigned Spacing;
6806     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6807     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6808     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6809                                             Spacing));
6810     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6811                                             Spacing * 2));
6812     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6813     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6814     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6815     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6816     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6817     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6818                                             Spacing));
6819     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6820                                             Spacing * 2));
6821     TmpInst.addOperand(Inst.getOperand(1)); // lane
6822     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6823     TmpInst.addOperand(Inst.getOperand(6));
6824     Inst = TmpInst;
6825     return true;
6826   }
6827 
6828   case ARM::VLD4LNdWB_register_Asm_8:
6829   case ARM::VLD4LNdWB_register_Asm_16:
6830   case ARM::VLD4LNdWB_register_Asm_32:
6831   case ARM::VLD4LNqWB_register_Asm_16:
6832   case ARM::VLD4LNqWB_register_Asm_32: {
6833     MCInst TmpInst;
6834     // Shuffle the operands around so the lane index operand is in the
6835     // right place.
6836     unsigned Spacing;
6837     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6838     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6839     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6840                                             Spacing));
6841     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6842                                             Spacing * 2));
6843     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6844                                             Spacing * 3));
6845     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6846     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6847     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6848     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6849     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6850     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6851                                             Spacing));
6852     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6853                                             Spacing * 2));
6854     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6855                                             Spacing * 3));
6856     TmpInst.addOperand(Inst.getOperand(1)); // lane
6857     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6858     TmpInst.addOperand(Inst.getOperand(6));
6859     Inst = TmpInst;
6860     return true;
6861   }
6862 
6863   case ARM::VLD1LNdWB_fixed_Asm_8:
6864   case ARM::VLD1LNdWB_fixed_Asm_16:
6865   case ARM::VLD1LNdWB_fixed_Asm_32: {
6866     MCInst TmpInst;
6867     // Shuffle the operands around so the lane index operand is in the
6868     // right place.
6869     unsigned Spacing;
6870     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6871     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6872     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6873     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6874     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6875     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6876     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6877     TmpInst.addOperand(Inst.getOperand(1)); // lane
6878     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6879     TmpInst.addOperand(Inst.getOperand(5));
6880     Inst = TmpInst;
6881     return true;
6882   }
6883 
6884   case ARM::VLD2LNdWB_fixed_Asm_8:
6885   case ARM::VLD2LNdWB_fixed_Asm_16:
6886   case ARM::VLD2LNdWB_fixed_Asm_32:
6887   case ARM::VLD2LNqWB_fixed_Asm_16:
6888   case ARM::VLD2LNqWB_fixed_Asm_32: {
6889     MCInst TmpInst;
6890     // Shuffle the operands around so the lane index operand is in the
6891     // right place.
6892     unsigned Spacing;
6893     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6894     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6895     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6896                                             Spacing));
6897     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6898     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6899     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6900     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6901     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6902     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6903                                             Spacing));
6904     TmpInst.addOperand(Inst.getOperand(1)); // lane
6905     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6906     TmpInst.addOperand(Inst.getOperand(5));
6907     Inst = TmpInst;
6908     return true;
6909   }
6910 
6911   case ARM::VLD3LNdWB_fixed_Asm_8:
6912   case ARM::VLD3LNdWB_fixed_Asm_16:
6913   case ARM::VLD3LNdWB_fixed_Asm_32:
6914   case ARM::VLD3LNqWB_fixed_Asm_16:
6915   case ARM::VLD3LNqWB_fixed_Asm_32: {
6916     MCInst TmpInst;
6917     // Shuffle the operands around so the lane index operand is in the
6918     // right place.
6919     unsigned Spacing;
6920     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6921     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6922     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6923                                             Spacing));
6924     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6925                                             Spacing * 2));
6926     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6927     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6928     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6929     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6930     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6931     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6932                                             Spacing));
6933     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6934                                             Spacing * 2));
6935     TmpInst.addOperand(Inst.getOperand(1)); // lane
6936     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6937     TmpInst.addOperand(Inst.getOperand(5));
6938     Inst = TmpInst;
6939     return true;
6940   }
6941 
6942   case ARM::VLD4LNdWB_fixed_Asm_8:
6943   case ARM::VLD4LNdWB_fixed_Asm_16:
6944   case ARM::VLD4LNdWB_fixed_Asm_32:
6945   case ARM::VLD4LNqWB_fixed_Asm_16:
6946   case ARM::VLD4LNqWB_fixed_Asm_32: {
6947     MCInst TmpInst;
6948     // Shuffle the operands around so the lane index operand is in the
6949     // right place.
6950     unsigned Spacing;
6951     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6952     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6953     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6954                                             Spacing));
6955     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6956                                             Spacing * 2));
6957     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6958                                             Spacing * 3));
6959     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6960     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6961     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6962     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6963     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6964     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6965                                             Spacing));
6966     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6967                                             Spacing * 2));
6968     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6969                                             Spacing * 3));
6970     TmpInst.addOperand(Inst.getOperand(1)); // lane
6971     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6972     TmpInst.addOperand(Inst.getOperand(5));
6973     Inst = TmpInst;
6974     return true;
6975   }
6976 
6977   case ARM::VLD1LNdAsm_8:
6978   case ARM::VLD1LNdAsm_16:
6979   case ARM::VLD1LNdAsm_32: {
6980     MCInst TmpInst;
6981     // Shuffle the operands around so the lane index operand is in the
6982     // right place.
6983     unsigned Spacing;
6984     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6985     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6986     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6987     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6988     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6989     TmpInst.addOperand(Inst.getOperand(1)); // lane
6990     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6991     TmpInst.addOperand(Inst.getOperand(5));
6992     Inst = TmpInst;
6993     return true;
6994   }
6995 
6996   case ARM::VLD2LNdAsm_8:
6997   case ARM::VLD2LNdAsm_16:
6998   case ARM::VLD2LNdAsm_32:
6999   case ARM::VLD2LNqAsm_16:
7000   case ARM::VLD2LNqAsm_32: {
7001     MCInst TmpInst;
7002     // Shuffle the operands around so the lane index operand is in the
7003     // right place.
7004     unsigned Spacing;
7005     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7006     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7007     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7008                                             Spacing));
7009     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7010     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7011     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7012     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7013                                             Spacing));
7014     TmpInst.addOperand(Inst.getOperand(1)); // lane
7015     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7016     TmpInst.addOperand(Inst.getOperand(5));
7017     Inst = TmpInst;
7018     return true;
7019   }
7020 
7021   case ARM::VLD3LNdAsm_8:
7022   case ARM::VLD3LNdAsm_16:
7023   case ARM::VLD3LNdAsm_32:
7024   case ARM::VLD3LNqAsm_16:
7025   case ARM::VLD3LNqAsm_32: {
7026     MCInst TmpInst;
7027     // Shuffle the operands around so the lane index operand is in the
7028     // right place.
7029     unsigned Spacing;
7030     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7031     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7032     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7033                                             Spacing));
7034     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7035                                             Spacing * 2));
7036     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7037     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7038     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7039     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7040                                             Spacing));
7041     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7042                                             Spacing * 2));
7043     TmpInst.addOperand(Inst.getOperand(1)); // lane
7044     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7045     TmpInst.addOperand(Inst.getOperand(5));
7046     Inst = TmpInst;
7047     return true;
7048   }
7049 
7050   case ARM::VLD4LNdAsm_8:
7051   case ARM::VLD4LNdAsm_16:
7052   case ARM::VLD4LNdAsm_32:
7053   case ARM::VLD4LNqAsm_16:
7054   case ARM::VLD4LNqAsm_32: {
7055     MCInst TmpInst;
7056     // Shuffle the operands around so the lane index operand is in the
7057     // right place.
7058     unsigned Spacing;
7059     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7060     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7061     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7062                                             Spacing));
7063     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7064                                             Spacing * 2));
7065     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7066                                             Spacing * 3));
7067     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7068     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7069     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7070     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7071                                             Spacing));
7072     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7073                                             Spacing * 2));
7074     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7075                                             Spacing * 3));
7076     TmpInst.addOperand(Inst.getOperand(1)); // lane
7077     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7078     TmpInst.addOperand(Inst.getOperand(5));
7079     Inst = TmpInst;
7080     return true;
7081   }
7082 
7083   // VLD3DUP single 3-element structure to all lanes instructions.
7084   case ARM::VLD3DUPdAsm_8:
7085   case ARM::VLD3DUPdAsm_16:
7086   case ARM::VLD3DUPdAsm_32:
7087   case ARM::VLD3DUPqAsm_8:
7088   case ARM::VLD3DUPqAsm_16:
7089   case ARM::VLD3DUPqAsm_32: {
7090     MCInst TmpInst;
7091     unsigned Spacing;
7092     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7093     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7094     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7095                                             Spacing));
7096     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7097                                             Spacing * 2));
7098     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7099     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7100     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7101     TmpInst.addOperand(Inst.getOperand(4));
7102     Inst = TmpInst;
7103     return true;
7104   }
7105 
7106   case ARM::VLD3DUPdWB_fixed_Asm_8:
7107   case ARM::VLD3DUPdWB_fixed_Asm_16:
7108   case ARM::VLD3DUPdWB_fixed_Asm_32:
7109   case ARM::VLD3DUPqWB_fixed_Asm_8:
7110   case ARM::VLD3DUPqWB_fixed_Asm_16:
7111   case ARM::VLD3DUPqWB_fixed_Asm_32: {
7112     MCInst TmpInst;
7113     unsigned Spacing;
7114     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7115     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7116     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7117                                             Spacing));
7118     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7119                                             Spacing * 2));
7120     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7121     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7122     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7123     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7124     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7125     TmpInst.addOperand(Inst.getOperand(4));
7126     Inst = TmpInst;
7127     return true;
7128   }
7129 
7130   case ARM::VLD3DUPdWB_register_Asm_8:
7131   case ARM::VLD3DUPdWB_register_Asm_16:
7132   case ARM::VLD3DUPdWB_register_Asm_32:
7133   case ARM::VLD3DUPqWB_register_Asm_8:
7134   case ARM::VLD3DUPqWB_register_Asm_16:
7135   case ARM::VLD3DUPqWB_register_Asm_32: {
7136     MCInst TmpInst;
7137     unsigned Spacing;
7138     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7139     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7140     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7141                                             Spacing));
7142     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7143                                             Spacing * 2));
7144     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7145     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7146     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7147     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7148     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7149     TmpInst.addOperand(Inst.getOperand(5));
7150     Inst = TmpInst;
7151     return true;
7152   }
7153 
7154   // VLD3 multiple 3-element structure instructions.
7155   case ARM::VLD3dAsm_8:
7156   case ARM::VLD3dAsm_16:
7157   case ARM::VLD3dAsm_32:
7158   case ARM::VLD3qAsm_8:
7159   case ARM::VLD3qAsm_16:
7160   case ARM::VLD3qAsm_32: {
7161     MCInst TmpInst;
7162     unsigned Spacing;
7163     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7164     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7165     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7166                                             Spacing));
7167     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7168                                             Spacing * 2));
7169     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7170     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7171     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7172     TmpInst.addOperand(Inst.getOperand(4));
7173     Inst = TmpInst;
7174     return true;
7175   }
7176 
7177   case ARM::VLD3dWB_fixed_Asm_8:
7178   case ARM::VLD3dWB_fixed_Asm_16:
7179   case ARM::VLD3dWB_fixed_Asm_32:
7180   case ARM::VLD3qWB_fixed_Asm_8:
7181   case ARM::VLD3qWB_fixed_Asm_16:
7182   case ARM::VLD3qWB_fixed_Asm_32: {
7183     MCInst TmpInst;
7184     unsigned Spacing;
7185     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7186     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7187     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7188                                             Spacing));
7189     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7190                                             Spacing * 2));
7191     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7192     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7193     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7194     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7195     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7196     TmpInst.addOperand(Inst.getOperand(4));
7197     Inst = TmpInst;
7198     return true;
7199   }
7200 
7201   case ARM::VLD3dWB_register_Asm_8:
7202   case ARM::VLD3dWB_register_Asm_16:
7203   case ARM::VLD3dWB_register_Asm_32:
7204   case ARM::VLD3qWB_register_Asm_8:
7205   case ARM::VLD3qWB_register_Asm_16:
7206   case ARM::VLD3qWB_register_Asm_32: {
7207     MCInst TmpInst;
7208     unsigned Spacing;
7209     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7210     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7211     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7212                                             Spacing));
7213     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7214                                             Spacing * 2));
7215     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7216     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7217     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7218     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7219     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7220     TmpInst.addOperand(Inst.getOperand(5));
7221     Inst = TmpInst;
7222     return true;
7223   }
7224 
7225   // VLD4DUP single 3-element structure to all lanes instructions.
7226   case ARM::VLD4DUPdAsm_8:
7227   case ARM::VLD4DUPdAsm_16:
7228   case ARM::VLD4DUPdAsm_32:
7229   case ARM::VLD4DUPqAsm_8:
7230   case ARM::VLD4DUPqAsm_16:
7231   case ARM::VLD4DUPqAsm_32: {
7232     MCInst TmpInst;
7233     unsigned Spacing;
7234     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7235     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7236     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7237                                             Spacing));
7238     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7239                                             Spacing * 2));
7240     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7241                                             Spacing * 3));
7242     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7243     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7244     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7245     TmpInst.addOperand(Inst.getOperand(4));
7246     Inst = TmpInst;
7247     return true;
7248   }
7249 
7250   case ARM::VLD4DUPdWB_fixed_Asm_8:
7251   case ARM::VLD4DUPdWB_fixed_Asm_16:
7252   case ARM::VLD4DUPdWB_fixed_Asm_32:
7253   case ARM::VLD4DUPqWB_fixed_Asm_8:
7254   case ARM::VLD4DUPqWB_fixed_Asm_16:
7255   case ARM::VLD4DUPqWB_fixed_Asm_32: {
7256     MCInst TmpInst;
7257     unsigned Spacing;
7258     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7259     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7260     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7261                                             Spacing));
7262     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7263                                             Spacing * 2));
7264     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7265                                             Spacing * 3));
7266     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7267     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7268     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7269     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7270     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7271     TmpInst.addOperand(Inst.getOperand(4));
7272     Inst = TmpInst;
7273     return true;
7274   }
7275 
7276   case ARM::VLD4DUPdWB_register_Asm_8:
7277   case ARM::VLD4DUPdWB_register_Asm_16:
7278   case ARM::VLD4DUPdWB_register_Asm_32:
7279   case ARM::VLD4DUPqWB_register_Asm_8:
7280   case ARM::VLD4DUPqWB_register_Asm_16:
7281   case ARM::VLD4DUPqWB_register_Asm_32: {
7282     MCInst TmpInst;
7283     unsigned Spacing;
7284     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7285     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7286     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7287                                             Spacing));
7288     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7289                                             Spacing * 2));
7290     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7291                                             Spacing * 3));
7292     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7293     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7294     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7295     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7296     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7297     TmpInst.addOperand(Inst.getOperand(5));
7298     Inst = TmpInst;
7299     return true;
7300   }
7301 
7302   // VLD4 multiple 4-element structure instructions.
7303   case ARM::VLD4dAsm_8:
7304   case ARM::VLD4dAsm_16:
7305   case ARM::VLD4dAsm_32:
7306   case ARM::VLD4qAsm_8:
7307   case ARM::VLD4qAsm_16:
7308   case ARM::VLD4qAsm_32: {
7309     MCInst TmpInst;
7310     unsigned Spacing;
7311     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7312     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7313     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7314                                             Spacing));
7315     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7316                                             Spacing * 2));
7317     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7318                                             Spacing * 3));
7319     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7320     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7321     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7322     TmpInst.addOperand(Inst.getOperand(4));
7323     Inst = TmpInst;
7324     return true;
7325   }
7326 
7327   case ARM::VLD4dWB_fixed_Asm_8:
7328   case ARM::VLD4dWB_fixed_Asm_16:
7329   case ARM::VLD4dWB_fixed_Asm_32:
7330   case ARM::VLD4qWB_fixed_Asm_8:
7331   case ARM::VLD4qWB_fixed_Asm_16:
7332   case ARM::VLD4qWB_fixed_Asm_32: {
7333     MCInst TmpInst;
7334     unsigned Spacing;
7335     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7336     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7337     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7338                                             Spacing));
7339     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7340                                             Spacing * 2));
7341     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7342                                             Spacing * 3));
7343     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7344     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7345     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7346     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7347     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7348     TmpInst.addOperand(Inst.getOperand(4));
7349     Inst = TmpInst;
7350     return true;
7351   }
7352 
7353   case ARM::VLD4dWB_register_Asm_8:
7354   case ARM::VLD4dWB_register_Asm_16:
7355   case ARM::VLD4dWB_register_Asm_32:
7356   case ARM::VLD4qWB_register_Asm_8:
7357   case ARM::VLD4qWB_register_Asm_16:
7358   case ARM::VLD4qWB_register_Asm_32: {
7359     MCInst TmpInst;
7360     unsigned Spacing;
7361     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7362     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7363     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7364                                             Spacing));
7365     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7366                                             Spacing * 2));
7367     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7368                                             Spacing * 3));
7369     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7370     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7371     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7372     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7373     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7374     TmpInst.addOperand(Inst.getOperand(5));
7375     Inst = TmpInst;
7376     return true;
7377   }
7378 
7379   // VST3 multiple 3-element structure instructions.
7380   case ARM::VST3dAsm_8:
7381   case ARM::VST3dAsm_16:
7382   case ARM::VST3dAsm_32:
7383   case ARM::VST3qAsm_8:
7384   case ARM::VST3qAsm_16:
7385   case ARM::VST3qAsm_32: {
7386     MCInst TmpInst;
7387     unsigned Spacing;
7388     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7389     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7390     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7391     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7392     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7393                                             Spacing));
7394     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7395                                             Spacing * 2));
7396     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7397     TmpInst.addOperand(Inst.getOperand(4));
7398     Inst = TmpInst;
7399     return true;
7400   }
7401 
7402   case ARM::VST3dWB_fixed_Asm_8:
7403   case ARM::VST3dWB_fixed_Asm_16:
7404   case ARM::VST3dWB_fixed_Asm_32:
7405   case ARM::VST3qWB_fixed_Asm_8:
7406   case ARM::VST3qWB_fixed_Asm_16:
7407   case ARM::VST3qWB_fixed_Asm_32: {
7408     MCInst TmpInst;
7409     unsigned Spacing;
7410     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7411     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7412     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7413     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7414     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7415     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7416     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7417                                             Spacing));
7418     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7419                                             Spacing * 2));
7420     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7421     TmpInst.addOperand(Inst.getOperand(4));
7422     Inst = TmpInst;
7423     return true;
7424   }
7425 
7426   case ARM::VST3dWB_register_Asm_8:
7427   case ARM::VST3dWB_register_Asm_16:
7428   case ARM::VST3dWB_register_Asm_32:
7429   case ARM::VST3qWB_register_Asm_8:
7430   case ARM::VST3qWB_register_Asm_16:
7431   case ARM::VST3qWB_register_Asm_32: {
7432     MCInst TmpInst;
7433     unsigned Spacing;
7434     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7435     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7436     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7437     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7438     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7439     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7440     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7441                                             Spacing));
7442     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7443                                             Spacing * 2));
7444     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7445     TmpInst.addOperand(Inst.getOperand(5));
7446     Inst = TmpInst;
7447     return true;
7448   }
7449 
7450   // VST4 multiple 3-element structure instructions.
7451   case ARM::VST4dAsm_8:
7452   case ARM::VST4dAsm_16:
7453   case ARM::VST4dAsm_32:
7454   case ARM::VST4qAsm_8:
7455   case ARM::VST4qAsm_16:
7456   case ARM::VST4qAsm_32: {
7457     MCInst TmpInst;
7458     unsigned Spacing;
7459     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7460     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7461     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7462     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7463     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7464                                             Spacing));
7465     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7466                                             Spacing * 2));
7467     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7468                                             Spacing * 3));
7469     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7470     TmpInst.addOperand(Inst.getOperand(4));
7471     Inst = TmpInst;
7472     return true;
7473   }
7474 
7475   case ARM::VST4dWB_fixed_Asm_8:
7476   case ARM::VST4dWB_fixed_Asm_16:
7477   case ARM::VST4dWB_fixed_Asm_32:
7478   case ARM::VST4qWB_fixed_Asm_8:
7479   case ARM::VST4qWB_fixed_Asm_16:
7480   case ARM::VST4qWB_fixed_Asm_32: {
7481     MCInst TmpInst;
7482     unsigned Spacing;
7483     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7484     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7485     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7486     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7487     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7488     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7489     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7490                                             Spacing));
7491     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7492                                             Spacing * 2));
7493     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7494                                             Spacing * 3));
7495     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7496     TmpInst.addOperand(Inst.getOperand(4));
7497     Inst = TmpInst;
7498     return true;
7499   }
7500 
7501   case ARM::VST4dWB_register_Asm_8:
7502   case ARM::VST4dWB_register_Asm_16:
7503   case ARM::VST4dWB_register_Asm_32:
7504   case ARM::VST4qWB_register_Asm_8:
7505   case ARM::VST4qWB_register_Asm_16:
7506   case ARM::VST4qWB_register_Asm_32: {
7507     MCInst TmpInst;
7508     unsigned Spacing;
7509     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7510     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7511     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7512     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7513     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7514     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7515     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7516                                             Spacing));
7517     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7518                                             Spacing * 2));
7519     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7520                                             Spacing * 3));
7521     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7522     TmpInst.addOperand(Inst.getOperand(5));
7523     Inst = TmpInst;
7524     return true;
7525   }
7526 
7527   // Handle encoding choice for the shift-immediate instructions.
7528   case ARM::t2LSLri:
7529   case ARM::t2LSRri:
7530   case ARM::t2ASRri: {
7531     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7532         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7533         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7534         !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7535           static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7536       unsigned NewOpc;
7537       switch (Inst.getOpcode()) {
7538       default: llvm_unreachable("unexpected opcode");
7539       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7540       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7541       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7542       }
7543       // The Thumb1 operands aren't in the same order. Awesome, eh?
7544       MCInst TmpInst;
7545       TmpInst.setOpcode(NewOpc);
7546       TmpInst.addOperand(Inst.getOperand(0));
7547       TmpInst.addOperand(Inst.getOperand(5));
7548       TmpInst.addOperand(Inst.getOperand(1));
7549       TmpInst.addOperand(Inst.getOperand(2));
7550       TmpInst.addOperand(Inst.getOperand(3));
7551       TmpInst.addOperand(Inst.getOperand(4));
7552       Inst = TmpInst;
7553       return true;
7554     }
7555     return false;
7556   }
7557 
7558   // Handle the Thumb2 mode MOV complex aliases.
7559   case ARM::t2MOVsr:
7560   case ARM::t2MOVSsr: {
7561     // Which instruction to expand to depends on the CCOut operand and
7562     // whether we're in an IT block if the register operands are low
7563     // registers.
7564     bool isNarrow = false;
7565     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7566         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7567         isARMLowRegister(Inst.getOperand(2).getReg()) &&
7568         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7569         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7570       isNarrow = true;
7571     MCInst TmpInst;
7572     unsigned newOpc;
7573     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7574     default: llvm_unreachable("unexpected opcode!");
7575     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7576     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7577     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7578     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7579     }
7580     TmpInst.setOpcode(newOpc);
7581     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7582     if (isNarrow)
7583       TmpInst.addOperand(MCOperand::CreateReg(
7584           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7585     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7586     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7587     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7588     TmpInst.addOperand(Inst.getOperand(5));
7589     if (!isNarrow)
7590       TmpInst.addOperand(MCOperand::CreateReg(
7591           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7592     Inst = TmpInst;
7593     return true;
7594   }
7595   case ARM::t2MOVsi:
7596   case ARM::t2MOVSsi: {
7597     // Which instruction to expand to depends on the CCOut operand and
7598     // whether we're in an IT block if the register operands are low
7599     // registers.
7600     bool isNarrow = false;
7601     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7602         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7603         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7604       isNarrow = true;
7605     MCInst TmpInst;
7606     unsigned newOpc;
7607     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7608     default: llvm_unreachable("unexpected opcode!");
7609     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7610     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7611     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7612     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7613     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7614     }
7615     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7616     if (Amount == 32) Amount = 0;
7617     TmpInst.setOpcode(newOpc);
7618     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7619     if (isNarrow)
7620       TmpInst.addOperand(MCOperand::CreateReg(
7621           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7622     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7623     if (newOpc != ARM::t2RRX)
7624       TmpInst.addOperand(MCOperand::CreateImm(Amount));
7625     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7626     TmpInst.addOperand(Inst.getOperand(4));
7627     if (!isNarrow)
7628       TmpInst.addOperand(MCOperand::CreateReg(
7629           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7630     Inst = TmpInst;
7631     return true;
7632   }
7633   // Handle the ARM mode MOV complex aliases.
7634   case ARM::ASRr:
7635   case ARM::LSRr:
7636   case ARM::LSLr:
7637   case ARM::RORr: {
7638     ARM_AM::ShiftOpc ShiftTy;
7639     switch(Inst.getOpcode()) {
7640     default: llvm_unreachable("unexpected opcode!");
7641     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7642     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7643     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7644     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7645     }
7646     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7647     MCInst TmpInst;
7648     TmpInst.setOpcode(ARM::MOVsr);
7649     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7650     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7651     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7652     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7653     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7654     TmpInst.addOperand(Inst.getOperand(4));
7655     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7656     Inst = TmpInst;
7657     return true;
7658   }
7659   case ARM::ASRi:
7660   case ARM::LSRi:
7661   case ARM::LSLi:
7662   case ARM::RORi: {
7663     ARM_AM::ShiftOpc ShiftTy;
7664     switch(Inst.getOpcode()) {
7665     default: llvm_unreachable("unexpected opcode!");
7666     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7667     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7668     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7669     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7670     }
7671     // A shift by zero is a plain MOVr, not a MOVsi.
7672     unsigned Amt = Inst.getOperand(2).getImm();
7673     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7674     // A shift by 32 should be encoded as 0 when permitted
7675     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7676       Amt = 0;
7677     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7678     MCInst TmpInst;
7679     TmpInst.setOpcode(Opc);
7680     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7681     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7682     if (Opc == ARM::MOVsi)
7683       TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7684     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7685     TmpInst.addOperand(Inst.getOperand(4));
7686     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7687     Inst = TmpInst;
7688     return true;
7689   }
7690   case ARM::RRXi: {
7691     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7692     MCInst TmpInst;
7693     TmpInst.setOpcode(ARM::MOVsi);
7694     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7695     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7696     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7697     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7698     TmpInst.addOperand(Inst.getOperand(3));
7699     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7700     Inst = TmpInst;
7701     return true;
7702   }
7703   case ARM::t2LDMIA_UPD: {
7704     // If this is a load of a single register, then we should use
7705     // a post-indexed LDR instruction instead, per the ARM ARM.
7706     if (Inst.getNumOperands() != 5)
7707       return false;
7708     MCInst TmpInst;
7709     TmpInst.setOpcode(ARM::t2LDR_POST);
7710     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7711     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7712     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7713     TmpInst.addOperand(MCOperand::CreateImm(4));
7714     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7715     TmpInst.addOperand(Inst.getOperand(3));
7716     Inst = TmpInst;
7717     return true;
7718   }
7719   case ARM::t2STMDB_UPD: {
7720     // If this is a store of a single register, then we should use
7721     // a pre-indexed STR instruction instead, per the ARM ARM.
7722     if (Inst.getNumOperands() != 5)
7723       return false;
7724     MCInst TmpInst;
7725     TmpInst.setOpcode(ARM::t2STR_PRE);
7726     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7727     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7728     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7729     TmpInst.addOperand(MCOperand::CreateImm(-4));
7730     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7731     TmpInst.addOperand(Inst.getOperand(3));
7732     Inst = TmpInst;
7733     return true;
7734   }
7735   case ARM::LDMIA_UPD:
7736     // If this is a load of a single register via a 'pop', then we should use
7737     // a post-indexed LDR instruction instead, per the ARM ARM.
7738     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
7739         Inst.getNumOperands() == 5) {
7740       MCInst TmpInst;
7741       TmpInst.setOpcode(ARM::LDR_POST_IMM);
7742       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7743       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7744       TmpInst.addOperand(Inst.getOperand(1)); // Rn
7745       TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7746       TmpInst.addOperand(MCOperand::CreateImm(4));
7747       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7748       TmpInst.addOperand(Inst.getOperand(3));
7749       Inst = TmpInst;
7750       return true;
7751     }
7752     break;
7753   case ARM::STMDB_UPD:
7754     // If this is a store of a single register via a 'push', then we should use
7755     // a pre-indexed STR instruction instead, per the ARM ARM.
7756     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
7757         Inst.getNumOperands() == 5) {
7758       MCInst TmpInst;
7759       TmpInst.setOpcode(ARM::STR_PRE_IMM);
7760       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7761       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7762       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7763       TmpInst.addOperand(MCOperand::CreateImm(-4));
7764       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7765       TmpInst.addOperand(Inst.getOperand(3));
7766       Inst = TmpInst;
7767     }
7768     break;
7769   case ARM::t2ADDri12:
7770     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7771     // mnemonic was used (not "addw"), encoding T3 is preferred.
7772     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
7773         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7774       break;
7775     Inst.setOpcode(ARM::t2ADDri);
7776     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7777     break;
7778   case ARM::t2SUBri12:
7779     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7780     // mnemonic was used (not "subw"), encoding T3 is preferred.
7781     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
7782         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7783       break;
7784     Inst.setOpcode(ARM::t2SUBri);
7785     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7786     break;
7787   case ARM::tADDi8:
7788     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7789     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7790     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7791     // to encoding T1 if <Rd> is omitted."
7792     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7793       Inst.setOpcode(ARM::tADDi3);
7794       return true;
7795     }
7796     break;
7797   case ARM::tSUBi8:
7798     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7799     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7800     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7801     // to encoding T1 if <Rd> is omitted."
7802     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7803       Inst.setOpcode(ARM::tSUBi3);
7804       return true;
7805     }
7806     break;
7807   case ARM::t2ADDri:
7808   case ARM::t2SUBri: {
7809     // If the destination and first source operand are the same, and
7810     // the flags are compatible with the current IT status, use encoding T2
7811     // instead of T3. For compatibility with the system 'as'. Make sure the
7812     // wide encoding wasn't explicit.
7813     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7814         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7815         (unsigned)Inst.getOperand(2).getImm() > 255 ||
7816         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7817          (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7818         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7819          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7820       break;
7821     MCInst TmpInst;
7822     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7823                       ARM::tADDi8 : ARM::tSUBi8);
7824     TmpInst.addOperand(Inst.getOperand(0));
7825     TmpInst.addOperand(Inst.getOperand(5));
7826     TmpInst.addOperand(Inst.getOperand(0));
7827     TmpInst.addOperand(Inst.getOperand(2));
7828     TmpInst.addOperand(Inst.getOperand(3));
7829     TmpInst.addOperand(Inst.getOperand(4));
7830     Inst = TmpInst;
7831     return true;
7832   }
7833   case ARM::t2ADDrr: {
7834     // If the destination and first source operand are the same, and
7835     // there's no setting of the flags, use encoding T2 instead of T3.
7836     // Note that this is only for ADD, not SUB. This mirrors the system
7837     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7838     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7839         Inst.getOperand(5).getReg() != 0 ||
7840         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7841          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7842       break;
7843     MCInst TmpInst;
7844     TmpInst.setOpcode(ARM::tADDhirr);
7845     TmpInst.addOperand(Inst.getOperand(0));
7846     TmpInst.addOperand(Inst.getOperand(0));
7847     TmpInst.addOperand(Inst.getOperand(2));
7848     TmpInst.addOperand(Inst.getOperand(3));
7849     TmpInst.addOperand(Inst.getOperand(4));
7850     Inst = TmpInst;
7851     return true;
7852   }
7853   case ARM::tADDrSP: {
7854     // If the non-SP source operand and the destination operand are not the
7855     // same, we need to use the 32-bit encoding if it's available.
7856     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7857       Inst.setOpcode(ARM::t2ADDrr);
7858       Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7859       return true;
7860     }
7861     break;
7862   }
7863   case ARM::tB:
7864     // A Thumb conditional branch outside of an IT block is a tBcc.
7865     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7866       Inst.setOpcode(ARM::tBcc);
7867       return true;
7868     }
7869     break;
7870   case ARM::t2B:
7871     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7872     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7873       Inst.setOpcode(ARM::t2Bcc);
7874       return true;
7875     }
7876     break;
7877   case ARM::t2Bcc:
7878     // If the conditional is AL or we're in an IT block, we really want t2B.
7879     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7880       Inst.setOpcode(ARM::t2B);
7881       return true;
7882     }
7883     break;
7884   case ARM::tBcc:
7885     // If the conditional is AL, we really want tB.
7886     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7887       Inst.setOpcode(ARM::tB);
7888       return true;
7889     }
7890     break;
7891   case ARM::tLDMIA: {
7892     // If the register list contains any high registers, or if the writeback
7893     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7894     // instead if we're in Thumb2. Otherwise, this should have generated
7895     // an error in validateInstruction().
7896     unsigned Rn = Inst.getOperand(0).getReg();
7897     bool hasWritebackToken =
7898         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7899          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7900     bool listContainsBase;
7901     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7902         (!listContainsBase && !hasWritebackToken) ||
7903         (listContainsBase && hasWritebackToken)) {
7904       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7905       assert (isThumbTwo());
7906       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7907       // If we're switching to the updating version, we need to insert
7908       // the writeback tied operand.
7909       if (hasWritebackToken)
7910         Inst.insert(Inst.begin(),
7911                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7912       return true;
7913     }
7914     break;
7915   }
7916   case ARM::tSTMIA_UPD: {
7917     // If the register list contains any high registers, we need to use
7918     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7919     // should have generated an error in validateInstruction().
7920     unsigned Rn = Inst.getOperand(0).getReg();
7921     bool listContainsBase;
7922     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7923       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7924       assert (isThumbTwo());
7925       Inst.setOpcode(ARM::t2STMIA_UPD);
7926       return true;
7927     }
7928     break;
7929   }
7930   case ARM::tPOP: {
7931     bool listContainsBase;
7932     // If the register list contains any high registers, we need to use
7933     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7934     // should have generated an error in validateInstruction().
7935     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7936       return false;
7937     assert (isThumbTwo());
7938     Inst.setOpcode(ARM::t2LDMIA_UPD);
7939     // Add the base register and writeback operands.
7940     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7941     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7942     return true;
7943   }
7944   case ARM::tPUSH: {
7945     bool listContainsBase;
7946     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7947       return false;
7948     assert (isThumbTwo());
7949     Inst.setOpcode(ARM::t2STMDB_UPD);
7950     // Add the base register and writeback operands.
7951     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7952     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7953     return true;
7954   }
7955   case ARM::t2MOVi: {
7956     // If we can use the 16-bit encoding and the user didn't explicitly
7957     // request the 32-bit variant, transform it here.
7958     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7959         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7960         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7961           Inst.getOperand(4).getReg() == ARM::CPSR) ||
7962          (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7963         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7964          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7965       // The operands aren't in the same order for tMOVi8...
7966       MCInst TmpInst;
7967       TmpInst.setOpcode(ARM::tMOVi8);
7968       TmpInst.addOperand(Inst.getOperand(0));
7969       TmpInst.addOperand(Inst.getOperand(4));
7970       TmpInst.addOperand(Inst.getOperand(1));
7971       TmpInst.addOperand(Inst.getOperand(2));
7972       TmpInst.addOperand(Inst.getOperand(3));
7973       Inst = TmpInst;
7974       return true;
7975     }
7976     break;
7977   }
7978   case ARM::t2MOVr: {
7979     // If we can use the 16-bit encoding and the user didn't explicitly
7980     // request the 32-bit variant, transform it here.
7981     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7982         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7983         Inst.getOperand(2).getImm() == ARMCC::AL &&
7984         Inst.getOperand(4).getReg() == ARM::CPSR &&
7985         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7986          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7987       // The operands aren't the same for tMOV[S]r... (no cc_out)
7988       MCInst TmpInst;
7989       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7990       TmpInst.addOperand(Inst.getOperand(0));
7991       TmpInst.addOperand(Inst.getOperand(1));
7992       TmpInst.addOperand(Inst.getOperand(2));
7993       TmpInst.addOperand(Inst.getOperand(3));
7994       Inst = TmpInst;
7995       return true;
7996     }
7997     break;
7998   }
7999   case ARM::t2SXTH:
8000   case ARM::t2SXTB:
8001   case ARM::t2UXTH:
8002   case ARM::t2UXTB: {
8003     // If we can use the 16-bit encoding and the user didn't explicitly
8004     // request the 32-bit variant, transform it here.
8005     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8006         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8007         Inst.getOperand(2).getImm() == 0 &&
8008         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8009          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8010       unsigned NewOpc;
8011       switch (Inst.getOpcode()) {
8012       default: llvm_unreachable("Illegal opcode!");
8013       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8014       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8015       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8016       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8017       }
8018       // The operands aren't the same for thumb1 (no rotate operand).
8019       MCInst TmpInst;
8020       TmpInst.setOpcode(NewOpc);
8021       TmpInst.addOperand(Inst.getOperand(0));
8022       TmpInst.addOperand(Inst.getOperand(1));
8023       TmpInst.addOperand(Inst.getOperand(3));
8024       TmpInst.addOperand(Inst.getOperand(4));
8025       Inst = TmpInst;
8026       return true;
8027     }
8028     break;
8029   }
8030   case ARM::MOVsi: {
8031     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8032     // rrx shifts and asr/lsr of #32 is encoded as 0
8033     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8034       return false;
8035     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8036       // Shifting by zero is accepted as a vanilla 'MOVr'
8037       MCInst TmpInst;
8038       TmpInst.setOpcode(ARM::MOVr);
8039       TmpInst.addOperand(Inst.getOperand(0));
8040       TmpInst.addOperand(Inst.getOperand(1));
8041       TmpInst.addOperand(Inst.getOperand(3));
8042       TmpInst.addOperand(Inst.getOperand(4));
8043       TmpInst.addOperand(Inst.getOperand(5));
8044       Inst = TmpInst;
8045       return true;
8046     }
8047     return false;
8048   }
8049   case ARM::ANDrsi:
8050   case ARM::ORRrsi:
8051   case ARM::EORrsi:
8052   case ARM::BICrsi:
8053   case ARM::SUBrsi:
8054   case ARM::ADDrsi: {
8055     unsigned newOpc;
8056     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8057     if (SOpc == ARM_AM::rrx) return false;
8058     switch (Inst.getOpcode()) {
8059     default: llvm_unreachable("unexpected opcode!");
8060     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8061     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8062     case ARM::EORrsi: newOpc = ARM::EORrr; break;
8063     case ARM::BICrsi: newOpc = ARM::BICrr; break;
8064     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8065     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8066     }
8067     // If the shift is by zero, use the non-shifted instruction definition.
8068     // The exception is for right shifts, where 0 == 32
8069     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8070         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8071       MCInst TmpInst;
8072       TmpInst.setOpcode(newOpc);
8073       TmpInst.addOperand(Inst.getOperand(0));
8074       TmpInst.addOperand(Inst.getOperand(1));
8075       TmpInst.addOperand(Inst.getOperand(2));
8076       TmpInst.addOperand(Inst.getOperand(4));
8077       TmpInst.addOperand(Inst.getOperand(5));
8078       TmpInst.addOperand(Inst.getOperand(6));
8079       Inst = TmpInst;
8080       return true;
8081     }
8082     return false;
8083   }
8084   case ARM::ITasm:
8085   case ARM::t2IT: {
8086     // The mask bits for all but the first condition are represented as
8087     // the low bit of the condition code value implies 't'. We currently
8088     // always have 1 implies 't', so XOR toggle the bits if the low bit
8089     // of the condition code is zero.
8090     MCOperand &MO = Inst.getOperand(1);
8091     unsigned Mask = MO.getImm();
8092     unsigned OrigMask = Mask;
8093     unsigned TZ = countTrailingZeros(Mask);
8094     if ((Inst.getOperand(0).getImm() & 1) == 0) {
8095       assert(Mask && TZ <= 3 && "illegal IT mask value!");
8096       Mask ^= (0xE << TZ) & 0xF;
8097     }
8098     MO.setImm(Mask);
8099 
8100     // Set up the IT block state according to the IT instruction we just
8101     // matched.
8102     assert(!inITBlock() && "nested IT blocks?!");
8103     ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8104     ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8105     ITState.CurPosition = 0;
8106     ITState.FirstCond = true;
8107     break;
8108   }
8109   case ARM::t2LSLrr:
8110   case ARM::t2LSRrr:
8111   case ARM::t2ASRrr:
8112   case ARM::t2SBCrr:
8113   case ARM::t2RORrr:
8114   case ARM::t2BICrr:
8115   {
8116     // Assemblers should use the narrow encodings of these instructions when permissible.
8117     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8118          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8119         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8120         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8121          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8122         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8123          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8124              ".w"))) {
8125       unsigned NewOpc;
8126       switch (Inst.getOpcode()) {
8127         default: llvm_unreachable("unexpected opcode");
8128         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8129         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8130         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8131         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8132         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8133         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8134       }
8135       MCInst TmpInst;
8136       TmpInst.setOpcode(NewOpc);
8137       TmpInst.addOperand(Inst.getOperand(0));
8138       TmpInst.addOperand(Inst.getOperand(5));
8139       TmpInst.addOperand(Inst.getOperand(1));
8140       TmpInst.addOperand(Inst.getOperand(2));
8141       TmpInst.addOperand(Inst.getOperand(3));
8142       TmpInst.addOperand(Inst.getOperand(4));
8143       Inst = TmpInst;
8144       return true;
8145     }
8146     return false;
8147   }
8148   case ARM::t2ANDrr:
8149   case ARM::t2EORrr:
8150   case ARM::t2ADCrr:
8151   case ARM::t2ORRrr:
8152   {
8153     // Assemblers should use the narrow encodings of these instructions when permissible.
8154     // These instructions are special in that they are commutable, so shorter encodings
8155     // are available more often.
8156     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8157          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8158         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8159          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8160         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8161          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8162         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8163          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8164              ".w"))) {
8165       unsigned NewOpc;
8166       switch (Inst.getOpcode()) {
8167         default: llvm_unreachable("unexpected opcode");
8168         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8169         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8170         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8171         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8172       }
8173       MCInst TmpInst;
8174       TmpInst.setOpcode(NewOpc);
8175       TmpInst.addOperand(Inst.getOperand(0));
8176       TmpInst.addOperand(Inst.getOperand(5));
8177       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8178         TmpInst.addOperand(Inst.getOperand(1));
8179         TmpInst.addOperand(Inst.getOperand(2));
8180       } else {
8181         TmpInst.addOperand(Inst.getOperand(2));
8182         TmpInst.addOperand(Inst.getOperand(1));
8183       }
8184       TmpInst.addOperand(Inst.getOperand(3));
8185       TmpInst.addOperand(Inst.getOperand(4));
8186       Inst = TmpInst;
8187       return true;
8188     }
8189     return false;
8190   }
8191   }
8192   return false;
8193 }
8194 
8195 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8196   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8197   // suffix depending on whether they're in an IT block or not.
8198   unsigned Opc = Inst.getOpcode();
8199   const MCInstrDesc &MCID = MII.get(Opc);
8200   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8201     assert(MCID.hasOptionalDef() &&
8202            "optionally flag setting instruction missing optional def operand");
8203     assert(MCID.NumOperands == Inst.getNumOperands() &&
8204            "operand count mismatch!");
8205     // Find the optional-def operand (cc_out).
8206     unsigned OpNo;
8207     for (OpNo = 0;
8208          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8209          ++OpNo)
8210       ;
8211     // If we're parsing Thumb1, reject it completely.
8212     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8213       return Match_MnemonicFail;
8214     // If we're parsing Thumb2, which form is legal depends on whether we're
8215     // in an IT block.
8216     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8217         !inITBlock())
8218       return Match_RequiresITBlock;
8219     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8220         inITBlock())
8221       return Match_RequiresNotITBlock;
8222   }
8223   // Some high-register supporting Thumb1 encodings only allow both registers
8224   // to be from r0-r7 when in Thumb2.
8225   else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
8226            isARMLowRegister(Inst.getOperand(1).getReg()) &&
8227            isARMLowRegister(Inst.getOperand(2).getReg()))
8228     return Match_RequiresThumb2;
8229   // Others only require ARMv6 or later.
8230   else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8231            isARMLowRegister(Inst.getOperand(0).getReg()) &&
8232            isARMLowRegister(Inst.getOperand(1).getReg()))
8233     return Match_RequiresV6;
8234   return Match_Success;
8235 }
8236 
8237 namespace llvm {
8238 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8239   return true; // In an assembly source, no need to second-guess
8240 }
8241 }
8242 
8243 static const char *getSubtargetFeatureName(uint64_t Val);
8244 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8245                                            OperandVector &Operands,
8246                                            MCStreamer &Out, uint64_t &ErrorInfo,
8247                                            bool MatchingInlineAsm) {
8248   MCInst Inst;
8249   unsigned MatchResult;
8250 
8251   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8252                                      MatchingInlineAsm);
8253   switch (MatchResult) {
8254   default: break;
8255   case Match_Success:
8256     // Context sensitive operand constraints aren't handled by the matcher,
8257     // so check them here.
8258     if (validateInstruction(Inst, Operands)) {
8259       // Still progress the IT block, otherwise one wrong condition causes
8260       // nasty cascading errors.
8261       forwardITPosition();
8262       return true;
8263     }
8264 
8265     { // processInstruction() updates inITBlock state, we need to save it away
8266       bool wasInITBlock = inITBlock();
8267 
8268       // Some instructions need post-processing to, for example, tweak which
8269       // encoding is selected. Loop on it while changes happen so the
8270       // individual transformations can chain off each other. E.g.,
8271       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8272       while (processInstruction(Inst, Operands))
8273         ;
8274 
8275       // Only after the instruction is fully processed, we can validate it
8276       if (wasInITBlock && hasV8Ops() && isThumb() &&
8277           !isV8EligibleForIT(&Inst)) {
8278         Warning(IDLoc, "deprecated instruction in IT block");
8279       }
8280     }
8281 
8282     // Only move forward at the very end so that everything in validate
8283     // and process gets a consistent answer about whether we're in an IT
8284     // block.
8285     forwardITPosition();
8286 
8287     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8288     // doesn't actually encode.
8289     if (Inst.getOpcode() == ARM::ITasm)
8290       return false;
8291 
8292     Inst.setLoc(IDLoc);
8293     Out.EmitInstruction(Inst, STI);
8294     return false;
8295   case Match_MissingFeature: {
8296     assert(ErrorInfo && "Unknown missing feature!");
8297     // Special case the error message for the very common case where only
8298     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8299     std::string Msg = "instruction requires:";
8300     uint64_t Mask = 1;
8301     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8302       if (ErrorInfo & Mask) {
8303         Msg += " ";
8304         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8305       }
8306       Mask <<= 1;
8307     }
8308     return Error(IDLoc, Msg);
8309   }
8310   case Match_InvalidOperand: {
8311     SMLoc ErrorLoc = IDLoc;
8312     if (ErrorInfo != ~0ULL) {
8313       if (ErrorInfo >= Operands.size())
8314         return Error(IDLoc, "too few operands for instruction");
8315 
8316       ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8317       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8318     }
8319 
8320     return Error(ErrorLoc, "invalid operand for instruction");
8321   }
8322   case Match_MnemonicFail:
8323     return Error(IDLoc, "invalid instruction",
8324                  ((ARMOperand &)*Operands[0]).getLocRange());
8325   case Match_RequiresNotITBlock:
8326     return Error(IDLoc, "flag setting instruction only valid outside IT block");
8327   case Match_RequiresITBlock:
8328     return Error(IDLoc, "instruction only valid inside IT block");
8329   case Match_RequiresV6:
8330     return Error(IDLoc, "instruction variant requires ARMv6 or later");
8331   case Match_RequiresThumb2:
8332     return Error(IDLoc, "instruction variant requires Thumb2");
8333   case Match_ImmRange0_15: {
8334     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8335     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8336     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8337   }
8338   case Match_ImmRange0_239: {
8339     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8340     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8341     return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8342   }
8343   case Match_AlignedMemoryRequiresNone:
8344   case Match_DupAlignedMemoryRequiresNone:
8345   case Match_AlignedMemoryRequires16:
8346   case Match_DupAlignedMemoryRequires16:
8347   case Match_AlignedMemoryRequires32:
8348   case Match_DupAlignedMemoryRequires32:
8349   case Match_AlignedMemoryRequires64:
8350   case Match_DupAlignedMemoryRequires64:
8351   case Match_AlignedMemoryRequires64or128:
8352   case Match_DupAlignedMemoryRequires64or128:
8353   case Match_AlignedMemoryRequires64or128or256:
8354   {
8355     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8356     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8357     switch (MatchResult) {
8358       default:
8359         llvm_unreachable("Missing Match_Aligned type");
8360       case Match_AlignedMemoryRequiresNone:
8361       case Match_DupAlignedMemoryRequiresNone:
8362         return Error(ErrorLoc, "alignment must be omitted");
8363       case Match_AlignedMemoryRequires16:
8364       case Match_DupAlignedMemoryRequires16:
8365         return Error(ErrorLoc, "alignment must be 16 or omitted");
8366       case Match_AlignedMemoryRequires32:
8367       case Match_DupAlignedMemoryRequires32:
8368         return Error(ErrorLoc, "alignment must be 32 or omitted");
8369       case Match_AlignedMemoryRequires64:
8370       case Match_DupAlignedMemoryRequires64:
8371         return Error(ErrorLoc, "alignment must be 64 or omitted");
8372       case Match_AlignedMemoryRequires64or128:
8373       case Match_DupAlignedMemoryRequires64or128:
8374         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8375       case Match_AlignedMemoryRequires64or128or256:
8376         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8377     }
8378   }
8379   }
8380 
8381   llvm_unreachable("Implement any new match types added!");
8382 }
8383 
8384 /// parseDirective parses the arm specific directives
8385 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8386   const MCObjectFileInfo::Environment Format =
8387     getContext().getObjectFileInfo()->getObjectFileType();
8388   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8389   bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8390 
8391   StringRef IDVal = DirectiveID.getIdentifier();
8392   if (IDVal == ".word")
8393     return parseLiteralValues(4, DirectiveID.getLoc());
8394   else if (IDVal == ".short" || IDVal == ".hword")
8395     return parseLiteralValues(2, DirectiveID.getLoc());
8396   else if (IDVal == ".thumb")
8397     return parseDirectiveThumb(DirectiveID.getLoc());
8398   else if (IDVal == ".arm")
8399     return parseDirectiveARM(DirectiveID.getLoc());
8400   else if (IDVal == ".thumb_func")
8401     return parseDirectiveThumbFunc(DirectiveID.getLoc());
8402   else if (IDVal == ".code")
8403     return parseDirectiveCode(DirectiveID.getLoc());
8404   else if (IDVal == ".syntax")
8405     return parseDirectiveSyntax(DirectiveID.getLoc());
8406   else if (IDVal == ".unreq")
8407     return parseDirectiveUnreq(DirectiveID.getLoc());
8408   else if (IDVal == ".fnend")
8409     return parseDirectiveFnEnd(DirectiveID.getLoc());
8410   else if (IDVal == ".cantunwind")
8411     return parseDirectiveCantUnwind(DirectiveID.getLoc());
8412   else if (IDVal == ".personality")
8413     return parseDirectivePersonality(DirectiveID.getLoc());
8414   else if (IDVal == ".handlerdata")
8415     return parseDirectiveHandlerData(DirectiveID.getLoc());
8416   else if (IDVal == ".setfp")
8417     return parseDirectiveSetFP(DirectiveID.getLoc());
8418   else if (IDVal == ".pad")
8419     return parseDirectivePad(DirectiveID.getLoc());
8420   else if (IDVal == ".save")
8421     return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8422   else if (IDVal == ".vsave")
8423     return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8424   else if (IDVal == ".ltorg" || IDVal == ".pool")
8425     return parseDirectiveLtorg(DirectiveID.getLoc());
8426   else if (IDVal == ".even")
8427     return parseDirectiveEven(DirectiveID.getLoc());
8428   else if (IDVal == ".personalityindex")
8429     return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8430   else if (IDVal == ".unwind_raw")
8431     return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8432   else if (IDVal == ".movsp")
8433     return parseDirectiveMovSP(DirectiveID.getLoc());
8434   else if (IDVal == ".arch_extension")
8435     return parseDirectiveArchExtension(DirectiveID.getLoc());
8436   else if (IDVal == ".align")
8437     return parseDirectiveAlign(DirectiveID.getLoc());
8438   else if (IDVal == ".thumb_set")
8439     return parseDirectiveThumbSet(DirectiveID.getLoc());
8440 
8441   if (!IsMachO && !IsCOFF) {
8442     if (IDVal == ".arch")
8443       return parseDirectiveArch(DirectiveID.getLoc());
8444     else if (IDVal == ".cpu")
8445       return parseDirectiveCPU(DirectiveID.getLoc());
8446     else if (IDVal == ".eabi_attribute")
8447       return parseDirectiveEabiAttr(DirectiveID.getLoc());
8448     else if (IDVal == ".fpu")
8449       return parseDirectiveFPU(DirectiveID.getLoc());
8450     else if (IDVal == ".fnstart")
8451       return parseDirectiveFnStart(DirectiveID.getLoc());
8452     else if (IDVal == ".inst")
8453       return parseDirectiveInst(DirectiveID.getLoc());
8454     else if (IDVal == ".inst.n")
8455       return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8456     else if (IDVal == ".inst.w")
8457       return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8458     else if (IDVal == ".object_arch")
8459       return parseDirectiveObjectArch(DirectiveID.getLoc());
8460     else if (IDVal == ".tlsdescseq")
8461       return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8462   }
8463 
8464   return true;
8465 }
8466 
8467 /// parseLiteralValues
8468 ///  ::= .hword expression [, expression]*
8469 ///  ::= .short expression [, expression]*
8470 ///  ::= .word expression [, expression]*
8471 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8472   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8473     for (;;) {
8474       const MCExpr *Value;
8475       if (getParser().parseExpression(Value)) {
8476         Parser.eatToEndOfStatement();
8477         return false;
8478       }
8479 
8480       getParser().getStreamer().EmitValue(Value, Size);
8481 
8482       if (getLexer().is(AsmToken::EndOfStatement))
8483         break;
8484 
8485       // FIXME: Improve diagnostic.
8486       if (getLexer().isNot(AsmToken::Comma)) {
8487         Error(L, "unexpected token in directive");
8488         return false;
8489       }
8490       Parser.Lex();
8491     }
8492   }
8493 
8494   Parser.Lex();
8495   return false;
8496 }
8497 
8498 /// parseDirectiveThumb
8499 ///  ::= .thumb
8500 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8501   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8502     Error(L, "unexpected token in directive");
8503     return false;
8504   }
8505   Parser.Lex();
8506 
8507   if (!hasThumb()) {
8508     Error(L, "target does not support Thumb mode");
8509     return false;
8510   }
8511 
8512   if (!isThumb())
8513     SwitchMode();
8514 
8515   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8516   return false;
8517 }
8518 
8519 /// parseDirectiveARM
8520 ///  ::= .arm
8521 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8522   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8523     Error(L, "unexpected token in directive");
8524     return false;
8525   }
8526   Parser.Lex();
8527 
8528   if (!hasARM()) {
8529     Error(L, "target does not support ARM mode");
8530     return false;
8531   }
8532 
8533   if (isThumb())
8534     SwitchMode();
8535 
8536   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8537   return false;
8538 }
8539 
8540 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8541   if (NextSymbolIsThumb) {
8542     getParser().getStreamer().EmitThumbFunc(Symbol);
8543     NextSymbolIsThumb = false;
8544   }
8545 }
8546 
8547 /// parseDirectiveThumbFunc
8548 ///  ::= .thumbfunc symbol_name
8549 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8550   const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8551   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8552 
8553   // Darwin asm has (optionally) function name after .thumb_func direction
8554   // ELF doesn't
8555   if (IsMachO) {
8556     const AsmToken &Tok = Parser.getTok();
8557     if (Tok.isNot(AsmToken::EndOfStatement)) {
8558       if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8559         Error(L, "unexpected token in .thumb_func directive");
8560         return false;
8561       }
8562 
8563       MCSymbol *Func =
8564           getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8565       getParser().getStreamer().EmitThumbFunc(Func);
8566       Parser.Lex(); // Consume the identifier token.
8567       return false;
8568     }
8569   }
8570 
8571   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8572     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8573     Parser.eatToEndOfStatement();
8574     return false;
8575   }
8576 
8577   NextSymbolIsThumb = true;
8578   return false;
8579 }
8580 
8581 /// parseDirectiveSyntax
8582 ///  ::= .syntax unified | divided
8583 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8584   const AsmToken &Tok = Parser.getTok();
8585   if (Tok.isNot(AsmToken::Identifier)) {
8586     Error(L, "unexpected token in .syntax directive");
8587     return false;
8588   }
8589 
8590   StringRef Mode = Tok.getString();
8591   if (Mode == "unified" || Mode == "UNIFIED") {
8592     Parser.Lex();
8593   } else if (Mode == "divided" || Mode == "DIVIDED") {
8594     Error(L, "'.syntax divided' arm asssembly not supported");
8595     return false;
8596   } else {
8597     Error(L, "unrecognized syntax mode in .syntax directive");
8598     return false;
8599   }
8600 
8601   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8602     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8603     return false;
8604   }
8605   Parser.Lex();
8606 
8607   // TODO tell the MC streamer the mode
8608   // getParser().getStreamer().Emit???();
8609   return false;
8610 }
8611 
8612 /// parseDirectiveCode
8613 ///  ::= .code 16 | 32
8614 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8615   const AsmToken &Tok = Parser.getTok();
8616   if (Tok.isNot(AsmToken::Integer)) {
8617     Error(L, "unexpected token in .code directive");
8618     return false;
8619   }
8620   int64_t Val = Parser.getTok().getIntVal();
8621   if (Val != 16 && Val != 32) {
8622     Error(L, "invalid operand to .code directive");
8623     return false;
8624   }
8625   Parser.Lex();
8626 
8627   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8628     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8629     return false;
8630   }
8631   Parser.Lex();
8632 
8633   if (Val == 16) {
8634     if (!hasThumb()) {
8635       Error(L, "target does not support Thumb mode");
8636       return false;
8637     }
8638 
8639     if (!isThumb())
8640       SwitchMode();
8641     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8642   } else {
8643     if (!hasARM()) {
8644       Error(L, "target does not support ARM mode");
8645       return false;
8646     }
8647 
8648     if (isThumb())
8649       SwitchMode();
8650     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8651   }
8652 
8653   return false;
8654 }
8655 
8656 /// parseDirectiveReq
8657 ///  ::= name .req registername
8658 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8659   Parser.Lex(); // Eat the '.req' token.
8660   unsigned Reg;
8661   SMLoc SRegLoc, ERegLoc;
8662   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8663     Parser.eatToEndOfStatement();
8664     Error(SRegLoc, "register name expected");
8665     return false;
8666   }
8667 
8668   // Shouldn't be anything else.
8669   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8670     Parser.eatToEndOfStatement();
8671     Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8672     return false;
8673   }
8674 
8675   Parser.Lex(); // Consume the EndOfStatement
8676 
8677   if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8678     Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8679     return false;
8680   }
8681 
8682   return false;
8683 }
8684 
8685 /// parseDirectiveUneq
8686 ///  ::= .unreq registername
8687 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8688   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8689     Parser.eatToEndOfStatement();
8690     Error(L, "unexpected input in .unreq directive.");
8691     return false;
8692   }
8693   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8694   Parser.Lex(); // Eat the identifier.
8695   return false;
8696 }
8697 
8698 /// parseDirectiveArch
8699 ///  ::= .arch token
8700 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8701   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8702 
8703   unsigned ID = StringSwitch<unsigned>(Arch)
8704 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8705     .Case(NAME, ARM::ID)
8706 #define ARM_ARCH_ALIAS(NAME, ID) \
8707     .Case(NAME, ARM::ID)
8708 #include "MCTargetDesc/ARMArchName.def"
8709     .Default(ARM::INVALID_ARCH);
8710 
8711   if (ID == ARM::INVALID_ARCH) {
8712     Error(L, "Unknown arch name");
8713     return false;
8714   }
8715 
8716   getTargetStreamer().emitArch(ID);
8717   return false;
8718 }
8719 
8720 /// parseDirectiveEabiAttr
8721 ///  ::= .eabi_attribute int, int [, "str"]
8722 ///  ::= .eabi_attribute Tag_name, int [, "str"]
8723 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8724   int64_t Tag;
8725   SMLoc TagLoc;
8726   TagLoc = Parser.getTok().getLoc();
8727   if (Parser.getTok().is(AsmToken::Identifier)) {
8728     StringRef Name = Parser.getTok().getIdentifier();
8729     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8730     if (Tag == -1) {
8731       Error(TagLoc, "attribute name not recognised: " + Name);
8732       Parser.eatToEndOfStatement();
8733       return false;
8734     }
8735     Parser.Lex();
8736   } else {
8737     const MCExpr *AttrExpr;
8738 
8739     TagLoc = Parser.getTok().getLoc();
8740     if (Parser.parseExpression(AttrExpr)) {
8741       Parser.eatToEndOfStatement();
8742       return false;
8743     }
8744 
8745     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8746     if (!CE) {
8747       Error(TagLoc, "expected numeric constant");
8748       Parser.eatToEndOfStatement();
8749       return false;
8750     }
8751 
8752     Tag = CE->getValue();
8753   }
8754 
8755   if (Parser.getTok().isNot(AsmToken::Comma)) {
8756     Error(Parser.getTok().getLoc(), "comma expected");
8757     Parser.eatToEndOfStatement();
8758     return false;
8759   }
8760   Parser.Lex(); // skip comma
8761 
8762   StringRef StringValue = "";
8763   bool IsStringValue = false;
8764 
8765   int64_t IntegerValue = 0;
8766   bool IsIntegerValue = false;
8767 
8768   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8769     IsStringValue = true;
8770   else if (Tag == ARMBuildAttrs::compatibility) {
8771     IsStringValue = true;
8772     IsIntegerValue = true;
8773   } else if (Tag < 32 || Tag % 2 == 0)
8774     IsIntegerValue = true;
8775   else if (Tag % 2 == 1)
8776     IsStringValue = true;
8777   else
8778     llvm_unreachable("invalid tag type");
8779 
8780   if (IsIntegerValue) {
8781     const MCExpr *ValueExpr;
8782     SMLoc ValueExprLoc = Parser.getTok().getLoc();
8783     if (Parser.parseExpression(ValueExpr)) {
8784       Parser.eatToEndOfStatement();
8785       return false;
8786     }
8787 
8788     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8789     if (!CE) {
8790       Error(ValueExprLoc, "expected numeric constant");
8791       Parser.eatToEndOfStatement();
8792       return false;
8793     }
8794 
8795     IntegerValue = CE->getValue();
8796   }
8797 
8798   if (Tag == ARMBuildAttrs::compatibility) {
8799     if (Parser.getTok().isNot(AsmToken::Comma))
8800       IsStringValue = false;
8801     else
8802       Parser.Lex();
8803   }
8804 
8805   if (IsStringValue) {
8806     if (Parser.getTok().isNot(AsmToken::String)) {
8807       Error(Parser.getTok().getLoc(), "bad string constant");
8808       Parser.eatToEndOfStatement();
8809       return false;
8810     }
8811 
8812     StringValue = Parser.getTok().getStringContents();
8813     Parser.Lex();
8814   }
8815 
8816   if (IsIntegerValue && IsStringValue) {
8817     assert(Tag == ARMBuildAttrs::compatibility);
8818     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8819   } else if (IsIntegerValue)
8820     getTargetStreamer().emitAttribute(Tag, IntegerValue);
8821   else if (IsStringValue)
8822     getTargetStreamer().emitTextAttribute(Tag, StringValue);
8823   return false;
8824 }
8825 
8826 /// parseDirectiveCPU
8827 ///  ::= .cpu str
8828 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8829   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8830   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8831   return false;
8832 }
8833 
8834 // FIXME: This is duplicated in getARMFPUFeatures() in
8835 // tools/clang/lib/Driver/Tools.cpp
8836 static const struct {
8837   const unsigned Fpu;
8838   const uint64_t Enabled;
8839   const uint64_t Disabled;
8840 } Fpus[] = {
8841       {ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON},
8842       {ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON},
8843       {ARM::VFPV3, ARM::FeatureVFP3, ARM::FeatureNEON},
8844       {ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},
8845       {ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},
8846       {ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},
8847       {ARM::FPV5_D16, ARM::FeatureFPARMv8 | ARM::FeatureD16,
8848        ARM::FeatureNEON | ARM::FeatureCrypto},
8849       {ARM::FP_ARMV8, ARM::FeatureFPARMv8,
8850        ARM::FeatureNEON | ARM::FeatureCrypto},
8851       {ARM::NEON, ARM::FeatureNEON, 0},
8852       {ARM::NEON_VFPV4, ARM::FeatureVFP4 | ARM::FeatureNEON, 0},
8853       {ARM::NEON_FP_ARMV8, ARM::FeatureFPARMv8 | ARM::FeatureNEON,
8854        ARM::FeatureCrypto},
8855       {ARM::CRYPTO_NEON_FP_ARMV8,
8856        ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, 0},
8857       {ARM::SOFTVFP, 0, 0},
8858 };
8859 
8860 /// parseDirectiveFPU
8861 ///  ::= .fpu str
8862 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8863   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8864 
8865   unsigned ID = StringSwitch<unsigned>(FPU)
8866 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8867 #include "ARMFPUName.def"
8868     .Default(ARM::INVALID_FPU);
8869 
8870   if (ID == ARM::INVALID_FPU) {
8871     Error(L, "Unknown FPU name");
8872     return false;
8873   }
8874 
8875   for (const auto &Fpu : Fpus) {
8876     if (Fpu.Fpu != ID)
8877       continue;
8878 
8879     // Need to toggle features that should be on but are off and that
8880     // should off but are on.
8881     uint64_t Toggle = (Fpu.Enabled & ~STI.getFeatureBits()) |
8882                       (Fpu.Disabled & STI.getFeatureBits());
8883     setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
8884     break;
8885   }
8886 
8887   getTargetStreamer().emitFPU(ID);
8888   return false;
8889 }
8890 
8891 /// parseDirectiveFnStart
8892 ///  ::= .fnstart
8893 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8894   if (UC.hasFnStart()) {
8895     Error(L, ".fnstart starts before the end of previous one");
8896     UC.emitFnStartLocNotes();
8897     return false;
8898   }
8899 
8900   // Reset the unwind directives parser state
8901   UC.reset();
8902 
8903   getTargetStreamer().emitFnStart();
8904 
8905   UC.recordFnStart(L);
8906   return false;
8907 }
8908 
8909 /// parseDirectiveFnEnd
8910 ///  ::= .fnend
8911 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8912   // Check the ordering of unwind directives
8913   if (!UC.hasFnStart()) {
8914     Error(L, ".fnstart must precede .fnend directive");
8915     return false;
8916   }
8917 
8918   // Reset the unwind directives parser state
8919   getTargetStreamer().emitFnEnd();
8920 
8921   UC.reset();
8922   return false;
8923 }
8924 
8925 /// parseDirectiveCantUnwind
8926 ///  ::= .cantunwind
8927 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8928   UC.recordCantUnwind(L);
8929 
8930   // Check the ordering of unwind directives
8931   if (!UC.hasFnStart()) {
8932     Error(L, ".fnstart must precede .cantunwind directive");
8933     return false;
8934   }
8935   if (UC.hasHandlerData()) {
8936     Error(L, ".cantunwind can't be used with .handlerdata directive");
8937     UC.emitHandlerDataLocNotes();
8938     return false;
8939   }
8940   if (UC.hasPersonality()) {
8941     Error(L, ".cantunwind can't be used with .personality directive");
8942     UC.emitPersonalityLocNotes();
8943     return false;
8944   }
8945 
8946   getTargetStreamer().emitCantUnwind();
8947   return false;
8948 }
8949 
8950 /// parseDirectivePersonality
8951 ///  ::= .personality name
8952 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8953   bool HasExistingPersonality = UC.hasPersonality();
8954 
8955   UC.recordPersonality(L);
8956 
8957   // Check the ordering of unwind directives
8958   if (!UC.hasFnStart()) {
8959     Error(L, ".fnstart must precede .personality directive");
8960     return false;
8961   }
8962   if (UC.cantUnwind()) {
8963     Error(L, ".personality can't be used with .cantunwind directive");
8964     UC.emitCantUnwindLocNotes();
8965     return false;
8966   }
8967   if (UC.hasHandlerData()) {
8968     Error(L, ".personality must precede .handlerdata directive");
8969     UC.emitHandlerDataLocNotes();
8970     return false;
8971   }
8972   if (HasExistingPersonality) {
8973     Parser.eatToEndOfStatement();
8974     Error(L, "multiple personality directives");
8975     UC.emitPersonalityLocNotes();
8976     return false;
8977   }
8978 
8979   // Parse the name of the personality routine
8980   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8981     Parser.eatToEndOfStatement();
8982     Error(L, "unexpected input in .personality directive.");
8983     return false;
8984   }
8985   StringRef Name(Parser.getTok().getIdentifier());
8986   Parser.Lex();
8987 
8988   MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8989   getTargetStreamer().emitPersonality(PR);
8990   return false;
8991 }
8992 
8993 /// parseDirectiveHandlerData
8994 ///  ::= .handlerdata
8995 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8996   UC.recordHandlerData(L);
8997 
8998   // Check the ordering of unwind directives
8999   if (!UC.hasFnStart()) {
9000     Error(L, ".fnstart must precede .personality directive");
9001     return false;
9002   }
9003   if (UC.cantUnwind()) {
9004     Error(L, ".handlerdata can't be used with .cantunwind directive");
9005     UC.emitCantUnwindLocNotes();
9006     return false;
9007   }
9008 
9009   getTargetStreamer().emitHandlerData();
9010   return false;
9011 }
9012 
9013 /// parseDirectiveSetFP
9014 ///  ::= .setfp fpreg, spreg [, offset]
9015 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9016   // Check the ordering of unwind directives
9017   if (!UC.hasFnStart()) {
9018     Error(L, ".fnstart must precede .setfp directive");
9019     return false;
9020   }
9021   if (UC.hasHandlerData()) {
9022     Error(L, ".setfp must precede .handlerdata directive");
9023     return false;
9024   }
9025 
9026   // Parse fpreg
9027   SMLoc FPRegLoc = Parser.getTok().getLoc();
9028   int FPReg = tryParseRegister();
9029   if (FPReg == -1) {
9030     Error(FPRegLoc, "frame pointer register expected");
9031     return false;
9032   }
9033 
9034   // Consume comma
9035   if (Parser.getTok().isNot(AsmToken::Comma)) {
9036     Error(Parser.getTok().getLoc(), "comma expected");
9037     return false;
9038   }
9039   Parser.Lex(); // skip comma
9040 
9041   // Parse spreg
9042   SMLoc SPRegLoc = Parser.getTok().getLoc();
9043   int SPReg = tryParseRegister();
9044   if (SPReg == -1) {
9045     Error(SPRegLoc, "stack pointer register expected");
9046     return false;
9047   }
9048 
9049   if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
9050     Error(SPRegLoc, "register should be either $sp or the latest fp register");
9051     return false;
9052   }
9053 
9054   // Update the frame pointer register
9055   UC.saveFPReg(FPReg);
9056 
9057   // Parse offset
9058   int64_t Offset = 0;
9059   if (Parser.getTok().is(AsmToken::Comma)) {
9060     Parser.Lex(); // skip comma
9061 
9062     if (Parser.getTok().isNot(AsmToken::Hash) &&
9063         Parser.getTok().isNot(AsmToken::Dollar)) {
9064       Error(Parser.getTok().getLoc(), "'#' expected");
9065       return false;
9066     }
9067     Parser.Lex(); // skip hash token.
9068 
9069     const MCExpr *OffsetExpr;
9070     SMLoc ExLoc = Parser.getTok().getLoc();
9071     SMLoc EndLoc;
9072     if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9073       Error(ExLoc, "malformed setfp offset");
9074       return false;
9075     }
9076     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9077     if (!CE) {
9078       Error(ExLoc, "setfp offset must be an immediate");
9079       return false;
9080     }
9081 
9082     Offset = CE->getValue();
9083   }
9084 
9085   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9086                                 static_cast<unsigned>(SPReg), Offset);
9087   return false;
9088 }
9089 
9090 /// parseDirective
9091 ///  ::= .pad offset
9092 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9093   // Check the ordering of unwind directives
9094   if (!UC.hasFnStart()) {
9095     Error(L, ".fnstart must precede .pad directive");
9096     return false;
9097   }
9098   if (UC.hasHandlerData()) {
9099     Error(L, ".pad must precede .handlerdata directive");
9100     return false;
9101   }
9102 
9103   // Parse the offset
9104   if (Parser.getTok().isNot(AsmToken::Hash) &&
9105       Parser.getTok().isNot(AsmToken::Dollar)) {
9106     Error(Parser.getTok().getLoc(), "'#' expected");
9107     return false;
9108   }
9109   Parser.Lex(); // skip hash token.
9110 
9111   const MCExpr *OffsetExpr;
9112   SMLoc ExLoc = Parser.getTok().getLoc();
9113   SMLoc EndLoc;
9114   if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9115     Error(ExLoc, "malformed pad offset");
9116     return false;
9117   }
9118   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9119   if (!CE) {
9120     Error(ExLoc, "pad offset must be an immediate");
9121     return false;
9122   }
9123 
9124   getTargetStreamer().emitPad(CE->getValue());
9125   return false;
9126 }
9127 
9128 /// parseDirectiveRegSave
9129 ///  ::= .save  { registers }
9130 ///  ::= .vsave { registers }
9131 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9132   // Check the ordering of unwind directives
9133   if (!UC.hasFnStart()) {
9134     Error(L, ".fnstart must precede .save or .vsave directives");
9135     return false;
9136   }
9137   if (UC.hasHandlerData()) {
9138     Error(L, ".save or .vsave must precede .handlerdata directive");
9139     return false;
9140   }
9141 
9142   // RAII object to make sure parsed operands are deleted.
9143   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9144 
9145   // Parse the register list
9146   if (parseRegisterList(Operands))
9147     return false;
9148   ARMOperand &Op = (ARMOperand &)*Operands[0];
9149   if (!IsVector && !Op.isRegList()) {
9150     Error(L, ".save expects GPR registers");
9151     return false;
9152   }
9153   if (IsVector && !Op.isDPRRegList()) {
9154     Error(L, ".vsave expects DPR registers");
9155     return false;
9156   }
9157 
9158   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9159   return false;
9160 }
9161 
9162 /// parseDirectiveInst
9163 ///  ::= .inst opcode [, ...]
9164 ///  ::= .inst.n opcode [, ...]
9165 ///  ::= .inst.w opcode [, ...]
9166 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9167   int Width;
9168 
9169   if (isThumb()) {
9170     switch (Suffix) {
9171     case 'n':
9172       Width = 2;
9173       break;
9174     case 'w':
9175       Width = 4;
9176       break;
9177     default:
9178       Parser.eatToEndOfStatement();
9179       Error(Loc, "cannot determine Thumb instruction size, "
9180                  "use inst.n/inst.w instead");
9181       return false;
9182     }
9183   } else {
9184     if (Suffix) {
9185       Parser.eatToEndOfStatement();
9186       Error(Loc, "width suffixes are invalid in ARM mode");
9187       return false;
9188     }
9189     Width = 4;
9190   }
9191 
9192   if (getLexer().is(AsmToken::EndOfStatement)) {
9193     Parser.eatToEndOfStatement();
9194     Error(Loc, "expected expression following directive");
9195     return false;
9196   }
9197 
9198   for (;;) {
9199     const MCExpr *Expr;
9200 
9201     if (getParser().parseExpression(Expr)) {
9202       Error(Loc, "expected expression");
9203       return false;
9204     }
9205 
9206     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9207     if (!Value) {
9208       Error(Loc, "expected constant expression");
9209       return false;
9210     }
9211 
9212     switch (Width) {
9213     case 2:
9214       if (Value->getValue() > 0xffff) {
9215         Error(Loc, "inst.n operand is too big, use inst.w instead");
9216         return false;
9217       }
9218       break;
9219     case 4:
9220       if (Value->getValue() > 0xffffffff) {
9221         Error(Loc,
9222               StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9223         return false;
9224       }
9225       break;
9226     default:
9227       llvm_unreachable("only supported widths are 2 and 4");
9228     }
9229 
9230     getTargetStreamer().emitInst(Value->getValue(), Suffix);
9231 
9232     if (getLexer().is(AsmToken::EndOfStatement))
9233       break;
9234 
9235     if (getLexer().isNot(AsmToken::Comma)) {
9236       Error(Loc, "unexpected token in directive");
9237       return false;
9238     }
9239 
9240     Parser.Lex();
9241   }
9242 
9243   Parser.Lex();
9244   return false;
9245 }
9246 
9247 /// parseDirectiveLtorg
9248 ///  ::= .ltorg | .pool
9249 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9250   getTargetStreamer().emitCurrentConstantPool();
9251   return false;
9252 }
9253 
9254 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9255   const MCSection *Section = getStreamer().getCurrentSection().first;
9256 
9257   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9258     TokError("unexpected token in directive");
9259     return false;
9260   }
9261 
9262   if (!Section) {
9263     getStreamer().InitSections();
9264     Section = getStreamer().getCurrentSection().first;
9265   }
9266 
9267   assert(Section && "must have section to emit alignment");
9268   if (Section->UseCodeAlign())
9269     getStreamer().EmitCodeAlignment(2);
9270   else
9271     getStreamer().EmitValueToAlignment(2);
9272 
9273   return false;
9274 }
9275 
9276 /// parseDirectivePersonalityIndex
9277 ///   ::= .personalityindex index
9278 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9279   bool HasExistingPersonality = UC.hasPersonality();
9280 
9281   UC.recordPersonalityIndex(L);
9282 
9283   if (!UC.hasFnStart()) {
9284     Parser.eatToEndOfStatement();
9285     Error(L, ".fnstart must precede .personalityindex directive");
9286     return false;
9287   }
9288   if (UC.cantUnwind()) {
9289     Parser.eatToEndOfStatement();
9290     Error(L, ".personalityindex cannot be used with .cantunwind");
9291     UC.emitCantUnwindLocNotes();
9292     return false;
9293   }
9294   if (UC.hasHandlerData()) {
9295     Parser.eatToEndOfStatement();
9296     Error(L, ".personalityindex must precede .handlerdata directive");
9297     UC.emitHandlerDataLocNotes();
9298     return false;
9299   }
9300   if (HasExistingPersonality) {
9301     Parser.eatToEndOfStatement();
9302     Error(L, "multiple personality directives");
9303     UC.emitPersonalityLocNotes();
9304     return false;
9305   }
9306 
9307   const MCExpr *IndexExpression;
9308   SMLoc IndexLoc = Parser.getTok().getLoc();
9309   if (Parser.parseExpression(IndexExpression)) {
9310     Parser.eatToEndOfStatement();
9311     return false;
9312   }
9313 
9314   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9315   if (!CE) {
9316     Parser.eatToEndOfStatement();
9317     Error(IndexLoc, "index must be a constant number");
9318     return false;
9319   }
9320   if (CE->getValue() < 0 ||
9321       CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9322     Parser.eatToEndOfStatement();
9323     Error(IndexLoc, "personality routine index should be in range [0-3]");
9324     return false;
9325   }
9326 
9327   getTargetStreamer().emitPersonalityIndex(CE->getValue());
9328   return false;
9329 }
9330 
9331 /// parseDirectiveUnwindRaw
9332 ///   ::= .unwind_raw offset, opcode [, opcode...]
9333 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9334   if (!UC.hasFnStart()) {
9335     Parser.eatToEndOfStatement();
9336     Error(L, ".fnstart must precede .unwind_raw directives");
9337     return false;
9338   }
9339 
9340   int64_t StackOffset;
9341 
9342   const MCExpr *OffsetExpr;
9343   SMLoc OffsetLoc = getLexer().getLoc();
9344   if (getLexer().is(AsmToken::EndOfStatement) ||
9345       getParser().parseExpression(OffsetExpr)) {
9346     Error(OffsetLoc, "expected expression");
9347     Parser.eatToEndOfStatement();
9348     return false;
9349   }
9350 
9351   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9352   if (!CE) {
9353     Error(OffsetLoc, "offset must be a constant");
9354     Parser.eatToEndOfStatement();
9355     return false;
9356   }
9357 
9358   StackOffset = CE->getValue();
9359 
9360   if (getLexer().isNot(AsmToken::Comma)) {
9361     Error(getLexer().getLoc(), "expected comma");
9362     Parser.eatToEndOfStatement();
9363     return false;
9364   }
9365   Parser.Lex();
9366 
9367   SmallVector<uint8_t, 16> Opcodes;
9368   for (;;) {
9369     const MCExpr *OE;
9370 
9371     SMLoc OpcodeLoc = getLexer().getLoc();
9372     if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9373       Error(OpcodeLoc, "expected opcode expression");
9374       Parser.eatToEndOfStatement();
9375       return false;
9376     }
9377 
9378     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9379     if (!OC) {
9380       Error(OpcodeLoc, "opcode value must be a constant");
9381       Parser.eatToEndOfStatement();
9382       return false;
9383     }
9384 
9385     const int64_t Opcode = OC->getValue();
9386     if (Opcode & ~0xff) {
9387       Error(OpcodeLoc, "invalid opcode");
9388       Parser.eatToEndOfStatement();
9389       return false;
9390     }
9391 
9392     Opcodes.push_back(uint8_t(Opcode));
9393 
9394     if (getLexer().is(AsmToken::EndOfStatement))
9395       break;
9396 
9397     if (getLexer().isNot(AsmToken::Comma)) {
9398       Error(getLexer().getLoc(), "unexpected token in directive");
9399       Parser.eatToEndOfStatement();
9400       return false;
9401     }
9402 
9403     Parser.Lex();
9404   }
9405 
9406   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9407 
9408   Parser.Lex();
9409   return false;
9410 }
9411 
9412 /// parseDirectiveTLSDescSeq
9413 ///   ::= .tlsdescseq tls-variable
9414 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9415   if (getLexer().isNot(AsmToken::Identifier)) {
9416     TokError("expected variable after '.tlsdescseq' directive");
9417     Parser.eatToEndOfStatement();
9418     return false;
9419   }
9420 
9421   const MCSymbolRefExpr *SRE =
9422     MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9423                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9424   Lex();
9425 
9426   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9427     Error(Parser.getTok().getLoc(), "unexpected token");
9428     Parser.eatToEndOfStatement();
9429     return false;
9430   }
9431 
9432   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9433   return false;
9434 }
9435 
9436 /// parseDirectiveMovSP
9437 ///  ::= .movsp reg [, #offset]
9438 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9439   if (!UC.hasFnStart()) {
9440     Parser.eatToEndOfStatement();
9441     Error(L, ".fnstart must precede .movsp directives");
9442     return false;
9443   }
9444   if (UC.getFPReg() != ARM::SP) {
9445     Parser.eatToEndOfStatement();
9446     Error(L, "unexpected .movsp directive");
9447     return false;
9448   }
9449 
9450   SMLoc SPRegLoc = Parser.getTok().getLoc();
9451   int SPReg = tryParseRegister();
9452   if (SPReg == -1) {
9453     Parser.eatToEndOfStatement();
9454     Error(SPRegLoc, "register expected");
9455     return false;
9456   }
9457 
9458   if (SPReg == ARM::SP || SPReg == ARM::PC) {
9459     Parser.eatToEndOfStatement();
9460     Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9461     return false;
9462   }
9463 
9464   int64_t Offset = 0;
9465   if (Parser.getTok().is(AsmToken::Comma)) {
9466     Parser.Lex();
9467 
9468     if (Parser.getTok().isNot(AsmToken::Hash)) {
9469       Error(Parser.getTok().getLoc(), "expected #constant");
9470       Parser.eatToEndOfStatement();
9471       return false;
9472     }
9473     Parser.Lex();
9474 
9475     const MCExpr *OffsetExpr;
9476     SMLoc OffsetLoc = Parser.getTok().getLoc();
9477     if (Parser.parseExpression(OffsetExpr)) {
9478       Parser.eatToEndOfStatement();
9479       Error(OffsetLoc, "malformed offset expression");
9480       return false;
9481     }
9482 
9483     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9484     if (!CE) {
9485       Parser.eatToEndOfStatement();
9486       Error(OffsetLoc, "offset must be an immediate constant");
9487       return false;
9488     }
9489 
9490     Offset = CE->getValue();
9491   }
9492 
9493   getTargetStreamer().emitMovSP(SPReg, Offset);
9494   UC.saveFPReg(SPReg);
9495 
9496   return false;
9497 }
9498 
9499 /// parseDirectiveObjectArch
9500 ///   ::= .object_arch name
9501 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9502   if (getLexer().isNot(AsmToken::Identifier)) {
9503     Error(getLexer().getLoc(), "unexpected token");
9504     Parser.eatToEndOfStatement();
9505     return false;
9506   }
9507 
9508   StringRef Arch = Parser.getTok().getString();
9509   SMLoc ArchLoc = Parser.getTok().getLoc();
9510   getLexer().Lex();
9511 
9512   unsigned ID = StringSwitch<unsigned>(Arch)
9513 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9514     .Case(NAME, ARM::ID)
9515 #define ARM_ARCH_ALIAS(NAME, ID) \
9516     .Case(NAME, ARM::ID)
9517 #include "MCTargetDesc/ARMArchName.def"
9518 #undef ARM_ARCH_NAME
9519 #undef ARM_ARCH_ALIAS
9520     .Default(ARM::INVALID_ARCH);
9521 
9522   if (ID == ARM::INVALID_ARCH) {
9523     Error(ArchLoc, "unknown architecture '" + Arch + "'");
9524     Parser.eatToEndOfStatement();
9525     return false;
9526   }
9527 
9528   getTargetStreamer().emitObjectArch(ID);
9529 
9530   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9531     Error(getLexer().getLoc(), "unexpected token");
9532     Parser.eatToEndOfStatement();
9533   }
9534 
9535   return false;
9536 }
9537 
9538 /// parseDirectiveAlign
9539 ///   ::= .align
9540 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9541   // NOTE: if this is not the end of the statement, fall back to the target
9542   // agnostic handling for this directive which will correctly handle this.
9543   if (getLexer().isNot(AsmToken::EndOfStatement))
9544     return true;
9545 
9546   // '.align' is target specifically handled to mean 2**2 byte alignment.
9547   if (getStreamer().getCurrentSection().first->UseCodeAlign())
9548     getStreamer().EmitCodeAlignment(4, 0);
9549   else
9550     getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9551 
9552   return false;
9553 }
9554 
9555 /// parseDirectiveThumbSet
9556 ///  ::= .thumb_set name, value
9557 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9558   StringRef Name;
9559   if (Parser.parseIdentifier(Name)) {
9560     TokError("expected identifier after '.thumb_set'");
9561     Parser.eatToEndOfStatement();
9562     return false;
9563   }
9564 
9565   if (getLexer().isNot(AsmToken::Comma)) {
9566     TokError("expected comma after name '" + Name + "'");
9567     Parser.eatToEndOfStatement();
9568     return false;
9569   }
9570   Lex();
9571 
9572   const MCExpr *Value;
9573   if (Parser.parseExpression(Value)) {
9574     TokError("missing expression");
9575     Parser.eatToEndOfStatement();
9576     return false;
9577   }
9578 
9579   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9580     TokError("unexpected token");
9581     Parser.eatToEndOfStatement();
9582     return false;
9583   }
9584   Lex();
9585 
9586   MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9587   getTargetStreamer().emitThumbSet(Alias, Value);
9588   return false;
9589 }
9590 
9591 /// Force static initialization.
9592 extern "C" void LLVMInitializeARMAsmParser() {
9593   RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9594   RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9595   RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9596   RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9597 }
9598 
9599 #define GET_REGISTER_MATCHER
9600 #define GET_SUBTARGET_FEATURE_NAME
9601 #define GET_MATCHER_IMPLEMENTATION
9602 #include "ARMGenAsmMatcher.inc"
9603 
9604 static const struct {
9605   const char *Name;
9606   const unsigned ArchCheck;
9607   const uint64_t Features;
9608 } Extensions[] = {
9609   { "crc", Feature_HasV8, ARM::FeatureCRC },
9610   { "crypto",  Feature_HasV8,
9611     ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9612   { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9613   { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9614     ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9615   // FIXME: iWMMXT not supported
9616   { "iwmmxt", Feature_None, 0 },
9617   // FIXME: iWMMXT2 not supported
9618   { "iwmmxt2", Feature_None, 0 },
9619   // FIXME: Maverick not supported
9620   { "maverick", Feature_None, 0 },
9621   { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9622   // FIXME: ARMv6-m OS Extensions feature not checked
9623   { "os", Feature_None, 0 },
9624   // FIXME: Also available in ARMv6-K
9625   { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9626   { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9627   // FIXME: Only available in A-class, isel not predicated
9628   { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9629   // FIXME: xscale not supported
9630   { "xscale", Feature_None, 0 },
9631 };
9632 
9633 /// parseDirectiveArchExtension
9634 ///   ::= .arch_extension [no]feature
9635 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9636   if (getLexer().isNot(AsmToken::Identifier)) {
9637     Error(getLexer().getLoc(), "unexpected token");
9638     Parser.eatToEndOfStatement();
9639     return false;
9640   }
9641 
9642   StringRef Name = Parser.getTok().getString();
9643   SMLoc ExtLoc = Parser.getTok().getLoc();
9644   getLexer().Lex();
9645 
9646   bool EnableFeature = true;
9647   if (Name.startswith_lower("no")) {
9648     EnableFeature = false;
9649     Name = Name.substr(2);
9650   }
9651 
9652   for (const auto &Extension : Extensions) {
9653     if (Extension.Name != Name)
9654       continue;
9655 
9656     if (!Extension.Features)
9657       report_fatal_error("unsupported architectural extension: " + Name);
9658 
9659     if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
9660       Error(ExtLoc, "architectural extension '" + Name + "' is not "
9661             "allowed for the current base architecture");
9662       return false;
9663     }
9664 
9665     uint64_t ToggleFeatures = EnableFeature
9666                                   ? (~STI.getFeatureBits() & Extension.Features)
9667                                   : ( STI.getFeatureBits() & Extension.Features);
9668     uint64_t Features =
9669         ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
9670     setAvailableFeatures(Features);
9671     return false;
9672   }
9673 
9674   Error(ExtLoc, "unknown architectural extension: " + Name);
9675   Parser.eatToEndOfStatement();
9676   return false;
9677 }
9678 
9679 // Define this matcher function after the auto-generated include so we
9680 // have the match class enum definitions.
9681 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
9682                                                   unsigned Kind) {
9683   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
9684   // If the kind is a token for a literal immediate, check if our asm
9685   // operand matches. This is for InstAliases which have a fixed-value
9686   // immediate in the syntax.
9687   switch (Kind) {
9688   default: break;
9689   case MCK__35_0:
9690     if (Op.isImm())
9691       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
9692         if (CE->getValue() == 0)
9693           return Match_Success;
9694     break;
9695   case MCK_ARMSOImm:
9696     if (Op.isImm()) {
9697       const MCExpr *SOExpr = Op.getImm();
9698       int64_t Value;
9699       if (!SOExpr->EvaluateAsAbsolute(Value))
9700         return Match_Success;
9701       assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
9702              "expression value must be representable in 32 bits");
9703     }
9704     break;
9705   case MCK_GPRPair:
9706     if (Op.isReg() &&
9707         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
9708       return Match_Success;
9709     break;
9710   }
9711   return Match_InvalidOperand;
9712 }
9713