1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
49 
50 using namespace llvm;
51 
52 namespace {
53 
54 class ARMOperand;
55 
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
57 
58 class UnwindContext {
59   MCAsmParser &Parser;
60 
61   typedef SmallVector<SMLoc, 4> Locs;
62 
63   Locs FnStartLocs;
64   Locs CantUnwindLocs;
65   Locs PersonalityLocs;
66   Locs PersonalityIndexLocs;
67   Locs HandlerDataLocs;
68   int FPReg;
69 
70 public:
71   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
72 
73   bool hasFnStart() const { return !FnStartLocs.empty(); }
74   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76   bool hasPersonality() const {
77     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
78   }
79 
80   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
85 
86   void saveFPReg(int Reg) { FPReg = Reg; }
87   int getFPReg() const { return FPReg; }
88 
89   void emitFnStartLocNotes() const {
90     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
91          FI != FE; ++FI)
92       Parser.Note(*FI, ".fnstart was specified here");
93   }
94   void emitCantUnwindLocNotes() const {
95     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
97       Parser.Note(*UI, ".cantunwind was specified here");
98   }
99   void emitHandlerDataLocNotes() const {
100     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
102       Parser.Note(*HI, ".handlerdata was specified here");
103   }
104   void emitPersonalityLocNotes() const {
105     for (Locs::const_iterator PI = PersonalityLocs.begin(),
106                               PE = PersonalityLocs.end(),
107                               PII = PersonalityIndexLocs.begin(),
108                               PIE = PersonalityIndexLocs.end();
109          PI != PE || PII != PIE;) {
110       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111         Parser.Note(*PI++, ".personality was specified here");
112       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113         Parser.Note(*PII++, ".personalityindex was specified here");
114       else
115         llvm_unreachable(".personality and .personalityindex cannot be "
116                          "at the same location");
117     }
118   }
119 
120   void reset() {
121     FnStartLocs = Locs();
122     CantUnwindLocs = Locs();
123     PersonalityLocs = Locs();
124     HandlerDataLocs = Locs();
125     PersonalityIndexLocs = Locs();
126     FPReg = ARM::SP;
127   }
128 };
129 
130 class ARMAsmParser : public MCTargetAsmParser {
131   MCSubtargetInfo &STI;
132   MCAsmParser &Parser;
133   const MCInstrInfo &MII;
134   const MCRegisterInfo *MRI;
135   UnwindContext UC;
136 
137   ARMTargetStreamer &getTargetStreamer() {
138     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
139     return static_cast<ARMTargetStreamer &>(TS);
140   }
141 
142   // Map of register aliases registers via the .req directive.
143   StringMap<unsigned> RegisterReqs;
144 
145   bool NextSymbolIsThumb;
146 
147   struct {
148     ARMCC::CondCodes Cond;    // Condition for IT block.
149     unsigned Mask:4;          // Condition mask for instructions.
150                               // Starting at first 1 (from lsb).
151                               //   '1'  condition as indicated in IT.
152                               //   '0'  inverse of condition (else).
153                               // Count of instructions in IT block is
154                               // 4 - trailingzeroes(mask)
155 
156     bool FirstCond;           // Explicit flag for when we're parsing the
157                               // First instruction in the IT block. It's
158                               // implied in the mask, so needs special
159                               // handling.
160 
161     unsigned CurPosition;     // Current position in parsing of IT
162                               // block. In range [0,3]. Initialized
163                               // according to count of instructions in block.
164                               // ~0U if no active IT block.
165   } ITState;
166   bool inITBlock() { return ITState.CurPosition != ~0U;}
167   void forwardITPosition() {
168     if (!inITBlock()) return;
169     // Move to the next instruction in the IT block, if there is one. If not,
170     // mark the block as done.
171     unsigned TZ = countTrailingZeros(ITState.Mask);
172     if (++ITState.CurPosition == 5 - TZ)
173       ITState.CurPosition = ~0U; // Done with the IT block after this.
174   }
175 
176 
177   MCAsmParser &getParser() const { return Parser; }
178   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
179 
180   void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
181     return Parser.Note(L, Msg, Ranges);
182   }
183   bool Warning(SMLoc L, const Twine &Msg,
184                ArrayRef<SMRange> Ranges = None) {
185     return Parser.Warning(L, Msg, Ranges);
186   }
187   bool Error(SMLoc L, const Twine &Msg,
188              ArrayRef<SMRange> Ranges = None) {
189     return Parser.Error(L, Msg, Ranges);
190   }
191 
192   int tryParseRegister();
193   bool tryParseRegisterWithWriteBack(OperandVector &);
194   int tryParseShiftRegister(OperandVector &);
195   bool parseRegisterList(OperandVector &);
196   bool parseMemory(OperandVector &);
197   bool parseOperand(OperandVector &, StringRef Mnemonic);
198   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
199   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
200                               unsigned &ShiftAmount);
201   bool parseLiteralValues(unsigned Size, SMLoc L);
202   bool parseDirectiveThumb(SMLoc L);
203   bool parseDirectiveARM(SMLoc L);
204   bool parseDirectiveThumbFunc(SMLoc L);
205   bool parseDirectiveCode(SMLoc L);
206   bool parseDirectiveSyntax(SMLoc L);
207   bool parseDirectiveReq(StringRef Name, SMLoc L);
208   bool parseDirectiveUnreq(SMLoc L);
209   bool parseDirectiveArch(SMLoc L);
210   bool parseDirectiveEabiAttr(SMLoc L);
211   bool parseDirectiveCPU(SMLoc L);
212   bool parseDirectiveFPU(SMLoc L);
213   bool parseDirectiveFnStart(SMLoc L);
214   bool parseDirectiveFnEnd(SMLoc L);
215   bool parseDirectiveCantUnwind(SMLoc L);
216   bool parseDirectivePersonality(SMLoc L);
217   bool parseDirectiveHandlerData(SMLoc L);
218   bool parseDirectiveSetFP(SMLoc L);
219   bool parseDirectivePad(SMLoc L);
220   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
221   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
222   bool parseDirectiveLtorg(SMLoc L);
223   bool parseDirectiveEven(SMLoc L);
224   bool parseDirectivePersonalityIndex(SMLoc L);
225   bool parseDirectiveUnwindRaw(SMLoc L);
226   bool parseDirectiveTLSDescSeq(SMLoc L);
227   bool parseDirectiveMovSP(SMLoc L);
228   bool parseDirectiveObjectArch(SMLoc L);
229   bool parseDirectiveArchExtension(SMLoc L);
230   bool parseDirectiveAlign(SMLoc L);
231   bool parseDirectiveThumbSet(SMLoc L);
232 
233   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
234                           bool &CarrySetting, unsigned &ProcessorIMod,
235                           StringRef &ITMask);
236   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
237                              bool &CanAcceptCarrySet,
238                              bool &CanAcceptPredicationCode);
239 
240   bool isThumb() const {
241     // FIXME: Can tablegen auto-generate this?
242     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
243   }
244   bool isThumbOne() const {
245     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
246   }
247   bool isThumbTwo() const {
248     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
249   }
250   bool hasThumb() const {
251     return STI.getFeatureBits() & ARM::HasV4TOps;
252   }
253   bool hasV6Ops() const {
254     return STI.getFeatureBits() & ARM::HasV6Ops;
255   }
256   bool hasV6MOps() const {
257     return STI.getFeatureBits() & ARM::HasV6MOps;
258   }
259   bool hasV7Ops() const {
260     return STI.getFeatureBits() & ARM::HasV7Ops;
261   }
262   bool hasV8Ops() const {
263     return STI.getFeatureBits() & ARM::HasV8Ops;
264   }
265   bool hasARM() const {
266     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
267   }
268 
269   void SwitchMode() {
270     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
271     setAvailableFeatures(FB);
272   }
273   bool isMClass() const {
274     return STI.getFeatureBits() & ARM::FeatureMClass;
275   }
276 
277   /// @name Auto-generated Match Functions
278   /// {
279 
280 #define GET_ASSEMBLER_HEADER
281 #include "ARMGenAsmMatcher.inc"
282 
283   /// }
284 
285   OperandMatchResultTy parseITCondCode(OperandVector &);
286   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
287   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
288   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
289   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
290   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
291   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
292   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
293   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
294                                    int High);
295   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
296     return parsePKHImm(O, "lsl", 0, 31);
297   }
298   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
299     return parsePKHImm(O, "asr", 1, 32);
300   }
301   OperandMatchResultTy parseSetEndImm(OperandVector &);
302   OperandMatchResultTy parseShifterImm(OperandVector &);
303   OperandMatchResultTy parseRotImm(OperandVector &);
304   OperandMatchResultTy parseBitfield(OperandVector &);
305   OperandMatchResultTy parsePostIdxReg(OperandVector &);
306   OperandMatchResultTy parseAM3Offset(OperandVector &);
307   OperandMatchResultTy parseFPImm(OperandVector &);
308   OperandMatchResultTy parseVectorList(OperandVector &);
309   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
310                                        SMLoc &EndLoc);
311 
312   // Asm Match Converter Methods
313   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
314   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
315 
316   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
317   bool processInstruction(MCInst &Inst, const OperandVector &Ops);
318   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
319   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
320 
321 public:
322   enum ARMMatchResultTy {
323     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
324     Match_RequiresNotITBlock,
325     Match_RequiresV6,
326     Match_RequiresThumb2,
327 #define GET_OPERAND_DIAGNOSTIC_TYPES
328 #include "ARMGenAsmMatcher.inc"
329 
330   };
331 
332   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
333                const MCInstrInfo &MII,
334                const MCTargetOptions &Options)
335       : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
336     MCAsmParserExtension::Initialize(_Parser);
337 
338     // Cache the MCRegisterInfo.
339     MRI = getContext().getRegisterInfo();
340 
341     // Initialize the set of available features.
342     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
343 
344     // Not in an ITBlock to start with.
345     ITState.CurPosition = ~0U;
346 
347     NextSymbolIsThumb = false;
348   }
349 
350   // Implementation of the MCTargetAsmParser interface:
351   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
352   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
353                         SMLoc NameLoc, OperandVector &Operands) override;
354   bool ParseDirective(AsmToken DirectiveID) override;
355 
356   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
357                                       unsigned Kind) override;
358   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
359 
360   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
361                                OperandVector &Operands, MCStreamer &Out,
362                                unsigned &ErrorInfo,
363                                bool MatchingInlineAsm) override;
364   void onLabelParsed(MCSymbol *Symbol) override;
365 };
366 } // end anonymous namespace
367 
368 namespace {
369 
370 /// ARMOperand - Instances of this class represent a parsed ARM machine
371 /// operand.
372 class ARMOperand : public MCParsedAsmOperand {
373   enum KindTy {
374     k_CondCode,
375     k_CCOut,
376     k_ITCondMask,
377     k_CoprocNum,
378     k_CoprocReg,
379     k_CoprocOption,
380     k_Immediate,
381     k_MemBarrierOpt,
382     k_InstSyncBarrierOpt,
383     k_Memory,
384     k_PostIndexRegister,
385     k_MSRMask,
386     k_ProcIFlags,
387     k_VectorIndex,
388     k_Register,
389     k_RegisterList,
390     k_DPRRegisterList,
391     k_SPRRegisterList,
392     k_VectorList,
393     k_VectorListAllLanes,
394     k_VectorListIndexed,
395     k_ShiftedRegister,
396     k_ShiftedImmediate,
397     k_ShifterImmediate,
398     k_RotateImmediate,
399     k_BitfieldDescriptor,
400     k_Token
401   } Kind;
402 
403   SMLoc StartLoc, EndLoc, AlignmentLoc;
404   SmallVector<unsigned, 8> Registers;
405 
406   struct CCOp {
407     ARMCC::CondCodes Val;
408   };
409 
410   struct CopOp {
411     unsigned Val;
412   };
413 
414   struct CoprocOptionOp {
415     unsigned Val;
416   };
417 
418   struct ITMaskOp {
419     unsigned Mask:4;
420   };
421 
422   struct MBOptOp {
423     ARM_MB::MemBOpt Val;
424   };
425 
426   struct ISBOptOp {
427     ARM_ISB::InstSyncBOpt Val;
428   };
429 
430   struct IFlagsOp {
431     ARM_PROC::IFlags Val;
432   };
433 
434   struct MMaskOp {
435     unsigned Val;
436   };
437 
438   struct TokOp {
439     const char *Data;
440     unsigned Length;
441   };
442 
443   struct RegOp {
444     unsigned RegNum;
445   };
446 
447   // A vector register list is a sequential list of 1 to 4 registers.
448   struct VectorListOp {
449     unsigned RegNum;
450     unsigned Count;
451     unsigned LaneIndex;
452     bool isDoubleSpaced;
453   };
454 
455   struct VectorIndexOp {
456     unsigned Val;
457   };
458 
459   struct ImmOp {
460     const MCExpr *Val;
461   };
462 
463   /// Combined record for all forms of ARM address expressions.
464   struct MemoryOp {
465     unsigned BaseRegNum;
466     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
467     // was specified.
468     const MCConstantExpr *OffsetImm;  // Offset immediate value
469     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
470     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
471     unsigned ShiftImm;        // shift for OffsetReg.
472     unsigned Alignment;       // 0 = no alignment specified
473     // n = alignment in bytes (2, 4, 8, 16, or 32)
474     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
475   };
476 
477   struct PostIdxRegOp {
478     unsigned RegNum;
479     bool isAdd;
480     ARM_AM::ShiftOpc ShiftTy;
481     unsigned ShiftImm;
482   };
483 
484   struct ShifterImmOp {
485     bool isASR;
486     unsigned Imm;
487   };
488 
489   struct RegShiftedRegOp {
490     ARM_AM::ShiftOpc ShiftTy;
491     unsigned SrcReg;
492     unsigned ShiftReg;
493     unsigned ShiftImm;
494   };
495 
496   struct RegShiftedImmOp {
497     ARM_AM::ShiftOpc ShiftTy;
498     unsigned SrcReg;
499     unsigned ShiftImm;
500   };
501 
502   struct RotImmOp {
503     unsigned Imm;
504   };
505 
506   struct BitfieldOp {
507     unsigned LSB;
508     unsigned Width;
509   };
510 
511   union {
512     struct CCOp CC;
513     struct CopOp Cop;
514     struct CoprocOptionOp CoprocOption;
515     struct MBOptOp MBOpt;
516     struct ISBOptOp ISBOpt;
517     struct ITMaskOp ITMask;
518     struct IFlagsOp IFlags;
519     struct MMaskOp MMask;
520     struct TokOp Tok;
521     struct RegOp Reg;
522     struct VectorListOp VectorList;
523     struct VectorIndexOp VectorIndex;
524     struct ImmOp Imm;
525     struct MemoryOp Memory;
526     struct PostIdxRegOp PostIdxReg;
527     struct ShifterImmOp ShifterImm;
528     struct RegShiftedRegOp RegShiftedReg;
529     struct RegShiftedImmOp RegShiftedImm;
530     struct RotImmOp RotImm;
531     struct BitfieldOp Bitfield;
532   };
533 
534 public:
535   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
536   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
537     Kind = o.Kind;
538     StartLoc = o.StartLoc;
539     EndLoc = o.EndLoc;
540     switch (Kind) {
541     case k_CondCode:
542       CC = o.CC;
543       break;
544     case k_ITCondMask:
545       ITMask = o.ITMask;
546       break;
547     case k_Token:
548       Tok = o.Tok;
549       break;
550     case k_CCOut:
551     case k_Register:
552       Reg = o.Reg;
553       break;
554     case k_RegisterList:
555     case k_DPRRegisterList:
556     case k_SPRRegisterList:
557       Registers = o.Registers;
558       break;
559     case k_VectorList:
560     case k_VectorListAllLanes:
561     case k_VectorListIndexed:
562       VectorList = o.VectorList;
563       break;
564     case k_CoprocNum:
565     case k_CoprocReg:
566       Cop = o.Cop;
567       break;
568     case k_CoprocOption:
569       CoprocOption = o.CoprocOption;
570       break;
571     case k_Immediate:
572       Imm = o.Imm;
573       break;
574     case k_MemBarrierOpt:
575       MBOpt = o.MBOpt;
576       break;
577     case k_InstSyncBarrierOpt:
578       ISBOpt = o.ISBOpt;
579     case k_Memory:
580       Memory = o.Memory;
581       break;
582     case k_PostIndexRegister:
583       PostIdxReg = o.PostIdxReg;
584       break;
585     case k_MSRMask:
586       MMask = o.MMask;
587       break;
588     case k_ProcIFlags:
589       IFlags = o.IFlags;
590       break;
591     case k_ShifterImmediate:
592       ShifterImm = o.ShifterImm;
593       break;
594     case k_ShiftedRegister:
595       RegShiftedReg = o.RegShiftedReg;
596       break;
597     case k_ShiftedImmediate:
598       RegShiftedImm = o.RegShiftedImm;
599       break;
600     case k_RotateImmediate:
601       RotImm = o.RotImm;
602       break;
603     case k_BitfieldDescriptor:
604       Bitfield = o.Bitfield;
605       break;
606     case k_VectorIndex:
607       VectorIndex = o.VectorIndex;
608       break;
609     }
610   }
611 
612   /// getStartLoc - Get the location of the first token of this operand.
613   SMLoc getStartLoc() const override { return StartLoc; }
614   /// getEndLoc - Get the location of the last token of this operand.
615   SMLoc getEndLoc() const override { return EndLoc; }
616   /// getLocRange - Get the range between the first and last token of this
617   /// operand.
618   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
619 
620   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
621   SMLoc getAlignmentLoc() const {
622     assert(Kind == k_Memory && "Invalid access!");
623     return AlignmentLoc;
624   }
625 
626   ARMCC::CondCodes getCondCode() const {
627     assert(Kind == k_CondCode && "Invalid access!");
628     return CC.Val;
629   }
630 
631   unsigned getCoproc() const {
632     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
633     return Cop.Val;
634   }
635 
636   StringRef getToken() const {
637     assert(Kind == k_Token && "Invalid access!");
638     return StringRef(Tok.Data, Tok.Length);
639   }
640 
641   unsigned getReg() const override {
642     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
643     return Reg.RegNum;
644   }
645 
646   const SmallVectorImpl<unsigned> &getRegList() const {
647     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
648             Kind == k_SPRRegisterList) && "Invalid access!");
649     return Registers;
650   }
651 
652   const MCExpr *getImm() const {
653     assert(isImm() && "Invalid access!");
654     return Imm.Val;
655   }
656 
657   unsigned getVectorIndex() const {
658     assert(Kind == k_VectorIndex && "Invalid access!");
659     return VectorIndex.Val;
660   }
661 
662   ARM_MB::MemBOpt getMemBarrierOpt() const {
663     assert(Kind == k_MemBarrierOpt && "Invalid access!");
664     return MBOpt.Val;
665   }
666 
667   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
668     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
669     return ISBOpt.Val;
670   }
671 
672   ARM_PROC::IFlags getProcIFlags() const {
673     assert(Kind == k_ProcIFlags && "Invalid access!");
674     return IFlags.Val;
675   }
676 
677   unsigned getMSRMask() const {
678     assert(Kind == k_MSRMask && "Invalid access!");
679     return MMask.Val;
680   }
681 
682   bool isCoprocNum() const { return Kind == k_CoprocNum; }
683   bool isCoprocReg() const { return Kind == k_CoprocReg; }
684   bool isCoprocOption() const { return Kind == k_CoprocOption; }
685   bool isCondCode() const { return Kind == k_CondCode; }
686   bool isCCOut() const { return Kind == k_CCOut; }
687   bool isITMask() const { return Kind == k_ITCondMask; }
688   bool isITCondCode() const { return Kind == k_CondCode; }
689   bool isImm() const override { return Kind == k_Immediate; }
690   // checks whether this operand is an unsigned offset which fits is a field
691   // of specified width and scaled by a specific number of bits
692   template<unsigned width, unsigned scale>
693   bool isUnsignedOffset() const {
694     if (!isImm()) return false;
695     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
696     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
697       int64_t Val = CE->getValue();
698       int64_t Align = 1LL << scale;
699       int64_t Max = Align * ((1LL << width) - 1);
700       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
701     }
702     return false;
703   }
704   // checks whether this operand is an signed offset which fits is a field
705   // of specified width and scaled by a specific number of bits
706   template<unsigned width, unsigned scale>
707   bool isSignedOffset() const {
708     if (!isImm()) return false;
709     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
710     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
711       int64_t Val = CE->getValue();
712       int64_t Align = 1LL << scale;
713       int64_t Max = Align * ((1LL << (width-1)) - 1);
714       int64_t Min = -Align * (1LL << (width-1));
715       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
716     }
717     return false;
718   }
719 
720   // checks whether this operand is a memory operand computed as an offset
721   // applied to PC. the offset may have 8 bits of magnitude and is represented
722   // with two bits of shift. textually it may be either [pc, #imm], #imm or
723   // relocable expression...
724   bool isThumbMemPC() const {
725     int64_t Val = 0;
726     if (isImm()) {
727       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
728       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
729       if (!CE) return false;
730       Val = CE->getValue();
731     }
732     else if (isMem()) {
733       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
734       if(Memory.BaseRegNum != ARM::PC) return false;
735       Val = Memory.OffsetImm->getValue();
736     }
737     else return false;
738     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
739   }
740   bool isFPImm() const {
741     if (!isImm()) return false;
742     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743     if (!CE) return false;
744     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
745     return Val != -1;
746   }
747   bool isFBits16() const {
748     if (!isImm()) return false;
749     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
750     if (!CE) return false;
751     int64_t Value = CE->getValue();
752     return Value >= 0 && Value <= 16;
753   }
754   bool isFBits32() const {
755     if (!isImm()) return false;
756     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
757     if (!CE) return false;
758     int64_t Value = CE->getValue();
759     return Value >= 1 && Value <= 32;
760   }
761   bool isImm8s4() const {
762     if (!isImm()) return false;
763     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764     if (!CE) return false;
765     int64_t Value = CE->getValue();
766     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
767   }
768   bool isImm0_1020s4() const {
769     if (!isImm()) return false;
770     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771     if (!CE) return false;
772     int64_t Value = CE->getValue();
773     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
774   }
775   bool isImm0_508s4() const {
776     if (!isImm()) return false;
777     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778     if (!CE) return false;
779     int64_t Value = CE->getValue();
780     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
781   }
782   bool isImm0_508s4Neg() const {
783     if (!isImm()) return false;
784     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785     if (!CE) return false;
786     int64_t Value = -CE->getValue();
787     // explicitly exclude zero. we want that to use the normal 0_508 version.
788     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
789   }
790   bool isImm0_239() const {
791     if (!isImm()) return false;
792     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
793     if (!CE) return false;
794     int64_t Value = CE->getValue();
795     return Value >= 0 && Value < 240;
796   }
797   bool isImm0_255() const {
798     if (!isImm()) return false;
799     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
800     if (!CE) return false;
801     int64_t Value = CE->getValue();
802     return Value >= 0 && Value < 256;
803   }
804   bool isImm0_4095() const {
805     if (!isImm()) return false;
806     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807     if (!CE) return false;
808     int64_t Value = CE->getValue();
809     return Value >= 0 && Value < 4096;
810   }
811   bool isImm0_4095Neg() const {
812     if (!isImm()) return false;
813     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
814     if (!CE) return false;
815     int64_t Value = -CE->getValue();
816     return Value > 0 && Value < 4096;
817   }
818   bool isImm0_1() const {
819     if (!isImm()) return false;
820     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
821     if (!CE) return false;
822     int64_t Value = CE->getValue();
823     return Value >= 0 && Value < 2;
824   }
825   bool isImm0_3() const {
826     if (!isImm()) return false;
827     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
828     if (!CE) return false;
829     int64_t Value = CE->getValue();
830     return Value >= 0 && Value < 4;
831   }
832   bool isImm0_7() const {
833     if (!isImm()) return false;
834     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
835     if (!CE) return false;
836     int64_t Value = CE->getValue();
837     return Value >= 0 && Value < 8;
838   }
839   bool isImm0_15() const {
840     if (!isImm()) return false;
841     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
842     if (!CE) return false;
843     int64_t Value = CE->getValue();
844     return Value >= 0 && Value < 16;
845   }
846   bool isImm0_31() const {
847     if (!isImm()) return false;
848     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
849     if (!CE) return false;
850     int64_t Value = CE->getValue();
851     return Value >= 0 && Value < 32;
852   }
853   bool isImm0_63() const {
854     if (!isImm()) return false;
855     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
856     if (!CE) return false;
857     int64_t Value = CE->getValue();
858     return Value >= 0 && Value < 64;
859   }
860   bool isImm8() const {
861     if (!isImm()) return false;
862     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
863     if (!CE) return false;
864     int64_t Value = CE->getValue();
865     return Value == 8;
866   }
867   bool isImm16() const {
868     if (!isImm()) return false;
869     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
870     if (!CE) return false;
871     int64_t Value = CE->getValue();
872     return Value == 16;
873   }
874   bool isImm32() const {
875     if (!isImm()) return false;
876     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
877     if (!CE) return false;
878     int64_t Value = CE->getValue();
879     return Value == 32;
880   }
881   bool isShrImm8() const {
882     if (!isImm()) return false;
883     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884     if (!CE) return false;
885     int64_t Value = CE->getValue();
886     return Value > 0 && Value <= 8;
887   }
888   bool isShrImm16() const {
889     if (!isImm()) return false;
890     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
891     if (!CE) return false;
892     int64_t Value = CE->getValue();
893     return Value > 0 && Value <= 16;
894   }
895   bool isShrImm32() const {
896     if (!isImm()) return false;
897     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
898     if (!CE) return false;
899     int64_t Value = CE->getValue();
900     return Value > 0 && Value <= 32;
901   }
902   bool isShrImm64() const {
903     if (!isImm()) return false;
904     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
905     if (!CE) return false;
906     int64_t Value = CE->getValue();
907     return Value > 0 && Value <= 64;
908   }
909   bool isImm1_7() const {
910     if (!isImm()) return false;
911     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
912     if (!CE) return false;
913     int64_t Value = CE->getValue();
914     return Value > 0 && Value < 8;
915   }
916   bool isImm1_15() const {
917     if (!isImm()) return false;
918     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
919     if (!CE) return false;
920     int64_t Value = CE->getValue();
921     return Value > 0 && Value < 16;
922   }
923   bool isImm1_31() const {
924     if (!isImm()) return false;
925     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
926     if (!CE) return false;
927     int64_t Value = CE->getValue();
928     return Value > 0 && Value < 32;
929   }
930   bool isImm1_16() const {
931     if (!isImm()) return false;
932     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933     if (!CE) return false;
934     int64_t Value = CE->getValue();
935     return Value > 0 && Value < 17;
936   }
937   bool isImm1_32() const {
938     if (!isImm()) return false;
939     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940     if (!CE) return false;
941     int64_t Value = CE->getValue();
942     return Value > 0 && Value < 33;
943   }
944   bool isImm0_32() const {
945     if (!isImm()) return false;
946     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
947     if (!CE) return false;
948     int64_t Value = CE->getValue();
949     return Value >= 0 && Value < 33;
950   }
951   bool isImm0_65535() const {
952     if (!isImm()) return false;
953     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
954     if (!CE) return false;
955     int64_t Value = CE->getValue();
956     return Value >= 0 && Value < 65536;
957   }
958   bool isImm256_65535Expr() const {
959     if (!isImm()) return false;
960     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
961     // If it's not a constant expression, it'll generate a fixup and be
962     // handled later.
963     if (!CE) return true;
964     int64_t Value = CE->getValue();
965     return Value >= 256 && Value < 65536;
966   }
967   bool isImm0_65535Expr() const {
968     if (!isImm()) return false;
969     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
970     // If it's not a constant expression, it'll generate a fixup and be
971     // handled later.
972     if (!CE) return true;
973     int64_t Value = CE->getValue();
974     return Value >= 0 && Value < 65536;
975   }
976   bool isImm24bit() const {
977     if (!isImm()) return false;
978     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
979     if (!CE) return false;
980     int64_t Value = CE->getValue();
981     return Value >= 0 && Value <= 0xffffff;
982   }
983   bool isImmThumbSR() const {
984     if (!isImm()) return false;
985     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
986     if (!CE) return false;
987     int64_t Value = CE->getValue();
988     return Value > 0 && Value < 33;
989   }
990   bool isPKHLSLImm() const {
991     if (!isImm()) return false;
992     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
993     if (!CE) return false;
994     int64_t Value = CE->getValue();
995     return Value >= 0 && Value < 32;
996   }
997   bool isPKHASRImm() const {
998     if (!isImm()) return false;
999     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1000     if (!CE) return false;
1001     int64_t Value = CE->getValue();
1002     return Value > 0 && Value <= 32;
1003   }
1004   bool isAdrLabel() const {
1005     // If we have an immediate that's not a constant, treat it as a label
1006     // reference needing a fixup. If it is a constant, but it can't fit
1007     // into shift immediate encoding, we reject it.
1008     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1009     else return (isARMSOImm() || isARMSOImmNeg());
1010   }
1011   bool isARMSOImm() const {
1012     if (!isImm()) return false;
1013     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1014     if (!CE) return false;
1015     int64_t Value = CE->getValue();
1016     return ARM_AM::getSOImmVal(Value) != -1;
1017   }
1018   bool isARMSOImmNot() const {
1019     if (!isImm()) return false;
1020     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1021     if (!CE) return false;
1022     int64_t Value = CE->getValue();
1023     return ARM_AM::getSOImmVal(~Value) != -1;
1024   }
1025   bool isARMSOImmNeg() const {
1026     if (!isImm()) return false;
1027     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1028     if (!CE) return false;
1029     int64_t Value = CE->getValue();
1030     // Only use this when not representable as a plain so_imm.
1031     return ARM_AM::getSOImmVal(Value) == -1 &&
1032       ARM_AM::getSOImmVal(-Value) != -1;
1033   }
1034   bool isT2SOImm() const {
1035     if (!isImm()) return false;
1036     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1037     if (!CE) return false;
1038     int64_t Value = CE->getValue();
1039     return ARM_AM::getT2SOImmVal(Value) != -1;
1040   }
1041   bool isT2SOImmNot() const {
1042     if (!isImm()) return false;
1043     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1044     if (!CE) return false;
1045     int64_t Value = CE->getValue();
1046     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1047       ARM_AM::getT2SOImmVal(~Value) != -1;
1048   }
1049   bool isT2SOImmNeg() const {
1050     if (!isImm()) return false;
1051     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1052     if (!CE) return false;
1053     int64_t Value = CE->getValue();
1054     // Only use this when not representable as a plain so_imm.
1055     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1056       ARM_AM::getT2SOImmVal(-Value) != -1;
1057   }
1058   bool isSetEndImm() const {
1059     if (!isImm()) return false;
1060     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1061     if (!CE) return false;
1062     int64_t Value = CE->getValue();
1063     return Value == 1 || Value == 0;
1064   }
1065   bool isReg() const override { return Kind == k_Register; }
1066   bool isRegList() const { return Kind == k_RegisterList; }
1067   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1068   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1069   bool isToken() const override { return Kind == k_Token; }
1070   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1071   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1072   bool isMem() const override { return Kind == k_Memory; }
1073   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1074   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1075   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1076   bool isRotImm() const { return Kind == k_RotateImmediate; }
1077   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1078   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1079   bool isPostIdxReg() const {
1080     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1081   }
1082   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1083     if (!isMem())
1084       return false;
1085     // No offset of any kind.
1086     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1087      (alignOK || Memory.Alignment == Alignment);
1088   }
1089   bool isMemPCRelImm12() const {
1090     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1091       return false;
1092     // Base register must be PC.
1093     if (Memory.BaseRegNum != ARM::PC)
1094       return false;
1095     // Immediate offset in range [-4095, 4095].
1096     if (!Memory.OffsetImm) return true;
1097     int64_t Val = Memory.OffsetImm->getValue();
1098     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1099   }
1100   bool isAlignedMemory() const {
1101     return isMemNoOffset(true);
1102   }
1103   bool isAlignedMemoryNone() const {
1104     return isMemNoOffset(false, 0);
1105   }
1106   bool isDupAlignedMemoryNone() const {
1107     return isMemNoOffset(false, 0);
1108   }
1109   bool isAlignedMemory16() const {
1110     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1111       return true;
1112     return isMemNoOffset(false, 0);
1113   }
1114   bool isDupAlignedMemory16() const {
1115     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1116       return true;
1117     return isMemNoOffset(false, 0);
1118   }
1119   bool isAlignedMemory32() const {
1120     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1121       return true;
1122     return isMemNoOffset(false, 0);
1123   }
1124   bool isDupAlignedMemory32() const {
1125     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1126       return true;
1127     return isMemNoOffset(false, 0);
1128   }
1129   bool isAlignedMemory64() const {
1130     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1131       return true;
1132     return isMemNoOffset(false, 0);
1133   }
1134   bool isDupAlignedMemory64() const {
1135     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1136       return true;
1137     return isMemNoOffset(false, 0);
1138   }
1139   bool isAlignedMemory64or128() const {
1140     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1141       return true;
1142     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1143       return true;
1144     return isMemNoOffset(false, 0);
1145   }
1146   bool isDupAlignedMemory64or128() const {
1147     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1148       return true;
1149     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1150       return true;
1151     return isMemNoOffset(false, 0);
1152   }
1153   bool isAlignedMemory64or128or256() const {
1154     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1155       return true;
1156     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1157       return true;
1158     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1159       return true;
1160     return isMemNoOffset(false, 0);
1161   }
1162   bool isAddrMode2() const {
1163     if (!isMem() || Memory.Alignment != 0) return false;
1164     // Check for register offset.
1165     if (Memory.OffsetRegNum) return true;
1166     // Immediate offset in range [-4095, 4095].
1167     if (!Memory.OffsetImm) return true;
1168     int64_t Val = Memory.OffsetImm->getValue();
1169     return Val > -4096 && Val < 4096;
1170   }
1171   bool isAM2OffsetImm() const {
1172     if (!isImm()) return false;
1173     // Immediate offset in range [-4095, 4095].
1174     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1175     if (!CE) return false;
1176     int64_t Val = CE->getValue();
1177     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1178   }
1179   bool isAddrMode3() const {
1180     // If we have an immediate that's not a constant, treat it as a label
1181     // reference needing a fixup. If it is a constant, it's something else
1182     // and we reject it.
1183     if (isImm() && !isa<MCConstantExpr>(getImm()))
1184       return true;
1185     if (!isMem() || Memory.Alignment != 0) return false;
1186     // No shifts are legal for AM3.
1187     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1188     // Check for register offset.
1189     if (Memory.OffsetRegNum) return true;
1190     // Immediate offset in range [-255, 255].
1191     if (!Memory.OffsetImm) return true;
1192     int64_t Val = Memory.OffsetImm->getValue();
1193     // The #-0 offset is encoded as INT32_MIN, and we have to check
1194     // for this too.
1195     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1196   }
1197   bool isAM3Offset() const {
1198     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1199       return false;
1200     if (Kind == k_PostIndexRegister)
1201       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1202     // Immediate offset in range [-255, 255].
1203     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1204     if (!CE) return false;
1205     int64_t Val = CE->getValue();
1206     // Special case, #-0 is INT32_MIN.
1207     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1208   }
1209   bool isAddrMode5() const {
1210     // If we have an immediate that's not a constant, treat it as a label
1211     // reference needing a fixup. If it is a constant, it's something else
1212     // and we reject it.
1213     if (isImm() && !isa<MCConstantExpr>(getImm()))
1214       return true;
1215     if (!isMem() || Memory.Alignment != 0) return false;
1216     // Check for register offset.
1217     if (Memory.OffsetRegNum) return false;
1218     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1219     if (!Memory.OffsetImm) return true;
1220     int64_t Val = Memory.OffsetImm->getValue();
1221     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1222       Val == INT32_MIN;
1223   }
1224   bool isMemTBB() const {
1225     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1226         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1227       return false;
1228     return true;
1229   }
1230   bool isMemTBH() const {
1231     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1232         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1233         Memory.Alignment != 0 )
1234       return false;
1235     return true;
1236   }
1237   bool isMemRegOffset() const {
1238     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1239       return false;
1240     return true;
1241   }
1242   bool isT2MemRegOffset() const {
1243     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1244         Memory.Alignment != 0)
1245       return false;
1246     // Only lsl #{0, 1, 2, 3} allowed.
1247     if (Memory.ShiftType == ARM_AM::no_shift)
1248       return true;
1249     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1250       return false;
1251     return true;
1252   }
1253   bool isMemThumbRR() const {
1254     // Thumb reg+reg addressing is simple. Just two registers, a base and
1255     // an offset. No shifts, negations or any other complicating factors.
1256     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1257         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1258       return false;
1259     return isARMLowRegister(Memory.BaseRegNum) &&
1260       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1261   }
1262   bool isMemThumbRIs4() const {
1263     if (!isMem() || Memory.OffsetRegNum != 0 ||
1264         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1265       return false;
1266     // Immediate offset, multiple of 4 in range [0, 124].
1267     if (!Memory.OffsetImm) return true;
1268     int64_t Val = Memory.OffsetImm->getValue();
1269     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1270   }
1271   bool isMemThumbRIs2() const {
1272     if (!isMem() || Memory.OffsetRegNum != 0 ||
1273         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1274       return false;
1275     // Immediate offset, multiple of 4 in range [0, 62].
1276     if (!Memory.OffsetImm) return true;
1277     int64_t Val = Memory.OffsetImm->getValue();
1278     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1279   }
1280   bool isMemThumbRIs1() const {
1281     if (!isMem() || Memory.OffsetRegNum != 0 ||
1282         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1283       return false;
1284     // Immediate offset in range [0, 31].
1285     if (!Memory.OffsetImm) return true;
1286     int64_t Val = Memory.OffsetImm->getValue();
1287     return Val >= 0 && Val <= 31;
1288   }
1289   bool isMemThumbSPI() const {
1290     if (!isMem() || Memory.OffsetRegNum != 0 ||
1291         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1292       return false;
1293     // Immediate offset, multiple of 4 in range [0, 1020].
1294     if (!Memory.OffsetImm) return true;
1295     int64_t Val = Memory.OffsetImm->getValue();
1296     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1297   }
1298   bool isMemImm8s4Offset() const {
1299     // If we have an immediate that's not a constant, treat it as a label
1300     // reference needing a fixup. If it is a constant, it's something else
1301     // and we reject it.
1302     if (isImm() && !isa<MCConstantExpr>(getImm()))
1303       return true;
1304     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1305       return false;
1306     // Immediate offset a multiple of 4 in range [-1020, 1020].
1307     if (!Memory.OffsetImm) return true;
1308     int64_t Val = Memory.OffsetImm->getValue();
1309     // Special case, #-0 is INT32_MIN.
1310     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1311   }
1312   bool isMemImm0_1020s4Offset() const {
1313     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1314       return false;
1315     // Immediate offset a multiple of 4 in range [0, 1020].
1316     if (!Memory.OffsetImm) return true;
1317     int64_t Val = Memory.OffsetImm->getValue();
1318     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1319   }
1320   bool isMemImm8Offset() const {
1321     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1322       return false;
1323     // Base reg of PC isn't allowed for these encodings.
1324     if (Memory.BaseRegNum == ARM::PC) return false;
1325     // Immediate offset in range [-255, 255].
1326     if (!Memory.OffsetImm) return true;
1327     int64_t Val = Memory.OffsetImm->getValue();
1328     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1329   }
1330   bool isMemPosImm8Offset() const {
1331     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1332       return false;
1333     // Immediate offset in range [0, 255].
1334     if (!Memory.OffsetImm) return true;
1335     int64_t Val = Memory.OffsetImm->getValue();
1336     return Val >= 0 && Val < 256;
1337   }
1338   bool isMemNegImm8Offset() const {
1339     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1340       return false;
1341     // Base reg of PC isn't allowed for these encodings.
1342     if (Memory.BaseRegNum == ARM::PC) return false;
1343     // Immediate offset in range [-255, -1].
1344     if (!Memory.OffsetImm) return false;
1345     int64_t Val = Memory.OffsetImm->getValue();
1346     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1347   }
1348   bool isMemUImm12Offset() const {
1349     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1350       return false;
1351     // Immediate offset in range [0, 4095].
1352     if (!Memory.OffsetImm) return true;
1353     int64_t Val = Memory.OffsetImm->getValue();
1354     return (Val >= 0 && Val < 4096);
1355   }
1356   bool isMemImm12Offset() const {
1357     // If we have an immediate that's not a constant, treat it as a label
1358     // reference needing a fixup. If it is a constant, it's something else
1359     // and we reject it.
1360     if (isImm() && !isa<MCConstantExpr>(getImm()))
1361       return true;
1362 
1363     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1364       return false;
1365     // Immediate offset in range [-4095, 4095].
1366     if (!Memory.OffsetImm) return true;
1367     int64_t Val = Memory.OffsetImm->getValue();
1368     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1369   }
1370   bool isPostIdxImm8() const {
1371     if (!isImm()) return false;
1372     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1373     if (!CE) return false;
1374     int64_t Val = CE->getValue();
1375     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1376   }
1377   bool isPostIdxImm8s4() const {
1378     if (!isImm()) return false;
1379     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1380     if (!CE) return false;
1381     int64_t Val = CE->getValue();
1382     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1383       (Val == INT32_MIN);
1384   }
1385 
1386   bool isMSRMask() const { return Kind == k_MSRMask; }
1387   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1388 
1389   // NEON operands.
1390   bool isSingleSpacedVectorList() const {
1391     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1392   }
1393   bool isDoubleSpacedVectorList() const {
1394     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1395   }
1396   bool isVecListOneD() const {
1397     if (!isSingleSpacedVectorList()) return false;
1398     return VectorList.Count == 1;
1399   }
1400 
1401   bool isVecListDPair() const {
1402     if (!isSingleSpacedVectorList()) return false;
1403     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1404               .contains(VectorList.RegNum));
1405   }
1406 
1407   bool isVecListThreeD() const {
1408     if (!isSingleSpacedVectorList()) return false;
1409     return VectorList.Count == 3;
1410   }
1411 
1412   bool isVecListFourD() const {
1413     if (!isSingleSpacedVectorList()) return false;
1414     return VectorList.Count == 4;
1415   }
1416 
1417   bool isVecListDPairSpaced() const {
1418     if (Kind != k_VectorList) return false;
1419     if (isSingleSpacedVectorList()) return false;
1420     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1421               .contains(VectorList.RegNum));
1422   }
1423 
1424   bool isVecListThreeQ() const {
1425     if (!isDoubleSpacedVectorList()) return false;
1426     return VectorList.Count == 3;
1427   }
1428 
1429   bool isVecListFourQ() const {
1430     if (!isDoubleSpacedVectorList()) return false;
1431     return VectorList.Count == 4;
1432   }
1433 
1434   bool isSingleSpacedVectorAllLanes() const {
1435     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1436   }
1437   bool isDoubleSpacedVectorAllLanes() const {
1438     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1439   }
1440   bool isVecListOneDAllLanes() const {
1441     if (!isSingleSpacedVectorAllLanes()) return false;
1442     return VectorList.Count == 1;
1443   }
1444 
1445   bool isVecListDPairAllLanes() const {
1446     if (!isSingleSpacedVectorAllLanes()) return false;
1447     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1448               .contains(VectorList.RegNum));
1449   }
1450 
1451   bool isVecListDPairSpacedAllLanes() const {
1452     if (!isDoubleSpacedVectorAllLanes()) return false;
1453     return VectorList.Count == 2;
1454   }
1455 
1456   bool isVecListThreeDAllLanes() const {
1457     if (!isSingleSpacedVectorAllLanes()) return false;
1458     return VectorList.Count == 3;
1459   }
1460 
1461   bool isVecListThreeQAllLanes() const {
1462     if (!isDoubleSpacedVectorAllLanes()) return false;
1463     return VectorList.Count == 3;
1464   }
1465 
1466   bool isVecListFourDAllLanes() const {
1467     if (!isSingleSpacedVectorAllLanes()) return false;
1468     return VectorList.Count == 4;
1469   }
1470 
1471   bool isVecListFourQAllLanes() const {
1472     if (!isDoubleSpacedVectorAllLanes()) return false;
1473     return VectorList.Count == 4;
1474   }
1475 
1476   bool isSingleSpacedVectorIndexed() const {
1477     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1478   }
1479   bool isDoubleSpacedVectorIndexed() const {
1480     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1481   }
1482   bool isVecListOneDByteIndexed() const {
1483     if (!isSingleSpacedVectorIndexed()) return false;
1484     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1485   }
1486 
1487   bool isVecListOneDHWordIndexed() const {
1488     if (!isSingleSpacedVectorIndexed()) return false;
1489     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1490   }
1491 
1492   bool isVecListOneDWordIndexed() const {
1493     if (!isSingleSpacedVectorIndexed()) return false;
1494     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1495   }
1496 
1497   bool isVecListTwoDByteIndexed() const {
1498     if (!isSingleSpacedVectorIndexed()) return false;
1499     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1500   }
1501 
1502   bool isVecListTwoDHWordIndexed() const {
1503     if (!isSingleSpacedVectorIndexed()) return false;
1504     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1505   }
1506 
1507   bool isVecListTwoQWordIndexed() const {
1508     if (!isDoubleSpacedVectorIndexed()) return false;
1509     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1510   }
1511 
1512   bool isVecListTwoQHWordIndexed() const {
1513     if (!isDoubleSpacedVectorIndexed()) return false;
1514     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1515   }
1516 
1517   bool isVecListTwoDWordIndexed() const {
1518     if (!isSingleSpacedVectorIndexed()) return false;
1519     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1520   }
1521 
1522   bool isVecListThreeDByteIndexed() const {
1523     if (!isSingleSpacedVectorIndexed()) return false;
1524     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1525   }
1526 
1527   bool isVecListThreeDHWordIndexed() const {
1528     if (!isSingleSpacedVectorIndexed()) return false;
1529     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1530   }
1531 
1532   bool isVecListThreeQWordIndexed() const {
1533     if (!isDoubleSpacedVectorIndexed()) return false;
1534     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1535   }
1536 
1537   bool isVecListThreeQHWordIndexed() const {
1538     if (!isDoubleSpacedVectorIndexed()) return false;
1539     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1540   }
1541 
1542   bool isVecListThreeDWordIndexed() const {
1543     if (!isSingleSpacedVectorIndexed()) return false;
1544     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1545   }
1546 
1547   bool isVecListFourDByteIndexed() const {
1548     if (!isSingleSpacedVectorIndexed()) return false;
1549     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1550   }
1551 
1552   bool isVecListFourDHWordIndexed() const {
1553     if (!isSingleSpacedVectorIndexed()) return false;
1554     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1555   }
1556 
1557   bool isVecListFourQWordIndexed() const {
1558     if (!isDoubleSpacedVectorIndexed()) return false;
1559     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1560   }
1561 
1562   bool isVecListFourQHWordIndexed() const {
1563     if (!isDoubleSpacedVectorIndexed()) return false;
1564     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1565   }
1566 
1567   bool isVecListFourDWordIndexed() const {
1568     if (!isSingleSpacedVectorIndexed()) return false;
1569     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1570   }
1571 
1572   bool isVectorIndex8() const {
1573     if (Kind != k_VectorIndex) return false;
1574     return VectorIndex.Val < 8;
1575   }
1576   bool isVectorIndex16() const {
1577     if (Kind != k_VectorIndex) return false;
1578     return VectorIndex.Val < 4;
1579   }
1580   bool isVectorIndex32() const {
1581     if (Kind != k_VectorIndex) return false;
1582     return VectorIndex.Val < 2;
1583   }
1584 
1585   bool isNEONi8splat() const {
1586     if (!isImm()) return false;
1587     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1588     // Must be a constant.
1589     if (!CE) return false;
1590     int64_t Value = CE->getValue();
1591     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1592     // value.
1593     return Value >= 0 && Value < 256;
1594   }
1595 
1596   bool isNEONi16splat() const {
1597     if (isNEONByteReplicate(2))
1598       return false; // Leave that for bytes replication and forbid by default.
1599     if (!isImm())
1600       return false;
1601     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602     // Must be a constant.
1603     if (!CE) return false;
1604     int64_t Value = CE->getValue();
1605     // i16 value in the range [0,255] or [0x0100, 0xff00]
1606     return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1607   }
1608 
1609   bool isNEONi32splat() const {
1610     if (isNEONByteReplicate(4))
1611       return false; // Leave that for bytes replication and forbid by default.
1612     if (!isImm())
1613       return false;
1614     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1615     // Must be a constant.
1616     if (!CE) return false;
1617     int64_t Value = CE->getValue();
1618     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1619     return (Value >= 0 && Value < 256) ||
1620       (Value >= 0x0100 && Value <= 0xff00) ||
1621       (Value >= 0x010000 && Value <= 0xff0000) ||
1622       (Value >= 0x01000000 && Value <= 0xff000000);
1623   }
1624 
1625   bool isNEONByteReplicate(unsigned NumBytes) const {
1626     if (!isImm())
1627       return false;
1628     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1629     // Must be a constant.
1630     if (!CE)
1631       return false;
1632     int64_t Value = CE->getValue();
1633     if (!Value)
1634       return false; // Don't bother with zero.
1635 
1636     unsigned char B = Value & 0xff;
1637     for (unsigned i = 1; i < NumBytes; ++i) {
1638       Value >>= 8;
1639       if ((Value & 0xff) != B)
1640         return false;
1641     }
1642     return true;
1643   }
1644   bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1645   bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1646   bool isNEONi32vmov() const {
1647     if (isNEONByteReplicate(4))
1648       return false; // Let it to be classified as byte-replicate case.
1649     if (!isImm())
1650       return false;
1651     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1652     // Must be a constant.
1653     if (!CE)
1654       return false;
1655     int64_t Value = CE->getValue();
1656     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1657     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1658     return (Value >= 0 && Value < 256) ||
1659       (Value >= 0x0100 && Value <= 0xff00) ||
1660       (Value >= 0x010000 && Value <= 0xff0000) ||
1661       (Value >= 0x01000000 && Value <= 0xff000000) ||
1662       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1663       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1664   }
1665   bool isNEONi32vmovNeg() const {
1666     if (!isImm()) return false;
1667     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668     // Must be a constant.
1669     if (!CE) return false;
1670     int64_t Value = ~CE->getValue();
1671     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1672     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1673     return (Value >= 0 && Value < 256) ||
1674       (Value >= 0x0100 && Value <= 0xff00) ||
1675       (Value >= 0x010000 && Value <= 0xff0000) ||
1676       (Value >= 0x01000000 && Value <= 0xff000000) ||
1677       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1678       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1679   }
1680 
1681   bool isNEONi64splat() const {
1682     if (!isImm()) return false;
1683     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1684     // Must be a constant.
1685     if (!CE) return false;
1686     uint64_t Value = CE->getValue();
1687     // i64 value with each byte being either 0 or 0xff.
1688     for (unsigned i = 0; i < 8; ++i)
1689       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1690     return true;
1691   }
1692 
1693   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1694     // Add as immediates when possible.  Null MCExpr = 0.
1695     if (!Expr)
1696       Inst.addOperand(MCOperand::CreateImm(0));
1697     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1698       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1699     else
1700       Inst.addOperand(MCOperand::CreateExpr(Expr));
1701   }
1702 
1703   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1704     assert(N == 2 && "Invalid number of operands!");
1705     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1706     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1707     Inst.addOperand(MCOperand::CreateReg(RegNum));
1708   }
1709 
1710   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1711     assert(N == 1 && "Invalid number of operands!");
1712     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1713   }
1714 
1715   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1716     assert(N == 1 && "Invalid number of operands!");
1717     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1718   }
1719 
1720   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1721     assert(N == 1 && "Invalid number of operands!");
1722     Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1723   }
1724 
1725   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1726     assert(N == 1 && "Invalid number of operands!");
1727     Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1728   }
1729 
1730   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1731     assert(N == 1 && "Invalid number of operands!");
1732     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1733   }
1734 
1735   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1736     assert(N == 1 && "Invalid number of operands!");
1737     Inst.addOperand(MCOperand::CreateReg(getReg()));
1738   }
1739 
1740   void addRegOperands(MCInst &Inst, unsigned N) const {
1741     assert(N == 1 && "Invalid number of operands!");
1742     Inst.addOperand(MCOperand::CreateReg(getReg()));
1743   }
1744 
1745   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1746     assert(N == 3 && "Invalid number of operands!");
1747     assert(isRegShiftedReg() &&
1748            "addRegShiftedRegOperands() on non-RegShiftedReg!");
1749     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1750     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1751     Inst.addOperand(MCOperand::CreateImm(
1752       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1753   }
1754 
1755   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1756     assert(N == 2 && "Invalid number of operands!");
1757     assert(isRegShiftedImm() &&
1758            "addRegShiftedImmOperands() on non-RegShiftedImm!");
1759     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1760     // Shift of #32 is encoded as 0 where permitted
1761     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1762     Inst.addOperand(MCOperand::CreateImm(
1763       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1764   }
1765 
1766   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1767     assert(N == 1 && "Invalid number of operands!");
1768     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1769                                          ShifterImm.Imm));
1770   }
1771 
1772   void addRegListOperands(MCInst &Inst, unsigned N) const {
1773     assert(N == 1 && "Invalid number of operands!");
1774     const SmallVectorImpl<unsigned> &RegList = getRegList();
1775     for (SmallVectorImpl<unsigned>::const_iterator
1776            I = RegList.begin(), E = RegList.end(); I != E; ++I)
1777       Inst.addOperand(MCOperand::CreateReg(*I));
1778   }
1779 
1780   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1781     addRegListOperands(Inst, N);
1782   }
1783 
1784   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1785     addRegListOperands(Inst, N);
1786   }
1787 
1788   void addRotImmOperands(MCInst &Inst, unsigned N) const {
1789     assert(N == 1 && "Invalid number of operands!");
1790     // Encoded as val>>3. The printer handles display as 8, 16, 24.
1791     Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1792   }
1793 
1794   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1795     assert(N == 1 && "Invalid number of operands!");
1796     // Munge the lsb/width into a bitfield mask.
1797     unsigned lsb = Bitfield.LSB;
1798     unsigned width = Bitfield.Width;
1799     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1800     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1801                       (32 - (lsb + width)));
1802     Inst.addOperand(MCOperand::CreateImm(Mask));
1803   }
1804 
1805   void addImmOperands(MCInst &Inst, unsigned N) const {
1806     assert(N == 1 && "Invalid number of operands!");
1807     addExpr(Inst, getImm());
1808   }
1809 
1810   void addFBits16Operands(MCInst &Inst, unsigned N) const {
1811     assert(N == 1 && "Invalid number of operands!");
1812     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1813     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1814   }
1815 
1816   void addFBits32Operands(MCInst &Inst, unsigned N) const {
1817     assert(N == 1 && "Invalid number of operands!");
1818     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1819     Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1820   }
1821 
1822   void addFPImmOperands(MCInst &Inst, unsigned N) const {
1823     assert(N == 1 && "Invalid number of operands!");
1824     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1825     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1826     Inst.addOperand(MCOperand::CreateImm(Val));
1827   }
1828 
1829   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1830     assert(N == 1 && "Invalid number of operands!");
1831     // FIXME: We really want to scale the value here, but the LDRD/STRD
1832     // instruction don't encode operands that way yet.
1833     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1834     Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1835   }
1836 
1837   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1838     assert(N == 1 && "Invalid number of operands!");
1839     // The immediate is scaled by four in the encoding and is stored
1840     // in the MCInst as such. Lop off the low two bits here.
1841     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1842     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1843   }
1844 
1845   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1846     assert(N == 1 && "Invalid number of operands!");
1847     // The immediate is scaled by four in the encoding and is stored
1848     // in the MCInst as such. Lop off the low two bits here.
1849     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1850     Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1851   }
1852 
1853   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1854     assert(N == 1 && "Invalid number of operands!");
1855     // The immediate is scaled by four in the encoding and is stored
1856     // in the MCInst as such. Lop off the low two bits here.
1857     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1858     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1859   }
1860 
1861   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1862     assert(N == 1 && "Invalid number of operands!");
1863     // The constant encodes as the immediate-1, and we store in the instruction
1864     // the bits as encoded, so subtract off one here.
1865     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1866     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1867   }
1868 
1869   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1870     assert(N == 1 && "Invalid number of operands!");
1871     // The constant encodes as the immediate-1, and we store in the instruction
1872     // the bits as encoded, so subtract off one here.
1873     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1874     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1875   }
1876 
1877   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1878     assert(N == 1 && "Invalid number of operands!");
1879     // The constant encodes as the immediate, except for 32, which encodes as
1880     // zero.
1881     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1882     unsigned Imm = CE->getValue();
1883     Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1884   }
1885 
1886   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1887     assert(N == 1 && "Invalid number of operands!");
1888     // An ASR value of 32 encodes as 0, so that's how we want to add it to
1889     // the instruction as well.
1890     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1891     int Val = CE->getValue();
1892     Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1893   }
1894 
1895   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1896     assert(N == 1 && "Invalid number of operands!");
1897     // The operand is actually a t2_so_imm, but we have its bitwise
1898     // negation in the assembly source, so twiddle it here.
1899     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1900     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1901   }
1902 
1903   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1904     assert(N == 1 && "Invalid number of operands!");
1905     // The operand is actually a t2_so_imm, but we have its
1906     // negation in the assembly source, so twiddle it here.
1907     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1908     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1909   }
1910 
1911   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1912     assert(N == 1 && "Invalid number of operands!");
1913     // The operand is actually an imm0_4095, but we have its
1914     // negation in the assembly source, so twiddle it here.
1915     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1916     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1917   }
1918 
1919   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1920     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1921       Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1922       return;
1923     }
1924 
1925     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1926     assert(SR && "Unknown value type!");
1927     Inst.addOperand(MCOperand::CreateExpr(SR));
1928   }
1929 
1930   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1931     assert(N == 1 && "Invalid number of operands!");
1932     if (isImm()) {
1933       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1934       if (CE) {
1935         Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1936         return;
1937       }
1938 
1939       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1940       assert(SR && "Unknown value type!");
1941       Inst.addOperand(MCOperand::CreateExpr(SR));
1942       return;
1943     }
1944 
1945     assert(isMem()  && "Unknown value type!");
1946     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1947     Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1948   }
1949 
1950   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1951     assert(N == 1 && "Invalid number of operands!");
1952     // The operand is actually a so_imm, but we have its bitwise
1953     // negation in the assembly source, so twiddle it here.
1954     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1955     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1956   }
1957 
1958   void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1959     assert(N == 1 && "Invalid number of operands!");
1960     // The operand is actually a so_imm, but we have its
1961     // negation in the assembly source, so twiddle it here.
1962     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1963     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1964   }
1965 
1966   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1967     assert(N == 1 && "Invalid number of operands!");
1968     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1969   }
1970 
1971   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1972     assert(N == 1 && "Invalid number of operands!");
1973     Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1974   }
1975 
1976   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1977     assert(N == 1 && "Invalid number of operands!");
1978     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1979   }
1980 
1981   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1982     assert(N == 1 && "Invalid number of operands!");
1983     int32_t Imm = Memory.OffsetImm->getValue();
1984     Inst.addOperand(MCOperand::CreateImm(Imm));
1985   }
1986 
1987   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1988     assert(N == 1 && "Invalid number of operands!");
1989     assert(isImm() && "Not an immediate!");
1990 
1991     // If we have an immediate that's not a constant, treat it as a label
1992     // reference needing a fixup.
1993     if (!isa<MCConstantExpr>(getImm())) {
1994       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1995       return;
1996     }
1997 
1998     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1999     int Val = CE->getValue();
2000     Inst.addOperand(MCOperand::CreateImm(Val));
2001   }
2002 
2003   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2004     assert(N == 2 && "Invalid number of operands!");
2005     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2006     Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2007   }
2008 
2009   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2010     addAlignedMemoryOperands(Inst, N);
2011   }
2012 
2013   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2014     addAlignedMemoryOperands(Inst, N);
2015   }
2016 
2017   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2018     addAlignedMemoryOperands(Inst, N);
2019   }
2020 
2021   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2022     addAlignedMemoryOperands(Inst, N);
2023   }
2024 
2025   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2026     addAlignedMemoryOperands(Inst, N);
2027   }
2028 
2029   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2030     addAlignedMemoryOperands(Inst, N);
2031   }
2032 
2033   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2034     addAlignedMemoryOperands(Inst, N);
2035   }
2036 
2037   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2038     addAlignedMemoryOperands(Inst, N);
2039   }
2040 
2041   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2042     addAlignedMemoryOperands(Inst, N);
2043   }
2044 
2045   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2046     addAlignedMemoryOperands(Inst, N);
2047   }
2048 
2049   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2050     addAlignedMemoryOperands(Inst, N);
2051   }
2052 
2053   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2054     assert(N == 3 && "Invalid number of operands!");
2055     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2056     if (!Memory.OffsetRegNum) {
2057       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2058       // Special case for #-0
2059       if (Val == INT32_MIN) Val = 0;
2060       if (Val < 0) Val = -Val;
2061       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2062     } else {
2063       // For register offset, we encode the shift type and negation flag
2064       // here.
2065       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2066                               Memory.ShiftImm, Memory.ShiftType);
2067     }
2068     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2069     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2070     Inst.addOperand(MCOperand::CreateImm(Val));
2071   }
2072 
2073   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2074     assert(N == 2 && "Invalid number of operands!");
2075     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2076     assert(CE && "non-constant AM2OffsetImm operand!");
2077     int32_t Val = CE->getValue();
2078     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2079     // Special case for #-0
2080     if (Val == INT32_MIN) Val = 0;
2081     if (Val < 0) Val = -Val;
2082     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2083     Inst.addOperand(MCOperand::CreateReg(0));
2084     Inst.addOperand(MCOperand::CreateImm(Val));
2085   }
2086 
2087   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2088     assert(N == 3 && "Invalid number of operands!");
2089     // If we have an immediate that's not a constant, treat it as a label
2090     // reference needing a fixup. If it is a constant, it's something else
2091     // and we reject it.
2092     if (isImm()) {
2093       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2094       Inst.addOperand(MCOperand::CreateReg(0));
2095       Inst.addOperand(MCOperand::CreateImm(0));
2096       return;
2097     }
2098 
2099     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2100     if (!Memory.OffsetRegNum) {
2101       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2102       // Special case for #-0
2103       if (Val == INT32_MIN) Val = 0;
2104       if (Val < 0) Val = -Val;
2105       Val = ARM_AM::getAM3Opc(AddSub, Val);
2106     } else {
2107       // For register offset, we encode the shift type and negation flag
2108       // here.
2109       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2110     }
2111     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2112     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2113     Inst.addOperand(MCOperand::CreateImm(Val));
2114   }
2115 
2116   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2117     assert(N == 2 && "Invalid number of operands!");
2118     if (Kind == k_PostIndexRegister) {
2119       int32_t Val =
2120         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2121       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2122       Inst.addOperand(MCOperand::CreateImm(Val));
2123       return;
2124     }
2125 
2126     // Constant offset.
2127     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2128     int32_t Val = CE->getValue();
2129     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2130     // Special case for #-0
2131     if (Val == INT32_MIN) Val = 0;
2132     if (Val < 0) Val = -Val;
2133     Val = ARM_AM::getAM3Opc(AddSub, Val);
2134     Inst.addOperand(MCOperand::CreateReg(0));
2135     Inst.addOperand(MCOperand::CreateImm(Val));
2136   }
2137 
2138   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2139     assert(N == 2 && "Invalid number of operands!");
2140     // If we have an immediate that's not a constant, treat it as a label
2141     // reference needing a fixup. If it is a constant, it's something else
2142     // and we reject it.
2143     if (isImm()) {
2144       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2145       Inst.addOperand(MCOperand::CreateImm(0));
2146       return;
2147     }
2148 
2149     // The lower two bits are always zero and as such are not encoded.
2150     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2151     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2152     // Special case for #-0
2153     if (Val == INT32_MIN) Val = 0;
2154     if (Val < 0) Val = -Val;
2155     Val = ARM_AM::getAM5Opc(AddSub, Val);
2156     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2157     Inst.addOperand(MCOperand::CreateImm(Val));
2158   }
2159 
2160   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2161     assert(N == 2 && "Invalid number of operands!");
2162     // If we have an immediate that's not a constant, treat it as a label
2163     // reference needing a fixup. If it is a constant, it's something else
2164     // and we reject it.
2165     if (isImm()) {
2166       Inst.addOperand(MCOperand::CreateExpr(getImm()));
2167       Inst.addOperand(MCOperand::CreateImm(0));
2168       return;
2169     }
2170 
2171     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2172     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2173     Inst.addOperand(MCOperand::CreateImm(Val));
2174   }
2175 
2176   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2177     assert(N == 2 && "Invalid number of operands!");
2178     // The lower two bits are always zero and as such are not encoded.
2179     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2180     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2181     Inst.addOperand(MCOperand::CreateImm(Val));
2182   }
2183 
2184   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2185     assert(N == 2 && "Invalid number of operands!");
2186     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2187     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2188     Inst.addOperand(MCOperand::CreateImm(Val));
2189   }
2190 
2191   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2192     addMemImm8OffsetOperands(Inst, N);
2193   }
2194 
2195   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2196     addMemImm8OffsetOperands(Inst, N);
2197   }
2198 
2199   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2200     assert(N == 2 && "Invalid number of operands!");
2201     // If this is an immediate, it's a label reference.
2202     if (isImm()) {
2203       addExpr(Inst, getImm());
2204       Inst.addOperand(MCOperand::CreateImm(0));
2205       return;
2206     }
2207 
2208     // Otherwise, it's a normal memory reg+offset.
2209     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2210     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2211     Inst.addOperand(MCOperand::CreateImm(Val));
2212   }
2213 
2214   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2215     assert(N == 2 && "Invalid number of operands!");
2216     // If this is an immediate, it's a label reference.
2217     if (isImm()) {
2218       addExpr(Inst, getImm());
2219       Inst.addOperand(MCOperand::CreateImm(0));
2220       return;
2221     }
2222 
2223     // Otherwise, it's a normal memory reg+offset.
2224     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2225     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2226     Inst.addOperand(MCOperand::CreateImm(Val));
2227   }
2228 
2229   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2230     assert(N == 2 && "Invalid number of operands!");
2231     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2232     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2233   }
2234 
2235   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2236     assert(N == 2 && "Invalid number of operands!");
2237     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2238     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2239   }
2240 
2241   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2242     assert(N == 3 && "Invalid number of operands!");
2243     unsigned Val =
2244       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2245                         Memory.ShiftImm, Memory.ShiftType);
2246     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2247     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2248     Inst.addOperand(MCOperand::CreateImm(Val));
2249   }
2250 
2251   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2252     assert(N == 3 && "Invalid number of operands!");
2253     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2254     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2255     Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2256   }
2257 
2258   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2259     assert(N == 2 && "Invalid number of operands!");
2260     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2261     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2262   }
2263 
2264   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2265     assert(N == 2 && "Invalid number of operands!");
2266     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2267     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2268     Inst.addOperand(MCOperand::CreateImm(Val));
2269   }
2270 
2271   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2272     assert(N == 2 && "Invalid number of operands!");
2273     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2274     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2275     Inst.addOperand(MCOperand::CreateImm(Val));
2276   }
2277 
2278   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2279     assert(N == 2 && "Invalid number of operands!");
2280     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2281     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2282     Inst.addOperand(MCOperand::CreateImm(Val));
2283   }
2284 
2285   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2286     assert(N == 2 && "Invalid number of operands!");
2287     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2288     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2289     Inst.addOperand(MCOperand::CreateImm(Val));
2290   }
2291 
2292   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2293     assert(N == 1 && "Invalid number of operands!");
2294     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2295     assert(CE && "non-constant post-idx-imm8 operand!");
2296     int Imm = CE->getValue();
2297     bool isAdd = Imm >= 0;
2298     if (Imm == INT32_MIN) Imm = 0;
2299     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2300     Inst.addOperand(MCOperand::CreateImm(Imm));
2301   }
2302 
2303   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2304     assert(N == 1 && "Invalid number of operands!");
2305     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2306     assert(CE && "non-constant post-idx-imm8s4 operand!");
2307     int Imm = CE->getValue();
2308     bool isAdd = Imm >= 0;
2309     if (Imm == INT32_MIN) Imm = 0;
2310     // Immediate is scaled by 4.
2311     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2312     Inst.addOperand(MCOperand::CreateImm(Imm));
2313   }
2314 
2315   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2316     assert(N == 2 && "Invalid number of operands!");
2317     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2318     Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2319   }
2320 
2321   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2322     assert(N == 2 && "Invalid number of operands!");
2323     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2324     // The sign, shift type, and shift amount are encoded in a single operand
2325     // using the AM2 encoding helpers.
2326     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2327     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2328                                      PostIdxReg.ShiftTy);
2329     Inst.addOperand(MCOperand::CreateImm(Imm));
2330   }
2331 
2332   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2333     assert(N == 1 && "Invalid number of operands!");
2334     Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2335   }
2336 
2337   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2338     assert(N == 1 && "Invalid number of operands!");
2339     Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2340   }
2341 
2342   void addVecListOperands(MCInst &Inst, unsigned N) const {
2343     assert(N == 1 && "Invalid number of operands!");
2344     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2345   }
2346 
2347   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2348     assert(N == 2 && "Invalid number of operands!");
2349     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2350     Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2351   }
2352 
2353   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2354     assert(N == 1 && "Invalid number of operands!");
2355     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2356   }
2357 
2358   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2359     assert(N == 1 && "Invalid number of operands!");
2360     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2361   }
2362 
2363   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2364     assert(N == 1 && "Invalid number of operands!");
2365     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2366   }
2367 
2368   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2369     assert(N == 1 && "Invalid number of operands!");
2370     // The immediate encodes the type of constant as well as the value.
2371     // Mask in that this is an i8 splat.
2372     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2373     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2374   }
2375 
2376   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2377     assert(N == 1 && "Invalid number of operands!");
2378     // The immediate encodes the type of constant as well as the value.
2379     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2380     unsigned Value = CE->getValue();
2381     if (Value >= 256)
2382       Value = (Value >> 8) | 0xa00;
2383     else
2384       Value |= 0x800;
2385     Inst.addOperand(MCOperand::CreateImm(Value));
2386   }
2387 
2388   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2389     assert(N == 1 && "Invalid number of operands!");
2390     // The immediate encodes the type of constant as well as the value.
2391     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2392     unsigned Value = CE->getValue();
2393     if (Value >= 256 && Value <= 0xff00)
2394       Value = (Value >> 8) | 0x200;
2395     else if (Value > 0xffff && Value <= 0xff0000)
2396       Value = (Value >> 16) | 0x400;
2397     else if (Value > 0xffffff)
2398       Value = (Value >> 24) | 0x600;
2399     Inst.addOperand(MCOperand::CreateImm(Value));
2400   }
2401 
2402   void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2403     assert(N == 1 && "Invalid number of operands!");
2404     // The immediate encodes the type of constant as well as the value.
2405     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2406     unsigned Value = CE->getValue();
2407     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2408             Inst.getOpcode() == ARM::VMOVv16i8) &&
2409            "All vmvn instructions that wants to replicate non-zero byte "
2410            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2411     unsigned B = ((~Value) & 0xff);
2412     B |= 0xe00; // cmode = 0b1110
2413     Inst.addOperand(MCOperand::CreateImm(B));
2414   }
2415   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2416     assert(N == 1 && "Invalid number of operands!");
2417     // The immediate encodes the type of constant as well as the value.
2418     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2419     unsigned Value = CE->getValue();
2420     if (Value >= 256 && Value <= 0xffff)
2421       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2422     else if (Value > 0xffff && Value <= 0xffffff)
2423       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2424     else if (Value > 0xffffff)
2425       Value = (Value >> 24) | 0x600;
2426     Inst.addOperand(MCOperand::CreateImm(Value));
2427   }
2428 
2429   void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2430     assert(N == 1 && "Invalid number of operands!");
2431     // The immediate encodes the type of constant as well as the value.
2432     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2433     unsigned Value = CE->getValue();
2434     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2435             Inst.getOpcode() == ARM::VMOVv16i8) &&
2436            "All instructions that wants to replicate non-zero byte "
2437            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2438     unsigned B = Value & 0xff;
2439     B |= 0xe00; // cmode = 0b1110
2440     Inst.addOperand(MCOperand::CreateImm(B));
2441   }
2442   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2443     assert(N == 1 && "Invalid number of operands!");
2444     // The immediate encodes the type of constant as well as the value.
2445     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2446     unsigned Value = ~CE->getValue();
2447     if (Value >= 256 && Value <= 0xffff)
2448       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2449     else if (Value > 0xffff && Value <= 0xffffff)
2450       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2451     else if (Value > 0xffffff)
2452       Value = (Value >> 24) | 0x600;
2453     Inst.addOperand(MCOperand::CreateImm(Value));
2454   }
2455 
2456   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2457     assert(N == 1 && "Invalid number of operands!");
2458     // The immediate encodes the type of constant as well as the value.
2459     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2460     uint64_t Value = CE->getValue();
2461     unsigned Imm = 0;
2462     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2463       Imm |= (Value & 1) << i;
2464     }
2465     Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2466   }
2467 
2468   void print(raw_ostream &OS) const override;
2469 
2470   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2471     auto Op = make_unique<ARMOperand>(k_ITCondMask);
2472     Op->ITMask.Mask = Mask;
2473     Op->StartLoc = S;
2474     Op->EndLoc = S;
2475     return Op;
2476   }
2477 
2478   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2479                                                     SMLoc S) {
2480     auto Op = make_unique<ARMOperand>(k_CondCode);
2481     Op->CC.Val = CC;
2482     Op->StartLoc = S;
2483     Op->EndLoc = S;
2484     return Op;
2485   }
2486 
2487   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2488     auto Op = make_unique<ARMOperand>(k_CoprocNum);
2489     Op->Cop.Val = CopVal;
2490     Op->StartLoc = S;
2491     Op->EndLoc = S;
2492     return Op;
2493   }
2494 
2495   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2496     auto Op = make_unique<ARMOperand>(k_CoprocReg);
2497     Op->Cop.Val = CopVal;
2498     Op->StartLoc = S;
2499     Op->EndLoc = S;
2500     return Op;
2501   }
2502 
2503   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2504                                                         SMLoc E) {
2505     auto Op = make_unique<ARMOperand>(k_CoprocOption);
2506     Op->Cop.Val = Val;
2507     Op->StartLoc = S;
2508     Op->EndLoc = E;
2509     return Op;
2510   }
2511 
2512   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2513     auto Op = make_unique<ARMOperand>(k_CCOut);
2514     Op->Reg.RegNum = RegNum;
2515     Op->StartLoc = S;
2516     Op->EndLoc = S;
2517     return Op;
2518   }
2519 
2520   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2521     auto Op = make_unique<ARMOperand>(k_Token);
2522     Op->Tok.Data = Str.data();
2523     Op->Tok.Length = Str.size();
2524     Op->StartLoc = S;
2525     Op->EndLoc = S;
2526     return Op;
2527   }
2528 
2529   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2530                                                SMLoc E) {
2531     auto Op = make_unique<ARMOperand>(k_Register);
2532     Op->Reg.RegNum = RegNum;
2533     Op->StartLoc = S;
2534     Op->EndLoc = E;
2535     return Op;
2536   }
2537 
2538   static std::unique_ptr<ARMOperand>
2539   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2540                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2541                         SMLoc E) {
2542     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2543     Op->RegShiftedReg.ShiftTy = ShTy;
2544     Op->RegShiftedReg.SrcReg = SrcReg;
2545     Op->RegShiftedReg.ShiftReg = ShiftReg;
2546     Op->RegShiftedReg.ShiftImm = ShiftImm;
2547     Op->StartLoc = S;
2548     Op->EndLoc = E;
2549     return Op;
2550   }
2551 
2552   static std::unique_ptr<ARMOperand>
2553   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2554                          unsigned ShiftImm, SMLoc S, SMLoc E) {
2555     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2556     Op->RegShiftedImm.ShiftTy = ShTy;
2557     Op->RegShiftedImm.SrcReg = SrcReg;
2558     Op->RegShiftedImm.ShiftImm = ShiftImm;
2559     Op->StartLoc = S;
2560     Op->EndLoc = E;
2561     return Op;
2562   }
2563 
2564   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2565                                                       SMLoc S, SMLoc E) {
2566     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2567     Op->ShifterImm.isASR = isASR;
2568     Op->ShifterImm.Imm = Imm;
2569     Op->StartLoc = S;
2570     Op->EndLoc = E;
2571     return Op;
2572   }
2573 
2574   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2575                                                   SMLoc E) {
2576     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2577     Op->RotImm.Imm = Imm;
2578     Op->StartLoc = S;
2579     Op->EndLoc = E;
2580     return Op;
2581   }
2582 
2583   static std::unique_ptr<ARMOperand>
2584   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2585     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2586     Op->Bitfield.LSB = LSB;
2587     Op->Bitfield.Width = Width;
2588     Op->StartLoc = S;
2589     Op->EndLoc = E;
2590     return Op;
2591   }
2592 
2593   static std::unique_ptr<ARMOperand>
2594   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2595                 SMLoc StartLoc, SMLoc EndLoc) {
2596     assert (Regs.size() > 0 && "RegList contains no registers?");
2597     KindTy Kind = k_RegisterList;
2598 
2599     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2600       Kind = k_DPRRegisterList;
2601     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2602              contains(Regs.front().second))
2603       Kind = k_SPRRegisterList;
2604 
2605     // Sort based on the register encoding values.
2606     array_pod_sort(Regs.begin(), Regs.end());
2607 
2608     auto Op = make_unique<ARMOperand>(Kind);
2609     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2610            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2611       Op->Registers.push_back(I->second);
2612     Op->StartLoc = StartLoc;
2613     Op->EndLoc = EndLoc;
2614     return Op;
2615   }
2616 
2617   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2618                                                       unsigned Count,
2619                                                       bool isDoubleSpaced,
2620                                                       SMLoc S, SMLoc E) {
2621     auto Op = make_unique<ARMOperand>(k_VectorList);
2622     Op->VectorList.RegNum = RegNum;
2623     Op->VectorList.Count = Count;
2624     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2625     Op->StartLoc = S;
2626     Op->EndLoc = E;
2627     return Op;
2628   }
2629 
2630   static std::unique_ptr<ARMOperand>
2631   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2632                            SMLoc S, SMLoc E) {
2633     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2634     Op->VectorList.RegNum = RegNum;
2635     Op->VectorList.Count = Count;
2636     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2637     Op->StartLoc = S;
2638     Op->EndLoc = E;
2639     return Op;
2640   }
2641 
2642   static std::unique_ptr<ARMOperand>
2643   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2644                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
2645     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2646     Op->VectorList.RegNum = RegNum;
2647     Op->VectorList.Count = Count;
2648     Op->VectorList.LaneIndex = Index;
2649     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2650     Op->StartLoc = S;
2651     Op->EndLoc = E;
2652     return Op;
2653   }
2654 
2655   static std::unique_ptr<ARMOperand>
2656   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2657     auto Op = make_unique<ARMOperand>(k_VectorIndex);
2658     Op->VectorIndex.Val = Idx;
2659     Op->StartLoc = S;
2660     Op->EndLoc = E;
2661     return Op;
2662   }
2663 
2664   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2665                                                SMLoc E) {
2666     auto Op = make_unique<ARMOperand>(k_Immediate);
2667     Op->Imm.Val = Val;
2668     Op->StartLoc = S;
2669     Op->EndLoc = E;
2670     return Op;
2671   }
2672 
2673   static std::unique_ptr<ARMOperand>
2674   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2675             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2676             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2677             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2678     auto Op = make_unique<ARMOperand>(k_Memory);
2679     Op->Memory.BaseRegNum = BaseRegNum;
2680     Op->Memory.OffsetImm = OffsetImm;
2681     Op->Memory.OffsetRegNum = OffsetRegNum;
2682     Op->Memory.ShiftType = ShiftType;
2683     Op->Memory.ShiftImm = ShiftImm;
2684     Op->Memory.Alignment = Alignment;
2685     Op->Memory.isNegative = isNegative;
2686     Op->StartLoc = S;
2687     Op->EndLoc = E;
2688     Op->AlignmentLoc = AlignmentLoc;
2689     return Op;
2690   }
2691 
2692   static std::unique_ptr<ARMOperand>
2693   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2694                    unsigned ShiftImm, SMLoc S, SMLoc E) {
2695     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2696     Op->PostIdxReg.RegNum = RegNum;
2697     Op->PostIdxReg.isAdd = isAdd;
2698     Op->PostIdxReg.ShiftTy = ShiftTy;
2699     Op->PostIdxReg.ShiftImm = ShiftImm;
2700     Op->StartLoc = S;
2701     Op->EndLoc = E;
2702     return Op;
2703   }
2704 
2705   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2706                                                          SMLoc S) {
2707     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2708     Op->MBOpt.Val = Opt;
2709     Op->StartLoc = S;
2710     Op->EndLoc = S;
2711     return Op;
2712   }
2713 
2714   static std::unique_ptr<ARMOperand>
2715   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2716     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2717     Op->ISBOpt.Val = Opt;
2718     Op->StartLoc = S;
2719     Op->EndLoc = S;
2720     return Op;
2721   }
2722 
2723   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2724                                                       SMLoc S) {
2725     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2726     Op->IFlags.Val = IFlags;
2727     Op->StartLoc = S;
2728     Op->EndLoc = S;
2729     return Op;
2730   }
2731 
2732   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2733     auto Op = make_unique<ARMOperand>(k_MSRMask);
2734     Op->MMask.Val = MMask;
2735     Op->StartLoc = S;
2736     Op->EndLoc = S;
2737     return Op;
2738   }
2739 };
2740 
2741 } // end anonymous namespace.
2742 
2743 void ARMOperand::print(raw_ostream &OS) const {
2744   switch (Kind) {
2745   case k_CondCode:
2746     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2747     break;
2748   case k_CCOut:
2749     OS << "<ccout " << getReg() << ">";
2750     break;
2751   case k_ITCondMask: {
2752     static const char *const MaskStr[] = {
2753       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2754       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2755     };
2756     assert((ITMask.Mask & 0xf) == ITMask.Mask);
2757     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2758     break;
2759   }
2760   case k_CoprocNum:
2761     OS << "<coprocessor number: " << getCoproc() << ">";
2762     break;
2763   case k_CoprocReg:
2764     OS << "<coprocessor register: " << getCoproc() << ">";
2765     break;
2766   case k_CoprocOption:
2767     OS << "<coprocessor option: " << CoprocOption.Val << ">";
2768     break;
2769   case k_MSRMask:
2770     OS << "<mask: " << getMSRMask() << ">";
2771     break;
2772   case k_Immediate:
2773     getImm()->print(OS);
2774     break;
2775   case k_MemBarrierOpt:
2776     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2777     break;
2778   case k_InstSyncBarrierOpt:
2779     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2780     break;
2781   case k_Memory:
2782     OS << "<memory "
2783        << " base:" << Memory.BaseRegNum;
2784     OS << ">";
2785     break;
2786   case k_PostIndexRegister:
2787     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2788        << PostIdxReg.RegNum;
2789     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2790       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2791          << PostIdxReg.ShiftImm;
2792     OS << ">";
2793     break;
2794   case k_ProcIFlags: {
2795     OS << "<ARM_PROC::";
2796     unsigned IFlags = getProcIFlags();
2797     for (int i=2; i >= 0; --i)
2798       if (IFlags & (1 << i))
2799         OS << ARM_PROC::IFlagsToString(1 << i);
2800     OS << ">";
2801     break;
2802   }
2803   case k_Register:
2804     OS << "<register " << getReg() << ">";
2805     break;
2806   case k_ShifterImmediate:
2807     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2808        << " #" << ShifterImm.Imm << ">";
2809     break;
2810   case k_ShiftedRegister:
2811     OS << "<so_reg_reg "
2812        << RegShiftedReg.SrcReg << " "
2813        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2814        << " " << RegShiftedReg.ShiftReg << ">";
2815     break;
2816   case k_ShiftedImmediate:
2817     OS << "<so_reg_imm "
2818        << RegShiftedImm.SrcReg << " "
2819        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2820        << " #" << RegShiftedImm.ShiftImm << ">";
2821     break;
2822   case k_RotateImmediate:
2823     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2824     break;
2825   case k_BitfieldDescriptor:
2826     OS << "<bitfield " << "lsb: " << Bitfield.LSB
2827        << ", width: " << Bitfield.Width << ">";
2828     break;
2829   case k_RegisterList:
2830   case k_DPRRegisterList:
2831   case k_SPRRegisterList: {
2832     OS << "<register_list ";
2833 
2834     const SmallVectorImpl<unsigned> &RegList = getRegList();
2835     for (SmallVectorImpl<unsigned>::const_iterator
2836            I = RegList.begin(), E = RegList.end(); I != E; ) {
2837       OS << *I;
2838       if (++I < E) OS << ", ";
2839     }
2840 
2841     OS << ">";
2842     break;
2843   }
2844   case k_VectorList:
2845     OS << "<vector_list " << VectorList.Count << " * "
2846        << VectorList.RegNum << ">";
2847     break;
2848   case k_VectorListAllLanes:
2849     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2850        << VectorList.RegNum << ">";
2851     break;
2852   case k_VectorListIndexed:
2853     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2854        << VectorList.Count << " * " << VectorList.RegNum << ">";
2855     break;
2856   case k_Token:
2857     OS << "'" << getToken() << "'";
2858     break;
2859   case k_VectorIndex:
2860     OS << "<vectorindex " << getVectorIndex() << ">";
2861     break;
2862   }
2863 }
2864 
2865 /// @name Auto-generated Match Functions
2866 /// {
2867 
2868 static unsigned MatchRegisterName(StringRef Name);
2869 
2870 /// }
2871 
2872 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2873                                  SMLoc &StartLoc, SMLoc &EndLoc) {
2874   StartLoc = Parser.getTok().getLoc();
2875   EndLoc = Parser.getTok().getEndLoc();
2876   RegNo = tryParseRegister();
2877 
2878   return (RegNo == (unsigned)-1);
2879 }
2880 
2881 /// Try to parse a register name.  The token must be an Identifier when called,
2882 /// and if it is a register name the token is eaten and the register number is
2883 /// returned.  Otherwise return -1.
2884 ///
2885 int ARMAsmParser::tryParseRegister() {
2886   const AsmToken &Tok = Parser.getTok();
2887   if (Tok.isNot(AsmToken::Identifier)) return -1;
2888 
2889   std::string lowerCase = Tok.getString().lower();
2890   unsigned RegNum = MatchRegisterName(lowerCase);
2891   if (!RegNum) {
2892     RegNum = StringSwitch<unsigned>(lowerCase)
2893       .Case("r13", ARM::SP)
2894       .Case("r14", ARM::LR)
2895       .Case("r15", ARM::PC)
2896       .Case("ip", ARM::R12)
2897       // Additional register name aliases for 'gas' compatibility.
2898       .Case("a1", ARM::R0)
2899       .Case("a2", ARM::R1)
2900       .Case("a3", ARM::R2)
2901       .Case("a4", ARM::R3)
2902       .Case("v1", ARM::R4)
2903       .Case("v2", ARM::R5)
2904       .Case("v3", ARM::R6)
2905       .Case("v4", ARM::R7)
2906       .Case("v5", ARM::R8)
2907       .Case("v6", ARM::R9)
2908       .Case("v7", ARM::R10)
2909       .Case("v8", ARM::R11)
2910       .Case("sb", ARM::R9)
2911       .Case("sl", ARM::R10)
2912       .Case("fp", ARM::R11)
2913       .Default(0);
2914   }
2915   if (!RegNum) {
2916     // Check for aliases registered via .req. Canonicalize to lower case.
2917     // That's more consistent since register names are case insensitive, and
2918     // it's how the original entry was passed in from MC/MCParser/AsmParser.
2919     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2920     // If no match, return failure.
2921     if (Entry == RegisterReqs.end())
2922       return -1;
2923     Parser.Lex(); // Eat identifier token.
2924     return Entry->getValue();
2925   }
2926 
2927   Parser.Lex(); // Eat identifier token.
2928 
2929   return RegNum;
2930 }
2931 
2932 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2933 // If a recoverable error occurs, return 1. If an irrecoverable error
2934 // occurs, return -1. An irrecoverable error is one where tokens have been
2935 // consumed in the process of trying to parse the shifter (i.e., when it is
2936 // indeed a shifter operand, but malformed).
2937 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
2938   SMLoc S = Parser.getTok().getLoc();
2939   const AsmToken &Tok = Parser.getTok();
2940   if (Tok.isNot(AsmToken::Identifier))
2941     return -1;
2942 
2943   std::string lowerCase = Tok.getString().lower();
2944   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2945       .Case("asl", ARM_AM::lsl)
2946       .Case("lsl", ARM_AM::lsl)
2947       .Case("lsr", ARM_AM::lsr)
2948       .Case("asr", ARM_AM::asr)
2949       .Case("ror", ARM_AM::ror)
2950       .Case("rrx", ARM_AM::rrx)
2951       .Default(ARM_AM::no_shift);
2952 
2953   if (ShiftTy == ARM_AM::no_shift)
2954     return 1;
2955 
2956   Parser.Lex(); // Eat the operator.
2957 
2958   // The source register for the shift has already been added to the
2959   // operand list, so we need to pop it off and combine it into the shifted
2960   // register operand instead.
2961   std::unique_ptr<ARMOperand> PrevOp(
2962       (ARMOperand *)Operands.pop_back_val().release());
2963   if (!PrevOp->isReg())
2964     return Error(PrevOp->getStartLoc(), "shift must be of a register");
2965   int SrcReg = PrevOp->getReg();
2966 
2967   SMLoc EndLoc;
2968   int64_t Imm = 0;
2969   int ShiftReg = 0;
2970   if (ShiftTy == ARM_AM::rrx) {
2971     // RRX Doesn't have an explicit shift amount. The encoder expects
2972     // the shift register to be the same as the source register. Seems odd,
2973     // but OK.
2974     ShiftReg = SrcReg;
2975   } else {
2976     // Figure out if this is shifted by a constant or a register (for non-RRX).
2977     if (Parser.getTok().is(AsmToken::Hash) ||
2978         Parser.getTok().is(AsmToken::Dollar)) {
2979       Parser.Lex(); // Eat hash.
2980       SMLoc ImmLoc = Parser.getTok().getLoc();
2981       const MCExpr *ShiftExpr = nullptr;
2982       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2983         Error(ImmLoc, "invalid immediate shift value");
2984         return -1;
2985       }
2986       // The expression must be evaluatable as an immediate.
2987       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2988       if (!CE) {
2989         Error(ImmLoc, "invalid immediate shift value");
2990         return -1;
2991       }
2992       // Range check the immediate.
2993       // lsl, ror: 0 <= imm <= 31
2994       // lsr, asr: 0 <= imm <= 32
2995       Imm = CE->getValue();
2996       if (Imm < 0 ||
2997           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2998           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2999         Error(ImmLoc, "immediate shift value out of range");
3000         return -1;
3001       }
3002       // shift by zero is a nop. Always send it through as lsl.
3003       // ('as' compatibility)
3004       if (Imm == 0)
3005         ShiftTy = ARM_AM::lsl;
3006     } else if (Parser.getTok().is(AsmToken::Identifier)) {
3007       SMLoc L = Parser.getTok().getLoc();
3008       EndLoc = Parser.getTok().getEndLoc();
3009       ShiftReg = tryParseRegister();
3010       if (ShiftReg == -1) {
3011         Error(L, "expected immediate or register in shift operand");
3012         return -1;
3013       }
3014     } else {
3015       Error(Parser.getTok().getLoc(),
3016             "expected immediate or register in shift operand");
3017       return -1;
3018     }
3019   }
3020 
3021   if (ShiftReg && ShiftTy != ARM_AM::rrx)
3022     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3023                                                          ShiftReg, Imm,
3024                                                          S, EndLoc));
3025   else
3026     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3027                                                           S, EndLoc));
3028 
3029   return 0;
3030 }
3031 
3032 
3033 /// Try to parse a register name.  The token must be an Identifier when called.
3034 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3035 /// if there is a "writeback". 'true' if it's not a register.
3036 ///
3037 /// TODO this is likely to change to allow different register types and or to
3038 /// parse for a specific register type.
3039 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3040   const AsmToken &RegTok = Parser.getTok();
3041   int RegNo = tryParseRegister();
3042   if (RegNo == -1)
3043     return true;
3044 
3045   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3046                                            RegTok.getEndLoc()));
3047 
3048   const AsmToken &ExclaimTok = Parser.getTok();
3049   if (ExclaimTok.is(AsmToken::Exclaim)) {
3050     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3051                                                ExclaimTok.getLoc()));
3052     Parser.Lex(); // Eat exclaim token
3053     return false;
3054   }
3055 
3056   // Also check for an index operand. This is only legal for vector registers,
3057   // but that'll get caught OK in operand matching, so we don't need to
3058   // explicitly filter everything else out here.
3059   if (Parser.getTok().is(AsmToken::LBrac)) {
3060     SMLoc SIdx = Parser.getTok().getLoc();
3061     Parser.Lex(); // Eat left bracket token.
3062 
3063     const MCExpr *ImmVal;
3064     if (getParser().parseExpression(ImmVal))
3065       return true;
3066     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3067     if (!MCE)
3068       return TokError("immediate value expected for vector index");
3069 
3070     if (Parser.getTok().isNot(AsmToken::RBrac))
3071       return Error(Parser.getTok().getLoc(), "']' expected");
3072 
3073     SMLoc E = Parser.getTok().getEndLoc();
3074     Parser.Lex(); // Eat right bracket token.
3075 
3076     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3077                                                      SIdx, E,
3078                                                      getContext()));
3079   }
3080 
3081   return false;
3082 }
3083 
3084 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3085 /// instruction with a symbolic operand name.
3086 /// We accept "crN" syntax for GAS compatibility.
3087 /// <operand-name> ::= <prefix><number>
3088 /// If CoprocOp is 'c', then:
3089 ///   <prefix> ::= c | cr
3090 /// If CoprocOp is 'p', then :
3091 ///   <prefix> ::= p
3092 /// <number> ::= integer in range [0, 15]
3093 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3094   // Use the same layout as the tablegen'erated register name matcher. Ugly,
3095   // but efficient.
3096   if (Name.size() < 2 || Name[0] != CoprocOp)
3097     return -1;
3098   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3099 
3100   switch (Name.size()) {
3101   default: return -1;
3102   case 1:
3103     switch (Name[0]) {
3104     default:  return -1;
3105     case '0': return 0;
3106     case '1': return 1;
3107     case '2': return 2;
3108     case '3': return 3;
3109     case '4': return 4;
3110     case '5': return 5;
3111     case '6': return 6;
3112     case '7': return 7;
3113     case '8': return 8;
3114     case '9': return 9;
3115     }
3116   case 2:
3117     if (Name[0] != '1')
3118       return -1;
3119     switch (Name[1]) {
3120     default:  return -1;
3121     // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3122     // However, old cores (v5/v6) did use them in that way.
3123     case '0': return 10;
3124     case '1': return 11;
3125     case '2': return 12;
3126     case '3': return 13;
3127     case '4': return 14;
3128     case '5': return 15;
3129     }
3130   }
3131 }
3132 
3133 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3134 ARMAsmParser::OperandMatchResultTy
3135 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3136   SMLoc S = Parser.getTok().getLoc();
3137   const AsmToken &Tok = Parser.getTok();
3138   if (!Tok.is(AsmToken::Identifier))
3139     return MatchOperand_NoMatch;
3140   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3141     .Case("eq", ARMCC::EQ)
3142     .Case("ne", ARMCC::NE)
3143     .Case("hs", ARMCC::HS)
3144     .Case("cs", ARMCC::HS)
3145     .Case("lo", ARMCC::LO)
3146     .Case("cc", ARMCC::LO)
3147     .Case("mi", ARMCC::MI)
3148     .Case("pl", ARMCC::PL)
3149     .Case("vs", ARMCC::VS)
3150     .Case("vc", ARMCC::VC)
3151     .Case("hi", ARMCC::HI)
3152     .Case("ls", ARMCC::LS)
3153     .Case("ge", ARMCC::GE)
3154     .Case("lt", ARMCC::LT)
3155     .Case("gt", ARMCC::GT)
3156     .Case("le", ARMCC::LE)
3157     .Case("al", ARMCC::AL)
3158     .Default(~0U);
3159   if (CC == ~0U)
3160     return MatchOperand_NoMatch;
3161   Parser.Lex(); // Eat the token.
3162 
3163   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3164 
3165   return MatchOperand_Success;
3166 }
3167 
3168 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3169 /// token must be an Identifier when called, and if it is a coprocessor
3170 /// number, the token is eaten and the operand is added to the operand list.
3171 ARMAsmParser::OperandMatchResultTy
3172 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3173   SMLoc S = Parser.getTok().getLoc();
3174   const AsmToken &Tok = Parser.getTok();
3175   if (Tok.isNot(AsmToken::Identifier))
3176     return MatchOperand_NoMatch;
3177 
3178   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3179   if (Num == -1)
3180     return MatchOperand_NoMatch;
3181   // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3182   if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3183     return MatchOperand_NoMatch;
3184 
3185   Parser.Lex(); // Eat identifier token.
3186   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3187   return MatchOperand_Success;
3188 }
3189 
3190 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3191 /// token must be an Identifier when called, and if it is a coprocessor
3192 /// number, the token is eaten and the operand is added to the operand list.
3193 ARMAsmParser::OperandMatchResultTy
3194 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3195   SMLoc S = Parser.getTok().getLoc();
3196   const AsmToken &Tok = Parser.getTok();
3197   if (Tok.isNot(AsmToken::Identifier))
3198     return MatchOperand_NoMatch;
3199 
3200   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3201   if (Reg == -1)
3202     return MatchOperand_NoMatch;
3203 
3204   Parser.Lex(); // Eat identifier token.
3205   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3206   return MatchOperand_Success;
3207 }
3208 
3209 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3210 /// coproc_option : '{' imm0_255 '}'
3211 ARMAsmParser::OperandMatchResultTy
3212 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3213   SMLoc S = Parser.getTok().getLoc();
3214 
3215   // If this isn't a '{', this isn't a coprocessor immediate operand.
3216   if (Parser.getTok().isNot(AsmToken::LCurly))
3217     return MatchOperand_NoMatch;
3218   Parser.Lex(); // Eat the '{'
3219 
3220   const MCExpr *Expr;
3221   SMLoc Loc = Parser.getTok().getLoc();
3222   if (getParser().parseExpression(Expr)) {
3223     Error(Loc, "illegal expression");
3224     return MatchOperand_ParseFail;
3225   }
3226   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3227   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3228     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3229     return MatchOperand_ParseFail;
3230   }
3231   int Val = CE->getValue();
3232 
3233   // Check for and consume the closing '}'
3234   if (Parser.getTok().isNot(AsmToken::RCurly))
3235     return MatchOperand_ParseFail;
3236   SMLoc E = Parser.getTok().getEndLoc();
3237   Parser.Lex(); // Eat the '}'
3238 
3239   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3240   return MatchOperand_Success;
3241 }
3242 
3243 // For register list parsing, we need to map from raw GPR register numbering
3244 // to the enumeration values. The enumeration values aren't sorted by
3245 // register number due to our using "sp", "lr" and "pc" as canonical names.
3246 static unsigned getNextRegister(unsigned Reg) {
3247   // If this is a GPR, we need to do it manually, otherwise we can rely
3248   // on the sort ordering of the enumeration since the other reg-classes
3249   // are sane.
3250   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3251     return Reg + 1;
3252   switch(Reg) {
3253   default: llvm_unreachable("Invalid GPR number!");
3254   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3255   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3256   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3257   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3258   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3259   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3260   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3261   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3262   }
3263 }
3264 
3265 // Return the low-subreg of a given Q register.
3266 static unsigned getDRegFromQReg(unsigned QReg) {
3267   switch (QReg) {
3268   default: llvm_unreachable("expected a Q register!");
3269   case ARM::Q0:  return ARM::D0;
3270   case ARM::Q1:  return ARM::D2;
3271   case ARM::Q2:  return ARM::D4;
3272   case ARM::Q3:  return ARM::D6;
3273   case ARM::Q4:  return ARM::D8;
3274   case ARM::Q5:  return ARM::D10;
3275   case ARM::Q6:  return ARM::D12;
3276   case ARM::Q7:  return ARM::D14;
3277   case ARM::Q8:  return ARM::D16;
3278   case ARM::Q9:  return ARM::D18;
3279   case ARM::Q10: return ARM::D20;
3280   case ARM::Q11: return ARM::D22;
3281   case ARM::Q12: return ARM::D24;
3282   case ARM::Q13: return ARM::D26;
3283   case ARM::Q14: return ARM::D28;
3284   case ARM::Q15: return ARM::D30;
3285   }
3286 }
3287 
3288 /// Parse a register list.
3289 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3290   assert(Parser.getTok().is(AsmToken::LCurly) &&
3291          "Token is not a Left Curly Brace");
3292   SMLoc S = Parser.getTok().getLoc();
3293   Parser.Lex(); // Eat '{' token.
3294   SMLoc RegLoc = Parser.getTok().getLoc();
3295 
3296   // Check the first register in the list to see what register class
3297   // this is a list of.
3298   int Reg = tryParseRegister();
3299   if (Reg == -1)
3300     return Error(RegLoc, "register expected");
3301 
3302   // The reglist instructions have at most 16 registers, so reserve
3303   // space for that many.
3304   int EReg = 0;
3305   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3306 
3307   // Allow Q regs and just interpret them as the two D sub-registers.
3308   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3309     Reg = getDRegFromQReg(Reg);
3310     EReg = MRI->getEncodingValue(Reg);
3311     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3312     ++Reg;
3313   }
3314   const MCRegisterClass *RC;
3315   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3316     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3317   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3318     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3319   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3320     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3321   else
3322     return Error(RegLoc, "invalid register in register list");
3323 
3324   // Store the register.
3325   EReg = MRI->getEncodingValue(Reg);
3326   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3327 
3328   // This starts immediately after the first register token in the list,
3329   // so we can see either a comma or a minus (range separator) as a legal
3330   // next token.
3331   while (Parser.getTok().is(AsmToken::Comma) ||
3332          Parser.getTok().is(AsmToken::Minus)) {
3333     if (Parser.getTok().is(AsmToken::Minus)) {
3334       Parser.Lex(); // Eat the minus.
3335       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3336       int EndReg = tryParseRegister();
3337       if (EndReg == -1)
3338         return Error(AfterMinusLoc, "register expected");
3339       // Allow Q regs and just interpret them as the two D sub-registers.
3340       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3341         EndReg = getDRegFromQReg(EndReg) + 1;
3342       // If the register is the same as the start reg, there's nothing
3343       // more to do.
3344       if (Reg == EndReg)
3345         continue;
3346       // The register must be in the same register class as the first.
3347       if (!RC->contains(EndReg))
3348         return Error(AfterMinusLoc, "invalid register in register list");
3349       // Ranges must go from low to high.
3350       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3351         return Error(AfterMinusLoc, "bad range in register list");
3352 
3353       // Add all the registers in the range to the register list.
3354       while (Reg != EndReg) {
3355         Reg = getNextRegister(Reg);
3356         EReg = MRI->getEncodingValue(Reg);
3357         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3358       }
3359       continue;
3360     }
3361     Parser.Lex(); // Eat the comma.
3362     RegLoc = Parser.getTok().getLoc();
3363     int OldReg = Reg;
3364     const AsmToken RegTok = Parser.getTok();
3365     Reg = tryParseRegister();
3366     if (Reg == -1)
3367       return Error(RegLoc, "register expected");
3368     // Allow Q regs and just interpret them as the two D sub-registers.
3369     bool isQReg = false;
3370     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3371       Reg = getDRegFromQReg(Reg);
3372       isQReg = true;
3373     }
3374     // The register must be in the same register class as the first.
3375     if (!RC->contains(Reg))
3376       return Error(RegLoc, "invalid register in register list");
3377     // List must be monotonically increasing.
3378     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3379       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3380         Warning(RegLoc, "register list not in ascending order");
3381       else
3382         return Error(RegLoc, "register list not in ascending order");
3383     }
3384     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3385       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3386               ") in register list");
3387       continue;
3388     }
3389     // VFP register lists must also be contiguous.
3390     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3391         Reg != OldReg + 1)
3392       return Error(RegLoc, "non-contiguous register range");
3393     EReg = MRI->getEncodingValue(Reg);
3394     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3395     if (isQReg) {
3396       EReg = MRI->getEncodingValue(++Reg);
3397       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3398     }
3399   }
3400 
3401   if (Parser.getTok().isNot(AsmToken::RCurly))
3402     return Error(Parser.getTok().getLoc(), "'}' expected");
3403   SMLoc E = Parser.getTok().getEndLoc();
3404   Parser.Lex(); // Eat '}' token.
3405 
3406   // Push the register list operand.
3407   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3408 
3409   // The ARM system instruction variants for LDM/STM have a '^' token here.
3410   if (Parser.getTok().is(AsmToken::Caret)) {
3411     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3412     Parser.Lex(); // Eat '^' token.
3413   }
3414 
3415   return false;
3416 }
3417 
3418 // Helper function to parse the lane index for vector lists.
3419 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3420 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3421   Index = 0; // Always return a defined index value.
3422   if (Parser.getTok().is(AsmToken::LBrac)) {
3423     Parser.Lex(); // Eat the '['.
3424     if (Parser.getTok().is(AsmToken::RBrac)) {
3425       // "Dn[]" is the 'all lanes' syntax.
3426       LaneKind = AllLanes;
3427       EndLoc = Parser.getTok().getEndLoc();
3428       Parser.Lex(); // Eat the ']'.
3429       return MatchOperand_Success;
3430     }
3431 
3432     // There's an optional '#' token here. Normally there wouldn't be, but
3433     // inline assemble puts one in, and it's friendly to accept that.
3434     if (Parser.getTok().is(AsmToken::Hash))
3435       Parser.Lex(); // Eat '#' or '$'.
3436 
3437     const MCExpr *LaneIndex;
3438     SMLoc Loc = Parser.getTok().getLoc();
3439     if (getParser().parseExpression(LaneIndex)) {
3440       Error(Loc, "illegal expression");
3441       return MatchOperand_ParseFail;
3442     }
3443     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3444     if (!CE) {
3445       Error(Loc, "lane index must be empty or an integer");
3446       return MatchOperand_ParseFail;
3447     }
3448     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3449       Error(Parser.getTok().getLoc(), "']' expected");
3450       return MatchOperand_ParseFail;
3451     }
3452     EndLoc = Parser.getTok().getEndLoc();
3453     Parser.Lex(); // Eat the ']'.
3454     int64_t Val = CE->getValue();
3455 
3456     // FIXME: Make this range check context sensitive for .8, .16, .32.
3457     if (Val < 0 || Val > 7) {
3458       Error(Parser.getTok().getLoc(), "lane index out of range");
3459       return MatchOperand_ParseFail;
3460     }
3461     Index = Val;
3462     LaneKind = IndexedLane;
3463     return MatchOperand_Success;
3464   }
3465   LaneKind = NoLanes;
3466   return MatchOperand_Success;
3467 }
3468 
3469 // parse a vector register list
3470 ARMAsmParser::OperandMatchResultTy
3471 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3472   VectorLaneTy LaneKind;
3473   unsigned LaneIndex;
3474   SMLoc S = Parser.getTok().getLoc();
3475   // As an extension (to match gas), support a plain D register or Q register
3476   // (without encosing curly braces) as a single or double entry list,
3477   // respectively.
3478   if (Parser.getTok().is(AsmToken::Identifier)) {
3479     SMLoc E = Parser.getTok().getEndLoc();
3480     int Reg = tryParseRegister();
3481     if (Reg == -1)
3482       return MatchOperand_NoMatch;
3483     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3484       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3485       if (Res != MatchOperand_Success)
3486         return Res;
3487       switch (LaneKind) {
3488       case NoLanes:
3489         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3490         break;
3491       case AllLanes:
3492         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3493                                                                 S, E));
3494         break;
3495       case IndexedLane:
3496         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3497                                                                LaneIndex,
3498                                                                false, S, E));
3499         break;
3500       }
3501       return MatchOperand_Success;
3502     }
3503     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3504       Reg = getDRegFromQReg(Reg);
3505       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3506       if (Res != MatchOperand_Success)
3507         return Res;
3508       switch (LaneKind) {
3509       case NoLanes:
3510         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3511                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3512         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3513         break;
3514       case AllLanes:
3515         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3516                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3517         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3518                                                                 S, E));
3519         break;
3520       case IndexedLane:
3521         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3522                                                                LaneIndex,
3523                                                                false, S, E));
3524         break;
3525       }
3526       return MatchOperand_Success;
3527     }
3528     Error(S, "vector register expected");
3529     return MatchOperand_ParseFail;
3530   }
3531 
3532   if (Parser.getTok().isNot(AsmToken::LCurly))
3533     return MatchOperand_NoMatch;
3534 
3535   Parser.Lex(); // Eat '{' token.
3536   SMLoc RegLoc = Parser.getTok().getLoc();
3537 
3538   int Reg = tryParseRegister();
3539   if (Reg == -1) {
3540     Error(RegLoc, "register expected");
3541     return MatchOperand_ParseFail;
3542   }
3543   unsigned Count = 1;
3544   int Spacing = 0;
3545   unsigned FirstReg = Reg;
3546   // The list is of D registers, but we also allow Q regs and just interpret
3547   // them as the two D sub-registers.
3548   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3549     FirstReg = Reg = getDRegFromQReg(Reg);
3550     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3551                  // it's ambiguous with four-register single spaced.
3552     ++Reg;
3553     ++Count;
3554   }
3555 
3556   SMLoc E;
3557   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3558     return MatchOperand_ParseFail;
3559 
3560   while (Parser.getTok().is(AsmToken::Comma) ||
3561          Parser.getTok().is(AsmToken::Minus)) {
3562     if (Parser.getTok().is(AsmToken::Minus)) {
3563       if (!Spacing)
3564         Spacing = 1; // Register range implies a single spaced list.
3565       else if (Spacing == 2) {
3566         Error(Parser.getTok().getLoc(),
3567               "sequential registers in double spaced list");
3568         return MatchOperand_ParseFail;
3569       }
3570       Parser.Lex(); // Eat the minus.
3571       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3572       int EndReg = tryParseRegister();
3573       if (EndReg == -1) {
3574         Error(AfterMinusLoc, "register expected");
3575         return MatchOperand_ParseFail;
3576       }
3577       // Allow Q regs and just interpret them as the two D sub-registers.
3578       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3579         EndReg = getDRegFromQReg(EndReg) + 1;
3580       // If the register is the same as the start reg, there's nothing
3581       // more to do.
3582       if (Reg == EndReg)
3583         continue;
3584       // The register must be in the same register class as the first.
3585       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3586         Error(AfterMinusLoc, "invalid register in register list");
3587         return MatchOperand_ParseFail;
3588       }
3589       // Ranges must go from low to high.
3590       if (Reg > EndReg) {
3591         Error(AfterMinusLoc, "bad range in register list");
3592         return MatchOperand_ParseFail;
3593       }
3594       // Parse the lane specifier if present.
3595       VectorLaneTy NextLaneKind;
3596       unsigned NextLaneIndex;
3597       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3598           MatchOperand_Success)
3599         return MatchOperand_ParseFail;
3600       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3601         Error(AfterMinusLoc, "mismatched lane index in register list");
3602         return MatchOperand_ParseFail;
3603       }
3604 
3605       // Add all the registers in the range to the register list.
3606       Count += EndReg - Reg;
3607       Reg = EndReg;
3608       continue;
3609     }
3610     Parser.Lex(); // Eat the comma.
3611     RegLoc = Parser.getTok().getLoc();
3612     int OldReg = Reg;
3613     Reg = tryParseRegister();
3614     if (Reg == -1) {
3615       Error(RegLoc, "register expected");
3616       return MatchOperand_ParseFail;
3617     }
3618     // vector register lists must be contiguous.
3619     // It's OK to use the enumeration values directly here rather, as the
3620     // VFP register classes have the enum sorted properly.
3621     //
3622     // The list is of D registers, but we also allow Q regs and just interpret
3623     // them as the two D sub-registers.
3624     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3625       if (!Spacing)
3626         Spacing = 1; // Register range implies a single spaced list.
3627       else if (Spacing == 2) {
3628         Error(RegLoc,
3629               "invalid register in double-spaced list (must be 'D' register')");
3630         return MatchOperand_ParseFail;
3631       }
3632       Reg = getDRegFromQReg(Reg);
3633       if (Reg != OldReg + 1) {
3634         Error(RegLoc, "non-contiguous register range");
3635         return MatchOperand_ParseFail;
3636       }
3637       ++Reg;
3638       Count += 2;
3639       // Parse the lane specifier if present.
3640       VectorLaneTy NextLaneKind;
3641       unsigned NextLaneIndex;
3642       SMLoc LaneLoc = Parser.getTok().getLoc();
3643       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3644           MatchOperand_Success)
3645         return MatchOperand_ParseFail;
3646       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3647         Error(LaneLoc, "mismatched lane index in register list");
3648         return MatchOperand_ParseFail;
3649       }
3650       continue;
3651     }
3652     // Normal D register.
3653     // Figure out the register spacing (single or double) of the list if
3654     // we don't know it already.
3655     if (!Spacing)
3656       Spacing = 1 + (Reg == OldReg + 2);
3657 
3658     // Just check that it's contiguous and keep going.
3659     if (Reg != OldReg + Spacing) {
3660       Error(RegLoc, "non-contiguous register range");
3661       return MatchOperand_ParseFail;
3662     }
3663     ++Count;
3664     // Parse the lane specifier if present.
3665     VectorLaneTy NextLaneKind;
3666     unsigned NextLaneIndex;
3667     SMLoc EndLoc = Parser.getTok().getLoc();
3668     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3669       return MatchOperand_ParseFail;
3670     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3671       Error(EndLoc, "mismatched lane index in register list");
3672       return MatchOperand_ParseFail;
3673     }
3674   }
3675 
3676   if (Parser.getTok().isNot(AsmToken::RCurly)) {
3677     Error(Parser.getTok().getLoc(), "'}' expected");
3678     return MatchOperand_ParseFail;
3679   }
3680   E = Parser.getTok().getEndLoc();
3681   Parser.Lex(); // Eat '}' token.
3682 
3683   switch (LaneKind) {
3684   case NoLanes:
3685     // Two-register operands have been converted to the
3686     // composite register classes.
3687     if (Count == 2) {
3688       const MCRegisterClass *RC = (Spacing == 1) ?
3689         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3690         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3691       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3692     }
3693 
3694     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3695                                                     (Spacing == 2), S, E));
3696     break;
3697   case AllLanes:
3698     // Two-register operands have been converted to the
3699     // composite register classes.
3700     if (Count == 2) {
3701       const MCRegisterClass *RC = (Spacing == 1) ?
3702         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3703         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3704       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3705     }
3706     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3707                                                             (Spacing == 2),
3708                                                             S, E));
3709     break;
3710   case IndexedLane:
3711     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3712                                                            LaneIndex,
3713                                                            (Spacing == 2),
3714                                                            S, E));
3715     break;
3716   }
3717   return MatchOperand_Success;
3718 }
3719 
3720 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3721 ARMAsmParser::OperandMatchResultTy
3722 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3723   SMLoc S = Parser.getTok().getLoc();
3724   const AsmToken &Tok = Parser.getTok();
3725   unsigned Opt;
3726 
3727   if (Tok.is(AsmToken::Identifier)) {
3728     StringRef OptStr = Tok.getString();
3729 
3730     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3731       .Case("sy",    ARM_MB::SY)
3732       .Case("st",    ARM_MB::ST)
3733       .Case("ld",    ARM_MB::LD)
3734       .Case("sh",    ARM_MB::ISH)
3735       .Case("ish",   ARM_MB::ISH)
3736       .Case("shst",  ARM_MB::ISHST)
3737       .Case("ishst", ARM_MB::ISHST)
3738       .Case("ishld", ARM_MB::ISHLD)
3739       .Case("nsh",   ARM_MB::NSH)
3740       .Case("un",    ARM_MB::NSH)
3741       .Case("nshst", ARM_MB::NSHST)
3742       .Case("nshld", ARM_MB::NSHLD)
3743       .Case("unst",  ARM_MB::NSHST)
3744       .Case("osh",   ARM_MB::OSH)
3745       .Case("oshst", ARM_MB::OSHST)
3746       .Case("oshld", ARM_MB::OSHLD)
3747       .Default(~0U);
3748 
3749     // ishld, oshld, nshld and ld are only available from ARMv8.
3750     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3751                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3752       Opt = ~0U;
3753 
3754     if (Opt == ~0U)
3755       return MatchOperand_NoMatch;
3756 
3757     Parser.Lex(); // Eat identifier token.
3758   } else if (Tok.is(AsmToken::Hash) ||
3759              Tok.is(AsmToken::Dollar) ||
3760              Tok.is(AsmToken::Integer)) {
3761     if (Parser.getTok().isNot(AsmToken::Integer))
3762       Parser.Lex(); // Eat '#' or '$'.
3763     SMLoc Loc = Parser.getTok().getLoc();
3764 
3765     const MCExpr *MemBarrierID;
3766     if (getParser().parseExpression(MemBarrierID)) {
3767       Error(Loc, "illegal expression");
3768       return MatchOperand_ParseFail;
3769     }
3770 
3771     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3772     if (!CE) {
3773       Error(Loc, "constant expression expected");
3774       return MatchOperand_ParseFail;
3775     }
3776 
3777     int Val = CE->getValue();
3778     if (Val & ~0xf) {
3779       Error(Loc, "immediate value out of range");
3780       return MatchOperand_ParseFail;
3781     }
3782 
3783     Opt = ARM_MB::RESERVED_0 + Val;
3784   } else
3785     return MatchOperand_ParseFail;
3786 
3787   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3788   return MatchOperand_Success;
3789 }
3790 
3791 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3792 ARMAsmParser::OperandMatchResultTy
3793 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3794   SMLoc S = Parser.getTok().getLoc();
3795   const AsmToken &Tok = Parser.getTok();
3796   unsigned Opt;
3797 
3798   if (Tok.is(AsmToken::Identifier)) {
3799     StringRef OptStr = Tok.getString();
3800 
3801     if (OptStr.equals_lower("sy"))
3802       Opt = ARM_ISB::SY;
3803     else
3804       return MatchOperand_NoMatch;
3805 
3806     Parser.Lex(); // Eat identifier token.
3807   } else if (Tok.is(AsmToken::Hash) ||
3808              Tok.is(AsmToken::Dollar) ||
3809              Tok.is(AsmToken::Integer)) {
3810     if (Parser.getTok().isNot(AsmToken::Integer))
3811       Parser.Lex(); // Eat '#' or '$'.
3812     SMLoc Loc = Parser.getTok().getLoc();
3813 
3814     const MCExpr *ISBarrierID;
3815     if (getParser().parseExpression(ISBarrierID)) {
3816       Error(Loc, "illegal expression");
3817       return MatchOperand_ParseFail;
3818     }
3819 
3820     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3821     if (!CE) {
3822       Error(Loc, "constant expression expected");
3823       return MatchOperand_ParseFail;
3824     }
3825 
3826     int Val = CE->getValue();
3827     if (Val & ~0xf) {
3828       Error(Loc, "immediate value out of range");
3829       return MatchOperand_ParseFail;
3830     }
3831 
3832     Opt = ARM_ISB::RESERVED_0 + Val;
3833   } else
3834     return MatchOperand_ParseFail;
3835 
3836   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3837           (ARM_ISB::InstSyncBOpt)Opt, S));
3838   return MatchOperand_Success;
3839 }
3840 
3841 
3842 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3843 ARMAsmParser::OperandMatchResultTy
3844 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3845   SMLoc S = Parser.getTok().getLoc();
3846   const AsmToken &Tok = Parser.getTok();
3847   if (!Tok.is(AsmToken::Identifier))
3848     return MatchOperand_NoMatch;
3849   StringRef IFlagsStr = Tok.getString();
3850 
3851   // An iflags string of "none" is interpreted to mean that none of the AIF
3852   // bits are set.  Not a terribly useful instruction, but a valid encoding.
3853   unsigned IFlags = 0;
3854   if (IFlagsStr != "none") {
3855         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3856       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3857         .Case("a", ARM_PROC::A)
3858         .Case("i", ARM_PROC::I)
3859         .Case("f", ARM_PROC::F)
3860         .Default(~0U);
3861 
3862       // If some specific iflag is already set, it means that some letter is
3863       // present more than once, this is not acceptable.
3864       if (Flag == ~0U || (IFlags & Flag))
3865         return MatchOperand_NoMatch;
3866 
3867       IFlags |= Flag;
3868     }
3869   }
3870 
3871   Parser.Lex(); // Eat identifier token.
3872   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3873   return MatchOperand_Success;
3874 }
3875 
3876 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3877 ARMAsmParser::OperandMatchResultTy
3878 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3879   SMLoc S = Parser.getTok().getLoc();
3880   const AsmToken &Tok = Parser.getTok();
3881   if (!Tok.is(AsmToken::Identifier))
3882     return MatchOperand_NoMatch;
3883   StringRef Mask = Tok.getString();
3884 
3885   if (isMClass()) {
3886     // See ARMv6-M 10.1.1
3887     std::string Name = Mask.lower();
3888     unsigned FlagsVal = StringSwitch<unsigned>(Name)
3889       // Note: in the documentation:
3890       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3891       //  for MSR APSR_nzcvq.
3892       // but we do make it an alias here.  This is so to get the "mask encoding"
3893       // bits correct on MSR APSR writes.
3894       //
3895       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3896       // should really only be allowed when writing a special register.  Note
3897       // they get dropped in the MRS instruction reading a special register as
3898       // the SYSm field is only 8 bits.
3899       //
3900       // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3901       // includes the DSP extension but that is not checked.
3902       .Case("apsr", 0x800)
3903       .Case("apsr_nzcvq", 0x800)
3904       .Case("apsr_g", 0x400)
3905       .Case("apsr_nzcvqg", 0xc00)
3906       .Case("iapsr", 0x801)
3907       .Case("iapsr_nzcvq", 0x801)
3908       .Case("iapsr_g", 0x401)
3909       .Case("iapsr_nzcvqg", 0xc01)
3910       .Case("eapsr", 0x802)
3911       .Case("eapsr_nzcvq", 0x802)
3912       .Case("eapsr_g", 0x402)
3913       .Case("eapsr_nzcvqg", 0xc02)
3914       .Case("xpsr", 0x803)
3915       .Case("xpsr_nzcvq", 0x803)
3916       .Case("xpsr_g", 0x403)
3917       .Case("xpsr_nzcvqg", 0xc03)
3918       .Case("ipsr", 0x805)
3919       .Case("epsr", 0x806)
3920       .Case("iepsr", 0x807)
3921       .Case("msp", 0x808)
3922       .Case("psp", 0x809)
3923       .Case("primask", 0x810)
3924       .Case("basepri", 0x811)
3925       .Case("basepri_max", 0x812)
3926       .Case("faultmask", 0x813)
3927       .Case("control", 0x814)
3928       .Default(~0U);
3929 
3930     if (FlagsVal == ~0U)
3931       return MatchOperand_NoMatch;
3932 
3933     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3934       // basepri, basepri_max and faultmask only valid for V7m.
3935       return MatchOperand_NoMatch;
3936 
3937     Parser.Lex(); // Eat identifier token.
3938     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3939     return MatchOperand_Success;
3940   }
3941 
3942   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3943   size_t Start = 0, Next = Mask.find('_');
3944   StringRef Flags = "";
3945   std::string SpecReg = Mask.slice(Start, Next).lower();
3946   if (Next != StringRef::npos)
3947     Flags = Mask.slice(Next+1, Mask.size());
3948 
3949   // FlagsVal contains the complete mask:
3950   // 3-0: Mask
3951   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3952   unsigned FlagsVal = 0;
3953 
3954   if (SpecReg == "apsr") {
3955     FlagsVal = StringSwitch<unsigned>(Flags)
3956     .Case("nzcvq",  0x8) // same as CPSR_f
3957     .Case("g",      0x4) // same as CPSR_s
3958     .Case("nzcvqg", 0xc) // same as CPSR_fs
3959     .Default(~0U);
3960 
3961     if (FlagsVal == ~0U) {
3962       if (!Flags.empty())
3963         return MatchOperand_NoMatch;
3964       else
3965         FlagsVal = 8; // No flag
3966     }
3967   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3968     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3969     if (Flags == "all" || Flags == "")
3970       Flags = "fc";
3971     for (int i = 0, e = Flags.size(); i != e; ++i) {
3972       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3973       .Case("c", 1)
3974       .Case("x", 2)
3975       .Case("s", 4)
3976       .Case("f", 8)
3977       .Default(~0U);
3978 
3979       // If some specific flag is already set, it means that some letter is
3980       // present more than once, this is not acceptable.
3981       if (FlagsVal == ~0U || (FlagsVal & Flag))
3982         return MatchOperand_NoMatch;
3983       FlagsVal |= Flag;
3984     }
3985   } else // No match for special register.
3986     return MatchOperand_NoMatch;
3987 
3988   // Special register without flags is NOT equivalent to "fc" flags.
3989   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3990   // two lines would enable gas compatibility at the expense of breaking
3991   // round-tripping.
3992   //
3993   // if (!FlagsVal)
3994   //  FlagsVal = 0x9;
3995 
3996   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3997   if (SpecReg == "spsr")
3998     FlagsVal |= 16;
3999 
4000   Parser.Lex(); // Eat identifier token.
4001   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4002   return MatchOperand_Success;
4003 }
4004 
4005 ARMAsmParser::OperandMatchResultTy
4006 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4007                           int High) {
4008   const AsmToken &Tok = Parser.getTok();
4009   if (Tok.isNot(AsmToken::Identifier)) {
4010     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4011     return MatchOperand_ParseFail;
4012   }
4013   StringRef ShiftName = Tok.getString();
4014   std::string LowerOp = Op.lower();
4015   std::string UpperOp = Op.upper();
4016   if (ShiftName != LowerOp && ShiftName != UpperOp) {
4017     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4018     return MatchOperand_ParseFail;
4019   }
4020   Parser.Lex(); // Eat shift type token.
4021 
4022   // There must be a '#' and a shift amount.
4023   if (Parser.getTok().isNot(AsmToken::Hash) &&
4024       Parser.getTok().isNot(AsmToken::Dollar)) {
4025     Error(Parser.getTok().getLoc(), "'#' expected");
4026     return MatchOperand_ParseFail;
4027   }
4028   Parser.Lex(); // Eat hash token.
4029 
4030   const MCExpr *ShiftAmount;
4031   SMLoc Loc = Parser.getTok().getLoc();
4032   SMLoc EndLoc;
4033   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4034     Error(Loc, "illegal expression");
4035     return MatchOperand_ParseFail;
4036   }
4037   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4038   if (!CE) {
4039     Error(Loc, "constant expression expected");
4040     return MatchOperand_ParseFail;
4041   }
4042   int Val = CE->getValue();
4043   if (Val < Low || Val > High) {
4044     Error(Loc, "immediate value out of range");
4045     return MatchOperand_ParseFail;
4046   }
4047 
4048   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4049 
4050   return MatchOperand_Success;
4051 }
4052 
4053 ARMAsmParser::OperandMatchResultTy
4054 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4055   const AsmToken &Tok = Parser.getTok();
4056   SMLoc S = Tok.getLoc();
4057   if (Tok.isNot(AsmToken::Identifier)) {
4058     Error(S, "'be' or 'le' operand expected");
4059     return MatchOperand_ParseFail;
4060   }
4061   int Val = StringSwitch<int>(Tok.getString().lower())
4062     .Case("be", 1)
4063     .Case("le", 0)
4064     .Default(-1);
4065   Parser.Lex(); // Eat the token.
4066 
4067   if (Val == -1) {
4068     Error(S, "'be' or 'le' operand expected");
4069     return MatchOperand_ParseFail;
4070   }
4071   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4072                                                                   getContext()),
4073                                            S, Tok.getEndLoc()));
4074   return MatchOperand_Success;
4075 }
4076 
4077 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4078 /// instructions. Legal values are:
4079 ///     lsl #n  'n' in [0,31]
4080 ///     asr #n  'n' in [1,32]
4081 ///             n == 32 encoded as n == 0.
4082 ARMAsmParser::OperandMatchResultTy
4083 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4084   const AsmToken &Tok = Parser.getTok();
4085   SMLoc S = Tok.getLoc();
4086   if (Tok.isNot(AsmToken::Identifier)) {
4087     Error(S, "shift operator 'asr' or 'lsl' expected");
4088     return MatchOperand_ParseFail;
4089   }
4090   StringRef ShiftName = Tok.getString();
4091   bool isASR;
4092   if (ShiftName == "lsl" || ShiftName == "LSL")
4093     isASR = false;
4094   else if (ShiftName == "asr" || ShiftName == "ASR")
4095     isASR = true;
4096   else {
4097     Error(S, "shift operator 'asr' or 'lsl' expected");
4098     return MatchOperand_ParseFail;
4099   }
4100   Parser.Lex(); // Eat the operator.
4101 
4102   // A '#' and a shift amount.
4103   if (Parser.getTok().isNot(AsmToken::Hash) &&
4104       Parser.getTok().isNot(AsmToken::Dollar)) {
4105     Error(Parser.getTok().getLoc(), "'#' expected");
4106     return MatchOperand_ParseFail;
4107   }
4108   Parser.Lex(); // Eat hash token.
4109   SMLoc ExLoc = Parser.getTok().getLoc();
4110 
4111   const MCExpr *ShiftAmount;
4112   SMLoc EndLoc;
4113   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4114     Error(ExLoc, "malformed shift expression");
4115     return MatchOperand_ParseFail;
4116   }
4117   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4118   if (!CE) {
4119     Error(ExLoc, "shift amount must be an immediate");
4120     return MatchOperand_ParseFail;
4121   }
4122 
4123   int64_t Val = CE->getValue();
4124   if (isASR) {
4125     // Shift amount must be in [1,32]
4126     if (Val < 1 || Val > 32) {
4127       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4128       return MatchOperand_ParseFail;
4129     }
4130     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4131     if (isThumb() && Val == 32) {
4132       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4133       return MatchOperand_ParseFail;
4134     }
4135     if (Val == 32) Val = 0;
4136   } else {
4137     // Shift amount must be in [1,32]
4138     if (Val < 0 || Val > 31) {
4139       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4140       return MatchOperand_ParseFail;
4141     }
4142   }
4143 
4144   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4145 
4146   return MatchOperand_Success;
4147 }
4148 
4149 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4150 /// of instructions. Legal values are:
4151 ///     ror #n  'n' in {0, 8, 16, 24}
4152 ARMAsmParser::OperandMatchResultTy
4153 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4154   const AsmToken &Tok = Parser.getTok();
4155   SMLoc S = Tok.getLoc();
4156   if (Tok.isNot(AsmToken::Identifier))
4157     return MatchOperand_NoMatch;
4158   StringRef ShiftName = Tok.getString();
4159   if (ShiftName != "ror" && ShiftName != "ROR")
4160     return MatchOperand_NoMatch;
4161   Parser.Lex(); // Eat the operator.
4162 
4163   // A '#' and a rotate amount.
4164   if (Parser.getTok().isNot(AsmToken::Hash) &&
4165       Parser.getTok().isNot(AsmToken::Dollar)) {
4166     Error(Parser.getTok().getLoc(), "'#' expected");
4167     return MatchOperand_ParseFail;
4168   }
4169   Parser.Lex(); // Eat hash token.
4170   SMLoc ExLoc = Parser.getTok().getLoc();
4171 
4172   const MCExpr *ShiftAmount;
4173   SMLoc EndLoc;
4174   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4175     Error(ExLoc, "malformed rotate expression");
4176     return MatchOperand_ParseFail;
4177   }
4178   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4179   if (!CE) {
4180     Error(ExLoc, "rotate amount must be an immediate");
4181     return MatchOperand_ParseFail;
4182   }
4183 
4184   int64_t Val = CE->getValue();
4185   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4186   // normally, zero is represented in asm by omitting the rotate operand
4187   // entirely.
4188   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4189     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4190     return MatchOperand_ParseFail;
4191   }
4192 
4193   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4194 
4195   return MatchOperand_Success;
4196 }
4197 
4198 ARMAsmParser::OperandMatchResultTy
4199 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4200   SMLoc S = Parser.getTok().getLoc();
4201   // The bitfield descriptor is really two operands, the LSB and the width.
4202   if (Parser.getTok().isNot(AsmToken::Hash) &&
4203       Parser.getTok().isNot(AsmToken::Dollar)) {
4204     Error(Parser.getTok().getLoc(), "'#' expected");
4205     return MatchOperand_ParseFail;
4206   }
4207   Parser.Lex(); // Eat hash token.
4208 
4209   const MCExpr *LSBExpr;
4210   SMLoc E = Parser.getTok().getLoc();
4211   if (getParser().parseExpression(LSBExpr)) {
4212     Error(E, "malformed immediate expression");
4213     return MatchOperand_ParseFail;
4214   }
4215   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4216   if (!CE) {
4217     Error(E, "'lsb' operand must be an immediate");
4218     return MatchOperand_ParseFail;
4219   }
4220 
4221   int64_t LSB = CE->getValue();
4222   // The LSB must be in the range [0,31]
4223   if (LSB < 0 || LSB > 31) {
4224     Error(E, "'lsb' operand must be in the range [0,31]");
4225     return MatchOperand_ParseFail;
4226   }
4227   E = Parser.getTok().getLoc();
4228 
4229   // Expect another immediate operand.
4230   if (Parser.getTok().isNot(AsmToken::Comma)) {
4231     Error(Parser.getTok().getLoc(), "too few operands");
4232     return MatchOperand_ParseFail;
4233   }
4234   Parser.Lex(); // Eat hash token.
4235   if (Parser.getTok().isNot(AsmToken::Hash) &&
4236       Parser.getTok().isNot(AsmToken::Dollar)) {
4237     Error(Parser.getTok().getLoc(), "'#' expected");
4238     return MatchOperand_ParseFail;
4239   }
4240   Parser.Lex(); // Eat hash token.
4241 
4242   const MCExpr *WidthExpr;
4243   SMLoc EndLoc;
4244   if (getParser().parseExpression(WidthExpr, EndLoc)) {
4245     Error(E, "malformed immediate expression");
4246     return MatchOperand_ParseFail;
4247   }
4248   CE = dyn_cast<MCConstantExpr>(WidthExpr);
4249   if (!CE) {
4250     Error(E, "'width' operand must be an immediate");
4251     return MatchOperand_ParseFail;
4252   }
4253 
4254   int64_t Width = CE->getValue();
4255   // The LSB must be in the range [1,32-lsb]
4256   if (Width < 1 || Width > 32 - LSB) {
4257     Error(E, "'width' operand must be in the range [1,32-lsb]");
4258     return MatchOperand_ParseFail;
4259   }
4260 
4261   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4262 
4263   return MatchOperand_Success;
4264 }
4265 
4266 ARMAsmParser::OperandMatchResultTy
4267 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4268   // Check for a post-index addressing register operand. Specifically:
4269   // postidx_reg := '+' register {, shift}
4270   //              | '-' register {, shift}
4271   //              | register {, shift}
4272 
4273   // This method must return MatchOperand_NoMatch without consuming any tokens
4274   // in the case where there is no match, as other alternatives take other
4275   // parse methods.
4276   AsmToken Tok = Parser.getTok();
4277   SMLoc S = Tok.getLoc();
4278   bool haveEaten = false;
4279   bool isAdd = true;
4280   if (Tok.is(AsmToken::Plus)) {
4281     Parser.Lex(); // Eat the '+' token.
4282     haveEaten = true;
4283   } else if (Tok.is(AsmToken::Minus)) {
4284     Parser.Lex(); // Eat the '-' token.
4285     isAdd = false;
4286     haveEaten = true;
4287   }
4288 
4289   SMLoc E = Parser.getTok().getEndLoc();
4290   int Reg = tryParseRegister();
4291   if (Reg == -1) {
4292     if (!haveEaten)
4293       return MatchOperand_NoMatch;
4294     Error(Parser.getTok().getLoc(), "register expected");
4295     return MatchOperand_ParseFail;
4296   }
4297 
4298   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4299   unsigned ShiftImm = 0;
4300   if (Parser.getTok().is(AsmToken::Comma)) {
4301     Parser.Lex(); // Eat the ','.
4302     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4303       return MatchOperand_ParseFail;
4304 
4305     // FIXME: Only approximates end...may include intervening whitespace.
4306     E = Parser.getTok().getLoc();
4307   }
4308 
4309   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4310                                                   ShiftImm, S, E));
4311 
4312   return MatchOperand_Success;
4313 }
4314 
4315 ARMAsmParser::OperandMatchResultTy
4316 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4317   // Check for a post-index addressing register operand. Specifically:
4318   // am3offset := '+' register
4319   //              | '-' register
4320   //              | register
4321   //              | # imm
4322   //              | # + imm
4323   //              | # - imm
4324 
4325   // This method must return MatchOperand_NoMatch without consuming any tokens
4326   // in the case where there is no match, as other alternatives take other
4327   // parse methods.
4328   AsmToken Tok = Parser.getTok();
4329   SMLoc S = Tok.getLoc();
4330 
4331   // Do immediates first, as we always parse those if we have a '#'.
4332   if (Parser.getTok().is(AsmToken::Hash) ||
4333       Parser.getTok().is(AsmToken::Dollar)) {
4334     Parser.Lex(); // Eat '#' or '$'.
4335     // Explicitly look for a '-', as we need to encode negative zero
4336     // differently.
4337     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4338     const MCExpr *Offset;
4339     SMLoc E;
4340     if (getParser().parseExpression(Offset, E))
4341       return MatchOperand_ParseFail;
4342     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4343     if (!CE) {
4344       Error(S, "constant expression expected");
4345       return MatchOperand_ParseFail;
4346     }
4347     // Negative zero is encoded as the flag value INT32_MIN.
4348     int32_t Val = CE->getValue();
4349     if (isNegative && Val == 0)
4350       Val = INT32_MIN;
4351 
4352     Operands.push_back(
4353       ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4354 
4355     return MatchOperand_Success;
4356   }
4357 
4358 
4359   bool haveEaten = false;
4360   bool isAdd = true;
4361   if (Tok.is(AsmToken::Plus)) {
4362     Parser.Lex(); // Eat the '+' token.
4363     haveEaten = true;
4364   } else if (Tok.is(AsmToken::Minus)) {
4365     Parser.Lex(); // Eat the '-' token.
4366     isAdd = false;
4367     haveEaten = true;
4368   }
4369 
4370   Tok = Parser.getTok();
4371   int Reg = tryParseRegister();
4372   if (Reg == -1) {
4373     if (!haveEaten)
4374       return MatchOperand_NoMatch;
4375     Error(Tok.getLoc(), "register expected");
4376     return MatchOperand_ParseFail;
4377   }
4378 
4379   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4380                                                   0, S, Tok.getEndLoc()));
4381 
4382   return MatchOperand_Success;
4383 }
4384 
4385 /// Convert parsed operands to MCInst.  Needed here because this instruction
4386 /// only has two register operands, but multiplication is commutative so
4387 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4388 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4389                                     const OperandVector &Operands) {
4390   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4391   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4392   // If we have a three-operand form, make sure to set Rn to be the operand
4393   // that isn't the same as Rd.
4394   unsigned RegOp = 4;
4395   if (Operands.size() == 6 &&
4396       ((ARMOperand &)*Operands[4]).getReg() ==
4397           ((ARMOperand &)*Operands[3]).getReg())
4398     RegOp = 5;
4399   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4400   Inst.addOperand(Inst.getOperand(0));
4401   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4402 }
4403 
4404 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4405                                     const OperandVector &Operands) {
4406   int CondOp = -1, ImmOp = -1;
4407   switch(Inst.getOpcode()) {
4408     case ARM::tB:
4409     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4410 
4411     case ARM::t2B:
4412     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4413 
4414     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4415   }
4416   // first decide whether or not the branch should be conditional
4417   // by looking at it's location relative to an IT block
4418   if(inITBlock()) {
4419     // inside an IT block we cannot have any conditional branches. any
4420     // such instructions needs to be converted to unconditional form
4421     switch(Inst.getOpcode()) {
4422       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4423       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4424     }
4425   } else {
4426     // outside IT blocks we can only have unconditional branches with AL
4427     // condition code or conditional branches with non-AL condition code
4428     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4429     switch(Inst.getOpcode()) {
4430       case ARM::tB:
4431       case ARM::tBcc:
4432         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4433         break;
4434       case ARM::t2B:
4435       case ARM::t2Bcc:
4436         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4437         break;
4438     }
4439   }
4440 
4441   // now decide on encoding size based on branch target range
4442   switch(Inst.getOpcode()) {
4443     // classify tB as either t2B or t1B based on range of immediate operand
4444     case ARM::tB: {
4445       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4446       if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4447         Inst.setOpcode(ARM::t2B);
4448       break;
4449     }
4450     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4451     case ARM::tBcc: {
4452       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4453       if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4454         Inst.setOpcode(ARM::t2Bcc);
4455       break;
4456     }
4457   }
4458   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4459   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4460 }
4461 
4462 /// Parse an ARM memory expression, return false if successful else return true
4463 /// or an error.  The first token must be a '[' when called.
4464 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4465   SMLoc S, E;
4466   assert(Parser.getTok().is(AsmToken::LBrac) &&
4467          "Token is not a Left Bracket");
4468   S = Parser.getTok().getLoc();
4469   Parser.Lex(); // Eat left bracket token.
4470 
4471   const AsmToken &BaseRegTok = Parser.getTok();
4472   int BaseRegNum = tryParseRegister();
4473   if (BaseRegNum == -1)
4474     return Error(BaseRegTok.getLoc(), "register expected");
4475 
4476   // The next token must either be a comma, a colon or a closing bracket.
4477   const AsmToken &Tok = Parser.getTok();
4478   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4479       !Tok.is(AsmToken::RBrac))
4480     return Error(Tok.getLoc(), "malformed memory operand");
4481 
4482   if (Tok.is(AsmToken::RBrac)) {
4483     E = Tok.getEndLoc();
4484     Parser.Lex(); // Eat right bracket token.
4485 
4486     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4487                                              ARM_AM::no_shift, 0, 0, false,
4488                                              S, E));
4489 
4490     // If there's a pre-indexing writeback marker, '!', just add it as a token
4491     // operand. It's rather odd, but syntactically valid.
4492     if (Parser.getTok().is(AsmToken::Exclaim)) {
4493       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4494       Parser.Lex(); // Eat the '!'.
4495     }
4496 
4497     return false;
4498   }
4499 
4500   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4501          "Lost colon or comma in memory operand?!");
4502   if (Tok.is(AsmToken::Comma)) {
4503     Parser.Lex(); // Eat the comma.
4504   }
4505 
4506   // If we have a ':', it's an alignment specifier.
4507   if (Parser.getTok().is(AsmToken::Colon)) {
4508     Parser.Lex(); // Eat the ':'.
4509     E = Parser.getTok().getLoc();
4510     SMLoc AlignmentLoc = Tok.getLoc();
4511 
4512     const MCExpr *Expr;
4513     if (getParser().parseExpression(Expr))
4514      return true;
4515 
4516     // The expression has to be a constant. Memory references with relocations
4517     // don't come through here, as they use the <label> forms of the relevant
4518     // instructions.
4519     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4520     if (!CE)
4521       return Error (E, "constant expression expected");
4522 
4523     unsigned Align = 0;
4524     switch (CE->getValue()) {
4525     default:
4526       return Error(E,
4527                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4528     case 16:  Align = 2; break;
4529     case 32:  Align = 4; break;
4530     case 64:  Align = 8; break;
4531     case 128: Align = 16; break;
4532     case 256: Align = 32; break;
4533     }
4534 
4535     // Now we should have the closing ']'
4536     if (Parser.getTok().isNot(AsmToken::RBrac))
4537       return Error(Parser.getTok().getLoc(), "']' expected");
4538     E = Parser.getTok().getEndLoc();
4539     Parser.Lex(); // Eat right bracket token.
4540 
4541     // Don't worry about range checking the value here. That's handled by
4542     // the is*() predicates.
4543     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4544                                              ARM_AM::no_shift, 0, Align,
4545                                              false, S, E, AlignmentLoc));
4546 
4547     // If there's a pre-indexing writeback marker, '!', just add it as a token
4548     // operand.
4549     if (Parser.getTok().is(AsmToken::Exclaim)) {
4550       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4551       Parser.Lex(); // Eat the '!'.
4552     }
4553 
4554     return false;
4555   }
4556 
4557   // If we have a '#', it's an immediate offset, else assume it's a register
4558   // offset. Be friendly and also accept a plain integer (without a leading
4559   // hash) for gas compatibility.
4560   if (Parser.getTok().is(AsmToken::Hash) ||
4561       Parser.getTok().is(AsmToken::Dollar) ||
4562       Parser.getTok().is(AsmToken::Integer)) {
4563     if (Parser.getTok().isNot(AsmToken::Integer))
4564       Parser.Lex(); // Eat '#' or '$'.
4565     E = Parser.getTok().getLoc();
4566 
4567     bool isNegative = getParser().getTok().is(AsmToken::Minus);
4568     const MCExpr *Offset;
4569     if (getParser().parseExpression(Offset))
4570      return true;
4571 
4572     // The expression has to be a constant. Memory references with relocations
4573     // don't come through here, as they use the <label> forms of the relevant
4574     // instructions.
4575     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4576     if (!CE)
4577       return Error (E, "constant expression expected");
4578 
4579     // If the constant was #-0, represent it as INT32_MIN.
4580     int32_t Val = CE->getValue();
4581     if (isNegative && Val == 0)
4582       CE = MCConstantExpr::Create(INT32_MIN, getContext());
4583 
4584     // Now we should have the closing ']'
4585     if (Parser.getTok().isNot(AsmToken::RBrac))
4586       return Error(Parser.getTok().getLoc(), "']' expected");
4587     E = Parser.getTok().getEndLoc();
4588     Parser.Lex(); // Eat right bracket token.
4589 
4590     // Don't worry about range checking the value here. That's handled by
4591     // the is*() predicates.
4592     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4593                                              ARM_AM::no_shift, 0, 0,
4594                                              false, S, E));
4595 
4596     // If there's a pre-indexing writeback marker, '!', just add it as a token
4597     // operand.
4598     if (Parser.getTok().is(AsmToken::Exclaim)) {
4599       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4600       Parser.Lex(); // Eat the '!'.
4601     }
4602 
4603     return false;
4604   }
4605 
4606   // The register offset is optionally preceded by a '+' or '-'
4607   bool isNegative = false;
4608   if (Parser.getTok().is(AsmToken::Minus)) {
4609     isNegative = true;
4610     Parser.Lex(); // Eat the '-'.
4611   } else if (Parser.getTok().is(AsmToken::Plus)) {
4612     // Nothing to do.
4613     Parser.Lex(); // Eat the '+'.
4614   }
4615 
4616   E = Parser.getTok().getLoc();
4617   int OffsetRegNum = tryParseRegister();
4618   if (OffsetRegNum == -1)
4619     return Error(E, "register expected");
4620 
4621   // If there's a shift operator, handle it.
4622   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4623   unsigned ShiftImm = 0;
4624   if (Parser.getTok().is(AsmToken::Comma)) {
4625     Parser.Lex(); // Eat the ','.
4626     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4627       return true;
4628   }
4629 
4630   // Now we should have the closing ']'
4631   if (Parser.getTok().isNot(AsmToken::RBrac))
4632     return Error(Parser.getTok().getLoc(), "']' expected");
4633   E = Parser.getTok().getEndLoc();
4634   Parser.Lex(); // Eat right bracket token.
4635 
4636   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4637                                            ShiftType, ShiftImm, 0, isNegative,
4638                                            S, E));
4639 
4640   // If there's a pre-indexing writeback marker, '!', just add it as a token
4641   // operand.
4642   if (Parser.getTok().is(AsmToken::Exclaim)) {
4643     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4644     Parser.Lex(); // Eat the '!'.
4645   }
4646 
4647   return false;
4648 }
4649 
4650 /// parseMemRegOffsetShift - one of these two:
4651 ///   ( lsl | lsr | asr | ror ) , # shift_amount
4652 ///   rrx
4653 /// return true if it parses a shift otherwise it returns false.
4654 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4655                                           unsigned &Amount) {
4656   SMLoc Loc = Parser.getTok().getLoc();
4657   const AsmToken &Tok = Parser.getTok();
4658   if (Tok.isNot(AsmToken::Identifier))
4659     return true;
4660   StringRef ShiftName = Tok.getString();
4661   if (ShiftName == "lsl" || ShiftName == "LSL" ||
4662       ShiftName == "asl" || ShiftName == "ASL")
4663     St = ARM_AM::lsl;
4664   else if (ShiftName == "lsr" || ShiftName == "LSR")
4665     St = ARM_AM::lsr;
4666   else if (ShiftName == "asr" || ShiftName == "ASR")
4667     St = ARM_AM::asr;
4668   else if (ShiftName == "ror" || ShiftName == "ROR")
4669     St = ARM_AM::ror;
4670   else if (ShiftName == "rrx" || ShiftName == "RRX")
4671     St = ARM_AM::rrx;
4672   else
4673     return Error(Loc, "illegal shift operator");
4674   Parser.Lex(); // Eat shift type token.
4675 
4676   // rrx stands alone.
4677   Amount = 0;
4678   if (St != ARM_AM::rrx) {
4679     Loc = Parser.getTok().getLoc();
4680     // A '#' and a shift amount.
4681     const AsmToken &HashTok = Parser.getTok();
4682     if (HashTok.isNot(AsmToken::Hash) &&
4683         HashTok.isNot(AsmToken::Dollar))
4684       return Error(HashTok.getLoc(), "'#' expected");
4685     Parser.Lex(); // Eat hash token.
4686 
4687     const MCExpr *Expr;
4688     if (getParser().parseExpression(Expr))
4689       return true;
4690     // Range check the immediate.
4691     // lsl, ror: 0 <= imm <= 31
4692     // lsr, asr: 0 <= imm <= 32
4693     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4694     if (!CE)
4695       return Error(Loc, "shift amount must be an immediate");
4696     int64_t Imm = CE->getValue();
4697     if (Imm < 0 ||
4698         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4699         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4700       return Error(Loc, "immediate shift value out of range");
4701     // If <ShiftTy> #0, turn it into a no_shift.
4702     if (Imm == 0)
4703       St = ARM_AM::lsl;
4704     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4705     if (Imm == 32)
4706       Imm = 0;
4707     Amount = Imm;
4708   }
4709 
4710   return false;
4711 }
4712 
4713 /// parseFPImm - A floating point immediate expression operand.
4714 ARMAsmParser::OperandMatchResultTy
4715 ARMAsmParser::parseFPImm(OperandVector &Operands) {
4716   // Anything that can accept a floating point constant as an operand
4717   // needs to go through here, as the regular parseExpression is
4718   // integer only.
4719   //
4720   // This routine still creates a generic Immediate operand, containing
4721   // a bitcast of the 64-bit floating point value. The various operands
4722   // that accept floats can check whether the value is valid for them
4723   // via the standard is*() predicates.
4724 
4725   SMLoc S = Parser.getTok().getLoc();
4726 
4727   if (Parser.getTok().isNot(AsmToken::Hash) &&
4728       Parser.getTok().isNot(AsmToken::Dollar))
4729     return MatchOperand_NoMatch;
4730 
4731   // Disambiguate the VMOV forms that can accept an FP immediate.
4732   // vmov.f32 <sreg>, #imm
4733   // vmov.f64 <dreg>, #imm
4734   // vmov.f32 <dreg>, #imm  @ vector f32x2
4735   // vmov.f32 <qreg>, #imm  @ vector f32x4
4736   //
4737   // There are also the NEON VMOV instructions which expect an
4738   // integer constant. Make sure we don't try to parse an FPImm
4739   // for these:
4740   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4741   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
4742   bool isVmovf = TyOp.isToken() &&
4743                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
4744   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
4745   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
4746                                          Mnemonic.getToken() == "fconsts");
4747   if (!(isVmovf || isFconst))
4748     return MatchOperand_NoMatch;
4749 
4750   Parser.Lex(); // Eat '#' or '$'.
4751 
4752   // Handle negation, as that still comes through as a separate token.
4753   bool isNegative = false;
4754   if (Parser.getTok().is(AsmToken::Minus)) {
4755     isNegative = true;
4756     Parser.Lex();
4757   }
4758   const AsmToken &Tok = Parser.getTok();
4759   SMLoc Loc = Tok.getLoc();
4760   if (Tok.is(AsmToken::Real) && isVmovf) {
4761     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4762     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4763     // If we had a '-' in front, toggle the sign bit.
4764     IntVal ^= (uint64_t)isNegative << 31;
4765     Parser.Lex(); // Eat the token.
4766     Operands.push_back(ARMOperand::CreateImm(
4767           MCConstantExpr::Create(IntVal, getContext()),
4768           S, Parser.getTok().getLoc()));
4769     return MatchOperand_Success;
4770   }
4771   // Also handle plain integers. Instructions which allow floating point
4772   // immediates also allow a raw encoded 8-bit value.
4773   if (Tok.is(AsmToken::Integer) && isFconst) {
4774     int64_t Val = Tok.getIntVal();
4775     Parser.Lex(); // Eat the token.
4776     if (Val > 255 || Val < 0) {
4777       Error(Loc, "encoded floating point value out of range");
4778       return MatchOperand_ParseFail;
4779     }
4780     float RealVal = ARM_AM::getFPImmFloat(Val);
4781     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4782 
4783     Operands.push_back(ARMOperand::CreateImm(
4784         MCConstantExpr::Create(Val, getContext()), S,
4785         Parser.getTok().getLoc()));
4786     return MatchOperand_Success;
4787   }
4788 
4789   Error(Loc, "invalid floating point immediate");
4790   return MatchOperand_ParseFail;
4791 }
4792 
4793 /// Parse a arm instruction operand.  For now this parses the operand regardless
4794 /// of the mnemonic.
4795 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
4796   SMLoc S, E;
4797 
4798   // Check if the current operand has a custom associated parser, if so, try to
4799   // custom parse the operand, or fallback to the general approach.
4800   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4801   if (ResTy == MatchOperand_Success)
4802     return false;
4803   // If there wasn't a custom match, try the generic matcher below. Otherwise,
4804   // there was a match, but an error occurred, in which case, just return that
4805   // the operand parsing failed.
4806   if (ResTy == MatchOperand_ParseFail)
4807     return true;
4808 
4809   switch (getLexer().getKind()) {
4810   default:
4811     Error(Parser.getTok().getLoc(), "unexpected token in operand");
4812     return true;
4813   case AsmToken::Identifier: {
4814     // If we've seen a branch mnemonic, the next operand must be a label.  This
4815     // is true even if the label is a register name.  So "br r1" means branch to
4816     // label "r1".
4817     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4818     if (!ExpectLabel) {
4819       if (!tryParseRegisterWithWriteBack(Operands))
4820         return false;
4821       int Res = tryParseShiftRegister(Operands);
4822       if (Res == 0) // success
4823         return false;
4824       else if (Res == -1) // irrecoverable error
4825         return true;
4826       // If this is VMRS, check for the apsr_nzcv operand.
4827       if (Mnemonic == "vmrs" &&
4828           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4829         S = Parser.getTok().getLoc();
4830         Parser.Lex();
4831         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4832         return false;
4833       }
4834     }
4835 
4836     // Fall though for the Identifier case that is not a register or a
4837     // special name.
4838   }
4839   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4840   case AsmToken::Integer: // things like 1f and 2b as a branch targets
4841   case AsmToken::String:  // quoted label names.
4842   case AsmToken::Dot: {   // . as a branch target
4843     // This was not a register so parse other operands that start with an
4844     // identifier (like labels) as expressions and create them as immediates.
4845     const MCExpr *IdVal;
4846     S = Parser.getTok().getLoc();
4847     if (getParser().parseExpression(IdVal))
4848       return true;
4849     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4850     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4851     return false;
4852   }
4853   case AsmToken::LBrac:
4854     return parseMemory(Operands);
4855   case AsmToken::LCurly:
4856     return parseRegisterList(Operands);
4857   case AsmToken::Dollar:
4858   case AsmToken::Hash: {
4859     // #42 -> immediate.
4860     S = Parser.getTok().getLoc();
4861     Parser.Lex();
4862 
4863     if (Parser.getTok().isNot(AsmToken::Colon)) {
4864       bool isNegative = Parser.getTok().is(AsmToken::Minus);
4865       const MCExpr *ImmVal;
4866       if (getParser().parseExpression(ImmVal))
4867         return true;
4868       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4869       if (CE) {
4870         int32_t Val = CE->getValue();
4871         if (isNegative && Val == 0)
4872           ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4873       }
4874       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4875       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4876 
4877       // There can be a trailing '!' on operands that we want as a separate
4878       // '!' Token operand. Handle that here. For example, the compatibility
4879       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4880       if (Parser.getTok().is(AsmToken::Exclaim)) {
4881         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4882                                                    Parser.getTok().getLoc()));
4883         Parser.Lex(); // Eat exclaim token
4884       }
4885       return false;
4886     }
4887     // w/ a ':' after the '#', it's just like a plain ':'.
4888     // FALLTHROUGH
4889   }
4890   case AsmToken::Colon: {
4891     // ":lower16:" and ":upper16:" expression prefixes
4892     // FIXME: Check it's an expression prefix,
4893     // e.g. (FOO - :lower16:BAR) isn't legal.
4894     ARMMCExpr::VariantKind RefKind;
4895     if (parsePrefix(RefKind))
4896       return true;
4897 
4898     const MCExpr *SubExprVal;
4899     if (getParser().parseExpression(SubExprVal))
4900       return true;
4901 
4902     const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4903                                               getContext());
4904     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4905     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4906     return false;
4907   }
4908   case AsmToken::Equal: {
4909     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4910       return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4911 
4912     Parser.Lex(); // Eat '='
4913     const MCExpr *SubExprVal;
4914     if (getParser().parseExpression(SubExprVal))
4915       return true;
4916     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4917 
4918     const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4919     Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4920     return false;
4921   }
4922   }
4923 }
4924 
4925 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4926 //  :lower16: and :upper16:.
4927 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4928   RefKind = ARMMCExpr::VK_ARM_None;
4929 
4930   // consume an optional '#' (GNU compatibility)
4931   if (getLexer().is(AsmToken::Hash))
4932     Parser.Lex();
4933 
4934   // :lower16: and :upper16: modifiers
4935   assert(getLexer().is(AsmToken::Colon) && "expected a :");
4936   Parser.Lex(); // Eat ':'
4937 
4938   if (getLexer().isNot(AsmToken::Identifier)) {
4939     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4940     return true;
4941   }
4942 
4943   StringRef IDVal = Parser.getTok().getIdentifier();
4944   if (IDVal == "lower16") {
4945     RefKind = ARMMCExpr::VK_ARM_LO16;
4946   } else if (IDVal == "upper16") {
4947     RefKind = ARMMCExpr::VK_ARM_HI16;
4948   } else {
4949     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4950     return true;
4951   }
4952   Parser.Lex();
4953 
4954   if (getLexer().isNot(AsmToken::Colon)) {
4955     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4956     return true;
4957   }
4958   Parser.Lex(); // Eat the last ':'
4959   return false;
4960 }
4961 
4962 /// \brief Given a mnemonic, split out possible predication code and carry
4963 /// setting letters to form a canonical mnemonic and flags.
4964 //
4965 // FIXME: Would be nice to autogen this.
4966 // FIXME: This is a bit of a maze of special cases.
4967 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4968                                       unsigned &PredicationCode,
4969                                       bool &CarrySetting,
4970                                       unsigned &ProcessorIMod,
4971                                       StringRef &ITMask) {
4972   PredicationCode = ARMCC::AL;
4973   CarrySetting = false;
4974   ProcessorIMod = 0;
4975 
4976   // Ignore some mnemonics we know aren't predicated forms.
4977   //
4978   // FIXME: Would be nice to autogen this.
4979   if ((Mnemonic == "movs" && isThumb()) ||
4980       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4981       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4982       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4983       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4984       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
4985       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4986       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4987       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4988       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4989       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
4990       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4991       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4992     return Mnemonic;
4993 
4994   // First, split out any predication code. Ignore mnemonics we know aren't
4995   // predicated but do have a carry-set and so weren't caught above.
4996   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4997       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4998       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4999       Mnemonic != "sbcs" && Mnemonic != "rscs") {
5000     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5001       .Case("eq", ARMCC::EQ)
5002       .Case("ne", ARMCC::NE)
5003       .Case("hs", ARMCC::HS)
5004       .Case("cs", ARMCC::HS)
5005       .Case("lo", ARMCC::LO)
5006       .Case("cc", ARMCC::LO)
5007       .Case("mi", ARMCC::MI)
5008       .Case("pl", ARMCC::PL)
5009       .Case("vs", ARMCC::VS)
5010       .Case("vc", ARMCC::VC)
5011       .Case("hi", ARMCC::HI)
5012       .Case("ls", ARMCC::LS)
5013       .Case("ge", ARMCC::GE)
5014       .Case("lt", ARMCC::LT)
5015       .Case("gt", ARMCC::GT)
5016       .Case("le", ARMCC::LE)
5017       .Case("al", ARMCC::AL)
5018       .Default(~0U);
5019     if (CC != ~0U) {
5020       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5021       PredicationCode = CC;
5022     }
5023   }
5024 
5025   // Next, determine if we have a carry setting bit. We explicitly ignore all
5026   // the instructions we know end in 's'.
5027   if (Mnemonic.endswith("s") &&
5028       !(Mnemonic == "cps" || Mnemonic == "mls" ||
5029         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5030         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5031         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5032         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5033         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5034         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5035         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5036         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5037         (Mnemonic == "movs" && isThumb()))) {
5038     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5039     CarrySetting = true;
5040   }
5041 
5042   // The "cps" instruction can have a interrupt mode operand which is glued into
5043   // the mnemonic. Check if this is the case, split it and parse the imod op
5044   if (Mnemonic.startswith("cps")) {
5045     // Split out any imod code.
5046     unsigned IMod =
5047       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5048       .Case("ie", ARM_PROC::IE)
5049       .Case("id", ARM_PROC::ID)
5050       .Default(~0U);
5051     if (IMod != ~0U) {
5052       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5053       ProcessorIMod = IMod;
5054     }
5055   }
5056 
5057   // The "it" instruction has the condition mask on the end of the mnemonic.
5058   if (Mnemonic.startswith("it")) {
5059     ITMask = Mnemonic.slice(2, Mnemonic.size());
5060     Mnemonic = Mnemonic.slice(0, 2);
5061   }
5062 
5063   return Mnemonic;
5064 }
5065 
5066 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5067 /// inclusion of carry set or predication code operands.
5068 //
5069 // FIXME: It would be nice to autogen this.
5070 void ARMAsmParser::
5071 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5072                      bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5073   if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5074       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5075       Mnemonic == "add" || Mnemonic == "adc" ||
5076       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5077       Mnemonic == "orr" || Mnemonic == "mvn" ||
5078       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5079       Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5080       Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5081       (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5082                       Mnemonic == "mla" || Mnemonic == "smlal" ||
5083                       Mnemonic == "umlal" || Mnemonic == "umull"))) {
5084     CanAcceptCarrySet = true;
5085   } else
5086     CanAcceptCarrySet = false;
5087 
5088   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5089       Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
5090       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5091       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5092       Mnemonic.startswith("vsel") ||
5093       Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5094       Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5095       Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5096       Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5097       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5098       (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5099     // These mnemonics are never predicable
5100     CanAcceptPredicationCode = false;
5101   } else if (!isThumb()) {
5102     // Some instructions are only predicable in Thumb mode
5103     CanAcceptPredicationCode
5104       = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5105         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5106         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5107         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5108         Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5109         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5110         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5111   } else if (isThumbOne()) {
5112     if (hasV6MOps())
5113       CanAcceptPredicationCode = Mnemonic != "movs";
5114     else
5115       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5116   } else
5117     CanAcceptPredicationCode = true;
5118 }
5119 
5120 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5121                                           OperandVector &Operands) {
5122   // FIXME: This is all horribly hacky. We really need a better way to deal
5123   // with optional operands like this in the matcher table.
5124 
5125   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5126   // another does not. Specifically, the MOVW instruction does not. So we
5127   // special case it here and remove the defaulted (non-setting) cc_out
5128   // operand if that's the instruction we're trying to match.
5129   //
5130   // We do this as post-processing of the explicit operands rather than just
5131   // conditionally adding the cc_out in the first place because we need
5132   // to check the type of the parsed immediate operand.
5133   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5134       !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() &&
5135       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5136       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5137     return true;
5138 
5139   // Register-register 'add' for thumb does not have a cc_out operand
5140   // when there are only two register operands.
5141   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5142       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5143       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5144       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5145     return true;
5146   // Register-register 'add' for thumb does not have a cc_out operand
5147   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5148   // have to check the immediate range here since Thumb2 has a variant
5149   // that can handle a different range and has a cc_out operand.
5150   if (((isThumb() && Mnemonic == "add") ||
5151        (isThumbTwo() && Mnemonic == "sub")) &&
5152       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5153       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5154       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5155       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5156       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5157        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5158     return true;
5159   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5160   // imm0_4095 variant. That's the least-preferred variant when
5161   // selecting via the generic "add" mnemonic, so to know that we
5162   // should remove the cc_out operand, we have to explicitly check that
5163   // it's not one of the other variants. Ugh.
5164   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5165       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5166       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5167       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5168     // Nest conditions rather than one big 'if' statement for readability.
5169     //
5170     // If both registers are low, we're in an IT block, and the immediate is
5171     // in range, we should use encoding T1 instead, which has a cc_out.
5172     if (inITBlock() &&
5173         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5174         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5175         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5176       return false;
5177     // Check against T3. If the second register is the PC, this is an
5178     // alternate form of ADR, which uses encoding T4, so check for that too.
5179     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5180         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5181       return false;
5182 
5183     // Otherwise, we use encoding T4, which does not have a cc_out
5184     // operand.
5185     return true;
5186   }
5187 
5188   // The thumb2 multiply instruction doesn't have a CCOut register, so
5189   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5190   // use the 16-bit encoding or not.
5191   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5192       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5193       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5194       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5195       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5196       // If the registers aren't low regs, the destination reg isn't the
5197       // same as one of the source regs, or the cc_out operand is zero
5198       // outside of an IT block, we have to use the 32-bit encoding, so
5199       // remove the cc_out operand.
5200       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5201        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5202        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5203        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5204                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5205                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5206                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
5207     return true;
5208 
5209   // Also check the 'mul' syntax variant that doesn't specify an explicit
5210   // destination register.
5211   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5212       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5213       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5214       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5215       // If the registers aren't low regs  or the cc_out operand is zero
5216       // outside of an IT block, we have to use the 32-bit encoding, so
5217       // remove the cc_out operand.
5218       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5219        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5220        !inITBlock()))
5221     return true;
5222 
5223 
5224 
5225   // Register-register 'add/sub' for thumb does not have a cc_out operand
5226   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5227   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5228   // right, this will result in better diagnostics (which operand is off)
5229   // anyway.
5230   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5231       (Operands.size() == 5 || Operands.size() == 6) &&
5232       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5233       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5234       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5235       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5236        (Operands.size() == 6 &&
5237         static_cast<ARMOperand &>(*Operands[5]).isImm())))
5238     return true;
5239 
5240   return false;
5241 }
5242 
5243 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5244                                               OperandVector &Operands) {
5245   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5246   unsigned RegIdx = 3;
5247   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5248       static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5249     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5250         static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5251       RegIdx = 4;
5252 
5253     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5254         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5255              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5256          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5257              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5258       return true;
5259   }
5260   return false;
5261 }
5262 
5263 static bool isDataTypeToken(StringRef Tok) {
5264   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5265     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5266     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5267     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5268     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5269     Tok == ".f" || Tok == ".d";
5270 }
5271 
5272 // FIXME: This bit should probably be handled via an explicit match class
5273 // in the .td files that matches the suffix instead of having it be
5274 // a literal string token the way it is now.
5275 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5276   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5277 }
5278 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5279                                  unsigned VariantID);
5280 
5281 static bool RequiresVFPRegListValidation(StringRef Inst,
5282                                          bool &AcceptSinglePrecisionOnly,
5283                                          bool &AcceptDoublePrecisionOnly) {
5284   if (Inst.size() < 7)
5285     return false;
5286 
5287   if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5288     StringRef AddressingMode = Inst.substr(4, 2);
5289     if (AddressingMode == "ia" || AddressingMode == "db" ||
5290         AddressingMode == "ea" || AddressingMode == "fd") {
5291       AcceptSinglePrecisionOnly = Inst[6] == 's';
5292       AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5293       return true;
5294     }
5295   }
5296 
5297   return false;
5298 }
5299 
5300 /// Parse an arm instruction mnemonic followed by its operands.
5301 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5302                                     SMLoc NameLoc, OperandVector &Operands) {
5303   // FIXME: Can this be done via tablegen in some fashion?
5304   bool RequireVFPRegisterListCheck;
5305   bool AcceptSinglePrecisionOnly;
5306   bool AcceptDoublePrecisionOnly;
5307   RequireVFPRegisterListCheck =
5308     RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5309                                  AcceptDoublePrecisionOnly);
5310 
5311   // Apply mnemonic aliases before doing anything else, as the destination
5312   // mnemonic may include suffices and we want to handle them normally.
5313   // The generic tblgen'erated code does this later, at the start of
5314   // MatchInstructionImpl(), but that's too late for aliases that include
5315   // any sort of suffix.
5316   unsigned AvailableFeatures = getAvailableFeatures();
5317   unsigned AssemblerDialect = getParser().getAssemblerDialect();
5318   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5319 
5320   // First check for the ARM-specific .req directive.
5321   if (Parser.getTok().is(AsmToken::Identifier) &&
5322       Parser.getTok().getIdentifier() == ".req") {
5323     parseDirectiveReq(Name, NameLoc);
5324     // We always return 'error' for this, as we're done with this
5325     // statement and don't need to match the 'instruction."
5326     return true;
5327   }
5328 
5329   // Create the leading tokens for the mnemonic, split by '.' characters.
5330   size_t Start = 0, Next = Name.find('.');
5331   StringRef Mnemonic = Name.slice(Start, Next);
5332 
5333   // Split out the predication code and carry setting flag from the mnemonic.
5334   unsigned PredicationCode;
5335   unsigned ProcessorIMod;
5336   bool CarrySetting;
5337   StringRef ITMask;
5338   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5339                            ProcessorIMod, ITMask);
5340 
5341   // In Thumb1, only the branch (B) instruction can be predicated.
5342   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5343     Parser.eatToEndOfStatement();
5344     return Error(NameLoc, "conditional execution not supported in Thumb1");
5345   }
5346 
5347   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5348 
5349   // Handle the IT instruction ITMask. Convert it to a bitmask. This
5350   // is the mask as it will be for the IT encoding if the conditional
5351   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5352   // where the conditional bit0 is zero, the instruction post-processing
5353   // will adjust the mask accordingly.
5354   if (Mnemonic == "it") {
5355     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5356     if (ITMask.size() > 3) {
5357       Parser.eatToEndOfStatement();
5358       return Error(Loc, "too many conditions on IT instruction");
5359     }
5360     unsigned Mask = 8;
5361     for (unsigned i = ITMask.size(); i != 0; --i) {
5362       char pos = ITMask[i - 1];
5363       if (pos != 't' && pos != 'e') {
5364         Parser.eatToEndOfStatement();
5365         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5366       }
5367       Mask >>= 1;
5368       if (ITMask[i - 1] == 't')
5369         Mask |= 8;
5370     }
5371     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5372   }
5373 
5374   // FIXME: This is all a pretty gross hack. We should automatically handle
5375   // optional operands like this via tblgen.
5376 
5377   // Next, add the CCOut and ConditionCode operands, if needed.
5378   //
5379   // For mnemonics which can ever incorporate a carry setting bit or predication
5380   // code, our matching model involves us always generating CCOut and
5381   // ConditionCode operands to match the mnemonic "as written" and then we let
5382   // the matcher deal with finding the right instruction or generating an
5383   // appropriate error.
5384   bool CanAcceptCarrySet, CanAcceptPredicationCode;
5385   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5386 
5387   // If we had a carry-set on an instruction that can't do that, issue an
5388   // error.
5389   if (!CanAcceptCarrySet && CarrySetting) {
5390     Parser.eatToEndOfStatement();
5391     return Error(NameLoc, "instruction '" + Mnemonic +
5392                  "' can not set flags, but 's' suffix specified");
5393   }
5394   // If we had a predication code on an instruction that can't do that, issue an
5395   // error.
5396   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5397     Parser.eatToEndOfStatement();
5398     return Error(NameLoc, "instruction '" + Mnemonic +
5399                  "' is not predicable, but condition code specified");
5400   }
5401 
5402   // Add the carry setting operand, if necessary.
5403   if (CanAcceptCarrySet) {
5404     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5405     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5406                                                Loc));
5407   }
5408 
5409   // Add the predication code operand, if necessary.
5410   if (CanAcceptPredicationCode) {
5411     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5412                                       CarrySetting);
5413     Operands.push_back(ARMOperand::CreateCondCode(
5414                          ARMCC::CondCodes(PredicationCode), Loc));
5415   }
5416 
5417   // Add the processor imod operand, if necessary.
5418   if (ProcessorIMod) {
5419     Operands.push_back(ARMOperand::CreateImm(
5420           MCConstantExpr::Create(ProcessorIMod, getContext()),
5421                                  NameLoc, NameLoc));
5422   }
5423 
5424   // Add the remaining tokens in the mnemonic.
5425   while (Next != StringRef::npos) {
5426     Start = Next;
5427     Next = Name.find('.', Start + 1);
5428     StringRef ExtraToken = Name.slice(Start, Next);
5429 
5430     // Some NEON instructions have an optional datatype suffix that is
5431     // completely ignored. Check for that.
5432     if (isDataTypeToken(ExtraToken) &&
5433         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5434       continue;
5435 
5436     // For for ARM mode generate an error if the .n qualifier is used.
5437     if (ExtraToken == ".n" && !isThumb()) {
5438       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5439       Parser.eatToEndOfStatement();
5440       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5441                    "arm mode");
5442     }
5443 
5444     // The .n qualifier is always discarded as that is what the tables
5445     // and matcher expect.  In ARM mode the .w qualifier has no effect,
5446     // so discard it to avoid errors that can be caused by the matcher.
5447     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5448       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5449       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5450     }
5451   }
5452 
5453   // Read the remaining operands.
5454   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5455     // Read the first operand.
5456     if (parseOperand(Operands, Mnemonic)) {
5457       Parser.eatToEndOfStatement();
5458       return true;
5459     }
5460 
5461     while (getLexer().is(AsmToken::Comma)) {
5462       Parser.Lex();  // Eat the comma.
5463 
5464       // Parse and remember the operand.
5465       if (parseOperand(Operands, Mnemonic)) {
5466         Parser.eatToEndOfStatement();
5467         return true;
5468       }
5469     }
5470   }
5471 
5472   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5473     SMLoc Loc = getLexer().getLoc();
5474     Parser.eatToEndOfStatement();
5475     return Error(Loc, "unexpected token in argument list");
5476   }
5477 
5478   Parser.Lex(); // Consume the EndOfStatement
5479 
5480   if (RequireVFPRegisterListCheck) {
5481     ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5482     if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5483       return Error(Op.getStartLoc(),
5484                    "VFP/Neon single precision register expected");
5485     if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5486       return Error(Op.getStartLoc(),
5487                    "VFP/Neon double precision register expected");
5488   }
5489 
5490   // Some instructions, mostly Thumb, have forms for the same mnemonic that
5491   // do and don't have a cc_out optional-def operand. With some spot-checks
5492   // of the operand list, we can figure out which variant we're trying to
5493   // parse and adjust accordingly before actually matching. We shouldn't ever
5494   // try to remove a cc_out operand that was explicitly set on the the
5495   // mnemonic, of course (CarrySetting == true). Reason number #317 the
5496   // table driven matcher doesn't fit well with the ARM instruction set.
5497   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5498     Operands.erase(Operands.begin() + 1);
5499 
5500   // Some instructions have the same mnemonic, but don't always
5501   // have a predicate. Distinguish them here and delete the
5502   // predicate if needed.
5503   if (shouldOmitPredicateOperand(Mnemonic, Operands))
5504     Operands.erase(Operands.begin() + 1);
5505 
5506   // ARM mode 'blx' need special handling, as the register operand version
5507   // is predicable, but the label operand version is not. So, we can't rely
5508   // on the Mnemonic based checking to correctly figure out when to put
5509   // a k_CondCode operand in the list. If we're trying to match the label
5510   // version, remove the k_CondCode operand here.
5511   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5512       static_cast<ARMOperand &>(*Operands[2]).isImm())
5513     Operands.erase(Operands.begin() + 1);
5514 
5515   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5516   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5517   // a single GPRPair reg operand is used in the .td file to replace the two
5518   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5519   // expressed as a GPRPair, so we have to manually merge them.
5520   // FIXME: We would really like to be able to tablegen'erate this.
5521   if (!isThumb() && Operands.size() > 4 &&
5522       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5523        Mnemonic == "stlexd")) {
5524     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5525     unsigned Idx = isLoad ? 2 : 3;
5526     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5527     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5528 
5529     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5530     // Adjust only if Op1 and Op2 are GPRs.
5531     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5532         MRC.contains(Op2.getReg())) {
5533       unsigned Reg1 = Op1.getReg();
5534       unsigned Reg2 = Op2.getReg();
5535       unsigned Rt = MRI->getEncodingValue(Reg1);
5536       unsigned Rt2 = MRI->getEncodingValue(Reg2);
5537 
5538       // Rt2 must be Rt + 1 and Rt must be even.
5539       if (Rt + 1 != Rt2 || (Rt & 1)) {
5540         Error(Op2.getStartLoc(), isLoad
5541                                      ? "destination operands must be sequential"
5542                                      : "source operands must be sequential");
5543         return true;
5544       }
5545       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5546           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5547       Operands[Idx] =
5548           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5549       Operands.erase(Operands.begin() + Idx + 1);
5550     }
5551   }
5552 
5553   // GNU Assembler extension (compatibility)
5554   if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5555     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5556     ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5557     if (Op3.isMem()) {
5558       assert(Op2.isReg() && "expected register argument");
5559 
5560       unsigned SuperReg = MRI->getMatchingSuperReg(
5561           Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5562 
5563       assert(SuperReg && "expected register pair");
5564 
5565       unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5566 
5567       Operands.insert(
5568           Operands.begin() + 3,
5569           ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5570     }
5571   }
5572 
5573   // FIXME: As said above, this is all a pretty gross hack.  This instruction
5574   // does not fit with other "subs" and tblgen.
5575   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5576   // so the Mnemonic is the original name "subs" and delete the predicate
5577   // operand so it will match the table entry.
5578   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5579       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5580       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5581       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5582       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5583       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5584     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5585     Operands.erase(Operands.begin() + 1);
5586   }
5587   return false;
5588 }
5589 
5590 // Validate context-sensitive operand constraints.
5591 
5592 // return 'true' if register list contains non-low GPR registers,
5593 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5594 // 'containsReg' to true.
5595 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5596                                  unsigned HiReg, bool &containsReg) {
5597   containsReg = false;
5598   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5599     unsigned OpReg = Inst.getOperand(i).getReg();
5600     if (OpReg == Reg)
5601       containsReg = true;
5602     // Anything other than a low register isn't legal here.
5603     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5604       return true;
5605   }
5606   return false;
5607 }
5608 
5609 // Check if the specified regisgter is in the register list of the inst,
5610 // starting at the indicated operand number.
5611 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5612   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5613     unsigned OpReg = Inst.getOperand(i).getReg();
5614     if (OpReg == Reg)
5615       return true;
5616   }
5617   return false;
5618 }
5619 
5620 // Return true if instruction has the interesting property of being
5621 // allowed in IT blocks, but not being predicable.
5622 static bool instIsBreakpoint(const MCInst &Inst) {
5623     return Inst.getOpcode() == ARM::tBKPT ||
5624            Inst.getOpcode() == ARM::BKPT ||
5625            Inst.getOpcode() == ARM::tHLT ||
5626            Inst.getOpcode() == ARM::HLT;
5627 
5628 }
5629 
5630 // FIXME: We would really like to be able to tablegen'erate this.
5631 bool ARMAsmParser::validateInstruction(MCInst &Inst,
5632                                        const OperandVector &Operands) {
5633   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5634   SMLoc Loc = Operands[0]->getStartLoc();
5635 
5636   // Check the IT block state first.
5637   // NOTE: BKPT and HLT instructions have the interesting property of being
5638   // allowed in IT blocks, but not being predicable. They just always execute.
5639   if (inITBlock() && !instIsBreakpoint(Inst)) {
5640     unsigned Bit = 1;
5641     if (ITState.FirstCond)
5642       ITState.FirstCond = false;
5643     else
5644       Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5645     // The instruction must be predicable.
5646     if (!MCID.isPredicable())
5647       return Error(Loc, "instructions in IT block must be predicable");
5648     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5649     unsigned ITCond = Bit ? ITState.Cond :
5650       ARMCC::getOppositeCondition(ITState.Cond);
5651     if (Cond != ITCond) {
5652       // Find the condition code Operand to get its SMLoc information.
5653       SMLoc CondLoc;
5654       for (unsigned I = 1; I < Operands.size(); ++I)
5655         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
5656           CondLoc = Operands[I]->getStartLoc();
5657       return Error(CondLoc, "incorrect condition in IT block; got '" +
5658                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5659                    "', but expected '" +
5660                    ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5661     }
5662   // Check for non-'al' condition codes outside of the IT block.
5663   } else if (isThumbTwo() && MCID.isPredicable() &&
5664              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5665              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5666              Inst.getOpcode() != ARM::t2Bcc)
5667     return Error(Loc, "predicated instructions must be in IT block");
5668 
5669   const unsigned Opcode = Inst.getOpcode();
5670   switch (Opcode) {
5671   case ARM::LDRD:
5672   case ARM::LDRD_PRE:
5673   case ARM::LDRD_POST: {
5674     const unsigned RtReg = Inst.getOperand(0).getReg();
5675 
5676     // Rt can't be R14.
5677     if (RtReg == ARM::LR)
5678       return Error(Operands[3]->getStartLoc(),
5679                    "Rt can't be R14");
5680 
5681     const unsigned Rt = MRI->getEncodingValue(RtReg);
5682     // Rt must be even-numbered.
5683     if ((Rt & 1) == 1)
5684       return Error(Operands[3]->getStartLoc(),
5685                    "Rt must be even-numbered");
5686 
5687     // Rt2 must be Rt + 1.
5688     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5689     if (Rt2 != Rt + 1)
5690       return Error(Operands[3]->getStartLoc(),
5691                    "destination operands must be sequential");
5692 
5693     if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5694       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5695       // For addressing modes with writeback, the base register needs to be
5696       // different from the destination registers.
5697       if (Rn == Rt || Rn == Rt2)
5698         return Error(Operands[3]->getStartLoc(),
5699                      "base register needs to be different from destination "
5700                      "registers");
5701     }
5702 
5703     return false;
5704   }
5705   case ARM::t2LDRDi8:
5706   case ARM::t2LDRD_PRE:
5707   case ARM::t2LDRD_POST: {
5708     // Rt2 must be different from Rt.
5709     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5710     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5711     if (Rt2 == Rt)
5712       return Error(Operands[3]->getStartLoc(),
5713                    "destination operands can't be identical");
5714     return false;
5715   }
5716   case ARM::STRD: {
5717     // Rt2 must be Rt + 1.
5718     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5719     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5720     if (Rt2 != Rt + 1)
5721       return Error(Operands[3]->getStartLoc(),
5722                    "source operands must be sequential");
5723     return false;
5724   }
5725   case ARM::STRD_PRE:
5726   case ARM::STRD_POST: {
5727     // Rt2 must be Rt + 1.
5728     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5729     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5730     if (Rt2 != Rt + 1)
5731       return Error(Operands[3]->getStartLoc(),
5732                    "source operands must be sequential");
5733     return false;
5734   }
5735   case ARM::STR_PRE_IMM:
5736   case ARM::STR_PRE_REG:
5737   case ARM::STR_POST_IMM:
5738   case ARM::STR_POST_REG:
5739   case ARM::STRH_PRE:
5740   case ARM::STRH_POST:
5741   case ARM::STRB_PRE_IMM:
5742   case ARM::STRB_PRE_REG:
5743   case ARM::STRB_POST_IMM:
5744   case ARM::STRB_POST_REG: {
5745     // Rt must be different from Rn.
5746     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5747     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5748 
5749     if (Rt == Rn)
5750       return Error(Operands[3]->getStartLoc(),
5751                    "source register and base register can't be identical");
5752     return false;
5753   }
5754   case ARM::LDR_PRE_IMM:
5755   case ARM::LDR_PRE_REG:
5756   case ARM::LDR_POST_IMM:
5757   case ARM::LDR_POST_REG:
5758   case ARM::LDRH_PRE:
5759   case ARM::LDRH_POST:
5760   case ARM::LDRSH_PRE:
5761   case ARM::LDRSH_POST:
5762   case ARM::LDRB_PRE_IMM:
5763   case ARM::LDRB_PRE_REG:
5764   case ARM::LDRB_POST_IMM:
5765   case ARM::LDRB_POST_REG:
5766   case ARM::LDRSB_PRE:
5767   case ARM::LDRSB_POST: {
5768     // Rt must be different from Rn.
5769     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5770     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5771 
5772     if (Rt == Rn)
5773       return Error(Operands[3]->getStartLoc(),
5774                    "destination register and base register can't be identical");
5775     return false;
5776   }
5777   case ARM::SBFX:
5778   case ARM::UBFX: {
5779     // Width must be in range [1, 32-lsb].
5780     unsigned LSB = Inst.getOperand(2).getImm();
5781     unsigned Widthm1 = Inst.getOperand(3).getImm();
5782     if (Widthm1 >= 32 - LSB)
5783       return Error(Operands[5]->getStartLoc(),
5784                    "bitfield width must be in range [1,32-lsb]");
5785     return false;
5786   }
5787   // Notionally handles ARM::tLDMIA_UPD too.
5788   case ARM::tLDMIA: {
5789     // If we're parsing Thumb2, the .w variant is available and handles
5790     // most cases that are normally illegal for a Thumb1 LDM instruction.
5791     // We'll make the transformation in processInstruction() if necessary.
5792     //
5793     // Thumb LDM instructions are writeback iff the base register is not
5794     // in the register list.
5795     unsigned Rn = Inst.getOperand(0).getReg();
5796     bool HasWritebackToken =
5797         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5798          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
5799     bool ListContainsBase;
5800     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5801       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5802                    "registers must be in range r0-r7");
5803     // If we should have writeback, then there should be a '!' token.
5804     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5805       return Error(Operands[2]->getStartLoc(),
5806                    "writeback operator '!' expected");
5807     // If we should not have writeback, there must not be a '!'. This is
5808     // true even for the 32-bit wide encodings.
5809     if (ListContainsBase && HasWritebackToken)
5810       return Error(Operands[3]->getStartLoc(),
5811                    "writeback operator '!' not allowed when base register "
5812                    "in register list");
5813 
5814     break;
5815   }
5816   case ARM::LDMIA_UPD:
5817   case ARM::LDMDB_UPD:
5818   case ARM::LDMIB_UPD:
5819   case ARM::LDMDA_UPD:
5820     // ARM variants loading and updating the same register are only officially
5821     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5822     if (!hasV7Ops())
5823       break;
5824     // Fallthrough
5825   case ARM::t2LDMIA_UPD:
5826   case ARM::t2LDMDB_UPD:
5827   case ARM::t2STMIA_UPD:
5828   case ARM::t2STMDB_UPD: {
5829     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5830       return Error(Operands.back()->getStartLoc(),
5831                    "writeback register not allowed in register list");
5832     break;
5833   }
5834   case ARM::sysLDMIA_UPD:
5835   case ARM::sysLDMDA_UPD:
5836   case ARM::sysLDMDB_UPD:
5837   case ARM::sysLDMIB_UPD:
5838     if (!listContainsReg(Inst, 3, ARM::PC))
5839       return Error(Operands[4]->getStartLoc(),
5840                    "writeback register only allowed on system LDM "
5841                    "if PC in register-list");
5842     break;
5843   case ARM::sysSTMIA_UPD:
5844   case ARM::sysSTMDA_UPD:
5845   case ARM::sysSTMDB_UPD:
5846   case ARM::sysSTMIB_UPD:
5847     return Error(Operands[2]->getStartLoc(),
5848                  "system STM cannot have writeback register");
5849   case ARM::tMUL: {
5850     // The second source operand must be the same register as the destination
5851     // operand.
5852     //
5853     // In this case, we must directly check the parsed operands because the
5854     // cvtThumbMultiply() function is written in such a way that it guarantees
5855     // this first statement is always true for the new Inst.  Essentially, the
5856     // destination is unconditionally copied into the second source operand
5857     // without checking to see if it matches what we actually parsed.
5858     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
5859                                  ((ARMOperand &)*Operands[5]).getReg()) &&
5860         (((ARMOperand &)*Operands[3]).getReg() !=
5861          ((ARMOperand &)*Operands[4]).getReg())) {
5862       return Error(Operands[3]->getStartLoc(),
5863                    "destination register must match source register");
5864     }
5865     break;
5866   }
5867   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5868   // so only issue a diagnostic for thumb1. The instructions will be
5869   // switched to the t2 encodings in processInstruction() if necessary.
5870   case ARM::tPOP: {
5871     bool ListContainsBase;
5872     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5873         !isThumbTwo())
5874       return Error(Operands[2]->getStartLoc(),
5875                    "registers must be in range r0-r7 or pc");
5876     break;
5877   }
5878   case ARM::tPUSH: {
5879     bool ListContainsBase;
5880     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5881         !isThumbTwo())
5882       return Error(Operands[2]->getStartLoc(),
5883                    "registers must be in range r0-r7 or lr");
5884     break;
5885   }
5886   case ARM::tSTMIA_UPD: {
5887     bool ListContainsBase, InvalidLowList;
5888     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5889                                           0, ListContainsBase);
5890     if (InvalidLowList && !isThumbTwo())
5891       return Error(Operands[4]->getStartLoc(),
5892                    "registers must be in range r0-r7");
5893 
5894     // This would be converted to a 32-bit stm, but that's not valid if the
5895     // writeback register is in the list.
5896     if (InvalidLowList && ListContainsBase)
5897       return Error(Operands[4]->getStartLoc(),
5898                    "writeback operator '!' not allowed when base register "
5899                    "in register list");
5900     break;
5901   }
5902   case ARM::tADDrSP: {
5903     // If the non-SP source operand and the destination operand are not the
5904     // same, we need thumb2 (for the wide encoding), or we have an error.
5905     if (!isThumbTwo() &&
5906         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5907       return Error(Operands[4]->getStartLoc(),
5908                    "source register must be the same as destination");
5909     }
5910     break;
5911   }
5912   // Final range checking for Thumb unconditional branch instructions.
5913   case ARM::tB:
5914     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
5915       return Error(Operands[2]->getStartLoc(), "branch target out of range");
5916     break;
5917   case ARM::t2B: {
5918     int op = (Operands[2]->isImm()) ? 2 : 3;
5919     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
5920       return Error(Operands[op]->getStartLoc(), "branch target out of range");
5921     break;
5922   }
5923   // Final range checking for Thumb conditional branch instructions.
5924   case ARM::tBcc:
5925     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
5926       return Error(Operands[2]->getStartLoc(), "branch target out of range");
5927     break;
5928   case ARM::t2Bcc: {
5929     int Op = (Operands[2]->isImm()) ? 2 : 3;
5930     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
5931       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5932     break;
5933   }
5934   case ARM::MOVi16:
5935   case ARM::t2MOVi16:
5936   case ARM::t2MOVTi16:
5937     {
5938     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
5939     // especially when we turn it into a movw and the expression <symbol> does
5940     // not have a :lower16: or :upper16 as part of the expression.  We don't
5941     // want the behavior of silently truncating, which can be unexpected and
5942     // lead to bugs that are difficult to find since this is an easy mistake
5943     // to make.
5944     int i = (Operands[3]->isImm()) ? 3 : 4;
5945     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
5946     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
5947     if (CE) break;
5948     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
5949     if (!E) break;
5950     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
5951     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
5952                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
5953       return Error(
5954           Op.getStartLoc(),
5955           "immediate expression for mov requires :lower16: or :upper16");
5956     break;
5957   }
5958   }
5959 
5960   return false;
5961 }
5962 
5963 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5964   switch(Opc) {
5965   default: llvm_unreachable("unexpected opcode!");
5966   // VST1LN
5967   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5968   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5969   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5970   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5971   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5972   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5973   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5974   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5975   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5976 
5977   // VST2LN
5978   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5979   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5980   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5981   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5982   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5983 
5984   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5985   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5986   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5987   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5988   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5989 
5990   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5991   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5992   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5993   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5994   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5995 
5996   // VST3LN
5997   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5998   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5999   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6000   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6001   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6002   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6003   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6004   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6005   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6006   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6007   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
6008   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6009   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6010   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6011   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6012 
6013   // VST3
6014   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6015   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6016   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6017   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6018   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6019   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6020   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6021   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6022   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6023   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6024   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6025   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6026   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
6027   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6028   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6029   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
6030   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6031   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6032 
6033   // VST4LN
6034   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6035   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6036   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6037   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6038   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6039   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6040   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6041   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6042   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6043   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6044   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
6045   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6046   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6047   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6048   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6049 
6050   // VST4
6051   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6052   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6053   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6054   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6055   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6056   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6057   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6058   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6059   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6060   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6061   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6062   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6063   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
6064   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6065   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6066   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
6067   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6068   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6069   }
6070 }
6071 
6072 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6073   switch(Opc) {
6074   default: llvm_unreachable("unexpected opcode!");
6075   // VLD1LN
6076   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6077   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6078   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6079   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6080   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6081   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6082   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
6083   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6084   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6085 
6086   // VLD2LN
6087   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6088   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6089   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6090   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6091   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6092   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6093   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6094   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6095   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6096   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6097   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
6098   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6099   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6100   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6101   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6102 
6103   // VLD3DUP
6104   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6105   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6106   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6107   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6108   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6109   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6110   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6111   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6112   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6113   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6114   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6115   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6116   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
6117   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6118   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6119   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6120   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6121   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6122 
6123   // VLD3LN
6124   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6125   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6126   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6127   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6128   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6129   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6130   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6131   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6132   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6133   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6134   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
6135   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6136   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6137   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6138   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6139 
6140   // VLD3
6141   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6142   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6143   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6144   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6145   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6146   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6147   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6148   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6149   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6150   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6151   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6152   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6153   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
6154   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6155   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6156   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
6157   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6158   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6159 
6160   // VLD4LN
6161   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6162   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6163   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6164   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6165   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6166   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6167   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6168   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6169   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6170   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6171   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
6172   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6173   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6174   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6175   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6176 
6177   // VLD4DUP
6178   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6179   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6180   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6181   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6182   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6183   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6184   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6185   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6186   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6187   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6188   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6189   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6190   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
6191   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6192   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6193   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6194   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6195   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6196 
6197   // VLD4
6198   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6199   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6200   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6201   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6202   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6203   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6204   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6205   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6206   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6207   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6208   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6209   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6210   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
6211   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6212   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6213   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
6214   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6215   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6216   }
6217 }
6218 
6219 bool ARMAsmParser::processInstruction(MCInst &Inst,
6220                                       const OperandVector &Operands) {
6221   switch (Inst.getOpcode()) {
6222   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6223   case ARM::LDRT_POST:
6224   case ARM::LDRBT_POST: {
6225     const unsigned Opcode =
6226       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6227                                            : ARM::LDRBT_POST_IMM;
6228     MCInst TmpInst;
6229     TmpInst.setOpcode(Opcode);
6230     TmpInst.addOperand(Inst.getOperand(0));
6231     TmpInst.addOperand(Inst.getOperand(1));
6232     TmpInst.addOperand(Inst.getOperand(1));
6233     TmpInst.addOperand(MCOperand::CreateReg(0));
6234     TmpInst.addOperand(MCOperand::CreateImm(0));
6235     TmpInst.addOperand(Inst.getOperand(2));
6236     TmpInst.addOperand(Inst.getOperand(3));
6237     Inst = TmpInst;
6238     return true;
6239   }
6240   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6241   case ARM::STRT_POST:
6242   case ARM::STRBT_POST: {
6243     const unsigned Opcode =
6244       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6245                                            : ARM::STRBT_POST_IMM;
6246     MCInst TmpInst;
6247     TmpInst.setOpcode(Opcode);
6248     TmpInst.addOperand(Inst.getOperand(1));
6249     TmpInst.addOperand(Inst.getOperand(0));
6250     TmpInst.addOperand(Inst.getOperand(1));
6251     TmpInst.addOperand(MCOperand::CreateReg(0));
6252     TmpInst.addOperand(MCOperand::CreateImm(0));
6253     TmpInst.addOperand(Inst.getOperand(2));
6254     TmpInst.addOperand(Inst.getOperand(3));
6255     Inst = TmpInst;
6256     return true;
6257   }
6258   // Alias for alternate form of 'ADR Rd, #imm' instruction.
6259   case ARM::ADDri: {
6260     if (Inst.getOperand(1).getReg() != ARM::PC ||
6261         Inst.getOperand(5).getReg() != 0)
6262       return false;
6263     MCInst TmpInst;
6264     TmpInst.setOpcode(ARM::ADR);
6265     TmpInst.addOperand(Inst.getOperand(0));
6266     TmpInst.addOperand(Inst.getOperand(2));
6267     TmpInst.addOperand(Inst.getOperand(3));
6268     TmpInst.addOperand(Inst.getOperand(4));
6269     Inst = TmpInst;
6270     return true;
6271   }
6272   // Aliases for alternate PC+imm syntax of LDR instructions.
6273   case ARM::t2LDRpcrel:
6274     // Select the narrow version if the immediate will fit.
6275     if (Inst.getOperand(1).getImm() > 0 &&
6276         Inst.getOperand(1).getImm() <= 0xff &&
6277         !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6278           static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6279       Inst.setOpcode(ARM::tLDRpci);
6280     else
6281       Inst.setOpcode(ARM::t2LDRpci);
6282     return true;
6283   case ARM::t2LDRBpcrel:
6284     Inst.setOpcode(ARM::t2LDRBpci);
6285     return true;
6286   case ARM::t2LDRHpcrel:
6287     Inst.setOpcode(ARM::t2LDRHpci);
6288     return true;
6289   case ARM::t2LDRSBpcrel:
6290     Inst.setOpcode(ARM::t2LDRSBpci);
6291     return true;
6292   case ARM::t2LDRSHpcrel:
6293     Inst.setOpcode(ARM::t2LDRSHpci);
6294     return true;
6295   // Handle NEON VST complex aliases.
6296   case ARM::VST1LNdWB_register_Asm_8:
6297   case ARM::VST1LNdWB_register_Asm_16:
6298   case ARM::VST1LNdWB_register_Asm_32: {
6299     MCInst TmpInst;
6300     // Shuffle the operands around so the lane index operand is in the
6301     // right place.
6302     unsigned Spacing;
6303     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6304     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6305     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6306     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6307     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6308     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6309     TmpInst.addOperand(Inst.getOperand(1)); // lane
6310     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6311     TmpInst.addOperand(Inst.getOperand(6));
6312     Inst = TmpInst;
6313     return true;
6314   }
6315 
6316   case ARM::VST2LNdWB_register_Asm_8:
6317   case ARM::VST2LNdWB_register_Asm_16:
6318   case ARM::VST2LNdWB_register_Asm_32:
6319   case ARM::VST2LNqWB_register_Asm_16:
6320   case ARM::VST2LNqWB_register_Asm_32: {
6321     MCInst TmpInst;
6322     // Shuffle the operands around so the lane index operand is in the
6323     // right place.
6324     unsigned Spacing;
6325     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6326     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6327     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6328     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6329     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6330     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6331     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6332                                             Spacing));
6333     TmpInst.addOperand(Inst.getOperand(1)); // lane
6334     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6335     TmpInst.addOperand(Inst.getOperand(6));
6336     Inst = TmpInst;
6337     return true;
6338   }
6339 
6340   case ARM::VST3LNdWB_register_Asm_8:
6341   case ARM::VST3LNdWB_register_Asm_16:
6342   case ARM::VST3LNdWB_register_Asm_32:
6343   case ARM::VST3LNqWB_register_Asm_16:
6344   case ARM::VST3LNqWB_register_Asm_32: {
6345     MCInst TmpInst;
6346     // Shuffle the operands around so the lane index operand is in the
6347     // right place.
6348     unsigned Spacing;
6349     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6350     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6351     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6352     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6353     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6354     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6355     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6356                                             Spacing));
6357     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6358                                             Spacing * 2));
6359     TmpInst.addOperand(Inst.getOperand(1)); // lane
6360     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6361     TmpInst.addOperand(Inst.getOperand(6));
6362     Inst = TmpInst;
6363     return true;
6364   }
6365 
6366   case ARM::VST4LNdWB_register_Asm_8:
6367   case ARM::VST4LNdWB_register_Asm_16:
6368   case ARM::VST4LNdWB_register_Asm_32:
6369   case ARM::VST4LNqWB_register_Asm_16:
6370   case ARM::VST4LNqWB_register_Asm_32: {
6371     MCInst TmpInst;
6372     // Shuffle the operands around so the lane index operand is in the
6373     // right place.
6374     unsigned Spacing;
6375     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6376     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6377     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6378     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6379     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6380     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6381     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6382                                             Spacing));
6383     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6384                                             Spacing * 2));
6385     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6386                                             Spacing * 3));
6387     TmpInst.addOperand(Inst.getOperand(1)); // lane
6388     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6389     TmpInst.addOperand(Inst.getOperand(6));
6390     Inst = TmpInst;
6391     return true;
6392   }
6393 
6394   case ARM::VST1LNdWB_fixed_Asm_8:
6395   case ARM::VST1LNdWB_fixed_Asm_16:
6396   case ARM::VST1LNdWB_fixed_Asm_32: {
6397     MCInst TmpInst;
6398     // Shuffle the operands around so the lane index operand is in the
6399     // right place.
6400     unsigned Spacing;
6401     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6402     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6403     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6404     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6405     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6406     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6407     TmpInst.addOperand(Inst.getOperand(1)); // lane
6408     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6409     TmpInst.addOperand(Inst.getOperand(5));
6410     Inst = TmpInst;
6411     return true;
6412   }
6413 
6414   case ARM::VST2LNdWB_fixed_Asm_8:
6415   case ARM::VST2LNdWB_fixed_Asm_16:
6416   case ARM::VST2LNdWB_fixed_Asm_32:
6417   case ARM::VST2LNqWB_fixed_Asm_16:
6418   case ARM::VST2LNqWB_fixed_Asm_32: {
6419     MCInst TmpInst;
6420     // Shuffle the operands around so the lane index operand is in the
6421     // right place.
6422     unsigned Spacing;
6423     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6424     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6425     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6426     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6427     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6428     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6429     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6430                                             Spacing));
6431     TmpInst.addOperand(Inst.getOperand(1)); // lane
6432     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6433     TmpInst.addOperand(Inst.getOperand(5));
6434     Inst = TmpInst;
6435     return true;
6436   }
6437 
6438   case ARM::VST3LNdWB_fixed_Asm_8:
6439   case ARM::VST3LNdWB_fixed_Asm_16:
6440   case ARM::VST3LNdWB_fixed_Asm_32:
6441   case ARM::VST3LNqWB_fixed_Asm_16:
6442   case ARM::VST3LNqWB_fixed_Asm_32: {
6443     MCInst TmpInst;
6444     // Shuffle the operands around so the lane index operand is in the
6445     // right place.
6446     unsigned Spacing;
6447     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6448     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6449     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6450     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6451     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6452     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6453     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6454                                             Spacing));
6455     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6456                                             Spacing * 2));
6457     TmpInst.addOperand(Inst.getOperand(1)); // lane
6458     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6459     TmpInst.addOperand(Inst.getOperand(5));
6460     Inst = TmpInst;
6461     return true;
6462   }
6463 
6464   case ARM::VST4LNdWB_fixed_Asm_8:
6465   case ARM::VST4LNdWB_fixed_Asm_16:
6466   case ARM::VST4LNdWB_fixed_Asm_32:
6467   case ARM::VST4LNqWB_fixed_Asm_16:
6468   case ARM::VST4LNqWB_fixed_Asm_32: {
6469     MCInst TmpInst;
6470     // Shuffle the operands around so the lane index operand is in the
6471     // right place.
6472     unsigned Spacing;
6473     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6474     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6475     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6476     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6477     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6478     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6479     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6480                                             Spacing));
6481     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6482                                             Spacing * 2));
6483     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6484                                             Spacing * 3));
6485     TmpInst.addOperand(Inst.getOperand(1)); // lane
6486     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6487     TmpInst.addOperand(Inst.getOperand(5));
6488     Inst = TmpInst;
6489     return true;
6490   }
6491 
6492   case ARM::VST1LNdAsm_8:
6493   case ARM::VST1LNdAsm_16:
6494   case ARM::VST1LNdAsm_32: {
6495     MCInst TmpInst;
6496     // Shuffle the operands around so the lane index operand is in the
6497     // right place.
6498     unsigned Spacing;
6499     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6500     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6501     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6502     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6503     TmpInst.addOperand(Inst.getOperand(1)); // lane
6504     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6505     TmpInst.addOperand(Inst.getOperand(5));
6506     Inst = TmpInst;
6507     return true;
6508   }
6509 
6510   case ARM::VST2LNdAsm_8:
6511   case ARM::VST2LNdAsm_16:
6512   case ARM::VST2LNdAsm_32:
6513   case ARM::VST2LNqAsm_16:
6514   case ARM::VST2LNqAsm_32: {
6515     MCInst TmpInst;
6516     // Shuffle the operands around so the lane index operand is in the
6517     // right place.
6518     unsigned Spacing;
6519     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6520     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6521     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6522     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6523     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6524                                             Spacing));
6525     TmpInst.addOperand(Inst.getOperand(1)); // lane
6526     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6527     TmpInst.addOperand(Inst.getOperand(5));
6528     Inst = TmpInst;
6529     return true;
6530   }
6531 
6532   case ARM::VST3LNdAsm_8:
6533   case ARM::VST3LNdAsm_16:
6534   case ARM::VST3LNdAsm_32:
6535   case ARM::VST3LNqAsm_16:
6536   case ARM::VST3LNqAsm_32: {
6537     MCInst TmpInst;
6538     // Shuffle the operands around so the lane index operand is in the
6539     // right place.
6540     unsigned Spacing;
6541     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6542     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6543     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6544     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6545     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6546                                             Spacing));
6547     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6548                                             Spacing * 2));
6549     TmpInst.addOperand(Inst.getOperand(1)); // lane
6550     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6551     TmpInst.addOperand(Inst.getOperand(5));
6552     Inst = TmpInst;
6553     return true;
6554   }
6555 
6556   case ARM::VST4LNdAsm_8:
6557   case ARM::VST4LNdAsm_16:
6558   case ARM::VST4LNdAsm_32:
6559   case ARM::VST4LNqAsm_16:
6560   case ARM::VST4LNqAsm_32: {
6561     MCInst TmpInst;
6562     // Shuffle the operands around so the lane index operand is in the
6563     // right place.
6564     unsigned Spacing;
6565     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6566     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6567     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6568     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6569     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6570                                             Spacing));
6571     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572                                             Spacing * 2));
6573     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574                                             Spacing * 3));
6575     TmpInst.addOperand(Inst.getOperand(1)); // lane
6576     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6577     TmpInst.addOperand(Inst.getOperand(5));
6578     Inst = TmpInst;
6579     return true;
6580   }
6581 
6582   // Handle NEON VLD complex aliases.
6583   case ARM::VLD1LNdWB_register_Asm_8:
6584   case ARM::VLD1LNdWB_register_Asm_16:
6585   case ARM::VLD1LNdWB_register_Asm_32: {
6586     MCInst TmpInst;
6587     // Shuffle the operands around so the lane index operand is in the
6588     // right place.
6589     unsigned Spacing;
6590     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6591     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6592     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6593     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6594     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6595     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6596     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6597     TmpInst.addOperand(Inst.getOperand(1)); // lane
6598     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6599     TmpInst.addOperand(Inst.getOperand(6));
6600     Inst = TmpInst;
6601     return true;
6602   }
6603 
6604   case ARM::VLD2LNdWB_register_Asm_8:
6605   case ARM::VLD2LNdWB_register_Asm_16:
6606   case ARM::VLD2LNdWB_register_Asm_32:
6607   case ARM::VLD2LNqWB_register_Asm_16:
6608   case ARM::VLD2LNqWB_register_Asm_32: {
6609     MCInst TmpInst;
6610     // Shuffle the operands around so the lane index operand is in the
6611     // right place.
6612     unsigned Spacing;
6613     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6614     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6615     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6616                                             Spacing));
6617     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6618     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6619     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6620     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6621     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6622     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6623                                             Spacing));
6624     TmpInst.addOperand(Inst.getOperand(1)); // lane
6625     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6626     TmpInst.addOperand(Inst.getOperand(6));
6627     Inst = TmpInst;
6628     return true;
6629   }
6630 
6631   case ARM::VLD3LNdWB_register_Asm_8:
6632   case ARM::VLD3LNdWB_register_Asm_16:
6633   case ARM::VLD3LNdWB_register_Asm_32:
6634   case ARM::VLD3LNqWB_register_Asm_16:
6635   case ARM::VLD3LNqWB_register_Asm_32: {
6636     MCInst TmpInst;
6637     // Shuffle the operands around so the lane index operand is in the
6638     // right place.
6639     unsigned Spacing;
6640     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6641     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6642     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6643                                             Spacing));
6644     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6645                                             Spacing * 2));
6646     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6647     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6648     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6649     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6650     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6651     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6652                                             Spacing));
6653     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6654                                             Spacing * 2));
6655     TmpInst.addOperand(Inst.getOperand(1)); // lane
6656     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6657     TmpInst.addOperand(Inst.getOperand(6));
6658     Inst = TmpInst;
6659     return true;
6660   }
6661 
6662   case ARM::VLD4LNdWB_register_Asm_8:
6663   case ARM::VLD4LNdWB_register_Asm_16:
6664   case ARM::VLD4LNdWB_register_Asm_32:
6665   case ARM::VLD4LNqWB_register_Asm_16:
6666   case ARM::VLD4LNqWB_register_Asm_32: {
6667     MCInst TmpInst;
6668     // Shuffle the operands around so the lane index operand is in the
6669     // right place.
6670     unsigned Spacing;
6671     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6672     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6673     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6674                                             Spacing));
6675     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6676                                             Spacing * 2));
6677     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6678                                             Spacing * 3));
6679     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6680     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6681     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6682     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6683     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6684     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6685                                             Spacing));
6686     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6687                                             Spacing * 2));
6688     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6689                                             Spacing * 3));
6690     TmpInst.addOperand(Inst.getOperand(1)); // lane
6691     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6692     TmpInst.addOperand(Inst.getOperand(6));
6693     Inst = TmpInst;
6694     return true;
6695   }
6696 
6697   case ARM::VLD1LNdWB_fixed_Asm_8:
6698   case ARM::VLD1LNdWB_fixed_Asm_16:
6699   case ARM::VLD1LNdWB_fixed_Asm_32: {
6700     MCInst TmpInst;
6701     // Shuffle the operands around so the lane index operand is in the
6702     // right place.
6703     unsigned Spacing;
6704     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6705     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6706     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6707     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6708     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6709     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6710     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6711     TmpInst.addOperand(Inst.getOperand(1)); // lane
6712     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6713     TmpInst.addOperand(Inst.getOperand(5));
6714     Inst = TmpInst;
6715     return true;
6716   }
6717 
6718   case ARM::VLD2LNdWB_fixed_Asm_8:
6719   case ARM::VLD2LNdWB_fixed_Asm_16:
6720   case ARM::VLD2LNdWB_fixed_Asm_32:
6721   case ARM::VLD2LNqWB_fixed_Asm_16:
6722   case ARM::VLD2LNqWB_fixed_Asm_32: {
6723     MCInst TmpInst;
6724     // Shuffle the operands around so the lane index operand is in the
6725     // right place.
6726     unsigned Spacing;
6727     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6728     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6729     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6730                                             Spacing));
6731     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6732     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6733     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6734     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6735     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6736     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6737                                             Spacing));
6738     TmpInst.addOperand(Inst.getOperand(1)); // lane
6739     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6740     TmpInst.addOperand(Inst.getOperand(5));
6741     Inst = TmpInst;
6742     return true;
6743   }
6744 
6745   case ARM::VLD3LNdWB_fixed_Asm_8:
6746   case ARM::VLD3LNdWB_fixed_Asm_16:
6747   case ARM::VLD3LNdWB_fixed_Asm_32:
6748   case ARM::VLD3LNqWB_fixed_Asm_16:
6749   case ARM::VLD3LNqWB_fixed_Asm_32: {
6750     MCInst TmpInst;
6751     // Shuffle the operands around so the lane index operand is in the
6752     // right place.
6753     unsigned Spacing;
6754     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6755     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6756     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6757                                             Spacing));
6758     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6759                                             Spacing * 2));
6760     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6761     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6762     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6763     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6764     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6765     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6766                                             Spacing));
6767     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6768                                             Spacing * 2));
6769     TmpInst.addOperand(Inst.getOperand(1)); // lane
6770     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6771     TmpInst.addOperand(Inst.getOperand(5));
6772     Inst = TmpInst;
6773     return true;
6774   }
6775 
6776   case ARM::VLD4LNdWB_fixed_Asm_8:
6777   case ARM::VLD4LNdWB_fixed_Asm_16:
6778   case ARM::VLD4LNdWB_fixed_Asm_32:
6779   case ARM::VLD4LNqWB_fixed_Asm_16:
6780   case ARM::VLD4LNqWB_fixed_Asm_32: {
6781     MCInst TmpInst;
6782     // Shuffle the operands around so the lane index operand is in the
6783     // right place.
6784     unsigned Spacing;
6785     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6786     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6787     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6788                                             Spacing));
6789     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6790                                             Spacing * 2));
6791     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6792                                             Spacing * 3));
6793     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6794     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6795     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6796     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6797     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6798     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6799                                             Spacing));
6800     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6801                                             Spacing * 2));
6802     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6803                                             Spacing * 3));
6804     TmpInst.addOperand(Inst.getOperand(1)); // lane
6805     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6806     TmpInst.addOperand(Inst.getOperand(5));
6807     Inst = TmpInst;
6808     return true;
6809   }
6810 
6811   case ARM::VLD1LNdAsm_8:
6812   case ARM::VLD1LNdAsm_16:
6813   case ARM::VLD1LNdAsm_32: {
6814     MCInst TmpInst;
6815     // Shuffle the operands around so the lane index operand is in the
6816     // right place.
6817     unsigned Spacing;
6818     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6819     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6820     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6821     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6822     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6823     TmpInst.addOperand(Inst.getOperand(1)); // lane
6824     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6825     TmpInst.addOperand(Inst.getOperand(5));
6826     Inst = TmpInst;
6827     return true;
6828   }
6829 
6830   case ARM::VLD2LNdAsm_8:
6831   case ARM::VLD2LNdAsm_16:
6832   case ARM::VLD2LNdAsm_32:
6833   case ARM::VLD2LNqAsm_16:
6834   case ARM::VLD2LNqAsm_32: {
6835     MCInst TmpInst;
6836     // Shuffle the operands around so the lane index operand is in the
6837     // right place.
6838     unsigned Spacing;
6839     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6840     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6841     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6842                                             Spacing));
6843     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6844     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6845     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6846     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6847                                             Spacing));
6848     TmpInst.addOperand(Inst.getOperand(1)); // lane
6849     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6850     TmpInst.addOperand(Inst.getOperand(5));
6851     Inst = TmpInst;
6852     return true;
6853   }
6854 
6855   case ARM::VLD3LNdAsm_8:
6856   case ARM::VLD3LNdAsm_16:
6857   case ARM::VLD3LNdAsm_32:
6858   case ARM::VLD3LNqAsm_16:
6859   case ARM::VLD3LNqAsm_32: {
6860     MCInst TmpInst;
6861     // Shuffle the operands around so the lane index operand is in the
6862     // right place.
6863     unsigned Spacing;
6864     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6865     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6866     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6867                                             Spacing));
6868     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6869                                             Spacing * 2));
6870     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6871     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6872     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6873     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6874                                             Spacing));
6875     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6876                                             Spacing * 2));
6877     TmpInst.addOperand(Inst.getOperand(1)); // lane
6878     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6879     TmpInst.addOperand(Inst.getOperand(5));
6880     Inst = TmpInst;
6881     return true;
6882   }
6883 
6884   case ARM::VLD4LNdAsm_8:
6885   case ARM::VLD4LNdAsm_16:
6886   case ARM::VLD4LNdAsm_32:
6887   case ARM::VLD4LNqAsm_16:
6888   case ARM::VLD4LNqAsm_32: {
6889     MCInst TmpInst;
6890     // Shuffle the operands around so the lane index operand is in the
6891     // right place.
6892     unsigned Spacing;
6893     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6894     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6895     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6896                                             Spacing));
6897     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6898                                             Spacing * 2));
6899     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6900                                             Spacing * 3));
6901     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6902     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6903     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6904     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6905                                             Spacing));
6906     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6907                                             Spacing * 2));
6908     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6909                                             Spacing * 3));
6910     TmpInst.addOperand(Inst.getOperand(1)); // lane
6911     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6912     TmpInst.addOperand(Inst.getOperand(5));
6913     Inst = TmpInst;
6914     return true;
6915   }
6916 
6917   // VLD3DUP single 3-element structure to all lanes instructions.
6918   case ARM::VLD3DUPdAsm_8:
6919   case ARM::VLD3DUPdAsm_16:
6920   case ARM::VLD3DUPdAsm_32:
6921   case ARM::VLD3DUPqAsm_8:
6922   case ARM::VLD3DUPqAsm_16:
6923   case ARM::VLD3DUPqAsm_32: {
6924     MCInst TmpInst;
6925     unsigned Spacing;
6926     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6927     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6928     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6929                                             Spacing));
6930     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6931                                             Spacing * 2));
6932     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6933     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6934     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6935     TmpInst.addOperand(Inst.getOperand(4));
6936     Inst = TmpInst;
6937     return true;
6938   }
6939 
6940   case ARM::VLD3DUPdWB_fixed_Asm_8:
6941   case ARM::VLD3DUPdWB_fixed_Asm_16:
6942   case ARM::VLD3DUPdWB_fixed_Asm_32:
6943   case ARM::VLD3DUPqWB_fixed_Asm_8:
6944   case ARM::VLD3DUPqWB_fixed_Asm_16:
6945   case ARM::VLD3DUPqWB_fixed_Asm_32: {
6946     MCInst TmpInst;
6947     unsigned Spacing;
6948     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6949     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6950     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6951                                             Spacing));
6952     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6953                                             Spacing * 2));
6954     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6955     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6956     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6957     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6958     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6959     TmpInst.addOperand(Inst.getOperand(4));
6960     Inst = TmpInst;
6961     return true;
6962   }
6963 
6964   case ARM::VLD3DUPdWB_register_Asm_8:
6965   case ARM::VLD3DUPdWB_register_Asm_16:
6966   case ARM::VLD3DUPdWB_register_Asm_32:
6967   case ARM::VLD3DUPqWB_register_Asm_8:
6968   case ARM::VLD3DUPqWB_register_Asm_16:
6969   case ARM::VLD3DUPqWB_register_Asm_32: {
6970     MCInst TmpInst;
6971     unsigned Spacing;
6972     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6973     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6974     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6975                                             Spacing));
6976     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6977                                             Spacing * 2));
6978     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6979     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6980     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6981     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6982     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6983     TmpInst.addOperand(Inst.getOperand(5));
6984     Inst = TmpInst;
6985     return true;
6986   }
6987 
6988   // VLD3 multiple 3-element structure instructions.
6989   case ARM::VLD3dAsm_8:
6990   case ARM::VLD3dAsm_16:
6991   case ARM::VLD3dAsm_32:
6992   case ARM::VLD3qAsm_8:
6993   case ARM::VLD3qAsm_16:
6994   case ARM::VLD3qAsm_32: {
6995     MCInst TmpInst;
6996     unsigned Spacing;
6997     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6998     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6999     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7000                                             Spacing));
7001     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7002                                             Spacing * 2));
7003     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7004     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7005     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7006     TmpInst.addOperand(Inst.getOperand(4));
7007     Inst = TmpInst;
7008     return true;
7009   }
7010 
7011   case ARM::VLD3dWB_fixed_Asm_8:
7012   case ARM::VLD3dWB_fixed_Asm_16:
7013   case ARM::VLD3dWB_fixed_Asm_32:
7014   case ARM::VLD3qWB_fixed_Asm_8:
7015   case ARM::VLD3qWB_fixed_Asm_16:
7016   case ARM::VLD3qWB_fixed_Asm_32: {
7017     MCInst TmpInst;
7018     unsigned Spacing;
7019     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7020     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7021     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7022                                             Spacing));
7023     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7024                                             Spacing * 2));
7025     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7026     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7027     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7028     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7029     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7030     TmpInst.addOperand(Inst.getOperand(4));
7031     Inst = TmpInst;
7032     return true;
7033   }
7034 
7035   case ARM::VLD3dWB_register_Asm_8:
7036   case ARM::VLD3dWB_register_Asm_16:
7037   case ARM::VLD3dWB_register_Asm_32:
7038   case ARM::VLD3qWB_register_Asm_8:
7039   case ARM::VLD3qWB_register_Asm_16:
7040   case ARM::VLD3qWB_register_Asm_32: {
7041     MCInst TmpInst;
7042     unsigned Spacing;
7043     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7044     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7045     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7046                                             Spacing));
7047     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7048                                             Spacing * 2));
7049     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7050     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7051     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7052     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7053     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7054     TmpInst.addOperand(Inst.getOperand(5));
7055     Inst = TmpInst;
7056     return true;
7057   }
7058 
7059   // VLD4DUP single 3-element structure to all lanes instructions.
7060   case ARM::VLD4DUPdAsm_8:
7061   case ARM::VLD4DUPdAsm_16:
7062   case ARM::VLD4DUPdAsm_32:
7063   case ARM::VLD4DUPqAsm_8:
7064   case ARM::VLD4DUPqAsm_16:
7065   case ARM::VLD4DUPqAsm_32: {
7066     MCInst TmpInst;
7067     unsigned Spacing;
7068     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7069     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7070     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7071                                             Spacing));
7072     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7073                                             Spacing * 2));
7074     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7075                                             Spacing * 3));
7076     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7077     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7078     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7079     TmpInst.addOperand(Inst.getOperand(4));
7080     Inst = TmpInst;
7081     return true;
7082   }
7083 
7084   case ARM::VLD4DUPdWB_fixed_Asm_8:
7085   case ARM::VLD4DUPdWB_fixed_Asm_16:
7086   case ARM::VLD4DUPdWB_fixed_Asm_32:
7087   case ARM::VLD4DUPqWB_fixed_Asm_8:
7088   case ARM::VLD4DUPqWB_fixed_Asm_16:
7089   case ARM::VLD4DUPqWB_fixed_Asm_32: {
7090     MCInst TmpInst;
7091     unsigned Spacing;
7092     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7093     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7094     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7095                                             Spacing));
7096     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7097                                             Spacing * 2));
7098     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7099                                             Spacing * 3));
7100     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7101     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7102     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7103     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7104     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7105     TmpInst.addOperand(Inst.getOperand(4));
7106     Inst = TmpInst;
7107     return true;
7108   }
7109 
7110   case ARM::VLD4DUPdWB_register_Asm_8:
7111   case ARM::VLD4DUPdWB_register_Asm_16:
7112   case ARM::VLD4DUPdWB_register_Asm_32:
7113   case ARM::VLD4DUPqWB_register_Asm_8:
7114   case ARM::VLD4DUPqWB_register_Asm_16:
7115   case ARM::VLD4DUPqWB_register_Asm_32: {
7116     MCInst TmpInst;
7117     unsigned Spacing;
7118     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7119     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7120     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7121                                             Spacing));
7122     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7123                                             Spacing * 2));
7124     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7125                                             Spacing * 3));
7126     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7127     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7128     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7129     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7130     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7131     TmpInst.addOperand(Inst.getOperand(5));
7132     Inst = TmpInst;
7133     return true;
7134   }
7135 
7136   // VLD4 multiple 4-element structure instructions.
7137   case ARM::VLD4dAsm_8:
7138   case ARM::VLD4dAsm_16:
7139   case ARM::VLD4dAsm_32:
7140   case ARM::VLD4qAsm_8:
7141   case ARM::VLD4qAsm_16:
7142   case ARM::VLD4qAsm_32: {
7143     MCInst TmpInst;
7144     unsigned Spacing;
7145     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7146     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7147     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7148                                             Spacing));
7149     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7150                                             Spacing * 2));
7151     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7152                                             Spacing * 3));
7153     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7154     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7155     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7156     TmpInst.addOperand(Inst.getOperand(4));
7157     Inst = TmpInst;
7158     return true;
7159   }
7160 
7161   case ARM::VLD4dWB_fixed_Asm_8:
7162   case ARM::VLD4dWB_fixed_Asm_16:
7163   case ARM::VLD4dWB_fixed_Asm_32:
7164   case ARM::VLD4qWB_fixed_Asm_8:
7165   case ARM::VLD4qWB_fixed_Asm_16:
7166   case ARM::VLD4qWB_fixed_Asm_32: {
7167     MCInst TmpInst;
7168     unsigned Spacing;
7169     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7170     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7171     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7172                                             Spacing));
7173     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7174                                             Spacing * 2));
7175     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7176                                             Spacing * 3));
7177     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7178     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7179     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7180     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7181     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7182     TmpInst.addOperand(Inst.getOperand(4));
7183     Inst = TmpInst;
7184     return true;
7185   }
7186 
7187   case ARM::VLD4dWB_register_Asm_8:
7188   case ARM::VLD4dWB_register_Asm_16:
7189   case ARM::VLD4dWB_register_Asm_32:
7190   case ARM::VLD4qWB_register_Asm_8:
7191   case ARM::VLD4qWB_register_Asm_16:
7192   case ARM::VLD4qWB_register_Asm_32: {
7193     MCInst TmpInst;
7194     unsigned Spacing;
7195     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7196     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7197     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7198                                             Spacing));
7199     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7200                                             Spacing * 2));
7201     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7202                                             Spacing * 3));
7203     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7204     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7205     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7206     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7207     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7208     TmpInst.addOperand(Inst.getOperand(5));
7209     Inst = TmpInst;
7210     return true;
7211   }
7212 
7213   // VST3 multiple 3-element structure instructions.
7214   case ARM::VST3dAsm_8:
7215   case ARM::VST3dAsm_16:
7216   case ARM::VST3dAsm_32:
7217   case ARM::VST3qAsm_8:
7218   case ARM::VST3qAsm_16:
7219   case ARM::VST3qAsm_32: {
7220     MCInst TmpInst;
7221     unsigned Spacing;
7222     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7223     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7224     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7225     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7226     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7227                                             Spacing));
7228     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7229                                             Spacing * 2));
7230     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7231     TmpInst.addOperand(Inst.getOperand(4));
7232     Inst = TmpInst;
7233     return true;
7234   }
7235 
7236   case ARM::VST3dWB_fixed_Asm_8:
7237   case ARM::VST3dWB_fixed_Asm_16:
7238   case ARM::VST3dWB_fixed_Asm_32:
7239   case ARM::VST3qWB_fixed_Asm_8:
7240   case ARM::VST3qWB_fixed_Asm_16:
7241   case ARM::VST3qWB_fixed_Asm_32: {
7242     MCInst TmpInst;
7243     unsigned Spacing;
7244     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7245     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7246     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7247     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7248     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7249     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7250     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7251                                             Spacing));
7252     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7253                                             Spacing * 2));
7254     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7255     TmpInst.addOperand(Inst.getOperand(4));
7256     Inst = TmpInst;
7257     return true;
7258   }
7259 
7260   case ARM::VST3dWB_register_Asm_8:
7261   case ARM::VST3dWB_register_Asm_16:
7262   case ARM::VST3dWB_register_Asm_32:
7263   case ARM::VST3qWB_register_Asm_8:
7264   case ARM::VST3qWB_register_Asm_16:
7265   case ARM::VST3qWB_register_Asm_32: {
7266     MCInst TmpInst;
7267     unsigned Spacing;
7268     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7269     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7270     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7271     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7272     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7273     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7274     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7275                                             Spacing));
7276     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7277                                             Spacing * 2));
7278     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7279     TmpInst.addOperand(Inst.getOperand(5));
7280     Inst = TmpInst;
7281     return true;
7282   }
7283 
7284   // VST4 multiple 3-element structure instructions.
7285   case ARM::VST4dAsm_8:
7286   case ARM::VST4dAsm_16:
7287   case ARM::VST4dAsm_32:
7288   case ARM::VST4qAsm_8:
7289   case ARM::VST4qAsm_16:
7290   case ARM::VST4qAsm_32: {
7291     MCInst TmpInst;
7292     unsigned Spacing;
7293     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7294     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7295     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7296     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7297     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7298                                             Spacing));
7299     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7300                                             Spacing * 2));
7301     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7302                                             Spacing * 3));
7303     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7304     TmpInst.addOperand(Inst.getOperand(4));
7305     Inst = TmpInst;
7306     return true;
7307   }
7308 
7309   case ARM::VST4dWB_fixed_Asm_8:
7310   case ARM::VST4dWB_fixed_Asm_16:
7311   case ARM::VST4dWB_fixed_Asm_32:
7312   case ARM::VST4qWB_fixed_Asm_8:
7313   case ARM::VST4qWB_fixed_Asm_16:
7314   case ARM::VST4qWB_fixed_Asm_32: {
7315     MCInst TmpInst;
7316     unsigned Spacing;
7317     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7318     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7319     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7320     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7321     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7322     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7323     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7324                                             Spacing));
7325     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7326                                             Spacing * 2));
7327     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7328                                             Spacing * 3));
7329     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7330     TmpInst.addOperand(Inst.getOperand(4));
7331     Inst = TmpInst;
7332     return true;
7333   }
7334 
7335   case ARM::VST4dWB_register_Asm_8:
7336   case ARM::VST4dWB_register_Asm_16:
7337   case ARM::VST4dWB_register_Asm_32:
7338   case ARM::VST4qWB_register_Asm_8:
7339   case ARM::VST4qWB_register_Asm_16:
7340   case ARM::VST4qWB_register_Asm_32: {
7341     MCInst TmpInst;
7342     unsigned Spacing;
7343     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7344     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7345     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7346     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7347     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7348     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7349     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7350                                             Spacing));
7351     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7352                                             Spacing * 2));
7353     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7354                                             Spacing * 3));
7355     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7356     TmpInst.addOperand(Inst.getOperand(5));
7357     Inst = TmpInst;
7358     return true;
7359   }
7360 
7361   // Handle encoding choice for the shift-immediate instructions.
7362   case ARM::t2LSLri:
7363   case ARM::t2LSRri:
7364   case ARM::t2ASRri: {
7365     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7366         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7367         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7368         !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7369           static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7370       unsigned NewOpc;
7371       switch (Inst.getOpcode()) {
7372       default: llvm_unreachable("unexpected opcode");
7373       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7374       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7375       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7376       }
7377       // The Thumb1 operands aren't in the same order. Awesome, eh?
7378       MCInst TmpInst;
7379       TmpInst.setOpcode(NewOpc);
7380       TmpInst.addOperand(Inst.getOperand(0));
7381       TmpInst.addOperand(Inst.getOperand(5));
7382       TmpInst.addOperand(Inst.getOperand(1));
7383       TmpInst.addOperand(Inst.getOperand(2));
7384       TmpInst.addOperand(Inst.getOperand(3));
7385       TmpInst.addOperand(Inst.getOperand(4));
7386       Inst = TmpInst;
7387       return true;
7388     }
7389     return false;
7390   }
7391 
7392   // Handle the Thumb2 mode MOV complex aliases.
7393   case ARM::t2MOVsr:
7394   case ARM::t2MOVSsr: {
7395     // Which instruction to expand to depends on the CCOut operand and
7396     // whether we're in an IT block if the register operands are low
7397     // registers.
7398     bool isNarrow = false;
7399     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7400         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7401         isARMLowRegister(Inst.getOperand(2).getReg()) &&
7402         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7403         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7404       isNarrow = true;
7405     MCInst TmpInst;
7406     unsigned newOpc;
7407     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7408     default: llvm_unreachable("unexpected opcode!");
7409     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7410     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7411     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7412     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
7413     }
7414     TmpInst.setOpcode(newOpc);
7415     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7416     if (isNarrow)
7417       TmpInst.addOperand(MCOperand::CreateReg(
7418           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7419     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7420     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7421     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7422     TmpInst.addOperand(Inst.getOperand(5));
7423     if (!isNarrow)
7424       TmpInst.addOperand(MCOperand::CreateReg(
7425           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7426     Inst = TmpInst;
7427     return true;
7428   }
7429   case ARM::t2MOVsi:
7430   case ARM::t2MOVSsi: {
7431     // Which instruction to expand to depends on the CCOut operand and
7432     // whether we're in an IT block if the register operands are low
7433     // registers.
7434     bool isNarrow = false;
7435     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7436         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7437         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7438       isNarrow = true;
7439     MCInst TmpInst;
7440     unsigned newOpc;
7441     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7442     default: llvm_unreachable("unexpected opcode!");
7443     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7444     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7445     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7446     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7447     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7448     }
7449     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7450     if (Amount == 32) Amount = 0;
7451     TmpInst.setOpcode(newOpc);
7452     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7453     if (isNarrow)
7454       TmpInst.addOperand(MCOperand::CreateReg(
7455           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7456     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7457     if (newOpc != ARM::t2RRX)
7458       TmpInst.addOperand(MCOperand::CreateImm(Amount));
7459     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7460     TmpInst.addOperand(Inst.getOperand(4));
7461     if (!isNarrow)
7462       TmpInst.addOperand(MCOperand::CreateReg(
7463           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7464     Inst = TmpInst;
7465     return true;
7466   }
7467   // Handle the ARM mode MOV complex aliases.
7468   case ARM::ASRr:
7469   case ARM::LSRr:
7470   case ARM::LSLr:
7471   case ARM::RORr: {
7472     ARM_AM::ShiftOpc ShiftTy;
7473     switch(Inst.getOpcode()) {
7474     default: llvm_unreachable("unexpected opcode!");
7475     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7476     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7477     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7478     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7479     }
7480     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7481     MCInst TmpInst;
7482     TmpInst.setOpcode(ARM::MOVsr);
7483     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7484     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7485     TmpInst.addOperand(Inst.getOperand(2)); // Rm
7486     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7487     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7488     TmpInst.addOperand(Inst.getOperand(4));
7489     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7490     Inst = TmpInst;
7491     return true;
7492   }
7493   case ARM::ASRi:
7494   case ARM::LSRi:
7495   case ARM::LSLi:
7496   case ARM::RORi: {
7497     ARM_AM::ShiftOpc ShiftTy;
7498     switch(Inst.getOpcode()) {
7499     default: llvm_unreachable("unexpected opcode!");
7500     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7501     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7502     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7503     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7504     }
7505     // A shift by zero is a plain MOVr, not a MOVsi.
7506     unsigned Amt = Inst.getOperand(2).getImm();
7507     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7508     // A shift by 32 should be encoded as 0 when permitted
7509     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7510       Amt = 0;
7511     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7512     MCInst TmpInst;
7513     TmpInst.setOpcode(Opc);
7514     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7515     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7516     if (Opc == ARM::MOVsi)
7517       TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7518     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7519     TmpInst.addOperand(Inst.getOperand(4));
7520     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7521     Inst = TmpInst;
7522     return true;
7523   }
7524   case ARM::RRXi: {
7525     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7526     MCInst TmpInst;
7527     TmpInst.setOpcode(ARM::MOVsi);
7528     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7529     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7530     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7531     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7532     TmpInst.addOperand(Inst.getOperand(3));
7533     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7534     Inst = TmpInst;
7535     return true;
7536   }
7537   case ARM::t2LDMIA_UPD: {
7538     // If this is a load of a single register, then we should use
7539     // a post-indexed LDR instruction instead, per the ARM ARM.
7540     if (Inst.getNumOperands() != 5)
7541       return false;
7542     MCInst TmpInst;
7543     TmpInst.setOpcode(ARM::t2LDR_POST);
7544     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7545     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7546     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7547     TmpInst.addOperand(MCOperand::CreateImm(4));
7548     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7549     TmpInst.addOperand(Inst.getOperand(3));
7550     Inst = TmpInst;
7551     return true;
7552   }
7553   case ARM::t2STMDB_UPD: {
7554     // If this is a store of a single register, then we should use
7555     // a pre-indexed STR instruction instead, per the ARM ARM.
7556     if (Inst.getNumOperands() != 5)
7557       return false;
7558     MCInst TmpInst;
7559     TmpInst.setOpcode(ARM::t2STR_PRE);
7560     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7561     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7562     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7563     TmpInst.addOperand(MCOperand::CreateImm(-4));
7564     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7565     TmpInst.addOperand(Inst.getOperand(3));
7566     Inst = TmpInst;
7567     return true;
7568   }
7569   case ARM::LDMIA_UPD:
7570     // If this is a load of a single register via a 'pop', then we should use
7571     // a post-indexed LDR instruction instead, per the ARM ARM.
7572     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
7573         Inst.getNumOperands() == 5) {
7574       MCInst TmpInst;
7575       TmpInst.setOpcode(ARM::LDR_POST_IMM);
7576       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7577       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7578       TmpInst.addOperand(Inst.getOperand(1)); // Rn
7579       TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7580       TmpInst.addOperand(MCOperand::CreateImm(4));
7581       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7582       TmpInst.addOperand(Inst.getOperand(3));
7583       Inst = TmpInst;
7584       return true;
7585     }
7586     break;
7587   case ARM::STMDB_UPD:
7588     // If this is a store of a single register via a 'push', then we should use
7589     // a pre-indexed STR instruction instead, per the ARM ARM.
7590     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
7591         Inst.getNumOperands() == 5) {
7592       MCInst TmpInst;
7593       TmpInst.setOpcode(ARM::STR_PRE_IMM);
7594       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7595       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7596       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7597       TmpInst.addOperand(MCOperand::CreateImm(-4));
7598       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7599       TmpInst.addOperand(Inst.getOperand(3));
7600       Inst = TmpInst;
7601     }
7602     break;
7603   case ARM::t2ADDri12:
7604     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7605     // mnemonic was used (not "addw"), encoding T3 is preferred.
7606     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
7607         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7608       break;
7609     Inst.setOpcode(ARM::t2ADDri);
7610     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7611     break;
7612   case ARM::t2SUBri12:
7613     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7614     // mnemonic was used (not "subw"), encoding T3 is preferred.
7615     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
7616         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7617       break;
7618     Inst.setOpcode(ARM::t2SUBri);
7619     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7620     break;
7621   case ARM::tADDi8:
7622     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7623     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7624     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7625     // to encoding T1 if <Rd> is omitted."
7626     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7627       Inst.setOpcode(ARM::tADDi3);
7628       return true;
7629     }
7630     break;
7631   case ARM::tSUBi8:
7632     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7633     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7634     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7635     // to encoding T1 if <Rd> is omitted."
7636     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7637       Inst.setOpcode(ARM::tSUBi3);
7638       return true;
7639     }
7640     break;
7641   case ARM::t2ADDri:
7642   case ARM::t2SUBri: {
7643     // If the destination and first source operand are the same, and
7644     // the flags are compatible with the current IT status, use encoding T2
7645     // instead of T3. For compatibility with the system 'as'. Make sure the
7646     // wide encoding wasn't explicit.
7647     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7648         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7649         (unsigned)Inst.getOperand(2).getImm() > 255 ||
7650         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7651          (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7652         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7653          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7654       break;
7655     MCInst TmpInst;
7656     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7657                       ARM::tADDi8 : ARM::tSUBi8);
7658     TmpInst.addOperand(Inst.getOperand(0));
7659     TmpInst.addOperand(Inst.getOperand(5));
7660     TmpInst.addOperand(Inst.getOperand(0));
7661     TmpInst.addOperand(Inst.getOperand(2));
7662     TmpInst.addOperand(Inst.getOperand(3));
7663     TmpInst.addOperand(Inst.getOperand(4));
7664     Inst = TmpInst;
7665     return true;
7666   }
7667   case ARM::t2ADDrr: {
7668     // If the destination and first source operand are the same, and
7669     // there's no setting of the flags, use encoding T2 instead of T3.
7670     // Note that this is only for ADD, not SUB. This mirrors the system
7671     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7672     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7673         Inst.getOperand(5).getReg() != 0 ||
7674         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7675          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7676       break;
7677     MCInst TmpInst;
7678     TmpInst.setOpcode(ARM::tADDhirr);
7679     TmpInst.addOperand(Inst.getOperand(0));
7680     TmpInst.addOperand(Inst.getOperand(0));
7681     TmpInst.addOperand(Inst.getOperand(2));
7682     TmpInst.addOperand(Inst.getOperand(3));
7683     TmpInst.addOperand(Inst.getOperand(4));
7684     Inst = TmpInst;
7685     return true;
7686   }
7687   case ARM::tADDrSP: {
7688     // If the non-SP source operand and the destination operand are not the
7689     // same, we need to use the 32-bit encoding if it's available.
7690     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7691       Inst.setOpcode(ARM::t2ADDrr);
7692       Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7693       return true;
7694     }
7695     break;
7696   }
7697   case ARM::tB:
7698     // A Thumb conditional branch outside of an IT block is a tBcc.
7699     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7700       Inst.setOpcode(ARM::tBcc);
7701       return true;
7702     }
7703     break;
7704   case ARM::t2B:
7705     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7706     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7707       Inst.setOpcode(ARM::t2Bcc);
7708       return true;
7709     }
7710     break;
7711   case ARM::t2Bcc:
7712     // If the conditional is AL or we're in an IT block, we really want t2B.
7713     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7714       Inst.setOpcode(ARM::t2B);
7715       return true;
7716     }
7717     break;
7718   case ARM::tBcc:
7719     // If the conditional is AL, we really want tB.
7720     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7721       Inst.setOpcode(ARM::tB);
7722       return true;
7723     }
7724     break;
7725   case ARM::tLDMIA: {
7726     // If the register list contains any high registers, or if the writeback
7727     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7728     // instead if we're in Thumb2. Otherwise, this should have generated
7729     // an error in validateInstruction().
7730     unsigned Rn = Inst.getOperand(0).getReg();
7731     bool hasWritebackToken =
7732         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7733          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7734     bool listContainsBase;
7735     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7736         (!listContainsBase && !hasWritebackToken) ||
7737         (listContainsBase && hasWritebackToken)) {
7738       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7739       assert (isThumbTwo());
7740       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7741       // If we're switching to the updating version, we need to insert
7742       // the writeback tied operand.
7743       if (hasWritebackToken)
7744         Inst.insert(Inst.begin(),
7745                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7746       return true;
7747     }
7748     break;
7749   }
7750   case ARM::tSTMIA_UPD: {
7751     // If the register list contains any high registers, we need to use
7752     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7753     // should have generated an error in validateInstruction().
7754     unsigned Rn = Inst.getOperand(0).getReg();
7755     bool listContainsBase;
7756     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7757       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7758       assert (isThumbTwo());
7759       Inst.setOpcode(ARM::t2STMIA_UPD);
7760       return true;
7761     }
7762     break;
7763   }
7764   case ARM::tPOP: {
7765     bool listContainsBase;
7766     // If the register list contains any high registers, we need to use
7767     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7768     // should have generated an error in validateInstruction().
7769     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7770       return false;
7771     assert (isThumbTwo());
7772     Inst.setOpcode(ARM::t2LDMIA_UPD);
7773     // Add the base register and writeback operands.
7774     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7775     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7776     return true;
7777   }
7778   case ARM::tPUSH: {
7779     bool listContainsBase;
7780     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7781       return false;
7782     assert (isThumbTwo());
7783     Inst.setOpcode(ARM::t2STMDB_UPD);
7784     // Add the base register and writeback operands.
7785     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7786     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7787     return true;
7788   }
7789   case ARM::t2MOVi: {
7790     // If we can use the 16-bit encoding and the user didn't explicitly
7791     // request the 32-bit variant, transform it here.
7792     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7793         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7794         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7795           Inst.getOperand(4).getReg() == ARM::CPSR) ||
7796          (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7797         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7798          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7799       // The operands aren't in the same order for tMOVi8...
7800       MCInst TmpInst;
7801       TmpInst.setOpcode(ARM::tMOVi8);
7802       TmpInst.addOperand(Inst.getOperand(0));
7803       TmpInst.addOperand(Inst.getOperand(4));
7804       TmpInst.addOperand(Inst.getOperand(1));
7805       TmpInst.addOperand(Inst.getOperand(2));
7806       TmpInst.addOperand(Inst.getOperand(3));
7807       Inst = TmpInst;
7808       return true;
7809     }
7810     break;
7811   }
7812   case ARM::t2MOVr: {
7813     // If we can use the 16-bit encoding and the user didn't explicitly
7814     // request the 32-bit variant, transform it here.
7815     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7816         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7817         Inst.getOperand(2).getImm() == ARMCC::AL &&
7818         Inst.getOperand(4).getReg() == ARM::CPSR &&
7819         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7820          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7821       // The operands aren't the same for tMOV[S]r... (no cc_out)
7822       MCInst TmpInst;
7823       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7824       TmpInst.addOperand(Inst.getOperand(0));
7825       TmpInst.addOperand(Inst.getOperand(1));
7826       TmpInst.addOperand(Inst.getOperand(2));
7827       TmpInst.addOperand(Inst.getOperand(3));
7828       Inst = TmpInst;
7829       return true;
7830     }
7831     break;
7832   }
7833   case ARM::t2SXTH:
7834   case ARM::t2SXTB:
7835   case ARM::t2UXTH:
7836   case ARM::t2UXTB: {
7837     // If we can use the 16-bit encoding and the user didn't explicitly
7838     // request the 32-bit variant, transform it here.
7839     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7840         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7841         Inst.getOperand(2).getImm() == 0 &&
7842         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7843          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7844       unsigned NewOpc;
7845       switch (Inst.getOpcode()) {
7846       default: llvm_unreachable("Illegal opcode!");
7847       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7848       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7849       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7850       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7851       }
7852       // The operands aren't the same for thumb1 (no rotate operand).
7853       MCInst TmpInst;
7854       TmpInst.setOpcode(NewOpc);
7855       TmpInst.addOperand(Inst.getOperand(0));
7856       TmpInst.addOperand(Inst.getOperand(1));
7857       TmpInst.addOperand(Inst.getOperand(3));
7858       TmpInst.addOperand(Inst.getOperand(4));
7859       Inst = TmpInst;
7860       return true;
7861     }
7862     break;
7863   }
7864   case ARM::MOVsi: {
7865     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7866     // rrx shifts and asr/lsr of #32 is encoded as 0
7867     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7868       return false;
7869     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7870       // Shifting by zero is accepted as a vanilla 'MOVr'
7871       MCInst TmpInst;
7872       TmpInst.setOpcode(ARM::MOVr);
7873       TmpInst.addOperand(Inst.getOperand(0));
7874       TmpInst.addOperand(Inst.getOperand(1));
7875       TmpInst.addOperand(Inst.getOperand(3));
7876       TmpInst.addOperand(Inst.getOperand(4));
7877       TmpInst.addOperand(Inst.getOperand(5));
7878       Inst = TmpInst;
7879       return true;
7880     }
7881     return false;
7882   }
7883   case ARM::ANDrsi:
7884   case ARM::ORRrsi:
7885   case ARM::EORrsi:
7886   case ARM::BICrsi:
7887   case ARM::SUBrsi:
7888   case ARM::ADDrsi: {
7889     unsigned newOpc;
7890     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7891     if (SOpc == ARM_AM::rrx) return false;
7892     switch (Inst.getOpcode()) {
7893     default: llvm_unreachable("unexpected opcode!");
7894     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7895     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7896     case ARM::EORrsi: newOpc = ARM::EORrr; break;
7897     case ARM::BICrsi: newOpc = ARM::BICrr; break;
7898     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7899     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7900     }
7901     // If the shift is by zero, use the non-shifted instruction definition.
7902     // The exception is for right shifts, where 0 == 32
7903     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7904         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7905       MCInst TmpInst;
7906       TmpInst.setOpcode(newOpc);
7907       TmpInst.addOperand(Inst.getOperand(0));
7908       TmpInst.addOperand(Inst.getOperand(1));
7909       TmpInst.addOperand(Inst.getOperand(2));
7910       TmpInst.addOperand(Inst.getOperand(4));
7911       TmpInst.addOperand(Inst.getOperand(5));
7912       TmpInst.addOperand(Inst.getOperand(6));
7913       Inst = TmpInst;
7914       return true;
7915     }
7916     return false;
7917   }
7918   case ARM::ITasm:
7919   case ARM::t2IT: {
7920     // The mask bits for all but the first condition are represented as
7921     // the low bit of the condition code value implies 't'. We currently
7922     // always have 1 implies 't', so XOR toggle the bits if the low bit
7923     // of the condition code is zero.
7924     MCOperand &MO = Inst.getOperand(1);
7925     unsigned Mask = MO.getImm();
7926     unsigned OrigMask = Mask;
7927     unsigned TZ = countTrailingZeros(Mask);
7928     if ((Inst.getOperand(0).getImm() & 1) == 0) {
7929       assert(Mask && TZ <= 3 && "illegal IT mask value!");
7930       Mask ^= (0xE << TZ) & 0xF;
7931     }
7932     MO.setImm(Mask);
7933 
7934     // Set up the IT block state according to the IT instruction we just
7935     // matched.
7936     assert(!inITBlock() && "nested IT blocks?!");
7937     ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7938     ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7939     ITState.CurPosition = 0;
7940     ITState.FirstCond = true;
7941     break;
7942   }
7943   case ARM::t2LSLrr:
7944   case ARM::t2LSRrr:
7945   case ARM::t2ASRrr:
7946   case ARM::t2SBCrr:
7947   case ARM::t2RORrr:
7948   case ARM::t2BICrr:
7949   {
7950     // Assemblers should use the narrow encodings of these instructions when permissible.
7951     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7952          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7953         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7954         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7955          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7956         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
7957          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
7958              ".w"))) {
7959       unsigned NewOpc;
7960       switch (Inst.getOpcode()) {
7961         default: llvm_unreachable("unexpected opcode");
7962         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7963         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7964         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7965         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7966         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7967         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7968       }
7969       MCInst TmpInst;
7970       TmpInst.setOpcode(NewOpc);
7971       TmpInst.addOperand(Inst.getOperand(0));
7972       TmpInst.addOperand(Inst.getOperand(5));
7973       TmpInst.addOperand(Inst.getOperand(1));
7974       TmpInst.addOperand(Inst.getOperand(2));
7975       TmpInst.addOperand(Inst.getOperand(3));
7976       TmpInst.addOperand(Inst.getOperand(4));
7977       Inst = TmpInst;
7978       return true;
7979     }
7980     return false;
7981   }
7982   case ARM::t2ANDrr:
7983   case ARM::t2EORrr:
7984   case ARM::t2ADCrr:
7985   case ARM::t2ORRrr:
7986   {
7987     // Assemblers should use the narrow encodings of these instructions when permissible.
7988     // These instructions are special in that they are commutable, so shorter encodings
7989     // are available more often.
7990     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7991          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7992         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7993          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7994         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7995          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7996         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
7997          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
7998              ".w"))) {
7999       unsigned NewOpc;
8000       switch (Inst.getOpcode()) {
8001         default: llvm_unreachable("unexpected opcode");
8002         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8003         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8004         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8005         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8006       }
8007       MCInst TmpInst;
8008       TmpInst.setOpcode(NewOpc);
8009       TmpInst.addOperand(Inst.getOperand(0));
8010       TmpInst.addOperand(Inst.getOperand(5));
8011       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8012         TmpInst.addOperand(Inst.getOperand(1));
8013         TmpInst.addOperand(Inst.getOperand(2));
8014       } else {
8015         TmpInst.addOperand(Inst.getOperand(2));
8016         TmpInst.addOperand(Inst.getOperand(1));
8017       }
8018       TmpInst.addOperand(Inst.getOperand(3));
8019       TmpInst.addOperand(Inst.getOperand(4));
8020       Inst = TmpInst;
8021       return true;
8022     }
8023     return false;
8024   }
8025   }
8026   return false;
8027 }
8028 
8029 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8030   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8031   // suffix depending on whether they're in an IT block or not.
8032   unsigned Opc = Inst.getOpcode();
8033   const MCInstrDesc &MCID = MII.get(Opc);
8034   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8035     assert(MCID.hasOptionalDef() &&
8036            "optionally flag setting instruction missing optional def operand");
8037     assert(MCID.NumOperands == Inst.getNumOperands() &&
8038            "operand count mismatch!");
8039     // Find the optional-def operand (cc_out).
8040     unsigned OpNo;
8041     for (OpNo = 0;
8042          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8043          ++OpNo)
8044       ;
8045     // If we're parsing Thumb1, reject it completely.
8046     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8047       return Match_MnemonicFail;
8048     // If we're parsing Thumb2, which form is legal depends on whether we're
8049     // in an IT block.
8050     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8051         !inITBlock())
8052       return Match_RequiresITBlock;
8053     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8054         inITBlock())
8055       return Match_RequiresNotITBlock;
8056   }
8057   // Some high-register supporting Thumb1 encodings only allow both registers
8058   // to be from r0-r7 when in Thumb2.
8059   else if (Opc == ARM::tADDhirr && isThumbOne() &&
8060            isARMLowRegister(Inst.getOperand(1).getReg()) &&
8061            isARMLowRegister(Inst.getOperand(2).getReg()))
8062     return Match_RequiresThumb2;
8063   // Others only require ARMv6 or later.
8064   else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8065            isARMLowRegister(Inst.getOperand(0).getReg()) &&
8066            isARMLowRegister(Inst.getOperand(1).getReg()))
8067     return Match_RequiresV6;
8068   return Match_Success;
8069 }
8070 
8071 namespace llvm {
8072 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8073   return true; // In an assembly source, no need to second-guess
8074 }
8075 }
8076 
8077 static const char *getSubtargetFeatureName(unsigned Val);
8078 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8079                                            OperandVector &Operands,
8080                                            MCStreamer &Out, unsigned &ErrorInfo,
8081                                            bool MatchingInlineAsm) {
8082   MCInst Inst;
8083   unsigned MatchResult;
8084 
8085   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8086                                      MatchingInlineAsm);
8087   switch (MatchResult) {
8088   default: break;
8089   case Match_Success:
8090     // Context sensitive operand constraints aren't handled by the matcher,
8091     // so check them here.
8092     if (validateInstruction(Inst, Operands)) {
8093       // Still progress the IT block, otherwise one wrong condition causes
8094       // nasty cascading errors.
8095       forwardITPosition();
8096       return true;
8097     }
8098 
8099     { // processInstruction() updates inITBlock state, we need to save it away
8100       bool wasInITBlock = inITBlock();
8101 
8102       // Some instructions need post-processing to, for example, tweak which
8103       // encoding is selected. Loop on it while changes happen so the
8104       // individual transformations can chain off each other. E.g.,
8105       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8106       while (processInstruction(Inst, Operands))
8107         ;
8108 
8109       // Only after the instruction is fully processed, we can validate it
8110       if (wasInITBlock && hasV8Ops() && isThumb() &&
8111           !isV8EligibleForIT(&Inst)) {
8112         Warning(IDLoc, "deprecated instruction in IT block");
8113       }
8114     }
8115 
8116     // Only move forward at the very end so that everything in validate
8117     // and process gets a consistent answer about whether we're in an IT
8118     // block.
8119     forwardITPosition();
8120 
8121     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8122     // doesn't actually encode.
8123     if (Inst.getOpcode() == ARM::ITasm)
8124       return false;
8125 
8126     Inst.setLoc(IDLoc);
8127     Out.EmitInstruction(Inst, STI);
8128     return false;
8129   case Match_MissingFeature: {
8130     assert(ErrorInfo && "Unknown missing feature!");
8131     // Special case the error message for the very common case where only
8132     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8133     std::string Msg = "instruction requires:";
8134     unsigned Mask = 1;
8135     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8136       if (ErrorInfo & Mask) {
8137         Msg += " ";
8138         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8139       }
8140       Mask <<= 1;
8141     }
8142     return Error(IDLoc, Msg);
8143   }
8144   case Match_InvalidOperand: {
8145     SMLoc ErrorLoc = IDLoc;
8146     if (ErrorInfo != ~0U) {
8147       if (ErrorInfo >= Operands.size())
8148         return Error(IDLoc, "too few operands for instruction");
8149 
8150       ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8151       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8152     }
8153 
8154     return Error(ErrorLoc, "invalid operand for instruction");
8155   }
8156   case Match_MnemonicFail:
8157     return Error(IDLoc, "invalid instruction",
8158                  ((ARMOperand &)*Operands[0]).getLocRange());
8159   case Match_RequiresNotITBlock:
8160     return Error(IDLoc, "flag setting instruction only valid outside IT block");
8161   case Match_RequiresITBlock:
8162     return Error(IDLoc, "instruction only valid inside IT block");
8163   case Match_RequiresV6:
8164     return Error(IDLoc, "instruction variant requires ARMv6 or later");
8165   case Match_RequiresThumb2:
8166     return Error(IDLoc, "instruction variant requires Thumb2");
8167   case Match_ImmRange0_15: {
8168     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8169     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8170     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8171   }
8172   case Match_ImmRange0_239: {
8173     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8174     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8175     return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8176   }
8177   case Match_AlignedMemoryRequiresNone:
8178   case Match_DupAlignedMemoryRequiresNone:
8179   case Match_AlignedMemoryRequires16:
8180   case Match_DupAlignedMemoryRequires16:
8181   case Match_AlignedMemoryRequires32:
8182   case Match_DupAlignedMemoryRequires32:
8183   case Match_AlignedMemoryRequires64:
8184   case Match_DupAlignedMemoryRequires64:
8185   case Match_AlignedMemoryRequires64or128:
8186   case Match_DupAlignedMemoryRequires64or128:
8187   case Match_AlignedMemoryRequires64or128or256:
8188   {
8189     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8190     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8191     switch (MatchResult) {
8192       default:
8193         llvm_unreachable("Missing Match_Aligned type");
8194       case Match_AlignedMemoryRequiresNone:
8195       case Match_DupAlignedMemoryRequiresNone:
8196         return Error(ErrorLoc, "alignment must be omitted");
8197       case Match_AlignedMemoryRequires16:
8198       case Match_DupAlignedMemoryRequires16:
8199         return Error(ErrorLoc, "alignment must be 16 or omitted");
8200       case Match_AlignedMemoryRequires32:
8201       case Match_DupAlignedMemoryRequires32:
8202         return Error(ErrorLoc, "alignment must be 32 or omitted");
8203       case Match_AlignedMemoryRequires64:
8204       case Match_DupAlignedMemoryRequires64:
8205         return Error(ErrorLoc, "alignment must be 64 or omitted");
8206       case Match_AlignedMemoryRequires64or128:
8207       case Match_DupAlignedMemoryRequires64or128:
8208         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8209       case Match_AlignedMemoryRequires64or128or256:
8210         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8211     }
8212   }
8213   }
8214 
8215   llvm_unreachable("Implement any new match types added!");
8216 }
8217 
8218 /// parseDirective parses the arm specific directives
8219 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8220   const MCObjectFileInfo::Environment Format =
8221     getContext().getObjectFileInfo()->getObjectFileType();
8222   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8223 
8224   StringRef IDVal = DirectiveID.getIdentifier();
8225   if (IDVal == ".word")
8226     return parseLiteralValues(4, DirectiveID.getLoc());
8227   else if (IDVal == ".short" || IDVal == ".hword")
8228     return parseLiteralValues(2, DirectiveID.getLoc());
8229   else if (IDVal == ".thumb")
8230     return parseDirectiveThumb(DirectiveID.getLoc());
8231   else if (IDVal == ".arm")
8232     return parseDirectiveARM(DirectiveID.getLoc());
8233   else if (IDVal == ".thumb_func")
8234     return parseDirectiveThumbFunc(DirectiveID.getLoc());
8235   else if (IDVal == ".code")
8236     return parseDirectiveCode(DirectiveID.getLoc());
8237   else if (IDVal == ".syntax")
8238     return parseDirectiveSyntax(DirectiveID.getLoc());
8239   else if (IDVal == ".unreq")
8240     return parseDirectiveUnreq(DirectiveID.getLoc());
8241   else if (IDVal == ".fnend")
8242     return parseDirectiveFnEnd(DirectiveID.getLoc());
8243   else if (IDVal == ".cantunwind")
8244     return parseDirectiveCantUnwind(DirectiveID.getLoc());
8245   else if (IDVal == ".personality")
8246     return parseDirectivePersonality(DirectiveID.getLoc());
8247   else if (IDVal == ".handlerdata")
8248     return parseDirectiveHandlerData(DirectiveID.getLoc());
8249   else if (IDVal == ".setfp")
8250     return parseDirectiveSetFP(DirectiveID.getLoc());
8251   else if (IDVal == ".pad")
8252     return parseDirectivePad(DirectiveID.getLoc());
8253   else if (IDVal == ".save")
8254     return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8255   else if (IDVal == ".vsave")
8256     return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8257   else if (IDVal == ".ltorg" || IDVal == ".pool")
8258     return parseDirectiveLtorg(DirectiveID.getLoc());
8259   else if (IDVal == ".even")
8260     return parseDirectiveEven(DirectiveID.getLoc());
8261   else if (IDVal == ".personalityindex")
8262     return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8263   else if (IDVal == ".unwind_raw")
8264     return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8265   else if (IDVal == ".movsp")
8266     return parseDirectiveMovSP(DirectiveID.getLoc());
8267   else if (IDVal == ".arch_extension")
8268     return parseDirectiveArchExtension(DirectiveID.getLoc());
8269   else if (IDVal == ".align")
8270     return parseDirectiveAlign(DirectiveID.getLoc());
8271   else if (IDVal == ".thumb_set")
8272     return parseDirectiveThumbSet(DirectiveID.getLoc());
8273 
8274   if (!IsMachO) {
8275     if (IDVal == ".arch")
8276       return parseDirectiveArch(DirectiveID.getLoc());
8277     else if (IDVal == ".cpu")
8278       return parseDirectiveCPU(DirectiveID.getLoc());
8279     else if (IDVal == ".eabi_attribute")
8280       return parseDirectiveEabiAttr(DirectiveID.getLoc());
8281     else if (IDVal == ".fpu")
8282       return parseDirectiveFPU(DirectiveID.getLoc());
8283     else if (IDVal == ".fnstart")
8284       return parseDirectiveFnStart(DirectiveID.getLoc());
8285     else if (IDVal == ".inst")
8286       return parseDirectiveInst(DirectiveID.getLoc());
8287     else if (IDVal == ".inst.n")
8288       return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8289     else if (IDVal == ".inst.w")
8290       return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8291     else if (IDVal == ".object_arch")
8292       return parseDirectiveObjectArch(DirectiveID.getLoc());
8293     else if (IDVal == ".tlsdescseq")
8294       return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8295   }
8296 
8297   return true;
8298 }
8299 
8300 /// parseLiteralValues
8301 ///  ::= .hword expression [, expression]*
8302 ///  ::= .short expression [, expression]*
8303 ///  ::= .word expression [, expression]*
8304 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8305   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8306     for (;;) {
8307       const MCExpr *Value;
8308       if (getParser().parseExpression(Value)) {
8309         Parser.eatToEndOfStatement();
8310         return false;
8311       }
8312 
8313       getParser().getStreamer().EmitValue(Value, Size);
8314 
8315       if (getLexer().is(AsmToken::EndOfStatement))
8316         break;
8317 
8318       // FIXME: Improve diagnostic.
8319       if (getLexer().isNot(AsmToken::Comma)) {
8320         Error(L, "unexpected token in directive");
8321         return false;
8322       }
8323       Parser.Lex();
8324     }
8325   }
8326 
8327   Parser.Lex();
8328   return false;
8329 }
8330 
8331 /// parseDirectiveThumb
8332 ///  ::= .thumb
8333 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8334   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8335     Error(L, "unexpected token in directive");
8336     return false;
8337   }
8338   Parser.Lex();
8339 
8340   if (!hasThumb()) {
8341     Error(L, "target does not support Thumb mode");
8342     return false;
8343   }
8344 
8345   if (!isThumb())
8346     SwitchMode();
8347 
8348   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8349   return false;
8350 }
8351 
8352 /// parseDirectiveARM
8353 ///  ::= .arm
8354 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8355   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8356     Error(L, "unexpected token in directive");
8357     return false;
8358   }
8359   Parser.Lex();
8360 
8361   if (!hasARM()) {
8362     Error(L, "target does not support ARM mode");
8363     return false;
8364   }
8365 
8366   if (isThumb())
8367     SwitchMode();
8368 
8369   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8370   return false;
8371 }
8372 
8373 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8374   if (NextSymbolIsThumb) {
8375     getParser().getStreamer().EmitThumbFunc(Symbol);
8376     NextSymbolIsThumb = false;
8377   }
8378 }
8379 
8380 /// parseDirectiveThumbFunc
8381 ///  ::= .thumbfunc symbol_name
8382 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8383   const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8384   bool isMachO = MAI->hasSubsectionsViaSymbols();
8385 
8386   // Darwin asm has (optionally) function name after .thumb_func direction
8387   // ELF doesn't
8388   if (isMachO) {
8389     const AsmToken &Tok = Parser.getTok();
8390     if (Tok.isNot(AsmToken::EndOfStatement)) {
8391       if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8392         Error(L, "unexpected token in .thumb_func directive");
8393         return false;
8394       }
8395 
8396       MCSymbol *Func =
8397           getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8398       getParser().getStreamer().EmitThumbFunc(Func);
8399       Parser.Lex(); // Consume the identifier token.
8400       return false;
8401     }
8402   }
8403 
8404   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8405     Error(L, "unexpected token in directive");
8406     return false;
8407   }
8408 
8409   NextSymbolIsThumb = true;
8410   return false;
8411 }
8412 
8413 /// parseDirectiveSyntax
8414 ///  ::= .syntax unified | divided
8415 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8416   const AsmToken &Tok = Parser.getTok();
8417   if (Tok.isNot(AsmToken::Identifier)) {
8418     Error(L, "unexpected token in .syntax directive");
8419     return false;
8420   }
8421 
8422   StringRef Mode = Tok.getString();
8423   if (Mode == "unified" || Mode == "UNIFIED") {
8424     Parser.Lex();
8425   } else if (Mode == "divided" || Mode == "DIVIDED") {
8426     Error(L, "'.syntax divided' arm asssembly not supported");
8427     return false;
8428   } else {
8429     Error(L, "unrecognized syntax mode in .syntax directive");
8430     return false;
8431   }
8432 
8433   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8434     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8435     return false;
8436   }
8437   Parser.Lex();
8438 
8439   // TODO tell the MC streamer the mode
8440   // getParser().getStreamer().Emit???();
8441   return false;
8442 }
8443 
8444 /// parseDirectiveCode
8445 ///  ::= .code 16 | 32
8446 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8447   const AsmToken &Tok = Parser.getTok();
8448   if (Tok.isNot(AsmToken::Integer)) {
8449     Error(L, "unexpected token in .code directive");
8450     return false;
8451   }
8452   int64_t Val = Parser.getTok().getIntVal();
8453   if (Val != 16 && Val != 32) {
8454     Error(L, "invalid operand to .code directive");
8455     return false;
8456   }
8457   Parser.Lex();
8458 
8459   if (getLexer().isNot(AsmToken::EndOfStatement)) {
8460     Error(Parser.getTok().getLoc(), "unexpected token in directive");
8461     return false;
8462   }
8463   Parser.Lex();
8464 
8465   if (Val == 16) {
8466     if (!hasThumb()) {
8467       Error(L, "target does not support Thumb mode");
8468       return false;
8469     }
8470 
8471     if (!isThumb())
8472       SwitchMode();
8473     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8474   } else {
8475     if (!hasARM()) {
8476       Error(L, "target does not support ARM mode");
8477       return false;
8478     }
8479 
8480     if (isThumb())
8481       SwitchMode();
8482     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8483   }
8484 
8485   return false;
8486 }
8487 
8488 /// parseDirectiveReq
8489 ///  ::= name .req registername
8490 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8491   Parser.Lex(); // Eat the '.req' token.
8492   unsigned Reg;
8493   SMLoc SRegLoc, ERegLoc;
8494   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8495     Parser.eatToEndOfStatement();
8496     Error(SRegLoc, "register name expected");
8497     return false;
8498   }
8499 
8500   // Shouldn't be anything else.
8501   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8502     Parser.eatToEndOfStatement();
8503     Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8504     return false;
8505   }
8506 
8507   Parser.Lex(); // Consume the EndOfStatement
8508 
8509   if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8510     Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8511     return false;
8512   }
8513 
8514   return false;
8515 }
8516 
8517 /// parseDirectiveUneq
8518 ///  ::= .unreq registername
8519 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8520   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8521     Parser.eatToEndOfStatement();
8522     Error(L, "unexpected input in .unreq directive.");
8523     return false;
8524   }
8525   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8526   Parser.Lex(); // Eat the identifier.
8527   return false;
8528 }
8529 
8530 /// parseDirectiveArch
8531 ///  ::= .arch token
8532 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8533   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8534 
8535   unsigned ID = StringSwitch<unsigned>(Arch)
8536 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8537     .Case(NAME, ARM::ID)
8538 #define ARM_ARCH_ALIAS(NAME, ID) \
8539     .Case(NAME, ARM::ID)
8540 #include "MCTargetDesc/ARMArchName.def"
8541     .Default(ARM::INVALID_ARCH);
8542 
8543   if (ID == ARM::INVALID_ARCH) {
8544     Error(L, "Unknown arch name");
8545     return false;
8546   }
8547 
8548   getTargetStreamer().emitArch(ID);
8549   return false;
8550 }
8551 
8552 /// parseDirectiveEabiAttr
8553 ///  ::= .eabi_attribute int, int [, "str"]
8554 ///  ::= .eabi_attribute Tag_name, int [, "str"]
8555 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8556   int64_t Tag;
8557   SMLoc TagLoc;
8558   TagLoc = Parser.getTok().getLoc();
8559   if (Parser.getTok().is(AsmToken::Identifier)) {
8560     StringRef Name = Parser.getTok().getIdentifier();
8561     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8562     if (Tag == -1) {
8563       Error(TagLoc, "attribute name not recognised: " + Name);
8564       Parser.eatToEndOfStatement();
8565       return false;
8566     }
8567     Parser.Lex();
8568   } else {
8569     const MCExpr *AttrExpr;
8570 
8571     TagLoc = Parser.getTok().getLoc();
8572     if (Parser.parseExpression(AttrExpr)) {
8573       Parser.eatToEndOfStatement();
8574       return false;
8575     }
8576 
8577     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8578     if (!CE) {
8579       Error(TagLoc, "expected numeric constant");
8580       Parser.eatToEndOfStatement();
8581       return false;
8582     }
8583 
8584     Tag = CE->getValue();
8585   }
8586 
8587   if (Parser.getTok().isNot(AsmToken::Comma)) {
8588     Error(Parser.getTok().getLoc(), "comma expected");
8589     Parser.eatToEndOfStatement();
8590     return false;
8591   }
8592   Parser.Lex(); // skip comma
8593 
8594   StringRef StringValue = "";
8595   bool IsStringValue = false;
8596 
8597   int64_t IntegerValue = 0;
8598   bool IsIntegerValue = false;
8599 
8600   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8601     IsStringValue = true;
8602   else if (Tag == ARMBuildAttrs::compatibility) {
8603     IsStringValue = true;
8604     IsIntegerValue = true;
8605   } else if (Tag < 32 || Tag % 2 == 0)
8606     IsIntegerValue = true;
8607   else if (Tag % 2 == 1)
8608     IsStringValue = true;
8609   else
8610     llvm_unreachable("invalid tag type");
8611 
8612   if (IsIntegerValue) {
8613     const MCExpr *ValueExpr;
8614     SMLoc ValueExprLoc = Parser.getTok().getLoc();
8615     if (Parser.parseExpression(ValueExpr)) {
8616       Parser.eatToEndOfStatement();
8617       return false;
8618     }
8619 
8620     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8621     if (!CE) {
8622       Error(ValueExprLoc, "expected numeric constant");
8623       Parser.eatToEndOfStatement();
8624       return false;
8625     }
8626 
8627     IntegerValue = CE->getValue();
8628   }
8629 
8630   if (Tag == ARMBuildAttrs::compatibility) {
8631     if (Parser.getTok().isNot(AsmToken::Comma))
8632       IsStringValue = false;
8633     else
8634       Parser.Lex();
8635   }
8636 
8637   if (IsStringValue) {
8638     if (Parser.getTok().isNot(AsmToken::String)) {
8639       Error(Parser.getTok().getLoc(), "bad string constant");
8640       Parser.eatToEndOfStatement();
8641       return false;
8642     }
8643 
8644     StringValue = Parser.getTok().getStringContents();
8645     Parser.Lex();
8646   }
8647 
8648   if (IsIntegerValue && IsStringValue) {
8649     assert(Tag == ARMBuildAttrs::compatibility);
8650     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8651   } else if (IsIntegerValue)
8652     getTargetStreamer().emitAttribute(Tag, IntegerValue);
8653   else if (IsStringValue)
8654     getTargetStreamer().emitTextAttribute(Tag, StringValue);
8655   return false;
8656 }
8657 
8658 /// parseDirectiveCPU
8659 ///  ::= .cpu str
8660 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8661   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8662   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8663   return false;
8664 }
8665 
8666 /// parseDirectiveFPU
8667 ///  ::= .fpu str
8668 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8669   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8670 
8671   unsigned ID = StringSwitch<unsigned>(FPU)
8672 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8673 #include "ARMFPUName.def"
8674     .Default(ARM::INVALID_FPU);
8675 
8676   if (ID == ARM::INVALID_FPU) {
8677     Error(L, "Unknown FPU name");
8678     return false;
8679   }
8680 
8681   getTargetStreamer().emitFPU(ID);
8682   return false;
8683 }
8684 
8685 /// parseDirectiveFnStart
8686 ///  ::= .fnstart
8687 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8688   if (UC.hasFnStart()) {
8689     Error(L, ".fnstart starts before the end of previous one");
8690     UC.emitFnStartLocNotes();
8691     return false;
8692   }
8693 
8694   // Reset the unwind directives parser state
8695   UC.reset();
8696 
8697   getTargetStreamer().emitFnStart();
8698 
8699   UC.recordFnStart(L);
8700   return false;
8701 }
8702 
8703 /// parseDirectiveFnEnd
8704 ///  ::= .fnend
8705 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8706   // Check the ordering of unwind directives
8707   if (!UC.hasFnStart()) {
8708     Error(L, ".fnstart must precede .fnend directive");
8709     return false;
8710   }
8711 
8712   // Reset the unwind directives parser state
8713   getTargetStreamer().emitFnEnd();
8714 
8715   UC.reset();
8716   return false;
8717 }
8718 
8719 /// parseDirectiveCantUnwind
8720 ///  ::= .cantunwind
8721 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8722   UC.recordCantUnwind(L);
8723 
8724   // Check the ordering of unwind directives
8725   if (!UC.hasFnStart()) {
8726     Error(L, ".fnstart must precede .cantunwind directive");
8727     return false;
8728   }
8729   if (UC.hasHandlerData()) {
8730     Error(L, ".cantunwind can't be used with .handlerdata directive");
8731     UC.emitHandlerDataLocNotes();
8732     return false;
8733   }
8734   if (UC.hasPersonality()) {
8735     Error(L, ".cantunwind can't be used with .personality directive");
8736     UC.emitPersonalityLocNotes();
8737     return false;
8738   }
8739 
8740   getTargetStreamer().emitCantUnwind();
8741   return false;
8742 }
8743 
8744 /// parseDirectivePersonality
8745 ///  ::= .personality name
8746 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8747   bool HasExistingPersonality = UC.hasPersonality();
8748 
8749   UC.recordPersonality(L);
8750 
8751   // Check the ordering of unwind directives
8752   if (!UC.hasFnStart()) {
8753     Error(L, ".fnstart must precede .personality directive");
8754     return false;
8755   }
8756   if (UC.cantUnwind()) {
8757     Error(L, ".personality can't be used with .cantunwind directive");
8758     UC.emitCantUnwindLocNotes();
8759     return false;
8760   }
8761   if (UC.hasHandlerData()) {
8762     Error(L, ".personality must precede .handlerdata directive");
8763     UC.emitHandlerDataLocNotes();
8764     return false;
8765   }
8766   if (HasExistingPersonality) {
8767     Parser.eatToEndOfStatement();
8768     Error(L, "multiple personality directives");
8769     UC.emitPersonalityLocNotes();
8770     return false;
8771   }
8772 
8773   // Parse the name of the personality routine
8774   if (Parser.getTok().isNot(AsmToken::Identifier)) {
8775     Parser.eatToEndOfStatement();
8776     Error(L, "unexpected input in .personality directive.");
8777     return false;
8778   }
8779   StringRef Name(Parser.getTok().getIdentifier());
8780   Parser.Lex();
8781 
8782   MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8783   getTargetStreamer().emitPersonality(PR);
8784   return false;
8785 }
8786 
8787 /// parseDirectiveHandlerData
8788 ///  ::= .handlerdata
8789 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8790   UC.recordHandlerData(L);
8791 
8792   // Check the ordering of unwind directives
8793   if (!UC.hasFnStart()) {
8794     Error(L, ".fnstart must precede .personality directive");
8795     return false;
8796   }
8797   if (UC.cantUnwind()) {
8798     Error(L, ".handlerdata can't be used with .cantunwind directive");
8799     UC.emitCantUnwindLocNotes();
8800     return false;
8801   }
8802 
8803   getTargetStreamer().emitHandlerData();
8804   return false;
8805 }
8806 
8807 /// parseDirectiveSetFP
8808 ///  ::= .setfp fpreg, spreg [, offset]
8809 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8810   // Check the ordering of unwind directives
8811   if (!UC.hasFnStart()) {
8812     Error(L, ".fnstart must precede .setfp directive");
8813     return false;
8814   }
8815   if (UC.hasHandlerData()) {
8816     Error(L, ".setfp must precede .handlerdata directive");
8817     return false;
8818   }
8819 
8820   // Parse fpreg
8821   SMLoc FPRegLoc = Parser.getTok().getLoc();
8822   int FPReg = tryParseRegister();
8823   if (FPReg == -1) {
8824     Error(FPRegLoc, "frame pointer register expected");
8825     return false;
8826   }
8827 
8828   // Consume comma
8829   if (Parser.getTok().isNot(AsmToken::Comma)) {
8830     Error(Parser.getTok().getLoc(), "comma expected");
8831     return false;
8832   }
8833   Parser.Lex(); // skip comma
8834 
8835   // Parse spreg
8836   SMLoc SPRegLoc = Parser.getTok().getLoc();
8837   int SPReg = tryParseRegister();
8838   if (SPReg == -1) {
8839     Error(SPRegLoc, "stack pointer register expected");
8840     return false;
8841   }
8842 
8843   if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8844     Error(SPRegLoc, "register should be either $sp or the latest fp register");
8845     return false;
8846   }
8847 
8848   // Update the frame pointer register
8849   UC.saveFPReg(FPReg);
8850 
8851   // Parse offset
8852   int64_t Offset = 0;
8853   if (Parser.getTok().is(AsmToken::Comma)) {
8854     Parser.Lex(); // skip comma
8855 
8856     if (Parser.getTok().isNot(AsmToken::Hash) &&
8857         Parser.getTok().isNot(AsmToken::Dollar)) {
8858       Error(Parser.getTok().getLoc(), "'#' expected");
8859       return false;
8860     }
8861     Parser.Lex(); // skip hash token.
8862 
8863     const MCExpr *OffsetExpr;
8864     SMLoc ExLoc = Parser.getTok().getLoc();
8865     SMLoc EndLoc;
8866     if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8867       Error(ExLoc, "malformed setfp offset");
8868       return false;
8869     }
8870     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8871     if (!CE) {
8872       Error(ExLoc, "setfp offset must be an immediate");
8873       return false;
8874     }
8875 
8876     Offset = CE->getValue();
8877   }
8878 
8879   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8880                                 static_cast<unsigned>(SPReg), Offset);
8881   return false;
8882 }
8883 
8884 /// parseDirective
8885 ///  ::= .pad offset
8886 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8887   // Check the ordering of unwind directives
8888   if (!UC.hasFnStart()) {
8889     Error(L, ".fnstart must precede .pad directive");
8890     return false;
8891   }
8892   if (UC.hasHandlerData()) {
8893     Error(L, ".pad must precede .handlerdata directive");
8894     return false;
8895   }
8896 
8897   // Parse the offset
8898   if (Parser.getTok().isNot(AsmToken::Hash) &&
8899       Parser.getTok().isNot(AsmToken::Dollar)) {
8900     Error(Parser.getTok().getLoc(), "'#' expected");
8901     return false;
8902   }
8903   Parser.Lex(); // skip hash token.
8904 
8905   const MCExpr *OffsetExpr;
8906   SMLoc ExLoc = Parser.getTok().getLoc();
8907   SMLoc EndLoc;
8908   if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8909     Error(ExLoc, "malformed pad offset");
8910     return false;
8911   }
8912   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8913   if (!CE) {
8914     Error(ExLoc, "pad offset must be an immediate");
8915     return false;
8916   }
8917 
8918   getTargetStreamer().emitPad(CE->getValue());
8919   return false;
8920 }
8921 
8922 /// parseDirectiveRegSave
8923 ///  ::= .save  { registers }
8924 ///  ::= .vsave { registers }
8925 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8926   // Check the ordering of unwind directives
8927   if (!UC.hasFnStart()) {
8928     Error(L, ".fnstart must precede .save or .vsave directives");
8929     return false;
8930   }
8931   if (UC.hasHandlerData()) {
8932     Error(L, ".save or .vsave must precede .handlerdata directive");
8933     return false;
8934   }
8935 
8936   // RAII object to make sure parsed operands are deleted.
8937   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
8938 
8939   // Parse the register list
8940   if (parseRegisterList(Operands))
8941     return false;
8942   ARMOperand &Op = (ARMOperand &)*Operands[0];
8943   if (!IsVector && !Op.isRegList()) {
8944     Error(L, ".save expects GPR registers");
8945     return false;
8946   }
8947   if (IsVector && !Op.isDPRRegList()) {
8948     Error(L, ".vsave expects DPR registers");
8949     return false;
8950   }
8951 
8952   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
8953   return false;
8954 }
8955 
8956 /// parseDirectiveInst
8957 ///  ::= .inst opcode [, ...]
8958 ///  ::= .inst.n opcode [, ...]
8959 ///  ::= .inst.w opcode [, ...]
8960 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8961   int Width;
8962 
8963   if (isThumb()) {
8964     switch (Suffix) {
8965     case 'n':
8966       Width = 2;
8967       break;
8968     case 'w':
8969       Width = 4;
8970       break;
8971     default:
8972       Parser.eatToEndOfStatement();
8973       Error(Loc, "cannot determine Thumb instruction size, "
8974                  "use inst.n/inst.w instead");
8975       return false;
8976     }
8977   } else {
8978     if (Suffix) {
8979       Parser.eatToEndOfStatement();
8980       Error(Loc, "width suffixes are invalid in ARM mode");
8981       return false;
8982     }
8983     Width = 4;
8984   }
8985 
8986   if (getLexer().is(AsmToken::EndOfStatement)) {
8987     Parser.eatToEndOfStatement();
8988     Error(Loc, "expected expression following directive");
8989     return false;
8990   }
8991 
8992   for (;;) {
8993     const MCExpr *Expr;
8994 
8995     if (getParser().parseExpression(Expr)) {
8996       Error(Loc, "expected expression");
8997       return false;
8998     }
8999 
9000     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9001     if (!Value) {
9002       Error(Loc, "expected constant expression");
9003       return false;
9004     }
9005 
9006     switch (Width) {
9007     case 2:
9008       if (Value->getValue() > 0xffff) {
9009         Error(Loc, "inst.n operand is too big, use inst.w instead");
9010         return false;
9011       }
9012       break;
9013     case 4:
9014       if (Value->getValue() > 0xffffffff) {
9015         Error(Loc,
9016               StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9017         return false;
9018       }
9019       break;
9020     default:
9021       llvm_unreachable("only supported widths are 2 and 4");
9022     }
9023 
9024     getTargetStreamer().emitInst(Value->getValue(), Suffix);
9025 
9026     if (getLexer().is(AsmToken::EndOfStatement))
9027       break;
9028 
9029     if (getLexer().isNot(AsmToken::Comma)) {
9030       Error(Loc, "unexpected token in directive");
9031       return false;
9032     }
9033 
9034     Parser.Lex();
9035   }
9036 
9037   Parser.Lex();
9038   return false;
9039 }
9040 
9041 /// parseDirectiveLtorg
9042 ///  ::= .ltorg | .pool
9043 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9044   getTargetStreamer().emitCurrentConstantPool();
9045   return false;
9046 }
9047 
9048 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9049   const MCSection *Section = getStreamer().getCurrentSection().first;
9050 
9051   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9052     TokError("unexpected token in directive");
9053     return false;
9054   }
9055 
9056   if (!Section) {
9057     getStreamer().InitSections();
9058     Section = getStreamer().getCurrentSection().first;
9059   }
9060 
9061   assert(Section && "must have section to emit alignment");
9062   if (Section->UseCodeAlign())
9063     getStreamer().EmitCodeAlignment(2);
9064   else
9065     getStreamer().EmitValueToAlignment(2);
9066 
9067   return false;
9068 }
9069 
9070 /// parseDirectivePersonalityIndex
9071 ///   ::= .personalityindex index
9072 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9073   bool HasExistingPersonality = UC.hasPersonality();
9074 
9075   UC.recordPersonalityIndex(L);
9076 
9077   if (!UC.hasFnStart()) {
9078     Parser.eatToEndOfStatement();
9079     Error(L, ".fnstart must precede .personalityindex directive");
9080     return false;
9081   }
9082   if (UC.cantUnwind()) {
9083     Parser.eatToEndOfStatement();
9084     Error(L, ".personalityindex cannot be used with .cantunwind");
9085     UC.emitCantUnwindLocNotes();
9086     return false;
9087   }
9088   if (UC.hasHandlerData()) {
9089     Parser.eatToEndOfStatement();
9090     Error(L, ".personalityindex must precede .handlerdata directive");
9091     UC.emitHandlerDataLocNotes();
9092     return false;
9093   }
9094   if (HasExistingPersonality) {
9095     Parser.eatToEndOfStatement();
9096     Error(L, "multiple personality directives");
9097     UC.emitPersonalityLocNotes();
9098     return false;
9099   }
9100 
9101   const MCExpr *IndexExpression;
9102   SMLoc IndexLoc = Parser.getTok().getLoc();
9103   if (Parser.parseExpression(IndexExpression)) {
9104     Parser.eatToEndOfStatement();
9105     return false;
9106   }
9107 
9108   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9109   if (!CE) {
9110     Parser.eatToEndOfStatement();
9111     Error(IndexLoc, "index must be a constant number");
9112     return false;
9113   }
9114   if (CE->getValue() < 0 ||
9115       CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9116     Parser.eatToEndOfStatement();
9117     Error(IndexLoc, "personality routine index should be in range [0-3]");
9118     return false;
9119   }
9120 
9121   getTargetStreamer().emitPersonalityIndex(CE->getValue());
9122   return false;
9123 }
9124 
9125 /// parseDirectiveUnwindRaw
9126 ///   ::= .unwind_raw offset, opcode [, opcode...]
9127 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9128   if (!UC.hasFnStart()) {
9129     Parser.eatToEndOfStatement();
9130     Error(L, ".fnstart must precede .unwind_raw directives");
9131     return false;
9132   }
9133 
9134   int64_t StackOffset;
9135 
9136   const MCExpr *OffsetExpr;
9137   SMLoc OffsetLoc = getLexer().getLoc();
9138   if (getLexer().is(AsmToken::EndOfStatement) ||
9139       getParser().parseExpression(OffsetExpr)) {
9140     Error(OffsetLoc, "expected expression");
9141     Parser.eatToEndOfStatement();
9142     return false;
9143   }
9144 
9145   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9146   if (!CE) {
9147     Error(OffsetLoc, "offset must be a constant");
9148     Parser.eatToEndOfStatement();
9149     return false;
9150   }
9151 
9152   StackOffset = CE->getValue();
9153 
9154   if (getLexer().isNot(AsmToken::Comma)) {
9155     Error(getLexer().getLoc(), "expected comma");
9156     Parser.eatToEndOfStatement();
9157     return false;
9158   }
9159   Parser.Lex();
9160 
9161   SmallVector<uint8_t, 16> Opcodes;
9162   for (;;) {
9163     const MCExpr *OE;
9164 
9165     SMLoc OpcodeLoc = getLexer().getLoc();
9166     if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9167       Error(OpcodeLoc, "expected opcode expression");
9168       Parser.eatToEndOfStatement();
9169       return false;
9170     }
9171 
9172     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9173     if (!OC) {
9174       Error(OpcodeLoc, "opcode value must be a constant");
9175       Parser.eatToEndOfStatement();
9176       return false;
9177     }
9178 
9179     const int64_t Opcode = OC->getValue();
9180     if (Opcode & ~0xff) {
9181       Error(OpcodeLoc, "invalid opcode");
9182       Parser.eatToEndOfStatement();
9183       return false;
9184     }
9185 
9186     Opcodes.push_back(uint8_t(Opcode));
9187 
9188     if (getLexer().is(AsmToken::EndOfStatement))
9189       break;
9190 
9191     if (getLexer().isNot(AsmToken::Comma)) {
9192       Error(getLexer().getLoc(), "unexpected token in directive");
9193       Parser.eatToEndOfStatement();
9194       return false;
9195     }
9196 
9197     Parser.Lex();
9198   }
9199 
9200   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9201 
9202   Parser.Lex();
9203   return false;
9204 }
9205 
9206 /// parseDirectiveTLSDescSeq
9207 ///   ::= .tlsdescseq tls-variable
9208 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9209   if (getLexer().isNot(AsmToken::Identifier)) {
9210     TokError("expected variable after '.tlsdescseq' directive");
9211     Parser.eatToEndOfStatement();
9212     return false;
9213   }
9214 
9215   const MCSymbolRefExpr *SRE =
9216     MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9217                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9218   Lex();
9219 
9220   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9221     Error(Parser.getTok().getLoc(), "unexpected token");
9222     Parser.eatToEndOfStatement();
9223     return false;
9224   }
9225 
9226   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9227   return false;
9228 }
9229 
9230 /// parseDirectiveMovSP
9231 ///  ::= .movsp reg [, #offset]
9232 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9233   if (!UC.hasFnStart()) {
9234     Parser.eatToEndOfStatement();
9235     Error(L, ".fnstart must precede .movsp directives");
9236     return false;
9237   }
9238   if (UC.getFPReg() != ARM::SP) {
9239     Parser.eatToEndOfStatement();
9240     Error(L, "unexpected .movsp directive");
9241     return false;
9242   }
9243 
9244   SMLoc SPRegLoc = Parser.getTok().getLoc();
9245   int SPReg = tryParseRegister();
9246   if (SPReg == -1) {
9247     Parser.eatToEndOfStatement();
9248     Error(SPRegLoc, "register expected");
9249     return false;
9250   }
9251 
9252   if (SPReg == ARM::SP || SPReg == ARM::PC) {
9253     Parser.eatToEndOfStatement();
9254     Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9255     return false;
9256   }
9257 
9258   int64_t Offset = 0;
9259   if (Parser.getTok().is(AsmToken::Comma)) {
9260     Parser.Lex();
9261 
9262     if (Parser.getTok().isNot(AsmToken::Hash)) {
9263       Error(Parser.getTok().getLoc(), "expected #constant");
9264       Parser.eatToEndOfStatement();
9265       return false;
9266     }
9267     Parser.Lex();
9268 
9269     const MCExpr *OffsetExpr;
9270     SMLoc OffsetLoc = Parser.getTok().getLoc();
9271     if (Parser.parseExpression(OffsetExpr)) {
9272       Parser.eatToEndOfStatement();
9273       Error(OffsetLoc, "malformed offset expression");
9274       return false;
9275     }
9276 
9277     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9278     if (!CE) {
9279       Parser.eatToEndOfStatement();
9280       Error(OffsetLoc, "offset must be an immediate constant");
9281       return false;
9282     }
9283 
9284     Offset = CE->getValue();
9285   }
9286 
9287   getTargetStreamer().emitMovSP(SPReg, Offset);
9288   UC.saveFPReg(SPReg);
9289 
9290   return false;
9291 }
9292 
9293 /// parseDirectiveObjectArch
9294 ///   ::= .object_arch name
9295 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9296   if (getLexer().isNot(AsmToken::Identifier)) {
9297     Error(getLexer().getLoc(), "unexpected token");
9298     Parser.eatToEndOfStatement();
9299     return false;
9300   }
9301 
9302   StringRef Arch = Parser.getTok().getString();
9303   SMLoc ArchLoc = Parser.getTok().getLoc();
9304   getLexer().Lex();
9305 
9306   unsigned ID = StringSwitch<unsigned>(Arch)
9307 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9308     .Case(NAME, ARM::ID)
9309 #define ARM_ARCH_ALIAS(NAME, ID) \
9310     .Case(NAME, ARM::ID)
9311 #include "MCTargetDesc/ARMArchName.def"
9312 #undef ARM_ARCH_NAME
9313 #undef ARM_ARCH_ALIAS
9314     .Default(ARM::INVALID_ARCH);
9315 
9316   if (ID == ARM::INVALID_ARCH) {
9317     Error(ArchLoc, "unknown architecture '" + Arch + "'");
9318     Parser.eatToEndOfStatement();
9319     return false;
9320   }
9321 
9322   getTargetStreamer().emitObjectArch(ID);
9323 
9324   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9325     Error(getLexer().getLoc(), "unexpected token");
9326     Parser.eatToEndOfStatement();
9327   }
9328 
9329   return false;
9330 }
9331 
9332 /// parseDirectiveAlign
9333 ///   ::= .align
9334 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9335   // NOTE: if this is not the end of the statement, fall back to the target
9336   // agnostic handling for this directive which will correctly handle this.
9337   if (getLexer().isNot(AsmToken::EndOfStatement))
9338     return true;
9339 
9340   // '.align' is target specifically handled to mean 2**2 byte alignment.
9341   if (getStreamer().getCurrentSection().first->UseCodeAlign())
9342     getStreamer().EmitCodeAlignment(4, 0);
9343   else
9344     getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9345 
9346   return false;
9347 }
9348 
9349 /// parseDirectiveThumbSet
9350 ///  ::= .thumb_set name, value
9351 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9352   StringRef Name;
9353   if (Parser.parseIdentifier(Name)) {
9354     TokError("expected identifier after '.thumb_set'");
9355     Parser.eatToEndOfStatement();
9356     return false;
9357   }
9358 
9359   if (getLexer().isNot(AsmToken::Comma)) {
9360     TokError("expected comma after name '" + Name + "'");
9361     Parser.eatToEndOfStatement();
9362     return false;
9363   }
9364   Lex();
9365 
9366   const MCExpr *Value;
9367   if (Parser.parseExpression(Value)) {
9368     TokError("missing expression");
9369     Parser.eatToEndOfStatement();
9370     return false;
9371   }
9372 
9373   if (getLexer().isNot(AsmToken::EndOfStatement)) {
9374     TokError("unexpected token");
9375     Parser.eatToEndOfStatement();
9376     return false;
9377   }
9378   Lex();
9379 
9380   MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9381   getTargetStreamer().emitThumbSet(Alias, Value);
9382   return false;
9383 }
9384 
9385 /// Force static initialization.
9386 extern "C" void LLVMInitializeARMAsmParser() {
9387   RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9388   RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9389   RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9390   RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9391 }
9392 
9393 #define GET_REGISTER_MATCHER
9394 #define GET_SUBTARGET_FEATURE_NAME
9395 #define GET_MATCHER_IMPLEMENTATION
9396 #include "ARMGenAsmMatcher.inc"
9397 
9398 static const struct {
9399   const char *Name;
9400   const unsigned ArchCheck;
9401   const uint64_t Features;
9402 } Extensions[] = {
9403   { "crc", Feature_HasV8, ARM::FeatureCRC },
9404   { "crypto",  Feature_HasV8,
9405     ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9406   { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9407   { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9408     ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9409   // FIXME: iWMMXT not supported
9410   { "iwmmxt", Feature_None, 0 },
9411   // FIXME: iWMMXT2 not supported
9412   { "iwmmxt2", Feature_None, 0 },
9413   // FIXME: Maverick not supported
9414   { "maverick", Feature_None, 0 },
9415   { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9416   // FIXME: ARMv6-m OS Extensions feature not checked
9417   { "os", Feature_None, 0 },
9418   // FIXME: Also available in ARMv6-K
9419   { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9420   { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9421   // FIXME: Only available in A-class, isel not predicated
9422   { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9423   // FIXME: xscale not supported
9424   { "xscale", Feature_None, 0 },
9425 };
9426 
9427 /// parseDirectiveArchExtension
9428 ///   ::= .arch_extension [no]feature
9429 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9430   if (getLexer().isNot(AsmToken::Identifier)) {
9431     Error(getLexer().getLoc(), "unexpected token");
9432     Parser.eatToEndOfStatement();
9433     return false;
9434   }
9435 
9436   StringRef Name = Parser.getTok().getString();
9437   SMLoc ExtLoc = Parser.getTok().getLoc();
9438   getLexer().Lex();
9439 
9440   bool EnableFeature = true;
9441   if (Name.startswith_lower("no")) {
9442     EnableFeature = false;
9443     Name = Name.substr(2);
9444   }
9445 
9446   for (const auto &Extension : Extensions) {
9447     if (Extension.Name != Name)
9448       continue;
9449 
9450     if (!Extension.Features)
9451       report_fatal_error("unsupported architectural extension: " + Name);
9452 
9453     if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
9454       Error(ExtLoc, "architectural extension '" + Name + "' is not "
9455             "allowed for the current base architecture");
9456       return false;
9457     }
9458 
9459     bool ToggleFeatures = EnableFeature
9460                               ? (~STI.getFeatureBits() & Extension.Features)
9461                               : ( STI.getFeatureBits() & Extension.Features);
9462     if (ToggleFeatures) {
9463       unsigned Features =
9464           ComputeAvailableFeatures(STI.ToggleFeature(Extension.Features));
9465       setAvailableFeatures(Features);
9466     }
9467     return false;
9468   }
9469 
9470   Error(ExtLoc, "unknown architectural extension: " + Name);
9471   Parser.eatToEndOfStatement();
9472   return false;
9473 }
9474 
9475 // Define this matcher function after the auto-generated include so we
9476 // have the match class enum definitions.
9477 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
9478                                                   unsigned Kind) {
9479   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
9480   // If the kind is a token for a literal immediate, check if our asm
9481   // operand matches. This is for InstAliases which have a fixed-value
9482   // immediate in the syntax.
9483   switch (Kind) {
9484   default: break;
9485   case MCK__35_0:
9486     if (Op.isImm())
9487       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
9488         if (CE->getValue() == 0)
9489           return Match_Success;
9490     break;
9491   case MCK_ARMSOImm:
9492     if (Op.isImm()) {
9493       const MCExpr *SOExpr = Op.getImm();
9494       int64_t Value;
9495       if (!SOExpr->EvaluateAsAbsolute(Value))
9496         return Match_Success;
9497       assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
9498              "expression value must be representable in 32 bits");
9499     }
9500     break;
9501   case MCK_GPRPair:
9502     if (Op.isReg() &&
9503         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
9504       return Match_Success;
9505     break;
9506   }
9507   return Match_InvalidOperand;
9508 }
9509