1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/MC/MCTargetAsmParser.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/OwningPtr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCParser/MCAsmLexer.h"
28 #include "llvm/MC/MCParser/MCAsmParser.h"
29 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/SourceMgr.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
38 
39 using namespace llvm;
40 
41 namespace {
42 
43 class ARMOperand;
44 
45 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
46 
47 class ARMAsmParser : public MCTargetAsmParser {
48   MCSubtargetInfo &STI;
49   MCAsmParser &Parser;
50   const MCRegisterInfo *MRI;
51 
52   // Unwind directives state
53   SMLoc FnStartLoc;
54   SMLoc CantUnwindLoc;
55   SMLoc PersonalityLoc;
56   SMLoc HandlerDataLoc;
57   int FPReg;
58   void resetUnwindDirectiveParserState() {
59     FnStartLoc = SMLoc();
60     CantUnwindLoc = SMLoc();
61     PersonalityLoc = SMLoc();
62     HandlerDataLoc = SMLoc();
63     FPReg = -1;
64   }
65 
66   // Map of register aliases registers via the .req directive.
67   StringMap<unsigned> RegisterReqs;
68 
69   struct {
70     ARMCC::CondCodes Cond;    // Condition for IT block.
71     unsigned Mask:4;          // Condition mask for instructions.
72                               // Starting at first 1 (from lsb).
73                               //   '1'  condition as indicated in IT.
74                               //   '0'  inverse of condition (else).
75                               // Count of instructions in IT block is
76                               // 4 - trailingzeroes(mask)
77 
78     bool FirstCond;           // Explicit flag for when we're parsing the
79                               // First instruction in the IT block. It's
80                               // implied in the mask, so needs special
81                               // handling.
82 
83     unsigned CurPosition;     // Current position in parsing of IT
84                               // block. In range [0,3]. Initialized
85                               // according to count of instructions in block.
86                               // ~0U if no active IT block.
87   } ITState;
88   bool inITBlock() { return ITState.CurPosition != ~0U;}
89   void forwardITPosition() {
90     if (!inITBlock()) return;
91     // Move to the next instruction in the IT block, if there is one. If not,
92     // mark the block as done.
93     unsigned TZ = countTrailingZeros(ITState.Mask);
94     if (++ITState.CurPosition == 5 - TZ)
95       ITState.CurPosition = ~0U; // Done with the IT block after this.
96   }
97 
98 
99   MCAsmParser &getParser() const { return Parser; }
100   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101 
102   bool Warning(SMLoc L, const Twine &Msg,
103                ArrayRef<SMRange> Ranges = None) {
104     return Parser.Warning(L, Msg, Ranges);
105   }
106   bool Error(SMLoc L, const Twine &Msg,
107              ArrayRef<SMRange> Ranges = None) {
108     return Parser.Error(L, Msg, Ranges);
109   }
110 
111   int tryParseRegister();
112   bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
113   int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
114   bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
115   bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
116   bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
117   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
118   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
119                               unsigned &ShiftAmount);
120   bool parseDirectiveWord(unsigned Size, SMLoc L);
121   bool parseDirectiveThumb(SMLoc L);
122   bool parseDirectiveARM(SMLoc L);
123   bool parseDirectiveThumbFunc(SMLoc L);
124   bool parseDirectiveCode(SMLoc L);
125   bool parseDirectiveSyntax(SMLoc L);
126   bool parseDirectiveReq(StringRef Name, SMLoc L);
127   bool parseDirectiveUnreq(SMLoc L);
128   bool parseDirectiveArch(SMLoc L);
129   bool parseDirectiveEabiAttr(SMLoc L);
130   bool parseDirectiveFnStart(SMLoc L);
131   bool parseDirectiveFnEnd(SMLoc L);
132   bool parseDirectiveCantUnwind(SMLoc L);
133   bool parseDirectivePersonality(SMLoc L);
134   bool parseDirectiveHandlerData(SMLoc L);
135   bool parseDirectiveSetFP(SMLoc L);
136   bool parseDirectivePad(SMLoc L);
137   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
138 
139   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
140                           bool &CarrySetting, unsigned &ProcessorIMod,
141                           StringRef &ITMask);
142   void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
143                              bool &CanAcceptPredicationCode);
144 
145   bool isThumb() const {
146     // FIXME: Can tablegen auto-generate this?
147     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
148   }
149   bool isThumbOne() const {
150     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
151   }
152   bool isThumbTwo() const {
153     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
154   }
155   bool hasThumb() const {
156     return STI.getFeatureBits() & ARM::HasV4TOps;
157   }
158   bool hasV6Ops() const {
159     return STI.getFeatureBits() & ARM::HasV6Ops;
160   }
161   bool hasV7Ops() const {
162     return STI.getFeatureBits() & ARM::HasV7Ops;
163   }
164   bool hasV8Ops() const {
165     return STI.getFeatureBits() & ARM::HasV8Ops;
166   }
167   bool hasARM() const {
168     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
169   }
170 
171   void SwitchMode() {
172     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
173     setAvailableFeatures(FB);
174   }
175   bool isMClass() const {
176     return STI.getFeatureBits() & ARM::FeatureMClass;
177   }
178 
179   /// @name Auto-generated Match Functions
180   /// {
181 
182 #define GET_ASSEMBLER_HEADER
183 #include "ARMGenAsmMatcher.inc"
184 
185   /// }
186 
187   OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
188   OperandMatchResultTy parseCoprocNumOperand(
189     SmallVectorImpl<MCParsedAsmOperand*>&);
190   OperandMatchResultTy parseCoprocRegOperand(
191     SmallVectorImpl<MCParsedAsmOperand*>&);
192   OperandMatchResultTy parseCoprocOptionOperand(
193     SmallVectorImpl<MCParsedAsmOperand*>&);
194   OperandMatchResultTy parseMemBarrierOptOperand(
195     SmallVectorImpl<MCParsedAsmOperand*>&);
196   OperandMatchResultTy parseInstSyncBarrierOptOperand(
197     SmallVectorImpl<MCParsedAsmOperand*>&);
198   OperandMatchResultTy parseProcIFlagsOperand(
199     SmallVectorImpl<MCParsedAsmOperand*>&);
200   OperandMatchResultTy parseMSRMaskOperand(
201     SmallVectorImpl<MCParsedAsmOperand*>&);
202   OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
203                                    StringRef Op, int Low, int High);
204   OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
205     return parsePKHImm(O, "lsl", 0, 31);
206   }
207   OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
208     return parsePKHImm(O, "asr", 1, 32);
209   }
210   OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
211   OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
212   OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
213   OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
214   OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
215   OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
216   OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
217   OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
218   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
219                                        SMLoc &EndLoc);
220 
221   // Asm Match Converter Methods
222   void cvtThumbMultiply(MCInst &Inst,
223                         const SmallVectorImpl<MCParsedAsmOperand*> &);
224   void cvtThumbBranches(MCInst &Inst,
225                         const SmallVectorImpl<MCParsedAsmOperand*> &);
226 
227   bool validateInstruction(MCInst &Inst,
228                            const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
229   bool processInstruction(MCInst &Inst,
230                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
231   bool shouldOmitCCOutOperand(StringRef Mnemonic,
232                               SmallVectorImpl<MCParsedAsmOperand*> &Operands);
233   bool shouldOmitPredicateOperand(StringRef Mnemonic,
234                               SmallVectorImpl<MCParsedAsmOperand*> &Operands);
235   bool isDeprecated(MCInst &Inst, StringRef &Info);
236 
237 public:
238   enum ARMMatchResultTy {
239     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
240     Match_RequiresNotITBlock,
241     Match_RequiresV6,
242     Match_RequiresThumb2,
243 #define GET_OPERAND_DIAGNOSTIC_TYPES
244 #include "ARMGenAsmMatcher.inc"
245 
246   };
247 
248   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
249     : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) {
250     MCAsmParserExtension::Initialize(_Parser);
251 
252     // Cache the MCRegisterInfo.
253     MRI = getContext().getRegisterInfo();
254 
255     // Initialize the set of available features.
256     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
257 
258     // Not in an ITBlock to start with.
259     ITState.CurPosition = ~0U;
260 
261     // Set ELF header flags.
262     // FIXME: This should eventually end up somewhere else where more
263     // intelligent flag decisions can be made. For now we are just maintaining
264     // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
265     if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
266       MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
267   }
268 
269   // Implementation of the MCTargetAsmParser interface:
270   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
271   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
272                         SMLoc NameLoc,
273                         SmallVectorImpl<MCParsedAsmOperand*> &Operands);
274   bool ParseDirective(AsmToken DirectiveID);
275 
276   unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
277   unsigned checkTargetMatchPredicate(MCInst &Inst);
278 
279   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
280                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
281                                MCStreamer &Out, unsigned &ErrorInfo,
282                                bool MatchingInlineAsm);
283 };
284 } // end anonymous namespace
285 
286 namespace {
287 
288 /// ARMOperand - Instances of this class represent a parsed ARM machine
289 /// operand.
290 class ARMOperand : public MCParsedAsmOperand {
291   enum KindTy {
292     k_CondCode,
293     k_CCOut,
294     k_ITCondMask,
295     k_CoprocNum,
296     k_CoprocReg,
297     k_CoprocOption,
298     k_Immediate,
299     k_MemBarrierOpt,
300     k_InstSyncBarrierOpt,
301     k_Memory,
302     k_PostIndexRegister,
303     k_MSRMask,
304     k_ProcIFlags,
305     k_VectorIndex,
306     k_Register,
307     k_RegisterList,
308     k_DPRRegisterList,
309     k_SPRRegisterList,
310     k_VectorList,
311     k_VectorListAllLanes,
312     k_VectorListIndexed,
313     k_ShiftedRegister,
314     k_ShiftedImmediate,
315     k_ShifterImmediate,
316     k_RotateImmediate,
317     k_BitfieldDescriptor,
318     k_Token
319   } Kind;
320 
321   SMLoc StartLoc, EndLoc;
322   SmallVector<unsigned, 8> Registers;
323 
324   struct CCOp {
325     ARMCC::CondCodes Val;
326   };
327 
328   struct CopOp {
329     unsigned Val;
330   };
331 
332   struct CoprocOptionOp {
333     unsigned Val;
334   };
335 
336   struct ITMaskOp {
337     unsigned Mask:4;
338   };
339 
340   struct MBOptOp {
341     ARM_MB::MemBOpt Val;
342   };
343 
344   struct ISBOptOp {
345     ARM_ISB::InstSyncBOpt Val;
346   };
347 
348   struct IFlagsOp {
349     ARM_PROC::IFlags Val;
350   };
351 
352   struct MMaskOp {
353     unsigned Val;
354   };
355 
356   struct TokOp {
357     const char *Data;
358     unsigned Length;
359   };
360 
361   struct RegOp {
362     unsigned RegNum;
363   };
364 
365   // A vector register list is a sequential list of 1 to 4 registers.
366   struct VectorListOp {
367     unsigned RegNum;
368     unsigned Count;
369     unsigned LaneIndex;
370     bool isDoubleSpaced;
371   };
372 
373   struct VectorIndexOp {
374     unsigned Val;
375   };
376 
377   struct ImmOp {
378     const MCExpr *Val;
379   };
380 
381   /// Combined record for all forms of ARM address expressions.
382   struct MemoryOp {
383     unsigned BaseRegNum;
384     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
385     // was specified.
386     const MCConstantExpr *OffsetImm;  // Offset immediate value
387     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
388     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
389     unsigned ShiftImm;        // shift for OffsetReg.
390     unsigned Alignment;       // 0 = no alignment specified
391     // n = alignment in bytes (2, 4, 8, 16, or 32)
392     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
393   };
394 
395   struct PostIdxRegOp {
396     unsigned RegNum;
397     bool isAdd;
398     ARM_AM::ShiftOpc ShiftTy;
399     unsigned ShiftImm;
400   };
401 
402   struct ShifterImmOp {
403     bool isASR;
404     unsigned Imm;
405   };
406 
407   struct RegShiftedRegOp {
408     ARM_AM::ShiftOpc ShiftTy;
409     unsigned SrcReg;
410     unsigned ShiftReg;
411     unsigned ShiftImm;
412   };
413 
414   struct RegShiftedImmOp {
415     ARM_AM::ShiftOpc ShiftTy;
416     unsigned SrcReg;
417     unsigned ShiftImm;
418   };
419 
420   struct RotImmOp {
421     unsigned Imm;
422   };
423 
424   struct BitfieldOp {
425     unsigned LSB;
426     unsigned Width;
427   };
428 
429   union {
430     struct CCOp CC;
431     struct CopOp Cop;
432     struct CoprocOptionOp CoprocOption;
433     struct MBOptOp MBOpt;
434     struct ISBOptOp ISBOpt;
435     struct ITMaskOp ITMask;
436     struct IFlagsOp IFlags;
437     struct MMaskOp MMask;
438     struct TokOp Tok;
439     struct RegOp Reg;
440     struct VectorListOp VectorList;
441     struct VectorIndexOp VectorIndex;
442     struct ImmOp Imm;
443     struct MemoryOp Memory;
444     struct PostIdxRegOp PostIdxReg;
445     struct ShifterImmOp ShifterImm;
446     struct RegShiftedRegOp RegShiftedReg;
447     struct RegShiftedImmOp RegShiftedImm;
448     struct RotImmOp RotImm;
449     struct BitfieldOp Bitfield;
450   };
451 
452   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
453 public:
454   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
455     Kind = o.Kind;
456     StartLoc = o.StartLoc;
457     EndLoc = o.EndLoc;
458     switch (Kind) {
459     case k_CondCode:
460       CC = o.CC;
461       break;
462     case k_ITCondMask:
463       ITMask = o.ITMask;
464       break;
465     case k_Token:
466       Tok = o.Tok;
467       break;
468     case k_CCOut:
469     case k_Register:
470       Reg = o.Reg;
471       break;
472     case k_RegisterList:
473     case k_DPRRegisterList:
474     case k_SPRRegisterList:
475       Registers = o.Registers;
476       break;
477     case k_VectorList:
478     case k_VectorListAllLanes:
479     case k_VectorListIndexed:
480       VectorList = o.VectorList;
481       break;
482     case k_CoprocNum:
483     case k_CoprocReg:
484       Cop = o.Cop;
485       break;
486     case k_CoprocOption:
487       CoprocOption = o.CoprocOption;
488       break;
489     case k_Immediate:
490       Imm = o.Imm;
491       break;
492     case k_MemBarrierOpt:
493       MBOpt = o.MBOpt;
494       break;
495     case k_InstSyncBarrierOpt:
496       ISBOpt = o.ISBOpt;
497     case k_Memory:
498       Memory = o.Memory;
499       break;
500     case k_PostIndexRegister:
501       PostIdxReg = o.PostIdxReg;
502       break;
503     case k_MSRMask:
504       MMask = o.MMask;
505       break;
506     case k_ProcIFlags:
507       IFlags = o.IFlags;
508       break;
509     case k_ShifterImmediate:
510       ShifterImm = o.ShifterImm;
511       break;
512     case k_ShiftedRegister:
513       RegShiftedReg = o.RegShiftedReg;
514       break;
515     case k_ShiftedImmediate:
516       RegShiftedImm = o.RegShiftedImm;
517       break;
518     case k_RotateImmediate:
519       RotImm = o.RotImm;
520       break;
521     case k_BitfieldDescriptor:
522       Bitfield = o.Bitfield;
523       break;
524     case k_VectorIndex:
525       VectorIndex = o.VectorIndex;
526       break;
527     }
528   }
529 
530   /// getStartLoc - Get the location of the first token of this operand.
531   SMLoc getStartLoc() const { return StartLoc; }
532   /// getEndLoc - Get the location of the last token of this operand.
533   SMLoc getEndLoc() const { return EndLoc; }
534   /// getLocRange - Get the range between the first and last token of this
535   /// operand.
536   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
537 
538   ARMCC::CondCodes getCondCode() const {
539     assert(Kind == k_CondCode && "Invalid access!");
540     return CC.Val;
541   }
542 
543   unsigned getCoproc() const {
544     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
545     return Cop.Val;
546   }
547 
548   StringRef getToken() const {
549     assert(Kind == k_Token && "Invalid access!");
550     return StringRef(Tok.Data, Tok.Length);
551   }
552 
553   unsigned getReg() const {
554     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
555     return Reg.RegNum;
556   }
557 
558   const SmallVectorImpl<unsigned> &getRegList() const {
559     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
560             Kind == k_SPRRegisterList) && "Invalid access!");
561     return Registers;
562   }
563 
564   const MCExpr *getImm() const {
565     assert(isImm() && "Invalid access!");
566     return Imm.Val;
567   }
568 
569   unsigned getVectorIndex() const {
570     assert(Kind == k_VectorIndex && "Invalid access!");
571     return VectorIndex.Val;
572   }
573 
574   ARM_MB::MemBOpt getMemBarrierOpt() const {
575     assert(Kind == k_MemBarrierOpt && "Invalid access!");
576     return MBOpt.Val;
577   }
578 
579   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
580     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
581     return ISBOpt.Val;
582   }
583 
584   ARM_PROC::IFlags getProcIFlags() const {
585     assert(Kind == k_ProcIFlags && "Invalid access!");
586     return IFlags.Val;
587   }
588 
589   unsigned getMSRMask() const {
590     assert(Kind == k_MSRMask && "Invalid access!");
591     return MMask.Val;
592   }
593 
594   bool isCoprocNum() const { return Kind == k_CoprocNum; }
595   bool isCoprocReg() const { return Kind == k_CoprocReg; }
596   bool isCoprocOption() const { return Kind == k_CoprocOption; }
597   bool isCondCode() const { return Kind == k_CondCode; }
598   bool isCCOut() const { return Kind == k_CCOut; }
599   bool isITMask() const { return Kind == k_ITCondMask; }
600   bool isITCondCode() const { return Kind == k_CondCode; }
601   bool isImm() const { return Kind == k_Immediate; }
602   // checks whether this operand is an unsigned offset which fits is a field
603   // of specified width and scaled by a specific number of bits
604   template<unsigned width, unsigned scale>
605   bool isUnsignedOffset() const {
606     if (!isImm()) return false;
607     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
608     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
609       int64_t Val = CE->getValue();
610       int64_t Align = 1LL << scale;
611       int64_t Max = Align * ((1LL << width) - 1);
612       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
613     }
614     return false;
615   }
616   // checks whether this operand is an signed offset which fits is a field
617   // of specified width and scaled by a specific number of bits
618   template<unsigned width, unsigned scale>
619   bool isSignedOffset() const {
620     if (!isImm()) return false;
621     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
622     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
623       int64_t Val = CE->getValue();
624       int64_t Align = 1LL << scale;
625       int64_t Max = Align * ((1LL << (width-1)) - 1);
626       int64_t Min = -Align * (1LL << (width-1));
627       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
628     }
629     return false;
630   }
631 
632   // checks whether this operand is a memory operand computed as an offset
633   // applied to PC. the offset may have 8 bits of magnitude and is represented
634   // with two bits of shift. textually it may be either [pc, #imm], #imm or
635   // relocable expression...
636   bool isThumbMemPC() const {
637     int64_t Val = 0;
638     if (isImm()) {
639       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
640       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
641       if (!CE) return false;
642       Val = CE->getValue();
643     }
644     else if (isMem()) {
645       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
646       if(Memory.BaseRegNum != ARM::PC) return false;
647       Val = Memory.OffsetImm->getValue();
648     }
649     else return false;
650     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
651   }
652   bool isFPImm() const {
653     if (!isImm()) return false;
654     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
655     if (!CE) return false;
656     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
657     return Val != -1;
658   }
659   bool isFBits16() const {
660     if (!isImm()) return false;
661     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
662     if (!CE) return false;
663     int64_t Value = CE->getValue();
664     return Value >= 0 && Value <= 16;
665   }
666   bool isFBits32() const {
667     if (!isImm()) return false;
668     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
669     if (!CE) return false;
670     int64_t Value = CE->getValue();
671     return Value >= 1 && Value <= 32;
672   }
673   bool isImm8s4() const {
674     if (!isImm()) return false;
675     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676     if (!CE) return false;
677     int64_t Value = CE->getValue();
678     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
679   }
680   bool isImm0_4() const {
681     if (!isImm()) return false;
682     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683     if (!CE) return false;
684     int64_t Value = CE->getValue();
685     return Value >= 0 && Value < 5;
686   }
687   bool isImm0_1020s4() const {
688     if (!isImm()) return false;
689     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
690     if (!CE) return false;
691     int64_t Value = CE->getValue();
692     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
693   }
694   bool isImm0_508s4() const {
695     if (!isImm()) return false;
696     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
697     if (!CE) return false;
698     int64_t Value = CE->getValue();
699     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
700   }
701   bool isImm0_508s4Neg() const {
702     if (!isImm()) return false;
703     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
704     if (!CE) return false;
705     int64_t Value = -CE->getValue();
706     // explicitly exclude zero. we want that to use the normal 0_508 version.
707     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
708   }
709   bool isImm0_255() const {
710     if (!isImm()) return false;
711     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
712     if (!CE) return false;
713     int64_t Value = CE->getValue();
714     return Value >= 0 && Value < 256;
715   }
716   bool isImm0_4095() const {
717     if (!isImm()) return false;
718     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
719     if (!CE) return false;
720     int64_t Value = CE->getValue();
721     return Value >= 0 && Value < 4096;
722   }
723   bool isImm0_4095Neg() const {
724     if (!isImm()) return false;
725     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
726     if (!CE) return false;
727     int64_t Value = -CE->getValue();
728     return Value > 0 && Value < 4096;
729   }
730   bool isImm0_1() const {
731     if (!isImm()) return false;
732     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
733     if (!CE) return false;
734     int64_t Value = CE->getValue();
735     return Value >= 0 && Value < 2;
736   }
737   bool isImm0_3() const {
738     if (!isImm()) return false;
739     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
740     if (!CE) return false;
741     int64_t Value = CE->getValue();
742     return Value >= 0 && Value < 4;
743   }
744   bool isImm0_7() const {
745     if (!isImm()) return false;
746     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
747     if (!CE) return false;
748     int64_t Value = CE->getValue();
749     return Value >= 0 && Value < 8;
750   }
751   bool isImm0_15() const {
752     if (!isImm()) return false;
753     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
754     if (!CE) return false;
755     int64_t Value = CE->getValue();
756     return Value >= 0 && Value < 16;
757   }
758   bool isImm0_31() const {
759     if (!isImm()) return false;
760     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
761     if (!CE) return false;
762     int64_t Value = CE->getValue();
763     return Value >= 0 && Value < 32;
764   }
765   bool isImm0_63() const {
766     if (!isImm()) return false;
767     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
768     if (!CE) return false;
769     int64_t Value = CE->getValue();
770     return Value >= 0 && Value < 64;
771   }
772   bool isImm8() const {
773     if (!isImm()) return false;
774     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
775     if (!CE) return false;
776     int64_t Value = CE->getValue();
777     return Value == 8;
778   }
779   bool isImm16() const {
780     if (!isImm()) return false;
781     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
782     if (!CE) return false;
783     int64_t Value = CE->getValue();
784     return Value == 16;
785   }
786   bool isImm32() const {
787     if (!isImm()) return false;
788     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
789     if (!CE) return false;
790     int64_t Value = CE->getValue();
791     return Value == 32;
792   }
793   bool isShrImm8() const {
794     if (!isImm()) return false;
795     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
796     if (!CE) return false;
797     int64_t Value = CE->getValue();
798     return Value > 0 && Value <= 8;
799   }
800   bool isShrImm16() const {
801     if (!isImm()) return false;
802     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
803     if (!CE) return false;
804     int64_t Value = CE->getValue();
805     return Value > 0 && Value <= 16;
806   }
807   bool isShrImm32() const {
808     if (!isImm()) return false;
809     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
810     if (!CE) return false;
811     int64_t Value = CE->getValue();
812     return Value > 0 && Value <= 32;
813   }
814   bool isShrImm64() const {
815     if (!isImm()) return false;
816     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
817     if (!CE) return false;
818     int64_t Value = CE->getValue();
819     return Value > 0 && Value <= 64;
820   }
821   bool isImm1_7() const {
822     if (!isImm()) return false;
823     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
824     if (!CE) return false;
825     int64_t Value = CE->getValue();
826     return Value > 0 && Value < 8;
827   }
828   bool isImm1_15() const {
829     if (!isImm()) return false;
830     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
831     if (!CE) return false;
832     int64_t Value = CE->getValue();
833     return Value > 0 && Value < 16;
834   }
835   bool isImm1_31() const {
836     if (!isImm()) return false;
837     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
838     if (!CE) return false;
839     int64_t Value = CE->getValue();
840     return Value > 0 && Value < 32;
841   }
842   bool isImm1_16() const {
843     if (!isImm()) return false;
844     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
845     if (!CE) return false;
846     int64_t Value = CE->getValue();
847     return Value > 0 && Value < 17;
848   }
849   bool isImm1_32() const {
850     if (!isImm()) return false;
851     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
852     if (!CE) return false;
853     int64_t Value = CE->getValue();
854     return Value > 0 && Value < 33;
855   }
856   bool isImm0_32() const {
857     if (!isImm()) return false;
858     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859     if (!CE) return false;
860     int64_t Value = CE->getValue();
861     return Value >= 0 && Value < 33;
862   }
863   bool isImm0_65535() const {
864     if (!isImm()) return false;
865     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866     if (!CE) return false;
867     int64_t Value = CE->getValue();
868     return Value >= 0 && Value < 65536;
869   }
870   bool isImm0_65535Expr() const {
871     if (!isImm()) return false;
872     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873     // If it's not a constant expression, it'll generate a fixup and be
874     // handled later.
875     if (!CE) return true;
876     int64_t Value = CE->getValue();
877     return Value >= 0 && Value < 65536;
878   }
879   bool isImm24bit() const {
880     if (!isImm()) return false;
881     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
882     if (!CE) return false;
883     int64_t Value = CE->getValue();
884     return Value >= 0 && Value <= 0xffffff;
885   }
886   bool isImmThumbSR() const {
887     if (!isImm()) return false;
888     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
889     if (!CE) return false;
890     int64_t Value = CE->getValue();
891     return Value > 0 && Value < 33;
892   }
893   bool isPKHLSLImm() const {
894     if (!isImm()) return false;
895     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
896     if (!CE) return false;
897     int64_t Value = CE->getValue();
898     return Value >= 0 && Value < 32;
899   }
900   bool isPKHASRImm() const {
901     if (!isImm()) return false;
902     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
903     if (!CE) return false;
904     int64_t Value = CE->getValue();
905     return Value > 0 && Value <= 32;
906   }
907   bool isAdrLabel() const {
908     // If we have an immediate that's not a constant, treat it as a label
909     // reference needing a fixup. If it is a constant, but it can't fit
910     // into shift immediate encoding, we reject it.
911     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
912     else return (isARMSOImm() || isARMSOImmNeg());
913   }
914   bool isARMSOImm() const {
915     if (!isImm()) return false;
916     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
917     if (!CE) return false;
918     int64_t Value = CE->getValue();
919     return ARM_AM::getSOImmVal(Value) != -1;
920   }
921   bool isARMSOImmNot() const {
922     if (!isImm()) return false;
923     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
924     if (!CE) return false;
925     int64_t Value = CE->getValue();
926     return ARM_AM::getSOImmVal(~Value) != -1;
927   }
928   bool isARMSOImmNeg() const {
929     if (!isImm()) return false;
930     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
931     if (!CE) return false;
932     int64_t Value = CE->getValue();
933     // Only use this when not representable as a plain so_imm.
934     return ARM_AM::getSOImmVal(Value) == -1 &&
935       ARM_AM::getSOImmVal(-Value) != -1;
936   }
937   bool isT2SOImm() const {
938     if (!isImm()) return false;
939     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940     if (!CE) return false;
941     int64_t Value = CE->getValue();
942     return ARM_AM::getT2SOImmVal(Value) != -1;
943   }
944   bool isT2SOImmNot() const {
945     if (!isImm()) return false;
946     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
947     if (!CE) return false;
948     int64_t Value = CE->getValue();
949     return ARM_AM::getT2SOImmVal(~Value) != -1;
950   }
951   bool isT2SOImmNeg() const {
952     if (!isImm()) return false;
953     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
954     if (!CE) return false;
955     int64_t Value = CE->getValue();
956     // Only use this when not representable as a plain so_imm.
957     return ARM_AM::getT2SOImmVal(Value) == -1 &&
958       ARM_AM::getT2SOImmVal(-Value) != -1;
959   }
960   bool isSetEndImm() const {
961     if (!isImm()) return false;
962     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
963     if (!CE) return false;
964     int64_t Value = CE->getValue();
965     return Value == 1 || Value == 0;
966   }
967   bool isReg() const { return Kind == k_Register; }
968   bool isRegList() const { return Kind == k_RegisterList; }
969   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
970   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
971   bool isToken() const { return Kind == k_Token; }
972   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
973   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
974   bool isMem() const { return Kind == k_Memory; }
975   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
976   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
977   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
978   bool isRotImm() const { return Kind == k_RotateImmediate; }
979   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
980   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
981   bool isPostIdxReg() const {
982     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
983   }
984   bool isMemNoOffset(bool alignOK = false) const {
985     if (!isMem())
986       return false;
987     // No offset of any kind.
988     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
989      (alignOK || Memory.Alignment == 0);
990   }
991   bool isMemPCRelImm12() const {
992     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
993       return false;
994     // Base register must be PC.
995     if (Memory.BaseRegNum != ARM::PC)
996       return false;
997     // Immediate offset in range [-4095, 4095].
998     if (!Memory.OffsetImm) return true;
999     int64_t Val = Memory.OffsetImm->getValue();
1000     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1001   }
1002   bool isAlignedMemory() const {
1003     return isMemNoOffset(true);
1004   }
1005   bool isAddrMode2() const {
1006     if (!isMem() || Memory.Alignment != 0) return false;
1007     // Check for register offset.
1008     if (Memory.OffsetRegNum) return true;
1009     // Immediate offset in range [-4095, 4095].
1010     if (!Memory.OffsetImm) return true;
1011     int64_t Val = Memory.OffsetImm->getValue();
1012     return Val > -4096 && Val < 4096;
1013   }
1014   bool isAM2OffsetImm() const {
1015     if (!isImm()) return false;
1016     // Immediate offset in range [-4095, 4095].
1017     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1018     if (!CE) return false;
1019     int64_t Val = CE->getValue();
1020     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1021   }
1022   bool isAddrMode3() const {
1023     // If we have an immediate that's not a constant, treat it as a label
1024     // reference needing a fixup. If it is a constant, it's something else
1025     // and we reject it.
1026     if (isImm() && !isa<MCConstantExpr>(getImm()))
1027       return true;
1028     if (!isMem() || Memory.Alignment != 0) return false;
1029     // No shifts are legal for AM3.
1030     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1031     // Check for register offset.
1032     if (Memory.OffsetRegNum) return true;
1033     // Immediate offset in range [-255, 255].
1034     if (!Memory.OffsetImm) return true;
1035     int64_t Val = Memory.OffsetImm->getValue();
1036     // The #-0 offset is encoded as INT32_MIN, and we have to check
1037     // for this too.
1038     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1039   }
1040   bool isAM3Offset() const {
1041     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1042       return false;
1043     if (Kind == k_PostIndexRegister)
1044       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1045     // Immediate offset in range [-255, 255].
1046     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1047     if (!CE) return false;
1048     int64_t Val = CE->getValue();
1049     // Special case, #-0 is INT32_MIN.
1050     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1051   }
1052   bool isAddrMode5() const {
1053     // If we have an immediate that's not a constant, treat it as a label
1054     // reference needing a fixup. If it is a constant, it's something else
1055     // and we reject it.
1056     if (isImm() && !isa<MCConstantExpr>(getImm()))
1057       return true;
1058     if (!isMem() || Memory.Alignment != 0) return false;
1059     // Check for register offset.
1060     if (Memory.OffsetRegNum) return false;
1061     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1062     if (!Memory.OffsetImm) return true;
1063     int64_t Val = Memory.OffsetImm->getValue();
1064     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1065       Val == INT32_MIN;
1066   }
1067   bool isMemTBB() const {
1068     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1069         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1070       return false;
1071     return true;
1072   }
1073   bool isMemTBH() const {
1074     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1075         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1076         Memory.Alignment != 0 )
1077       return false;
1078     return true;
1079   }
1080   bool isMemRegOffset() const {
1081     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1082       return false;
1083     return true;
1084   }
1085   bool isT2MemRegOffset() const {
1086     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1087         Memory.Alignment != 0)
1088       return false;
1089     // Only lsl #{0, 1, 2, 3} allowed.
1090     if (Memory.ShiftType == ARM_AM::no_shift)
1091       return true;
1092     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1093       return false;
1094     return true;
1095   }
1096   bool isMemThumbRR() const {
1097     // Thumb reg+reg addressing is simple. Just two registers, a base and
1098     // an offset. No shifts, negations or any other complicating factors.
1099     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1100         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1101       return false;
1102     return isARMLowRegister(Memory.BaseRegNum) &&
1103       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1104   }
1105   bool isMemThumbRIs4() const {
1106     if (!isMem() || Memory.OffsetRegNum != 0 ||
1107         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1108       return false;
1109     // Immediate offset, multiple of 4 in range [0, 124].
1110     if (!Memory.OffsetImm) return true;
1111     int64_t Val = Memory.OffsetImm->getValue();
1112     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1113   }
1114   bool isMemThumbRIs2() const {
1115     if (!isMem() || Memory.OffsetRegNum != 0 ||
1116         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1117       return false;
1118     // Immediate offset, multiple of 4 in range [0, 62].
1119     if (!Memory.OffsetImm) return true;
1120     int64_t Val = Memory.OffsetImm->getValue();
1121     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1122   }
1123   bool isMemThumbRIs1() const {
1124     if (!isMem() || Memory.OffsetRegNum != 0 ||
1125         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1126       return false;
1127     // Immediate offset in range [0, 31].
1128     if (!Memory.OffsetImm) return true;
1129     int64_t Val = Memory.OffsetImm->getValue();
1130     return Val >= 0 && Val <= 31;
1131   }
1132   bool isMemThumbSPI() const {
1133     if (!isMem() || Memory.OffsetRegNum != 0 ||
1134         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1135       return false;
1136     // Immediate offset, multiple of 4 in range [0, 1020].
1137     if (!Memory.OffsetImm) return true;
1138     int64_t Val = Memory.OffsetImm->getValue();
1139     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1140   }
1141   bool isMemImm8s4Offset() const {
1142     // If we have an immediate that's not a constant, treat it as a label
1143     // reference needing a fixup. If it is a constant, it's something else
1144     // and we reject it.
1145     if (isImm() && !isa<MCConstantExpr>(getImm()))
1146       return true;
1147     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1148       return false;
1149     // Immediate offset a multiple of 4 in range [-1020, 1020].
1150     if (!Memory.OffsetImm) return true;
1151     int64_t Val = Memory.OffsetImm->getValue();
1152     // Special case, #-0 is INT32_MIN.
1153     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1154   }
1155   bool isMemImm0_1020s4Offset() const {
1156     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1157       return false;
1158     // Immediate offset a multiple of 4 in range [0, 1020].
1159     if (!Memory.OffsetImm) return true;
1160     int64_t Val = Memory.OffsetImm->getValue();
1161     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1162   }
1163   bool isMemImm8Offset() const {
1164     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1165       return false;
1166     // Base reg of PC isn't allowed for these encodings.
1167     if (Memory.BaseRegNum == ARM::PC) return false;
1168     // Immediate offset in range [-255, 255].
1169     if (!Memory.OffsetImm) return true;
1170     int64_t Val = Memory.OffsetImm->getValue();
1171     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1172   }
1173   bool isMemPosImm8Offset() const {
1174     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1175       return false;
1176     // Immediate offset in range [0, 255].
1177     if (!Memory.OffsetImm) return true;
1178     int64_t Val = Memory.OffsetImm->getValue();
1179     return Val >= 0 && Val < 256;
1180   }
1181   bool isMemNegImm8Offset() const {
1182     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1183       return false;
1184     // Base reg of PC isn't allowed for these encodings.
1185     if (Memory.BaseRegNum == ARM::PC) return false;
1186     // Immediate offset in range [-255, -1].
1187     if (!Memory.OffsetImm) return false;
1188     int64_t Val = Memory.OffsetImm->getValue();
1189     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1190   }
1191   bool isMemUImm12Offset() const {
1192     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1193       return false;
1194     // Immediate offset in range [0, 4095].
1195     if (!Memory.OffsetImm) return true;
1196     int64_t Val = Memory.OffsetImm->getValue();
1197     return (Val >= 0 && Val < 4096);
1198   }
1199   bool isMemImm12Offset() const {
1200     // If we have an immediate that's not a constant, treat it as a label
1201     // reference needing a fixup. If it is a constant, it's something else
1202     // and we reject it.
1203     if (isImm() && !isa<MCConstantExpr>(getImm()))
1204       return true;
1205 
1206     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1207       return false;
1208     // Immediate offset in range [-4095, 4095].
1209     if (!Memory.OffsetImm) return true;
1210     int64_t Val = Memory.OffsetImm->getValue();
1211     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1212   }
1213   bool isPostIdxImm8() const {
1214     if (!isImm()) return false;
1215     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1216     if (!CE) return false;
1217     int64_t Val = CE->getValue();
1218     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1219   }
1220   bool isPostIdxImm8s4() const {
1221     if (!isImm()) return false;
1222     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1223     if (!CE) return false;
1224     int64_t Val = CE->getValue();
1225     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1226       (Val == INT32_MIN);
1227   }
1228 
1229   bool isMSRMask() const { return Kind == k_MSRMask; }
1230   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1231 
1232   // NEON operands.
1233   bool isSingleSpacedVectorList() const {
1234     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1235   }
1236   bool isDoubleSpacedVectorList() const {
1237     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1238   }
1239   bool isVecListOneD() const {
1240     if (!isSingleSpacedVectorList()) return false;
1241     return VectorList.Count == 1;
1242   }
1243 
1244   bool isVecListDPair() const {
1245     if (!isSingleSpacedVectorList()) return false;
1246     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1247               .contains(VectorList.RegNum));
1248   }
1249 
1250   bool isVecListThreeD() const {
1251     if (!isSingleSpacedVectorList()) return false;
1252     return VectorList.Count == 3;
1253   }
1254 
1255   bool isVecListFourD() const {
1256     if (!isSingleSpacedVectorList()) return false;
1257     return VectorList.Count == 4;
1258   }
1259 
1260   bool isVecListDPairSpaced() const {
1261     if (isSingleSpacedVectorList()) return false;
1262     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1263               .contains(VectorList.RegNum));
1264   }
1265 
1266   bool isVecListThreeQ() const {
1267     if (!isDoubleSpacedVectorList()) return false;
1268     return VectorList.Count == 3;
1269   }
1270 
1271   bool isVecListFourQ() const {
1272     if (!isDoubleSpacedVectorList()) return false;
1273     return VectorList.Count == 4;
1274   }
1275 
1276   bool isSingleSpacedVectorAllLanes() const {
1277     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1278   }
1279   bool isDoubleSpacedVectorAllLanes() const {
1280     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1281   }
1282   bool isVecListOneDAllLanes() const {
1283     if (!isSingleSpacedVectorAllLanes()) return false;
1284     return VectorList.Count == 1;
1285   }
1286 
1287   bool isVecListDPairAllLanes() const {
1288     if (!isSingleSpacedVectorAllLanes()) return false;
1289     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1290               .contains(VectorList.RegNum));
1291   }
1292 
1293   bool isVecListDPairSpacedAllLanes() const {
1294     if (!isDoubleSpacedVectorAllLanes()) return false;
1295     return VectorList.Count == 2;
1296   }
1297 
1298   bool isVecListThreeDAllLanes() const {
1299     if (!isSingleSpacedVectorAllLanes()) return false;
1300     return VectorList.Count == 3;
1301   }
1302 
1303   bool isVecListThreeQAllLanes() const {
1304     if (!isDoubleSpacedVectorAllLanes()) return false;
1305     return VectorList.Count == 3;
1306   }
1307 
1308   bool isVecListFourDAllLanes() const {
1309     if (!isSingleSpacedVectorAllLanes()) return false;
1310     return VectorList.Count == 4;
1311   }
1312 
1313   bool isVecListFourQAllLanes() const {
1314     if (!isDoubleSpacedVectorAllLanes()) return false;
1315     return VectorList.Count == 4;
1316   }
1317 
1318   bool isSingleSpacedVectorIndexed() const {
1319     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1320   }
1321   bool isDoubleSpacedVectorIndexed() const {
1322     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1323   }
1324   bool isVecListOneDByteIndexed() const {
1325     if (!isSingleSpacedVectorIndexed()) return false;
1326     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1327   }
1328 
1329   bool isVecListOneDHWordIndexed() const {
1330     if (!isSingleSpacedVectorIndexed()) return false;
1331     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1332   }
1333 
1334   bool isVecListOneDWordIndexed() const {
1335     if (!isSingleSpacedVectorIndexed()) return false;
1336     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1337   }
1338 
1339   bool isVecListTwoDByteIndexed() const {
1340     if (!isSingleSpacedVectorIndexed()) return false;
1341     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1342   }
1343 
1344   bool isVecListTwoDHWordIndexed() const {
1345     if (!isSingleSpacedVectorIndexed()) return false;
1346     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1347   }
1348 
1349   bool isVecListTwoQWordIndexed() const {
1350     if (!isDoubleSpacedVectorIndexed()) return false;
1351     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1352   }
1353 
1354   bool isVecListTwoQHWordIndexed() const {
1355     if (!isDoubleSpacedVectorIndexed()) return false;
1356     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1357   }
1358 
1359   bool isVecListTwoDWordIndexed() const {
1360     if (!isSingleSpacedVectorIndexed()) return false;
1361     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1362   }
1363 
1364   bool isVecListThreeDByteIndexed() const {
1365     if (!isSingleSpacedVectorIndexed()) return false;
1366     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1367   }
1368 
1369   bool isVecListThreeDHWordIndexed() const {
1370     if (!isSingleSpacedVectorIndexed()) return false;
1371     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1372   }
1373 
1374   bool isVecListThreeQWordIndexed() const {
1375     if (!isDoubleSpacedVectorIndexed()) return false;
1376     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1377   }
1378 
1379   bool isVecListThreeQHWordIndexed() const {
1380     if (!isDoubleSpacedVectorIndexed()) return false;
1381     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1382   }
1383 
1384   bool isVecListThreeDWordIndexed() const {
1385     if (!isSingleSpacedVectorIndexed()) return false;
1386     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1387   }
1388 
1389   bool isVecListFourDByteIndexed() const {
1390     if (!isSingleSpacedVectorIndexed()) return false;
1391     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1392   }
1393 
1394   bool isVecListFourDHWordIndexed() const {
1395     if (!isSingleSpacedVectorIndexed()) return false;
1396     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1397   }
1398 
1399   bool isVecListFourQWordIndexed() const {
1400     if (!isDoubleSpacedVectorIndexed()) return false;
1401     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1402   }
1403 
1404   bool isVecListFourQHWordIndexed() const {
1405     if (!isDoubleSpacedVectorIndexed()) return false;
1406     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1407   }
1408 
1409   bool isVecListFourDWordIndexed() const {
1410     if (!isSingleSpacedVectorIndexed()) return false;
1411     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1412   }
1413 
1414   bool isVectorIndex8() const {
1415     if (Kind != k_VectorIndex) return false;
1416     return VectorIndex.Val < 8;
1417   }
1418   bool isVectorIndex16() const {
1419     if (Kind != k_VectorIndex) return false;
1420     return VectorIndex.Val < 4;
1421   }
1422   bool isVectorIndex32() const {
1423     if (Kind != k_VectorIndex) return false;
1424     return VectorIndex.Val < 2;
1425   }
1426 
1427   bool isNEONi8splat() const {
1428     if (!isImm()) return false;
1429     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1430     // Must be a constant.
1431     if (!CE) return false;
1432     int64_t Value = CE->getValue();
1433     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1434     // value.
1435     return Value >= 0 && Value < 256;
1436   }
1437 
1438   bool isNEONi16splat() const {
1439     if (!isImm()) return false;
1440     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1441     // Must be a constant.
1442     if (!CE) return false;
1443     int64_t Value = CE->getValue();
1444     // i16 value in the range [0,255] or [0x0100, 0xff00]
1445     return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1446   }
1447 
1448   bool isNEONi32splat() const {
1449     if (!isImm()) return false;
1450     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1451     // Must be a constant.
1452     if (!CE) return false;
1453     int64_t Value = CE->getValue();
1454     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1455     return (Value >= 0 && Value < 256) ||
1456       (Value >= 0x0100 && Value <= 0xff00) ||
1457       (Value >= 0x010000 && Value <= 0xff0000) ||
1458       (Value >= 0x01000000 && Value <= 0xff000000);
1459   }
1460 
1461   bool isNEONi32vmov() const {
1462     if (!isImm()) return false;
1463     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1464     // Must be a constant.
1465     if (!CE) return false;
1466     int64_t Value = CE->getValue();
1467     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1468     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1469     return (Value >= 0 && Value < 256) ||
1470       (Value >= 0x0100 && Value <= 0xff00) ||
1471       (Value >= 0x010000 && Value <= 0xff0000) ||
1472       (Value >= 0x01000000 && Value <= 0xff000000) ||
1473       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1474       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1475   }
1476   bool isNEONi32vmovNeg() const {
1477     if (!isImm()) return false;
1478     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1479     // Must be a constant.
1480     if (!CE) return false;
1481     int64_t Value = ~CE->getValue();
1482     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1483     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1484     return (Value >= 0 && Value < 256) ||
1485       (Value >= 0x0100 && Value <= 0xff00) ||
1486       (Value >= 0x010000 && Value <= 0xff0000) ||
1487       (Value >= 0x01000000 && Value <= 0xff000000) ||
1488       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1489       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1490   }
1491 
1492   bool isNEONi64splat() const {
1493     if (!isImm()) return false;
1494     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1495     // Must be a constant.
1496     if (!CE) return false;
1497     uint64_t Value = CE->getValue();
1498     // i64 value with each byte being either 0 or 0xff.
1499     for (unsigned i = 0; i < 8; ++i)
1500       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1501     return true;
1502   }
1503 
1504   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1505     // Add as immediates when possible.  Null MCExpr = 0.
1506     if (Expr == 0)
1507       Inst.addOperand(MCOperand::CreateImm(0));
1508     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1509       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1510     else
1511       Inst.addOperand(MCOperand::CreateExpr(Expr));
1512   }
1513 
1514   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1515     assert(N == 2 && "Invalid number of operands!");
1516     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1517     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1518     Inst.addOperand(MCOperand::CreateReg(RegNum));
1519   }
1520 
1521   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1522     assert(N == 1 && "Invalid number of operands!");
1523     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1524   }
1525 
1526   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1527     assert(N == 1 && "Invalid number of operands!");
1528     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1529   }
1530 
1531   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1532     assert(N == 1 && "Invalid number of operands!");
1533     Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1534   }
1535 
1536   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1537     assert(N == 1 && "Invalid number of operands!");
1538     Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1539   }
1540 
1541   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1542     assert(N == 1 && "Invalid number of operands!");
1543     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1544   }
1545 
1546   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1547     assert(N == 1 && "Invalid number of operands!");
1548     Inst.addOperand(MCOperand::CreateReg(getReg()));
1549   }
1550 
1551   void addRegOperands(MCInst &Inst, unsigned N) const {
1552     assert(N == 1 && "Invalid number of operands!");
1553     Inst.addOperand(MCOperand::CreateReg(getReg()));
1554   }
1555 
1556   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1557     assert(N == 3 && "Invalid number of operands!");
1558     assert(isRegShiftedReg() &&
1559            "addRegShiftedRegOperands() on non RegShiftedReg!");
1560     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1561     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1562     Inst.addOperand(MCOperand::CreateImm(
1563       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1564   }
1565 
1566   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1567     assert(N == 2 && "Invalid number of operands!");
1568     assert(isRegShiftedImm() &&
1569            "addRegShiftedImmOperands() on non RegShiftedImm!");
1570     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1571     // Shift of #32 is encoded as 0 where permitted
1572     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1573     Inst.addOperand(MCOperand::CreateImm(
1574       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1575   }
1576 
1577   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1578     assert(N == 1 && "Invalid number of operands!");
1579     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1580                                          ShifterImm.Imm));
1581   }
1582 
1583   void addRegListOperands(MCInst &Inst, unsigned N) const {
1584     assert(N == 1 && "Invalid number of operands!");
1585     const SmallVectorImpl<unsigned> &RegList = getRegList();
1586     for (SmallVectorImpl<unsigned>::const_iterator
1587            I = RegList.begin(), E = RegList.end(); I != E; ++I)
1588       Inst.addOperand(MCOperand::CreateReg(*I));
1589   }
1590 
1591   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1592     addRegListOperands(Inst, N);
1593   }
1594 
1595   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1596     addRegListOperands(Inst, N);
1597   }
1598 
1599   void addRotImmOperands(MCInst &Inst, unsigned N) const {
1600     assert(N == 1 && "Invalid number of operands!");
1601     // Encoded as val>>3. The printer handles display as 8, 16, 24.
1602     Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1603   }
1604 
1605   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1606     assert(N == 1 && "Invalid number of operands!");
1607     // Munge the lsb/width into a bitfield mask.
1608     unsigned lsb = Bitfield.LSB;
1609     unsigned width = Bitfield.Width;
1610     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1611     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1612                       (32 - (lsb + width)));
1613     Inst.addOperand(MCOperand::CreateImm(Mask));
1614   }
1615 
1616   void addImmOperands(MCInst &Inst, unsigned N) const {
1617     assert(N == 1 && "Invalid number of operands!");
1618     addExpr(Inst, getImm());
1619   }
1620 
1621   void addFBits16Operands(MCInst &Inst, unsigned N) const {
1622     assert(N == 1 && "Invalid number of operands!");
1623     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1624     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1625   }
1626 
1627   void addFBits32Operands(MCInst &Inst, unsigned N) const {
1628     assert(N == 1 && "Invalid number of operands!");
1629     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1630     Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1631   }
1632 
1633   void addFPImmOperands(MCInst &Inst, unsigned N) const {
1634     assert(N == 1 && "Invalid number of operands!");
1635     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1636     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1637     Inst.addOperand(MCOperand::CreateImm(Val));
1638   }
1639 
1640   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1641     assert(N == 1 && "Invalid number of operands!");
1642     // FIXME: We really want to scale the value here, but the LDRD/STRD
1643     // instruction don't encode operands that way yet.
1644     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1645     Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1646   }
1647 
1648   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1649     assert(N == 1 && "Invalid number of operands!");
1650     // The immediate is scaled by four in the encoding and is stored
1651     // in the MCInst as such. Lop off the low two bits here.
1652     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1653     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1654   }
1655 
1656   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1657     assert(N == 1 && "Invalid number of operands!");
1658     // The immediate is scaled by four in the encoding and is stored
1659     // in the MCInst as such. Lop off the low two bits here.
1660     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1661     Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1662   }
1663 
1664   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1665     assert(N == 1 && "Invalid number of operands!");
1666     // The immediate is scaled by four in the encoding and is stored
1667     // in the MCInst as such. Lop off the low two bits here.
1668     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1669     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1670   }
1671 
1672   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1673     assert(N == 1 && "Invalid number of operands!");
1674     // The constant encodes as the immediate-1, and we store in the instruction
1675     // the bits as encoded, so subtract off one here.
1676     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1677     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1678   }
1679 
1680   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1681     assert(N == 1 && "Invalid number of operands!");
1682     // The constant encodes as the immediate-1, and we store in the instruction
1683     // the bits as encoded, so subtract off one here.
1684     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1685     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1686   }
1687 
1688   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1689     assert(N == 1 && "Invalid number of operands!");
1690     // The constant encodes as the immediate, except for 32, which encodes as
1691     // zero.
1692     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1693     unsigned Imm = CE->getValue();
1694     Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1695   }
1696 
1697   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1698     assert(N == 1 && "Invalid number of operands!");
1699     // An ASR value of 32 encodes as 0, so that's how we want to add it to
1700     // the instruction as well.
1701     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1702     int Val = CE->getValue();
1703     Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1704   }
1705 
1706   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1707     assert(N == 1 && "Invalid number of operands!");
1708     // The operand is actually a t2_so_imm, but we have its bitwise
1709     // negation in the assembly source, so twiddle it here.
1710     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1711     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1712   }
1713 
1714   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1715     assert(N == 1 && "Invalid number of operands!");
1716     // The operand is actually a t2_so_imm, but we have its
1717     // negation in the assembly source, so twiddle it here.
1718     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1719     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1720   }
1721 
1722   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1723     assert(N == 1 && "Invalid number of operands!");
1724     // The operand is actually an imm0_4095, but we have its
1725     // negation in the assembly source, so twiddle it here.
1726     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1727     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1728   }
1729 
1730   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1731     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1732       Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1733       return;
1734     }
1735 
1736     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1737     assert(SR && "Unknown value type!");
1738     Inst.addOperand(MCOperand::CreateExpr(SR));
1739   }
1740 
1741   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1742     assert(N == 1 && "Invalid number of operands!");
1743     if (isImm()) {
1744       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1745       if (CE) {
1746         Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1747         return;
1748       }
1749 
1750       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1751       assert(SR && "Unknown value type!");
1752       Inst.addOperand(MCOperand::CreateExpr(SR));
1753       return;
1754     }
1755 
1756     assert(isMem()  && "Unknown value type!");
1757     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1758     Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1759   }
1760 
1761   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1762     assert(N == 1 && "Invalid number of operands!");
1763     // The operand is actually a so_imm, but we have its bitwise
1764     // negation in the assembly source, so twiddle it here.
1765     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1766     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1767   }
1768 
1769   void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1770     assert(N == 1 && "Invalid number of operands!");
1771     // The operand is actually a so_imm, but we have its
1772     // negation in the assembly source, so twiddle it here.
1773     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1774     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1775   }
1776 
1777   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1778     assert(N == 1 && "Invalid number of operands!");
1779     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1780   }
1781 
1782   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1783     assert(N == 1 && "Invalid number of operands!");
1784     Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1785   }
1786 
1787   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1788     assert(N == 1 && "Invalid number of operands!");
1789     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1790   }
1791 
1792   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1793     assert(N == 1 && "Invalid number of operands!");
1794     int32_t Imm = Memory.OffsetImm->getValue();
1795     // FIXME: Handle #-0
1796     if (Imm == INT32_MIN) Imm = 0;
1797     Inst.addOperand(MCOperand::CreateImm(Imm));
1798   }
1799 
1800   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1801     assert(N == 1 && "Invalid number of operands!");
1802     assert(isImm() && "Not an immediate!");
1803 
1804     // If we have an immediate that's not a constant, treat it as a label
1805     // reference needing a fixup.
1806     if (!isa<MCConstantExpr>(getImm())) {
1807       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1808       return;
1809     }
1810 
1811     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1812     int Val = CE->getValue();
1813     Inst.addOperand(MCOperand::CreateImm(Val));
1814   }
1815 
1816   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1817     assert(N == 2 && "Invalid number of operands!");
1818     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1819     Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1820   }
1821 
1822   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1823     assert(N == 3 && "Invalid number of operands!");
1824     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1825     if (!Memory.OffsetRegNum) {
1826       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1827       // Special case for #-0
1828       if (Val == INT32_MIN) Val = 0;
1829       if (Val < 0) Val = -Val;
1830       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1831     } else {
1832       // For register offset, we encode the shift type and negation flag
1833       // here.
1834       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1835                               Memory.ShiftImm, Memory.ShiftType);
1836     }
1837     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1838     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1839     Inst.addOperand(MCOperand::CreateImm(Val));
1840   }
1841 
1842   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1843     assert(N == 2 && "Invalid number of operands!");
1844     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1845     assert(CE && "non-constant AM2OffsetImm operand!");
1846     int32_t Val = CE->getValue();
1847     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1848     // Special case for #-0
1849     if (Val == INT32_MIN) Val = 0;
1850     if (Val < 0) Val = -Val;
1851     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1852     Inst.addOperand(MCOperand::CreateReg(0));
1853     Inst.addOperand(MCOperand::CreateImm(Val));
1854   }
1855 
1856   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1857     assert(N == 3 && "Invalid number of operands!");
1858     // If we have an immediate that's not a constant, treat it as a label
1859     // reference needing a fixup. If it is a constant, it's something else
1860     // and we reject it.
1861     if (isImm()) {
1862       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1863       Inst.addOperand(MCOperand::CreateReg(0));
1864       Inst.addOperand(MCOperand::CreateImm(0));
1865       return;
1866     }
1867 
1868     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1869     if (!Memory.OffsetRegNum) {
1870       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1871       // Special case for #-0
1872       if (Val == INT32_MIN) Val = 0;
1873       if (Val < 0) Val = -Val;
1874       Val = ARM_AM::getAM3Opc(AddSub, Val);
1875     } else {
1876       // For register offset, we encode the shift type and negation flag
1877       // here.
1878       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1879     }
1880     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1881     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1882     Inst.addOperand(MCOperand::CreateImm(Val));
1883   }
1884 
1885   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1886     assert(N == 2 && "Invalid number of operands!");
1887     if (Kind == k_PostIndexRegister) {
1888       int32_t Val =
1889         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1890       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1891       Inst.addOperand(MCOperand::CreateImm(Val));
1892       return;
1893     }
1894 
1895     // Constant offset.
1896     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1897     int32_t Val = CE->getValue();
1898     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1899     // Special case for #-0
1900     if (Val == INT32_MIN) Val = 0;
1901     if (Val < 0) Val = -Val;
1902     Val = ARM_AM::getAM3Opc(AddSub, Val);
1903     Inst.addOperand(MCOperand::CreateReg(0));
1904     Inst.addOperand(MCOperand::CreateImm(Val));
1905   }
1906 
1907   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1908     assert(N == 2 && "Invalid number of operands!");
1909     // If we have an immediate that's not a constant, treat it as a label
1910     // reference needing a fixup. If it is a constant, it's something else
1911     // and we reject it.
1912     if (isImm()) {
1913       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1914       Inst.addOperand(MCOperand::CreateImm(0));
1915       return;
1916     }
1917 
1918     // The lower two bits are always zero and as such are not encoded.
1919     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1920     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1921     // Special case for #-0
1922     if (Val == INT32_MIN) Val = 0;
1923     if (Val < 0) Val = -Val;
1924     Val = ARM_AM::getAM5Opc(AddSub, Val);
1925     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1926     Inst.addOperand(MCOperand::CreateImm(Val));
1927   }
1928 
1929   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1930     assert(N == 2 && "Invalid number of operands!");
1931     // If we have an immediate that's not a constant, treat it as a label
1932     // reference needing a fixup. If it is a constant, it's something else
1933     // and we reject it.
1934     if (isImm()) {
1935       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1936       Inst.addOperand(MCOperand::CreateImm(0));
1937       return;
1938     }
1939 
1940     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1941     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1942     Inst.addOperand(MCOperand::CreateImm(Val));
1943   }
1944 
1945   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1946     assert(N == 2 && "Invalid number of operands!");
1947     // The lower two bits are always zero and as such are not encoded.
1948     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1949     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1950     Inst.addOperand(MCOperand::CreateImm(Val));
1951   }
1952 
1953   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1954     assert(N == 2 && "Invalid number of operands!");
1955     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1956     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1957     Inst.addOperand(MCOperand::CreateImm(Val));
1958   }
1959 
1960   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1961     addMemImm8OffsetOperands(Inst, N);
1962   }
1963 
1964   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1965     addMemImm8OffsetOperands(Inst, N);
1966   }
1967 
1968   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1969     assert(N == 2 && "Invalid number of operands!");
1970     // If this is an immediate, it's a label reference.
1971     if (isImm()) {
1972       addExpr(Inst, getImm());
1973       Inst.addOperand(MCOperand::CreateImm(0));
1974       return;
1975     }
1976 
1977     // Otherwise, it's a normal memory reg+offset.
1978     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1979     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1980     Inst.addOperand(MCOperand::CreateImm(Val));
1981   }
1982 
1983   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1984     assert(N == 2 && "Invalid number of operands!");
1985     // If this is an immediate, it's a label reference.
1986     if (isImm()) {
1987       addExpr(Inst, getImm());
1988       Inst.addOperand(MCOperand::CreateImm(0));
1989       return;
1990     }
1991 
1992     // Otherwise, it's a normal memory reg+offset.
1993     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1994     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1995     Inst.addOperand(MCOperand::CreateImm(Val));
1996   }
1997 
1998   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1999     assert(N == 2 && "Invalid number of operands!");
2000     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2001     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2002   }
2003 
2004   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2005     assert(N == 2 && "Invalid number of operands!");
2006     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2007     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2008   }
2009 
2010   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2011     assert(N == 3 && "Invalid number of operands!");
2012     unsigned Val =
2013       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2014                         Memory.ShiftImm, Memory.ShiftType);
2015     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2016     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2017     Inst.addOperand(MCOperand::CreateImm(Val));
2018   }
2019 
2020   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2021     assert(N == 3 && "Invalid number of operands!");
2022     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2023     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2024     Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2025   }
2026 
2027   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2028     assert(N == 2 && "Invalid number of operands!");
2029     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2030     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2031   }
2032 
2033   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2034     assert(N == 2 && "Invalid number of operands!");
2035     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2036     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2037     Inst.addOperand(MCOperand::CreateImm(Val));
2038   }
2039 
2040   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2041     assert(N == 2 && "Invalid number of operands!");
2042     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2043     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2044     Inst.addOperand(MCOperand::CreateImm(Val));
2045   }
2046 
2047   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2048     assert(N == 2 && "Invalid number of operands!");
2049     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2050     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2051     Inst.addOperand(MCOperand::CreateImm(Val));
2052   }
2053 
2054   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2055     assert(N == 2 && "Invalid number of operands!");
2056     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2057     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2058     Inst.addOperand(MCOperand::CreateImm(Val));
2059   }
2060 
2061   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2062     assert(N == 1 && "Invalid number of operands!");
2063     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2064     assert(CE && "non-constant post-idx-imm8 operand!");
2065     int Imm = CE->getValue();
2066     bool isAdd = Imm >= 0;
2067     if (Imm == INT32_MIN) Imm = 0;
2068     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2069     Inst.addOperand(MCOperand::CreateImm(Imm));
2070   }
2071 
2072   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2073     assert(N == 1 && "Invalid number of operands!");
2074     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2075     assert(CE && "non-constant post-idx-imm8s4 operand!");
2076     int Imm = CE->getValue();
2077     bool isAdd = Imm >= 0;
2078     if (Imm == INT32_MIN) Imm = 0;
2079     // Immediate is scaled by 4.
2080     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2081     Inst.addOperand(MCOperand::CreateImm(Imm));
2082   }
2083 
2084   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2085     assert(N == 2 && "Invalid number of operands!");
2086     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2087     Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2088   }
2089 
2090   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2091     assert(N == 2 && "Invalid number of operands!");
2092     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2093     // The sign, shift type, and shift amount are encoded in a single operand
2094     // using the AM2 encoding helpers.
2095     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2096     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2097                                      PostIdxReg.ShiftTy);
2098     Inst.addOperand(MCOperand::CreateImm(Imm));
2099   }
2100 
2101   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2102     assert(N == 1 && "Invalid number of operands!");
2103     Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2104   }
2105 
2106   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2107     assert(N == 1 && "Invalid number of operands!");
2108     Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2109   }
2110 
2111   void addVecListOperands(MCInst &Inst, unsigned N) const {
2112     assert(N == 1 && "Invalid number of operands!");
2113     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2114   }
2115 
2116   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2117     assert(N == 2 && "Invalid number of operands!");
2118     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2119     Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2120   }
2121 
2122   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2123     assert(N == 1 && "Invalid number of operands!");
2124     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2125   }
2126 
2127   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2128     assert(N == 1 && "Invalid number of operands!");
2129     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2130   }
2131 
2132   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2133     assert(N == 1 && "Invalid number of operands!");
2134     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2135   }
2136 
2137   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2138     assert(N == 1 && "Invalid number of operands!");
2139     // The immediate encodes the type of constant as well as the value.
2140     // Mask in that this is an i8 splat.
2141     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2142     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2143   }
2144 
2145   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2146     assert(N == 1 && "Invalid number of operands!");
2147     // The immediate encodes the type of constant as well as the value.
2148     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2149     unsigned Value = CE->getValue();
2150     if (Value >= 256)
2151       Value = (Value >> 8) | 0xa00;
2152     else
2153       Value |= 0x800;
2154     Inst.addOperand(MCOperand::CreateImm(Value));
2155   }
2156 
2157   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2158     assert(N == 1 && "Invalid number of operands!");
2159     // The immediate encodes the type of constant as well as the value.
2160     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2161     unsigned Value = CE->getValue();
2162     if (Value >= 256 && Value <= 0xff00)
2163       Value = (Value >> 8) | 0x200;
2164     else if (Value > 0xffff && Value <= 0xff0000)
2165       Value = (Value >> 16) | 0x400;
2166     else if (Value > 0xffffff)
2167       Value = (Value >> 24) | 0x600;
2168     Inst.addOperand(MCOperand::CreateImm(Value));
2169   }
2170 
2171   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2172     assert(N == 1 && "Invalid number of operands!");
2173     // The immediate encodes the type of constant as well as the value.
2174     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2175     unsigned Value = CE->getValue();
2176     if (Value >= 256 && Value <= 0xffff)
2177       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2178     else if (Value > 0xffff && Value <= 0xffffff)
2179       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2180     else if (Value > 0xffffff)
2181       Value = (Value >> 24) | 0x600;
2182     Inst.addOperand(MCOperand::CreateImm(Value));
2183   }
2184 
2185   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2186     assert(N == 1 && "Invalid number of operands!");
2187     // The immediate encodes the type of constant as well as the value.
2188     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2189     unsigned Value = ~CE->getValue();
2190     if (Value >= 256 && Value <= 0xffff)
2191       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2192     else if (Value > 0xffff && Value <= 0xffffff)
2193       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2194     else if (Value > 0xffffff)
2195       Value = (Value >> 24) | 0x600;
2196     Inst.addOperand(MCOperand::CreateImm(Value));
2197   }
2198 
2199   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2200     assert(N == 1 && "Invalid number of operands!");
2201     // The immediate encodes the type of constant as well as the value.
2202     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2203     uint64_t Value = CE->getValue();
2204     unsigned Imm = 0;
2205     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2206       Imm |= (Value & 1) << i;
2207     }
2208     Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2209   }
2210 
2211   virtual void print(raw_ostream &OS) const;
2212 
2213   static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2214     ARMOperand *Op = new ARMOperand(k_ITCondMask);
2215     Op->ITMask.Mask = Mask;
2216     Op->StartLoc = S;
2217     Op->EndLoc = S;
2218     return Op;
2219   }
2220 
2221   static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2222     ARMOperand *Op = new ARMOperand(k_CondCode);
2223     Op->CC.Val = CC;
2224     Op->StartLoc = S;
2225     Op->EndLoc = S;
2226     return Op;
2227   }
2228 
2229   static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2230     ARMOperand *Op = new ARMOperand(k_CoprocNum);
2231     Op->Cop.Val = CopVal;
2232     Op->StartLoc = S;
2233     Op->EndLoc = S;
2234     return Op;
2235   }
2236 
2237   static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2238     ARMOperand *Op = new ARMOperand(k_CoprocReg);
2239     Op->Cop.Val = CopVal;
2240     Op->StartLoc = S;
2241     Op->EndLoc = S;
2242     return Op;
2243   }
2244 
2245   static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2246     ARMOperand *Op = new ARMOperand(k_CoprocOption);
2247     Op->Cop.Val = Val;
2248     Op->StartLoc = S;
2249     Op->EndLoc = E;
2250     return Op;
2251   }
2252 
2253   static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2254     ARMOperand *Op = new ARMOperand(k_CCOut);
2255     Op->Reg.RegNum = RegNum;
2256     Op->StartLoc = S;
2257     Op->EndLoc = S;
2258     return Op;
2259   }
2260 
2261   static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2262     ARMOperand *Op = new ARMOperand(k_Token);
2263     Op->Tok.Data = Str.data();
2264     Op->Tok.Length = Str.size();
2265     Op->StartLoc = S;
2266     Op->EndLoc = S;
2267     return Op;
2268   }
2269 
2270   static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2271     ARMOperand *Op = new ARMOperand(k_Register);
2272     Op->Reg.RegNum = RegNum;
2273     Op->StartLoc = S;
2274     Op->EndLoc = E;
2275     return Op;
2276   }
2277 
2278   static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2279                                            unsigned SrcReg,
2280                                            unsigned ShiftReg,
2281                                            unsigned ShiftImm,
2282                                            SMLoc S, SMLoc E) {
2283     ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2284     Op->RegShiftedReg.ShiftTy = ShTy;
2285     Op->RegShiftedReg.SrcReg = SrcReg;
2286     Op->RegShiftedReg.ShiftReg = ShiftReg;
2287     Op->RegShiftedReg.ShiftImm = ShiftImm;
2288     Op->StartLoc = S;
2289     Op->EndLoc = E;
2290     return Op;
2291   }
2292 
2293   static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2294                                             unsigned SrcReg,
2295                                             unsigned ShiftImm,
2296                                             SMLoc S, SMLoc E) {
2297     ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2298     Op->RegShiftedImm.ShiftTy = ShTy;
2299     Op->RegShiftedImm.SrcReg = SrcReg;
2300     Op->RegShiftedImm.ShiftImm = ShiftImm;
2301     Op->StartLoc = S;
2302     Op->EndLoc = E;
2303     return Op;
2304   }
2305 
2306   static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2307                                    SMLoc S, SMLoc E) {
2308     ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2309     Op->ShifterImm.isASR = isASR;
2310     Op->ShifterImm.Imm = Imm;
2311     Op->StartLoc = S;
2312     Op->EndLoc = E;
2313     return Op;
2314   }
2315 
2316   static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2317     ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2318     Op->RotImm.Imm = Imm;
2319     Op->StartLoc = S;
2320     Op->EndLoc = E;
2321     return Op;
2322   }
2323 
2324   static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2325                                     SMLoc S, SMLoc E) {
2326     ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2327     Op->Bitfield.LSB = LSB;
2328     Op->Bitfield.Width = Width;
2329     Op->StartLoc = S;
2330     Op->EndLoc = E;
2331     return Op;
2332   }
2333 
2334   static ARMOperand *
2335   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2336                 SMLoc StartLoc, SMLoc EndLoc) {
2337     assert (Regs.size() > 0 && "RegList contains no registers?");
2338     KindTy Kind = k_RegisterList;
2339 
2340     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2341       Kind = k_DPRRegisterList;
2342     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2343              contains(Regs.front().second))
2344       Kind = k_SPRRegisterList;
2345 
2346     // Sort based on the register encoding values.
2347     array_pod_sort(Regs.begin(), Regs.end());
2348 
2349     ARMOperand *Op = new ARMOperand(Kind);
2350     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2351            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2352       Op->Registers.push_back(I->second);
2353     Op->StartLoc = StartLoc;
2354     Op->EndLoc = EndLoc;
2355     return Op;
2356   }
2357 
2358   static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2359                                       bool isDoubleSpaced, SMLoc S, SMLoc E) {
2360     ARMOperand *Op = new ARMOperand(k_VectorList);
2361     Op->VectorList.RegNum = RegNum;
2362     Op->VectorList.Count = Count;
2363     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2364     Op->StartLoc = S;
2365     Op->EndLoc = E;
2366     return Op;
2367   }
2368 
2369   static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2370                                               bool isDoubleSpaced,
2371                                               SMLoc S, SMLoc E) {
2372     ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2373     Op->VectorList.RegNum = RegNum;
2374     Op->VectorList.Count = Count;
2375     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2376     Op->StartLoc = S;
2377     Op->EndLoc = E;
2378     return Op;
2379   }
2380 
2381   static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2382                                              unsigned Index,
2383                                              bool isDoubleSpaced,
2384                                              SMLoc S, SMLoc E) {
2385     ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2386     Op->VectorList.RegNum = RegNum;
2387     Op->VectorList.Count = Count;
2388     Op->VectorList.LaneIndex = Index;
2389     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2390     Op->StartLoc = S;
2391     Op->EndLoc = E;
2392     return Op;
2393   }
2394 
2395   static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2396                                        MCContext &Ctx) {
2397     ARMOperand *Op = new ARMOperand(k_VectorIndex);
2398     Op->VectorIndex.Val = Idx;
2399     Op->StartLoc = S;
2400     Op->EndLoc = E;
2401     return Op;
2402   }
2403 
2404   static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2405     ARMOperand *Op = new ARMOperand(k_Immediate);
2406     Op->Imm.Val = Val;
2407     Op->StartLoc = S;
2408     Op->EndLoc = E;
2409     return Op;
2410   }
2411 
2412   static ARMOperand *CreateMem(unsigned BaseRegNum,
2413                                const MCConstantExpr *OffsetImm,
2414                                unsigned OffsetRegNum,
2415                                ARM_AM::ShiftOpc ShiftType,
2416                                unsigned ShiftImm,
2417                                unsigned Alignment,
2418                                bool isNegative,
2419                                SMLoc S, SMLoc E) {
2420     ARMOperand *Op = new ARMOperand(k_Memory);
2421     Op->Memory.BaseRegNum = BaseRegNum;
2422     Op->Memory.OffsetImm = OffsetImm;
2423     Op->Memory.OffsetRegNum = OffsetRegNum;
2424     Op->Memory.ShiftType = ShiftType;
2425     Op->Memory.ShiftImm = ShiftImm;
2426     Op->Memory.Alignment = Alignment;
2427     Op->Memory.isNegative = isNegative;
2428     Op->StartLoc = S;
2429     Op->EndLoc = E;
2430     return Op;
2431   }
2432 
2433   static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2434                                       ARM_AM::ShiftOpc ShiftTy,
2435                                       unsigned ShiftImm,
2436                                       SMLoc S, SMLoc E) {
2437     ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2438     Op->PostIdxReg.RegNum = RegNum;
2439     Op->PostIdxReg.isAdd = isAdd;
2440     Op->PostIdxReg.ShiftTy = ShiftTy;
2441     Op->PostIdxReg.ShiftImm = ShiftImm;
2442     Op->StartLoc = S;
2443     Op->EndLoc = E;
2444     return Op;
2445   }
2446 
2447   static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2448     ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2449     Op->MBOpt.Val = Opt;
2450     Op->StartLoc = S;
2451     Op->EndLoc = S;
2452     return Op;
2453   }
2454 
2455   static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2456                                               SMLoc S) {
2457     ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2458     Op->ISBOpt.Val = Opt;
2459     Op->StartLoc = S;
2460     Op->EndLoc = S;
2461     return Op;
2462   }
2463 
2464   static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2465     ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2466     Op->IFlags.Val = IFlags;
2467     Op->StartLoc = S;
2468     Op->EndLoc = S;
2469     return Op;
2470   }
2471 
2472   static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2473     ARMOperand *Op = new ARMOperand(k_MSRMask);
2474     Op->MMask.Val = MMask;
2475     Op->StartLoc = S;
2476     Op->EndLoc = S;
2477     return Op;
2478   }
2479 };
2480 
2481 } // end anonymous namespace.
2482 
2483 void ARMOperand::print(raw_ostream &OS) const {
2484   switch (Kind) {
2485   case k_CondCode:
2486     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2487     break;
2488   case k_CCOut:
2489     OS << "<ccout " << getReg() << ">";
2490     break;
2491   case k_ITCondMask: {
2492     static const char *const MaskStr[] = {
2493       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2494       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2495     };
2496     assert((ITMask.Mask & 0xf) == ITMask.Mask);
2497     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2498     break;
2499   }
2500   case k_CoprocNum:
2501     OS << "<coprocessor number: " << getCoproc() << ">";
2502     break;
2503   case k_CoprocReg:
2504     OS << "<coprocessor register: " << getCoproc() << ">";
2505     break;
2506   case k_CoprocOption:
2507     OS << "<coprocessor option: " << CoprocOption.Val << ">";
2508     break;
2509   case k_MSRMask:
2510     OS << "<mask: " << getMSRMask() << ">";
2511     break;
2512   case k_Immediate:
2513     getImm()->print(OS);
2514     break;
2515   case k_MemBarrierOpt:
2516     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2517     break;
2518   case k_InstSyncBarrierOpt:
2519     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2520     break;
2521   case k_Memory:
2522     OS << "<memory "
2523        << " base:" << Memory.BaseRegNum;
2524     OS << ">";
2525     break;
2526   case k_PostIndexRegister:
2527     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2528        << PostIdxReg.RegNum;
2529     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2530       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2531          << PostIdxReg.ShiftImm;
2532     OS << ">";
2533     break;
2534   case k_ProcIFlags: {
2535     OS << "<ARM_PROC::";
2536     unsigned IFlags = getProcIFlags();
2537     for (int i=2; i >= 0; --i)
2538       if (IFlags & (1 << i))
2539         OS << ARM_PROC::IFlagsToString(1 << i);
2540     OS << ">";
2541     break;
2542   }
2543   case k_Register:
2544     OS << "<register " << getReg() << ">";
2545     break;
2546   case k_ShifterImmediate:
2547     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2548        << " #" << ShifterImm.Imm << ">";
2549     break;
2550   case k_ShiftedRegister:
2551     OS << "<so_reg_reg "
2552        << RegShiftedReg.SrcReg << " "
2553        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2554        << " " << RegShiftedReg.ShiftReg << ">";
2555     break;
2556   case k_ShiftedImmediate:
2557     OS << "<so_reg_imm "
2558        << RegShiftedImm.SrcReg << " "
2559        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2560        << " #" << RegShiftedImm.ShiftImm << ">";
2561     break;
2562   case k_RotateImmediate:
2563     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2564     break;
2565   case k_BitfieldDescriptor:
2566     OS << "<bitfield " << "lsb: " << Bitfield.LSB
2567        << ", width: " << Bitfield.Width << ">";
2568     break;
2569   case k_RegisterList:
2570   case k_DPRRegisterList:
2571   case k_SPRRegisterList: {
2572     OS << "<register_list ";
2573 
2574     const SmallVectorImpl<unsigned> &RegList = getRegList();
2575     for (SmallVectorImpl<unsigned>::const_iterator
2576            I = RegList.begin(), E = RegList.end(); I != E; ) {
2577       OS << *I;
2578       if (++I < E) OS << ", ";
2579     }
2580 
2581     OS << ">";
2582     break;
2583   }
2584   case k_VectorList:
2585     OS << "<vector_list " << VectorList.Count << " * "
2586        << VectorList.RegNum << ">";
2587     break;
2588   case k_VectorListAllLanes:
2589     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2590        << VectorList.RegNum << ">";
2591     break;
2592   case k_VectorListIndexed:
2593     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2594        << VectorList.Count << " * " << VectorList.RegNum << ">";
2595     break;
2596   case k_Token:
2597     OS << "'" << getToken() << "'";
2598     break;
2599   case k_VectorIndex:
2600     OS << "<vectorindex " << getVectorIndex() << ">";
2601     break;
2602   }
2603 }
2604 
2605 /// @name Auto-generated Match Functions
2606 /// {
2607 
2608 static unsigned MatchRegisterName(StringRef Name);
2609 
2610 /// }
2611 
2612 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2613                                  SMLoc &StartLoc, SMLoc &EndLoc) {
2614   StartLoc = Parser.getTok().getLoc();
2615   EndLoc = Parser.getTok().getEndLoc();
2616   RegNo = tryParseRegister();
2617 
2618   return (RegNo == (unsigned)-1);
2619 }
2620 
2621 /// Try to parse a register name.  The token must be an Identifier when called,
2622 /// and if it is a register name the token is eaten and the register number is
2623 /// returned.  Otherwise return -1.
2624 ///
2625 int ARMAsmParser::tryParseRegister() {
2626   const AsmToken &Tok = Parser.getTok();
2627   if (Tok.isNot(AsmToken::Identifier)) return -1;
2628 
2629   std::string lowerCase = Tok.getString().lower();
2630   unsigned RegNum = MatchRegisterName(lowerCase);
2631   if (!RegNum) {
2632     RegNum = StringSwitch<unsigned>(lowerCase)
2633       .Case("r13", ARM::SP)
2634       .Case("r14", ARM::LR)
2635       .Case("r15", ARM::PC)
2636       .Case("ip", ARM::R12)
2637       // Additional register name aliases for 'gas' compatibility.
2638       .Case("a1", ARM::R0)
2639       .Case("a2", ARM::R1)
2640       .Case("a3", ARM::R2)
2641       .Case("a4", ARM::R3)
2642       .Case("v1", ARM::R4)
2643       .Case("v2", ARM::R5)
2644       .Case("v3", ARM::R6)
2645       .Case("v4", ARM::R7)
2646       .Case("v5", ARM::R8)
2647       .Case("v6", ARM::R9)
2648       .Case("v7", ARM::R10)
2649       .Case("v8", ARM::R11)
2650       .Case("sb", ARM::R9)
2651       .Case("sl", ARM::R10)
2652       .Case("fp", ARM::R11)
2653       .Default(0);
2654   }
2655   if (!RegNum) {
2656     // Check for aliases registered via .req. Canonicalize to lower case.
2657     // That's more consistent since register names are case insensitive, and
2658     // it's how the original entry was passed in from MC/MCParser/AsmParser.
2659     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2660     // If no match, return failure.
2661     if (Entry == RegisterReqs.end())
2662       return -1;
2663     Parser.Lex(); // Eat identifier token.
2664     return Entry->getValue();
2665   }
2666 
2667   Parser.Lex(); // Eat identifier token.
2668 
2669   return RegNum;
2670 }
2671 
2672 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2673 // If a recoverable error occurs, return 1. If an irrecoverable error
2674 // occurs, return -1. An irrecoverable error is one where tokens have been
2675 // consumed in the process of trying to parse the shifter (i.e., when it is
2676 // indeed a shifter operand, but malformed).
2677 int ARMAsmParser::tryParseShiftRegister(
2678                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2679   SMLoc S = Parser.getTok().getLoc();
2680   const AsmToken &Tok = Parser.getTok();
2681   assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2682 
2683   std::string lowerCase = Tok.getString().lower();
2684   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2685       .Case("asl", ARM_AM::lsl)
2686       .Case("lsl", ARM_AM::lsl)
2687       .Case("lsr", ARM_AM::lsr)
2688       .Case("asr", ARM_AM::asr)
2689       .Case("ror", ARM_AM::ror)
2690       .Case("rrx", ARM_AM::rrx)
2691       .Default(ARM_AM::no_shift);
2692 
2693   if (ShiftTy == ARM_AM::no_shift)
2694     return 1;
2695 
2696   Parser.Lex(); // Eat the operator.
2697 
2698   // The source register for the shift has already been added to the
2699   // operand list, so we need to pop it off and combine it into the shifted
2700   // register operand instead.
2701   OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2702   if (!PrevOp->isReg())
2703     return Error(PrevOp->getStartLoc(), "shift must be of a register");
2704   int SrcReg = PrevOp->getReg();
2705 
2706   SMLoc EndLoc;
2707   int64_t Imm = 0;
2708   int ShiftReg = 0;
2709   if (ShiftTy == ARM_AM::rrx) {
2710     // RRX Doesn't have an explicit shift amount. The encoder expects
2711     // the shift register to be the same as the source register. Seems odd,
2712     // but OK.
2713     ShiftReg = SrcReg;
2714   } else {
2715     // Figure out if this is shifted by a constant or a register (for non-RRX).
2716     if (Parser.getTok().is(AsmToken::Hash) ||
2717         Parser.getTok().is(AsmToken::Dollar)) {
2718       Parser.Lex(); // Eat hash.
2719       SMLoc ImmLoc = Parser.getTok().getLoc();
2720       const MCExpr *ShiftExpr = 0;
2721       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2722         Error(ImmLoc, "invalid immediate shift value");
2723         return -1;
2724       }
2725       // The expression must be evaluatable as an immediate.
2726       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2727       if (!CE) {
2728         Error(ImmLoc, "invalid immediate shift value");
2729         return -1;
2730       }
2731       // Range check the immediate.
2732       // lsl, ror: 0 <= imm <= 31
2733       // lsr, asr: 0 <= imm <= 32
2734       Imm = CE->getValue();
2735       if (Imm < 0 ||
2736           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2737           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2738         Error(ImmLoc, "immediate shift value out of range");
2739         return -1;
2740       }
2741       // shift by zero is a nop. Always send it through as lsl.
2742       // ('as' compatibility)
2743       if (Imm == 0)
2744         ShiftTy = ARM_AM::lsl;
2745     } else if (Parser.getTok().is(AsmToken::Identifier)) {
2746       SMLoc L = Parser.getTok().getLoc();
2747       EndLoc = Parser.getTok().getEndLoc();
2748       ShiftReg = tryParseRegister();
2749       if (ShiftReg == -1) {
2750         Error (L, "expected immediate or register in shift operand");
2751         return -1;
2752       }
2753     } else {
2754       Error (Parser.getTok().getLoc(),
2755                     "expected immediate or register in shift operand");
2756       return -1;
2757     }
2758   }
2759 
2760   if (ShiftReg && ShiftTy != ARM_AM::rrx)
2761     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2762                                                          ShiftReg, Imm,
2763                                                          S, EndLoc));
2764   else
2765     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2766                                                           S, EndLoc));
2767 
2768   return 0;
2769 }
2770 
2771 
2772 /// Try to parse a register name.  The token must be an Identifier when called.
2773 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2774 /// if there is a "writeback". 'true' if it's not a register.
2775 ///
2776 /// TODO this is likely to change to allow different register types and or to
2777 /// parse for a specific register type.
2778 bool ARMAsmParser::
2779 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2780   const AsmToken &RegTok = Parser.getTok();
2781   int RegNo = tryParseRegister();
2782   if (RegNo == -1)
2783     return true;
2784 
2785   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2786                                            RegTok.getEndLoc()));
2787 
2788   const AsmToken &ExclaimTok = Parser.getTok();
2789   if (ExclaimTok.is(AsmToken::Exclaim)) {
2790     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2791                                                ExclaimTok.getLoc()));
2792     Parser.Lex(); // Eat exclaim token
2793     return false;
2794   }
2795 
2796   // Also check for an index operand. This is only legal for vector registers,
2797   // but that'll get caught OK in operand matching, so we don't need to
2798   // explicitly filter everything else out here.
2799   if (Parser.getTok().is(AsmToken::LBrac)) {
2800     SMLoc SIdx = Parser.getTok().getLoc();
2801     Parser.Lex(); // Eat left bracket token.
2802 
2803     const MCExpr *ImmVal;
2804     if (getParser().parseExpression(ImmVal))
2805       return true;
2806     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2807     if (!MCE)
2808       return TokError("immediate value expected for vector index");
2809 
2810     if (Parser.getTok().isNot(AsmToken::RBrac))
2811       return Error(Parser.getTok().getLoc(), "']' expected");
2812 
2813     SMLoc E = Parser.getTok().getEndLoc();
2814     Parser.Lex(); // Eat right bracket token.
2815 
2816     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2817                                                      SIdx, E,
2818                                                      getContext()));
2819   }
2820 
2821   return false;
2822 }
2823 
2824 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2825 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2826 /// "c5", ...
2827 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2828   // Use the same layout as the tablegen'erated register name matcher. Ugly,
2829   // but efficient.
2830   switch (Name.size()) {
2831   default: return -1;
2832   case 2:
2833     if (Name[0] != CoprocOp)
2834       return -1;
2835     switch (Name[1]) {
2836     default:  return -1;
2837     case '0': return 0;
2838     case '1': return 1;
2839     case '2': return 2;
2840     case '3': return 3;
2841     case '4': return 4;
2842     case '5': return 5;
2843     case '6': return 6;
2844     case '7': return 7;
2845     case '8': return 8;
2846     case '9': return 9;
2847     }
2848   case 3:
2849     if (Name[0] != CoprocOp || Name[1] != '1')
2850       return -1;
2851     switch (Name[2]) {
2852     default:  return -1;
2853     case '0': return 10;
2854     case '1': return 11;
2855     case '2': return 12;
2856     case '3': return 13;
2857     case '4': return 14;
2858     case '5': return 15;
2859     }
2860   }
2861 }
2862 
2863 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2864 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2865 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2866   SMLoc S = Parser.getTok().getLoc();
2867   const AsmToken &Tok = Parser.getTok();
2868   if (!Tok.is(AsmToken::Identifier))
2869     return MatchOperand_NoMatch;
2870   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2871     .Case("eq", ARMCC::EQ)
2872     .Case("ne", ARMCC::NE)
2873     .Case("hs", ARMCC::HS)
2874     .Case("cs", ARMCC::HS)
2875     .Case("lo", ARMCC::LO)
2876     .Case("cc", ARMCC::LO)
2877     .Case("mi", ARMCC::MI)
2878     .Case("pl", ARMCC::PL)
2879     .Case("vs", ARMCC::VS)
2880     .Case("vc", ARMCC::VC)
2881     .Case("hi", ARMCC::HI)
2882     .Case("ls", ARMCC::LS)
2883     .Case("ge", ARMCC::GE)
2884     .Case("lt", ARMCC::LT)
2885     .Case("gt", ARMCC::GT)
2886     .Case("le", ARMCC::LE)
2887     .Case("al", ARMCC::AL)
2888     .Default(~0U);
2889   if (CC == ~0U)
2890     return MatchOperand_NoMatch;
2891   Parser.Lex(); // Eat the token.
2892 
2893   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2894 
2895   return MatchOperand_Success;
2896 }
2897 
2898 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2899 /// token must be an Identifier when called, and if it is a coprocessor
2900 /// number, the token is eaten and the operand is added to the operand list.
2901 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2902 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2903   SMLoc S = Parser.getTok().getLoc();
2904   const AsmToken &Tok = Parser.getTok();
2905   if (Tok.isNot(AsmToken::Identifier))
2906     return MatchOperand_NoMatch;
2907 
2908   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2909   if (Num == -1)
2910     return MatchOperand_NoMatch;
2911 
2912   Parser.Lex(); // Eat identifier token.
2913   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2914   return MatchOperand_Success;
2915 }
2916 
2917 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2918 /// token must be an Identifier when called, and if it is a coprocessor
2919 /// number, the token is eaten and the operand is added to the operand list.
2920 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2921 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2922   SMLoc S = Parser.getTok().getLoc();
2923   const AsmToken &Tok = Parser.getTok();
2924   if (Tok.isNot(AsmToken::Identifier))
2925     return MatchOperand_NoMatch;
2926 
2927   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2928   if (Reg == -1)
2929     return MatchOperand_NoMatch;
2930 
2931   Parser.Lex(); // Eat identifier token.
2932   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2933   return MatchOperand_Success;
2934 }
2935 
2936 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2937 /// coproc_option : '{' imm0_255 '}'
2938 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2939 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2940   SMLoc S = Parser.getTok().getLoc();
2941 
2942   // If this isn't a '{', this isn't a coprocessor immediate operand.
2943   if (Parser.getTok().isNot(AsmToken::LCurly))
2944     return MatchOperand_NoMatch;
2945   Parser.Lex(); // Eat the '{'
2946 
2947   const MCExpr *Expr;
2948   SMLoc Loc = Parser.getTok().getLoc();
2949   if (getParser().parseExpression(Expr)) {
2950     Error(Loc, "illegal expression");
2951     return MatchOperand_ParseFail;
2952   }
2953   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2954   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2955     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2956     return MatchOperand_ParseFail;
2957   }
2958   int Val = CE->getValue();
2959 
2960   // Check for and consume the closing '}'
2961   if (Parser.getTok().isNot(AsmToken::RCurly))
2962     return MatchOperand_ParseFail;
2963   SMLoc E = Parser.getTok().getEndLoc();
2964   Parser.Lex(); // Eat the '}'
2965 
2966   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2967   return MatchOperand_Success;
2968 }
2969 
2970 // For register list parsing, we need to map from raw GPR register numbering
2971 // to the enumeration values. The enumeration values aren't sorted by
2972 // register number due to our using "sp", "lr" and "pc" as canonical names.
2973 static unsigned getNextRegister(unsigned Reg) {
2974   // If this is a GPR, we need to do it manually, otherwise we can rely
2975   // on the sort ordering of the enumeration since the other reg-classes
2976   // are sane.
2977   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2978     return Reg + 1;
2979   switch(Reg) {
2980   default: llvm_unreachable("Invalid GPR number!");
2981   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2982   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2983   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2984   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2985   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2986   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2987   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2988   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2989   }
2990 }
2991 
2992 // Return the low-subreg of a given Q register.
2993 static unsigned getDRegFromQReg(unsigned QReg) {
2994   switch (QReg) {
2995   default: llvm_unreachable("expected a Q register!");
2996   case ARM::Q0:  return ARM::D0;
2997   case ARM::Q1:  return ARM::D2;
2998   case ARM::Q2:  return ARM::D4;
2999   case ARM::Q3:  return ARM::D6;
3000   case ARM::Q4:  return ARM::D8;
3001   case ARM::Q5:  return ARM::D10;
3002   case ARM::Q6:  return ARM::D12;
3003   case ARM::Q7:  return ARM::D14;
3004   case ARM::Q8:  return ARM::D16;
3005   case ARM::Q9:  return ARM::D18;
3006   case ARM::Q10: return ARM::D20;
3007   case ARM::Q11: return ARM::D22;
3008   case ARM::Q12: return ARM::D24;
3009   case ARM::Q13: return ARM::D26;
3010   case ARM::Q14: return ARM::D28;
3011   case ARM::Q15: return ARM::D30;
3012   }
3013 }
3014 
3015 /// Parse a register list.
3016 bool ARMAsmParser::
3017 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3018   assert(Parser.getTok().is(AsmToken::LCurly) &&
3019          "Token is not a Left Curly Brace");
3020   SMLoc S = Parser.getTok().getLoc();
3021   Parser.Lex(); // Eat '{' token.
3022   SMLoc RegLoc = Parser.getTok().getLoc();
3023 
3024   // Check the first register in the list to see what register class
3025   // this is a list of.
3026   int Reg = tryParseRegister();
3027   if (Reg == -1)
3028     return Error(RegLoc, "register expected");
3029 
3030   // The reglist instructions have at most 16 registers, so reserve
3031   // space for that many.
3032   int EReg = 0;
3033   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3034 
3035   // Allow Q regs and just interpret them as the two D sub-registers.
3036   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3037     Reg = getDRegFromQReg(Reg);
3038     EReg = MRI->getEncodingValue(Reg);
3039     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3040     ++Reg;
3041   }
3042   const MCRegisterClass *RC;
3043   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3044     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3045   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3046     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3047   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3048     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3049   else
3050     return Error(RegLoc, "invalid register in register list");
3051 
3052   // Store the register.
3053   EReg = MRI->getEncodingValue(Reg);
3054   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3055 
3056   // This starts immediately after the first register token in the list,
3057   // so we can see either a comma or a minus (range separator) as a legal
3058   // next token.
3059   while (Parser.getTok().is(AsmToken::Comma) ||
3060          Parser.getTok().is(AsmToken::Minus)) {
3061     if (Parser.getTok().is(AsmToken::Minus)) {
3062       Parser.Lex(); // Eat the minus.
3063       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3064       int EndReg = tryParseRegister();
3065       if (EndReg == -1)
3066         return Error(AfterMinusLoc, "register expected");
3067       // Allow Q regs and just interpret them as the two D sub-registers.
3068       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3069         EndReg = getDRegFromQReg(EndReg) + 1;
3070       // If the register is the same as the start reg, there's nothing
3071       // more to do.
3072       if (Reg == EndReg)
3073         continue;
3074       // The register must be in the same register class as the first.
3075       if (!RC->contains(EndReg))
3076         return Error(AfterMinusLoc, "invalid register in register list");
3077       // Ranges must go from low to high.
3078       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3079         return Error(AfterMinusLoc, "bad range in register list");
3080 
3081       // Add all the registers in the range to the register list.
3082       while (Reg != EndReg) {
3083         Reg = getNextRegister(Reg);
3084         EReg = MRI->getEncodingValue(Reg);
3085         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3086       }
3087       continue;
3088     }
3089     Parser.Lex(); // Eat the comma.
3090     RegLoc = Parser.getTok().getLoc();
3091     int OldReg = Reg;
3092     const AsmToken RegTok = Parser.getTok();
3093     Reg = tryParseRegister();
3094     if (Reg == -1)
3095       return Error(RegLoc, "register expected");
3096     // Allow Q regs and just interpret them as the two D sub-registers.
3097     bool isQReg = false;
3098     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3099       Reg = getDRegFromQReg(Reg);
3100       isQReg = true;
3101     }
3102     // The register must be in the same register class as the first.
3103     if (!RC->contains(Reg))
3104       return Error(RegLoc, "invalid register in register list");
3105     // List must be monotonically increasing.
3106     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3107       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3108         Warning(RegLoc, "register list not in ascending order");
3109       else
3110         return Error(RegLoc, "register list not in ascending order");
3111     }
3112     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3113       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3114               ") in register list");
3115       continue;
3116     }
3117     // VFP register lists must also be contiguous.
3118     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3119         Reg != OldReg + 1)
3120       return Error(RegLoc, "non-contiguous register range");
3121     EReg = MRI->getEncodingValue(Reg);
3122     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3123     if (isQReg) {
3124       EReg = MRI->getEncodingValue(++Reg);
3125       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3126     }
3127   }
3128 
3129   if (Parser.getTok().isNot(AsmToken::RCurly))
3130     return Error(Parser.getTok().getLoc(), "'}' expected");
3131   SMLoc E = Parser.getTok().getEndLoc();
3132   Parser.Lex(); // Eat '}' token.
3133 
3134   // Push the register list operand.
3135   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3136 
3137   // The ARM system instruction variants for LDM/STM have a '^' token here.
3138   if (Parser.getTok().is(AsmToken::Caret)) {
3139     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3140     Parser.Lex(); // Eat '^' token.
3141   }
3142 
3143   return false;
3144 }
3145 
3146 // Helper function to parse the lane index for vector lists.
3147 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3148 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3149   Index = 0; // Always return a defined index value.
3150   if (Parser.getTok().is(AsmToken::LBrac)) {
3151     Parser.Lex(); // Eat the '['.
3152     if (Parser.getTok().is(AsmToken::RBrac)) {
3153       // "Dn[]" is the 'all lanes' syntax.
3154       LaneKind = AllLanes;
3155       EndLoc = Parser.getTok().getEndLoc();
3156       Parser.Lex(); // Eat the ']'.
3157       return MatchOperand_Success;
3158     }
3159 
3160     // There's an optional '#' token here. Normally there wouldn't be, but
3161     // inline assemble puts one in, and it's friendly to accept that.
3162     if (Parser.getTok().is(AsmToken::Hash))
3163       Parser.Lex(); // Eat '#' or '$'.
3164 
3165     const MCExpr *LaneIndex;
3166     SMLoc Loc = Parser.getTok().getLoc();
3167     if (getParser().parseExpression(LaneIndex)) {
3168       Error(Loc, "illegal expression");
3169       return MatchOperand_ParseFail;
3170     }
3171     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3172     if (!CE) {
3173       Error(Loc, "lane index must be empty or an integer");
3174       return MatchOperand_ParseFail;
3175     }
3176     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3177       Error(Parser.getTok().getLoc(), "']' expected");
3178       return MatchOperand_ParseFail;
3179     }
3180     EndLoc = Parser.getTok().getEndLoc();
3181     Parser.Lex(); // Eat the ']'.
3182     int64_t Val = CE->getValue();
3183 
3184     // FIXME: Make this range check context sensitive for .8, .16, .32.
3185     if (Val < 0 || Val > 7) {
3186       Error(Parser.getTok().getLoc(), "lane index out of range");
3187       return MatchOperand_ParseFail;
3188     }
3189     Index = Val;
3190     LaneKind = IndexedLane;
3191     return MatchOperand_Success;
3192   }
3193   LaneKind = NoLanes;
3194   return MatchOperand_Success;
3195 }
3196 
3197 // parse a vector register list
3198 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3199 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3200   VectorLaneTy LaneKind;
3201   unsigned LaneIndex;
3202   SMLoc S = Parser.getTok().getLoc();
3203   // As an extension (to match gas), support a plain D register or Q register
3204   // (without encosing curly braces) as a single or double entry list,
3205   // respectively.
3206   if (Parser.getTok().is(AsmToken::Identifier)) {
3207     SMLoc E = Parser.getTok().getEndLoc();
3208     int Reg = tryParseRegister();
3209     if (Reg == -1)
3210       return MatchOperand_NoMatch;
3211     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3212       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3213       if (Res != MatchOperand_Success)
3214         return Res;
3215       switch (LaneKind) {
3216       case NoLanes:
3217         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3218         break;
3219       case AllLanes:
3220         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3221                                                                 S, E));
3222         break;
3223       case IndexedLane:
3224         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3225                                                                LaneIndex,
3226                                                                false, S, E));
3227         break;
3228       }
3229       return MatchOperand_Success;
3230     }
3231     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3232       Reg = getDRegFromQReg(Reg);
3233       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3234       if (Res != MatchOperand_Success)
3235         return Res;
3236       switch (LaneKind) {
3237       case NoLanes:
3238         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3239                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3240         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3241         break;
3242       case AllLanes:
3243         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3244                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3245         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3246                                                                 S, E));
3247         break;
3248       case IndexedLane:
3249         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3250                                                                LaneIndex,
3251                                                                false, S, E));
3252         break;
3253       }
3254       return MatchOperand_Success;
3255     }
3256     Error(S, "vector register expected");
3257     return MatchOperand_ParseFail;
3258   }
3259 
3260   if (Parser.getTok().isNot(AsmToken::LCurly))
3261     return MatchOperand_NoMatch;
3262 
3263   Parser.Lex(); // Eat '{' token.
3264   SMLoc RegLoc = Parser.getTok().getLoc();
3265 
3266   int Reg = tryParseRegister();
3267   if (Reg == -1) {
3268     Error(RegLoc, "register expected");
3269     return MatchOperand_ParseFail;
3270   }
3271   unsigned Count = 1;
3272   int Spacing = 0;
3273   unsigned FirstReg = Reg;
3274   // The list is of D registers, but we also allow Q regs and just interpret
3275   // them as the two D sub-registers.
3276   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3277     FirstReg = Reg = getDRegFromQReg(Reg);
3278     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3279                  // it's ambiguous with four-register single spaced.
3280     ++Reg;
3281     ++Count;
3282   }
3283 
3284   SMLoc E;
3285   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3286     return MatchOperand_ParseFail;
3287 
3288   while (Parser.getTok().is(AsmToken::Comma) ||
3289          Parser.getTok().is(AsmToken::Minus)) {
3290     if (Parser.getTok().is(AsmToken::Minus)) {
3291       if (!Spacing)
3292         Spacing = 1; // Register range implies a single spaced list.
3293       else if (Spacing == 2) {
3294         Error(Parser.getTok().getLoc(),
3295               "sequential registers in double spaced list");
3296         return MatchOperand_ParseFail;
3297       }
3298       Parser.Lex(); // Eat the minus.
3299       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3300       int EndReg = tryParseRegister();
3301       if (EndReg == -1) {
3302         Error(AfterMinusLoc, "register expected");
3303         return MatchOperand_ParseFail;
3304       }
3305       // Allow Q regs and just interpret them as the two D sub-registers.
3306       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3307         EndReg = getDRegFromQReg(EndReg) + 1;
3308       // If the register is the same as the start reg, there's nothing
3309       // more to do.
3310       if (Reg == EndReg)
3311         continue;
3312       // The register must be in the same register class as the first.
3313       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3314         Error(AfterMinusLoc, "invalid register in register list");
3315         return MatchOperand_ParseFail;
3316       }
3317       // Ranges must go from low to high.
3318       if (Reg > EndReg) {
3319         Error(AfterMinusLoc, "bad range in register list");
3320         return MatchOperand_ParseFail;
3321       }
3322       // Parse the lane specifier if present.
3323       VectorLaneTy NextLaneKind;
3324       unsigned NextLaneIndex;
3325       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3326           MatchOperand_Success)
3327         return MatchOperand_ParseFail;
3328       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3329         Error(AfterMinusLoc, "mismatched lane index in register list");
3330         return MatchOperand_ParseFail;
3331       }
3332 
3333       // Add all the registers in the range to the register list.
3334       Count += EndReg - Reg;
3335       Reg = EndReg;
3336       continue;
3337     }
3338     Parser.Lex(); // Eat the comma.
3339     RegLoc = Parser.getTok().getLoc();
3340     int OldReg = Reg;
3341     Reg = tryParseRegister();
3342     if (Reg == -1) {
3343       Error(RegLoc, "register expected");
3344       return MatchOperand_ParseFail;
3345     }
3346     // vector register lists must be contiguous.
3347     // It's OK to use the enumeration values directly here rather, as the
3348     // VFP register classes have the enum sorted properly.
3349     //
3350     // The list is of D registers, but we also allow Q regs and just interpret
3351     // them as the two D sub-registers.
3352     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3353       if (!Spacing)
3354         Spacing = 1; // Register range implies a single spaced list.
3355       else if (Spacing == 2) {
3356         Error(RegLoc,
3357               "invalid register in double-spaced list (must be 'D' register')");
3358         return MatchOperand_ParseFail;
3359       }
3360       Reg = getDRegFromQReg(Reg);
3361       if (Reg != OldReg + 1) {
3362         Error(RegLoc, "non-contiguous register range");
3363         return MatchOperand_ParseFail;
3364       }
3365       ++Reg;
3366       Count += 2;
3367       // Parse the lane specifier if present.
3368       VectorLaneTy NextLaneKind;
3369       unsigned NextLaneIndex;
3370       SMLoc LaneLoc = Parser.getTok().getLoc();
3371       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3372           MatchOperand_Success)
3373         return MatchOperand_ParseFail;
3374       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3375         Error(LaneLoc, "mismatched lane index in register list");
3376         return MatchOperand_ParseFail;
3377       }
3378       continue;
3379     }
3380     // Normal D register.
3381     // Figure out the register spacing (single or double) of the list if
3382     // we don't know it already.
3383     if (!Spacing)
3384       Spacing = 1 + (Reg == OldReg + 2);
3385 
3386     // Just check that it's contiguous and keep going.
3387     if (Reg != OldReg + Spacing) {
3388       Error(RegLoc, "non-contiguous register range");
3389       return MatchOperand_ParseFail;
3390     }
3391     ++Count;
3392     // Parse the lane specifier if present.
3393     VectorLaneTy NextLaneKind;
3394     unsigned NextLaneIndex;
3395     SMLoc EndLoc = Parser.getTok().getLoc();
3396     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3397       return MatchOperand_ParseFail;
3398     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3399       Error(EndLoc, "mismatched lane index in register list");
3400       return MatchOperand_ParseFail;
3401     }
3402   }
3403 
3404   if (Parser.getTok().isNot(AsmToken::RCurly)) {
3405     Error(Parser.getTok().getLoc(), "'}' expected");
3406     return MatchOperand_ParseFail;
3407   }
3408   E = Parser.getTok().getEndLoc();
3409   Parser.Lex(); // Eat '}' token.
3410 
3411   switch (LaneKind) {
3412   case NoLanes:
3413     // Two-register operands have been converted to the
3414     // composite register classes.
3415     if (Count == 2) {
3416       const MCRegisterClass *RC = (Spacing == 1) ?
3417         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3418         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3419       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3420     }
3421 
3422     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3423                                                     (Spacing == 2), S, E));
3424     break;
3425   case AllLanes:
3426     // Two-register operands have been converted to the
3427     // composite register classes.
3428     if (Count == 2) {
3429       const MCRegisterClass *RC = (Spacing == 1) ?
3430         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3431         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3432       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3433     }
3434     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3435                                                             (Spacing == 2),
3436                                                             S, E));
3437     break;
3438   case IndexedLane:
3439     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3440                                                            LaneIndex,
3441                                                            (Spacing == 2),
3442                                                            S, E));
3443     break;
3444   }
3445   return MatchOperand_Success;
3446 }
3447 
3448 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3449 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3450 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3451   SMLoc S = Parser.getTok().getLoc();
3452   const AsmToken &Tok = Parser.getTok();
3453   unsigned Opt;
3454 
3455   if (Tok.is(AsmToken::Identifier)) {
3456     StringRef OptStr = Tok.getString();
3457 
3458     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3459       .Case("sy",    ARM_MB::SY)
3460       .Case("st",    ARM_MB::ST)
3461       .Case("sh",    ARM_MB::ISH)
3462       .Case("ish",   ARM_MB::ISH)
3463       .Case("shst",  ARM_MB::ISHST)
3464       .Case("ishst", ARM_MB::ISHST)
3465       .Case("nsh",   ARM_MB::NSH)
3466       .Case("un",    ARM_MB::NSH)
3467       .Case("nshst", ARM_MB::NSHST)
3468       .Case("unst",  ARM_MB::NSHST)
3469       .Case("osh",   ARM_MB::OSH)
3470       .Case("oshst", ARM_MB::OSHST)
3471       .Default(~0U);
3472 
3473     if (Opt == ~0U)
3474       return MatchOperand_NoMatch;
3475 
3476     Parser.Lex(); // Eat identifier token.
3477   } else if (Tok.is(AsmToken::Hash) ||
3478              Tok.is(AsmToken::Dollar) ||
3479              Tok.is(AsmToken::Integer)) {
3480     if (Parser.getTok().isNot(AsmToken::Integer))
3481       Parser.Lex(); // Eat '#' or '$'.
3482     SMLoc Loc = Parser.getTok().getLoc();
3483 
3484     const MCExpr *MemBarrierID;
3485     if (getParser().parseExpression(MemBarrierID)) {
3486       Error(Loc, "illegal expression");
3487       return MatchOperand_ParseFail;
3488     }
3489 
3490     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3491     if (!CE) {
3492       Error(Loc, "constant expression expected");
3493       return MatchOperand_ParseFail;
3494     }
3495 
3496     int Val = CE->getValue();
3497     if (Val & ~0xf) {
3498       Error(Loc, "immediate value out of range");
3499       return MatchOperand_ParseFail;
3500     }
3501 
3502     Opt = ARM_MB::RESERVED_0 + Val;
3503   } else
3504     return MatchOperand_ParseFail;
3505 
3506   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3507   return MatchOperand_Success;
3508 }
3509 
3510 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3511 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3512 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3513   SMLoc S = Parser.getTok().getLoc();
3514   const AsmToken &Tok = Parser.getTok();
3515   unsigned Opt;
3516 
3517   if (Tok.is(AsmToken::Identifier)) {
3518     StringRef OptStr = Tok.getString();
3519 
3520     if (OptStr.lower() == "sy")
3521       Opt = ARM_ISB::SY;
3522     else
3523       return MatchOperand_NoMatch;
3524 
3525     Parser.Lex(); // Eat identifier token.
3526   } else if (Tok.is(AsmToken::Hash) ||
3527              Tok.is(AsmToken::Dollar) ||
3528              Tok.is(AsmToken::Integer)) {
3529     if (Parser.getTok().isNot(AsmToken::Integer))
3530       Parser.Lex(); // Eat '#' or '$'.
3531     SMLoc Loc = Parser.getTok().getLoc();
3532 
3533     const MCExpr *ISBarrierID;
3534     if (getParser().parseExpression(ISBarrierID)) {
3535       Error(Loc, "illegal expression");
3536       return MatchOperand_ParseFail;
3537     }
3538 
3539     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3540     if (!CE) {
3541       Error(Loc, "constant expression expected");
3542       return MatchOperand_ParseFail;
3543     }
3544 
3545     int Val = CE->getValue();
3546     if (Val & ~0xf) {
3547       Error(Loc, "immediate value out of range");
3548       return MatchOperand_ParseFail;
3549     }
3550 
3551     Opt = ARM_ISB::RESERVED_0 + Val;
3552   } else
3553     return MatchOperand_ParseFail;
3554 
3555   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3556           (ARM_ISB::InstSyncBOpt)Opt, S));
3557   return MatchOperand_Success;
3558 }
3559 
3560 
3561 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3562 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3563 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3564   SMLoc S = Parser.getTok().getLoc();
3565   const AsmToken &Tok = Parser.getTok();
3566   if (!Tok.is(AsmToken::Identifier))
3567     return MatchOperand_NoMatch;
3568   StringRef IFlagsStr = Tok.getString();
3569 
3570   // An iflags string of "none" is interpreted to mean that none of the AIF
3571   // bits are set.  Not a terribly useful instruction, but a valid encoding.
3572   unsigned IFlags = 0;
3573   if (IFlagsStr != "none") {
3574         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3575       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3576         .Case("a", ARM_PROC::A)
3577         .Case("i", ARM_PROC::I)
3578         .Case("f", ARM_PROC::F)
3579         .Default(~0U);
3580 
3581       // If some specific iflag is already set, it means that some letter is
3582       // present more than once, this is not acceptable.
3583       if (Flag == ~0U || (IFlags & Flag))
3584         return MatchOperand_NoMatch;
3585 
3586       IFlags |= Flag;
3587     }
3588   }
3589 
3590   Parser.Lex(); // Eat identifier token.
3591   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3592   return MatchOperand_Success;
3593 }
3594 
3595 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3596 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3597 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3598   SMLoc S = Parser.getTok().getLoc();
3599   const AsmToken &Tok = Parser.getTok();
3600   if (!Tok.is(AsmToken::Identifier))
3601     return MatchOperand_NoMatch;
3602   StringRef Mask = Tok.getString();
3603 
3604   if (isMClass()) {
3605     // See ARMv6-M 10.1.1
3606     std::string Name = Mask.lower();
3607     unsigned FlagsVal = StringSwitch<unsigned>(Name)
3608       // Note: in the documentation:
3609       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3610       //  for MSR APSR_nzcvq.
3611       // but we do make it an alias here.  This is so to get the "mask encoding"
3612       // bits correct on MSR APSR writes.
3613       //
3614       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3615       // should really only be allowed when writing a special register.  Note
3616       // they get dropped in the MRS instruction reading a special register as
3617       // the SYSm field is only 8 bits.
3618       //
3619       // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3620       // includes the DSP extension but that is not checked.
3621       .Case("apsr", 0x800)
3622       .Case("apsr_nzcvq", 0x800)
3623       .Case("apsr_g", 0x400)
3624       .Case("apsr_nzcvqg", 0xc00)
3625       .Case("iapsr", 0x801)
3626       .Case("iapsr_nzcvq", 0x801)
3627       .Case("iapsr_g", 0x401)
3628       .Case("iapsr_nzcvqg", 0xc01)
3629       .Case("eapsr", 0x802)
3630       .Case("eapsr_nzcvq", 0x802)
3631       .Case("eapsr_g", 0x402)
3632       .Case("eapsr_nzcvqg", 0xc02)
3633       .Case("xpsr", 0x803)
3634       .Case("xpsr_nzcvq", 0x803)
3635       .Case("xpsr_g", 0x403)
3636       .Case("xpsr_nzcvqg", 0xc03)
3637       .Case("ipsr", 0x805)
3638       .Case("epsr", 0x806)
3639       .Case("iepsr", 0x807)
3640       .Case("msp", 0x808)
3641       .Case("psp", 0x809)
3642       .Case("primask", 0x810)
3643       .Case("basepri", 0x811)
3644       .Case("basepri_max", 0x812)
3645       .Case("faultmask", 0x813)
3646       .Case("control", 0x814)
3647       .Default(~0U);
3648 
3649     if (FlagsVal == ~0U)
3650       return MatchOperand_NoMatch;
3651 
3652     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3653       // basepri, basepri_max and faultmask only valid for V7m.
3654       return MatchOperand_NoMatch;
3655 
3656     Parser.Lex(); // Eat identifier token.
3657     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3658     return MatchOperand_Success;
3659   }
3660 
3661   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3662   size_t Start = 0, Next = Mask.find('_');
3663   StringRef Flags = "";
3664   std::string SpecReg = Mask.slice(Start, Next).lower();
3665   if (Next != StringRef::npos)
3666     Flags = Mask.slice(Next+1, Mask.size());
3667 
3668   // FlagsVal contains the complete mask:
3669   // 3-0: Mask
3670   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3671   unsigned FlagsVal = 0;
3672 
3673   if (SpecReg == "apsr") {
3674     FlagsVal = StringSwitch<unsigned>(Flags)
3675     .Case("nzcvq",  0x8) // same as CPSR_f
3676     .Case("g",      0x4) // same as CPSR_s
3677     .Case("nzcvqg", 0xc) // same as CPSR_fs
3678     .Default(~0U);
3679 
3680     if (FlagsVal == ~0U) {
3681       if (!Flags.empty())
3682         return MatchOperand_NoMatch;
3683       else
3684         FlagsVal = 8; // No flag
3685     }
3686   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3687     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3688     if (Flags == "all" || Flags == "")
3689       Flags = "fc";
3690     for (int i = 0, e = Flags.size(); i != e; ++i) {
3691       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3692       .Case("c", 1)
3693       .Case("x", 2)
3694       .Case("s", 4)
3695       .Case("f", 8)
3696       .Default(~0U);
3697 
3698       // If some specific flag is already set, it means that some letter is
3699       // present more than once, this is not acceptable.
3700       if (FlagsVal == ~0U || (FlagsVal & Flag))
3701         return MatchOperand_NoMatch;
3702       FlagsVal |= Flag;
3703     }
3704   } else // No match for special register.
3705     return MatchOperand_NoMatch;
3706 
3707   // Special register without flags is NOT equivalent to "fc" flags.
3708   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3709   // two lines would enable gas compatibility at the expense of breaking
3710   // round-tripping.
3711   //
3712   // if (!FlagsVal)
3713   //  FlagsVal = 0x9;
3714 
3715   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3716   if (SpecReg == "spsr")
3717     FlagsVal |= 16;
3718 
3719   Parser.Lex(); // Eat identifier token.
3720   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3721   return MatchOperand_Success;
3722 }
3723 
3724 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3725 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3726             int Low, int High) {
3727   const AsmToken &Tok = Parser.getTok();
3728   if (Tok.isNot(AsmToken::Identifier)) {
3729     Error(Parser.getTok().getLoc(), Op + " operand expected.");
3730     return MatchOperand_ParseFail;
3731   }
3732   StringRef ShiftName = Tok.getString();
3733   std::string LowerOp = Op.lower();
3734   std::string UpperOp = Op.upper();
3735   if (ShiftName != LowerOp && ShiftName != UpperOp) {
3736     Error(Parser.getTok().getLoc(), Op + " operand expected.");
3737     return MatchOperand_ParseFail;
3738   }
3739   Parser.Lex(); // Eat shift type token.
3740 
3741   // There must be a '#' and a shift amount.
3742   if (Parser.getTok().isNot(AsmToken::Hash) &&
3743       Parser.getTok().isNot(AsmToken::Dollar)) {
3744     Error(Parser.getTok().getLoc(), "'#' expected");
3745     return MatchOperand_ParseFail;
3746   }
3747   Parser.Lex(); // Eat hash token.
3748 
3749   const MCExpr *ShiftAmount;
3750   SMLoc Loc = Parser.getTok().getLoc();
3751   SMLoc EndLoc;
3752   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3753     Error(Loc, "illegal expression");
3754     return MatchOperand_ParseFail;
3755   }
3756   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3757   if (!CE) {
3758     Error(Loc, "constant expression expected");
3759     return MatchOperand_ParseFail;
3760   }
3761   int Val = CE->getValue();
3762   if (Val < Low || Val > High) {
3763     Error(Loc, "immediate value out of range");
3764     return MatchOperand_ParseFail;
3765   }
3766 
3767   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3768 
3769   return MatchOperand_Success;
3770 }
3771 
3772 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3773 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3774   const AsmToken &Tok = Parser.getTok();
3775   SMLoc S = Tok.getLoc();
3776   if (Tok.isNot(AsmToken::Identifier)) {
3777     Error(S, "'be' or 'le' operand expected");
3778     return MatchOperand_ParseFail;
3779   }
3780   int Val = StringSwitch<int>(Tok.getString().lower())
3781     .Case("be", 1)
3782     .Case("le", 0)
3783     .Default(-1);
3784   Parser.Lex(); // Eat the token.
3785 
3786   if (Val == -1) {
3787     Error(S, "'be' or 'le' operand expected");
3788     return MatchOperand_ParseFail;
3789   }
3790   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3791                                                                   getContext()),
3792                                            S, Tok.getEndLoc()));
3793   return MatchOperand_Success;
3794 }
3795 
3796 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3797 /// instructions. Legal values are:
3798 ///     lsl #n  'n' in [0,31]
3799 ///     asr #n  'n' in [1,32]
3800 ///             n == 32 encoded as n == 0.
3801 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3802 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3803   const AsmToken &Tok = Parser.getTok();
3804   SMLoc S = Tok.getLoc();
3805   if (Tok.isNot(AsmToken::Identifier)) {
3806     Error(S, "shift operator 'asr' or 'lsl' expected");
3807     return MatchOperand_ParseFail;
3808   }
3809   StringRef ShiftName = Tok.getString();
3810   bool isASR;
3811   if (ShiftName == "lsl" || ShiftName == "LSL")
3812     isASR = false;
3813   else if (ShiftName == "asr" || ShiftName == "ASR")
3814     isASR = true;
3815   else {
3816     Error(S, "shift operator 'asr' or 'lsl' expected");
3817     return MatchOperand_ParseFail;
3818   }
3819   Parser.Lex(); // Eat the operator.
3820 
3821   // A '#' and a shift amount.
3822   if (Parser.getTok().isNot(AsmToken::Hash) &&
3823       Parser.getTok().isNot(AsmToken::Dollar)) {
3824     Error(Parser.getTok().getLoc(), "'#' expected");
3825     return MatchOperand_ParseFail;
3826   }
3827   Parser.Lex(); // Eat hash token.
3828   SMLoc ExLoc = Parser.getTok().getLoc();
3829 
3830   const MCExpr *ShiftAmount;
3831   SMLoc EndLoc;
3832   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3833     Error(ExLoc, "malformed shift expression");
3834     return MatchOperand_ParseFail;
3835   }
3836   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3837   if (!CE) {
3838     Error(ExLoc, "shift amount must be an immediate");
3839     return MatchOperand_ParseFail;
3840   }
3841 
3842   int64_t Val = CE->getValue();
3843   if (isASR) {
3844     // Shift amount must be in [1,32]
3845     if (Val < 1 || Val > 32) {
3846       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3847       return MatchOperand_ParseFail;
3848     }
3849     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3850     if (isThumb() && Val == 32) {
3851       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3852       return MatchOperand_ParseFail;
3853     }
3854     if (Val == 32) Val = 0;
3855   } else {
3856     // Shift amount must be in [1,32]
3857     if (Val < 0 || Val > 31) {
3858       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3859       return MatchOperand_ParseFail;
3860     }
3861   }
3862 
3863   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3864 
3865   return MatchOperand_Success;
3866 }
3867 
3868 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3869 /// of instructions. Legal values are:
3870 ///     ror #n  'n' in {0, 8, 16, 24}
3871 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3872 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3873   const AsmToken &Tok = Parser.getTok();
3874   SMLoc S = Tok.getLoc();
3875   if (Tok.isNot(AsmToken::Identifier))
3876     return MatchOperand_NoMatch;
3877   StringRef ShiftName = Tok.getString();
3878   if (ShiftName != "ror" && ShiftName != "ROR")
3879     return MatchOperand_NoMatch;
3880   Parser.Lex(); // Eat the operator.
3881 
3882   // A '#' and a rotate amount.
3883   if (Parser.getTok().isNot(AsmToken::Hash) &&
3884       Parser.getTok().isNot(AsmToken::Dollar)) {
3885     Error(Parser.getTok().getLoc(), "'#' expected");
3886     return MatchOperand_ParseFail;
3887   }
3888   Parser.Lex(); // Eat hash token.
3889   SMLoc ExLoc = Parser.getTok().getLoc();
3890 
3891   const MCExpr *ShiftAmount;
3892   SMLoc EndLoc;
3893   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3894     Error(ExLoc, "malformed rotate expression");
3895     return MatchOperand_ParseFail;
3896   }
3897   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3898   if (!CE) {
3899     Error(ExLoc, "rotate amount must be an immediate");
3900     return MatchOperand_ParseFail;
3901   }
3902 
3903   int64_t Val = CE->getValue();
3904   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3905   // normally, zero is represented in asm by omitting the rotate operand
3906   // entirely.
3907   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3908     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3909     return MatchOperand_ParseFail;
3910   }
3911 
3912   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3913 
3914   return MatchOperand_Success;
3915 }
3916 
3917 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3918 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3919   SMLoc S = Parser.getTok().getLoc();
3920   // The bitfield descriptor is really two operands, the LSB and the width.
3921   if (Parser.getTok().isNot(AsmToken::Hash) &&
3922       Parser.getTok().isNot(AsmToken::Dollar)) {
3923     Error(Parser.getTok().getLoc(), "'#' expected");
3924     return MatchOperand_ParseFail;
3925   }
3926   Parser.Lex(); // Eat hash token.
3927 
3928   const MCExpr *LSBExpr;
3929   SMLoc E = Parser.getTok().getLoc();
3930   if (getParser().parseExpression(LSBExpr)) {
3931     Error(E, "malformed immediate expression");
3932     return MatchOperand_ParseFail;
3933   }
3934   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3935   if (!CE) {
3936     Error(E, "'lsb' operand must be an immediate");
3937     return MatchOperand_ParseFail;
3938   }
3939 
3940   int64_t LSB = CE->getValue();
3941   // The LSB must be in the range [0,31]
3942   if (LSB < 0 || LSB > 31) {
3943     Error(E, "'lsb' operand must be in the range [0,31]");
3944     return MatchOperand_ParseFail;
3945   }
3946   E = Parser.getTok().getLoc();
3947 
3948   // Expect another immediate operand.
3949   if (Parser.getTok().isNot(AsmToken::Comma)) {
3950     Error(Parser.getTok().getLoc(), "too few operands");
3951     return MatchOperand_ParseFail;
3952   }
3953   Parser.Lex(); // Eat hash token.
3954   if (Parser.getTok().isNot(AsmToken::Hash) &&
3955       Parser.getTok().isNot(AsmToken::Dollar)) {
3956     Error(Parser.getTok().getLoc(), "'#' expected");
3957     return MatchOperand_ParseFail;
3958   }
3959   Parser.Lex(); // Eat hash token.
3960 
3961   const MCExpr *WidthExpr;
3962   SMLoc EndLoc;
3963   if (getParser().parseExpression(WidthExpr, EndLoc)) {
3964     Error(E, "malformed immediate expression");
3965     return MatchOperand_ParseFail;
3966   }
3967   CE = dyn_cast<MCConstantExpr>(WidthExpr);
3968   if (!CE) {
3969     Error(E, "'width' operand must be an immediate");
3970     return MatchOperand_ParseFail;
3971   }
3972 
3973   int64_t Width = CE->getValue();
3974   // The LSB must be in the range [1,32-lsb]
3975   if (Width < 1 || Width > 32 - LSB) {
3976     Error(E, "'width' operand must be in the range [1,32-lsb]");
3977     return MatchOperand_ParseFail;
3978   }
3979 
3980   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3981 
3982   return MatchOperand_Success;
3983 }
3984 
3985 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3986 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3987   // Check for a post-index addressing register operand. Specifically:
3988   // postidx_reg := '+' register {, shift}
3989   //              | '-' register {, shift}
3990   //              | register {, shift}
3991 
3992   // This method must return MatchOperand_NoMatch without consuming any tokens
3993   // in the case where there is no match, as other alternatives take other
3994   // parse methods.
3995   AsmToken Tok = Parser.getTok();
3996   SMLoc S = Tok.getLoc();
3997   bool haveEaten = false;
3998   bool isAdd = true;
3999   if (Tok.is(AsmToken::Plus)) {
4000     Parser.Lex(); // Eat the '+' token.
4001     haveEaten = true;
4002   } else if (Tok.is(AsmToken::Minus)) {
4003     Parser.Lex(); // Eat the '-' token.
4004     isAdd = false;
4005     haveEaten = true;
4006   }
4007 
4008   SMLoc E = Parser.getTok().getEndLoc();
4009   int Reg = tryParseRegister();
4010   if (Reg == -1) {
4011     if (!haveEaten)
4012       return MatchOperand_NoMatch;
4013     Error(Parser.getTok().getLoc(), "register expected");
4014     return MatchOperand_ParseFail;
4015   }
4016 
4017   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4018   unsigned ShiftImm = 0;
4019   if (Parser.getTok().is(AsmToken::Comma)) {
4020     Parser.Lex(); // Eat the ','.
4021     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4022       return MatchOperand_ParseFail;
4023 
4024     // FIXME: Only approximates end...may include intervening whitespace.
4025     E = Parser.getTok().getLoc();
4026   }
4027 
4028   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4029                                                   ShiftImm, S, E));
4030 
4031   return MatchOperand_Success;
4032 }
4033 
4034 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4035 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4036   // Check for a post-index addressing register operand. Specifically:
4037   // am3offset := '+' register
4038   //              | '-' register
4039   //              | register
4040   //              | # imm
4041   //              | # + imm
4042   //              | # - imm
4043 
4044   // This method must return MatchOperand_NoMatch without consuming any tokens
4045   // in the case where there is no match, as other alternatives take other
4046   // parse methods.
4047   AsmToken Tok = Parser.getTok();
4048   SMLoc S = Tok.getLoc();
4049 
4050   // Do immediates first, as we always parse those if we have a '#'.
4051   if (Parser.getTok().is(AsmToken::Hash) ||
4052       Parser.getTok().is(AsmToken::Dollar)) {
4053     Parser.Lex(); // Eat '#' or '$'.
4054     // Explicitly look for a '-', as we need to encode negative zero
4055     // differently.
4056     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4057     const MCExpr *Offset;
4058     SMLoc E;
4059     if (getParser().parseExpression(Offset, E))
4060       return MatchOperand_ParseFail;
4061     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4062     if (!CE) {
4063       Error(S, "constant expression expected");
4064       return MatchOperand_ParseFail;
4065     }
4066     // Negative zero is encoded as the flag value INT32_MIN.
4067     int32_t Val = CE->getValue();
4068     if (isNegative && Val == 0)
4069       Val = INT32_MIN;
4070 
4071     Operands.push_back(
4072       ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4073 
4074     return MatchOperand_Success;
4075   }
4076 
4077 
4078   bool haveEaten = false;
4079   bool isAdd = true;
4080   if (Tok.is(AsmToken::Plus)) {
4081     Parser.Lex(); // Eat the '+' token.
4082     haveEaten = true;
4083   } else if (Tok.is(AsmToken::Minus)) {
4084     Parser.Lex(); // Eat the '-' token.
4085     isAdd = false;
4086     haveEaten = true;
4087   }
4088 
4089   Tok = Parser.getTok();
4090   int Reg = tryParseRegister();
4091   if (Reg == -1) {
4092     if (!haveEaten)
4093       return MatchOperand_NoMatch;
4094     Error(Tok.getLoc(), "register expected");
4095     return MatchOperand_ParseFail;
4096   }
4097 
4098   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4099                                                   0, S, Tok.getEndLoc()));
4100 
4101   return MatchOperand_Success;
4102 }
4103 
4104 /// Convert parsed operands to MCInst.  Needed here because this instruction
4105 /// only has two register operands, but multiplication is commutative so
4106 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4107 void ARMAsmParser::
4108 cvtThumbMultiply(MCInst &Inst,
4109            const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4110   ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4111   ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4112   // If we have a three-operand form, make sure to set Rn to be the operand
4113   // that isn't the same as Rd.
4114   unsigned RegOp = 4;
4115   if (Operands.size() == 6 &&
4116       ((ARMOperand*)Operands[4])->getReg() ==
4117         ((ARMOperand*)Operands[3])->getReg())
4118     RegOp = 5;
4119   ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4120   Inst.addOperand(Inst.getOperand(0));
4121   ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4122 }
4123 
4124 void ARMAsmParser::
4125 cvtThumbBranches(MCInst &Inst,
4126            const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4127   int CondOp = -1, ImmOp = -1;
4128   switch(Inst.getOpcode()) {
4129     case ARM::tB:
4130     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4131 
4132     case ARM::t2B:
4133     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4134 
4135     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4136   }
4137   // first decide whether or not the branch should be conditional
4138   // by looking at it's location relative to an IT block
4139   if(inITBlock()) {
4140     // inside an IT block we cannot have any conditional branches. any
4141     // such instructions needs to be converted to unconditional form
4142     switch(Inst.getOpcode()) {
4143       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4144       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4145     }
4146   } else {
4147     // outside IT blocks we can only have unconditional branches with AL
4148     // condition code or conditional branches with non-AL condition code
4149     unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4150     switch(Inst.getOpcode()) {
4151       case ARM::tB:
4152       case ARM::tBcc:
4153         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4154         break;
4155       case ARM::t2B:
4156       case ARM::t2Bcc:
4157         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4158         break;
4159     }
4160   }
4161 
4162   // now decide on encoding size based on branch target range
4163   switch(Inst.getOpcode()) {
4164     // classify tB as either t2B or t1B based on range of immediate operand
4165     case ARM::tB: {
4166       ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4167       if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4168         Inst.setOpcode(ARM::t2B);
4169       break;
4170     }
4171     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4172     case ARM::tBcc: {
4173       ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4174       if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4175         Inst.setOpcode(ARM::t2Bcc);
4176       break;
4177     }
4178   }
4179   ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4180   ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4181 }
4182 
4183 /// Parse an ARM memory expression, return false if successful else return true
4184 /// or an error.  The first token must be a '[' when called.
4185 bool ARMAsmParser::
4186 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4187   SMLoc S, E;
4188   assert(Parser.getTok().is(AsmToken::LBrac) &&
4189          "Token is not a Left Bracket");
4190   S = Parser.getTok().getLoc();
4191   Parser.Lex(); // Eat left bracket token.
4192 
4193   const AsmToken &BaseRegTok = Parser.getTok();
4194   int BaseRegNum = tryParseRegister();
4195   if (BaseRegNum == -1)
4196     return Error(BaseRegTok.getLoc(), "register expected");
4197 
4198   // The next token must either be a comma, a colon or a closing bracket.
4199   const AsmToken &Tok = Parser.getTok();
4200   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4201       !Tok.is(AsmToken::RBrac))
4202     return Error(Tok.getLoc(), "malformed memory operand");
4203 
4204   if (Tok.is(AsmToken::RBrac)) {
4205     E = Tok.getEndLoc();
4206     Parser.Lex(); // Eat right bracket token.
4207 
4208     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4209                                              0, 0, false, S, E));
4210 
4211     // If there's a pre-indexing writeback marker, '!', just add it as a token
4212     // operand. It's rather odd, but syntactically valid.
4213     if (Parser.getTok().is(AsmToken::Exclaim)) {
4214       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4215       Parser.Lex(); // Eat the '!'.
4216     }
4217 
4218     return false;
4219   }
4220 
4221   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4222          "Lost colon or comma in memory operand?!");
4223   if (Tok.is(AsmToken::Comma)) {
4224     Parser.Lex(); // Eat the comma.
4225   }
4226 
4227   // If we have a ':', it's an alignment specifier.
4228   if (Parser.getTok().is(AsmToken::Colon)) {
4229     Parser.Lex(); // Eat the ':'.
4230     E = Parser.getTok().getLoc();
4231 
4232     const MCExpr *Expr;
4233     if (getParser().parseExpression(Expr))
4234      return true;
4235 
4236     // The expression has to be a constant. Memory references with relocations
4237     // don't come through here, as they use the <label> forms of the relevant
4238     // instructions.
4239     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4240     if (!CE)
4241       return Error (E, "constant expression expected");
4242 
4243     unsigned Align = 0;
4244     switch (CE->getValue()) {
4245     default:
4246       return Error(E,
4247                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4248     case 16:  Align = 2; break;
4249     case 32:  Align = 4; break;
4250     case 64:  Align = 8; break;
4251     case 128: Align = 16; break;
4252     case 256: Align = 32; break;
4253     }
4254 
4255     // Now we should have the closing ']'
4256     if (Parser.getTok().isNot(AsmToken::RBrac))
4257       return Error(Parser.getTok().getLoc(), "']' expected");
4258     E = Parser.getTok().getEndLoc();
4259     Parser.Lex(); // Eat right bracket token.
4260 
4261     // Don't worry about range checking the value here. That's handled by
4262     // the is*() predicates.
4263     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4264                                              ARM_AM::no_shift, 0, Align,
4265                                              false, S, E));
4266 
4267     // If there's a pre-indexing writeback marker, '!', just add it as a token
4268     // operand.
4269     if (Parser.getTok().is(AsmToken::Exclaim)) {
4270       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4271       Parser.Lex(); // Eat the '!'.
4272     }
4273 
4274     return false;
4275   }
4276 
4277   // If we have a '#', it's an immediate offset, else assume it's a register
4278   // offset. Be friendly and also accept a plain integer (without a leading
4279   // hash) for gas compatibility.
4280   if (Parser.getTok().is(AsmToken::Hash) ||
4281       Parser.getTok().is(AsmToken::Dollar) ||
4282       Parser.getTok().is(AsmToken::Integer)) {
4283     if (Parser.getTok().isNot(AsmToken::Integer))
4284       Parser.Lex(); // Eat '#' or '$'.
4285     E = Parser.getTok().getLoc();
4286 
4287     bool isNegative = getParser().getTok().is(AsmToken::Minus);
4288     const MCExpr *Offset;
4289     if (getParser().parseExpression(Offset))
4290      return true;
4291 
4292     // The expression has to be a constant. Memory references with relocations
4293     // don't come through here, as they use the <label> forms of the relevant
4294     // instructions.
4295     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4296     if (!CE)
4297       return Error (E, "constant expression expected");
4298 
4299     // If the constant was #-0, represent it as INT32_MIN.
4300     int32_t Val = CE->getValue();
4301     if (isNegative && Val == 0)
4302       CE = MCConstantExpr::Create(INT32_MIN, getContext());
4303 
4304     // Now we should have the closing ']'
4305     if (Parser.getTok().isNot(AsmToken::RBrac))
4306       return Error(Parser.getTok().getLoc(), "']' expected");
4307     E = Parser.getTok().getEndLoc();
4308     Parser.Lex(); // Eat right bracket token.
4309 
4310     // Don't worry about range checking the value here. That's handled by
4311     // the is*() predicates.
4312     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4313                                              ARM_AM::no_shift, 0, 0,
4314                                              false, S, E));
4315 
4316     // If there's a pre-indexing writeback marker, '!', just add it as a token
4317     // operand.
4318     if (Parser.getTok().is(AsmToken::Exclaim)) {
4319       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4320       Parser.Lex(); // Eat the '!'.
4321     }
4322 
4323     return false;
4324   }
4325 
4326   // The register offset is optionally preceded by a '+' or '-'
4327   bool isNegative = false;
4328   if (Parser.getTok().is(AsmToken::Minus)) {
4329     isNegative = true;
4330     Parser.Lex(); // Eat the '-'.
4331   } else if (Parser.getTok().is(AsmToken::Plus)) {
4332     // Nothing to do.
4333     Parser.Lex(); // Eat the '+'.
4334   }
4335 
4336   E = Parser.getTok().getLoc();
4337   int OffsetRegNum = tryParseRegister();
4338   if (OffsetRegNum == -1)
4339     return Error(E, "register expected");
4340 
4341   // If there's a shift operator, handle it.
4342   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4343   unsigned ShiftImm = 0;
4344   if (Parser.getTok().is(AsmToken::Comma)) {
4345     Parser.Lex(); // Eat the ','.
4346     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4347       return true;
4348   }
4349 
4350   // Now we should have the closing ']'
4351   if (Parser.getTok().isNot(AsmToken::RBrac))
4352     return Error(Parser.getTok().getLoc(), "']' expected");
4353   E = Parser.getTok().getEndLoc();
4354   Parser.Lex(); // Eat right bracket token.
4355 
4356   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4357                                            ShiftType, ShiftImm, 0, isNegative,
4358                                            S, E));
4359 
4360   // If there's a pre-indexing writeback marker, '!', just add it as a token
4361   // operand.
4362   if (Parser.getTok().is(AsmToken::Exclaim)) {
4363     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4364     Parser.Lex(); // Eat the '!'.
4365   }
4366 
4367   return false;
4368 }
4369 
4370 /// parseMemRegOffsetShift - one of these two:
4371 ///   ( lsl | lsr | asr | ror ) , # shift_amount
4372 ///   rrx
4373 /// return true if it parses a shift otherwise it returns false.
4374 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4375                                           unsigned &Amount) {
4376   SMLoc Loc = Parser.getTok().getLoc();
4377   const AsmToken &Tok = Parser.getTok();
4378   if (Tok.isNot(AsmToken::Identifier))
4379     return true;
4380   StringRef ShiftName = Tok.getString();
4381   if (ShiftName == "lsl" || ShiftName == "LSL" ||
4382       ShiftName == "asl" || ShiftName == "ASL")
4383     St = ARM_AM::lsl;
4384   else if (ShiftName == "lsr" || ShiftName == "LSR")
4385     St = ARM_AM::lsr;
4386   else if (ShiftName == "asr" || ShiftName == "ASR")
4387     St = ARM_AM::asr;
4388   else if (ShiftName == "ror" || ShiftName == "ROR")
4389     St = ARM_AM::ror;
4390   else if (ShiftName == "rrx" || ShiftName == "RRX")
4391     St = ARM_AM::rrx;
4392   else
4393     return Error(Loc, "illegal shift operator");
4394   Parser.Lex(); // Eat shift type token.
4395 
4396   // rrx stands alone.
4397   Amount = 0;
4398   if (St != ARM_AM::rrx) {
4399     Loc = Parser.getTok().getLoc();
4400     // A '#' and a shift amount.
4401     const AsmToken &HashTok = Parser.getTok();
4402     if (HashTok.isNot(AsmToken::Hash) &&
4403         HashTok.isNot(AsmToken::Dollar))
4404       return Error(HashTok.getLoc(), "'#' expected");
4405     Parser.Lex(); // Eat hash token.
4406 
4407     const MCExpr *Expr;
4408     if (getParser().parseExpression(Expr))
4409       return true;
4410     // Range check the immediate.
4411     // lsl, ror: 0 <= imm <= 31
4412     // lsr, asr: 0 <= imm <= 32
4413     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4414     if (!CE)
4415       return Error(Loc, "shift amount must be an immediate");
4416     int64_t Imm = CE->getValue();
4417     if (Imm < 0 ||
4418         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4419         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4420       return Error(Loc, "immediate shift value out of range");
4421     // If <ShiftTy> #0, turn it into a no_shift.
4422     if (Imm == 0)
4423       St = ARM_AM::lsl;
4424     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4425     if (Imm == 32)
4426       Imm = 0;
4427     Amount = Imm;
4428   }
4429 
4430   return false;
4431 }
4432 
4433 /// parseFPImm - A floating point immediate expression operand.
4434 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4435 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4436   // Anything that can accept a floating point constant as an operand
4437   // needs to go through here, as the regular parseExpression is
4438   // integer only.
4439   //
4440   // This routine still creates a generic Immediate operand, containing
4441   // a bitcast of the 64-bit floating point value. The various operands
4442   // that accept floats can check whether the value is valid for them
4443   // via the standard is*() predicates.
4444 
4445   SMLoc S = Parser.getTok().getLoc();
4446 
4447   if (Parser.getTok().isNot(AsmToken::Hash) &&
4448       Parser.getTok().isNot(AsmToken::Dollar))
4449     return MatchOperand_NoMatch;
4450 
4451   // Disambiguate the VMOV forms that can accept an FP immediate.
4452   // vmov.f32 <sreg>, #imm
4453   // vmov.f64 <dreg>, #imm
4454   // vmov.f32 <dreg>, #imm  @ vector f32x2
4455   // vmov.f32 <qreg>, #imm  @ vector f32x4
4456   //
4457   // There are also the NEON VMOV instructions which expect an
4458   // integer constant. Make sure we don't try to parse an FPImm
4459   // for these:
4460   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4461   ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4462   if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4463                            TyOp->getToken() != ".f64"))
4464     return MatchOperand_NoMatch;
4465 
4466   Parser.Lex(); // Eat '#' or '$'.
4467 
4468   // Handle negation, as that still comes through as a separate token.
4469   bool isNegative = false;
4470   if (Parser.getTok().is(AsmToken::Minus)) {
4471     isNegative = true;
4472     Parser.Lex();
4473   }
4474   const AsmToken &Tok = Parser.getTok();
4475   SMLoc Loc = Tok.getLoc();
4476   if (Tok.is(AsmToken::Real)) {
4477     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4478     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4479     // If we had a '-' in front, toggle the sign bit.
4480     IntVal ^= (uint64_t)isNegative << 31;
4481     Parser.Lex(); // Eat the token.
4482     Operands.push_back(ARMOperand::CreateImm(
4483           MCConstantExpr::Create(IntVal, getContext()),
4484           S, Parser.getTok().getLoc()));
4485     return MatchOperand_Success;
4486   }
4487   // Also handle plain integers. Instructions which allow floating point
4488   // immediates also allow a raw encoded 8-bit value.
4489   if (Tok.is(AsmToken::Integer)) {
4490     int64_t Val = Tok.getIntVal();
4491     Parser.Lex(); // Eat the token.
4492     if (Val > 255 || Val < 0) {
4493       Error(Loc, "encoded floating point value out of range");
4494       return MatchOperand_ParseFail;
4495     }
4496     double RealVal = ARM_AM::getFPImmFloat(Val);
4497     Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4498     Operands.push_back(ARMOperand::CreateImm(
4499         MCConstantExpr::Create(Val, getContext()), S,
4500         Parser.getTok().getLoc()));
4501     return MatchOperand_Success;
4502   }
4503 
4504   Error(Loc, "invalid floating point immediate");
4505   return MatchOperand_ParseFail;
4506 }
4507 
4508 /// Parse a arm instruction operand.  For now this parses the operand regardless
4509 /// of the mnemonic.
4510 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4511                                 StringRef Mnemonic) {
4512   SMLoc S, E;
4513 
4514   // Check if the current operand has a custom associated parser, if so, try to
4515   // custom parse the operand, or fallback to the general approach.
4516   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4517   if (ResTy == MatchOperand_Success)
4518     return false;
4519   // If there wasn't a custom match, try the generic matcher below. Otherwise,
4520   // there was a match, but an error occurred, in which case, just return that
4521   // the operand parsing failed.
4522   if (ResTy == MatchOperand_ParseFail)
4523     return true;
4524 
4525   switch (getLexer().getKind()) {
4526   default:
4527     Error(Parser.getTok().getLoc(), "unexpected token in operand");
4528     return true;
4529   case AsmToken::Identifier: {
4530     // If we've seen a branch mnemonic, the next operand must be a label.  This
4531     // is true even if the label is a register name.  So "br r1" means branch to
4532     // label "r1".
4533     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4534     if (!ExpectLabel) {
4535       if (!tryParseRegisterWithWriteBack(Operands))
4536         return false;
4537       int Res = tryParseShiftRegister(Operands);
4538       if (Res == 0) // success
4539         return false;
4540       else if (Res == -1) // irrecoverable error
4541         return true;
4542       // If this is VMRS, check for the apsr_nzcv operand.
4543       if (Mnemonic == "vmrs" &&
4544           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4545         S = Parser.getTok().getLoc();
4546         Parser.Lex();
4547         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4548         return false;
4549       }
4550     }
4551 
4552     // Fall though for the Identifier case that is not a register or a
4553     // special name.
4554   }
4555   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4556   case AsmToken::Integer: // things like 1f and 2b as a branch targets
4557   case AsmToken::String:  // quoted label names.
4558   case AsmToken::Dot: {   // . as a branch target
4559     // This was not a register so parse other operands that start with an
4560     // identifier (like labels) as expressions and create them as immediates.
4561     const MCExpr *IdVal;
4562     S = Parser.getTok().getLoc();
4563     if (getParser().parseExpression(IdVal))
4564       return true;
4565     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4566     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4567     return false;
4568   }
4569   case AsmToken::LBrac:
4570     return parseMemory(Operands);
4571   case AsmToken::LCurly:
4572     return parseRegisterList(Operands);
4573   case AsmToken::Dollar:
4574   case AsmToken::Hash: {
4575     // #42 -> immediate.
4576     S = Parser.getTok().getLoc();
4577     Parser.Lex();
4578 
4579     if (Parser.getTok().isNot(AsmToken::Colon)) {
4580       bool isNegative = Parser.getTok().is(AsmToken::Minus);
4581       const MCExpr *ImmVal;
4582       if (getParser().parseExpression(ImmVal))
4583         return true;
4584       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4585       if (CE) {
4586         int32_t Val = CE->getValue();
4587         if (isNegative && Val == 0)
4588           ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4589       }
4590       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4591       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4592 
4593       // There can be a trailing '!' on operands that we want as a separate
4594       // '!' Token operand. Handle that here. For example, the compatibilty
4595       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4596       if (Parser.getTok().is(AsmToken::Exclaim)) {
4597         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4598                                                    Parser.getTok().getLoc()));
4599         Parser.Lex(); // Eat exclaim token
4600       }
4601       return false;
4602     }
4603     // w/ a ':' after the '#', it's just like a plain ':'.
4604     // FALLTHROUGH
4605   }
4606   case AsmToken::Colon: {
4607     // ":lower16:" and ":upper16:" expression prefixes
4608     // FIXME: Check it's an expression prefix,
4609     // e.g. (FOO - :lower16:BAR) isn't legal.
4610     ARMMCExpr::VariantKind RefKind;
4611     if (parsePrefix(RefKind))
4612       return true;
4613 
4614     const MCExpr *SubExprVal;
4615     if (getParser().parseExpression(SubExprVal))
4616       return true;
4617 
4618     const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4619                                               getContext());
4620     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4621     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4622     return false;
4623   }
4624   }
4625 }
4626 
4627 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4628 //  :lower16: and :upper16:.
4629 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4630   RefKind = ARMMCExpr::VK_ARM_None;
4631 
4632   // :lower16: and :upper16: modifiers
4633   assert(getLexer().is(AsmToken::Colon) && "expected a :");
4634   Parser.Lex(); // Eat ':'
4635 
4636   if (getLexer().isNot(AsmToken::Identifier)) {
4637     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4638     return true;
4639   }
4640 
4641   StringRef IDVal = Parser.getTok().getIdentifier();
4642   if (IDVal == "lower16") {
4643     RefKind = ARMMCExpr::VK_ARM_LO16;
4644   } else if (IDVal == "upper16") {
4645     RefKind = ARMMCExpr::VK_ARM_HI16;
4646   } else {
4647     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4648     return true;
4649   }
4650   Parser.Lex();
4651 
4652   if (getLexer().isNot(AsmToken::Colon)) {
4653     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4654     return true;
4655   }
4656   Parser.Lex(); // Eat the last ':'
4657   return false;
4658 }
4659 
4660 /// \brief Given a mnemonic, split out possible predication code and carry
4661 /// setting letters to form a canonical mnemonic and flags.
4662 //
4663 // FIXME: Would be nice to autogen this.
4664 // FIXME: This is a bit of a maze of special cases.
4665 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4666                                       unsigned &PredicationCode,
4667                                       bool &CarrySetting,
4668                                       unsigned &ProcessorIMod,
4669                                       StringRef &ITMask) {
4670   PredicationCode = ARMCC::AL;
4671   CarrySetting = false;
4672   ProcessorIMod = 0;
4673 
4674   // Ignore some mnemonics we know aren't predicated forms.
4675   //
4676   // FIXME: Would be nice to autogen this.
4677   if ((Mnemonic == "movs" && isThumb()) ||
4678       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4679       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4680       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4681       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4682       Mnemonic == "vaclt" || Mnemonic == "vacle"  ||
4683       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4684       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4685       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4686       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4687       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
4688       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4689       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4690     return Mnemonic;
4691 
4692   // First, split out any predication code. Ignore mnemonics we know aren't
4693   // predicated but do have a carry-set and so weren't caught above.
4694   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4695       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4696       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4697       Mnemonic != "sbcs" && Mnemonic != "rscs") {
4698     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4699       .Case("eq", ARMCC::EQ)
4700       .Case("ne", ARMCC::NE)
4701       .Case("hs", ARMCC::HS)
4702       .Case("cs", ARMCC::HS)
4703       .Case("lo", ARMCC::LO)
4704       .Case("cc", ARMCC::LO)
4705       .Case("mi", ARMCC::MI)
4706       .Case("pl", ARMCC::PL)
4707       .Case("vs", ARMCC::VS)
4708       .Case("vc", ARMCC::VC)
4709       .Case("hi", ARMCC::HI)
4710       .Case("ls", ARMCC::LS)
4711       .Case("ge", ARMCC::GE)
4712       .Case("lt", ARMCC::LT)
4713       .Case("gt", ARMCC::GT)
4714       .Case("le", ARMCC::LE)
4715       .Case("al", ARMCC::AL)
4716       .Default(~0U);
4717     if (CC != ~0U) {
4718       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4719       PredicationCode = CC;
4720     }
4721   }
4722 
4723   // Next, determine if we have a carry setting bit. We explicitly ignore all
4724   // the instructions we know end in 's'.
4725   if (Mnemonic.endswith("s") &&
4726       !(Mnemonic == "cps" || Mnemonic == "mls" ||
4727         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4728         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4729         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4730         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4731         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4732         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4733         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4734         Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4735         (Mnemonic == "movs" && isThumb()))) {
4736     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4737     CarrySetting = true;
4738   }
4739 
4740   // The "cps" instruction can have a interrupt mode operand which is glued into
4741   // the mnemonic. Check if this is the case, split it and parse the imod op
4742   if (Mnemonic.startswith("cps")) {
4743     // Split out any imod code.
4744     unsigned IMod =
4745       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4746       .Case("ie", ARM_PROC::IE)
4747       .Case("id", ARM_PROC::ID)
4748       .Default(~0U);
4749     if (IMod != ~0U) {
4750       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4751       ProcessorIMod = IMod;
4752     }
4753   }
4754 
4755   // The "it" instruction has the condition mask on the end of the mnemonic.
4756   if (Mnemonic.startswith("it")) {
4757     ITMask = Mnemonic.slice(2, Mnemonic.size());
4758     Mnemonic = Mnemonic.slice(0, 2);
4759   }
4760 
4761   return Mnemonic;
4762 }
4763 
4764 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4765 /// inclusion of carry set or predication code operands.
4766 //
4767 // FIXME: It would be nice to autogen this.
4768 void ARMAsmParser::
4769 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4770                       bool &CanAcceptPredicationCode) {
4771   if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4772       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4773       Mnemonic == "add" || Mnemonic == "adc" ||
4774       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4775       Mnemonic == "orr" || Mnemonic == "mvn" ||
4776       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4777       Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4778       Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4779       (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4780                       Mnemonic == "mla" || Mnemonic == "smlal" ||
4781                       Mnemonic == "umlal" || Mnemonic == "umull"))) {
4782     CanAcceptCarrySet = true;
4783   } else
4784     CanAcceptCarrySet = false;
4785 
4786   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4787       Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
4788       Mnemonic == "trap" || Mnemonic == "setend" ||
4789       Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4790       Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4791       Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4792       Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4793       Mnemonic == "vrintm") {
4794     // These mnemonics are never predicable
4795     CanAcceptPredicationCode = false;
4796   } else if (!isThumb()) {
4797     // Some instructions are only predicable in Thumb mode
4798     CanAcceptPredicationCode
4799       = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4800         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4801         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4802         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4803         Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4804         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4805         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4806   } else if (isThumbOne()) {
4807     CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4808   } else
4809     CanAcceptPredicationCode = true;
4810 }
4811 
4812 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4813                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4814   // FIXME: This is all horribly hacky. We really need a better way to deal
4815   // with optional operands like this in the matcher table.
4816 
4817   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4818   // another does not. Specifically, the MOVW instruction does not. So we
4819   // special case it here and remove the defaulted (non-setting) cc_out
4820   // operand if that's the instruction we're trying to match.
4821   //
4822   // We do this as post-processing of the explicit operands rather than just
4823   // conditionally adding the cc_out in the first place because we need
4824   // to check the type of the parsed immediate operand.
4825   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4826       !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4827       static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4828       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4829     return true;
4830 
4831   // Register-register 'add' for thumb does not have a cc_out operand
4832   // when there are only two register operands.
4833   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4834       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4835       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4836       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4837     return true;
4838   // Register-register 'add' for thumb does not have a cc_out operand
4839   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4840   // have to check the immediate range here since Thumb2 has a variant
4841   // that can handle a different range and has a cc_out operand.
4842   if (((isThumb() && Mnemonic == "add") ||
4843        (isThumbTwo() && Mnemonic == "sub")) &&
4844       Operands.size() == 6 &&
4845       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4846       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4847       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4848       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4849       ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4850        static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4851     return true;
4852   // For Thumb2, add/sub immediate does not have a cc_out operand for the
4853   // imm0_4095 variant. That's the least-preferred variant when
4854   // selecting via the generic "add" mnemonic, so to know that we
4855   // should remove the cc_out operand, we have to explicitly check that
4856   // it's not one of the other variants. Ugh.
4857   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4858       Operands.size() == 6 &&
4859       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4860       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4861       static_cast<ARMOperand*>(Operands[5])->isImm()) {
4862     // Nest conditions rather than one big 'if' statement for readability.
4863     //
4864     // If both registers are low, we're in an IT block, and the immediate is
4865     // in range, we should use encoding T1 instead, which has a cc_out.
4866     if (inITBlock() &&
4867         isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4868         isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4869         static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4870       return false;
4871     // Check against T3. If the second register is the PC, this is an
4872     // alternate form of ADR, which uses encoding T4, so check for that too.
4873     if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4874         static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4875       return false;
4876 
4877     // Otherwise, we use encoding T4, which does not have a cc_out
4878     // operand.
4879     return true;
4880   }
4881 
4882   // The thumb2 multiply instruction doesn't have a CCOut register, so
4883   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4884   // use the 16-bit encoding or not.
4885   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4886       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4887       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4888       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4889       static_cast<ARMOperand*>(Operands[5])->isReg() &&
4890       // If the registers aren't low regs, the destination reg isn't the
4891       // same as one of the source regs, or the cc_out operand is zero
4892       // outside of an IT block, we have to use the 32-bit encoding, so
4893       // remove the cc_out operand.
4894       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4895        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4896        !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4897        !inITBlock() ||
4898        (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4899         static_cast<ARMOperand*>(Operands[5])->getReg() &&
4900         static_cast<ARMOperand*>(Operands[3])->getReg() !=
4901         static_cast<ARMOperand*>(Operands[4])->getReg())))
4902     return true;
4903 
4904   // Also check the 'mul' syntax variant that doesn't specify an explicit
4905   // destination register.
4906   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4907       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4908       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4909       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4910       // If the registers aren't low regs  or the cc_out operand is zero
4911       // outside of an IT block, we have to use the 32-bit encoding, so
4912       // remove the cc_out operand.
4913       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4914        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4915        !inITBlock()))
4916     return true;
4917 
4918 
4919 
4920   // Register-register 'add/sub' for thumb does not have a cc_out operand
4921   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4922   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4923   // right, this will result in better diagnostics (which operand is off)
4924   // anyway.
4925   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4926       (Operands.size() == 5 || Operands.size() == 6) &&
4927       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4928       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4929       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4930       (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4931        (Operands.size() == 6 &&
4932         static_cast<ARMOperand*>(Operands[5])->isImm())))
4933     return true;
4934 
4935   return false;
4936 }
4937 
4938 bool ARMAsmParser::shouldOmitPredicateOperand(
4939     StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
4940   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
4941   unsigned RegIdx = 3;
4942   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
4943       static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
4944     if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
4945         static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
4946       RegIdx = 4;
4947 
4948     if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
4949         (ARMMCRegisterClasses[ARM::DPRRegClassID]
4950              .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4951          ARMMCRegisterClasses[ARM::QPRRegClassID]
4952              .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
4953       return true;
4954   }
4955   return false;
4956 }
4957 
4958 bool ARMAsmParser::isDeprecated(MCInst &Inst, StringRef &Info) {
4959   if (hasV8Ops() && Inst.getOpcode() == ARM::SETEND) {
4960     Info = "armv8";
4961     return true;
4962   }
4963   return false;
4964 }
4965 
4966 static bool isDataTypeToken(StringRef Tok) {
4967   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4968     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4969     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4970     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4971     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4972     Tok == ".f" || Tok == ".d";
4973 }
4974 
4975 // FIXME: This bit should probably be handled via an explicit match class
4976 // in the .td files that matches the suffix instead of having it be
4977 // a literal string token the way it is now.
4978 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4979   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4980 }
4981 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
4982                                  unsigned VariantID);
4983 /// Parse an arm instruction mnemonic followed by its operands.
4984 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4985                                     SMLoc NameLoc,
4986                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4987   // Apply mnemonic aliases before doing anything else, as the destination
4988   // mnemnonic may include suffices and we want to handle them normally.
4989   // The generic tblgen'erated code does this later, at the start of
4990   // MatchInstructionImpl(), but that's too late for aliases that include
4991   // any sort of suffix.
4992   unsigned AvailableFeatures = getAvailableFeatures();
4993   unsigned AssemblerDialect = getParser().getAssemblerDialect();
4994   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
4995 
4996   // First check for the ARM-specific .req directive.
4997   if (Parser.getTok().is(AsmToken::Identifier) &&
4998       Parser.getTok().getIdentifier() == ".req") {
4999     parseDirectiveReq(Name, NameLoc);
5000     // We always return 'error' for this, as we're done with this
5001     // statement and don't need to match the 'instruction."
5002     return true;
5003   }
5004 
5005   // Create the leading tokens for the mnemonic, split by '.' characters.
5006   size_t Start = 0, Next = Name.find('.');
5007   StringRef Mnemonic = Name.slice(Start, Next);
5008 
5009   // Split out the predication code and carry setting flag from the mnemonic.
5010   unsigned PredicationCode;
5011   unsigned ProcessorIMod;
5012   bool CarrySetting;
5013   StringRef ITMask;
5014   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5015                            ProcessorIMod, ITMask);
5016 
5017   // In Thumb1, only the branch (B) instruction can be predicated.
5018   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5019     Parser.eatToEndOfStatement();
5020     return Error(NameLoc, "conditional execution not supported in Thumb1");
5021   }
5022 
5023   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5024 
5025   // Handle the IT instruction ITMask. Convert it to a bitmask. This
5026   // is the mask as it will be for the IT encoding if the conditional
5027   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5028   // where the conditional bit0 is zero, the instruction post-processing
5029   // will adjust the mask accordingly.
5030   if (Mnemonic == "it") {
5031     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5032     if (ITMask.size() > 3) {
5033       Parser.eatToEndOfStatement();
5034       return Error(Loc, "too many conditions on IT instruction");
5035     }
5036     unsigned Mask = 8;
5037     for (unsigned i = ITMask.size(); i != 0; --i) {
5038       char pos = ITMask[i - 1];
5039       if (pos != 't' && pos != 'e') {
5040         Parser.eatToEndOfStatement();
5041         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5042       }
5043       Mask >>= 1;
5044       if (ITMask[i - 1] == 't')
5045         Mask |= 8;
5046     }
5047     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5048   }
5049 
5050   // FIXME: This is all a pretty gross hack. We should automatically handle
5051   // optional operands like this via tblgen.
5052 
5053   // Next, add the CCOut and ConditionCode operands, if needed.
5054   //
5055   // For mnemonics which can ever incorporate a carry setting bit or predication
5056   // code, our matching model involves us always generating CCOut and
5057   // ConditionCode operands to match the mnemonic "as written" and then we let
5058   // the matcher deal with finding the right instruction or generating an
5059   // appropriate error.
5060   bool CanAcceptCarrySet, CanAcceptPredicationCode;
5061   getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5062 
5063   // If we had a carry-set on an instruction that can't do that, issue an
5064   // error.
5065   if (!CanAcceptCarrySet && CarrySetting) {
5066     Parser.eatToEndOfStatement();
5067     return Error(NameLoc, "instruction '" + Mnemonic +
5068                  "' can not set flags, but 's' suffix specified");
5069   }
5070   // If we had a predication code on an instruction that can't do that, issue an
5071   // error.
5072   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5073     Parser.eatToEndOfStatement();
5074     return Error(NameLoc, "instruction '" + Mnemonic +
5075                  "' is not predicable, but condition code specified");
5076   }
5077 
5078   // Add the carry setting operand, if necessary.
5079   if (CanAcceptCarrySet) {
5080     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5081     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5082                                                Loc));
5083   }
5084 
5085   // Add the predication code operand, if necessary.
5086   if (CanAcceptPredicationCode) {
5087     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5088                                       CarrySetting);
5089     Operands.push_back(ARMOperand::CreateCondCode(
5090                          ARMCC::CondCodes(PredicationCode), Loc));
5091   }
5092 
5093   // Add the processor imod operand, if necessary.
5094   if (ProcessorIMod) {
5095     Operands.push_back(ARMOperand::CreateImm(
5096           MCConstantExpr::Create(ProcessorIMod, getContext()),
5097                                  NameLoc, NameLoc));
5098   }
5099 
5100   // Add the remaining tokens in the mnemonic.
5101   while (Next != StringRef::npos) {
5102     Start = Next;
5103     Next = Name.find('.', Start + 1);
5104     StringRef ExtraToken = Name.slice(Start, Next);
5105 
5106     // Some NEON instructions have an optional datatype suffix that is
5107     // completely ignored. Check for that.
5108     if (isDataTypeToken(ExtraToken) &&
5109         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5110       continue;
5111 
5112     // For for ARM mode generate an error if the .n qualifier is used.
5113     if (ExtraToken == ".n" && !isThumb()) {
5114       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5115       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5116                    "arm mode");
5117     }
5118 
5119     // The .n qualifier is always discarded as that is what the tables
5120     // and matcher expect.  In ARM mode the .w qualifier has no effect,
5121     // so discard it to avoid errors that can be caused by the matcher.
5122     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5123       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5124       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5125     }
5126   }
5127 
5128   // Read the remaining operands.
5129   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5130     // Read the first operand.
5131     if (parseOperand(Operands, Mnemonic)) {
5132       Parser.eatToEndOfStatement();
5133       return true;
5134     }
5135 
5136     while (getLexer().is(AsmToken::Comma)) {
5137       Parser.Lex();  // Eat the comma.
5138 
5139       // Parse and remember the operand.
5140       if (parseOperand(Operands, Mnemonic)) {
5141         Parser.eatToEndOfStatement();
5142         return true;
5143       }
5144     }
5145   }
5146 
5147   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5148     SMLoc Loc = getLexer().getLoc();
5149     Parser.eatToEndOfStatement();
5150     return Error(Loc, "unexpected token in argument list");
5151   }
5152 
5153   Parser.Lex(); // Consume the EndOfStatement
5154 
5155   // Some instructions, mostly Thumb, have forms for the same mnemonic that
5156   // do and don't have a cc_out optional-def operand. With some spot-checks
5157   // of the operand list, we can figure out which variant we're trying to
5158   // parse and adjust accordingly before actually matching. We shouldn't ever
5159   // try to remove a cc_out operand that was explicitly set on the the
5160   // mnemonic, of course (CarrySetting == true). Reason number #317 the
5161   // table driven matcher doesn't fit well with the ARM instruction set.
5162   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5163     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5164     Operands.erase(Operands.begin() + 1);
5165     delete Op;
5166   }
5167 
5168   // Some instructions have the same mnemonic, but don't always
5169   // have a predicate. Distinguish them here and delete the
5170   // predicate if needed.
5171   if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5172     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5173     Operands.erase(Operands.begin() + 1);
5174     delete Op;
5175   }
5176 
5177   // ARM mode 'blx' need special handling, as the register operand version
5178   // is predicable, but the label operand version is not. So, we can't rely
5179   // on the Mnemonic based checking to correctly figure out when to put
5180   // a k_CondCode operand in the list. If we're trying to match the label
5181   // version, remove the k_CondCode operand here.
5182   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5183       static_cast<ARMOperand*>(Operands[2])->isImm()) {
5184     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5185     Operands.erase(Operands.begin() + 1);
5186     delete Op;
5187   }
5188 
5189   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5190   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5191   // a single GPRPair reg operand is used in the .td file to replace the two
5192   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5193   // expressed as a GPRPair, so we have to manually merge them.
5194   // FIXME: We would really like to be able to tablegen'erate this.
5195   if (!isThumb() && Operands.size() > 4 &&
5196       (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5197     bool isLoad = (Mnemonic == "ldrexd");
5198     unsigned Idx = isLoad ? 2 : 3;
5199     ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5200     ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5201 
5202     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5203     // Adjust only if Op1 and Op2 are GPRs.
5204     if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5205         MRC.contains(Op2->getReg())) {
5206       unsigned Reg1 = Op1->getReg();
5207       unsigned Reg2 = Op2->getReg();
5208       unsigned Rt = MRI->getEncodingValue(Reg1);
5209       unsigned Rt2 = MRI->getEncodingValue(Reg2);
5210 
5211       // Rt2 must be Rt + 1 and Rt must be even.
5212       if (Rt + 1 != Rt2 || (Rt & 1)) {
5213         Error(Op2->getStartLoc(), isLoad ?
5214             "destination operands must be sequential" :
5215             "source operands must be sequential");
5216         return true;
5217       }
5218       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5219           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5220       Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5221       Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5222             NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5223       delete Op1;
5224       delete Op2;
5225     }
5226   }
5227 
5228   // FIXME: As said above, this is all a pretty gross hack.  This instruction
5229   // does not fit with other "subs" and tblgen.
5230   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5231   // so the Mnemonic is the original name "subs" and delete the predicate
5232   // operand so it will match the table entry.
5233   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5234       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5235       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5236       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5237       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5238       static_cast<ARMOperand*>(Operands[5])->isImm()) {
5239     ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5240     Operands.erase(Operands.begin());
5241     delete Op0;
5242     Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5243 
5244     ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5245     Operands.erase(Operands.begin() + 1);
5246     delete Op1;
5247   }
5248   return false;
5249 }
5250 
5251 // Validate context-sensitive operand constraints.
5252 
5253 // return 'true' if register list contains non-low GPR registers,
5254 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5255 // 'containsReg' to true.
5256 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5257                                  unsigned HiReg, bool &containsReg) {
5258   containsReg = false;
5259   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5260     unsigned OpReg = Inst.getOperand(i).getReg();
5261     if (OpReg == Reg)
5262       containsReg = true;
5263     // Anything other than a low register isn't legal here.
5264     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5265       return true;
5266   }
5267   return false;
5268 }
5269 
5270 // Check if the specified regisgter is in the register list of the inst,
5271 // starting at the indicated operand number.
5272 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5273   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5274     unsigned OpReg = Inst.getOperand(i).getReg();
5275     if (OpReg == Reg)
5276       return true;
5277   }
5278   return false;
5279 }
5280 
5281 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5282 // the ARMInsts array) instead. Getting that here requires awkward
5283 // API changes, though. Better way?
5284 namespace llvm {
5285 extern const MCInstrDesc ARMInsts[];
5286 }
5287 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5288   return ARMInsts[Opcode];
5289 }
5290 
5291 // FIXME: We would really like to be able to tablegen'erate this.
5292 bool ARMAsmParser::
5293 validateInstruction(MCInst &Inst,
5294                     const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5295   const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5296   SMLoc Loc = Operands[0]->getStartLoc();
5297 
5298   // Check the IT block state first.
5299   // NOTE: BKPT instruction has the interesting property of being
5300   // allowed in IT blocks, but not being predicable.  It just always
5301   // executes.
5302   if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5303       Inst.getOpcode() != ARM::BKPT) {
5304     unsigned bit = 1;
5305     if (ITState.FirstCond)
5306       ITState.FirstCond = false;
5307     else
5308       bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5309     // The instruction must be predicable.
5310     if (!MCID.isPredicable())
5311       return Error(Loc, "instructions in IT block must be predicable");
5312     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5313     unsigned ITCond = bit ? ITState.Cond :
5314       ARMCC::getOppositeCondition(ITState.Cond);
5315     if (Cond != ITCond) {
5316       // Find the condition code Operand to get its SMLoc information.
5317       SMLoc CondLoc;
5318       for (unsigned i = 1; i < Operands.size(); ++i)
5319         if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5320           CondLoc = Operands[i]->getStartLoc();
5321       return Error(CondLoc, "incorrect condition in IT block; got '" +
5322                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5323                    "', but expected '" +
5324                    ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5325     }
5326   // Check for non-'al' condition codes outside of the IT block.
5327   } else if (isThumbTwo() && MCID.isPredicable() &&
5328              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5329              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5330              Inst.getOpcode() != ARM::t2Bcc)
5331     return Error(Loc, "predicated instructions must be in IT block");
5332 
5333   switch (Inst.getOpcode()) {
5334   case ARM::LDRD:
5335   case ARM::LDRD_PRE:
5336   case ARM::LDRD_POST: {
5337     // Rt2 must be Rt + 1.
5338     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5339     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5340     if (Rt2 != Rt + 1)
5341       return Error(Operands[3]->getStartLoc(),
5342                    "destination operands must be sequential");
5343     return false;
5344   }
5345   case ARM::STRD: {
5346     // Rt2 must be Rt + 1.
5347     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5348     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5349     if (Rt2 != Rt + 1)
5350       return Error(Operands[3]->getStartLoc(),
5351                    "source operands must be sequential");
5352     return false;
5353   }
5354   case ARM::STRD_PRE:
5355   case ARM::STRD_POST: {
5356     // Rt2 must be Rt + 1.
5357     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5358     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5359     if (Rt2 != Rt + 1)
5360       return Error(Operands[3]->getStartLoc(),
5361                    "source operands must be sequential");
5362     return false;
5363   }
5364   case ARM::SBFX:
5365   case ARM::UBFX: {
5366     // width must be in range [1, 32-lsb]
5367     unsigned lsb = Inst.getOperand(2).getImm();
5368     unsigned widthm1 = Inst.getOperand(3).getImm();
5369     if (widthm1 >= 32 - lsb)
5370       return Error(Operands[5]->getStartLoc(),
5371                    "bitfield width must be in range [1,32-lsb]");
5372     return false;
5373   }
5374   case ARM::tLDMIA: {
5375     // If we're parsing Thumb2, the .w variant is available and handles
5376     // most cases that are normally illegal for a Thumb1 LDM
5377     // instruction. We'll make the transformation in processInstruction()
5378     // if necessary.
5379     //
5380     // Thumb LDM instructions are writeback iff the base register is not
5381     // in the register list.
5382     unsigned Rn = Inst.getOperand(0).getReg();
5383     bool hasWritebackToken =
5384       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5385        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5386     bool listContainsBase;
5387     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5388       return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5389                    "registers must be in range r0-r7");
5390     // If we should have writeback, then there should be a '!' token.
5391     if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5392       return Error(Operands[2]->getStartLoc(),
5393                    "writeback operator '!' expected");
5394     // If we should not have writeback, there must not be a '!'. This is
5395     // true even for the 32-bit wide encodings.
5396     if (listContainsBase && hasWritebackToken)
5397       return Error(Operands[3]->getStartLoc(),
5398                    "writeback operator '!' not allowed when base register "
5399                    "in register list");
5400 
5401     break;
5402   }
5403   case ARM::t2LDMIA_UPD: {
5404     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5405       return Error(Operands[4]->getStartLoc(),
5406                    "writeback operator '!' not allowed when base register "
5407                    "in register list");
5408     break;
5409   }
5410   case ARM::tMUL: {
5411     // The second source operand must be the same register as the destination
5412     // operand.
5413     //
5414     // In this case, we must directly check the parsed operands because the
5415     // cvtThumbMultiply() function is written in such a way that it guarantees
5416     // this first statement is always true for the new Inst.  Essentially, the
5417     // destination is unconditionally copied into the second source operand
5418     // without checking to see if it matches what we actually parsed.
5419     if (Operands.size() == 6 &&
5420         (((ARMOperand*)Operands[3])->getReg() !=
5421          ((ARMOperand*)Operands[5])->getReg()) &&
5422         (((ARMOperand*)Operands[3])->getReg() !=
5423          ((ARMOperand*)Operands[4])->getReg())) {
5424       return Error(Operands[3]->getStartLoc(),
5425                    "destination register must match source register");
5426     }
5427     break;
5428   }
5429   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5430   // so only issue a diagnostic for thumb1. The instructions will be
5431   // switched to the t2 encodings in processInstruction() if necessary.
5432   case ARM::tPOP: {
5433     bool listContainsBase;
5434     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5435         !isThumbTwo())
5436       return Error(Operands[2]->getStartLoc(),
5437                    "registers must be in range r0-r7 or pc");
5438     break;
5439   }
5440   case ARM::tPUSH: {
5441     bool listContainsBase;
5442     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5443         !isThumbTwo())
5444       return Error(Operands[2]->getStartLoc(),
5445                    "registers must be in range r0-r7 or lr");
5446     break;
5447   }
5448   case ARM::tSTMIA_UPD: {
5449     bool listContainsBase;
5450     if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5451       return Error(Operands[4]->getStartLoc(),
5452                    "registers must be in range r0-r7");
5453     break;
5454   }
5455   case ARM::tADDrSP: {
5456     // If the non-SP source operand and the destination operand are not the
5457     // same, we need thumb2 (for the wide encoding), or we have an error.
5458     if (!isThumbTwo() &&
5459         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5460       return Error(Operands[4]->getStartLoc(),
5461                    "source register must be the same as destination");
5462     }
5463     break;
5464   }
5465   // final range checking for Thumb unconditional branch instructions
5466   case ARM::tB:
5467     if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5468       return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5469     break;
5470   case ARM::t2B: {
5471     int op = (Operands[2]->isImm()) ? 2 : 3;
5472     if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5473       return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5474     break;
5475   }
5476   // final range checking for Thumb conditional branch instructions
5477   case ARM::tBcc:
5478     if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5479       return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5480     break;
5481   case ARM::t2Bcc: {
5482     int op = (Operands[2]->isImm()) ? 2 : 3;
5483     if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<20, 1>())
5484       return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5485     break;
5486   }
5487   }
5488 
5489   StringRef DepInfo;
5490   if (isDeprecated(Inst, DepInfo))
5491     Warning(Loc, "deprecated on " + DepInfo);
5492 
5493   return false;
5494 }
5495 
5496 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5497   switch(Opc) {
5498   default: llvm_unreachable("unexpected opcode!");
5499   // VST1LN
5500   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5501   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5502   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5503   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5504   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5505   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5506   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5507   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5508   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5509 
5510   // VST2LN
5511   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5512   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5513   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5514   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5515   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5516 
5517   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5518   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5519   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5520   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5521   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5522 
5523   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5524   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5525   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5526   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5527   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5528 
5529   // VST3LN
5530   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5531   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5532   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5533   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5534   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5535   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5536   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5537   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5538   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5539   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5540   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5541   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5542   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5543   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5544   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5545 
5546   // VST3
5547   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5548   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5549   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5550   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5551   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5552   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5553   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5554   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5555   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5556   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5557   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5558   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5559   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5560   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5561   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5562   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5563   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5564   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5565 
5566   // VST4LN
5567   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5568   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5569   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5570   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5571   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5572   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5573   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5574   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5575   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5576   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5577   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5578   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5579   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5580   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5581   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5582 
5583   // VST4
5584   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5585   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5586   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5587   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5588   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5589   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5590   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5591   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5592   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5593   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5594   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5595   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5596   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5597   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5598   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5599   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5600   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5601   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5602   }
5603 }
5604 
5605 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5606   switch(Opc) {
5607   default: llvm_unreachable("unexpected opcode!");
5608   // VLD1LN
5609   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5610   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5611   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5612   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5613   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5614   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5615   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5616   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5617   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5618 
5619   // VLD2LN
5620   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5621   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5622   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5623   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5624   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5625   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5626   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5627   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5628   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5629   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5630   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5631   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5632   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5633   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5634   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5635 
5636   // VLD3DUP
5637   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5638   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5639   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5640   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5641   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5642   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5643   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5644   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5645   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5646   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5647   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5648   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5649   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5650   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5651   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5652   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5653   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5654   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5655 
5656   // VLD3LN
5657   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5658   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5659   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5660   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5661   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5662   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5663   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5664   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5665   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5666   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5667   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5668   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5669   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5670   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5671   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5672 
5673   // VLD3
5674   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5675   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5676   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5677   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5678   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5679   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5680   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5681   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5682   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5683   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5684   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5685   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5686   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5687   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5688   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5689   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5690   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5691   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5692 
5693   // VLD4LN
5694   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5695   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5696   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5697   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5698   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5699   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5700   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5701   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5702   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5703   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5704   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5705   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5706   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5707   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5708   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5709 
5710   // VLD4DUP
5711   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5712   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5713   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5714   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5715   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5716   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5717   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5718   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5719   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5720   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5721   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5722   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5723   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5724   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5725   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5726   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5727   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5728   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5729 
5730   // VLD4
5731   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5732   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5733   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5734   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5735   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5736   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5737   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5738   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5739   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5740   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5741   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5742   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5743   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5744   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5745   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5746   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5747   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5748   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5749   }
5750 }
5751 
5752 bool ARMAsmParser::
5753 processInstruction(MCInst &Inst,
5754                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5755   switch (Inst.getOpcode()) {
5756   // Alias for alternate form of 'ADR Rd, #imm' instruction.
5757   case ARM::ADDri: {
5758     if (Inst.getOperand(1).getReg() != ARM::PC ||
5759         Inst.getOperand(5).getReg() != 0)
5760       return false;
5761     MCInst TmpInst;
5762     TmpInst.setOpcode(ARM::ADR);
5763     TmpInst.addOperand(Inst.getOperand(0));
5764     TmpInst.addOperand(Inst.getOperand(2));
5765     TmpInst.addOperand(Inst.getOperand(3));
5766     TmpInst.addOperand(Inst.getOperand(4));
5767     Inst = TmpInst;
5768     return true;
5769   }
5770   // Aliases for alternate PC+imm syntax of LDR instructions.
5771   case ARM::t2LDRpcrel:
5772     // Select the narrow version if the immediate will fit.
5773     if (Inst.getOperand(1).getImm() > 0 &&
5774         Inst.getOperand(1).getImm() <= 0xff &&
5775         !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5776          static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5777       Inst.setOpcode(ARM::tLDRpci);
5778     else
5779       Inst.setOpcode(ARM::t2LDRpci);
5780     return true;
5781   case ARM::t2LDRBpcrel:
5782     Inst.setOpcode(ARM::t2LDRBpci);
5783     return true;
5784   case ARM::t2LDRHpcrel:
5785     Inst.setOpcode(ARM::t2LDRHpci);
5786     return true;
5787   case ARM::t2LDRSBpcrel:
5788     Inst.setOpcode(ARM::t2LDRSBpci);
5789     return true;
5790   case ARM::t2LDRSHpcrel:
5791     Inst.setOpcode(ARM::t2LDRSHpci);
5792     return true;
5793   // Handle NEON VST complex aliases.
5794   case ARM::VST1LNdWB_register_Asm_8:
5795   case ARM::VST1LNdWB_register_Asm_16:
5796   case ARM::VST1LNdWB_register_Asm_32: {
5797     MCInst TmpInst;
5798     // Shuffle the operands around so the lane index operand is in the
5799     // right place.
5800     unsigned Spacing;
5801     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5802     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5803     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5804     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5805     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5806     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5807     TmpInst.addOperand(Inst.getOperand(1)); // lane
5808     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5809     TmpInst.addOperand(Inst.getOperand(6));
5810     Inst = TmpInst;
5811     return true;
5812   }
5813 
5814   case ARM::VST2LNdWB_register_Asm_8:
5815   case ARM::VST2LNdWB_register_Asm_16:
5816   case ARM::VST2LNdWB_register_Asm_32:
5817   case ARM::VST2LNqWB_register_Asm_16:
5818   case ARM::VST2LNqWB_register_Asm_32: {
5819     MCInst TmpInst;
5820     // Shuffle the operands around so the lane index operand is in the
5821     // right place.
5822     unsigned Spacing;
5823     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5824     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5825     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5826     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5827     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5828     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5829     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5830                                             Spacing));
5831     TmpInst.addOperand(Inst.getOperand(1)); // lane
5832     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5833     TmpInst.addOperand(Inst.getOperand(6));
5834     Inst = TmpInst;
5835     return true;
5836   }
5837 
5838   case ARM::VST3LNdWB_register_Asm_8:
5839   case ARM::VST3LNdWB_register_Asm_16:
5840   case ARM::VST3LNdWB_register_Asm_32:
5841   case ARM::VST3LNqWB_register_Asm_16:
5842   case ARM::VST3LNqWB_register_Asm_32: {
5843     MCInst TmpInst;
5844     // Shuffle the operands around so the lane index operand is in the
5845     // right place.
5846     unsigned Spacing;
5847     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5848     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5849     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5850     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5851     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5852     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5853     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5854                                             Spacing));
5855     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5856                                             Spacing * 2));
5857     TmpInst.addOperand(Inst.getOperand(1)); // lane
5858     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5859     TmpInst.addOperand(Inst.getOperand(6));
5860     Inst = TmpInst;
5861     return true;
5862   }
5863 
5864   case ARM::VST4LNdWB_register_Asm_8:
5865   case ARM::VST4LNdWB_register_Asm_16:
5866   case ARM::VST4LNdWB_register_Asm_32:
5867   case ARM::VST4LNqWB_register_Asm_16:
5868   case ARM::VST4LNqWB_register_Asm_32: {
5869     MCInst TmpInst;
5870     // Shuffle the operands around so the lane index operand is in the
5871     // right place.
5872     unsigned Spacing;
5873     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5874     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5875     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5876     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5877     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5878     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5879     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5880                                             Spacing));
5881     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5882                                             Spacing * 2));
5883     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5884                                             Spacing * 3));
5885     TmpInst.addOperand(Inst.getOperand(1)); // lane
5886     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5887     TmpInst.addOperand(Inst.getOperand(6));
5888     Inst = TmpInst;
5889     return true;
5890   }
5891 
5892   case ARM::VST1LNdWB_fixed_Asm_8:
5893   case ARM::VST1LNdWB_fixed_Asm_16:
5894   case ARM::VST1LNdWB_fixed_Asm_32: {
5895     MCInst TmpInst;
5896     // Shuffle the operands around so the lane index operand is in the
5897     // right place.
5898     unsigned Spacing;
5899     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5900     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5901     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5902     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5903     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5904     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5905     TmpInst.addOperand(Inst.getOperand(1)); // lane
5906     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5907     TmpInst.addOperand(Inst.getOperand(5));
5908     Inst = TmpInst;
5909     return true;
5910   }
5911 
5912   case ARM::VST2LNdWB_fixed_Asm_8:
5913   case ARM::VST2LNdWB_fixed_Asm_16:
5914   case ARM::VST2LNdWB_fixed_Asm_32:
5915   case ARM::VST2LNqWB_fixed_Asm_16:
5916   case ARM::VST2LNqWB_fixed_Asm_32: {
5917     MCInst TmpInst;
5918     // Shuffle the operands around so the lane index operand is in the
5919     // right place.
5920     unsigned Spacing;
5921     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5922     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5923     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5924     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5925     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5926     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5927     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5928                                             Spacing));
5929     TmpInst.addOperand(Inst.getOperand(1)); // lane
5930     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5931     TmpInst.addOperand(Inst.getOperand(5));
5932     Inst = TmpInst;
5933     return true;
5934   }
5935 
5936   case ARM::VST3LNdWB_fixed_Asm_8:
5937   case ARM::VST3LNdWB_fixed_Asm_16:
5938   case ARM::VST3LNdWB_fixed_Asm_32:
5939   case ARM::VST3LNqWB_fixed_Asm_16:
5940   case ARM::VST3LNqWB_fixed_Asm_32: {
5941     MCInst TmpInst;
5942     // Shuffle the operands around so the lane index operand is in the
5943     // right place.
5944     unsigned Spacing;
5945     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5946     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5947     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5948     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5949     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5950     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5951     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5952                                             Spacing));
5953     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5954                                             Spacing * 2));
5955     TmpInst.addOperand(Inst.getOperand(1)); // lane
5956     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5957     TmpInst.addOperand(Inst.getOperand(5));
5958     Inst = TmpInst;
5959     return true;
5960   }
5961 
5962   case ARM::VST4LNdWB_fixed_Asm_8:
5963   case ARM::VST4LNdWB_fixed_Asm_16:
5964   case ARM::VST4LNdWB_fixed_Asm_32:
5965   case ARM::VST4LNqWB_fixed_Asm_16:
5966   case ARM::VST4LNqWB_fixed_Asm_32: {
5967     MCInst TmpInst;
5968     // Shuffle the operands around so the lane index operand is in the
5969     // right place.
5970     unsigned Spacing;
5971     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5972     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5973     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5974     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5975     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5976     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5977     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5978                                             Spacing));
5979     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5980                                             Spacing * 2));
5981     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5982                                             Spacing * 3));
5983     TmpInst.addOperand(Inst.getOperand(1)); // lane
5984     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5985     TmpInst.addOperand(Inst.getOperand(5));
5986     Inst = TmpInst;
5987     return true;
5988   }
5989 
5990   case ARM::VST1LNdAsm_8:
5991   case ARM::VST1LNdAsm_16:
5992   case ARM::VST1LNdAsm_32: {
5993     MCInst TmpInst;
5994     // Shuffle the operands around so the lane index operand is in the
5995     // right place.
5996     unsigned Spacing;
5997     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5998     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5999     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6000     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6001     TmpInst.addOperand(Inst.getOperand(1)); // lane
6002     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6003     TmpInst.addOperand(Inst.getOperand(5));
6004     Inst = TmpInst;
6005     return true;
6006   }
6007 
6008   case ARM::VST2LNdAsm_8:
6009   case ARM::VST2LNdAsm_16:
6010   case ARM::VST2LNdAsm_32:
6011   case ARM::VST2LNqAsm_16:
6012   case ARM::VST2LNqAsm_32: {
6013     MCInst TmpInst;
6014     // Shuffle the operands around so the lane index operand is in the
6015     // right place.
6016     unsigned Spacing;
6017     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6018     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6019     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6020     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6021     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6022                                             Spacing));
6023     TmpInst.addOperand(Inst.getOperand(1)); // lane
6024     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6025     TmpInst.addOperand(Inst.getOperand(5));
6026     Inst = TmpInst;
6027     return true;
6028   }
6029 
6030   case ARM::VST3LNdAsm_8:
6031   case ARM::VST3LNdAsm_16:
6032   case ARM::VST3LNdAsm_32:
6033   case ARM::VST3LNqAsm_16:
6034   case ARM::VST3LNqAsm_32: {
6035     MCInst TmpInst;
6036     // Shuffle the operands around so the lane index operand is in the
6037     // right place.
6038     unsigned Spacing;
6039     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6040     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6041     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6042     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6043     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6044                                             Spacing));
6045     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6046                                             Spacing * 2));
6047     TmpInst.addOperand(Inst.getOperand(1)); // lane
6048     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6049     TmpInst.addOperand(Inst.getOperand(5));
6050     Inst = TmpInst;
6051     return true;
6052   }
6053 
6054   case ARM::VST4LNdAsm_8:
6055   case ARM::VST4LNdAsm_16:
6056   case ARM::VST4LNdAsm_32:
6057   case ARM::VST4LNqAsm_16:
6058   case ARM::VST4LNqAsm_32: {
6059     MCInst TmpInst;
6060     // Shuffle the operands around so the lane index operand is in the
6061     // right place.
6062     unsigned Spacing;
6063     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6064     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6065     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6066     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6067     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6068                                             Spacing));
6069     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6070                                             Spacing * 2));
6071     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6072                                             Spacing * 3));
6073     TmpInst.addOperand(Inst.getOperand(1)); // lane
6074     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6075     TmpInst.addOperand(Inst.getOperand(5));
6076     Inst = TmpInst;
6077     return true;
6078   }
6079 
6080   // Handle NEON VLD complex aliases.
6081   case ARM::VLD1LNdWB_register_Asm_8:
6082   case ARM::VLD1LNdWB_register_Asm_16:
6083   case ARM::VLD1LNdWB_register_Asm_32: {
6084     MCInst TmpInst;
6085     // Shuffle the operands around so the lane index operand is in the
6086     // right place.
6087     unsigned Spacing;
6088     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6089     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6090     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6091     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6092     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6093     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6094     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6095     TmpInst.addOperand(Inst.getOperand(1)); // lane
6096     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6097     TmpInst.addOperand(Inst.getOperand(6));
6098     Inst = TmpInst;
6099     return true;
6100   }
6101 
6102   case ARM::VLD2LNdWB_register_Asm_8:
6103   case ARM::VLD2LNdWB_register_Asm_16:
6104   case ARM::VLD2LNdWB_register_Asm_32:
6105   case ARM::VLD2LNqWB_register_Asm_16:
6106   case ARM::VLD2LNqWB_register_Asm_32: {
6107     MCInst TmpInst;
6108     // Shuffle the operands around so the lane index operand is in the
6109     // right place.
6110     unsigned Spacing;
6111     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6112     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6113     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6114                                             Spacing));
6115     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6116     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6117     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6118     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6119     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6120     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6121                                             Spacing));
6122     TmpInst.addOperand(Inst.getOperand(1)); // lane
6123     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6124     TmpInst.addOperand(Inst.getOperand(6));
6125     Inst = TmpInst;
6126     return true;
6127   }
6128 
6129   case ARM::VLD3LNdWB_register_Asm_8:
6130   case ARM::VLD3LNdWB_register_Asm_16:
6131   case ARM::VLD3LNdWB_register_Asm_32:
6132   case ARM::VLD3LNqWB_register_Asm_16:
6133   case ARM::VLD3LNqWB_register_Asm_32: {
6134     MCInst TmpInst;
6135     // Shuffle the operands around so the lane index operand is in the
6136     // right place.
6137     unsigned Spacing;
6138     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6139     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6140     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6141                                             Spacing));
6142     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6143                                             Spacing * 2));
6144     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6145     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6146     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6147     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6148     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6149     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6150                                             Spacing));
6151     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6152                                             Spacing * 2));
6153     TmpInst.addOperand(Inst.getOperand(1)); // lane
6154     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6155     TmpInst.addOperand(Inst.getOperand(6));
6156     Inst = TmpInst;
6157     return true;
6158   }
6159 
6160   case ARM::VLD4LNdWB_register_Asm_8:
6161   case ARM::VLD4LNdWB_register_Asm_16:
6162   case ARM::VLD4LNdWB_register_Asm_32:
6163   case ARM::VLD4LNqWB_register_Asm_16:
6164   case ARM::VLD4LNqWB_register_Asm_32: {
6165     MCInst TmpInst;
6166     // Shuffle the operands around so the lane index operand is in the
6167     // right place.
6168     unsigned Spacing;
6169     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6170     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6171     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6172                                             Spacing));
6173     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6174                                             Spacing * 2));
6175     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6176                                             Spacing * 3));
6177     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6178     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6179     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6180     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6181     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6182     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6183                                             Spacing));
6184     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6185                                             Spacing * 2));
6186     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6187                                             Spacing * 3));
6188     TmpInst.addOperand(Inst.getOperand(1)); // lane
6189     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6190     TmpInst.addOperand(Inst.getOperand(6));
6191     Inst = TmpInst;
6192     return true;
6193   }
6194 
6195   case ARM::VLD1LNdWB_fixed_Asm_8:
6196   case ARM::VLD1LNdWB_fixed_Asm_16:
6197   case ARM::VLD1LNdWB_fixed_Asm_32: {
6198     MCInst TmpInst;
6199     // Shuffle the operands around so the lane index operand is in the
6200     // right place.
6201     unsigned Spacing;
6202     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6203     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6204     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6205     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6206     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6207     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6208     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6209     TmpInst.addOperand(Inst.getOperand(1)); // lane
6210     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6211     TmpInst.addOperand(Inst.getOperand(5));
6212     Inst = TmpInst;
6213     return true;
6214   }
6215 
6216   case ARM::VLD2LNdWB_fixed_Asm_8:
6217   case ARM::VLD2LNdWB_fixed_Asm_16:
6218   case ARM::VLD2LNdWB_fixed_Asm_32:
6219   case ARM::VLD2LNqWB_fixed_Asm_16:
6220   case ARM::VLD2LNqWB_fixed_Asm_32: {
6221     MCInst TmpInst;
6222     // Shuffle the operands around so the lane index operand is in the
6223     // right place.
6224     unsigned Spacing;
6225     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6226     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6227     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6228                                             Spacing));
6229     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6230     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6231     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6232     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6233     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6234     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6235                                             Spacing));
6236     TmpInst.addOperand(Inst.getOperand(1)); // lane
6237     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6238     TmpInst.addOperand(Inst.getOperand(5));
6239     Inst = TmpInst;
6240     return true;
6241   }
6242 
6243   case ARM::VLD3LNdWB_fixed_Asm_8:
6244   case ARM::VLD3LNdWB_fixed_Asm_16:
6245   case ARM::VLD3LNdWB_fixed_Asm_32:
6246   case ARM::VLD3LNqWB_fixed_Asm_16:
6247   case ARM::VLD3LNqWB_fixed_Asm_32: {
6248     MCInst TmpInst;
6249     // Shuffle the operands around so the lane index operand is in the
6250     // right place.
6251     unsigned Spacing;
6252     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6253     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6254     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6255                                             Spacing));
6256     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6257                                             Spacing * 2));
6258     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6259     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6260     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6261     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6262     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6263     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6264                                             Spacing));
6265     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6266                                             Spacing * 2));
6267     TmpInst.addOperand(Inst.getOperand(1)); // lane
6268     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6269     TmpInst.addOperand(Inst.getOperand(5));
6270     Inst = TmpInst;
6271     return true;
6272   }
6273 
6274   case ARM::VLD4LNdWB_fixed_Asm_8:
6275   case ARM::VLD4LNdWB_fixed_Asm_16:
6276   case ARM::VLD4LNdWB_fixed_Asm_32:
6277   case ARM::VLD4LNqWB_fixed_Asm_16:
6278   case ARM::VLD4LNqWB_fixed_Asm_32: {
6279     MCInst TmpInst;
6280     // Shuffle the operands around so the lane index operand is in the
6281     // right place.
6282     unsigned Spacing;
6283     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6284     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6285     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6286                                             Spacing));
6287     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6288                                             Spacing * 2));
6289     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6290                                             Spacing * 3));
6291     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6292     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6293     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6294     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6295     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6296     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6297                                             Spacing));
6298     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6299                                             Spacing * 2));
6300     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6301                                             Spacing * 3));
6302     TmpInst.addOperand(Inst.getOperand(1)); // lane
6303     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6304     TmpInst.addOperand(Inst.getOperand(5));
6305     Inst = TmpInst;
6306     return true;
6307   }
6308 
6309   case ARM::VLD1LNdAsm_8:
6310   case ARM::VLD1LNdAsm_16:
6311   case ARM::VLD1LNdAsm_32: {
6312     MCInst TmpInst;
6313     // Shuffle the operands around so the lane index operand is in the
6314     // right place.
6315     unsigned Spacing;
6316     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6317     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6318     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6319     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6320     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6321     TmpInst.addOperand(Inst.getOperand(1)); // lane
6322     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6323     TmpInst.addOperand(Inst.getOperand(5));
6324     Inst = TmpInst;
6325     return true;
6326   }
6327 
6328   case ARM::VLD2LNdAsm_8:
6329   case ARM::VLD2LNdAsm_16:
6330   case ARM::VLD2LNdAsm_32:
6331   case ARM::VLD2LNqAsm_16:
6332   case ARM::VLD2LNqAsm_32: {
6333     MCInst TmpInst;
6334     // Shuffle the operands around so the lane index operand is in the
6335     // right place.
6336     unsigned Spacing;
6337     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6338     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6339     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6340                                             Spacing));
6341     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6342     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6343     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6344     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6345                                             Spacing));
6346     TmpInst.addOperand(Inst.getOperand(1)); // lane
6347     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6348     TmpInst.addOperand(Inst.getOperand(5));
6349     Inst = TmpInst;
6350     return true;
6351   }
6352 
6353   case ARM::VLD3LNdAsm_8:
6354   case ARM::VLD3LNdAsm_16:
6355   case ARM::VLD3LNdAsm_32:
6356   case ARM::VLD3LNqAsm_16:
6357   case ARM::VLD3LNqAsm_32: {
6358     MCInst TmpInst;
6359     // Shuffle the operands around so the lane index operand is in the
6360     // right place.
6361     unsigned Spacing;
6362     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6363     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6364     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6365                                             Spacing));
6366     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6367                                             Spacing * 2));
6368     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6369     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6370     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6371     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6372                                             Spacing));
6373     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6374                                             Spacing * 2));
6375     TmpInst.addOperand(Inst.getOperand(1)); // lane
6376     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6377     TmpInst.addOperand(Inst.getOperand(5));
6378     Inst = TmpInst;
6379     return true;
6380   }
6381 
6382   case ARM::VLD4LNdAsm_8:
6383   case ARM::VLD4LNdAsm_16:
6384   case ARM::VLD4LNdAsm_32:
6385   case ARM::VLD4LNqAsm_16:
6386   case ARM::VLD4LNqAsm_32: {
6387     MCInst TmpInst;
6388     // Shuffle the operands around so the lane index operand is in the
6389     // right place.
6390     unsigned Spacing;
6391     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6392     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6393     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6394                                             Spacing));
6395     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6396                                             Spacing * 2));
6397     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6398                                             Spacing * 3));
6399     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6400     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6401     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6402     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6403                                             Spacing));
6404     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6405                                             Spacing * 2));
6406     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6407                                             Spacing * 3));
6408     TmpInst.addOperand(Inst.getOperand(1)); // lane
6409     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6410     TmpInst.addOperand(Inst.getOperand(5));
6411     Inst = TmpInst;
6412     return true;
6413   }
6414 
6415   // VLD3DUP single 3-element structure to all lanes instructions.
6416   case ARM::VLD3DUPdAsm_8:
6417   case ARM::VLD3DUPdAsm_16:
6418   case ARM::VLD3DUPdAsm_32:
6419   case ARM::VLD3DUPqAsm_8:
6420   case ARM::VLD3DUPqAsm_16:
6421   case ARM::VLD3DUPqAsm_32: {
6422     MCInst TmpInst;
6423     unsigned Spacing;
6424     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6425     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6426     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6427                                             Spacing));
6428     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6429                                             Spacing * 2));
6430     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6431     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6432     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6433     TmpInst.addOperand(Inst.getOperand(4));
6434     Inst = TmpInst;
6435     return true;
6436   }
6437 
6438   case ARM::VLD3DUPdWB_fixed_Asm_8:
6439   case ARM::VLD3DUPdWB_fixed_Asm_16:
6440   case ARM::VLD3DUPdWB_fixed_Asm_32:
6441   case ARM::VLD3DUPqWB_fixed_Asm_8:
6442   case ARM::VLD3DUPqWB_fixed_Asm_16:
6443   case ARM::VLD3DUPqWB_fixed_Asm_32: {
6444     MCInst TmpInst;
6445     unsigned Spacing;
6446     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6447     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6448     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6449                                             Spacing));
6450     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6451                                             Spacing * 2));
6452     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6453     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6454     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6455     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6456     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6457     TmpInst.addOperand(Inst.getOperand(4));
6458     Inst = TmpInst;
6459     return true;
6460   }
6461 
6462   case ARM::VLD3DUPdWB_register_Asm_8:
6463   case ARM::VLD3DUPdWB_register_Asm_16:
6464   case ARM::VLD3DUPdWB_register_Asm_32:
6465   case ARM::VLD3DUPqWB_register_Asm_8:
6466   case ARM::VLD3DUPqWB_register_Asm_16:
6467   case ARM::VLD3DUPqWB_register_Asm_32: {
6468     MCInst TmpInst;
6469     unsigned Spacing;
6470     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6471     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6472     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6473                                             Spacing));
6474     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6475                                             Spacing * 2));
6476     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6477     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6478     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6479     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6480     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6481     TmpInst.addOperand(Inst.getOperand(5));
6482     Inst = TmpInst;
6483     return true;
6484   }
6485 
6486   // VLD3 multiple 3-element structure instructions.
6487   case ARM::VLD3dAsm_8:
6488   case ARM::VLD3dAsm_16:
6489   case ARM::VLD3dAsm_32:
6490   case ARM::VLD3qAsm_8:
6491   case ARM::VLD3qAsm_16:
6492   case ARM::VLD3qAsm_32: {
6493     MCInst TmpInst;
6494     unsigned Spacing;
6495     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6496     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6497     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6498                                             Spacing));
6499     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6500                                             Spacing * 2));
6501     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6502     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6503     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6504     TmpInst.addOperand(Inst.getOperand(4));
6505     Inst = TmpInst;
6506     return true;
6507   }
6508 
6509   case ARM::VLD3dWB_fixed_Asm_8:
6510   case ARM::VLD3dWB_fixed_Asm_16:
6511   case ARM::VLD3dWB_fixed_Asm_32:
6512   case ARM::VLD3qWB_fixed_Asm_8:
6513   case ARM::VLD3qWB_fixed_Asm_16:
6514   case ARM::VLD3qWB_fixed_Asm_32: {
6515     MCInst TmpInst;
6516     unsigned Spacing;
6517     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6518     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6519     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6520                                             Spacing));
6521     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6522                                             Spacing * 2));
6523     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6524     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6525     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6526     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6527     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6528     TmpInst.addOperand(Inst.getOperand(4));
6529     Inst = TmpInst;
6530     return true;
6531   }
6532 
6533   case ARM::VLD3dWB_register_Asm_8:
6534   case ARM::VLD3dWB_register_Asm_16:
6535   case ARM::VLD3dWB_register_Asm_32:
6536   case ARM::VLD3qWB_register_Asm_8:
6537   case ARM::VLD3qWB_register_Asm_16:
6538   case ARM::VLD3qWB_register_Asm_32: {
6539     MCInst TmpInst;
6540     unsigned Spacing;
6541     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6542     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6543     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6544                                             Spacing));
6545     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6546                                             Spacing * 2));
6547     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6548     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6549     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6550     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6551     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6552     TmpInst.addOperand(Inst.getOperand(5));
6553     Inst = TmpInst;
6554     return true;
6555   }
6556 
6557   // VLD4DUP single 3-element structure to all lanes instructions.
6558   case ARM::VLD4DUPdAsm_8:
6559   case ARM::VLD4DUPdAsm_16:
6560   case ARM::VLD4DUPdAsm_32:
6561   case ARM::VLD4DUPqAsm_8:
6562   case ARM::VLD4DUPqAsm_16:
6563   case ARM::VLD4DUPqAsm_32: {
6564     MCInst TmpInst;
6565     unsigned Spacing;
6566     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6567     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6568     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6569                                             Spacing));
6570     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6571                                             Spacing * 2));
6572     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6573                                             Spacing * 3));
6574     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6575     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6576     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6577     TmpInst.addOperand(Inst.getOperand(4));
6578     Inst = TmpInst;
6579     return true;
6580   }
6581 
6582   case ARM::VLD4DUPdWB_fixed_Asm_8:
6583   case ARM::VLD4DUPdWB_fixed_Asm_16:
6584   case ARM::VLD4DUPdWB_fixed_Asm_32:
6585   case ARM::VLD4DUPqWB_fixed_Asm_8:
6586   case ARM::VLD4DUPqWB_fixed_Asm_16:
6587   case ARM::VLD4DUPqWB_fixed_Asm_32: {
6588     MCInst TmpInst;
6589     unsigned Spacing;
6590     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6591     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6592     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6593                                             Spacing));
6594     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6595                                             Spacing * 2));
6596     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6597                                             Spacing * 3));
6598     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6599     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6600     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6601     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6602     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6603     TmpInst.addOperand(Inst.getOperand(4));
6604     Inst = TmpInst;
6605     return true;
6606   }
6607 
6608   case ARM::VLD4DUPdWB_register_Asm_8:
6609   case ARM::VLD4DUPdWB_register_Asm_16:
6610   case ARM::VLD4DUPdWB_register_Asm_32:
6611   case ARM::VLD4DUPqWB_register_Asm_8:
6612   case ARM::VLD4DUPqWB_register_Asm_16:
6613   case ARM::VLD4DUPqWB_register_Asm_32: {
6614     MCInst TmpInst;
6615     unsigned Spacing;
6616     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6617     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6618     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6619                                             Spacing));
6620     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6621                                             Spacing * 2));
6622     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6623                                             Spacing * 3));
6624     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6625     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6626     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6627     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6628     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6629     TmpInst.addOperand(Inst.getOperand(5));
6630     Inst = TmpInst;
6631     return true;
6632   }
6633 
6634   // VLD4 multiple 4-element structure instructions.
6635   case ARM::VLD4dAsm_8:
6636   case ARM::VLD4dAsm_16:
6637   case ARM::VLD4dAsm_32:
6638   case ARM::VLD4qAsm_8:
6639   case ARM::VLD4qAsm_16:
6640   case ARM::VLD4qAsm_32: {
6641     MCInst TmpInst;
6642     unsigned Spacing;
6643     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6644     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6645     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6646                                             Spacing));
6647     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6648                                             Spacing * 2));
6649     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6650                                             Spacing * 3));
6651     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6652     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6653     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6654     TmpInst.addOperand(Inst.getOperand(4));
6655     Inst = TmpInst;
6656     return true;
6657   }
6658 
6659   case ARM::VLD4dWB_fixed_Asm_8:
6660   case ARM::VLD4dWB_fixed_Asm_16:
6661   case ARM::VLD4dWB_fixed_Asm_32:
6662   case ARM::VLD4qWB_fixed_Asm_8:
6663   case ARM::VLD4qWB_fixed_Asm_16:
6664   case ARM::VLD4qWB_fixed_Asm_32: {
6665     MCInst TmpInst;
6666     unsigned Spacing;
6667     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6668     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6669     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670                                             Spacing));
6671     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6672                                             Spacing * 2));
6673     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6674                                             Spacing * 3));
6675     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6676     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6677     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6678     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6679     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6680     TmpInst.addOperand(Inst.getOperand(4));
6681     Inst = TmpInst;
6682     return true;
6683   }
6684 
6685   case ARM::VLD4dWB_register_Asm_8:
6686   case ARM::VLD4dWB_register_Asm_16:
6687   case ARM::VLD4dWB_register_Asm_32:
6688   case ARM::VLD4qWB_register_Asm_8:
6689   case ARM::VLD4qWB_register_Asm_16:
6690   case ARM::VLD4qWB_register_Asm_32: {
6691     MCInst TmpInst;
6692     unsigned Spacing;
6693     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6694     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6695     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6696                                             Spacing));
6697     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6698                                             Spacing * 2));
6699     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6700                                             Spacing * 3));
6701     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6702     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6703     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6704     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6705     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6706     TmpInst.addOperand(Inst.getOperand(5));
6707     Inst = TmpInst;
6708     return true;
6709   }
6710 
6711   // VST3 multiple 3-element structure instructions.
6712   case ARM::VST3dAsm_8:
6713   case ARM::VST3dAsm_16:
6714   case ARM::VST3dAsm_32:
6715   case ARM::VST3qAsm_8:
6716   case ARM::VST3qAsm_16:
6717   case ARM::VST3qAsm_32: {
6718     MCInst TmpInst;
6719     unsigned Spacing;
6720     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6721     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6722     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6723     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6724     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6725                                             Spacing));
6726     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6727                                             Spacing * 2));
6728     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6729     TmpInst.addOperand(Inst.getOperand(4));
6730     Inst = TmpInst;
6731     return true;
6732   }
6733 
6734   case ARM::VST3dWB_fixed_Asm_8:
6735   case ARM::VST3dWB_fixed_Asm_16:
6736   case ARM::VST3dWB_fixed_Asm_32:
6737   case ARM::VST3qWB_fixed_Asm_8:
6738   case ARM::VST3qWB_fixed_Asm_16:
6739   case ARM::VST3qWB_fixed_Asm_32: {
6740     MCInst TmpInst;
6741     unsigned Spacing;
6742     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6743     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6744     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6745     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6746     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6747     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6748     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6749                                             Spacing));
6750     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6751                                             Spacing * 2));
6752     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6753     TmpInst.addOperand(Inst.getOperand(4));
6754     Inst = TmpInst;
6755     return true;
6756   }
6757 
6758   case ARM::VST3dWB_register_Asm_8:
6759   case ARM::VST3dWB_register_Asm_16:
6760   case ARM::VST3dWB_register_Asm_32:
6761   case ARM::VST3qWB_register_Asm_8:
6762   case ARM::VST3qWB_register_Asm_16:
6763   case ARM::VST3qWB_register_Asm_32: {
6764     MCInst TmpInst;
6765     unsigned Spacing;
6766     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6767     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6768     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6769     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6770     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6771     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6772     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6773                                             Spacing));
6774     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6775                                             Spacing * 2));
6776     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6777     TmpInst.addOperand(Inst.getOperand(5));
6778     Inst = TmpInst;
6779     return true;
6780   }
6781 
6782   // VST4 multiple 3-element structure instructions.
6783   case ARM::VST4dAsm_8:
6784   case ARM::VST4dAsm_16:
6785   case ARM::VST4dAsm_32:
6786   case ARM::VST4qAsm_8:
6787   case ARM::VST4qAsm_16:
6788   case ARM::VST4qAsm_32: {
6789     MCInst TmpInst;
6790     unsigned Spacing;
6791     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6792     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6793     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6794     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6795     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6796                                             Spacing));
6797     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6798                                             Spacing * 2));
6799     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6800                                             Spacing * 3));
6801     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6802     TmpInst.addOperand(Inst.getOperand(4));
6803     Inst = TmpInst;
6804     return true;
6805   }
6806 
6807   case ARM::VST4dWB_fixed_Asm_8:
6808   case ARM::VST4dWB_fixed_Asm_16:
6809   case ARM::VST4dWB_fixed_Asm_32:
6810   case ARM::VST4qWB_fixed_Asm_8:
6811   case ARM::VST4qWB_fixed_Asm_16:
6812   case ARM::VST4qWB_fixed_Asm_32: {
6813     MCInst TmpInst;
6814     unsigned Spacing;
6815     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6816     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6817     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6818     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6819     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6820     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6821     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6822                                             Spacing));
6823     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6824                                             Spacing * 2));
6825     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6826                                             Spacing * 3));
6827     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6828     TmpInst.addOperand(Inst.getOperand(4));
6829     Inst = TmpInst;
6830     return true;
6831   }
6832 
6833   case ARM::VST4dWB_register_Asm_8:
6834   case ARM::VST4dWB_register_Asm_16:
6835   case ARM::VST4dWB_register_Asm_32:
6836   case ARM::VST4qWB_register_Asm_8:
6837   case ARM::VST4qWB_register_Asm_16:
6838   case ARM::VST4qWB_register_Asm_32: {
6839     MCInst TmpInst;
6840     unsigned Spacing;
6841     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6842     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6843     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6844     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6845     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6846     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6847     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6848                                             Spacing));
6849     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6850                                             Spacing * 2));
6851     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6852                                             Spacing * 3));
6853     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6854     TmpInst.addOperand(Inst.getOperand(5));
6855     Inst = TmpInst;
6856     return true;
6857   }
6858 
6859   // Handle encoding choice for the shift-immediate instructions.
6860   case ARM::t2LSLri:
6861   case ARM::t2LSRri:
6862   case ARM::t2ASRri: {
6863     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6864         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6865         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6866         !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6867          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6868       unsigned NewOpc;
6869       switch (Inst.getOpcode()) {
6870       default: llvm_unreachable("unexpected opcode");
6871       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6872       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6873       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6874       }
6875       // The Thumb1 operands aren't in the same order. Awesome, eh?
6876       MCInst TmpInst;
6877       TmpInst.setOpcode(NewOpc);
6878       TmpInst.addOperand(Inst.getOperand(0));
6879       TmpInst.addOperand(Inst.getOperand(5));
6880       TmpInst.addOperand(Inst.getOperand(1));
6881       TmpInst.addOperand(Inst.getOperand(2));
6882       TmpInst.addOperand(Inst.getOperand(3));
6883       TmpInst.addOperand(Inst.getOperand(4));
6884       Inst = TmpInst;
6885       return true;
6886     }
6887     return false;
6888   }
6889 
6890   // Handle the Thumb2 mode MOV complex aliases.
6891   case ARM::t2MOVsr:
6892   case ARM::t2MOVSsr: {
6893     // Which instruction to expand to depends on the CCOut operand and
6894     // whether we're in an IT block if the register operands are low
6895     // registers.
6896     bool isNarrow = false;
6897     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6898         isARMLowRegister(Inst.getOperand(1).getReg()) &&
6899         isARMLowRegister(Inst.getOperand(2).getReg()) &&
6900         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6901         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6902       isNarrow = true;
6903     MCInst TmpInst;
6904     unsigned newOpc;
6905     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6906     default: llvm_unreachable("unexpected opcode!");
6907     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6908     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6909     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6910     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6911     }
6912     TmpInst.setOpcode(newOpc);
6913     TmpInst.addOperand(Inst.getOperand(0)); // Rd
6914     if (isNarrow)
6915       TmpInst.addOperand(MCOperand::CreateReg(
6916           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6917     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6918     TmpInst.addOperand(Inst.getOperand(2)); // Rm
6919     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6920     TmpInst.addOperand(Inst.getOperand(5));
6921     if (!isNarrow)
6922       TmpInst.addOperand(MCOperand::CreateReg(
6923           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6924     Inst = TmpInst;
6925     return true;
6926   }
6927   case ARM::t2MOVsi:
6928   case ARM::t2MOVSsi: {
6929     // Which instruction to expand to depends on the CCOut operand and
6930     // whether we're in an IT block if the register operands are low
6931     // registers.
6932     bool isNarrow = false;
6933     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6934         isARMLowRegister(Inst.getOperand(1).getReg()) &&
6935         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6936       isNarrow = true;
6937     MCInst TmpInst;
6938     unsigned newOpc;
6939     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6940     default: llvm_unreachable("unexpected opcode!");
6941     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6942     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6943     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6944     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6945     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6946     }
6947     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6948     if (Amount == 32) Amount = 0;
6949     TmpInst.setOpcode(newOpc);
6950     TmpInst.addOperand(Inst.getOperand(0)); // Rd
6951     if (isNarrow)
6952       TmpInst.addOperand(MCOperand::CreateReg(
6953           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6954     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6955     if (newOpc != ARM::t2RRX)
6956       TmpInst.addOperand(MCOperand::CreateImm(Amount));
6957     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6958     TmpInst.addOperand(Inst.getOperand(4));
6959     if (!isNarrow)
6960       TmpInst.addOperand(MCOperand::CreateReg(
6961           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6962     Inst = TmpInst;
6963     return true;
6964   }
6965   // Handle the ARM mode MOV complex aliases.
6966   case ARM::ASRr:
6967   case ARM::LSRr:
6968   case ARM::LSLr:
6969   case ARM::RORr: {
6970     ARM_AM::ShiftOpc ShiftTy;
6971     switch(Inst.getOpcode()) {
6972     default: llvm_unreachable("unexpected opcode!");
6973     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6974     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6975     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6976     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6977     }
6978     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6979     MCInst TmpInst;
6980     TmpInst.setOpcode(ARM::MOVsr);
6981     TmpInst.addOperand(Inst.getOperand(0)); // Rd
6982     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6983     TmpInst.addOperand(Inst.getOperand(2)); // Rm
6984     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6985     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6986     TmpInst.addOperand(Inst.getOperand(4));
6987     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6988     Inst = TmpInst;
6989     return true;
6990   }
6991   case ARM::ASRi:
6992   case ARM::LSRi:
6993   case ARM::LSLi:
6994   case ARM::RORi: {
6995     ARM_AM::ShiftOpc ShiftTy;
6996     switch(Inst.getOpcode()) {
6997     default: llvm_unreachable("unexpected opcode!");
6998     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6999     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7000     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7001     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7002     }
7003     // A shift by zero is a plain MOVr, not a MOVsi.
7004     unsigned Amt = Inst.getOperand(2).getImm();
7005     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7006     // A shift by 32 should be encoded as 0 when permitted
7007     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7008       Amt = 0;
7009     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7010     MCInst TmpInst;
7011     TmpInst.setOpcode(Opc);
7012     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7013     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7014     if (Opc == ARM::MOVsi)
7015       TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7016     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7017     TmpInst.addOperand(Inst.getOperand(4));
7018     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7019     Inst = TmpInst;
7020     return true;
7021   }
7022   case ARM::RRXi: {
7023     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7024     MCInst TmpInst;
7025     TmpInst.setOpcode(ARM::MOVsi);
7026     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7027     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7028     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7029     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7030     TmpInst.addOperand(Inst.getOperand(3));
7031     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7032     Inst = TmpInst;
7033     return true;
7034   }
7035   case ARM::t2LDMIA_UPD: {
7036     // If this is a load of a single register, then we should use
7037     // a post-indexed LDR instruction instead, per the ARM ARM.
7038     if (Inst.getNumOperands() != 5)
7039       return false;
7040     MCInst TmpInst;
7041     TmpInst.setOpcode(ARM::t2LDR_POST);
7042     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7043     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7044     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7045     TmpInst.addOperand(MCOperand::CreateImm(4));
7046     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7047     TmpInst.addOperand(Inst.getOperand(3));
7048     Inst = TmpInst;
7049     return true;
7050   }
7051   case ARM::t2STMDB_UPD: {
7052     // If this is a store of a single register, then we should use
7053     // a pre-indexed STR instruction instead, per the ARM ARM.
7054     if (Inst.getNumOperands() != 5)
7055       return false;
7056     MCInst TmpInst;
7057     TmpInst.setOpcode(ARM::t2STR_PRE);
7058     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7059     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7060     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7061     TmpInst.addOperand(MCOperand::CreateImm(-4));
7062     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7063     TmpInst.addOperand(Inst.getOperand(3));
7064     Inst = TmpInst;
7065     return true;
7066   }
7067   case ARM::LDMIA_UPD:
7068     // If this is a load of a single register via a 'pop', then we should use
7069     // a post-indexed LDR instruction instead, per the ARM ARM.
7070     if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7071         Inst.getNumOperands() == 5) {
7072       MCInst TmpInst;
7073       TmpInst.setOpcode(ARM::LDR_POST_IMM);
7074       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7075       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7076       TmpInst.addOperand(Inst.getOperand(1)); // Rn
7077       TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7078       TmpInst.addOperand(MCOperand::CreateImm(4));
7079       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7080       TmpInst.addOperand(Inst.getOperand(3));
7081       Inst = TmpInst;
7082       return true;
7083     }
7084     break;
7085   case ARM::STMDB_UPD:
7086     // If this is a store of a single register via a 'push', then we should use
7087     // a pre-indexed STR instruction instead, per the ARM ARM.
7088     if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7089         Inst.getNumOperands() == 5) {
7090       MCInst TmpInst;
7091       TmpInst.setOpcode(ARM::STR_PRE_IMM);
7092       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7093       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7094       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7095       TmpInst.addOperand(MCOperand::CreateImm(-4));
7096       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7097       TmpInst.addOperand(Inst.getOperand(3));
7098       Inst = TmpInst;
7099     }
7100     break;
7101   case ARM::t2ADDri12:
7102     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7103     // mnemonic was used (not "addw"), encoding T3 is preferred.
7104     if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7105         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7106       break;
7107     Inst.setOpcode(ARM::t2ADDri);
7108     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7109     break;
7110   case ARM::t2SUBri12:
7111     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7112     // mnemonic was used (not "subw"), encoding T3 is preferred.
7113     if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7114         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7115       break;
7116     Inst.setOpcode(ARM::t2SUBri);
7117     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7118     break;
7119   case ARM::tADDi8:
7120     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7121     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7122     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7123     // to encoding T1 if <Rd> is omitted."
7124     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7125       Inst.setOpcode(ARM::tADDi3);
7126       return true;
7127     }
7128     break;
7129   case ARM::tSUBi8:
7130     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7131     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7132     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7133     // to encoding T1 if <Rd> is omitted."
7134     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7135       Inst.setOpcode(ARM::tSUBi3);
7136       return true;
7137     }
7138     break;
7139   case ARM::t2ADDri:
7140   case ARM::t2SUBri: {
7141     // If the destination and first source operand are the same, and
7142     // the flags are compatible with the current IT status, use encoding T2
7143     // instead of T3. For compatibility with the system 'as'. Make sure the
7144     // wide encoding wasn't explicit.
7145     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7146         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7147         (unsigned)Inst.getOperand(2).getImm() > 255 ||
7148         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7149         (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7150         (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7151          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7152       break;
7153     MCInst TmpInst;
7154     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7155                       ARM::tADDi8 : ARM::tSUBi8);
7156     TmpInst.addOperand(Inst.getOperand(0));
7157     TmpInst.addOperand(Inst.getOperand(5));
7158     TmpInst.addOperand(Inst.getOperand(0));
7159     TmpInst.addOperand(Inst.getOperand(2));
7160     TmpInst.addOperand(Inst.getOperand(3));
7161     TmpInst.addOperand(Inst.getOperand(4));
7162     Inst = TmpInst;
7163     return true;
7164   }
7165   case ARM::t2ADDrr: {
7166     // If the destination and first source operand are the same, and
7167     // there's no setting of the flags, use encoding T2 instead of T3.
7168     // Note that this is only for ADD, not SUB. This mirrors the system
7169     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7170     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7171         Inst.getOperand(5).getReg() != 0 ||
7172         (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7173          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7174       break;
7175     MCInst TmpInst;
7176     TmpInst.setOpcode(ARM::tADDhirr);
7177     TmpInst.addOperand(Inst.getOperand(0));
7178     TmpInst.addOperand(Inst.getOperand(0));
7179     TmpInst.addOperand(Inst.getOperand(2));
7180     TmpInst.addOperand(Inst.getOperand(3));
7181     TmpInst.addOperand(Inst.getOperand(4));
7182     Inst = TmpInst;
7183     return true;
7184   }
7185   case ARM::tADDrSP: {
7186     // If the non-SP source operand and the destination operand are not the
7187     // same, we need to use the 32-bit encoding if it's available.
7188     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7189       Inst.setOpcode(ARM::t2ADDrr);
7190       Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7191       return true;
7192     }
7193     break;
7194   }
7195   case ARM::tB:
7196     // A Thumb conditional branch outside of an IT block is a tBcc.
7197     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7198       Inst.setOpcode(ARM::tBcc);
7199       return true;
7200     }
7201     break;
7202   case ARM::t2B:
7203     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7204     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7205       Inst.setOpcode(ARM::t2Bcc);
7206       return true;
7207     }
7208     break;
7209   case ARM::t2Bcc:
7210     // If the conditional is AL or we're in an IT block, we really want t2B.
7211     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7212       Inst.setOpcode(ARM::t2B);
7213       return true;
7214     }
7215     break;
7216   case ARM::tBcc:
7217     // If the conditional is AL, we really want tB.
7218     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7219       Inst.setOpcode(ARM::tB);
7220       return true;
7221     }
7222     break;
7223   case ARM::tLDMIA: {
7224     // If the register list contains any high registers, or if the writeback
7225     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7226     // instead if we're in Thumb2. Otherwise, this should have generated
7227     // an error in validateInstruction().
7228     unsigned Rn = Inst.getOperand(0).getReg();
7229     bool hasWritebackToken =
7230       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7231        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7232     bool listContainsBase;
7233     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7234         (!listContainsBase && !hasWritebackToken) ||
7235         (listContainsBase && hasWritebackToken)) {
7236       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7237       assert (isThumbTwo());
7238       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7239       // If we're switching to the updating version, we need to insert
7240       // the writeback tied operand.
7241       if (hasWritebackToken)
7242         Inst.insert(Inst.begin(),
7243                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7244       return true;
7245     }
7246     break;
7247   }
7248   case ARM::tSTMIA_UPD: {
7249     // If the register list contains any high registers, we need to use
7250     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7251     // should have generated an error in validateInstruction().
7252     unsigned Rn = Inst.getOperand(0).getReg();
7253     bool listContainsBase;
7254     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7255       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7256       assert (isThumbTwo());
7257       Inst.setOpcode(ARM::t2STMIA_UPD);
7258       return true;
7259     }
7260     break;
7261   }
7262   case ARM::tPOP: {
7263     bool listContainsBase;
7264     // If the register list contains any high registers, we need to use
7265     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7266     // should have generated an error in validateInstruction().
7267     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7268       return false;
7269     assert (isThumbTwo());
7270     Inst.setOpcode(ARM::t2LDMIA_UPD);
7271     // Add the base register and writeback operands.
7272     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7273     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7274     return true;
7275   }
7276   case ARM::tPUSH: {
7277     bool listContainsBase;
7278     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7279       return false;
7280     assert (isThumbTwo());
7281     Inst.setOpcode(ARM::t2STMDB_UPD);
7282     // Add the base register and writeback operands.
7283     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7284     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7285     return true;
7286   }
7287   case ARM::t2MOVi: {
7288     // If we can use the 16-bit encoding and the user didn't explicitly
7289     // request the 32-bit variant, transform it here.
7290     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7291         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7292         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7293          Inst.getOperand(4).getReg() == ARM::CPSR) ||
7294         (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7295         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7296          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7297       // The operands aren't in the same order for tMOVi8...
7298       MCInst TmpInst;
7299       TmpInst.setOpcode(ARM::tMOVi8);
7300       TmpInst.addOperand(Inst.getOperand(0));
7301       TmpInst.addOperand(Inst.getOperand(4));
7302       TmpInst.addOperand(Inst.getOperand(1));
7303       TmpInst.addOperand(Inst.getOperand(2));
7304       TmpInst.addOperand(Inst.getOperand(3));
7305       Inst = TmpInst;
7306       return true;
7307     }
7308     break;
7309   }
7310   case ARM::t2MOVr: {
7311     // If we can use the 16-bit encoding and the user didn't explicitly
7312     // request the 32-bit variant, transform it here.
7313     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7314         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7315         Inst.getOperand(2).getImm() == ARMCC::AL &&
7316         Inst.getOperand(4).getReg() == ARM::CPSR &&
7317         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7318          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7319       // The operands aren't the same for tMOV[S]r... (no cc_out)
7320       MCInst TmpInst;
7321       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7322       TmpInst.addOperand(Inst.getOperand(0));
7323       TmpInst.addOperand(Inst.getOperand(1));
7324       TmpInst.addOperand(Inst.getOperand(2));
7325       TmpInst.addOperand(Inst.getOperand(3));
7326       Inst = TmpInst;
7327       return true;
7328     }
7329     break;
7330   }
7331   case ARM::t2SXTH:
7332   case ARM::t2SXTB:
7333   case ARM::t2UXTH:
7334   case ARM::t2UXTB: {
7335     // If we can use the 16-bit encoding and the user didn't explicitly
7336     // request the 32-bit variant, transform it here.
7337     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7338         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7339         Inst.getOperand(2).getImm() == 0 &&
7340         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7341          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7342       unsigned NewOpc;
7343       switch (Inst.getOpcode()) {
7344       default: llvm_unreachable("Illegal opcode!");
7345       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7346       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7347       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7348       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7349       }
7350       // The operands aren't the same for thumb1 (no rotate operand).
7351       MCInst TmpInst;
7352       TmpInst.setOpcode(NewOpc);
7353       TmpInst.addOperand(Inst.getOperand(0));
7354       TmpInst.addOperand(Inst.getOperand(1));
7355       TmpInst.addOperand(Inst.getOperand(3));
7356       TmpInst.addOperand(Inst.getOperand(4));
7357       Inst = TmpInst;
7358       return true;
7359     }
7360     break;
7361   }
7362   case ARM::MOVsi: {
7363     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7364     // rrx shifts and asr/lsr of #32 is encoded as 0
7365     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7366       return false;
7367     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7368       // Shifting by zero is accepted as a vanilla 'MOVr'
7369       MCInst TmpInst;
7370       TmpInst.setOpcode(ARM::MOVr);
7371       TmpInst.addOperand(Inst.getOperand(0));
7372       TmpInst.addOperand(Inst.getOperand(1));
7373       TmpInst.addOperand(Inst.getOperand(3));
7374       TmpInst.addOperand(Inst.getOperand(4));
7375       TmpInst.addOperand(Inst.getOperand(5));
7376       Inst = TmpInst;
7377       return true;
7378     }
7379     return false;
7380   }
7381   case ARM::ANDrsi:
7382   case ARM::ORRrsi:
7383   case ARM::EORrsi:
7384   case ARM::BICrsi:
7385   case ARM::SUBrsi:
7386   case ARM::ADDrsi: {
7387     unsigned newOpc;
7388     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7389     if (SOpc == ARM_AM::rrx) return false;
7390     switch (Inst.getOpcode()) {
7391     default: llvm_unreachable("unexpected opcode!");
7392     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7393     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7394     case ARM::EORrsi: newOpc = ARM::EORrr; break;
7395     case ARM::BICrsi: newOpc = ARM::BICrr; break;
7396     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7397     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7398     }
7399     // If the shift is by zero, use the non-shifted instruction definition.
7400     // The exception is for right shifts, where 0 == 32
7401     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7402         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7403       MCInst TmpInst;
7404       TmpInst.setOpcode(newOpc);
7405       TmpInst.addOperand(Inst.getOperand(0));
7406       TmpInst.addOperand(Inst.getOperand(1));
7407       TmpInst.addOperand(Inst.getOperand(2));
7408       TmpInst.addOperand(Inst.getOperand(4));
7409       TmpInst.addOperand(Inst.getOperand(5));
7410       TmpInst.addOperand(Inst.getOperand(6));
7411       Inst = TmpInst;
7412       return true;
7413     }
7414     return false;
7415   }
7416   case ARM::ITasm:
7417   case ARM::t2IT: {
7418     // The mask bits for all but the first condition are represented as
7419     // the low bit of the condition code value implies 't'. We currently
7420     // always have 1 implies 't', so XOR toggle the bits if the low bit
7421     // of the condition code is zero.
7422     MCOperand &MO = Inst.getOperand(1);
7423     unsigned Mask = MO.getImm();
7424     unsigned OrigMask = Mask;
7425     unsigned TZ = countTrailingZeros(Mask);
7426     if ((Inst.getOperand(0).getImm() & 1) == 0) {
7427       assert(Mask && TZ <= 3 && "illegal IT mask value!");
7428       Mask ^= (0xE << TZ) & 0xF;
7429     }
7430     MO.setImm(Mask);
7431 
7432     // Set up the IT block state according to the IT instruction we just
7433     // matched.
7434     assert(!inITBlock() && "nested IT blocks?!");
7435     ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7436     ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7437     ITState.CurPosition = 0;
7438     ITState.FirstCond = true;
7439     break;
7440   }
7441   case ARM::t2LSLrr:
7442   case ARM::t2LSRrr:
7443   case ARM::t2ASRrr:
7444   case ARM::t2SBCrr:
7445   case ARM::t2RORrr:
7446   case ARM::t2BICrr:
7447   {
7448     // Assemblers should use the narrow encodings of these instructions when permissible.
7449     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7450          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7451         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7452         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7453          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7454         (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7455          !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7456       unsigned NewOpc;
7457       switch (Inst.getOpcode()) {
7458         default: llvm_unreachable("unexpected opcode");
7459         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7460         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7461         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7462         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7463         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7464         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7465       }
7466       MCInst TmpInst;
7467       TmpInst.setOpcode(NewOpc);
7468       TmpInst.addOperand(Inst.getOperand(0));
7469       TmpInst.addOperand(Inst.getOperand(5));
7470       TmpInst.addOperand(Inst.getOperand(1));
7471       TmpInst.addOperand(Inst.getOperand(2));
7472       TmpInst.addOperand(Inst.getOperand(3));
7473       TmpInst.addOperand(Inst.getOperand(4));
7474       Inst = TmpInst;
7475       return true;
7476     }
7477     return false;
7478   }
7479   case ARM::t2ANDrr:
7480   case ARM::t2EORrr:
7481   case ARM::t2ADCrr:
7482   case ARM::t2ORRrr:
7483   {
7484     // Assemblers should use the narrow encodings of these instructions when permissible.
7485     // These instructions are special in that they are commutable, so shorter encodings
7486     // are available more often.
7487     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7488          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7489         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7490          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7491         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7492          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7493         (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7494          !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7495       unsigned NewOpc;
7496       switch (Inst.getOpcode()) {
7497         default: llvm_unreachable("unexpected opcode");
7498         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7499         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7500         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7501         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7502       }
7503       MCInst TmpInst;
7504       TmpInst.setOpcode(NewOpc);
7505       TmpInst.addOperand(Inst.getOperand(0));
7506       TmpInst.addOperand(Inst.getOperand(5));
7507       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7508         TmpInst.addOperand(Inst.getOperand(1));
7509         TmpInst.addOperand(Inst.getOperand(2));
7510       } else {
7511         TmpInst.addOperand(Inst.getOperand(2));
7512         TmpInst.addOperand(Inst.getOperand(1));
7513       }
7514       TmpInst.addOperand(Inst.getOperand(3));
7515       TmpInst.addOperand(Inst.getOperand(4));
7516       Inst = TmpInst;
7517       return true;
7518     }
7519     return false;
7520   }
7521   }
7522   return false;
7523 }
7524 
7525 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7526   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7527   // suffix depending on whether they're in an IT block or not.
7528   unsigned Opc = Inst.getOpcode();
7529   const MCInstrDesc &MCID = getInstDesc(Opc);
7530   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7531     assert(MCID.hasOptionalDef() &&
7532            "optionally flag setting instruction missing optional def operand");
7533     assert(MCID.NumOperands == Inst.getNumOperands() &&
7534            "operand count mismatch!");
7535     // Find the optional-def operand (cc_out).
7536     unsigned OpNo;
7537     for (OpNo = 0;
7538          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7539          ++OpNo)
7540       ;
7541     // If we're parsing Thumb1, reject it completely.
7542     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7543       return Match_MnemonicFail;
7544     // If we're parsing Thumb2, which form is legal depends on whether we're
7545     // in an IT block.
7546     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7547         !inITBlock())
7548       return Match_RequiresITBlock;
7549     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7550         inITBlock())
7551       return Match_RequiresNotITBlock;
7552   }
7553   // Some high-register supporting Thumb1 encodings only allow both registers
7554   // to be from r0-r7 when in Thumb2.
7555   else if (Opc == ARM::tADDhirr && isThumbOne() &&
7556            isARMLowRegister(Inst.getOperand(1).getReg()) &&
7557            isARMLowRegister(Inst.getOperand(2).getReg()))
7558     return Match_RequiresThumb2;
7559   // Others only require ARMv6 or later.
7560   else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7561            isARMLowRegister(Inst.getOperand(0).getReg()) &&
7562            isARMLowRegister(Inst.getOperand(1).getReg()))
7563     return Match_RequiresV6;
7564   return Match_Success;
7565 }
7566 
7567 static const char *getSubtargetFeatureName(unsigned Val);
7568 bool ARMAsmParser::
7569 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7570                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7571                         MCStreamer &Out, unsigned &ErrorInfo,
7572                         bool MatchingInlineAsm) {
7573   MCInst Inst;
7574   unsigned MatchResult;
7575 
7576   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7577                                      MatchingInlineAsm);
7578   switch (MatchResult) {
7579   default: break;
7580   case Match_Success:
7581     // Context sensitive operand constraints aren't handled by the matcher,
7582     // so check them here.
7583     if (validateInstruction(Inst, Operands)) {
7584       // Still progress the IT block, otherwise one wrong condition causes
7585       // nasty cascading errors.
7586       forwardITPosition();
7587       return true;
7588     }
7589 
7590     // Some instructions need post-processing to, for example, tweak which
7591     // encoding is selected. Loop on it while changes happen so the
7592     // individual transformations can chain off each other. E.g.,
7593     // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7594     while (processInstruction(Inst, Operands))
7595       ;
7596 
7597     // Only move forward at the very end so that everything in validate
7598     // and process gets a consistent answer about whether we're in an IT
7599     // block.
7600     forwardITPosition();
7601 
7602     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7603     // doesn't actually encode.
7604     if (Inst.getOpcode() == ARM::ITasm)
7605       return false;
7606 
7607     Inst.setLoc(IDLoc);
7608     Out.EmitInstruction(Inst);
7609     return false;
7610   case Match_MissingFeature: {
7611     assert(ErrorInfo && "Unknown missing feature!");
7612     // Special case the error message for the very common case where only
7613     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7614     std::string Msg = "instruction requires:";
7615     unsigned Mask = 1;
7616     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7617       if (ErrorInfo & Mask) {
7618         Msg += " ";
7619         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7620       }
7621       Mask <<= 1;
7622     }
7623     return Error(IDLoc, Msg);
7624   }
7625   case Match_InvalidOperand: {
7626     SMLoc ErrorLoc = IDLoc;
7627     if (ErrorInfo != ~0U) {
7628       if (ErrorInfo >= Operands.size())
7629         return Error(IDLoc, "too few operands for instruction");
7630 
7631       ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7632       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7633     }
7634 
7635     return Error(ErrorLoc, "invalid operand for instruction");
7636   }
7637   case Match_MnemonicFail:
7638     return Error(IDLoc, "invalid instruction",
7639                  ((ARMOperand*)Operands[0])->getLocRange());
7640   case Match_RequiresNotITBlock:
7641     return Error(IDLoc, "flag setting instruction only valid outside IT block");
7642   case Match_RequiresITBlock:
7643     return Error(IDLoc, "instruction only valid inside IT block");
7644   case Match_RequiresV6:
7645     return Error(IDLoc, "instruction variant requires ARMv6 or later");
7646   case Match_RequiresThumb2:
7647     return Error(IDLoc, "instruction variant requires Thumb2");
7648   case Match_ImmRange0_4: {
7649     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7650     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7651     return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7652   }
7653   case Match_ImmRange0_15: {
7654     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7655     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7656     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7657   }
7658   }
7659 
7660   llvm_unreachable("Implement any new match types added!");
7661 }
7662 
7663 /// parseDirective parses the arm specific directives
7664 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7665   StringRef IDVal = DirectiveID.getIdentifier();
7666   if (IDVal == ".word")
7667     return parseDirectiveWord(4, DirectiveID.getLoc());
7668   else if (IDVal == ".thumb")
7669     return parseDirectiveThumb(DirectiveID.getLoc());
7670   else if (IDVal == ".arm")
7671     return parseDirectiveARM(DirectiveID.getLoc());
7672   else if (IDVal == ".thumb_func")
7673     return parseDirectiveThumbFunc(DirectiveID.getLoc());
7674   else if (IDVal == ".code")
7675     return parseDirectiveCode(DirectiveID.getLoc());
7676   else if (IDVal == ".syntax")
7677     return parseDirectiveSyntax(DirectiveID.getLoc());
7678   else if (IDVal == ".unreq")
7679     return parseDirectiveUnreq(DirectiveID.getLoc());
7680   else if (IDVal == ".arch")
7681     return parseDirectiveArch(DirectiveID.getLoc());
7682   else if (IDVal == ".eabi_attribute")
7683     return parseDirectiveEabiAttr(DirectiveID.getLoc());
7684   else if (IDVal == ".fnstart")
7685     return parseDirectiveFnStart(DirectiveID.getLoc());
7686   else if (IDVal == ".fnend")
7687     return parseDirectiveFnEnd(DirectiveID.getLoc());
7688   else if (IDVal == ".cantunwind")
7689     return parseDirectiveCantUnwind(DirectiveID.getLoc());
7690   else if (IDVal == ".personality")
7691     return parseDirectivePersonality(DirectiveID.getLoc());
7692   else if (IDVal == ".handlerdata")
7693     return parseDirectiveHandlerData(DirectiveID.getLoc());
7694   else if (IDVal == ".setfp")
7695     return parseDirectiveSetFP(DirectiveID.getLoc());
7696   else if (IDVal == ".pad")
7697     return parseDirectivePad(DirectiveID.getLoc());
7698   else if (IDVal == ".save")
7699     return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7700   else if (IDVal == ".vsave")
7701     return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7702   return true;
7703 }
7704 
7705 /// parseDirectiveWord
7706 ///  ::= .word [ expression (, expression)* ]
7707 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7708   if (getLexer().isNot(AsmToken::EndOfStatement)) {
7709     for (;;) {
7710       const MCExpr *Value;
7711       if (getParser().parseExpression(Value))
7712         return true;
7713 
7714       getParser().getStreamer().EmitValue(Value, Size);
7715 
7716       if (getLexer().is(AsmToken::EndOfStatement))
7717         break;
7718 
7719       // FIXME: Improve diagnostic.
7720       if (getLexer().isNot(AsmToken::Comma))
7721         return Error(L, "unexpected token in directive");
7722       Parser.Lex();
7723     }
7724   }
7725 
7726   Parser.Lex();
7727   return false;
7728 }
7729 
7730 /// parseDirectiveThumb
7731 ///  ::= .thumb
7732 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7733   if (getLexer().isNot(AsmToken::EndOfStatement))
7734     return Error(L, "unexpected token in directive");
7735   Parser.Lex();
7736 
7737   if (!hasThumb())
7738     return Error(L, "target does not support Thumb mode");
7739 
7740   if (!isThumb())
7741     SwitchMode();
7742   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7743   return false;
7744 }
7745 
7746 /// parseDirectiveARM
7747 ///  ::= .arm
7748 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7749   if (getLexer().isNot(AsmToken::EndOfStatement))
7750     return Error(L, "unexpected token in directive");
7751   Parser.Lex();
7752 
7753   if (!hasARM())
7754     return Error(L, "target does not support ARM mode");
7755 
7756   if (isThumb())
7757     SwitchMode();
7758   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7759   return false;
7760 }
7761 
7762 /// parseDirectiveThumbFunc
7763 ///  ::= .thumbfunc symbol_name
7764 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7765   const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7766   bool isMachO = MAI->hasSubsectionsViaSymbols();
7767   StringRef Name;
7768   bool needFuncName = true;
7769 
7770   // Darwin asm has (optionally) function name after .thumb_func direction
7771   // ELF doesn't
7772   if (isMachO) {
7773     const AsmToken &Tok = Parser.getTok();
7774     if (Tok.isNot(AsmToken::EndOfStatement)) {
7775       if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7776         return Error(L, "unexpected token in .thumb_func directive");
7777       Name = Tok.getIdentifier();
7778       Parser.Lex(); // Consume the identifier token.
7779       needFuncName = false;
7780     }
7781   }
7782 
7783   if (getLexer().isNot(AsmToken::EndOfStatement))
7784     return Error(L, "unexpected token in directive");
7785 
7786   // Eat the end of statement and any blank lines that follow.
7787   while (getLexer().is(AsmToken::EndOfStatement))
7788     Parser.Lex();
7789 
7790   // FIXME: assuming function name will be the line following .thumb_func
7791   // We really should be checking the next symbol definition even if there's
7792   // stuff in between.
7793   if (needFuncName) {
7794     Name = Parser.getTok().getIdentifier();
7795   }
7796 
7797   // Mark symbol as a thumb symbol.
7798   MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7799   getParser().getStreamer().EmitThumbFunc(Func);
7800   return false;
7801 }
7802 
7803 /// parseDirectiveSyntax
7804 ///  ::= .syntax unified | divided
7805 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7806   const AsmToken &Tok = Parser.getTok();
7807   if (Tok.isNot(AsmToken::Identifier))
7808     return Error(L, "unexpected token in .syntax directive");
7809   StringRef Mode = Tok.getString();
7810   if (Mode == "unified" || Mode == "UNIFIED")
7811     Parser.Lex();
7812   else if (Mode == "divided" || Mode == "DIVIDED")
7813     return Error(L, "'.syntax divided' arm asssembly not supported");
7814   else
7815     return Error(L, "unrecognized syntax mode in .syntax directive");
7816 
7817   if (getLexer().isNot(AsmToken::EndOfStatement))
7818     return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7819   Parser.Lex();
7820 
7821   // TODO tell the MC streamer the mode
7822   // getParser().getStreamer().Emit???();
7823   return false;
7824 }
7825 
7826 /// parseDirectiveCode
7827 ///  ::= .code 16 | 32
7828 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7829   const AsmToken &Tok = Parser.getTok();
7830   if (Tok.isNot(AsmToken::Integer))
7831     return Error(L, "unexpected token in .code directive");
7832   int64_t Val = Parser.getTok().getIntVal();
7833   if (Val == 16)
7834     Parser.Lex();
7835   else if (Val == 32)
7836     Parser.Lex();
7837   else
7838     return Error(L, "invalid operand to .code directive");
7839 
7840   if (getLexer().isNot(AsmToken::EndOfStatement))
7841     return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7842   Parser.Lex();
7843 
7844   if (Val == 16) {
7845     if (!hasThumb())
7846       return Error(L, "target does not support Thumb mode");
7847 
7848     if (!isThumb())
7849       SwitchMode();
7850     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7851   } else {
7852     if (!hasARM())
7853       return Error(L, "target does not support ARM mode");
7854 
7855     if (isThumb())
7856       SwitchMode();
7857     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7858   }
7859 
7860   return false;
7861 }
7862 
7863 /// parseDirectiveReq
7864 ///  ::= name .req registername
7865 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7866   Parser.Lex(); // Eat the '.req' token.
7867   unsigned Reg;
7868   SMLoc SRegLoc, ERegLoc;
7869   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7870     Parser.eatToEndOfStatement();
7871     return Error(SRegLoc, "register name expected");
7872   }
7873 
7874   // Shouldn't be anything else.
7875   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7876     Parser.eatToEndOfStatement();
7877     return Error(Parser.getTok().getLoc(),
7878                  "unexpected input in .req directive.");
7879   }
7880 
7881   Parser.Lex(); // Consume the EndOfStatement
7882 
7883   if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7884     return Error(SRegLoc, "redefinition of '" + Name +
7885                           "' does not match original.");
7886 
7887   return false;
7888 }
7889 
7890 /// parseDirectiveUneq
7891 ///  ::= .unreq registername
7892 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7893   if (Parser.getTok().isNot(AsmToken::Identifier)) {
7894     Parser.eatToEndOfStatement();
7895     return Error(L, "unexpected input in .unreq directive.");
7896   }
7897   RegisterReqs.erase(Parser.getTok().getIdentifier());
7898   Parser.Lex(); // Eat the identifier.
7899   return false;
7900 }
7901 
7902 /// parseDirectiveArch
7903 ///  ::= .arch token
7904 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7905   return true;
7906 }
7907 
7908 /// parseDirectiveEabiAttr
7909 ///  ::= .eabi_attribute int, int
7910 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7911   return true;
7912 }
7913 
7914 /// parseDirectiveFnStart
7915 ///  ::= .fnstart
7916 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
7917   if (FnStartLoc.isValid()) {
7918     Error(L, ".fnstart starts before the end of previous one");
7919     Error(FnStartLoc, "previous .fnstart starts here");
7920     return true;
7921   }
7922 
7923   FnStartLoc = L;
7924   getParser().getStreamer().EmitFnStart();
7925   return false;
7926 }
7927 
7928 /// parseDirectiveFnEnd
7929 ///  ::= .fnend
7930 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
7931   // Check the ordering of unwind directives
7932   if (!FnStartLoc.isValid())
7933     return Error(L, ".fnstart must precede .fnend directive");
7934 
7935   // Reset the unwind directives parser state
7936   resetUnwindDirectiveParserState();
7937 
7938   getParser().getStreamer().EmitFnEnd();
7939   return false;
7940 }
7941 
7942 /// parseDirectiveCantUnwind
7943 ///  ::= .cantunwind
7944 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
7945   // Check the ordering of unwind directives
7946   CantUnwindLoc = L;
7947   if (!FnStartLoc.isValid())
7948     return Error(L, ".fnstart must precede .cantunwind directive");
7949   if (HandlerDataLoc.isValid()) {
7950     Error(L, ".cantunwind can't be used with .handlerdata directive");
7951     Error(HandlerDataLoc, ".handlerdata was specified here");
7952     return true;
7953   }
7954   if (PersonalityLoc.isValid()) {
7955     Error(L, ".cantunwind can't be used with .personality directive");
7956     Error(PersonalityLoc, ".personality was specified here");
7957     return true;
7958   }
7959 
7960   getParser().getStreamer().EmitCantUnwind();
7961   return false;
7962 }
7963 
7964 /// parseDirectivePersonality
7965 ///  ::= .personality name
7966 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
7967   // Check the ordering of unwind directives
7968   PersonalityLoc = L;
7969   if (!FnStartLoc.isValid())
7970     return Error(L, ".fnstart must precede .personality directive");
7971   if (CantUnwindLoc.isValid()) {
7972     Error(L, ".personality can't be used with .cantunwind directive");
7973     Error(CantUnwindLoc, ".cantunwind was specified here");
7974     return true;
7975   }
7976   if (HandlerDataLoc.isValid()) {
7977     Error(L, ".personality must precede .handlerdata directive");
7978     Error(HandlerDataLoc, ".handlerdata was specified here");
7979     return true;
7980   }
7981 
7982   // Parse the name of the personality routine
7983   if (Parser.getTok().isNot(AsmToken::Identifier)) {
7984     Parser.eatToEndOfStatement();
7985     return Error(L, "unexpected input in .personality directive.");
7986   }
7987   StringRef Name(Parser.getTok().getIdentifier());
7988   Parser.Lex();
7989 
7990   MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
7991   getParser().getStreamer().EmitPersonality(PR);
7992   return false;
7993 }
7994 
7995 /// parseDirectiveHandlerData
7996 ///  ::= .handlerdata
7997 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
7998   // Check the ordering of unwind directives
7999   HandlerDataLoc = L;
8000   if (!FnStartLoc.isValid())
8001     return Error(L, ".fnstart must precede .personality directive");
8002   if (CantUnwindLoc.isValid()) {
8003     Error(L, ".handlerdata can't be used with .cantunwind directive");
8004     Error(CantUnwindLoc, ".cantunwind was specified here");
8005     return true;
8006   }
8007 
8008   getParser().getStreamer().EmitHandlerData();
8009   return false;
8010 }
8011 
8012 /// parseDirectiveSetFP
8013 ///  ::= .setfp fpreg, spreg [, offset]
8014 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8015   // Check the ordering of unwind directives
8016   if (!FnStartLoc.isValid())
8017     return Error(L, ".fnstart must precede .setfp directive");
8018   if (HandlerDataLoc.isValid())
8019     return Error(L, ".setfp must precede .handlerdata directive");
8020 
8021   // Parse fpreg
8022   SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8023   int NewFPReg = tryParseRegister();
8024   if (NewFPReg == -1)
8025     return Error(NewFPRegLoc, "frame pointer register expected");
8026 
8027   // Consume comma
8028   if (!Parser.getTok().is(AsmToken::Comma))
8029     return Error(Parser.getTok().getLoc(), "comma expected");
8030   Parser.Lex(); // skip comma
8031 
8032   // Parse spreg
8033   SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8034   int NewSPReg = tryParseRegister();
8035   if (NewSPReg == -1)
8036     return Error(NewSPRegLoc, "stack pointer register expected");
8037 
8038   if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8039     return Error(NewSPRegLoc,
8040                  "register should be either $sp or the latest fp register");
8041 
8042   // Update the frame pointer register
8043   FPReg = NewFPReg;
8044 
8045   // Parse offset
8046   int64_t Offset = 0;
8047   if (Parser.getTok().is(AsmToken::Comma)) {
8048     Parser.Lex(); // skip comma
8049 
8050     if (Parser.getTok().isNot(AsmToken::Hash) &&
8051         Parser.getTok().isNot(AsmToken::Dollar)) {
8052       return Error(Parser.getTok().getLoc(), "'#' expected");
8053     }
8054     Parser.Lex(); // skip hash token.
8055 
8056     const MCExpr *OffsetExpr;
8057     SMLoc ExLoc = Parser.getTok().getLoc();
8058     SMLoc EndLoc;
8059     if (getParser().parseExpression(OffsetExpr, EndLoc))
8060       return Error(ExLoc, "malformed setfp offset");
8061     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8062     if (!CE)
8063       return Error(ExLoc, "setfp offset must be an immediate");
8064 
8065     Offset = CE->getValue();
8066   }
8067 
8068   getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8069                                       static_cast<unsigned>(NewSPReg),
8070                                       Offset);
8071   return false;
8072 }
8073 
8074 /// parseDirective
8075 ///  ::= .pad offset
8076 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8077   // Check the ordering of unwind directives
8078   if (!FnStartLoc.isValid())
8079     return Error(L, ".fnstart must precede .pad directive");
8080   if (HandlerDataLoc.isValid())
8081     return Error(L, ".pad must precede .handlerdata directive");
8082 
8083   // Parse the offset
8084   if (Parser.getTok().isNot(AsmToken::Hash) &&
8085       Parser.getTok().isNot(AsmToken::Dollar)) {
8086     return Error(Parser.getTok().getLoc(), "'#' expected");
8087   }
8088   Parser.Lex(); // skip hash token.
8089 
8090   const MCExpr *OffsetExpr;
8091   SMLoc ExLoc = Parser.getTok().getLoc();
8092   SMLoc EndLoc;
8093   if (getParser().parseExpression(OffsetExpr, EndLoc))
8094     return Error(ExLoc, "malformed pad offset");
8095   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8096   if (!CE)
8097     return Error(ExLoc, "pad offset must be an immediate");
8098 
8099   getParser().getStreamer().EmitPad(CE->getValue());
8100   return false;
8101 }
8102 
8103 /// parseDirectiveRegSave
8104 ///  ::= .save  { registers }
8105 ///  ::= .vsave { registers }
8106 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8107   // Check the ordering of unwind directives
8108   if (!FnStartLoc.isValid())
8109     return Error(L, ".fnstart must precede .save or .vsave directives");
8110   if (HandlerDataLoc.isValid())
8111     return Error(L, ".save or .vsave must precede .handlerdata directive");
8112 
8113   // RAII object to make sure parsed operands are deleted.
8114   struct CleanupObject {
8115     SmallVector<MCParsedAsmOperand *, 1> Operands;
8116     ~CleanupObject() {
8117       for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8118         delete Operands[I];
8119     }
8120   } CO;
8121 
8122   // Parse the register list
8123   if (parseRegisterList(CO.Operands))
8124     return true;
8125   ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8126   if (!IsVector && !Op->isRegList())
8127     return Error(L, ".save expects GPR registers");
8128   if (IsVector && !Op->isDPRRegList())
8129     return Error(L, ".vsave expects DPR registers");
8130 
8131   getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8132   return false;
8133 }
8134 
8135 /// Force static initialization.
8136 extern "C" void LLVMInitializeARMAsmParser() {
8137   RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8138   RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8139 }
8140 
8141 #define GET_REGISTER_MATCHER
8142 #define GET_SUBTARGET_FEATURE_NAME
8143 #define GET_MATCHER_IMPLEMENTATION
8144 #include "ARMGenAsmMatcher.inc"
8145 
8146 // Define this matcher function after the auto-generated include so we
8147 // have the match class enum definitions.
8148 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8149                                                   unsigned Kind) {
8150   ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8151   // If the kind is a token for a literal immediate, check if our asm
8152   // operand matches. This is for InstAliases which have a fixed-value
8153   // immediate in the syntax.
8154   if (Kind == MCK__35_0 && Op->isImm()) {
8155     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8156     if (!CE)
8157       return Match_InvalidOperand;
8158     if (CE->getValue() == 0)
8159       return Match_Success;
8160   }
8161   return Match_InvalidOperand;
8162 }
8163