1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMFeatures.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
24 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCExpr.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCObjectFileInfo.h"
30 #include "llvm/MC/MCParser/MCAsmLexer.h"
31 #include "llvm/MC/MCParser/MCAsmParser.h"
32 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/MC/MCSection.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSubtargetInfo.h"
39 #include "llvm/MC/MCSymbol.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SourceMgr.h"
48 #include "llvm/Support/TargetParser.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
51 
52 using namespace llvm;
53 
54 namespace {
55 
56 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
57 
58 static cl::opt<ImplicitItModeTy> ImplicitItMode(
59     "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
60     cl::desc("Allow conditional instructions outdside of an IT block"),
61     cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
62                           "Accept in both ISAs, emit implicit ITs in Thumb"),
63                clEnumValN(ImplicitItModeTy::Never, "never",
64                           "Warn in ARM, reject in Thumb"),
65                clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
66                           "Accept in ARM, reject in Thumb"),
67                clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
68                           "Warn in ARM, emit implicit ITs in Thumb")));
69 
70 class ARMOperand;
71 
72 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
73 
74 class UnwindContext {
75   MCAsmParser &Parser;
76 
77   typedef SmallVector<SMLoc, 4> Locs;
78 
79   Locs FnStartLocs;
80   Locs CantUnwindLocs;
81   Locs PersonalityLocs;
82   Locs PersonalityIndexLocs;
83   Locs HandlerDataLocs;
84   int FPReg;
85 
86 public:
87   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
88 
89   bool hasFnStart() const { return !FnStartLocs.empty(); }
90   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
91   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
92   bool hasPersonality() const {
93     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
94   }
95 
96   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
97   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
98   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
99   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
100   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
101 
102   void saveFPReg(int Reg) { FPReg = Reg; }
103   int getFPReg() const { return FPReg; }
104 
105   void emitFnStartLocNotes() const {
106     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
107          FI != FE; ++FI)
108       Parser.Note(*FI, ".fnstart was specified here");
109   }
110   void emitCantUnwindLocNotes() const {
111     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
112                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
113       Parser.Note(*UI, ".cantunwind was specified here");
114   }
115   void emitHandlerDataLocNotes() const {
116     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
117                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
118       Parser.Note(*HI, ".handlerdata was specified here");
119   }
120   void emitPersonalityLocNotes() const {
121     for (Locs::const_iterator PI = PersonalityLocs.begin(),
122                               PE = PersonalityLocs.end(),
123                               PII = PersonalityIndexLocs.begin(),
124                               PIE = PersonalityIndexLocs.end();
125          PI != PE || PII != PIE;) {
126       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
127         Parser.Note(*PI++, ".personality was specified here");
128       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
129         Parser.Note(*PII++, ".personalityindex was specified here");
130       else
131         llvm_unreachable(".personality and .personalityindex cannot be "
132                          "at the same location");
133     }
134   }
135 
136   void reset() {
137     FnStartLocs = Locs();
138     CantUnwindLocs = Locs();
139     PersonalityLocs = Locs();
140     HandlerDataLocs = Locs();
141     PersonalityIndexLocs = Locs();
142     FPReg = ARM::SP;
143   }
144 };
145 
146 class ARMAsmParser : public MCTargetAsmParser {
147   const MCInstrInfo &MII;
148   const MCRegisterInfo *MRI;
149   UnwindContext UC;
150 
151   ARMTargetStreamer &getTargetStreamer() {
152     assert(getParser().getStreamer().getTargetStreamer() &&
153            "do not have a target streamer");
154     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
155     return static_cast<ARMTargetStreamer &>(TS);
156   }
157 
158   // Map of register aliases registers via the .req directive.
159   StringMap<unsigned> RegisterReqs;
160 
161   bool NextSymbolIsThumb;
162 
163   bool useImplicitITThumb() const {
164     return ImplicitItMode == ImplicitItModeTy::Always ||
165            ImplicitItMode == ImplicitItModeTy::ThumbOnly;
166   }
167 
168   bool useImplicitITARM() const {
169     return ImplicitItMode == ImplicitItModeTy::Always ||
170            ImplicitItMode == ImplicitItModeTy::ARMOnly;
171   }
172 
173   struct {
174     ARMCC::CondCodes Cond;    // Condition for IT block.
175     unsigned Mask:4;          // Condition mask for instructions.
176                               // Starting at first 1 (from lsb).
177                               //   '1'  condition as indicated in IT.
178                               //   '0'  inverse of condition (else).
179                               // Count of instructions in IT block is
180                               // 4 - trailingzeroes(mask)
181                               // Note that this does not have the same encoding
182                               // as in the IT instruction, which also depends
183                               // on the low bit of the condition code.
184 
185     unsigned CurPosition;     // Current position in parsing of IT
186                               // block. In range [0,4], with 0 being the IT
187                               // instruction itself. Initialized according to
188                               // count of instructions in block.  ~0U if no
189                               // active IT block.
190 
191     bool IsExplicit;          // true  - The IT instruction was present in the
192                               //         input, we should not modify it.
193                               // false - The IT instruction was added
194                               //         implicitly, we can extend it if that
195                               //         would be legal.
196   } ITState;
197 
198   llvm::SmallVector<MCInst, 4> PendingConditionalInsts;
199 
200   void flushPendingInstructions(MCStreamer &Out) override {
201     if (!inImplicitITBlock()) {
202       assert(PendingConditionalInsts.size() == 0);
203       return;
204     }
205 
206     // Emit the IT instruction
207     unsigned Mask = getITMaskEncoding();
208     MCInst ITInst;
209     ITInst.setOpcode(ARM::t2IT);
210     ITInst.addOperand(MCOperand::createImm(ITState.Cond));
211     ITInst.addOperand(MCOperand::createImm(Mask));
212     Out.EmitInstruction(ITInst, getSTI());
213 
214     // Emit the conditonal instructions
215     assert(PendingConditionalInsts.size() <= 4);
216     for (const MCInst &Inst : PendingConditionalInsts) {
217       Out.EmitInstruction(Inst, getSTI());
218     }
219     PendingConditionalInsts.clear();
220 
221     // Clear the IT state
222     ITState.Mask = 0;
223     ITState.CurPosition = ~0U;
224   }
225 
226   bool inITBlock() { return ITState.CurPosition != ~0U; }
227   bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
228   bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
229   bool lastInITBlock() {
230     return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
231   }
232   void forwardITPosition() {
233     if (!inITBlock()) return;
234     // Move to the next instruction in the IT block, if there is one. If not,
235     // mark the block as done, except for implicit IT blocks, which we leave
236     // open until we find an instruction that can't be added to it.
237     unsigned TZ = countTrailingZeros(ITState.Mask);
238     if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
239       ITState.CurPosition = ~0U; // Done with the IT block after this.
240   }
241 
242   // Rewind the state of the current IT block, removing the last slot from it.
243   void rewindImplicitITPosition() {
244     assert(inImplicitITBlock());
245     assert(ITState.CurPosition > 1);
246     ITState.CurPosition--;
247     unsigned TZ = countTrailingZeros(ITState.Mask);
248     unsigned NewMask = 0;
249     NewMask |= ITState.Mask & (0xC << TZ);
250     NewMask |= 0x2 << TZ;
251     ITState.Mask = NewMask;
252   }
253 
254   // Rewind the state of the current IT block, removing the last slot from it.
255   // If we were at the first slot, this closes the IT block.
256   void discardImplicitITBlock() {
257     assert(inImplicitITBlock());
258     assert(ITState.CurPosition == 1);
259     ITState.CurPosition = ~0U;
260     return;
261   }
262 
263   // Get the encoding of the IT mask, as it will appear in an IT instruction.
264   unsigned getITMaskEncoding() {
265     assert(inITBlock());
266     unsigned Mask = ITState.Mask;
267     unsigned TZ = countTrailingZeros(Mask);
268     if ((ITState.Cond & 1) == 0) {
269       assert(Mask && TZ <= 3 && "illegal IT mask value!");
270       Mask ^= (0xE << TZ) & 0xF;
271     }
272     return Mask;
273   }
274 
275   // Get the condition code corresponding to the current IT block slot.
276   ARMCC::CondCodes currentITCond() {
277     unsigned MaskBit;
278     if (ITState.CurPosition == 1)
279       MaskBit = 1;
280     else
281       MaskBit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
282 
283     return MaskBit ? ITState.Cond : ARMCC::getOppositeCondition(ITState.Cond);
284   }
285 
286   // Invert the condition of the current IT block slot without changing any
287   // other slots in the same block.
288   void invertCurrentITCondition() {
289     if (ITState.CurPosition == 1) {
290       ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
291     } else {
292       ITState.Mask ^= 1 << (5 - ITState.CurPosition);
293     }
294   }
295 
296   // Returns true if the current IT block is full (all 4 slots used).
297   bool isITBlockFull() {
298     return inITBlock() && (ITState.Mask & 1);
299   }
300 
301   // Extend the current implicit IT block to have one more slot with the given
302   // condition code.
303   void extendImplicitITBlock(ARMCC::CondCodes Cond) {
304     assert(inImplicitITBlock());
305     assert(!isITBlockFull());
306     assert(Cond == ITState.Cond ||
307            Cond == ARMCC::getOppositeCondition(ITState.Cond));
308     unsigned TZ = countTrailingZeros(ITState.Mask);
309     unsigned NewMask = 0;
310     // Keep any existing condition bits.
311     NewMask |= ITState.Mask & (0xE << TZ);
312     // Insert the new condition bit.
313     NewMask |= (Cond == ITState.Cond) << TZ;
314     // Move the trailing 1 down one bit.
315     NewMask |= 1 << (TZ - 1);
316     ITState.Mask = NewMask;
317   }
318 
319   // Create a new implicit IT block with a dummy condition code.
320   void startImplicitITBlock() {
321     assert(!inITBlock());
322     ITState.Cond = ARMCC::AL;
323     ITState.Mask = 8;
324     ITState.CurPosition = 1;
325     ITState.IsExplicit = false;
326     return;
327   }
328 
329   // Create a new explicit IT block with the given condition and mask. The mask
330   // should be in the parsed format, with a 1 implying 't', regardless of the
331   // low bit of the condition.
332   void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
333     assert(!inITBlock());
334     ITState.Cond = Cond;
335     ITState.Mask = Mask;
336     ITState.CurPosition = 0;
337     ITState.IsExplicit = true;
338     return;
339   }
340 
341   void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
342     return getParser().Note(L, Msg, Range);
343   }
344   bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
345     return getParser().Warning(L, Msg, Range);
346   }
347   bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
348     return getParser().Error(L, Msg, Range);
349   }
350 
351   bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
352                            unsigned ListNo, bool IsARPop = false);
353   bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
354                            unsigned ListNo);
355 
356   int tryParseRegister();
357   bool tryParseRegisterWithWriteBack(OperandVector &);
358   int tryParseShiftRegister(OperandVector &);
359   bool parseRegisterList(OperandVector &);
360   bool parseMemory(OperandVector &);
361   bool parseOperand(OperandVector &, StringRef Mnemonic);
362   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
363   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
364                               unsigned &ShiftAmount);
365   bool parseLiteralValues(unsigned Size, SMLoc L);
366   bool parseDirectiveThumb(SMLoc L);
367   bool parseDirectiveARM(SMLoc L);
368   bool parseDirectiveThumbFunc(SMLoc L);
369   bool parseDirectiveCode(SMLoc L);
370   bool parseDirectiveSyntax(SMLoc L);
371   bool parseDirectiveReq(StringRef Name, SMLoc L);
372   bool parseDirectiveUnreq(SMLoc L);
373   bool parseDirectiveArch(SMLoc L);
374   bool parseDirectiveEabiAttr(SMLoc L);
375   bool parseDirectiveCPU(SMLoc L);
376   bool parseDirectiveFPU(SMLoc L);
377   bool parseDirectiveFnStart(SMLoc L);
378   bool parseDirectiveFnEnd(SMLoc L);
379   bool parseDirectiveCantUnwind(SMLoc L);
380   bool parseDirectivePersonality(SMLoc L);
381   bool parseDirectiveHandlerData(SMLoc L);
382   bool parseDirectiveSetFP(SMLoc L);
383   bool parseDirectivePad(SMLoc L);
384   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
385   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
386   bool parseDirectiveLtorg(SMLoc L);
387   bool parseDirectiveEven(SMLoc L);
388   bool parseDirectivePersonalityIndex(SMLoc L);
389   bool parseDirectiveUnwindRaw(SMLoc L);
390   bool parseDirectiveTLSDescSeq(SMLoc L);
391   bool parseDirectiveMovSP(SMLoc L);
392   bool parseDirectiveObjectArch(SMLoc L);
393   bool parseDirectiveArchExtension(SMLoc L);
394   bool parseDirectiveAlign(SMLoc L);
395   bool parseDirectiveThumbSet(SMLoc L);
396 
397   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
398                           bool &CarrySetting, unsigned &ProcessorIMod,
399                           StringRef &ITMask);
400   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
401                              bool &CanAcceptCarrySet,
402                              bool &CanAcceptPredicationCode);
403 
404   void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
405                                      OperandVector &Operands);
406   bool isThumb() const {
407     // FIXME: Can tablegen auto-generate this?
408     return getSTI().getFeatureBits()[ARM::ModeThumb];
409   }
410   bool isThumbOne() const {
411     return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
412   }
413   bool isThumbTwo() const {
414     return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
415   }
416   bool hasThumb() const {
417     return getSTI().getFeatureBits()[ARM::HasV4TOps];
418   }
419   bool hasThumb2() const {
420     return getSTI().getFeatureBits()[ARM::FeatureThumb2];
421   }
422   bool hasV6Ops() const {
423     return getSTI().getFeatureBits()[ARM::HasV6Ops];
424   }
425   bool hasV6T2Ops() const {
426     return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
427   }
428   bool hasV6MOps() const {
429     return getSTI().getFeatureBits()[ARM::HasV6MOps];
430   }
431   bool hasV7Ops() const {
432     return getSTI().getFeatureBits()[ARM::HasV7Ops];
433   }
434   bool hasV8Ops() const {
435     return getSTI().getFeatureBits()[ARM::HasV8Ops];
436   }
437   bool hasV8MBaseline() const {
438     return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
439   }
440   bool hasV8MMainline() const {
441     return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
442   }
443   bool has8MSecExt() const {
444     return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
445   }
446   bool hasARM() const {
447     return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
448   }
449   bool hasDSP() const {
450     return getSTI().getFeatureBits()[ARM::FeatureDSP];
451   }
452   bool hasD16() const {
453     return getSTI().getFeatureBits()[ARM::FeatureD16];
454   }
455   bool hasV8_1aOps() const {
456     return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
457   }
458   bool hasRAS() const {
459     return getSTI().getFeatureBits()[ARM::FeatureRAS];
460   }
461 
462   void SwitchMode() {
463     MCSubtargetInfo &STI = copySTI();
464     uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
465     setAvailableFeatures(FB);
466   }
467   void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
468   bool isMClass() const {
469     return getSTI().getFeatureBits()[ARM::FeatureMClass];
470   }
471 
472   /// @name Auto-generated Match Functions
473   /// {
474 
475 #define GET_ASSEMBLER_HEADER
476 #include "ARMGenAsmMatcher.inc"
477 
478   /// }
479 
480   OperandMatchResultTy parseITCondCode(OperandVector &);
481   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
482   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
483   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
484   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
485   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
486   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
487   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
488   OperandMatchResultTy parseBankedRegOperand(OperandVector &);
489   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
490                                    int High);
491   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
492     return parsePKHImm(O, "lsl", 0, 31);
493   }
494   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
495     return parsePKHImm(O, "asr", 1, 32);
496   }
497   OperandMatchResultTy parseSetEndImm(OperandVector &);
498   OperandMatchResultTy parseShifterImm(OperandVector &);
499   OperandMatchResultTy parseRotImm(OperandVector &);
500   OperandMatchResultTy parseModImm(OperandVector &);
501   OperandMatchResultTy parseBitfield(OperandVector &);
502   OperandMatchResultTy parsePostIdxReg(OperandVector &);
503   OperandMatchResultTy parseAM3Offset(OperandVector &);
504   OperandMatchResultTy parseFPImm(OperandVector &);
505   OperandMatchResultTy parseVectorList(OperandVector &);
506   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
507                                        SMLoc &EndLoc);
508 
509   // Asm Match Converter Methods
510   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
511   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
512 
513   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
514   bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
515   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
516   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
517   bool isITBlockTerminator(MCInst &Inst) const;
518 
519 public:
520   enum ARMMatchResultTy {
521     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
522     Match_RequiresNotITBlock,
523     Match_RequiresV6,
524     Match_RequiresThumb2,
525     Match_RequiresV8,
526     Match_RequiresFlagSetting,
527 #define GET_OPERAND_DIAGNOSTIC_TYPES
528 #include "ARMGenAsmMatcher.inc"
529 
530   };
531 
532   ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
533                const MCInstrInfo &MII, const MCTargetOptions &Options)
534     : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
535     MCAsmParserExtension::Initialize(Parser);
536 
537     // Cache the MCRegisterInfo.
538     MRI = getContext().getRegisterInfo();
539 
540     // Initialize the set of available features.
541     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
542 
543     // Not in an ITBlock to start with.
544     ITState.CurPosition = ~0U;
545 
546     NextSymbolIsThumb = false;
547   }
548 
549   // Implementation of the MCTargetAsmParser interface:
550   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
551   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
552                         SMLoc NameLoc, OperandVector &Operands) override;
553   bool ParseDirective(AsmToken DirectiveID) override;
554 
555   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
556                                       unsigned Kind) override;
557   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
558 
559   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
560                                OperandVector &Operands, MCStreamer &Out,
561                                uint64_t &ErrorInfo,
562                                bool MatchingInlineAsm) override;
563   unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
564                             uint64_t &ErrorInfo, bool MatchingInlineAsm,
565                             bool &EmitInITBlock, MCStreamer &Out);
566   void onLabelParsed(MCSymbol *Symbol) override;
567 };
568 } // end anonymous namespace
569 
570 namespace {
571 
572 /// ARMOperand - Instances of this class represent a parsed ARM machine
573 /// operand.
574 class ARMOperand : public MCParsedAsmOperand {
575   enum KindTy {
576     k_CondCode,
577     k_CCOut,
578     k_ITCondMask,
579     k_CoprocNum,
580     k_CoprocReg,
581     k_CoprocOption,
582     k_Immediate,
583     k_MemBarrierOpt,
584     k_InstSyncBarrierOpt,
585     k_Memory,
586     k_PostIndexRegister,
587     k_MSRMask,
588     k_BankedReg,
589     k_ProcIFlags,
590     k_VectorIndex,
591     k_Register,
592     k_RegisterList,
593     k_DPRRegisterList,
594     k_SPRRegisterList,
595     k_VectorList,
596     k_VectorListAllLanes,
597     k_VectorListIndexed,
598     k_ShiftedRegister,
599     k_ShiftedImmediate,
600     k_ShifterImmediate,
601     k_RotateImmediate,
602     k_ModifiedImmediate,
603     k_ConstantPoolImmediate,
604     k_BitfieldDescriptor,
605     k_Token,
606   } Kind;
607 
608   SMLoc StartLoc, EndLoc, AlignmentLoc;
609   SmallVector<unsigned, 8> Registers;
610 
611   struct CCOp {
612     ARMCC::CondCodes Val;
613   };
614 
615   struct CopOp {
616     unsigned Val;
617   };
618 
619   struct CoprocOptionOp {
620     unsigned Val;
621   };
622 
623   struct ITMaskOp {
624     unsigned Mask:4;
625   };
626 
627   struct MBOptOp {
628     ARM_MB::MemBOpt Val;
629   };
630 
631   struct ISBOptOp {
632     ARM_ISB::InstSyncBOpt Val;
633   };
634 
635   struct IFlagsOp {
636     ARM_PROC::IFlags Val;
637   };
638 
639   struct MMaskOp {
640     unsigned Val;
641   };
642 
643   struct BankedRegOp {
644     unsigned Val;
645   };
646 
647   struct TokOp {
648     const char *Data;
649     unsigned Length;
650   };
651 
652   struct RegOp {
653     unsigned RegNum;
654   };
655 
656   // A vector register list is a sequential list of 1 to 4 registers.
657   struct VectorListOp {
658     unsigned RegNum;
659     unsigned Count;
660     unsigned LaneIndex;
661     bool isDoubleSpaced;
662   };
663 
664   struct VectorIndexOp {
665     unsigned Val;
666   };
667 
668   struct ImmOp {
669     const MCExpr *Val;
670   };
671 
672   /// Combined record for all forms of ARM address expressions.
673   struct MemoryOp {
674     unsigned BaseRegNum;
675     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
676     // was specified.
677     const MCConstantExpr *OffsetImm;  // Offset immediate value
678     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
679     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
680     unsigned ShiftImm;        // shift for OffsetReg.
681     unsigned Alignment;       // 0 = no alignment specified
682     // n = alignment in bytes (2, 4, 8, 16, or 32)
683     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
684   };
685 
686   struct PostIdxRegOp {
687     unsigned RegNum;
688     bool isAdd;
689     ARM_AM::ShiftOpc ShiftTy;
690     unsigned ShiftImm;
691   };
692 
693   struct ShifterImmOp {
694     bool isASR;
695     unsigned Imm;
696   };
697 
698   struct RegShiftedRegOp {
699     ARM_AM::ShiftOpc ShiftTy;
700     unsigned SrcReg;
701     unsigned ShiftReg;
702     unsigned ShiftImm;
703   };
704 
705   struct RegShiftedImmOp {
706     ARM_AM::ShiftOpc ShiftTy;
707     unsigned SrcReg;
708     unsigned ShiftImm;
709   };
710 
711   struct RotImmOp {
712     unsigned Imm;
713   };
714 
715   struct ModImmOp {
716     unsigned Bits;
717     unsigned Rot;
718   };
719 
720   struct BitfieldOp {
721     unsigned LSB;
722     unsigned Width;
723   };
724 
725   union {
726     struct CCOp CC;
727     struct CopOp Cop;
728     struct CoprocOptionOp CoprocOption;
729     struct MBOptOp MBOpt;
730     struct ISBOptOp ISBOpt;
731     struct ITMaskOp ITMask;
732     struct IFlagsOp IFlags;
733     struct MMaskOp MMask;
734     struct BankedRegOp BankedReg;
735     struct TokOp Tok;
736     struct RegOp Reg;
737     struct VectorListOp VectorList;
738     struct VectorIndexOp VectorIndex;
739     struct ImmOp Imm;
740     struct MemoryOp Memory;
741     struct PostIdxRegOp PostIdxReg;
742     struct ShifterImmOp ShifterImm;
743     struct RegShiftedRegOp RegShiftedReg;
744     struct RegShiftedImmOp RegShiftedImm;
745     struct RotImmOp RotImm;
746     struct ModImmOp ModImm;
747     struct BitfieldOp Bitfield;
748   };
749 
750 public:
751   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
752 
753   /// getStartLoc - Get the location of the first token of this operand.
754   SMLoc getStartLoc() const override { return StartLoc; }
755   /// getEndLoc - Get the location of the last token of this operand.
756   SMLoc getEndLoc() const override { return EndLoc; }
757   /// getLocRange - Get the range between the first and last token of this
758   /// operand.
759   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
760 
761   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
762   SMLoc getAlignmentLoc() const {
763     assert(Kind == k_Memory && "Invalid access!");
764     return AlignmentLoc;
765   }
766 
767   ARMCC::CondCodes getCondCode() const {
768     assert(Kind == k_CondCode && "Invalid access!");
769     return CC.Val;
770   }
771 
772   unsigned getCoproc() const {
773     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
774     return Cop.Val;
775   }
776 
777   StringRef getToken() const {
778     assert(Kind == k_Token && "Invalid access!");
779     return StringRef(Tok.Data, Tok.Length);
780   }
781 
782   unsigned getReg() const override {
783     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
784     return Reg.RegNum;
785   }
786 
787   const SmallVectorImpl<unsigned> &getRegList() const {
788     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
789             Kind == k_SPRRegisterList) && "Invalid access!");
790     return Registers;
791   }
792 
793   const MCExpr *getImm() const {
794     assert(isImm() && "Invalid access!");
795     return Imm.Val;
796   }
797 
798   const MCExpr *getConstantPoolImm() const {
799     assert(isConstantPoolImm() && "Invalid access!");
800     return Imm.Val;
801   }
802 
803   unsigned getVectorIndex() const {
804     assert(Kind == k_VectorIndex && "Invalid access!");
805     return VectorIndex.Val;
806   }
807 
808   ARM_MB::MemBOpt getMemBarrierOpt() const {
809     assert(Kind == k_MemBarrierOpt && "Invalid access!");
810     return MBOpt.Val;
811   }
812 
813   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
814     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
815     return ISBOpt.Val;
816   }
817 
818   ARM_PROC::IFlags getProcIFlags() const {
819     assert(Kind == k_ProcIFlags && "Invalid access!");
820     return IFlags.Val;
821   }
822 
823   unsigned getMSRMask() const {
824     assert(Kind == k_MSRMask && "Invalid access!");
825     return MMask.Val;
826   }
827 
828   unsigned getBankedReg() const {
829     assert(Kind == k_BankedReg && "Invalid access!");
830     return BankedReg.Val;
831   }
832 
833   bool isCoprocNum() const { return Kind == k_CoprocNum; }
834   bool isCoprocReg() const { return Kind == k_CoprocReg; }
835   bool isCoprocOption() const { return Kind == k_CoprocOption; }
836   bool isCondCode() const { return Kind == k_CondCode; }
837   bool isCCOut() const { return Kind == k_CCOut; }
838   bool isITMask() const { return Kind == k_ITCondMask; }
839   bool isITCondCode() const { return Kind == k_CondCode; }
840   bool isImm() const override {
841     return Kind == k_Immediate;
842   }
843 
844   bool isARMBranchTarget() const {
845     if (!isImm()) return false;
846 
847     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
848       return CE->getValue() % 4 == 0;
849     return true;
850   }
851 
852 
853   bool isThumbBranchTarget() const {
854     if (!isImm()) return false;
855 
856     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
857       return CE->getValue() % 2 == 0;
858     return true;
859   }
860 
861   // checks whether this operand is an unsigned offset which fits is a field
862   // of specified width and scaled by a specific number of bits
863   template<unsigned width, unsigned scale>
864   bool isUnsignedOffset() const {
865     if (!isImm()) return false;
866     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
867     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
868       int64_t Val = CE->getValue();
869       int64_t Align = 1LL << scale;
870       int64_t Max = Align * ((1LL << width) - 1);
871       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
872     }
873     return false;
874   }
875   // checks whether this operand is an signed offset which fits is a field
876   // of specified width and scaled by a specific number of bits
877   template<unsigned width, unsigned scale>
878   bool isSignedOffset() const {
879     if (!isImm()) return false;
880     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
881     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
882       int64_t Val = CE->getValue();
883       int64_t Align = 1LL << scale;
884       int64_t Max = Align * ((1LL << (width-1)) - 1);
885       int64_t Min = -Align * (1LL << (width-1));
886       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
887     }
888     return false;
889   }
890 
891   // checks whether this operand is a memory operand computed as an offset
892   // applied to PC. the offset may have 8 bits of magnitude and is represented
893   // with two bits of shift. textually it may be either [pc, #imm], #imm or
894   // relocable expression...
895   bool isThumbMemPC() const {
896     int64_t Val = 0;
897     if (isImm()) {
898       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
899       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
900       if (!CE) return false;
901       Val = CE->getValue();
902     }
903     else if (isMem()) {
904       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
905       if(Memory.BaseRegNum != ARM::PC) return false;
906       Val = Memory.OffsetImm->getValue();
907     }
908     else return false;
909     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
910   }
911   bool isFPImm() const {
912     if (!isImm()) return false;
913     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
914     if (!CE) return false;
915     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
916     return Val != -1;
917   }
918   bool isFBits16() const {
919     if (!isImm()) return false;
920     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
921     if (!CE) return false;
922     int64_t Value = CE->getValue();
923     return Value >= 0 && Value <= 16;
924   }
925   bool isFBits32() const {
926     if (!isImm()) return false;
927     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
928     if (!CE) return false;
929     int64_t Value = CE->getValue();
930     return Value >= 1 && Value <= 32;
931   }
932   bool isImm8s4() const {
933     if (!isImm()) return false;
934     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
935     if (!CE) return false;
936     int64_t Value = CE->getValue();
937     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
938   }
939   bool isImm0_1020s4() const {
940     if (!isImm()) return false;
941     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
942     if (!CE) return false;
943     int64_t Value = CE->getValue();
944     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
945   }
946   bool isImm0_508s4() const {
947     if (!isImm()) return false;
948     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
949     if (!CE) return false;
950     int64_t Value = CE->getValue();
951     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
952   }
953   bool isImm0_508s4Neg() const {
954     if (!isImm()) return false;
955     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
956     if (!CE) return false;
957     int64_t Value = -CE->getValue();
958     // explicitly exclude zero. we want that to use the normal 0_508 version.
959     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
960   }
961   bool isImm0_239() const {
962     if (!isImm()) return false;
963     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964     if (!CE) return false;
965     int64_t Value = CE->getValue();
966     return Value >= 0 && Value < 240;
967   }
968   bool isImm0_255() const {
969     if (!isImm()) return false;
970     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
971     if (!CE) return false;
972     int64_t Value = CE->getValue();
973     return Value >= 0 && Value < 256;
974   }
975   bool isImm0_4095() const {
976     if (!isImm()) return false;
977     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
978     if (!CE) return false;
979     int64_t Value = CE->getValue();
980     return Value >= 0 && Value < 4096;
981   }
982   bool isImm0_4095Neg() const {
983     if (!isImm()) return false;
984     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
985     if (!CE) return false;
986     int64_t Value = -CE->getValue();
987     return Value > 0 && Value < 4096;
988   }
989   bool isImm0_1() const {
990     if (!isImm()) return false;
991     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
992     if (!CE) return false;
993     int64_t Value = CE->getValue();
994     return Value >= 0 && Value < 2;
995   }
996   bool isImm0_3() const {
997     if (!isImm()) return false;
998     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999     if (!CE) return false;
1000     int64_t Value = CE->getValue();
1001     return Value >= 0 && Value < 4;
1002   }
1003   bool isImm0_7() const {
1004     if (!isImm()) return false;
1005     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1006     if (!CE) return false;
1007     int64_t Value = CE->getValue();
1008     return Value >= 0 && Value < 8;
1009   }
1010   bool isImm0_15() const {
1011     if (!isImm()) return false;
1012     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1013     if (!CE) return false;
1014     int64_t Value = CE->getValue();
1015     return Value >= 0 && Value < 16;
1016   }
1017   bool isImm0_31() const {
1018     if (!isImm()) return false;
1019     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1020     if (!CE) return false;
1021     int64_t Value = CE->getValue();
1022     return Value >= 0 && Value < 32;
1023   }
1024   bool isImm0_63() const {
1025     if (!isImm()) return false;
1026     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1027     if (!CE) return false;
1028     int64_t Value = CE->getValue();
1029     return Value >= 0 && Value < 64;
1030   }
1031   bool isImm8() const {
1032     if (!isImm()) return false;
1033     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034     if (!CE) return false;
1035     int64_t Value = CE->getValue();
1036     return Value == 8;
1037   }
1038   bool isImm16() const {
1039     if (!isImm()) return false;
1040     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041     if (!CE) return false;
1042     int64_t Value = CE->getValue();
1043     return Value == 16;
1044   }
1045   bool isImm32() const {
1046     if (!isImm()) return false;
1047     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048     if (!CE) return false;
1049     int64_t Value = CE->getValue();
1050     return Value == 32;
1051   }
1052   bool isShrImm8() const {
1053     if (!isImm()) return false;
1054     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1055     if (!CE) return false;
1056     int64_t Value = CE->getValue();
1057     return Value > 0 && Value <= 8;
1058   }
1059   bool isShrImm16() const {
1060     if (!isImm()) return false;
1061     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1062     if (!CE) return false;
1063     int64_t Value = CE->getValue();
1064     return Value > 0 && Value <= 16;
1065   }
1066   bool isShrImm32() const {
1067     if (!isImm()) return false;
1068     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1069     if (!CE) return false;
1070     int64_t Value = CE->getValue();
1071     return Value > 0 && Value <= 32;
1072   }
1073   bool isShrImm64() const {
1074     if (!isImm()) return false;
1075     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1076     if (!CE) return false;
1077     int64_t Value = CE->getValue();
1078     return Value > 0 && Value <= 64;
1079   }
1080   bool isImm1_7() const {
1081     if (!isImm()) return false;
1082     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1083     if (!CE) return false;
1084     int64_t Value = CE->getValue();
1085     return Value > 0 && Value < 8;
1086   }
1087   bool isImm1_15() const {
1088     if (!isImm()) return false;
1089     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1090     if (!CE) return false;
1091     int64_t Value = CE->getValue();
1092     return Value > 0 && Value < 16;
1093   }
1094   bool isImm1_31() const {
1095     if (!isImm()) return false;
1096     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1097     if (!CE) return false;
1098     int64_t Value = CE->getValue();
1099     return Value > 0 && Value < 32;
1100   }
1101   bool isImm1_16() const {
1102     if (!isImm()) return false;
1103     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1104     if (!CE) return false;
1105     int64_t Value = CE->getValue();
1106     return Value > 0 && Value < 17;
1107   }
1108   bool isImm1_32() const {
1109     if (!isImm()) return false;
1110     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1111     if (!CE) return false;
1112     int64_t Value = CE->getValue();
1113     return Value > 0 && Value < 33;
1114   }
1115   bool isImm0_32() const {
1116     if (!isImm()) return false;
1117     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1118     if (!CE) return false;
1119     int64_t Value = CE->getValue();
1120     return Value >= 0 && Value < 33;
1121   }
1122   bool isImm0_65535() const {
1123     if (!isImm()) return false;
1124     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1125     if (!CE) return false;
1126     int64_t Value = CE->getValue();
1127     return Value >= 0 && Value < 65536;
1128   }
1129   bool isImm256_65535Expr() const {
1130     if (!isImm()) return false;
1131     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1132     // If it's not a constant expression, it'll generate a fixup and be
1133     // handled later.
1134     if (!CE) return true;
1135     int64_t Value = CE->getValue();
1136     return Value >= 256 && Value < 65536;
1137   }
1138   bool isImm0_65535Expr() const {
1139     if (!isImm()) return false;
1140     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1141     // If it's not a constant expression, it'll generate a fixup and be
1142     // handled later.
1143     if (!CE) return true;
1144     int64_t Value = CE->getValue();
1145     return Value >= 0 && Value < 65536;
1146   }
1147   bool isImm24bit() const {
1148     if (!isImm()) return false;
1149     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1150     if (!CE) return false;
1151     int64_t Value = CE->getValue();
1152     return Value >= 0 && Value <= 0xffffff;
1153   }
1154   bool isImmThumbSR() const {
1155     if (!isImm()) return false;
1156     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1157     if (!CE) return false;
1158     int64_t Value = CE->getValue();
1159     return Value > 0 && Value < 33;
1160   }
1161   bool isPKHLSLImm() const {
1162     if (!isImm()) return false;
1163     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1164     if (!CE) return false;
1165     int64_t Value = CE->getValue();
1166     return Value >= 0 && Value < 32;
1167   }
1168   bool isPKHASRImm() const {
1169     if (!isImm()) return false;
1170     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1171     if (!CE) return false;
1172     int64_t Value = CE->getValue();
1173     return Value > 0 && Value <= 32;
1174   }
1175   bool isAdrLabel() const {
1176     // If we have an immediate that's not a constant, treat it as a label
1177     // reference needing a fixup.
1178     if (isImm() && !isa<MCConstantExpr>(getImm()))
1179       return true;
1180 
1181     // If it is a constant, it must fit into a modified immediate encoding.
1182     if (!isImm()) return false;
1183     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1184     if (!CE) return false;
1185     int64_t Value = CE->getValue();
1186     return (ARM_AM::getSOImmVal(Value) != -1 ||
1187             ARM_AM::getSOImmVal(-Value) != -1);
1188   }
1189   bool isT2SOImm() const {
1190     if (!isImm()) return false;
1191     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1192     if (!CE) return false;
1193     int64_t Value = CE->getValue();
1194     return ARM_AM::getT2SOImmVal(Value) != -1;
1195   }
1196   bool isT2SOImmNot() const {
1197     if (!isImm()) return false;
1198     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1199     if (!CE) return false;
1200     int64_t Value = CE->getValue();
1201     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1202       ARM_AM::getT2SOImmVal(~Value) != -1;
1203   }
1204   bool isT2SOImmNeg() const {
1205     if (!isImm()) return false;
1206     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1207     if (!CE) return false;
1208     int64_t Value = CE->getValue();
1209     // Only use this when not representable as a plain so_imm.
1210     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1211       ARM_AM::getT2SOImmVal(-Value) != -1;
1212   }
1213   bool isSetEndImm() const {
1214     if (!isImm()) return false;
1215     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1216     if (!CE) return false;
1217     int64_t Value = CE->getValue();
1218     return Value == 1 || Value == 0;
1219   }
1220   bool isReg() const override { return Kind == k_Register; }
1221   bool isRegList() const { return Kind == k_RegisterList; }
1222   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1223   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1224   bool isToken() const override { return Kind == k_Token; }
1225   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1226   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1227   bool isMem() const override { return Kind == k_Memory; }
1228   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1229   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1230   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1231   bool isRotImm() const { return Kind == k_RotateImmediate; }
1232   bool isModImm() const { return Kind == k_ModifiedImmediate; }
1233   bool isModImmNot() const {
1234     if (!isImm()) return false;
1235     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1236     if (!CE) return false;
1237     int64_t Value = CE->getValue();
1238     return ARM_AM::getSOImmVal(~Value) != -1;
1239   }
1240   bool isModImmNeg() const {
1241     if (!isImm()) return false;
1242     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1243     if (!CE) return false;
1244     int64_t Value = CE->getValue();
1245     return ARM_AM::getSOImmVal(Value) == -1 &&
1246       ARM_AM::getSOImmVal(-Value) != -1;
1247   }
1248   bool isThumbModImmNeg1_7() const {
1249     if (!isImm()) return false;
1250     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1251     if (!CE) return false;
1252     int32_t Value = -(int32_t)CE->getValue();
1253     return 0 < Value && Value < 8;
1254   }
1255   bool isThumbModImmNeg8_255() const {
1256     if (!isImm()) return false;
1257     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1258     if (!CE) return false;
1259     int32_t Value = -(int32_t)CE->getValue();
1260     return 7 < Value && Value < 256;
1261   }
1262   bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1263   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1264   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1265   bool isPostIdxReg() const {
1266     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1267   }
1268   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1269     if (!isMem())
1270       return false;
1271     // No offset of any kind.
1272     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1273      (alignOK || Memory.Alignment == Alignment);
1274   }
1275   bool isMemPCRelImm12() const {
1276     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1277       return false;
1278     // Base register must be PC.
1279     if (Memory.BaseRegNum != ARM::PC)
1280       return false;
1281     // Immediate offset in range [-4095, 4095].
1282     if (!Memory.OffsetImm) return true;
1283     int64_t Val = Memory.OffsetImm->getValue();
1284     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1285   }
1286   bool isAlignedMemory() const {
1287     return isMemNoOffset(true);
1288   }
1289   bool isAlignedMemoryNone() const {
1290     return isMemNoOffset(false, 0);
1291   }
1292   bool isDupAlignedMemoryNone() const {
1293     return isMemNoOffset(false, 0);
1294   }
1295   bool isAlignedMemory16() const {
1296     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1297       return true;
1298     return isMemNoOffset(false, 0);
1299   }
1300   bool isDupAlignedMemory16() const {
1301     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1302       return true;
1303     return isMemNoOffset(false, 0);
1304   }
1305   bool isAlignedMemory32() const {
1306     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1307       return true;
1308     return isMemNoOffset(false, 0);
1309   }
1310   bool isDupAlignedMemory32() const {
1311     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1312       return true;
1313     return isMemNoOffset(false, 0);
1314   }
1315   bool isAlignedMemory64() const {
1316     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1317       return true;
1318     return isMemNoOffset(false, 0);
1319   }
1320   bool isDupAlignedMemory64() const {
1321     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1322       return true;
1323     return isMemNoOffset(false, 0);
1324   }
1325   bool isAlignedMemory64or128() const {
1326     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1327       return true;
1328     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1329       return true;
1330     return isMemNoOffset(false, 0);
1331   }
1332   bool isDupAlignedMemory64or128() const {
1333     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1334       return true;
1335     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1336       return true;
1337     return isMemNoOffset(false, 0);
1338   }
1339   bool isAlignedMemory64or128or256() const {
1340     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1341       return true;
1342     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1343       return true;
1344     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1345       return true;
1346     return isMemNoOffset(false, 0);
1347   }
1348   bool isAddrMode2() const {
1349     if (!isMem() || Memory.Alignment != 0) return false;
1350     // Check for register offset.
1351     if (Memory.OffsetRegNum) return true;
1352     // Immediate offset in range [-4095, 4095].
1353     if (!Memory.OffsetImm) return true;
1354     int64_t Val = Memory.OffsetImm->getValue();
1355     return Val > -4096 && Val < 4096;
1356   }
1357   bool isAM2OffsetImm() const {
1358     if (!isImm()) return false;
1359     // Immediate offset in range [-4095, 4095].
1360     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1361     if (!CE) return false;
1362     int64_t Val = CE->getValue();
1363     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1364   }
1365   bool isAddrMode3() const {
1366     // If we have an immediate that's not a constant, treat it as a label
1367     // reference needing a fixup. If it is a constant, it's something else
1368     // and we reject it.
1369     if (isImm() && !isa<MCConstantExpr>(getImm()))
1370       return true;
1371     if (!isMem() || Memory.Alignment != 0) return false;
1372     // No shifts are legal for AM3.
1373     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1374     // Check for register offset.
1375     if (Memory.OffsetRegNum) return true;
1376     // Immediate offset in range [-255, 255].
1377     if (!Memory.OffsetImm) return true;
1378     int64_t Val = Memory.OffsetImm->getValue();
1379     // The #-0 offset is encoded as INT32_MIN, and we have to check
1380     // for this too.
1381     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1382   }
1383   bool isAM3Offset() const {
1384     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1385       return false;
1386     if (Kind == k_PostIndexRegister)
1387       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1388     // Immediate offset in range [-255, 255].
1389     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1390     if (!CE) return false;
1391     int64_t Val = CE->getValue();
1392     // Special case, #-0 is INT32_MIN.
1393     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1394   }
1395   bool isAddrMode5() const {
1396     // If we have an immediate that's not a constant, treat it as a label
1397     // reference needing a fixup. If it is a constant, it's something else
1398     // and we reject it.
1399     if (isImm() && !isa<MCConstantExpr>(getImm()))
1400       return true;
1401     if (!isMem() || Memory.Alignment != 0) return false;
1402     // Check for register offset.
1403     if (Memory.OffsetRegNum) return false;
1404     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1405     if (!Memory.OffsetImm) return true;
1406     int64_t Val = Memory.OffsetImm->getValue();
1407     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1408       Val == INT32_MIN;
1409   }
1410   bool isAddrMode5FP16() const {
1411     // If we have an immediate that's not a constant, treat it as a label
1412     // reference needing a fixup. If it is a constant, it's something else
1413     // and we reject it.
1414     if (isImm() && !isa<MCConstantExpr>(getImm()))
1415       return true;
1416     if (!isMem() || Memory.Alignment != 0) return false;
1417     // Check for register offset.
1418     if (Memory.OffsetRegNum) return false;
1419     // Immediate offset in range [-510, 510] and a multiple of 2.
1420     if (!Memory.OffsetImm) return true;
1421     int64_t Val = Memory.OffsetImm->getValue();
1422     return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == INT32_MIN;
1423   }
1424   bool isMemTBB() const {
1425     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1426         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1427       return false;
1428     return true;
1429   }
1430   bool isMemTBH() const {
1431     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1432         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1433         Memory.Alignment != 0 )
1434       return false;
1435     return true;
1436   }
1437   bool isMemRegOffset() const {
1438     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1439       return false;
1440     return true;
1441   }
1442   bool isT2MemRegOffset() const {
1443     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1444         Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1445       return false;
1446     // Only lsl #{0, 1, 2, 3} allowed.
1447     if (Memory.ShiftType == ARM_AM::no_shift)
1448       return true;
1449     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1450       return false;
1451     return true;
1452   }
1453   bool isMemThumbRR() const {
1454     // Thumb reg+reg addressing is simple. Just two registers, a base and
1455     // an offset. No shifts, negations or any other complicating factors.
1456     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1457         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1458       return false;
1459     return isARMLowRegister(Memory.BaseRegNum) &&
1460       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1461   }
1462   bool isMemThumbRIs4() const {
1463     if (!isMem() || Memory.OffsetRegNum != 0 ||
1464         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1465       return false;
1466     // Immediate offset, multiple of 4 in range [0, 124].
1467     if (!Memory.OffsetImm) return true;
1468     int64_t Val = Memory.OffsetImm->getValue();
1469     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1470   }
1471   bool isMemThumbRIs2() const {
1472     if (!isMem() || Memory.OffsetRegNum != 0 ||
1473         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1474       return false;
1475     // Immediate offset, multiple of 4 in range [0, 62].
1476     if (!Memory.OffsetImm) return true;
1477     int64_t Val = Memory.OffsetImm->getValue();
1478     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1479   }
1480   bool isMemThumbRIs1() const {
1481     if (!isMem() || Memory.OffsetRegNum != 0 ||
1482         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1483       return false;
1484     // Immediate offset in range [0, 31].
1485     if (!Memory.OffsetImm) return true;
1486     int64_t Val = Memory.OffsetImm->getValue();
1487     return Val >= 0 && Val <= 31;
1488   }
1489   bool isMemThumbSPI() const {
1490     if (!isMem() || Memory.OffsetRegNum != 0 ||
1491         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1492       return false;
1493     // Immediate offset, multiple of 4 in range [0, 1020].
1494     if (!Memory.OffsetImm) return true;
1495     int64_t Val = Memory.OffsetImm->getValue();
1496     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1497   }
1498   bool isMemImm8s4Offset() const {
1499     // If we have an immediate that's not a constant, treat it as a label
1500     // reference needing a fixup. If it is a constant, it's something else
1501     // and we reject it.
1502     if (isImm() && !isa<MCConstantExpr>(getImm()))
1503       return true;
1504     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1505       return false;
1506     // Immediate offset a multiple of 4 in range [-1020, 1020].
1507     if (!Memory.OffsetImm) return true;
1508     int64_t Val = Memory.OffsetImm->getValue();
1509     // Special case, #-0 is INT32_MIN.
1510     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1511   }
1512   bool isMemImm0_1020s4Offset() const {
1513     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1514       return false;
1515     // Immediate offset a multiple of 4 in range [0, 1020].
1516     if (!Memory.OffsetImm) return true;
1517     int64_t Val = Memory.OffsetImm->getValue();
1518     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1519   }
1520   bool isMemImm8Offset() const {
1521     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1522       return false;
1523     // Base reg of PC isn't allowed for these encodings.
1524     if (Memory.BaseRegNum == ARM::PC) return false;
1525     // Immediate offset in range [-255, 255].
1526     if (!Memory.OffsetImm) return true;
1527     int64_t Val = Memory.OffsetImm->getValue();
1528     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1529   }
1530   bool isMemPosImm8Offset() const {
1531     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1532       return false;
1533     // Immediate offset in range [0, 255].
1534     if (!Memory.OffsetImm) return true;
1535     int64_t Val = Memory.OffsetImm->getValue();
1536     return Val >= 0 && Val < 256;
1537   }
1538   bool isMemNegImm8Offset() const {
1539     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1540       return false;
1541     // Base reg of PC isn't allowed for these encodings.
1542     if (Memory.BaseRegNum == ARM::PC) return false;
1543     // Immediate offset in range [-255, -1].
1544     if (!Memory.OffsetImm) return false;
1545     int64_t Val = Memory.OffsetImm->getValue();
1546     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1547   }
1548   bool isMemUImm12Offset() const {
1549     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1550       return false;
1551     // Immediate offset in range [0, 4095].
1552     if (!Memory.OffsetImm) return true;
1553     int64_t Val = Memory.OffsetImm->getValue();
1554     return (Val >= 0 && Val < 4096);
1555   }
1556   bool isMemImm12Offset() const {
1557     // If we have an immediate that's not a constant, treat it as a label
1558     // reference needing a fixup. If it is a constant, it's something else
1559     // and we reject it.
1560 
1561     if (isImm() && !isa<MCConstantExpr>(getImm()))
1562       return true;
1563 
1564     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1565       return false;
1566     // Immediate offset in range [-4095, 4095].
1567     if (!Memory.OffsetImm) return true;
1568     int64_t Val = Memory.OffsetImm->getValue();
1569     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1570   }
1571   bool isConstPoolAsmImm() const {
1572     // Delay processing of Constant Pool Immediate, this will turn into
1573     // a constant. Match no other operand
1574     return (isConstantPoolImm());
1575   }
1576   bool isPostIdxImm8() const {
1577     if (!isImm()) return false;
1578     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1579     if (!CE) return false;
1580     int64_t Val = CE->getValue();
1581     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1582   }
1583   bool isPostIdxImm8s4() const {
1584     if (!isImm()) return false;
1585     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1586     if (!CE) return false;
1587     int64_t Val = CE->getValue();
1588     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1589       (Val == INT32_MIN);
1590   }
1591 
1592   bool isMSRMask() const { return Kind == k_MSRMask; }
1593   bool isBankedReg() const { return Kind == k_BankedReg; }
1594   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1595 
1596   // NEON operands.
1597   bool isSingleSpacedVectorList() const {
1598     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1599   }
1600   bool isDoubleSpacedVectorList() const {
1601     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1602   }
1603   bool isVecListOneD() const {
1604     if (!isSingleSpacedVectorList()) return false;
1605     return VectorList.Count == 1;
1606   }
1607 
1608   bool isVecListDPair() const {
1609     if (!isSingleSpacedVectorList()) return false;
1610     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1611               .contains(VectorList.RegNum));
1612   }
1613 
1614   bool isVecListThreeD() const {
1615     if (!isSingleSpacedVectorList()) return false;
1616     return VectorList.Count == 3;
1617   }
1618 
1619   bool isVecListFourD() const {
1620     if (!isSingleSpacedVectorList()) return false;
1621     return VectorList.Count == 4;
1622   }
1623 
1624   bool isVecListDPairSpaced() const {
1625     if (Kind != k_VectorList) return false;
1626     if (isSingleSpacedVectorList()) return false;
1627     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1628               .contains(VectorList.RegNum));
1629   }
1630 
1631   bool isVecListThreeQ() const {
1632     if (!isDoubleSpacedVectorList()) return false;
1633     return VectorList.Count == 3;
1634   }
1635 
1636   bool isVecListFourQ() const {
1637     if (!isDoubleSpacedVectorList()) return false;
1638     return VectorList.Count == 4;
1639   }
1640 
1641   bool isSingleSpacedVectorAllLanes() const {
1642     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1643   }
1644   bool isDoubleSpacedVectorAllLanes() const {
1645     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1646   }
1647   bool isVecListOneDAllLanes() const {
1648     if (!isSingleSpacedVectorAllLanes()) return false;
1649     return VectorList.Count == 1;
1650   }
1651 
1652   bool isVecListDPairAllLanes() const {
1653     if (!isSingleSpacedVectorAllLanes()) return false;
1654     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1655               .contains(VectorList.RegNum));
1656   }
1657 
1658   bool isVecListDPairSpacedAllLanes() const {
1659     if (!isDoubleSpacedVectorAllLanes()) return false;
1660     return VectorList.Count == 2;
1661   }
1662 
1663   bool isVecListThreeDAllLanes() const {
1664     if (!isSingleSpacedVectorAllLanes()) return false;
1665     return VectorList.Count == 3;
1666   }
1667 
1668   bool isVecListThreeQAllLanes() const {
1669     if (!isDoubleSpacedVectorAllLanes()) return false;
1670     return VectorList.Count == 3;
1671   }
1672 
1673   bool isVecListFourDAllLanes() const {
1674     if (!isSingleSpacedVectorAllLanes()) return false;
1675     return VectorList.Count == 4;
1676   }
1677 
1678   bool isVecListFourQAllLanes() const {
1679     if (!isDoubleSpacedVectorAllLanes()) return false;
1680     return VectorList.Count == 4;
1681   }
1682 
1683   bool isSingleSpacedVectorIndexed() const {
1684     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1685   }
1686   bool isDoubleSpacedVectorIndexed() const {
1687     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1688   }
1689   bool isVecListOneDByteIndexed() const {
1690     if (!isSingleSpacedVectorIndexed()) return false;
1691     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1692   }
1693 
1694   bool isVecListOneDHWordIndexed() const {
1695     if (!isSingleSpacedVectorIndexed()) return false;
1696     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1697   }
1698 
1699   bool isVecListOneDWordIndexed() const {
1700     if (!isSingleSpacedVectorIndexed()) return false;
1701     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1702   }
1703 
1704   bool isVecListTwoDByteIndexed() const {
1705     if (!isSingleSpacedVectorIndexed()) return false;
1706     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1707   }
1708 
1709   bool isVecListTwoDHWordIndexed() const {
1710     if (!isSingleSpacedVectorIndexed()) return false;
1711     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1712   }
1713 
1714   bool isVecListTwoQWordIndexed() const {
1715     if (!isDoubleSpacedVectorIndexed()) return false;
1716     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1717   }
1718 
1719   bool isVecListTwoQHWordIndexed() const {
1720     if (!isDoubleSpacedVectorIndexed()) return false;
1721     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1722   }
1723 
1724   bool isVecListTwoDWordIndexed() const {
1725     if (!isSingleSpacedVectorIndexed()) return false;
1726     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1727   }
1728 
1729   bool isVecListThreeDByteIndexed() const {
1730     if (!isSingleSpacedVectorIndexed()) return false;
1731     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1732   }
1733 
1734   bool isVecListThreeDHWordIndexed() const {
1735     if (!isSingleSpacedVectorIndexed()) return false;
1736     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1737   }
1738 
1739   bool isVecListThreeQWordIndexed() const {
1740     if (!isDoubleSpacedVectorIndexed()) return false;
1741     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1742   }
1743 
1744   bool isVecListThreeQHWordIndexed() const {
1745     if (!isDoubleSpacedVectorIndexed()) return false;
1746     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1747   }
1748 
1749   bool isVecListThreeDWordIndexed() const {
1750     if (!isSingleSpacedVectorIndexed()) return false;
1751     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1752   }
1753 
1754   bool isVecListFourDByteIndexed() const {
1755     if (!isSingleSpacedVectorIndexed()) return false;
1756     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1757   }
1758 
1759   bool isVecListFourDHWordIndexed() const {
1760     if (!isSingleSpacedVectorIndexed()) return false;
1761     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1762   }
1763 
1764   bool isVecListFourQWordIndexed() const {
1765     if (!isDoubleSpacedVectorIndexed()) return false;
1766     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1767   }
1768 
1769   bool isVecListFourQHWordIndexed() const {
1770     if (!isDoubleSpacedVectorIndexed()) return false;
1771     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1772   }
1773 
1774   bool isVecListFourDWordIndexed() const {
1775     if (!isSingleSpacedVectorIndexed()) return false;
1776     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1777   }
1778 
1779   bool isVectorIndex8() const {
1780     if (Kind != k_VectorIndex) return false;
1781     return VectorIndex.Val < 8;
1782   }
1783   bool isVectorIndex16() const {
1784     if (Kind != k_VectorIndex) return false;
1785     return VectorIndex.Val < 4;
1786   }
1787   bool isVectorIndex32() const {
1788     if (Kind != k_VectorIndex) return false;
1789     return VectorIndex.Val < 2;
1790   }
1791 
1792   bool isNEONi8splat() const {
1793     if (!isImm()) return false;
1794     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1795     // Must be a constant.
1796     if (!CE) return false;
1797     int64_t Value = CE->getValue();
1798     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1799     // value.
1800     return Value >= 0 && Value < 256;
1801   }
1802 
1803   bool isNEONi16splat() const {
1804     if (isNEONByteReplicate(2))
1805       return false; // Leave that for bytes replication and forbid by default.
1806     if (!isImm())
1807       return false;
1808     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1809     // Must be a constant.
1810     if (!CE) return false;
1811     unsigned Value = CE->getValue();
1812     return ARM_AM::isNEONi16splat(Value);
1813   }
1814 
1815   bool isNEONi16splatNot() const {
1816     if (!isImm())
1817       return false;
1818     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1819     // Must be a constant.
1820     if (!CE) return false;
1821     unsigned Value = CE->getValue();
1822     return ARM_AM::isNEONi16splat(~Value & 0xffff);
1823   }
1824 
1825   bool isNEONi32splat() const {
1826     if (isNEONByteReplicate(4))
1827       return false; // Leave that for bytes replication and forbid by default.
1828     if (!isImm())
1829       return false;
1830     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1831     // Must be a constant.
1832     if (!CE) return false;
1833     unsigned Value = CE->getValue();
1834     return ARM_AM::isNEONi32splat(Value);
1835   }
1836 
1837   bool isNEONi32splatNot() const {
1838     if (!isImm())
1839       return false;
1840     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1841     // Must be a constant.
1842     if (!CE) return false;
1843     unsigned Value = CE->getValue();
1844     return ARM_AM::isNEONi32splat(~Value);
1845   }
1846 
1847   bool isNEONByteReplicate(unsigned NumBytes) const {
1848     if (!isImm())
1849       return false;
1850     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1851     // Must be a constant.
1852     if (!CE)
1853       return false;
1854     int64_t Value = CE->getValue();
1855     if (!Value)
1856       return false; // Don't bother with zero.
1857 
1858     unsigned char B = Value & 0xff;
1859     for (unsigned i = 1; i < NumBytes; ++i) {
1860       Value >>= 8;
1861       if ((Value & 0xff) != B)
1862         return false;
1863     }
1864     return true;
1865   }
1866   bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1867   bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1868   bool isNEONi32vmov() const {
1869     if (isNEONByteReplicate(4))
1870       return false; // Let it to be classified as byte-replicate case.
1871     if (!isImm())
1872       return false;
1873     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1874     // Must be a constant.
1875     if (!CE)
1876       return false;
1877     int64_t Value = CE->getValue();
1878     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1879     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1880     // FIXME: This is probably wrong and a copy and paste from previous example
1881     return (Value >= 0 && Value < 256) ||
1882       (Value >= 0x0100 && Value <= 0xff00) ||
1883       (Value >= 0x010000 && Value <= 0xff0000) ||
1884       (Value >= 0x01000000 && Value <= 0xff000000) ||
1885       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1886       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1887   }
1888   bool isNEONi32vmovNeg() const {
1889     if (!isImm()) return false;
1890     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1891     // Must be a constant.
1892     if (!CE) return false;
1893     int64_t Value = ~CE->getValue();
1894     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1895     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1896     // FIXME: This is probably wrong and a copy and paste from previous example
1897     return (Value >= 0 && Value < 256) ||
1898       (Value >= 0x0100 && Value <= 0xff00) ||
1899       (Value >= 0x010000 && Value <= 0xff0000) ||
1900       (Value >= 0x01000000 && Value <= 0xff000000) ||
1901       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1902       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1903   }
1904 
1905   bool isNEONi64splat() const {
1906     if (!isImm()) return false;
1907     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1908     // Must be a constant.
1909     if (!CE) return false;
1910     uint64_t Value = CE->getValue();
1911     // i64 value with each byte being either 0 or 0xff.
1912     for (unsigned i = 0; i < 8; ++i, Value >>= 8)
1913       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1914     return true;
1915   }
1916 
1917   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1918     // Add as immediates when possible.  Null MCExpr = 0.
1919     if (!Expr)
1920       Inst.addOperand(MCOperand::createImm(0));
1921     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1922       Inst.addOperand(MCOperand::createImm(CE->getValue()));
1923     else
1924       Inst.addOperand(MCOperand::createExpr(Expr));
1925   }
1926 
1927   void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
1928     assert(N == 1 && "Invalid number of operands!");
1929     addExpr(Inst, getImm());
1930   }
1931 
1932   void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
1933     assert(N == 1 && "Invalid number of operands!");
1934     addExpr(Inst, getImm());
1935   }
1936 
1937   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1938     assert(N == 2 && "Invalid number of operands!");
1939     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1940     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1941     Inst.addOperand(MCOperand::createReg(RegNum));
1942   }
1943 
1944   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1945     assert(N == 1 && "Invalid number of operands!");
1946     Inst.addOperand(MCOperand::createImm(getCoproc()));
1947   }
1948 
1949   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1950     assert(N == 1 && "Invalid number of operands!");
1951     Inst.addOperand(MCOperand::createImm(getCoproc()));
1952   }
1953 
1954   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1955     assert(N == 1 && "Invalid number of operands!");
1956     Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
1957   }
1958 
1959   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1960     assert(N == 1 && "Invalid number of operands!");
1961     Inst.addOperand(MCOperand::createImm(ITMask.Mask));
1962   }
1963 
1964   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1965     assert(N == 1 && "Invalid number of operands!");
1966     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1967   }
1968 
1969   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1970     assert(N == 1 && "Invalid number of operands!");
1971     Inst.addOperand(MCOperand::createReg(getReg()));
1972   }
1973 
1974   void addRegOperands(MCInst &Inst, unsigned N) const {
1975     assert(N == 1 && "Invalid number of operands!");
1976     Inst.addOperand(MCOperand::createReg(getReg()));
1977   }
1978 
1979   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1980     assert(N == 3 && "Invalid number of operands!");
1981     assert(isRegShiftedReg() &&
1982            "addRegShiftedRegOperands() on non-RegShiftedReg!");
1983     Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
1984     Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
1985     Inst.addOperand(MCOperand::createImm(
1986       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1987   }
1988 
1989   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1990     assert(N == 2 && "Invalid number of operands!");
1991     assert(isRegShiftedImm() &&
1992            "addRegShiftedImmOperands() on non-RegShiftedImm!");
1993     Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
1994     // Shift of #32 is encoded as 0 where permitted
1995     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1996     Inst.addOperand(MCOperand::createImm(
1997       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1998   }
1999 
2000   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2001     assert(N == 1 && "Invalid number of operands!");
2002     Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2003                                          ShifterImm.Imm));
2004   }
2005 
2006   void addRegListOperands(MCInst &Inst, unsigned N) const {
2007     assert(N == 1 && "Invalid number of operands!");
2008     const SmallVectorImpl<unsigned> &RegList = getRegList();
2009     for (SmallVectorImpl<unsigned>::const_iterator
2010            I = RegList.begin(), E = RegList.end(); I != E; ++I)
2011       Inst.addOperand(MCOperand::createReg(*I));
2012   }
2013 
2014   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2015     addRegListOperands(Inst, N);
2016   }
2017 
2018   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2019     addRegListOperands(Inst, N);
2020   }
2021 
2022   void addRotImmOperands(MCInst &Inst, unsigned N) const {
2023     assert(N == 1 && "Invalid number of operands!");
2024     // Encoded as val>>3. The printer handles display as 8, 16, 24.
2025     Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2026   }
2027 
2028   void addModImmOperands(MCInst &Inst, unsigned N) const {
2029     assert(N == 1 && "Invalid number of operands!");
2030 
2031     // Support for fixups (MCFixup)
2032     if (isImm())
2033       return addImmOperands(Inst, N);
2034 
2035     Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2036   }
2037 
2038   void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2039     assert(N == 1 && "Invalid number of operands!");
2040     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2041     uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2042     Inst.addOperand(MCOperand::createImm(Enc));
2043   }
2044 
2045   void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2046     assert(N == 1 && "Invalid number of operands!");
2047     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2048     uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2049     Inst.addOperand(MCOperand::createImm(Enc));
2050   }
2051 
2052   void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2053     assert(N == 1 && "Invalid number of operands!");
2054     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2055     uint32_t Val = -CE->getValue();
2056     Inst.addOperand(MCOperand::createImm(Val));
2057   }
2058 
2059   void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2060     assert(N == 1 && "Invalid number of operands!");
2061     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2062     uint32_t Val = -CE->getValue();
2063     Inst.addOperand(MCOperand::createImm(Val));
2064   }
2065 
2066   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2067     assert(N == 1 && "Invalid number of operands!");
2068     // Munge the lsb/width into a bitfield mask.
2069     unsigned lsb = Bitfield.LSB;
2070     unsigned width = Bitfield.Width;
2071     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2072     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2073                       (32 - (lsb + width)));
2074     Inst.addOperand(MCOperand::createImm(Mask));
2075   }
2076 
2077   void addImmOperands(MCInst &Inst, unsigned N) const {
2078     assert(N == 1 && "Invalid number of operands!");
2079     addExpr(Inst, getImm());
2080   }
2081 
2082   void addFBits16Operands(MCInst &Inst, unsigned N) const {
2083     assert(N == 1 && "Invalid number of operands!");
2084     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2085     Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2086   }
2087 
2088   void addFBits32Operands(MCInst &Inst, unsigned N) const {
2089     assert(N == 1 && "Invalid number of operands!");
2090     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2091     Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2092   }
2093 
2094   void addFPImmOperands(MCInst &Inst, unsigned N) const {
2095     assert(N == 1 && "Invalid number of operands!");
2096     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2097     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2098     Inst.addOperand(MCOperand::createImm(Val));
2099   }
2100 
2101   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2102     assert(N == 1 && "Invalid number of operands!");
2103     // FIXME: We really want to scale the value here, but the LDRD/STRD
2104     // instruction don't encode operands that way yet.
2105     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2106     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2107   }
2108 
2109   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2110     assert(N == 1 && "Invalid number of operands!");
2111     // The immediate is scaled by four in the encoding and is stored
2112     // in the MCInst as such. Lop off the low two bits here.
2113     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2114     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2115   }
2116 
2117   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2118     assert(N == 1 && "Invalid number of operands!");
2119     // The immediate is scaled by four in the encoding and is stored
2120     // in the MCInst as such. Lop off the low two bits here.
2121     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2122     Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2123   }
2124 
2125   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2126     assert(N == 1 && "Invalid number of operands!");
2127     // The immediate is scaled by four in the encoding and is stored
2128     // in the MCInst as such. Lop off the low two bits here.
2129     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2130     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2131   }
2132 
2133   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2134     assert(N == 1 && "Invalid number of operands!");
2135     // The constant encodes as the immediate-1, and we store in the instruction
2136     // the bits as encoded, so subtract off one here.
2137     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2138     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2139   }
2140 
2141   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2142     assert(N == 1 && "Invalid number of operands!");
2143     // The constant encodes as the immediate-1, and we store in the instruction
2144     // the bits as encoded, so subtract off one here.
2145     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2146     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2147   }
2148 
2149   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2150     assert(N == 1 && "Invalid number of operands!");
2151     // The constant encodes as the immediate, except for 32, which encodes as
2152     // zero.
2153     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2154     unsigned Imm = CE->getValue();
2155     Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2156   }
2157 
2158   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2159     assert(N == 1 && "Invalid number of operands!");
2160     // An ASR value of 32 encodes as 0, so that's how we want to add it to
2161     // the instruction as well.
2162     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2163     int Val = CE->getValue();
2164     Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2165   }
2166 
2167   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2168     assert(N == 1 && "Invalid number of operands!");
2169     // The operand is actually a t2_so_imm, but we have its bitwise
2170     // negation in the assembly source, so twiddle it here.
2171     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2172     Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
2173   }
2174 
2175   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2176     assert(N == 1 && "Invalid number of operands!");
2177     // The operand is actually a t2_so_imm, but we have its
2178     // negation in the assembly source, so twiddle it here.
2179     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2180     Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2181   }
2182 
2183   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2184     assert(N == 1 && "Invalid number of operands!");
2185     // The operand is actually an imm0_4095, but we have its
2186     // negation in the assembly source, so twiddle it here.
2187     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2188     Inst.addOperand(MCOperand::createImm(-CE->getValue()));
2189   }
2190 
2191   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2192     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2193       Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2194       return;
2195     }
2196 
2197     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2198     assert(SR && "Unknown value type!");
2199     Inst.addOperand(MCOperand::createExpr(SR));
2200   }
2201 
2202   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2203     assert(N == 1 && "Invalid number of operands!");
2204     if (isImm()) {
2205       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2206       if (CE) {
2207         Inst.addOperand(MCOperand::createImm(CE->getValue()));
2208         return;
2209       }
2210 
2211       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2212 
2213       assert(SR && "Unknown value type!");
2214       Inst.addOperand(MCOperand::createExpr(SR));
2215       return;
2216     }
2217 
2218     assert(isMem()  && "Unknown value type!");
2219     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2220     Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2221   }
2222 
2223   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2224     assert(N == 1 && "Invalid number of operands!");
2225     Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2226   }
2227 
2228   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2229     assert(N == 1 && "Invalid number of operands!");
2230     Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2231   }
2232 
2233   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2234     assert(N == 1 && "Invalid number of operands!");
2235     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2236   }
2237 
2238   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2239     assert(N == 1 && "Invalid number of operands!");
2240     int32_t Imm = Memory.OffsetImm->getValue();
2241     Inst.addOperand(MCOperand::createImm(Imm));
2242   }
2243 
2244   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2245     assert(N == 1 && "Invalid number of operands!");
2246     assert(isImm() && "Not an immediate!");
2247 
2248     // If we have an immediate that's not a constant, treat it as a label
2249     // reference needing a fixup.
2250     if (!isa<MCConstantExpr>(getImm())) {
2251       Inst.addOperand(MCOperand::createExpr(getImm()));
2252       return;
2253     }
2254 
2255     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2256     int Val = CE->getValue();
2257     Inst.addOperand(MCOperand::createImm(Val));
2258   }
2259 
2260   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2261     assert(N == 2 && "Invalid number of operands!");
2262     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2263     Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2264   }
2265 
2266   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2267     addAlignedMemoryOperands(Inst, N);
2268   }
2269 
2270   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2271     addAlignedMemoryOperands(Inst, N);
2272   }
2273 
2274   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2275     addAlignedMemoryOperands(Inst, N);
2276   }
2277 
2278   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2279     addAlignedMemoryOperands(Inst, N);
2280   }
2281 
2282   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2283     addAlignedMemoryOperands(Inst, N);
2284   }
2285 
2286   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2287     addAlignedMemoryOperands(Inst, N);
2288   }
2289 
2290   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2291     addAlignedMemoryOperands(Inst, N);
2292   }
2293 
2294   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2295     addAlignedMemoryOperands(Inst, N);
2296   }
2297 
2298   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2299     addAlignedMemoryOperands(Inst, N);
2300   }
2301 
2302   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2303     addAlignedMemoryOperands(Inst, N);
2304   }
2305 
2306   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2307     addAlignedMemoryOperands(Inst, N);
2308   }
2309 
2310   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2311     assert(N == 3 && "Invalid number of operands!");
2312     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2313     if (!Memory.OffsetRegNum) {
2314       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2315       // Special case for #-0
2316       if (Val == INT32_MIN) Val = 0;
2317       if (Val < 0) Val = -Val;
2318       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2319     } else {
2320       // For register offset, we encode the shift type and negation flag
2321       // here.
2322       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2323                               Memory.ShiftImm, Memory.ShiftType);
2324     }
2325     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2326     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2327     Inst.addOperand(MCOperand::createImm(Val));
2328   }
2329 
2330   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2331     assert(N == 2 && "Invalid number of operands!");
2332     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2333     assert(CE && "non-constant AM2OffsetImm operand!");
2334     int32_t Val = CE->getValue();
2335     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2336     // Special case for #-0
2337     if (Val == INT32_MIN) Val = 0;
2338     if (Val < 0) Val = -Val;
2339     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2340     Inst.addOperand(MCOperand::createReg(0));
2341     Inst.addOperand(MCOperand::createImm(Val));
2342   }
2343 
2344   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2345     assert(N == 3 && "Invalid number of operands!");
2346     // If we have an immediate that's not a constant, treat it as a label
2347     // reference needing a fixup. If it is a constant, it's something else
2348     // and we reject it.
2349     if (isImm()) {
2350       Inst.addOperand(MCOperand::createExpr(getImm()));
2351       Inst.addOperand(MCOperand::createReg(0));
2352       Inst.addOperand(MCOperand::createImm(0));
2353       return;
2354     }
2355 
2356     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2357     if (!Memory.OffsetRegNum) {
2358       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2359       // Special case for #-0
2360       if (Val == INT32_MIN) Val = 0;
2361       if (Val < 0) Val = -Val;
2362       Val = ARM_AM::getAM3Opc(AddSub, Val);
2363     } else {
2364       // For register offset, we encode the shift type and negation flag
2365       // here.
2366       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2367     }
2368     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2369     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2370     Inst.addOperand(MCOperand::createImm(Val));
2371   }
2372 
2373   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2374     assert(N == 2 && "Invalid number of operands!");
2375     if (Kind == k_PostIndexRegister) {
2376       int32_t Val =
2377         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2378       Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2379       Inst.addOperand(MCOperand::createImm(Val));
2380       return;
2381     }
2382 
2383     // Constant offset.
2384     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2385     int32_t Val = CE->getValue();
2386     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2387     // Special case for #-0
2388     if (Val == INT32_MIN) Val = 0;
2389     if (Val < 0) Val = -Val;
2390     Val = ARM_AM::getAM3Opc(AddSub, Val);
2391     Inst.addOperand(MCOperand::createReg(0));
2392     Inst.addOperand(MCOperand::createImm(Val));
2393   }
2394 
2395   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2396     assert(N == 2 && "Invalid number of operands!");
2397     // If we have an immediate that's not a constant, treat it as a label
2398     // reference needing a fixup. If it is a constant, it's something else
2399     // and we reject it.
2400     if (isImm()) {
2401       Inst.addOperand(MCOperand::createExpr(getImm()));
2402       Inst.addOperand(MCOperand::createImm(0));
2403       return;
2404     }
2405 
2406     // The lower two bits are always zero and as such are not encoded.
2407     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2408     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2409     // Special case for #-0
2410     if (Val == INT32_MIN) Val = 0;
2411     if (Val < 0) Val = -Val;
2412     Val = ARM_AM::getAM5Opc(AddSub, Val);
2413     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2414     Inst.addOperand(MCOperand::createImm(Val));
2415   }
2416 
2417   void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2418     assert(N == 2 && "Invalid number of operands!");
2419     // If we have an immediate that's not a constant, treat it as a label
2420     // reference needing a fixup. If it is a constant, it's something else
2421     // and we reject it.
2422     if (isImm()) {
2423       Inst.addOperand(MCOperand::createExpr(getImm()));
2424       Inst.addOperand(MCOperand::createImm(0));
2425       return;
2426     }
2427 
2428     // The lower bit is always zero and as such is not encoded.
2429     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2430     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2431     // Special case for #-0
2432     if (Val == INT32_MIN) Val = 0;
2433     if (Val < 0) Val = -Val;
2434     Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2435     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2436     Inst.addOperand(MCOperand::createImm(Val));
2437   }
2438 
2439   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2440     assert(N == 2 && "Invalid number of operands!");
2441     // If we have an immediate that's not a constant, treat it as a label
2442     // reference needing a fixup. If it is a constant, it's something else
2443     // and we reject it.
2444     if (isImm()) {
2445       Inst.addOperand(MCOperand::createExpr(getImm()));
2446       Inst.addOperand(MCOperand::createImm(0));
2447       return;
2448     }
2449 
2450     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2451     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2452     Inst.addOperand(MCOperand::createImm(Val));
2453   }
2454 
2455   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2456     assert(N == 2 && "Invalid number of operands!");
2457     // The lower two bits are always zero and as such are not encoded.
2458     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2459     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2460     Inst.addOperand(MCOperand::createImm(Val));
2461   }
2462 
2463   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2464     assert(N == 2 && "Invalid number of operands!");
2465     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2466     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2467     Inst.addOperand(MCOperand::createImm(Val));
2468   }
2469 
2470   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2471     addMemImm8OffsetOperands(Inst, N);
2472   }
2473 
2474   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2475     addMemImm8OffsetOperands(Inst, N);
2476   }
2477 
2478   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2479     assert(N == 2 && "Invalid number of operands!");
2480     // If this is an immediate, it's a label reference.
2481     if (isImm()) {
2482       addExpr(Inst, getImm());
2483       Inst.addOperand(MCOperand::createImm(0));
2484       return;
2485     }
2486 
2487     // Otherwise, it's a normal memory reg+offset.
2488     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2489     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2490     Inst.addOperand(MCOperand::createImm(Val));
2491   }
2492 
2493   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2494     assert(N == 2 && "Invalid number of operands!");
2495     // If this is an immediate, it's a label reference.
2496     if (isImm()) {
2497       addExpr(Inst, getImm());
2498       Inst.addOperand(MCOperand::createImm(0));
2499       return;
2500     }
2501 
2502     // Otherwise, it's a normal memory reg+offset.
2503     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2504     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2505     Inst.addOperand(MCOperand::createImm(Val));
2506   }
2507 
2508   void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
2509     assert(N == 1 && "Invalid number of operands!");
2510     // This is container for the immediate that we will create the constant
2511     // pool from
2512     addExpr(Inst, getConstantPoolImm());
2513     return;
2514   }
2515 
2516   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2517     assert(N == 2 && "Invalid number of operands!");
2518     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2519     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2520   }
2521 
2522   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2523     assert(N == 2 && "Invalid number of operands!");
2524     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2525     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2526   }
2527 
2528   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2529     assert(N == 3 && "Invalid number of operands!");
2530     unsigned Val =
2531       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2532                         Memory.ShiftImm, Memory.ShiftType);
2533     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2534     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2535     Inst.addOperand(MCOperand::createImm(Val));
2536   }
2537 
2538   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2539     assert(N == 3 && "Invalid number of operands!");
2540     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2541     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2542     Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2543   }
2544 
2545   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2546     assert(N == 2 && "Invalid number of operands!");
2547     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2548     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2549   }
2550 
2551   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2552     assert(N == 2 && "Invalid number of operands!");
2553     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2554     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2555     Inst.addOperand(MCOperand::createImm(Val));
2556   }
2557 
2558   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2559     assert(N == 2 && "Invalid number of operands!");
2560     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2561     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2562     Inst.addOperand(MCOperand::createImm(Val));
2563   }
2564 
2565   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2566     assert(N == 2 && "Invalid number of operands!");
2567     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2568     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2569     Inst.addOperand(MCOperand::createImm(Val));
2570   }
2571 
2572   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2573     assert(N == 2 && "Invalid number of operands!");
2574     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2575     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2576     Inst.addOperand(MCOperand::createImm(Val));
2577   }
2578 
2579   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2580     assert(N == 1 && "Invalid number of operands!");
2581     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2582     assert(CE && "non-constant post-idx-imm8 operand!");
2583     int Imm = CE->getValue();
2584     bool isAdd = Imm >= 0;
2585     if (Imm == INT32_MIN) Imm = 0;
2586     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2587     Inst.addOperand(MCOperand::createImm(Imm));
2588   }
2589 
2590   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2591     assert(N == 1 && "Invalid number of operands!");
2592     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2593     assert(CE && "non-constant post-idx-imm8s4 operand!");
2594     int Imm = CE->getValue();
2595     bool isAdd = Imm >= 0;
2596     if (Imm == INT32_MIN) Imm = 0;
2597     // Immediate is scaled by 4.
2598     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2599     Inst.addOperand(MCOperand::createImm(Imm));
2600   }
2601 
2602   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2603     assert(N == 2 && "Invalid number of operands!");
2604     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2605     Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2606   }
2607 
2608   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2609     assert(N == 2 && "Invalid number of operands!");
2610     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2611     // The sign, shift type, and shift amount are encoded in a single operand
2612     // using the AM2 encoding helpers.
2613     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2614     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2615                                      PostIdxReg.ShiftTy);
2616     Inst.addOperand(MCOperand::createImm(Imm));
2617   }
2618 
2619   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2620     assert(N == 1 && "Invalid number of operands!");
2621     Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2622   }
2623 
2624   void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2625     assert(N == 1 && "Invalid number of operands!");
2626     Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2627   }
2628 
2629   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2630     assert(N == 1 && "Invalid number of operands!");
2631     Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2632   }
2633 
2634   void addVecListOperands(MCInst &Inst, unsigned N) const {
2635     assert(N == 1 && "Invalid number of operands!");
2636     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2637   }
2638 
2639   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2640     assert(N == 2 && "Invalid number of operands!");
2641     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2642     Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2643   }
2644 
2645   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2646     assert(N == 1 && "Invalid number of operands!");
2647     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2648   }
2649 
2650   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2651     assert(N == 1 && "Invalid number of operands!");
2652     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2653   }
2654 
2655   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2656     assert(N == 1 && "Invalid number of operands!");
2657     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2658   }
2659 
2660   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2661     assert(N == 1 && "Invalid number of operands!");
2662     // The immediate encodes the type of constant as well as the value.
2663     // Mask in that this is an i8 splat.
2664     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2665     Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2666   }
2667 
2668   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2669     assert(N == 1 && "Invalid number of operands!");
2670     // The immediate encodes the type of constant as well as the value.
2671     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2672     unsigned Value = CE->getValue();
2673     Value = ARM_AM::encodeNEONi16splat(Value);
2674     Inst.addOperand(MCOperand::createImm(Value));
2675   }
2676 
2677   void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2678     assert(N == 1 && "Invalid number of operands!");
2679     // The immediate encodes the type of constant as well as the value.
2680     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2681     unsigned Value = CE->getValue();
2682     Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2683     Inst.addOperand(MCOperand::createImm(Value));
2684   }
2685 
2686   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2687     assert(N == 1 && "Invalid number of operands!");
2688     // The immediate encodes the type of constant as well as the value.
2689     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2690     unsigned Value = CE->getValue();
2691     Value = ARM_AM::encodeNEONi32splat(Value);
2692     Inst.addOperand(MCOperand::createImm(Value));
2693   }
2694 
2695   void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2696     assert(N == 1 && "Invalid number of operands!");
2697     // The immediate encodes the type of constant as well as the value.
2698     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2699     unsigned Value = CE->getValue();
2700     Value = ARM_AM::encodeNEONi32splat(~Value);
2701     Inst.addOperand(MCOperand::createImm(Value));
2702   }
2703 
2704   void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2705     assert(N == 1 && "Invalid number of operands!");
2706     // The immediate encodes the type of constant as well as the value.
2707     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2708     unsigned Value = CE->getValue();
2709     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2710             Inst.getOpcode() == ARM::VMOVv16i8) &&
2711            "All vmvn instructions that wants to replicate non-zero byte "
2712            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2713     unsigned B = ((~Value) & 0xff);
2714     B |= 0xe00; // cmode = 0b1110
2715     Inst.addOperand(MCOperand::createImm(B));
2716   }
2717   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2718     assert(N == 1 && "Invalid number of operands!");
2719     // The immediate encodes the type of constant as well as the value.
2720     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2721     unsigned Value = CE->getValue();
2722     if (Value >= 256 && Value <= 0xffff)
2723       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2724     else if (Value > 0xffff && Value <= 0xffffff)
2725       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2726     else if (Value > 0xffffff)
2727       Value = (Value >> 24) | 0x600;
2728     Inst.addOperand(MCOperand::createImm(Value));
2729   }
2730 
2731   void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2732     assert(N == 1 && "Invalid number of operands!");
2733     // The immediate encodes the type of constant as well as the value.
2734     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2735     unsigned Value = CE->getValue();
2736     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2737             Inst.getOpcode() == ARM::VMOVv16i8) &&
2738            "All instructions that wants to replicate non-zero byte "
2739            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2740     unsigned B = Value & 0xff;
2741     B |= 0xe00; // cmode = 0b1110
2742     Inst.addOperand(MCOperand::createImm(B));
2743   }
2744   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2745     assert(N == 1 && "Invalid number of operands!");
2746     // The immediate encodes the type of constant as well as the value.
2747     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2748     unsigned Value = ~CE->getValue();
2749     if (Value >= 256 && Value <= 0xffff)
2750       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2751     else if (Value > 0xffff && Value <= 0xffffff)
2752       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2753     else if (Value > 0xffffff)
2754       Value = (Value >> 24) | 0x600;
2755     Inst.addOperand(MCOperand::createImm(Value));
2756   }
2757 
2758   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2759     assert(N == 1 && "Invalid number of operands!");
2760     // The immediate encodes the type of constant as well as the value.
2761     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2762     uint64_t Value = CE->getValue();
2763     unsigned Imm = 0;
2764     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2765       Imm |= (Value & 1) << i;
2766     }
2767     Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2768   }
2769 
2770   void print(raw_ostream &OS) const override;
2771 
2772   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2773     auto Op = make_unique<ARMOperand>(k_ITCondMask);
2774     Op->ITMask.Mask = Mask;
2775     Op->StartLoc = S;
2776     Op->EndLoc = S;
2777     return Op;
2778   }
2779 
2780   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2781                                                     SMLoc S) {
2782     auto Op = make_unique<ARMOperand>(k_CondCode);
2783     Op->CC.Val = CC;
2784     Op->StartLoc = S;
2785     Op->EndLoc = S;
2786     return Op;
2787   }
2788 
2789   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2790     auto Op = make_unique<ARMOperand>(k_CoprocNum);
2791     Op->Cop.Val = CopVal;
2792     Op->StartLoc = S;
2793     Op->EndLoc = S;
2794     return Op;
2795   }
2796 
2797   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2798     auto Op = make_unique<ARMOperand>(k_CoprocReg);
2799     Op->Cop.Val = CopVal;
2800     Op->StartLoc = S;
2801     Op->EndLoc = S;
2802     return Op;
2803   }
2804 
2805   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2806                                                         SMLoc E) {
2807     auto Op = make_unique<ARMOperand>(k_CoprocOption);
2808     Op->Cop.Val = Val;
2809     Op->StartLoc = S;
2810     Op->EndLoc = E;
2811     return Op;
2812   }
2813 
2814   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2815     auto Op = make_unique<ARMOperand>(k_CCOut);
2816     Op->Reg.RegNum = RegNum;
2817     Op->StartLoc = S;
2818     Op->EndLoc = S;
2819     return Op;
2820   }
2821 
2822   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2823     auto Op = make_unique<ARMOperand>(k_Token);
2824     Op->Tok.Data = Str.data();
2825     Op->Tok.Length = Str.size();
2826     Op->StartLoc = S;
2827     Op->EndLoc = S;
2828     return Op;
2829   }
2830 
2831   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2832                                                SMLoc E) {
2833     auto Op = make_unique<ARMOperand>(k_Register);
2834     Op->Reg.RegNum = RegNum;
2835     Op->StartLoc = S;
2836     Op->EndLoc = E;
2837     return Op;
2838   }
2839 
2840   static std::unique_ptr<ARMOperand>
2841   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2842                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2843                         SMLoc E) {
2844     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2845     Op->RegShiftedReg.ShiftTy = ShTy;
2846     Op->RegShiftedReg.SrcReg = SrcReg;
2847     Op->RegShiftedReg.ShiftReg = ShiftReg;
2848     Op->RegShiftedReg.ShiftImm = ShiftImm;
2849     Op->StartLoc = S;
2850     Op->EndLoc = E;
2851     return Op;
2852   }
2853 
2854   static std::unique_ptr<ARMOperand>
2855   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2856                          unsigned ShiftImm, SMLoc S, SMLoc E) {
2857     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2858     Op->RegShiftedImm.ShiftTy = ShTy;
2859     Op->RegShiftedImm.SrcReg = SrcReg;
2860     Op->RegShiftedImm.ShiftImm = ShiftImm;
2861     Op->StartLoc = S;
2862     Op->EndLoc = E;
2863     return Op;
2864   }
2865 
2866   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2867                                                       SMLoc S, SMLoc E) {
2868     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2869     Op->ShifterImm.isASR = isASR;
2870     Op->ShifterImm.Imm = Imm;
2871     Op->StartLoc = S;
2872     Op->EndLoc = E;
2873     return Op;
2874   }
2875 
2876   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2877                                                   SMLoc E) {
2878     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2879     Op->RotImm.Imm = Imm;
2880     Op->StartLoc = S;
2881     Op->EndLoc = E;
2882     return Op;
2883   }
2884 
2885   static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2886                                                   SMLoc S, SMLoc E) {
2887     auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2888     Op->ModImm.Bits = Bits;
2889     Op->ModImm.Rot = Rot;
2890     Op->StartLoc = S;
2891     Op->EndLoc = E;
2892     return Op;
2893   }
2894 
2895   static std::unique_ptr<ARMOperand>
2896   CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2897     auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate);
2898     Op->Imm.Val = Val;
2899     Op->StartLoc = S;
2900     Op->EndLoc = E;
2901     return Op;
2902   }
2903 
2904   static std::unique_ptr<ARMOperand>
2905   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2906     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2907     Op->Bitfield.LSB = LSB;
2908     Op->Bitfield.Width = Width;
2909     Op->StartLoc = S;
2910     Op->EndLoc = E;
2911     return Op;
2912   }
2913 
2914   static std::unique_ptr<ARMOperand>
2915   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2916                 SMLoc StartLoc, SMLoc EndLoc) {
2917     assert (Regs.size() > 0 && "RegList contains no registers?");
2918     KindTy Kind = k_RegisterList;
2919 
2920     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2921       Kind = k_DPRRegisterList;
2922     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2923              contains(Regs.front().second))
2924       Kind = k_SPRRegisterList;
2925 
2926     // Sort based on the register encoding values.
2927     array_pod_sort(Regs.begin(), Regs.end());
2928 
2929     auto Op = make_unique<ARMOperand>(Kind);
2930     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2931            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2932       Op->Registers.push_back(I->second);
2933     Op->StartLoc = StartLoc;
2934     Op->EndLoc = EndLoc;
2935     return Op;
2936   }
2937 
2938   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2939                                                       unsigned Count,
2940                                                       bool isDoubleSpaced,
2941                                                       SMLoc S, SMLoc E) {
2942     auto Op = make_unique<ARMOperand>(k_VectorList);
2943     Op->VectorList.RegNum = RegNum;
2944     Op->VectorList.Count = Count;
2945     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2946     Op->StartLoc = S;
2947     Op->EndLoc = E;
2948     return Op;
2949   }
2950 
2951   static std::unique_ptr<ARMOperand>
2952   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2953                            SMLoc S, SMLoc E) {
2954     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2955     Op->VectorList.RegNum = RegNum;
2956     Op->VectorList.Count = Count;
2957     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2958     Op->StartLoc = S;
2959     Op->EndLoc = E;
2960     return Op;
2961   }
2962 
2963   static std::unique_ptr<ARMOperand>
2964   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2965                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
2966     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2967     Op->VectorList.RegNum = RegNum;
2968     Op->VectorList.Count = Count;
2969     Op->VectorList.LaneIndex = Index;
2970     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2971     Op->StartLoc = S;
2972     Op->EndLoc = E;
2973     return Op;
2974   }
2975 
2976   static std::unique_ptr<ARMOperand>
2977   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2978     auto Op = make_unique<ARMOperand>(k_VectorIndex);
2979     Op->VectorIndex.Val = Idx;
2980     Op->StartLoc = S;
2981     Op->EndLoc = E;
2982     return Op;
2983   }
2984 
2985   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2986                                                SMLoc E) {
2987     auto Op = make_unique<ARMOperand>(k_Immediate);
2988     Op->Imm.Val = Val;
2989     Op->StartLoc = S;
2990     Op->EndLoc = E;
2991     return Op;
2992   }
2993 
2994   static std::unique_ptr<ARMOperand>
2995   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2996             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2997             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2998             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2999     auto Op = make_unique<ARMOperand>(k_Memory);
3000     Op->Memory.BaseRegNum = BaseRegNum;
3001     Op->Memory.OffsetImm = OffsetImm;
3002     Op->Memory.OffsetRegNum = OffsetRegNum;
3003     Op->Memory.ShiftType = ShiftType;
3004     Op->Memory.ShiftImm = ShiftImm;
3005     Op->Memory.Alignment = Alignment;
3006     Op->Memory.isNegative = isNegative;
3007     Op->StartLoc = S;
3008     Op->EndLoc = E;
3009     Op->AlignmentLoc = AlignmentLoc;
3010     return Op;
3011   }
3012 
3013   static std::unique_ptr<ARMOperand>
3014   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3015                    unsigned ShiftImm, SMLoc S, SMLoc E) {
3016     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
3017     Op->PostIdxReg.RegNum = RegNum;
3018     Op->PostIdxReg.isAdd = isAdd;
3019     Op->PostIdxReg.ShiftTy = ShiftTy;
3020     Op->PostIdxReg.ShiftImm = ShiftImm;
3021     Op->StartLoc = S;
3022     Op->EndLoc = E;
3023     return Op;
3024   }
3025 
3026   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3027                                                          SMLoc S) {
3028     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
3029     Op->MBOpt.Val = Opt;
3030     Op->StartLoc = S;
3031     Op->EndLoc = S;
3032     return Op;
3033   }
3034 
3035   static std::unique_ptr<ARMOperand>
3036   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3037     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3038     Op->ISBOpt.Val = Opt;
3039     Op->StartLoc = S;
3040     Op->EndLoc = S;
3041     return Op;
3042   }
3043 
3044   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3045                                                       SMLoc S) {
3046     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
3047     Op->IFlags.Val = IFlags;
3048     Op->StartLoc = S;
3049     Op->EndLoc = S;
3050     return Op;
3051   }
3052 
3053   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3054     auto Op = make_unique<ARMOperand>(k_MSRMask);
3055     Op->MMask.Val = MMask;
3056     Op->StartLoc = S;
3057     Op->EndLoc = S;
3058     return Op;
3059   }
3060 
3061   static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3062     auto Op = make_unique<ARMOperand>(k_BankedReg);
3063     Op->BankedReg.Val = Reg;
3064     Op->StartLoc = S;
3065     Op->EndLoc = S;
3066     return Op;
3067   }
3068 };
3069 
3070 } // end anonymous namespace.
3071 
3072 void ARMOperand::print(raw_ostream &OS) const {
3073   switch (Kind) {
3074   case k_CondCode:
3075     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3076     break;
3077   case k_CCOut:
3078     OS << "<ccout " << getReg() << ">";
3079     break;
3080   case k_ITCondMask: {
3081     static const char *const MaskStr[] = {
3082       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
3083       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
3084     };
3085     assert((ITMask.Mask & 0xf) == ITMask.Mask);
3086     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3087     break;
3088   }
3089   case k_CoprocNum:
3090     OS << "<coprocessor number: " << getCoproc() << ">";
3091     break;
3092   case k_CoprocReg:
3093     OS << "<coprocessor register: " << getCoproc() << ">";
3094     break;
3095   case k_CoprocOption:
3096     OS << "<coprocessor option: " << CoprocOption.Val << ">";
3097     break;
3098   case k_MSRMask:
3099     OS << "<mask: " << getMSRMask() << ">";
3100     break;
3101   case k_BankedReg:
3102     OS << "<banked reg: " << getBankedReg() << ">";
3103     break;
3104   case k_Immediate:
3105     OS << *getImm();
3106     break;
3107   case k_MemBarrierOpt:
3108     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3109     break;
3110   case k_InstSyncBarrierOpt:
3111     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3112     break;
3113   case k_Memory:
3114     OS << "<memory "
3115        << " base:" << Memory.BaseRegNum;
3116     OS << ">";
3117     break;
3118   case k_PostIndexRegister:
3119     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3120        << PostIdxReg.RegNum;
3121     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3122       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3123          << PostIdxReg.ShiftImm;
3124     OS << ">";
3125     break;
3126   case k_ProcIFlags: {
3127     OS << "<ARM_PROC::";
3128     unsigned IFlags = getProcIFlags();
3129     for (int i=2; i >= 0; --i)
3130       if (IFlags & (1 << i))
3131         OS << ARM_PROC::IFlagsToString(1 << i);
3132     OS << ">";
3133     break;
3134   }
3135   case k_Register:
3136     OS << "<register " << getReg() << ">";
3137     break;
3138   case k_ShifterImmediate:
3139     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3140        << " #" << ShifterImm.Imm << ">";
3141     break;
3142   case k_ShiftedRegister:
3143     OS << "<so_reg_reg "
3144        << RegShiftedReg.SrcReg << " "
3145        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
3146        << " " << RegShiftedReg.ShiftReg << ">";
3147     break;
3148   case k_ShiftedImmediate:
3149     OS << "<so_reg_imm "
3150        << RegShiftedImm.SrcReg << " "
3151        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
3152        << " #" << RegShiftedImm.ShiftImm << ">";
3153     break;
3154   case k_RotateImmediate:
3155     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3156     break;
3157   case k_ModifiedImmediate:
3158     OS << "<mod_imm #" << ModImm.Bits << ", #"
3159        <<  ModImm.Rot << ")>";
3160     break;
3161   case k_ConstantPoolImmediate:
3162     OS << "<constant_pool_imm #" << *getConstantPoolImm();
3163     break;
3164   case k_BitfieldDescriptor:
3165     OS << "<bitfield " << "lsb: " << Bitfield.LSB
3166        << ", width: " << Bitfield.Width << ">";
3167     break;
3168   case k_RegisterList:
3169   case k_DPRRegisterList:
3170   case k_SPRRegisterList: {
3171     OS << "<register_list ";
3172 
3173     const SmallVectorImpl<unsigned> &RegList = getRegList();
3174     for (SmallVectorImpl<unsigned>::const_iterator
3175            I = RegList.begin(), E = RegList.end(); I != E; ) {
3176       OS << *I;
3177       if (++I < E) OS << ", ";
3178     }
3179 
3180     OS << ">";
3181     break;
3182   }
3183   case k_VectorList:
3184     OS << "<vector_list " << VectorList.Count << " * "
3185        << VectorList.RegNum << ">";
3186     break;
3187   case k_VectorListAllLanes:
3188     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3189        << VectorList.RegNum << ">";
3190     break;
3191   case k_VectorListIndexed:
3192     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3193        << VectorList.Count << " * " << VectorList.RegNum << ">";
3194     break;
3195   case k_Token:
3196     OS << "'" << getToken() << "'";
3197     break;
3198   case k_VectorIndex:
3199     OS << "<vectorindex " << getVectorIndex() << ">";
3200     break;
3201   }
3202 }
3203 
3204 /// @name Auto-generated Match Functions
3205 /// {
3206 
3207 static unsigned MatchRegisterName(StringRef Name);
3208 
3209 /// }
3210 
3211 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3212                                  SMLoc &StartLoc, SMLoc &EndLoc) {
3213   const AsmToken &Tok = getParser().getTok();
3214   StartLoc = Tok.getLoc();
3215   EndLoc = Tok.getEndLoc();
3216   RegNo = tryParseRegister();
3217 
3218   return (RegNo == (unsigned)-1);
3219 }
3220 
3221 /// Try to parse a register name.  The token must be an Identifier when called,
3222 /// and if it is a register name the token is eaten and the register number is
3223 /// returned.  Otherwise return -1.
3224 ///
3225 int ARMAsmParser::tryParseRegister() {
3226   MCAsmParser &Parser = getParser();
3227   const AsmToken &Tok = Parser.getTok();
3228   if (Tok.isNot(AsmToken::Identifier)) return -1;
3229 
3230   std::string lowerCase = Tok.getString().lower();
3231   unsigned RegNum = MatchRegisterName(lowerCase);
3232   if (!RegNum) {
3233     RegNum = StringSwitch<unsigned>(lowerCase)
3234       .Case("r13", ARM::SP)
3235       .Case("r14", ARM::LR)
3236       .Case("r15", ARM::PC)
3237       .Case("ip", ARM::R12)
3238       // Additional register name aliases for 'gas' compatibility.
3239       .Case("a1", ARM::R0)
3240       .Case("a2", ARM::R1)
3241       .Case("a3", ARM::R2)
3242       .Case("a4", ARM::R3)
3243       .Case("v1", ARM::R4)
3244       .Case("v2", ARM::R5)
3245       .Case("v3", ARM::R6)
3246       .Case("v4", ARM::R7)
3247       .Case("v5", ARM::R8)
3248       .Case("v6", ARM::R9)
3249       .Case("v7", ARM::R10)
3250       .Case("v8", ARM::R11)
3251       .Case("sb", ARM::R9)
3252       .Case("sl", ARM::R10)
3253       .Case("fp", ARM::R11)
3254       .Default(0);
3255   }
3256   if (!RegNum) {
3257     // Check for aliases registered via .req. Canonicalize to lower case.
3258     // That's more consistent since register names are case insensitive, and
3259     // it's how the original entry was passed in from MC/MCParser/AsmParser.
3260     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3261     // If no match, return failure.
3262     if (Entry == RegisterReqs.end())
3263       return -1;
3264     Parser.Lex(); // Eat identifier token.
3265     return Entry->getValue();
3266   }
3267 
3268   // Some FPUs only have 16 D registers, so D16-D31 are invalid
3269   if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3270     return -1;
3271 
3272   Parser.Lex(); // Eat identifier token.
3273 
3274   return RegNum;
3275 }
3276 
3277 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
3278 // If a recoverable error occurs, return 1. If an irrecoverable error
3279 // occurs, return -1. An irrecoverable error is one where tokens have been
3280 // consumed in the process of trying to parse the shifter (i.e., when it is
3281 // indeed a shifter operand, but malformed).
3282 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3283   MCAsmParser &Parser = getParser();
3284   SMLoc S = Parser.getTok().getLoc();
3285   const AsmToken &Tok = Parser.getTok();
3286   if (Tok.isNot(AsmToken::Identifier))
3287     return -1;
3288 
3289   std::string lowerCase = Tok.getString().lower();
3290   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3291       .Case("asl", ARM_AM::lsl)
3292       .Case("lsl", ARM_AM::lsl)
3293       .Case("lsr", ARM_AM::lsr)
3294       .Case("asr", ARM_AM::asr)
3295       .Case("ror", ARM_AM::ror)
3296       .Case("rrx", ARM_AM::rrx)
3297       .Default(ARM_AM::no_shift);
3298 
3299   if (ShiftTy == ARM_AM::no_shift)
3300     return 1;
3301 
3302   Parser.Lex(); // Eat the operator.
3303 
3304   // The source register for the shift has already been added to the
3305   // operand list, so we need to pop it off and combine it into the shifted
3306   // register operand instead.
3307   std::unique_ptr<ARMOperand> PrevOp(
3308       (ARMOperand *)Operands.pop_back_val().release());
3309   if (!PrevOp->isReg())
3310     return Error(PrevOp->getStartLoc(), "shift must be of a register");
3311   int SrcReg = PrevOp->getReg();
3312 
3313   SMLoc EndLoc;
3314   int64_t Imm = 0;
3315   int ShiftReg = 0;
3316   if (ShiftTy == ARM_AM::rrx) {
3317     // RRX Doesn't have an explicit shift amount. The encoder expects
3318     // the shift register to be the same as the source register. Seems odd,
3319     // but OK.
3320     ShiftReg = SrcReg;
3321   } else {
3322     // Figure out if this is shifted by a constant or a register (for non-RRX).
3323     if (Parser.getTok().is(AsmToken::Hash) ||
3324         Parser.getTok().is(AsmToken::Dollar)) {
3325       Parser.Lex(); // Eat hash.
3326       SMLoc ImmLoc = Parser.getTok().getLoc();
3327       const MCExpr *ShiftExpr = nullptr;
3328       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3329         Error(ImmLoc, "invalid immediate shift value");
3330         return -1;
3331       }
3332       // The expression must be evaluatable as an immediate.
3333       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3334       if (!CE) {
3335         Error(ImmLoc, "invalid immediate shift value");
3336         return -1;
3337       }
3338       // Range check the immediate.
3339       // lsl, ror: 0 <= imm <= 31
3340       // lsr, asr: 0 <= imm <= 32
3341       Imm = CE->getValue();
3342       if (Imm < 0 ||
3343           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3344           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3345         Error(ImmLoc, "immediate shift value out of range");
3346         return -1;
3347       }
3348       // shift by zero is a nop. Always send it through as lsl.
3349       // ('as' compatibility)
3350       if (Imm == 0)
3351         ShiftTy = ARM_AM::lsl;
3352     } else if (Parser.getTok().is(AsmToken::Identifier)) {
3353       SMLoc L = Parser.getTok().getLoc();
3354       EndLoc = Parser.getTok().getEndLoc();
3355       ShiftReg = tryParseRegister();
3356       if (ShiftReg == -1) {
3357         Error(L, "expected immediate or register in shift operand");
3358         return -1;
3359       }
3360     } else {
3361       Error(Parser.getTok().getLoc(),
3362             "expected immediate or register in shift operand");
3363       return -1;
3364     }
3365   }
3366 
3367   if (ShiftReg && ShiftTy != ARM_AM::rrx)
3368     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3369                                                          ShiftReg, Imm,
3370                                                          S, EndLoc));
3371   else
3372     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3373                                                           S, EndLoc));
3374 
3375   return 0;
3376 }
3377 
3378 
3379 /// Try to parse a register name.  The token must be an Identifier when called.
3380 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3381 /// if there is a "writeback". 'true' if it's not a register.
3382 ///
3383 /// TODO this is likely to change to allow different register types and or to
3384 /// parse for a specific register type.
3385 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3386   MCAsmParser &Parser = getParser();
3387   const AsmToken &RegTok = Parser.getTok();
3388   int RegNo = tryParseRegister();
3389   if (RegNo == -1)
3390     return true;
3391 
3392   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3393                                            RegTok.getEndLoc()));
3394 
3395   const AsmToken &ExclaimTok = Parser.getTok();
3396   if (ExclaimTok.is(AsmToken::Exclaim)) {
3397     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3398                                                ExclaimTok.getLoc()));
3399     Parser.Lex(); // Eat exclaim token
3400     return false;
3401   }
3402 
3403   // Also check for an index operand. This is only legal for vector registers,
3404   // but that'll get caught OK in operand matching, so we don't need to
3405   // explicitly filter everything else out here.
3406   if (Parser.getTok().is(AsmToken::LBrac)) {
3407     SMLoc SIdx = Parser.getTok().getLoc();
3408     Parser.Lex(); // Eat left bracket token.
3409 
3410     const MCExpr *ImmVal;
3411     if (getParser().parseExpression(ImmVal))
3412       return true;
3413     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3414     if (!MCE)
3415       return TokError("immediate value expected for vector index");
3416 
3417     if (Parser.getTok().isNot(AsmToken::RBrac))
3418       return Error(Parser.getTok().getLoc(), "']' expected");
3419 
3420     SMLoc E = Parser.getTok().getEndLoc();
3421     Parser.Lex(); // Eat right bracket token.
3422 
3423     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3424                                                      SIdx, E,
3425                                                      getContext()));
3426   }
3427 
3428   return false;
3429 }
3430 
3431 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3432 /// instruction with a symbolic operand name.
3433 /// We accept "crN" syntax for GAS compatibility.
3434 /// <operand-name> ::= <prefix><number>
3435 /// If CoprocOp is 'c', then:
3436 ///   <prefix> ::= c | cr
3437 /// If CoprocOp is 'p', then :
3438 ///   <prefix> ::= p
3439 /// <number> ::= integer in range [0, 15]
3440 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3441   // Use the same layout as the tablegen'erated register name matcher. Ugly,
3442   // but efficient.
3443   if (Name.size() < 2 || Name[0] != CoprocOp)
3444     return -1;
3445   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3446 
3447   switch (Name.size()) {
3448   default: return -1;
3449   case 1:
3450     switch (Name[0]) {
3451     default:  return -1;
3452     case '0': return 0;
3453     case '1': return 1;
3454     case '2': return 2;
3455     case '3': return 3;
3456     case '4': return 4;
3457     case '5': return 5;
3458     case '6': return 6;
3459     case '7': return 7;
3460     case '8': return 8;
3461     case '9': return 9;
3462     }
3463   case 2:
3464     if (Name[0] != '1')
3465       return -1;
3466     switch (Name[1]) {
3467     default:  return -1;
3468     // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3469     // However, old cores (v5/v6) did use them in that way.
3470     case '0': return 10;
3471     case '1': return 11;
3472     case '2': return 12;
3473     case '3': return 13;
3474     case '4': return 14;
3475     case '5': return 15;
3476     }
3477   }
3478 }
3479 
3480 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3481 OperandMatchResultTy
3482 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3483   MCAsmParser &Parser = getParser();
3484   SMLoc S = Parser.getTok().getLoc();
3485   const AsmToken &Tok = Parser.getTok();
3486   if (!Tok.is(AsmToken::Identifier))
3487     return MatchOperand_NoMatch;
3488   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3489     .Case("eq", ARMCC::EQ)
3490     .Case("ne", ARMCC::NE)
3491     .Case("hs", ARMCC::HS)
3492     .Case("cs", ARMCC::HS)
3493     .Case("lo", ARMCC::LO)
3494     .Case("cc", ARMCC::LO)
3495     .Case("mi", ARMCC::MI)
3496     .Case("pl", ARMCC::PL)
3497     .Case("vs", ARMCC::VS)
3498     .Case("vc", ARMCC::VC)
3499     .Case("hi", ARMCC::HI)
3500     .Case("ls", ARMCC::LS)
3501     .Case("ge", ARMCC::GE)
3502     .Case("lt", ARMCC::LT)
3503     .Case("gt", ARMCC::GT)
3504     .Case("le", ARMCC::LE)
3505     .Case("al", ARMCC::AL)
3506     .Default(~0U);
3507   if (CC == ~0U)
3508     return MatchOperand_NoMatch;
3509   Parser.Lex(); // Eat the token.
3510 
3511   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3512 
3513   return MatchOperand_Success;
3514 }
3515 
3516 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3517 /// token must be an Identifier when called, and if it is a coprocessor
3518 /// number, the token is eaten and the operand is added to the operand list.
3519 OperandMatchResultTy
3520 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3521   MCAsmParser &Parser = getParser();
3522   SMLoc S = Parser.getTok().getLoc();
3523   const AsmToken &Tok = Parser.getTok();
3524   if (Tok.isNot(AsmToken::Identifier))
3525     return MatchOperand_NoMatch;
3526 
3527   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3528   if (Num == -1)
3529     return MatchOperand_NoMatch;
3530   // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3531   if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3532     return MatchOperand_NoMatch;
3533 
3534   Parser.Lex(); // Eat identifier token.
3535   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3536   return MatchOperand_Success;
3537 }
3538 
3539 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3540 /// token must be an Identifier when called, and if it is a coprocessor
3541 /// number, the token is eaten and the operand is added to the operand list.
3542 OperandMatchResultTy
3543 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3544   MCAsmParser &Parser = getParser();
3545   SMLoc S = Parser.getTok().getLoc();
3546   const AsmToken &Tok = Parser.getTok();
3547   if (Tok.isNot(AsmToken::Identifier))
3548     return MatchOperand_NoMatch;
3549 
3550   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3551   if (Reg == -1)
3552     return MatchOperand_NoMatch;
3553 
3554   Parser.Lex(); // Eat identifier token.
3555   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3556   return MatchOperand_Success;
3557 }
3558 
3559 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3560 /// coproc_option : '{' imm0_255 '}'
3561 OperandMatchResultTy
3562 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3563   MCAsmParser &Parser = getParser();
3564   SMLoc S = Parser.getTok().getLoc();
3565 
3566   // If this isn't a '{', this isn't a coprocessor immediate operand.
3567   if (Parser.getTok().isNot(AsmToken::LCurly))
3568     return MatchOperand_NoMatch;
3569   Parser.Lex(); // Eat the '{'
3570 
3571   const MCExpr *Expr;
3572   SMLoc Loc = Parser.getTok().getLoc();
3573   if (getParser().parseExpression(Expr)) {
3574     Error(Loc, "illegal expression");
3575     return MatchOperand_ParseFail;
3576   }
3577   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3578   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3579     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3580     return MatchOperand_ParseFail;
3581   }
3582   int Val = CE->getValue();
3583 
3584   // Check for and consume the closing '}'
3585   if (Parser.getTok().isNot(AsmToken::RCurly))
3586     return MatchOperand_ParseFail;
3587   SMLoc E = Parser.getTok().getEndLoc();
3588   Parser.Lex(); // Eat the '}'
3589 
3590   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3591   return MatchOperand_Success;
3592 }
3593 
3594 // For register list parsing, we need to map from raw GPR register numbering
3595 // to the enumeration values. The enumeration values aren't sorted by
3596 // register number due to our using "sp", "lr" and "pc" as canonical names.
3597 static unsigned getNextRegister(unsigned Reg) {
3598   // If this is a GPR, we need to do it manually, otherwise we can rely
3599   // on the sort ordering of the enumeration since the other reg-classes
3600   // are sane.
3601   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3602     return Reg + 1;
3603   switch(Reg) {
3604   default: llvm_unreachable("Invalid GPR number!");
3605   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
3606   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
3607   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
3608   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
3609   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
3610   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3611   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
3612   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
3613   }
3614 }
3615 
3616 // Return the low-subreg of a given Q register.
3617 static unsigned getDRegFromQReg(unsigned QReg) {
3618   switch (QReg) {
3619   default: llvm_unreachable("expected a Q register!");
3620   case ARM::Q0:  return ARM::D0;
3621   case ARM::Q1:  return ARM::D2;
3622   case ARM::Q2:  return ARM::D4;
3623   case ARM::Q3:  return ARM::D6;
3624   case ARM::Q4:  return ARM::D8;
3625   case ARM::Q5:  return ARM::D10;
3626   case ARM::Q6:  return ARM::D12;
3627   case ARM::Q7:  return ARM::D14;
3628   case ARM::Q8:  return ARM::D16;
3629   case ARM::Q9:  return ARM::D18;
3630   case ARM::Q10: return ARM::D20;
3631   case ARM::Q11: return ARM::D22;
3632   case ARM::Q12: return ARM::D24;
3633   case ARM::Q13: return ARM::D26;
3634   case ARM::Q14: return ARM::D28;
3635   case ARM::Q15: return ARM::D30;
3636   }
3637 }
3638 
3639 /// Parse a register list.
3640 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3641   MCAsmParser &Parser = getParser();
3642   if (Parser.getTok().isNot(AsmToken::LCurly))
3643     return TokError("Token is not a Left Curly Brace");
3644   SMLoc S = Parser.getTok().getLoc();
3645   Parser.Lex(); // Eat '{' token.
3646   SMLoc RegLoc = Parser.getTok().getLoc();
3647 
3648   // Check the first register in the list to see what register class
3649   // this is a list of.
3650   int Reg = tryParseRegister();
3651   if (Reg == -1)
3652     return Error(RegLoc, "register expected");
3653 
3654   // The reglist instructions have at most 16 registers, so reserve
3655   // space for that many.
3656   int EReg = 0;
3657   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3658 
3659   // Allow Q regs and just interpret them as the two D sub-registers.
3660   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3661     Reg = getDRegFromQReg(Reg);
3662     EReg = MRI->getEncodingValue(Reg);
3663     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3664     ++Reg;
3665   }
3666   const MCRegisterClass *RC;
3667   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3668     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3669   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3670     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3671   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3672     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3673   else
3674     return Error(RegLoc, "invalid register in register list");
3675 
3676   // Store the register.
3677   EReg = MRI->getEncodingValue(Reg);
3678   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3679 
3680   // This starts immediately after the first register token in the list,
3681   // so we can see either a comma or a minus (range separator) as a legal
3682   // next token.
3683   while (Parser.getTok().is(AsmToken::Comma) ||
3684          Parser.getTok().is(AsmToken::Minus)) {
3685     if (Parser.getTok().is(AsmToken::Minus)) {
3686       Parser.Lex(); // Eat the minus.
3687       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3688       int EndReg = tryParseRegister();
3689       if (EndReg == -1)
3690         return Error(AfterMinusLoc, "register expected");
3691       // Allow Q regs and just interpret them as the two D sub-registers.
3692       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3693         EndReg = getDRegFromQReg(EndReg) + 1;
3694       // If the register is the same as the start reg, there's nothing
3695       // more to do.
3696       if (Reg == EndReg)
3697         continue;
3698       // The register must be in the same register class as the first.
3699       if (!RC->contains(EndReg))
3700         return Error(AfterMinusLoc, "invalid register in register list");
3701       // Ranges must go from low to high.
3702       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3703         return Error(AfterMinusLoc, "bad range in register list");
3704 
3705       // Add all the registers in the range to the register list.
3706       while (Reg != EndReg) {
3707         Reg = getNextRegister(Reg);
3708         EReg = MRI->getEncodingValue(Reg);
3709         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3710       }
3711       continue;
3712     }
3713     Parser.Lex(); // Eat the comma.
3714     RegLoc = Parser.getTok().getLoc();
3715     int OldReg = Reg;
3716     const AsmToken RegTok = Parser.getTok();
3717     Reg = tryParseRegister();
3718     if (Reg == -1)
3719       return Error(RegLoc, "register expected");
3720     // Allow Q regs and just interpret them as the two D sub-registers.
3721     bool isQReg = false;
3722     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3723       Reg = getDRegFromQReg(Reg);
3724       isQReg = true;
3725     }
3726     // The register must be in the same register class as the first.
3727     if (!RC->contains(Reg))
3728       return Error(RegLoc, "invalid register in register list");
3729     // List must be monotonically increasing.
3730     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3731       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3732         Warning(RegLoc, "register list not in ascending order");
3733       else
3734         return Error(RegLoc, "register list not in ascending order");
3735     }
3736     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3737       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3738               ") in register list");
3739       continue;
3740     }
3741     // VFP register lists must also be contiguous.
3742     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3743         Reg != OldReg + 1)
3744       return Error(RegLoc, "non-contiguous register range");
3745     EReg = MRI->getEncodingValue(Reg);
3746     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3747     if (isQReg) {
3748       EReg = MRI->getEncodingValue(++Reg);
3749       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3750     }
3751   }
3752 
3753   if (Parser.getTok().isNot(AsmToken::RCurly))
3754     return Error(Parser.getTok().getLoc(), "'}' expected");
3755   SMLoc E = Parser.getTok().getEndLoc();
3756   Parser.Lex(); // Eat '}' token.
3757 
3758   // Push the register list operand.
3759   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3760 
3761   // The ARM system instruction variants for LDM/STM have a '^' token here.
3762   if (Parser.getTok().is(AsmToken::Caret)) {
3763     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3764     Parser.Lex(); // Eat '^' token.
3765   }
3766 
3767   return false;
3768 }
3769 
3770 // Helper function to parse the lane index for vector lists.
3771 OperandMatchResultTy ARMAsmParser::
3772 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3773   MCAsmParser &Parser = getParser();
3774   Index = 0; // Always return a defined index value.
3775   if (Parser.getTok().is(AsmToken::LBrac)) {
3776     Parser.Lex(); // Eat the '['.
3777     if (Parser.getTok().is(AsmToken::RBrac)) {
3778       // "Dn[]" is the 'all lanes' syntax.
3779       LaneKind = AllLanes;
3780       EndLoc = Parser.getTok().getEndLoc();
3781       Parser.Lex(); // Eat the ']'.
3782       return MatchOperand_Success;
3783     }
3784 
3785     // There's an optional '#' token here. Normally there wouldn't be, but
3786     // inline assemble puts one in, and it's friendly to accept that.
3787     if (Parser.getTok().is(AsmToken::Hash))
3788       Parser.Lex(); // Eat '#' or '$'.
3789 
3790     const MCExpr *LaneIndex;
3791     SMLoc Loc = Parser.getTok().getLoc();
3792     if (getParser().parseExpression(LaneIndex)) {
3793       Error(Loc, "illegal expression");
3794       return MatchOperand_ParseFail;
3795     }
3796     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3797     if (!CE) {
3798       Error(Loc, "lane index must be empty or an integer");
3799       return MatchOperand_ParseFail;
3800     }
3801     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3802       Error(Parser.getTok().getLoc(), "']' expected");
3803       return MatchOperand_ParseFail;
3804     }
3805     EndLoc = Parser.getTok().getEndLoc();
3806     Parser.Lex(); // Eat the ']'.
3807     int64_t Val = CE->getValue();
3808 
3809     // FIXME: Make this range check context sensitive for .8, .16, .32.
3810     if (Val < 0 || Val > 7) {
3811       Error(Parser.getTok().getLoc(), "lane index out of range");
3812       return MatchOperand_ParseFail;
3813     }
3814     Index = Val;
3815     LaneKind = IndexedLane;
3816     return MatchOperand_Success;
3817   }
3818   LaneKind = NoLanes;
3819   return MatchOperand_Success;
3820 }
3821 
3822 // parse a vector register list
3823 OperandMatchResultTy
3824 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3825   MCAsmParser &Parser = getParser();
3826   VectorLaneTy LaneKind;
3827   unsigned LaneIndex;
3828   SMLoc S = Parser.getTok().getLoc();
3829   // As an extension (to match gas), support a plain D register or Q register
3830   // (without encosing curly braces) as a single or double entry list,
3831   // respectively.
3832   if (Parser.getTok().is(AsmToken::Identifier)) {
3833     SMLoc E = Parser.getTok().getEndLoc();
3834     int Reg = tryParseRegister();
3835     if (Reg == -1)
3836       return MatchOperand_NoMatch;
3837     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3838       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3839       if (Res != MatchOperand_Success)
3840         return Res;
3841       switch (LaneKind) {
3842       case NoLanes:
3843         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3844         break;
3845       case AllLanes:
3846         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3847                                                                 S, E));
3848         break;
3849       case IndexedLane:
3850         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3851                                                                LaneIndex,
3852                                                                false, S, E));
3853         break;
3854       }
3855       return MatchOperand_Success;
3856     }
3857     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3858       Reg = getDRegFromQReg(Reg);
3859       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3860       if (Res != MatchOperand_Success)
3861         return Res;
3862       switch (LaneKind) {
3863       case NoLanes:
3864         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3865                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3866         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3867         break;
3868       case AllLanes:
3869         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3870                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3871         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3872                                                                 S, E));
3873         break;
3874       case IndexedLane:
3875         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3876                                                                LaneIndex,
3877                                                                false, S, E));
3878         break;
3879       }
3880       return MatchOperand_Success;
3881     }
3882     Error(S, "vector register expected");
3883     return MatchOperand_ParseFail;
3884   }
3885 
3886   if (Parser.getTok().isNot(AsmToken::LCurly))
3887     return MatchOperand_NoMatch;
3888 
3889   Parser.Lex(); // Eat '{' token.
3890   SMLoc RegLoc = Parser.getTok().getLoc();
3891 
3892   int Reg = tryParseRegister();
3893   if (Reg == -1) {
3894     Error(RegLoc, "register expected");
3895     return MatchOperand_ParseFail;
3896   }
3897   unsigned Count = 1;
3898   int Spacing = 0;
3899   unsigned FirstReg = Reg;
3900   // The list is of D registers, but we also allow Q regs and just interpret
3901   // them as the two D sub-registers.
3902   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3903     FirstReg = Reg = getDRegFromQReg(Reg);
3904     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3905                  // it's ambiguous with four-register single spaced.
3906     ++Reg;
3907     ++Count;
3908   }
3909 
3910   SMLoc E;
3911   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3912     return MatchOperand_ParseFail;
3913 
3914   while (Parser.getTok().is(AsmToken::Comma) ||
3915          Parser.getTok().is(AsmToken::Minus)) {
3916     if (Parser.getTok().is(AsmToken::Minus)) {
3917       if (!Spacing)
3918         Spacing = 1; // Register range implies a single spaced list.
3919       else if (Spacing == 2) {
3920         Error(Parser.getTok().getLoc(),
3921               "sequential registers in double spaced list");
3922         return MatchOperand_ParseFail;
3923       }
3924       Parser.Lex(); // Eat the minus.
3925       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3926       int EndReg = tryParseRegister();
3927       if (EndReg == -1) {
3928         Error(AfterMinusLoc, "register expected");
3929         return MatchOperand_ParseFail;
3930       }
3931       // Allow Q regs and just interpret them as the two D sub-registers.
3932       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3933         EndReg = getDRegFromQReg(EndReg) + 1;
3934       // If the register is the same as the start reg, there's nothing
3935       // more to do.
3936       if (Reg == EndReg)
3937         continue;
3938       // The register must be in the same register class as the first.
3939       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3940         Error(AfterMinusLoc, "invalid register in register list");
3941         return MatchOperand_ParseFail;
3942       }
3943       // Ranges must go from low to high.
3944       if (Reg > EndReg) {
3945         Error(AfterMinusLoc, "bad range in register list");
3946         return MatchOperand_ParseFail;
3947       }
3948       // Parse the lane specifier if present.
3949       VectorLaneTy NextLaneKind;
3950       unsigned NextLaneIndex;
3951       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3952           MatchOperand_Success)
3953         return MatchOperand_ParseFail;
3954       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3955         Error(AfterMinusLoc, "mismatched lane index in register list");
3956         return MatchOperand_ParseFail;
3957       }
3958 
3959       // Add all the registers in the range to the register list.
3960       Count += EndReg - Reg;
3961       Reg = EndReg;
3962       continue;
3963     }
3964     Parser.Lex(); // Eat the comma.
3965     RegLoc = Parser.getTok().getLoc();
3966     int OldReg = Reg;
3967     Reg = tryParseRegister();
3968     if (Reg == -1) {
3969       Error(RegLoc, "register expected");
3970       return MatchOperand_ParseFail;
3971     }
3972     // vector register lists must be contiguous.
3973     // It's OK to use the enumeration values directly here rather, as the
3974     // VFP register classes have the enum sorted properly.
3975     //
3976     // The list is of D registers, but we also allow Q regs and just interpret
3977     // them as the two D sub-registers.
3978     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3979       if (!Spacing)
3980         Spacing = 1; // Register range implies a single spaced list.
3981       else if (Spacing == 2) {
3982         Error(RegLoc,
3983               "invalid register in double-spaced list (must be 'D' register')");
3984         return MatchOperand_ParseFail;
3985       }
3986       Reg = getDRegFromQReg(Reg);
3987       if (Reg != OldReg + 1) {
3988         Error(RegLoc, "non-contiguous register range");
3989         return MatchOperand_ParseFail;
3990       }
3991       ++Reg;
3992       Count += 2;
3993       // Parse the lane specifier if present.
3994       VectorLaneTy NextLaneKind;
3995       unsigned NextLaneIndex;
3996       SMLoc LaneLoc = Parser.getTok().getLoc();
3997       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3998           MatchOperand_Success)
3999         return MatchOperand_ParseFail;
4000       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4001         Error(LaneLoc, "mismatched lane index in register list");
4002         return MatchOperand_ParseFail;
4003       }
4004       continue;
4005     }
4006     // Normal D register.
4007     // Figure out the register spacing (single or double) of the list if
4008     // we don't know it already.
4009     if (!Spacing)
4010       Spacing = 1 + (Reg == OldReg + 2);
4011 
4012     // Just check that it's contiguous and keep going.
4013     if (Reg != OldReg + Spacing) {
4014       Error(RegLoc, "non-contiguous register range");
4015       return MatchOperand_ParseFail;
4016     }
4017     ++Count;
4018     // Parse the lane specifier if present.
4019     VectorLaneTy NextLaneKind;
4020     unsigned NextLaneIndex;
4021     SMLoc EndLoc = Parser.getTok().getLoc();
4022     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4023       return MatchOperand_ParseFail;
4024     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4025       Error(EndLoc, "mismatched lane index in register list");
4026       return MatchOperand_ParseFail;
4027     }
4028   }
4029 
4030   if (Parser.getTok().isNot(AsmToken::RCurly)) {
4031     Error(Parser.getTok().getLoc(), "'}' expected");
4032     return MatchOperand_ParseFail;
4033   }
4034   E = Parser.getTok().getEndLoc();
4035   Parser.Lex(); // Eat '}' token.
4036 
4037   switch (LaneKind) {
4038   case NoLanes:
4039     // Two-register operands have been converted to the
4040     // composite register classes.
4041     if (Count == 2) {
4042       const MCRegisterClass *RC = (Spacing == 1) ?
4043         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4044         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4045       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4046     }
4047 
4048     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
4049                                                     (Spacing == 2), S, E));
4050     break;
4051   case AllLanes:
4052     // Two-register operands have been converted to the
4053     // composite register classes.
4054     if (Count == 2) {
4055       const MCRegisterClass *RC = (Spacing == 1) ?
4056         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4057         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4058       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4059     }
4060     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
4061                                                             (Spacing == 2),
4062                                                             S, E));
4063     break;
4064   case IndexedLane:
4065     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4066                                                            LaneIndex,
4067                                                            (Spacing == 2),
4068                                                            S, E));
4069     break;
4070   }
4071   return MatchOperand_Success;
4072 }
4073 
4074 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4075 OperandMatchResultTy
4076 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4077   MCAsmParser &Parser = getParser();
4078   SMLoc S = Parser.getTok().getLoc();
4079   const AsmToken &Tok = Parser.getTok();
4080   unsigned Opt;
4081 
4082   if (Tok.is(AsmToken::Identifier)) {
4083     StringRef OptStr = Tok.getString();
4084 
4085     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4086       .Case("sy",    ARM_MB::SY)
4087       .Case("st",    ARM_MB::ST)
4088       .Case("ld",    ARM_MB::LD)
4089       .Case("sh",    ARM_MB::ISH)
4090       .Case("ish",   ARM_MB::ISH)
4091       .Case("shst",  ARM_MB::ISHST)
4092       .Case("ishst", ARM_MB::ISHST)
4093       .Case("ishld", ARM_MB::ISHLD)
4094       .Case("nsh",   ARM_MB::NSH)
4095       .Case("un",    ARM_MB::NSH)
4096       .Case("nshst", ARM_MB::NSHST)
4097       .Case("nshld", ARM_MB::NSHLD)
4098       .Case("unst",  ARM_MB::NSHST)
4099       .Case("osh",   ARM_MB::OSH)
4100       .Case("oshst", ARM_MB::OSHST)
4101       .Case("oshld", ARM_MB::OSHLD)
4102       .Default(~0U);
4103 
4104     // ishld, oshld, nshld and ld are only available from ARMv8.
4105     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4106                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4107       Opt = ~0U;
4108 
4109     if (Opt == ~0U)
4110       return MatchOperand_NoMatch;
4111 
4112     Parser.Lex(); // Eat identifier token.
4113   } else if (Tok.is(AsmToken::Hash) ||
4114              Tok.is(AsmToken::Dollar) ||
4115              Tok.is(AsmToken::Integer)) {
4116     if (Parser.getTok().isNot(AsmToken::Integer))
4117       Parser.Lex(); // Eat '#' or '$'.
4118     SMLoc Loc = Parser.getTok().getLoc();
4119 
4120     const MCExpr *MemBarrierID;
4121     if (getParser().parseExpression(MemBarrierID)) {
4122       Error(Loc, "illegal expression");
4123       return MatchOperand_ParseFail;
4124     }
4125 
4126     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4127     if (!CE) {
4128       Error(Loc, "constant expression expected");
4129       return MatchOperand_ParseFail;
4130     }
4131 
4132     int Val = CE->getValue();
4133     if (Val & ~0xf) {
4134       Error(Loc, "immediate value out of range");
4135       return MatchOperand_ParseFail;
4136     }
4137 
4138     Opt = ARM_MB::RESERVED_0 + Val;
4139   } else
4140     return MatchOperand_ParseFail;
4141 
4142   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4143   return MatchOperand_Success;
4144 }
4145 
4146 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4147 OperandMatchResultTy
4148 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4149   MCAsmParser &Parser = getParser();
4150   SMLoc S = Parser.getTok().getLoc();
4151   const AsmToken &Tok = Parser.getTok();
4152   unsigned Opt;
4153 
4154   if (Tok.is(AsmToken::Identifier)) {
4155     StringRef OptStr = Tok.getString();
4156 
4157     if (OptStr.equals_lower("sy"))
4158       Opt = ARM_ISB::SY;
4159     else
4160       return MatchOperand_NoMatch;
4161 
4162     Parser.Lex(); // Eat identifier token.
4163   } else if (Tok.is(AsmToken::Hash) ||
4164              Tok.is(AsmToken::Dollar) ||
4165              Tok.is(AsmToken::Integer)) {
4166     if (Parser.getTok().isNot(AsmToken::Integer))
4167       Parser.Lex(); // Eat '#' or '$'.
4168     SMLoc Loc = Parser.getTok().getLoc();
4169 
4170     const MCExpr *ISBarrierID;
4171     if (getParser().parseExpression(ISBarrierID)) {
4172       Error(Loc, "illegal expression");
4173       return MatchOperand_ParseFail;
4174     }
4175 
4176     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4177     if (!CE) {
4178       Error(Loc, "constant expression expected");
4179       return MatchOperand_ParseFail;
4180     }
4181 
4182     int Val = CE->getValue();
4183     if (Val & ~0xf) {
4184       Error(Loc, "immediate value out of range");
4185       return MatchOperand_ParseFail;
4186     }
4187 
4188     Opt = ARM_ISB::RESERVED_0 + Val;
4189   } else
4190     return MatchOperand_ParseFail;
4191 
4192   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4193           (ARM_ISB::InstSyncBOpt)Opt, S));
4194   return MatchOperand_Success;
4195 }
4196 
4197 
4198 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4199 OperandMatchResultTy
4200 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4201   MCAsmParser &Parser = getParser();
4202   SMLoc S = Parser.getTok().getLoc();
4203   const AsmToken &Tok = Parser.getTok();
4204   if (!Tok.is(AsmToken::Identifier))
4205     return MatchOperand_NoMatch;
4206   StringRef IFlagsStr = Tok.getString();
4207 
4208   // An iflags string of "none" is interpreted to mean that none of the AIF
4209   // bits are set.  Not a terribly useful instruction, but a valid encoding.
4210   unsigned IFlags = 0;
4211   if (IFlagsStr != "none") {
4212         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4213       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
4214         .Case("a", ARM_PROC::A)
4215         .Case("i", ARM_PROC::I)
4216         .Case("f", ARM_PROC::F)
4217         .Default(~0U);
4218 
4219       // If some specific iflag is already set, it means that some letter is
4220       // present more than once, this is not acceptable.
4221       if (Flag == ~0U || (IFlags & Flag))
4222         return MatchOperand_NoMatch;
4223 
4224       IFlags |= Flag;
4225     }
4226   }
4227 
4228   Parser.Lex(); // Eat identifier token.
4229   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4230   return MatchOperand_Success;
4231 }
4232 
4233 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4234 OperandMatchResultTy
4235 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4236   MCAsmParser &Parser = getParser();
4237   SMLoc S = Parser.getTok().getLoc();
4238   const AsmToken &Tok = Parser.getTok();
4239   if (!Tok.is(AsmToken::Identifier))
4240     return MatchOperand_NoMatch;
4241   StringRef Mask = Tok.getString();
4242 
4243   if (isMClass()) {
4244     // See ARMv6-M 10.1.1
4245     std::string Name = Mask.lower();
4246     unsigned FlagsVal = StringSwitch<unsigned>(Name)
4247       // Note: in the documentation:
4248       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
4249       //  for MSR APSR_nzcvq.
4250       // but we do make it an alias here.  This is so to get the "mask encoding"
4251       // bits correct on MSR APSR writes.
4252       //
4253       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
4254       // should really only be allowed when writing a special register.  Note
4255       // they get dropped in the MRS instruction reading a special register as
4256       // the SYSm field is only 8 bits.
4257       .Case("apsr", 0x800)
4258       .Case("apsr_nzcvq", 0x800)
4259       .Case("apsr_g", 0x400)
4260       .Case("apsr_nzcvqg", 0xc00)
4261       .Case("iapsr", 0x801)
4262       .Case("iapsr_nzcvq", 0x801)
4263       .Case("iapsr_g", 0x401)
4264       .Case("iapsr_nzcvqg", 0xc01)
4265       .Case("eapsr", 0x802)
4266       .Case("eapsr_nzcvq", 0x802)
4267       .Case("eapsr_g", 0x402)
4268       .Case("eapsr_nzcvqg", 0xc02)
4269       .Case("xpsr", 0x803)
4270       .Case("xpsr_nzcvq", 0x803)
4271       .Case("xpsr_g", 0x403)
4272       .Case("xpsr_nzcvqg", 0xc03)
4273       .Case("ipsr", 0x805)
4274       .Case("epsr", 0x806)
4275       .Case("iepsr", 0x807)
4276       .Case("msp", 0x808)
4277       .Case("psp", 0x809)
4278       .Case("primask", 0x810)
4279       .Case("basepri", 0x811)
4280       .Case("basepri_max", 0x812)
4281       .Case("faultmask", 0x813)
4282       .Case("control", 0x814)
4283       .Case("msplim", 0x80a)
4284       .Case("psplim", 0x80b)
4285       .Case("msp_ns", 0x888)
4286       .Case("psp_ns", 0x889)
4287       .Case("msplim_ns", 0x88a)
4288       .Case("psplim_ns", 0x88b)
4289       .Case("primask_ns", 0x890)
4290       .Case("basepri_ns", 0x891)
4291       .Case("basepri_max_ns", 0x892)
4292       .Case("faultmask_ns", 0x893)
4293       .Case("control_ns", 0x894)
4294       .Case("sp_ns", 0x898)
4295       .Default(~0U);
4296 
4297     if (FlagsVal == ~0U)
4298       return MatchOperand_NoMatch;
4299 
4300     if (!hasDSP() && (FlagsVal & 0x400))
4301       // The _g and _nzcvqg versions are only valid if the DSP extension is
4302       // available.
4303       return MatchOperand_NoMatch;
4304 
4305     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4306       // basepri, basepri_max and faultmask only valid for V7m.
4307       return MatchOperand_NoMatch;
4308 
4309     if (!has8MSecExt() && (FlagsVal == 0x80a || FlagsVal == 0x80b ||
4310                              (FlagsVal > 0x814 && FlagsVal < 0xc00)))
4311       return MatchOperand_NoMatch;
4312 
4313     if (!hasV8MMainline() && (FlagsVal == 0x88a || FlagsVal == 0x88b ||
4314                               (FlagsVal > 0x890 && FlagsVal <= 0x893)))
4315       return MatchOperand_NoMatch;
4316 
4317     Parser.Lex(); // Eat identifier token.
4318     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4319     return MatchOperand_Success;
4320   }
4321 
4322   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4323   size_t Start = 0, Next = Mask.find('_');
4324   StringRef Flags = "";
4325   std::string SpecReg = Mask.slice(Start, Next).lower();
4326   if (Next != StringRef::npos)
4327     Flags = Mask.slice(Next+1, Mask.size());
4328 
4329   // FlagsVal contains the complete mask:
4330   // 3-0: Mask
4331   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4332   unsigned FlagsVal = 0;
4333 
4334   if (SpecReg == "apsr") {
4335     FlagsVal = StringSwitch<unsigned>(Flags)
4336     .Case("nzcvq",  0x8) // same as CPSR_f
4337     .Case("g",      0x4) // same as CPSR_s
4338     .Case("nzcvqg", 0xc) // same as CPSR_fs
4339     .Default(~0U);
4340 
4341     if (FlagsVal == ~0U) {
4342       if (!Flags.empty())
4343         return MatchOperand_NoMatch;
4344       else
4345         FlagsVal = 8; // No flag
4346     }
4347   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4348     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4349     if (Flags == "all" || Flags == "")
4350       Flags = "fc";
4351     for (int i = 0, e = Flags.size(); i != e; ++i) {
4352       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4353       .Case("c", 1)
4354       .Case("x", 2)
4355       .Case("s", 4)
4356       .Case("f", 8)
4357       .Default(~0U);
4358 
4359       // If some specific flag is already set, it means that some letter is
4360       // present more than once, this is not acceptable.
4361       if (Flag == ~0U || (FlagsVal & Flag))
4362         return MatchOperand_NoMatch;
4363       FlagsVal |= Flag;
4364     }
4365   } else // No match for special register.
4366     return MatchOperand_NoMatch;
4367 
4368   // Special register without flags is NOT equivalent to "fc" flags.
4369   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
4370   // two lines would enable gas compatibility at the expense of breaking
4371   // round-tripping.
4372   //
4373   // if (!FlagsVal)
4374   //  FlagsVal = 0x9;
4375 
4376   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4377   if (SpecReg == "spsr")
4378     FlagsVal |= 16;
4379 
4380   Parser.Lex(); // Eat identifier token.
4381   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4382   return MatchOperand_Success;
4383 }
4384 
4385 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4386 /// use in the MRS/MSR instructions added to support virtualization.
4387 OperandMatchResultTy
4388 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4389   MCAsmParser &Parser = getParser();
4390   SMLoc S = Parser.getTok().getLoc();
4391   const AsmToken &Tok = Parser.getTok();
4392   if (!Tok.is(AsmToken::Identifier))
4393     return MatchOperand_NoMatch;
4394   StringRef RegName = Tok.getString();
4395 
4396   // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4397   // and bit 5 is R.
4398   unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4399                           .Case("r8_usr", 0x00)
4400                           .Case("r9_usr", 0x01)
4401                           .Case("r10_usr", 0x02)
4402                           .Case("r11_usr", 0x03)
4403                           .Case("r12_usr", 0x04)
4404                           .Case("sp_usr", 0x05)
4405                           .Case("lr_usr", 0x06)
4406                           .Case("r8_fiq", 0x08)
4407                           .Case("r9_fiq", 0x09)
4408                           .Case("r10_fiq", 0x0a)
4409                           .Case("r11_fiq", 0x0b)
4410                           .Case("r12_fiq", 0x0c)
4411                           .Case("sp_fiq", 0x0d)
4412                           .Case("lr_fiq", 0x0e)
4413                           .Case("lr_irq", 0x10)
4414                           .Case("sp_irq", 0x11)
4415                           .Case("lr_svc", 0x12)
4416                           .Case("sp_svc", 0x13)
4417                           .Case("lr_abt", 0x14)
4418                           .Case("sp_abt", 0x15)
4419                           .Case("lr_und", 0x16)
4420                           .Case("sp_und", 0x17)
4421                           .Case("lr_mon", 0x1c)
4422                           .Case("sp_mon", 0x1d)
4423                           .Case("elr_hyp", 0x1e)
4424                           .Case("sp_hyp", 0x1f)
4425                           .Case("spsr_fiq", 0x2e)
4426                           .Case("spsr_irq", 0x30)
4427                           .Case("spsr_svc", 0x32)
4428                           .Case("spsr_abt", 0x34)
4429                           .Case("spsr_und", 0x36)
4430                           .Case("spsr_mon", 0x3c)
4431                           .Case("spsr_hyp", 0x3e)
4432                           .Default(~0U);
4433 
4434   if (Encoding == ~0U)
4435     return MatchOperand_NoMatch;
4436 
4437   Parser.Lex(); // Eat identifier token.
4438   Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4439   return MatchOperand_Success;
4440 }
4441 
4442 OperandMatchResultTy
4443 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4444                           int High) {
4445   MCAsmParser &Parser = getParser();
4446   const AsmToken &Tok = Parser.getTok();
4447   if (Tok.isNot(AsmToken::Identifier)) {
4448     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4449     return MatchOperand_ParseFail;
4450   }
4451   StringRef ShiftName = Tok.getString();
4452   std::string LowerOp = Op.lower();
4453   std::string UpperOp = Op.upper();
4454   if (ShiftName != LowerOp && ShiftName != UpperOp) {
4455     Error(Parser.getTok().getLoc(), Op + " operand expected.");
4456     return MatchOperand_ParseFail;
4457   }
4458   Parser.Lex(); // Eat shift type token.
4459 
4460   // There must be a '#' and a shift amount.
4461   if (Parser.getTok().isNot(AsmToken::Hash) &&
4462       Parser.getTok().isNot(AsmToken::Dollar)) {
4463     Error(Parser.getTok().getLoc(), "'#' expected");
4464     return MatchOperand_ParseFail;
4465   }
4466   Parser.Lex(); // Eat hash token.
4467 
4468   const MCExpr *ShiftAmount;
4469   SMLoc Loc = Parser.getTok().getLoc();
4470   SMLoc EndLoc;
4471   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4472     Error(Loc, "illegal expression");
4473     return MatchOperand_ParseFail;
4474   }
4475   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4476   if (!CE) {
4477     Error(Loc, "constant expression expected");
4478     return MatchOperand_ParseFail;
4479   }
4480   int Val = CE->getValue();
4481   if (Val < Low || Val > High) {
4482     Error(Loc, "immediate value out of range");
4483     return MatchOperand_ParseFail;
4484   }
4485 
4486   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4487 
4488   return MatchOperand_Success;
4489 }
4490 
4491 OperandMatchResultTy
4492 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4493   MCAsmParser &Parser = getParser();
4494   const AsmToken &Tok = Parser.getTok();
4495   SMLoc S = Tok.getLoc();
4496   if (Tok.isNot(AsmToken::Identifier)) {
4497     Error(S, "'be' or 'le' operand expected");
4498     return MatchOperand_ParseFail;
4499   }
4500   int Val = StringSwitch<int>(Tok.getString().lower())
4501     .Case("be", 1)
4502     .Case("le", 0)
4503     .Default(-1);
4504   Parser.Lex(); // Eat the token.
4505 
4506   if (Val == -1) {
4507     Error(S, "'be' or 'le' operand expected");
4508     return MatchOperand_ParseFail;
4509   }
4510   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4511                                                                   getContext()),
4512                                            S, Tok.getEndLoc()));
4513   return MatchOperand_Success;
4514 }
4515 
4516 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4517 /// instructions. Legal values are:
4518 ///     lsl #n  'n' in [0,31]
4519 ///     asr #n  'n' in [1,32]
4520 ///             n == 32 encoded as n == 0.
4521 OperandMatchResultTy
4522 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4523   MCAsmParser &Parser = getParser();
4524   const AsmToken &Tok = Parser.getTok();
4525   SMLoc S = Tok.getLoc();
4526   if (Tok.isNot(AsmToken::Identifier)) {
4527     Error(S, "shift operator 'asr' or 'lsl' expected");
4528     return MatchOperand_ParseFail;
4529   }
4530   StringRef ShiftName = Tok.getString();
4531   bool isASR;
4532   if (ShiftName == "lsl" || ShiftName == "LSL")
4533     isASR = false;
4534   else if (ShiftName == "asr" || ShiftName == "ASR")
4535     isASR = true;
4536   else {
4537     Error(S, "shift operator 'asr' or 'lsl' expected");
4538     return MatchOperand_ParseFail;
4539   }
4540   Parser.Lex(); // Eat the operator.
4541 
4542   // A '#' and a shift amount.
4543   if (Parser.getTok().isNot(AsmToken::Hash) &&
4544       Parser.getTok().isNot(AsmToken::Dollar)) {
4545     Error(Parser.getTok().getLoc(), "'#' expected");
4546     return MatchOperand_ParseFail;
4547   }
4548   Parser.Lex(); // Eat hash token.
4549   SMLoc ExLoc = Parser.getTok().getLoc();
4550 
4551   const MCExpr *ShiftAmount;
4552   SMLoc EndLoc;
4553   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4554     Error(ExLoc, "malformed shift expression");
4555     return MatchOperand_ParseFail;
4556   }
4557   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4558   if (!CE) {
4559     Error(ExLoc, "shift amount must be an immediate");
4560     return MatchOperand_ParseFail;
4561   }
4562 
4563   int64_t Val = CE->getValue();
4564   if (isASR) {
4565     // Shift amount must be in [1,32]
4566     if (Val < 1 || Val > 32) {
4567       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4568       return MatchOperand_ParseFail;
4569     }
4570     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4571     if (isThumb() && Val == 32) {
4572       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4573       return MatchOperand_ParseFail;
4574     }
4575     if (Val == 32) Val = 0;
4576   } else {
4577     // Shift amount must be in [1,32]
4578     if (Val < 0 || Val > 31) {
4579       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4580       return MatchOperand_ParseFail;
4581     }
4582   }
4583 
4584   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4585 
4586   return MatchOperand_Success;
4587 }
4588 
4589 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4590 /// of instructions. Legal values are:
4591 ///     ror #n  'n' in {0, 8, 16, 24}
4592 OperandMatchResultTy
4593 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4594   MCAsmParser &Parser = getParser();
4595   const AsmToken &Tok = Parser.getTok();
4596   SMLoc S = Tok.getLoc();
4597   if (Tok.isNot(AsmToken::Identifier))
4598     return MatchOperand_NoMatch;
4599   StringRef ShiftName = Tok.getString();
4600   if (ShiftName != "ror" && ShiftName != "ROR")
4601     return MatchOperand_NoMatch;
4602   Parser.Lex(); // Eat the operator.
4603 
4604   // A '#' and a rotate amount.
4605   if (Parser.getTok().isNot(AsmToken::Hash) &&
4606       Parser.getTok().isNot(AsmToken::Dollar)) {
4607     Error(Parser.getTok().getLoc(), "'#' expected");
4608     return MatchOperand_ParseFail;
4609   }
4610   Parser.Lex(); // Eat hash token.
4611   SMLoc ExLoc = Parser.getTok().getLoc();
4612 
4613   const MCExpr *ShiftAmount;
4614   SMLoc EndLoc;
4615   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4616     Error(ExLoc, "malformed rotate expression");
4617     return MatchOperand_ParseFail;
4618   }
4619   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4620   if (!CE) {
4621     Error(ExLoc, "rotate amount must be an immediate");
4622     return MatchOperand_ParseFail;
4623   }
4624 
4625   int64_t Val = CE->getValue();
4626   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4627   // normally, zero is represented in asm by omitting the rotate operand
4628   // entirely.
4629   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4630     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4631     return MatchOperand_ParseFail;
4632   }
4633 
4634   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4635 
4636   return MatchOperand_Success;
4637 }
4638 
4639 OperandMatchResultTy
4640 ARMAsmParser::parseModImm(OperandVector &Operands) {
4641   MCAsmParser &Parser = getParser();
4642   MCAsmLexer &Lexer = getLexer();
4643   int64_t Imm1, Imm2;
4644 
4645   SMLoc S = Parser.getTok().getLoc();
4646 
4647   // 1) A mod_imm operand can appear in the place of a register name:
4648   //   add r0, #mod_imm
4649   //   add r0, r0, #mod_imm
4650   // to correctly handle the latter, we bail out as soon as we see an
4651   // identifier.
4652   //
4653   // 2) Similarly, we do not want to parse into complex operands:
4654   //   mov r0, #mod_imm
4655   //   mov r0, :lower16:(_foo)
4656   if (Parser.getTok().is(AsmToken::Identifier) ||
4657       Parser.getTok().is(AsmToken::Colon))
4658     return MatchOperand_NoMatch;
4659 
4660   // Hash (dollar) is optional as per the ARMARM
4661   if (Parser.getTok().is(AsmToken::Hash) ||
4662       Parser.getTok().is(AsmToken::Dollar)) {
4663     // Avoid parsing into complex operands (#:)
4664     if (Lexer.peekTok().is(AsmToken::Colon))
4665       return MatchOperand_NoMatch;
4666 
4667     // Eat the hash (dollar)
4668     Parser.Lex();
4669   }
4670 
4671   SMLoc Sx1, Ex1;
4672   Sx1 = Parser.getTok().getLoc();
4673   const MCExpr *Imm1Exp;
4674   if (getParser().parseExpression(Imm1Exp, Ex1)) {
4675     Error(Sx1, "malformed expression");
4676     return MatchOperand_ParseFail;
4677   }
4678 
4679   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4680 
4681   if (CE) {
4682     // Immediate must fit within 32-bits
4683     Imm1 = CE->getValue();
4684     int Enc = ARM_AM::getSOImmVal(Imm1);
4685     if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4686       // We have a match!
4687       Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4688                                                   (Enc & 0xF00) >> 7,
4689                                                   Sx1, Ex1));
4690       return MatchOperand_Success;
4691     }
4692 
4693     // We have parsed an immediate which is not for us, fallback to a plain
4694     // immediate. This can happen for instruction aliases. For an example,
4695     // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4696     // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4697     // instruction with a mod_imm operand. The alias is defined such that the
4698     // parser method is shared, that's why we have to do this here.
4699     if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4700       Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4701       return MatchOperand_Success;
4702     }
4703   } else {
4704     // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4705     // MCFixup). Fallback to a plain immediate.
4706     Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4707     return MatchOperand_Success;
4708   }
4709 
4710   // From this point onward, we expect the input to be a (#bits, #rot) pair
4711   if (Parser.getTok().isNot(AsmToken::Comma)) {
4712     Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4713     return MatchOperand_ParseFail;
4714   }
4715 
4716   if (Imm1 & ~0xFF) {
4717     Error(Sx1, "immediate operand must a number in the range [0, 255]");
4718     return MatchOperand_ParseFail;
4719   }
4720 
4721   // Eat the comma
4722   Parser.Lex();
4723 
4724   // Repeat for #rot
4725   SMLoc Sx2, Ex2;
4726   Sx2 = Parser.getTok().getLoc();
4727 
4728   // Eat the optional hash (dollar)
4729   if (Parser.getTok().is(AsmToken::Hash) ||
4730       Parser.getTok().is(AsmToken::Dollar))
4731     Parser.Lex();
4732 
4733   const MCExpr *Imm2Exp;
4734   if (getParser().parseExpression(Imm2Exp, Ex2)) {
4735     Error(Sx2, "malformed expression");
4736     return MatchOperand_ParseFail;
4737   }
4738 
4739   CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4740 
4741   if (CE) {
4742     Imm2 = CE->getValue();
4743     if (!(Imm2 & ~0x1E)) {
4744       // We have a match!
4745       Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4746       return MatchOperand_Success;
4747     }
4748     Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4749     return MatchOperand_ParseFail;
4750   } else {
4751     Error(Sx2, "constant expression expected");
4752     return MatchOperand_ParseFail;
4753   }
4754 }
4755 
4756 OperandMatchResultTy
4757 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4758   MCAsmParser &Parser = getParser();
4759   SMLoc S = Parser.getTok().getLoc();
4760   // The bitfield descriptor is really two operands, the LSB and the width.
4761   if (Parser.getTok().isNot(AsmToken::Hash) &&
4762       Parser.getTok().isNot(AsmToken::Dollar)) {
4763     Error(Parser.getTok().getLoc(), "'#' expected");
4764     return MatchOperand_ParseFail;
4765   }
4766   Parser.Lex(); // Eat hash token.
4767 
4768   const MCExpr *LSBExpr;
4769   SMLoc E = Parser.getTok().getLoc();
4770   if (getParser().parseExpression(LSBExpr)) {
4771     Error(E, "malformed immediate expression");
4772     return MatchOperand_ParseFail;
4773   }
4774   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4775   if (!CE) {
4776     Error(E, "'lsb' operand must be an immediate");
4777     return MatchOperand_ParseFail;
4778   }
4779 
4780   int64_t LSB = CE->getValue();
4781   // The LSB must be in the range [0,31]
4782   if (LSB < 0 || LSB > 31) {
4783     Error(E, "'lsb' operand must be in the range [0,31]");
4784     return MatchOperand_ParseFail;
4785   }
4786   E = Parser.getTok().getLoc();
4787 
4788   // Expect another immediate operand.
4789   if (Parser.getTok().isNot(AsmToken::Comma)) {
4790     Error(Parser.getTok().getLoc(), "too few operands");
4791     return MatchOperand_ParseFail;
4792   }
4793   Parser.Lex(); // Eat hash token.
4794   if (Parser.getTok().isNot(AsmToken::Hash) &&
4795       Parser.getTok().isNot(AsmToken::Dollar)) {
4796     Error(Parser.getTok().getLoc(), "'#' expected");
4797     return MatchOperand_ParseFail;
4798   }
4799   Parser.Lex(); // Eat hash token.
4800 
4801   const MCExpr *WidthExpr;
4802   SMLoc EndLoc;
4803   if (getParser().parseExpression(WidthExpr, EndLoc)) {
4804     Error(E, "malformed immediate expression");
4805     return MatchOperand_ParseFail;
4806   }
4807   CE = dyn_cast<MCConstantExpr>(WidthExpr);
4808   if (!CE) {
4809     Error(E, "'width' operand must be an immediate");
4810     return MatchOperand_ParseFail;
4811   }
4812 
4813   int64_t Width = CE->getValue();
4814   // The LSB must be in the range [1,32-lsb]
4815   if (Width < 1 || Width > 32 - LSB) {
4816     Error(E, "'width' operand must be in the range [1,32-lsb]");
4817     return MatchOperand_ParseFail;
4818   }
4819 
4820   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4821 
4822   return MatchOperand_Success;
4823 }
4824 
4825 OperandMatchResultTy
4826 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4827   // Check for a post-index addressing register operand. Specifically:
4828   // postidx_reg := '+' register {, shift}
4829   //              | '-' register {, shift}
4830   //              | register {, shift}
4831 
4832   // This method must return MatchOperand_NoMatch without consuming any tokens
4833   // in the case where there is no match, as other alternatives take other
4834   // parse methods.
4835   MCAsmParser &Parser = getParser();
4836   AsmToken Tok = Parser.getTok();
4837   SMLoc S = Tok.getLoc();
4838   bool haveEaten = false;
4839   bool isAdd = true;
4840   if (Tok.is(AsmToken::Plus)) {
4841     Parser.Lex(); // Eat the '+' token.
4842     haveEaten = true;
4843   } else if (Tok.is(AsmToken::Minus)) {
4844     Parser.Lex(); // Eat the '-' token.
4845     isAdd = false;
4846     haveEaten = true;
4847   }
4848 
4849   SMLoc E = Parser.getTok().getEndLoc();
4850   int Reg = tryParseRegister();
4851   if (Reg == -1) {
4852     if (!haveEaten)
4853       return MatchOperand_NoMatch;
4854     Error(Parser.getTok().getLoc(), "register expected");
4855     return MatchOperand_ParseFail;
4856   }
4857 
4858   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4859   unsigned ShiftImm = 0;
4860   if (Parser.getTok().is(AsmToken::Comma)) {
4861     Parser.Lex(); // Eat the ','.
4862     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4863       return MatchOperand_ParseFail;
4864 
4865     // FIXME: Only approximates end...may include intervening whitespace.
4866     E = Parser.getTok().getLoc();
4867   }
4868 
4869   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4870                                                   ShiftImm, S, E));
4871 
4872   return MatchOperand_Success;
4873 }
4874 
4875 OperandMatchResultTy
4876 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4877   // Check for a post-index addressing register operand. Specifically:
4878   // am3offset := '+' register
4879   //              | '-' register
4880   //              | register
4881   //              | # imm
4882   //              | # + imm
4883   //              | # - imm
4884 
4885   // This method must return MatchOperand_NoMatch without consuming any tokens
4886   // in the case where there is no match, as other alternatives take other
4887   // parse methods.
4888   MCAsmParser &Parser = getParser();
4889   AsmToken Tok = Parser.getTok();
4890   SMLoc S = Tok.getLoc();
4891 
4892   // Do immediates first, as we always parse those if we have a '#'.
4893   if (Parser.getTok().is(AsmToken::Hash) ||
4894       Parser.getTok().is(AsmToken::Dollar)) {
4895     Parser.Lex(); // Eat '#' or '$'.
4896     // Explicitly look for a '-', as we need to encode negative zero
4897     // differently.
4898     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4899     const MCExpr *Offset;
4900     SMLoc E;
4901     if (getParser().parseExpression(Offset, E))
4902       return MatchOperand_ParseFail;
4903     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4904     if (!CE) {
4905       Error(S, "constant expression expected");
4906       return MatchOperand_ParseFail;
4907     }
4908     // Negative zero is encoded as the flag value INT32_MIN.
4909     int32_t Val = CE->getValue();
4910     if (isNegative && Val == 0)
4911       Val = INT32_MIN;
4912 
4913     Operands.push_back(
4914       ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4915 
4916     return MatchOperand_Success;
4917   }
4918 
4919 
4920   bool haveEaten = false;
4921   bool isAdd = true;
4922   if (Tok.is(AsmToken::Plus)) {
4923     Parser.Lex(); // Eat the '+' token.
4924     haveEaten = true;
4925   } else if (Tok.is(AsmToken::Minus)) {
4926     Parser.Lex(); // Eat the '-' token.
4927     isAdd = false;
4928     haveEaten = true;
4929   }
4930 
4931   Tok = Parser.getTok();
4932   int Reg = tryParseRegister();
4933   if (Reg == -1) {
4934     if (!haveEaten)
4935       return MatchOperand_NoMatch;
4936     Error(Tok.getLoc(), "register expected");
4937     return MatchOperand_ParseFail;
4938   }
4939 
4940   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4941                                                   0, S, Tok.getEndLoc()));
4942 
4943   return MatchOperand_Success;
4944 }
4945 
4946 /// Convert parsed operands to MCInst.  Needed here because this instruction
4947 /// only has two register operands, but multiplication is commutative so
4948 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4949 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4950                                     const OperandVector &Operands) {
4951   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4952   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4953   // If we have a three-operand form, make sure to set Rn to be the operand
4954   // that isn't the same as Rd.
4955   unsigned RegOp = 4;
4956   if (Operands.size() == 6 &&
4957       ((ARMOperand &)*Operands[4]).getReg() ==
4958           ((ARMOperand &)*Operands[3]).getReg())
4959     RegOp = 5;
4960   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4961   Inst.addOperand(Inst.getOperand(0));
4962   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4963 }
4964 
4965 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4966                                     const OperandVector &Operands) {
4967   int CondOp = -1, ImmOp = -1;
4968   switch(Inst.getOpcode()) {
4969     case ARM::tB:
4970     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4971 
4972     case ARM::t2B:
4973     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4974 
4975     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4976   }
4977   // first decide whether or not the branch should be conditional
4978   // by looking at it's location relative to an IT block
4979   if(inITBlock()) {
4980     // inside an IT block we cannot have any conditional branches. any
4981     // such instructions needs to be converted to unconditional form
4982     switch(Inst.getOpcode()) {
4983       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4984       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4985     }
4986   } else {
4987     // outside IT blocks we can only have unconditional branches with AL
4988     // condition code or conditional branches with non-AL condition code
4989     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4990     switch(Inst.getOpcode()) {
4991       case ARM::tB:
4992       case ARM::tBcc:
4993         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4994         break;
4995       case ARM::t2B:
4996       case ARM::t2Bcc:
4997         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4998         break;
4999     }
5000   }
5001 
5002   // now decide on encoding size based on branch target range
5003   switch(Inst.getOpcode()) {
5004     // classify tB as either t2B or t1B based on range of immediate operand
5005     case ARM::tB: {
5006       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5007       if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
5008         Inst.setOpcode(ARM::t2B);
5009       break;
5010     }
5011     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
5012     case ARM::tBcc: {
5013       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5014       if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
5015         Inst.setOpcode(ARM::t2Bcc);
5016       break;
5017     }
5018   }
5019   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
5020   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5021 }
5022 
5023 /// Parse an ARM memory expression, return false if successful else return true
5024 /// or an error.  The first token must be a '[' when called.
5025 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5026   MCAsmParser &Parser = getParser();
5027   SMLoc S, E;
5028   if (Parser.getTok().isNot(AsmToken::LBrac))
5029     return TokError("Token is not a Left Bracket");
5030   S = Parser.getTok().getLoc();
5031   Parser.Lex(); // Eat left bracket token.
5032 
5033   const AsmToken &BaseRegTok = Parser.getTok();
5034   int BaseRegNum = tryParseRegister();
5035   if (BaseRegNum == -1)
5036     return Error(BaseRegTok.getLoc(), "register expected");
5037 
5038   // The next token must either be a comma, a colon or a closing bracket.
5039   const AsmToken &Tok = Parser.getTok();
5040   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5041       !Tok.is(AsmToken::RBrac))
5042     return Error(Tok.getLoc(), "malformed memory operand");
5043 
5044   if (Tok.is(AsmToken::RBrac)) {
5045     E = Tok.getEndLoc();
5046     Parser.Lex(); // Eat right bracket token.
5047 
5048     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5049                                              ARM_AM::no_shift, 0, 0, false,
5050                                              S, E));
5051 
5052     // If there's a pre-indexing writeback marker, '!', just add it as a token
5053     // operand. It's rather odd, but syntactically valid.
5054     if (Parser.getTok().is(AsmToken::Exclaim)) {
5055       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5056       Parser.Lex(); // Eat the '!'.
5057     }
5058 
5059     return false;
5060   }
5061 
5062   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
5063          "Lost colon or comma in memory operand?!");
5064   if (Tok.is(AsmToken::Comma)) {
5065     Parser.Lex(); // Eat the comma.
5066   }
5067 
5068   // If we have a ':', it's an alignment specifier.
5069   if (Parser.getTok().is(AsmToken::Colon)) {
5070     Parser.Lex(); // Eat the ':'.
5071     E = Parser.getTok().getLoc();
5072     SMLoc AlignmentLoc = Tok.getLoc();
5073 
5074     const MCExpr *Expr;
5075     if (getParser().parseExpression(Expr))
5076      return true;
5077 
5078     // The expression has to be a constant. Memory references with relocations
5079     // don't come through here, as they use the <label> forms of the relevant
5080     // instructions.
5081     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5082     if (!CE)
5083       return Error (E, "constant expression expected");
5084 
5085     unsigned Align = 0;
5086     switch (CE->getValue()) {
5087     default:
5088       return Error(E,
5089                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5090     case 16:  Align = 2; break;
5091     case 32:  Align = 4; break;
5092     case 64:  Align = 8; break;
5093     case 128: Align = 16; break;
5094     case 256: Align = 32; break;
5095     }
5096 
5097     // Now we should have the closing ']'
5098     if (Parser.getTok().isNot(AsmToken::RBrac))
5099       return Error(Parser.getTok().getLoc(), "']' expected");
5100     E = Parser.getTok().getEndLoc();
5101     Parser.Lex(); // Eat right bracket token.
5102 
5103     // Don't worry about range checking the value here. That's handled by
5104     // the is*() predicates.
5105     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5106                                              ARM_AM::no_shift, 0, Align,
5107                                              false, S, E, AlignmentLoc));
5108 
5109     // If there's a pre-indexing writeback marker, '!', just add it as a token
5110     // operand.
5111     if (Parser.getTok().is(AsmToken::Exclaim)) {
5112       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5113       Parser.Lex(); // Eat the '!'.
5114     }
5115 
5116     return false;
5117   }
5118 
5119   // If we have a '#', it's an immediate offset, else assume it's a register
5120   // offset. Be friendly and also accept a plain integer (without a leading
5121   // hash) for gas compatibility.
5122   if (Parser.getTok().is(AsmToken::Hash) ||
5123       Parser.getTok().is(AsmToken::Dollar) ||
5124       Parser.getTok().is(AsmToken::Integer)) {
5125     if (Parser.getTok().isNot(AsmToken::Integer))
5126       Parser.Lex(); // Eat '#' or '$'.
5127     E = Parser.getTok().getLoc();
5128 
5129     bool isNegative = getParser().getTok().is(AsmToken::Minus);
5130     const MCExpr *Offset;
5131     if (getParser().parseExpression(Offset))
5132      return true;
5133 
5134     // The expression has to be a constant. Memory references with relocations
5135     // don't come through here, as they use the <label> forms of the relevant
5136     // instructions.
5137     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5138     if (!CE)
5139       return Error (E, "constant expression expected");
5140 
5141     // If the constant was #-0, represent it as INT32_MIN.
5142     int32_t Val = CE->getValue();
5143     if (isNegative && Val == 0)
5144       CE = MCConstantExpr::create(INT32_MIN, getContext());
5145 
5146     // Now we should have the closing ']'
5147     if (Parser.getTok().isNot(AsmToken::RBrac))
5148       return Error(Parser.getTok().getLoc(), "']' expected");
5149     E = Parser.getTok().getEndLoc();
5150     Parser.Lex(); // Eat right bracket token.
5151 
5152     // Don't worry about range checking the value here. That's handled by
5153     // the is*() predicates.
5154     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
5155                                              ARM_AM::no_shift, 0, 0,
5156                                              false, S, E));
5157 
5158     // If there's a pre-indexing writeback marker, '!', just add it as a token
5159     // operand.
5160     if (Parser.getTok().is(AsmToken::Exclaim)) {
5161       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5162       Parser.Lex(); // Eat the '!'.
5163     }
5164 
5165     return false;
5166   }
5167 
5168   // The register offset is optionally preceded by a '+' or '-'
5169   bool isNegative = false;
5170   if (Parser.getTok().is(AsmToken::Minus)) {
5171     isNegative = true;
5172     Parser.Lex(); // Eat the '-'.
5173   } else if (Parser.getTok().is(AsmToken::Plus)) {
5174     // Nothing to do.
5175     Parser.Lex(); // Eat the '+'.
5176   }
5177 
5178   E = Parser.getTok().getLoc();
5179   int OffsetRegNum = tryParseRegister();
5180   if (OffsetRegNum == -1)
5181     return Error(E, "register expected");
5182 
5183   // If there's a shift operator, handle it.
5184   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5185   unsigned ShiftImm = 0;
5186   if (Parser.getTok().is(AsmToken::Comma)) {
5187     Parser.Lex(); // Eat the ','.
5188     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5189       return true;
5190   }
5191 
5192   // Now we should have the closing ']'
5193   if (Parser.getTok().isNot(AsmToken::RBrac))
5194     return Error(Parser.getTok().getLoc(), "']' expected");
5195   E = Parser.getTok().getEndLoc();
5196   Parser.Lex(); // Eat right bracket token.
5197 
5198   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
5199                                            ShiftType, ShiftImm, 0, isNegative,
5200                                            S, E));
5201 
5202   // If there's a pre-indexing writeback marker, '!', just add it as a token
5203   // operand.
5204   if (Parser.getTok().is(AsmToken::Exclaim)) {
5205     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5206     Parser.Lex(); // Eat the '!'.
5207   }
5208 
5209   return false;
5210 }
5211 
5212 /// parseMemRegOffsetShift - one of these two:
5213 ///   ( lsl | lsr | asr | ror ) , # shift_amount
5214 ///   rrx
5215 /// return true if it parses a shift otherwise it returns false.
5216 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5217                                           unsigned &Amount) {
5218   MCAsmParser &Parser = getParser();
5219   SMLoc Loc = Parser.getTok().getLoc();
5220   const AsmToken &Tok = Parser.getTok();
5221   if (Tok.isNot(AsmToken::Identifier))
5222     return true;
5223   StringRef ShiftName = Tok.getString();
5224   if (ShiftName == "lsl" || ShiftName == "LSL" ||
5225       ShiftName == "asl" || ShiftName == "ASL")
5226     St = ARM_AM::lsl;
5227   else if (ShiftName == "lsr" || ShiftName == "LSR")
5228     St = ARM_AM::lsr;
5229   else if (ShiftName == "asr" || ShiftName == "ASR")
5230     St = ARM_AM::asr;
5231   else if (ShiftName == "ror" || ShiftName == "ROR")
5232     St = ARM_AM::ror;
5233   else if (ShiftName == "rrx" || ShiftName == "RRX")
5234     St = ARM_AM::rrx;
5235   else
5236     return Error(Loc, "illegal shift operator");
5237   Parser.Lex(); // Eat shift type token.
5238 
5239   // rrx stands alone.
5240   Amount = 0;
5241   if (St != ARM_AM::rrx) {
5242     Loc = Parser.getTok().getLoc();
5243     // A '#' and a shift amount.
5244     const AsmToken &HashTok = Parser.getTok();
5245     if (HashTok.isNot(AsmToken::Hash) &&
5246         HashTok.isNot(AsmToken::Dollar))
5247       return Error(HashTok.getLoc(), "'#' expected");
5248     Parser.Lex(); // Eat hash token.
5249 
5250     const MCExpr *Expr;
5251     if (getParser().parseExpression(Expr))
5252       return true;
5253     // Range check the immediate.
5254     // lsl, ror: 0 <= imm <= 31
5255     // lsr, asr: 0 <= imm <= 32
5256     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5257     if (!CE)
5258       return Error(Loc, "shift amount must be an immediate");
5259     int64_t Imm = CE->getValue();
5260     if (Imm < 0 ||
5261         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5262         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5263       return Error(Loc, "immediate shift value out of range");
5264     // If <ShiftTy> #0, turn it into a no_shift.
5265     if (Imm == 0)
5266       St = ARM_AM::lsl;
5267     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5268     if (Imm == 32)
5269       Imm = 0;
5270     Amount = Imm;
5271   }
5272 
5273   return false;
5274 }
5275 
5276 /// parseFPImm - A floating point immediate expression operand.
5277 OperandMatchResultTy
5278 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5279   MCAsmParser &Parser = getParser();
5280   // Anything that can accept a floating point constant as an operand
5281   // needs to go through here, as the regular parseExpression is
5282   // integer only.
5283   //
5284   // This routine still creates a generic Immediate operand, containing
5285   // a bitcast of the 64-bit floating point value. The various operands
5286   // that accept floats can check whether the value is valid for them
5287   // via the standard is*() predicates.
5288 
5289   SMLoc S = Parser.getTok().getLoc();
5290 
5291   if (Parser.getTok().isNot(AsmToken::Hash) &&
5292       Parser.getTok().isNot(AsmToken::Dollar))
5293     return MatchOperand_NoMatch;
5294 
5295   // Disambiguate the VMOV forms that can accept an FP immediate.
5296   // vmov.f32 <sreg>, #imm
5297   // vmov.f64 <dreg>, #imm
5298   // vmov.f32 <dreg>, #imm  @ vector f32x2
5299   // vmov.f32 <qreg>, #imm  @ vector f32x4
5300   //
5301   // There are also the NEON VMOV instructions which expect an
5302   // integer constant. Make sure we don't try to parse an FPImm
5303   // for these:
5304   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5305   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5306   bool isVmovf = TyOp.isToken() &&
5307                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5308                   TyOp.getToken() == ".f16");
5309   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5310   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5311                                          Mnemonic.getToken() == "fconsts");
5312   if (!(isVmovf || isFconst))
5313     return MatchOperand_NoMatch;
5314 
5315   Parser.Lex(); // Eat '#' or '$'.
5316 
5317   // Handle negation, as that still comes through as a separate token.
5318   bool isNegative = false;
5319   if (Parser.getTok().is(AsmToken::Minus)) {
5320     isNegative = true;
5321     Parser.Lex();
5322   }
5323   const AsmToken &Tok = Parser.getTok();
5324   SMLoc Loc = Tok.getLoc();
5325   if (Tok.is(AsmToken::Real) && isVmovf) {
5326     APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
5327     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5328     // If we had a '-' in front, toggle the sign bit.
5329     IntVal ^= (uint64_t)isNegative << 31;
5330     Parser.Lex(); // Eat the token.
5331     Operands.push_back(ARMOperand::CreateImm(
5332           MCConstantExpr::create(IntVal, getContext()),
5333           S, Parser.getTok().getLoc()));
5334     return MatchOperand_Success;
5335   }
5336   // Also handle plain integers. Instructions which allow floating point
5337   // immediates also allow a raw encoded 8-bit value.
5338   if (Tok.is(AsmToken::Integer) && isFconst) {
5339     int64_t Val = Tok.getIntVal();
5340     Parser.Lex(); // Eat the token.
5341     if (Val > 255 || Val < 0) {
5342       Error(Loc, "encoded floating point value out of range");
5343       return MatchOperand_ParseFail;
5344     }
5345     float RealVal = ARM_AM::getFPImmFloat(Val);
5346     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5347 
5348     Operands.push_back(ARMOperand::CreateImm(
5349         MCConstantExpr::create(Val, getContext()), S,
5350         Parser.getTok().getLoc()));
5351     return MatchOperand_Success;
5352   }
5353 
5354   Error(Loc, "invalid floating point immediate");
5355   return MatchOperand_ParseFail;
5356 }
5357 
5358 /// Parse a arm instruction operand.  For now this parses the operand regardless
5359 /// of the mnemonic.
5360 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5361   MCAsmParser &Parser = getParser();
5362   SMLoc S, E;
5363 
5364   // Check if the current operand has a custom associated parser, if so, try to
5365   // custom parse the operand, or fallback to the general approach.
5366   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5367   if (ResTy == MatchOperand_Success)
5368     return false;
5369   // If there wasn't a custom match, try the generic matcher below. Otherwise,
5370   // there was a match, but an error occurred, in which case, just return that
5371   // the operand parsing failed.
5372   if (ResTy == MatchOperand_ParseFail)
5373     return true;
5374 
5375   switch (getLexer().getKind()) {
5376   default:
5377     Error(Parser.getTok().getLoc(), "unexpected token in operand");
5378     return true;
5379   case AsmToken::Identifier: {
5380     // If we've seen a branch mnemonic, the next operand must be a label.  This
5381     // is true even if the label is a register name.  So "br r1" means branch to
5382     // label "r1".
5383     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5384     if (!ExpectLabel) {
5385       if (!tryParseRegisterWithWriteBack(Operands))
5386         return false;
5387       int Res = tryParseShiftRegister(Operands);
5388       if (Res == 0) // success
5389         return false;
5390       else if (Res == -1) // irrecoverable error
5391         return true;
5392       // If this is VMRS, check for the apsr_nzcv operand.
5393       if (Mnemonic == "vmrs" &&
5394           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5395         S = Parser.getTok().getLoc();
5396         Parser.Lex();
5397         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5398         return false;
5399       }
5400     }
5401 
5402     // Fall though for the Identifier case that is not a register or a
5403     // special name.
5404   }
5405   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
5406   case AsmToken::Integer: // things like 1f and 2b as a branch targets
5407   case AsmToken::String:  // quoted label names.
5408   case AsmToken::Dot: {   // . as a branch target
5409     // This was not a register so parse other operands that start with an
5410     // identifier (like labels) as expressions and create them as immediates.
5411     const MCExpr *IdVal;
5412     S = Parser.getTok().getLoc();
5413     if (getParser().parseExpression(IdVal))
5414       return true;
5415     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5416     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5417     return false;
5418   }
5419   case AsmToken::LBrac:
5420     return parseMemory(Operands);
5421   case AsmToken::LCurly:
5422     return parseRegisterList(Operands);
5423   case AsmToken::Dollar:
5424   case AsmToken::Hash: {
5425     // #42 -> immediate.
5426     S = Parser.getTok().getLoc();
5427     Parser.Lex();
5428 
5429     if (Parser.getTok().isNot(AsmToken::Colon)) {
5430       bool isNegative = Parser.getTok().is(AsmToken::Minus);
5431       const MCExpr *ImmVal;
5432       if (getParser().parseExpression(ImmVal))
5433         return true;
5434       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5435       if (CE) {
5436         int32_t Val = CE->getValue();
5437         if (isNegative && Val == 0)
5438           ImmVal = MCConstantExpr::create(INT32_MIN, getContext());
5439       }
5440       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5441       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5442 
5443       // There can be a trailing '!' on operands that we want as a separate
5444       // '!' Token operand. Handle that here. For example, the compatibility
5445       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5446       if (Parser.getTok().is(AsmToken::Exclaim)) {
5447         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5448                                                    Parser.getTok().getLoc()));
5449         Parser.Lex(); // Eat exclaim token
5450       }
5451       return false;
5452     }
5453     // w/ a ':' after the '#', it's just like a plain ':'.
5454     LLVM_FALLTHROUGH;
5455   }
5456   case AsmToken::Colon: {
5457     S = Parser.getTok().getLoc();
5458     // ":lower16:" and ":upper16:" expression prefixes
5459     // FIXME: Check it's an expression prefix,
5460     // e.g. (FOO - :lower16:BAR) isn't legal.
5461     ARMMCExpr::VariantKind RefKind;
5462     if (parsePrefix(RefKind))
5463       return true;
5464 
5465     const MCExpr *SubExprVal;
5466     if (getParser().parseExpression(SubExprVal))
5467       return true;
5468 
5469     const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
5470                                               getContext());
5471     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5472     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5473     return false;
5474   }
5475   case AsmToken::Equal: {
5476     S = Parser.getTok().getLoc();
5477     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5478       return Error(S, "unexpected token in operand");
5479     Parser.Lex(); // Eat '='
5480     const MCExpr *SubExprVal;
5481     if (getParser().parseExpression(SubExprVal))
5482       return true;
5483     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5484 
5485     // execute-only: we assume that assembly programmers know what they are
5486     // doing and allow literal pool creation here
5487     Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
5488     return false;
5489   }
5490   }
5491 }
5492 
5493 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5494 //  :lower16: and :upper16:.
5495 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5496   MCAsmParser &Parser = getParser();
5497   RefKind = ARMMCExpr::VK_ARM_None;
5498 
5499   // consume an optional '#' (GNU compatibility)
5500   if (getLexer().is(AsmToken::Hash))
5501     Parser.Lex();
5502 
5503   // :lower16: and :upper16: modifiers
5504   assert(getLexer().is(AsmToken::Colon) && "expected a :");
5505   Parser.Lex(); // Eat ':'
5506 
5507   if (getLexer().isNot(AsmToken::Identifier)) {
5508     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5509     return true;
5510   }
5511 
5512   enum {
5513     COFF = (1 << MCObjectFileInfo::IsCOFF),
5514     ELF = (1 << MCObjectFileInfo::IsELF),
5515     MACHO = (1 << MCObjectFileInfo::IsMachO),
5516     WASM = (1 << MCObjectFileInfo::IsWasm),
5517   };
5518   static const struct PrefixEntry {
5519     const char *Spelling;
5520     ARMMCExpr::VariantKind VariantKind;
5521     uint8_t SupportedFormats;
5522   } PrefixEntries[] = {
5523     { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5524     { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5525   };
5526 
5527   StringRef IDVal = Parser.getTok().getIdentifier();
5528 
5529   const auto &Prefix =
5530       std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5531                    [&IDVal](const PrefixEntry &PE) {
5532                       return PE.Spelling == IDVal;
5533                    });
5534   if (Prefix == std::end(PrefixEntries)) {
5535     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5536     return true;
5537   }
5538 
5539   uint8_t CurrentFormat;
5540   switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5541   case MCObjectFileInfo::IsMachO:
5542     CurrentFormat = MACHO;
5543     break;
5544   case MCObjectFileInfo::IsELF:
5545     CurrentFormat = ELF;
5546     break;
5547   case MCObjectFileInfo::IsCOFF:
5548     CurrentFormat = COFF;
5549     break;
5550   case MCObjectFileInfo::IsWasm:
5551     CurrentFormat = WASM;
5552     break;
5553   }
5554 
5555   if (~Prefix->SupportedFormats & CurrentFormat) {
5556     Error(Parser.getTok().getLoc(),
5557           "cannot represent relocation in the current file format");
5558     return true;
5559   }
5560 
5561   RefKind = Prefix->VariantKind;
5562   Parser.Lex();
5563 
5564   if (getLexer().isNot(AsmToken::Colon)) {
5565     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5566     return true;
5567   }
5568   Parser.Lex(); // Eat the last ':'
5569 
5570   return false;
5571 }
5572 
5573 /// \brief Given a mnemonic, split out possible predication code and carry
5574 /// setting letters to form a canonical mnemonic and flags.
5575 //
5576 // FIXME: Would be nice to autogen this.
5577 // FIXME: This is a bit of a maze of special cases.
5578 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5579                                       unsigned &PredicationCode,
5580                                       bool &CarrySetting,
5581                                       unsigned &ProcessorIMod,
5582                                       StringRef &ITMask) {
5583   PredicationCode = ARMCC::AL;
5584   CarrySetting = false;
5585   ProcessorIMod = 0;
5586 
5587   // Ignore some mnemonics we know aren't predicated forms.
5588   //
5589   // FIXME: Would be nice to autogen this.
5590   if ((Mnemonic == "movs" && isThumb()) ||
5591       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
5592       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
5593       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
5594       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
5595       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
5596       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
5597       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
5598       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5599       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5600       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
5601       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5602       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5603       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
5604       Mnemonic == "bxns"  || Mnemonic == "blxns")
5605     return Mnemonic;
5606 
5607   // First, split out any predication code. Ignore mnemonics we know aren't
5608   // predicated but do have a carry-set and so weren't caught above.
5609   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5610       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5611       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5612       Mnemonic != "sbcs" && Mnemonic != "rscs") {
5613     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5614       .Case("eq", ARMCC::EQ)
5615       .Case("ne", ARMCC::NE)
5616       .Case("hs", ARMCC::HS)
5617       .Case("cs", ARMCC::HS)
5618       .Case("lo", ARMCC::LO)
5619       .Case("cc", ARMCC::LO)
5620       .Case("mi", ARMCC::MI)
5621       .Case("pl", ARMCC::PL)
5622       .Case("vs", ARMCC::VS)
5623       .Case("vc", ARMCC::VC)
5624       .Case("hi", ARMCC::HI)
5625       .Case("ls", ARMCC::LS)
5626       .Case("ge", ARMCC::GE)
5627       .Case("lt", ARMCC::LT)
5628       .Case("gt", ARMCC::GT)
5629       .Case("le", ARMCC::LE)
5630       .Case("al", ARMCC::AL)
5631       .Default(~0U);
5632     if (CC != ~0U) {
5633       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5634       PredicationCode = CC;
5635     }
5636   }
5637 
5638   // Next, determine if we have a carry setting bit. We explicitly ignore all
5639   // the instructions we know end in 's'.
5640   if (Mnemonic.endswith("s") &&
5641       !(Mnemonic == "cps" || Mnemonic == "mls" ||
5642         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5643         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5644         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5645         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5646         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5647         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5648         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5649         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5650         Mnemonic == "bxns" || Mnemonic == "blxns" ||
5651         (Mnemonic == "movs" && isThumb()))) {
5652     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5653     CarrySetting = true;
5654   }
5655 
5656   // The "cps" instruction can have a interrupt mode operand which is glued into
5657   // the mnemonic. Check if this is the case, split it and parse the imod op
5658   if (Mnemonic.startswith("cps")) {
5659     // Split out any imod code.
5660     unsigned IMod =
5661       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5662       .Case("ie", ARM_PROC::IE)
5663       .Case("id", ARM_PROC::ID)
5664       .Default(~0U);
5665     if (IMod != ~0U) {
5666       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5667       ProcessorIMod = IMod;
5668     }
5669   }
5670 
5671   // The "it" instruction has the condition mask on the end of the mnemonic.
5672   if (Mnemonic.startswith("it")) {
5673     ITMask = Mnemonic.slice(2, Mnemonic.size());
5674     Mnemonic = Mnemonic.slice(0, 2);
5675   }
5676 
5677   return Mnemonic;
5678 }
5679 
5680 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5681 /// inclusion of carry set or predication code operands.
5682 //
5683 // FIXME: It would be nice to autogen this.
5684 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5685                                          bool &CanAcceptCarrySet,
5686                                          bool &CanAcceptPredicationCode) {
5687   CanAcceptCarrySet =
5688       Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5689       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5690       Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
5691       Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
5692       Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
5693       Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
5694       Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5695       (!isThumb() &&
5696        (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
5697         Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
5698 
5699   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5700       Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5701       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5702       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5703       Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
5704       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
5705       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
5706       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
5707       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
5708       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5709       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
5710       Mnemonic == "vmovx" || Mnemonic == "vins") {
5711     // These mnemonics are never predicable
5712     CanAcceptPredicationCode = false;
5713   } else if (!isThumb()) {
5714     // Some instructions are only predicable in Thumb mode
5715     CanAcceptPredicationCode =
5716         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5717         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5718         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5719         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5720         Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" &&
5721         Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") &&
5722         !Mnemonic.startswith("srs");
5723   } else if (isThumbOne()) {
5724     if (hasV6MOps())
5725       CanAcceptPredicationCode = Mnemonic != "movs";
5726     else
5727       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5728   } else
5729     CanAcceptPredicationCode = true;
5730 }
5731 
5732 // \brief Some Thumb instructions have two operand forms that are not
5733 // available as three operand, convert to two operand form if possible.
5734 //
5735 // FIXME: We would really like to be able to tablegen'erate this.
5736 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
5737                                                  bool CarrySetting,
5738                                                  OperandVector &Operands) {
5739   if (Operands.size() != 6)
5740     return;
5741 
5742   const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5743         auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5744   if (!Op3.isReg() || !Op4.isReg())
5745     return;
5746 
5747   auto Op3Reg = Op3.getReg();
5748   auto Op4Reg = Op4.getReg();
5749 
5750   // For most Thumb2 cases we just generate the 3 operand form and reduce
5751   // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
5752   // won't accept SP or PC so we do the transformation here taking care
5753   // with immediate range in the 'add sp, sp #imm' case.
5754   auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5755   if (isThumbTwo()) {
5756     if (Mnemonic != "add")
5757       return;
5758     bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
5759                         (Op5.isReg() && Op5.getReg() == ARM::PC);
5760     if (!TryTransform) {
5761       TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
5762                       (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
5763                      !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
5764                        Op5.isImm() && !Op5.isImm0_508s4());
5765     }
5766     if (!TryTransform)
5767       return;
5768   } else if (!isThumbOne())
5769     return;
5770 
5771   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5772         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5773         Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5774         Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
5775     return;
5776 
5777   // If first 2 operands of a 3 operand instruction are the same
5778   // then transform to 2 operand version of the same instruction
5779   // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5780   bool Transform = Op3Reg == Op4Reg;
5781 
5782   // For communtative operations, we might be able to transform if we swap
5783   // Op4 and Op5.  The 'ADD Rdm, SP, Rdm' form is already handled specially
5784   // as tADDrsp.
5785   const ARMOperand *LastOp = &Op5;
5786   bool Swap = false;
5787   if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
5788       ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
5789        Mnemonic == "and" || Mnemonic == "eor" ||
5790        Mnemonic == "adc" || Mnemonic == "orr")) {
5791     Swap = true;
5792     LastOp = &Op4;
5793     Transform = true;
5794   }
5795 
5796   // If both registers are the same then remove one of them from
5797   // the operand list, with certain exceptions.
5798   if (Transform) {
5799     // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
5800     // 2 operand forms don't exist.
5801     if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
5802         LastOp->isReg())
5803       Transform = false;
5804 
5805     // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
5806     // 3-bits because the ARMARM says not to.
5807     if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
5808       Transform = false;
5809   }
5810 
5811   if (Transform) {
5812     if (Swap)
5813       std::swap(Op4, Op5);
5814     Operands.erase(Operands.begin() + 3);
5815   }
5816 }
5817 
5818 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5819                                           OperandVector &Operands) {
5820   // FIXME: This is all horribly hacky. We really need a better way to deal
5821   // with optional operands like this in the matcher table.
5822 
5823   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5824   // another does not. Specifically, the MOVW instruction does not. So we
5825   // special case it here and remove the defaulted (non-setting) cc_out
5826   // operand if that's the instruction we're trying to match.
5827   //
5828   // We do this as post-processing of the explicit operands rather than just
5829   // conditionally adding the cc_out in the first place because we need
5830   // to check the type of the parsed immediate operand.
5831   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5832       !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5833       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5834       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5835     return true;
5836 
5837   // Register-register 'add' for thumb does not have a cc_out operand
5838   // when there are only two register operands.
5839   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5840       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5841       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5842       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5843     return true;
5844   // Register-register 'add' for thumb does not have a cc_out operand
5845   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5846   // have to check the immediate range here since Thumb2 has a variant
5847   // that can handle a different range and has a cc_out operand.
5848   if (((isThumb() && Mnemonic == "add") ||
5849        (isThumbTwo() && Mnemonic == "sub")) &&
5850       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5851       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5852       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5853       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5854       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5855        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5856     return true;
5857   // For Thumb2, add/sub immediate does not have a cc_out operand for the
5858   // imm0_4095 variant. That's the least-preferred variant when
5859   // selecting via the generic "add" mnemonic, so to know that we
5860   // should remove the cc_out operand, we have to explicitly check that
5861   // it's not one of the other variants. Ugh.
5862   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5863       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5864       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5865       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5866     // Nest conditions rather than one big 'if' statement for readability.
5867     //
5868     // If both registers are low, we're in an IT block, and the immediate is
5869     // in range, we should use encoding T1 instead, which has a cc_out.
5870     if (inITBlock() &&
5871         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5872         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5873         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5874       return false;
5875     // Check against T3. If the second register is the PC, this is an
5876     // alternate form of ADR, which uses encoding T4, so check for that too.
5877     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5878         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5879       return false;
5880 
5881     // Otherwise, we use encoding T4, which does not have a cc_out
5882     // operand.
5883     return true;
5884   }
5885 
5886   // The thumb2 multiply instruction doesn't have a CCOut register, so
5887   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5888   // use the 16-bit encoding or not.
5889   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5890       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5891       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5892       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5893       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5894       // If the registers aren't low regs, the destination reg isn't the
5895       // same as one of the source regs, or the cc_out operand is zero
5896       // outside of an IT block, we have to use the 32-bit encoding, so
5897       // remove the cc_out operand.
5898       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5899        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5900        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5901        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5902                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5903                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5904                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
5905     return true;
5906 
5907   // Also check the 'mul' syntax variant that doesn't specify an explicit
5908   // destination register.
5909   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5910       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5911       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5912       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5913       // If the registers aren't low regs  or the cc_out operand is zero
5914       // outside of an IT block, we have to use the 32-bit encoding, so
5915       // remove the cc_out operand.
5916       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5917        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5918        !inITBlock()))
5919     return true;
5920 
5921 
5922 
5923   // Register-register 'add/sub' for thumb does not have a cc_out operand
5924   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5925   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5926   // right, this will result in better diagnostics (which operand is off)
5927   // anyway.
5928   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5929       (Operands.size() == 5 || Operands.size() == 6) &&
5930       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5931       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5932       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5933       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5934        (Operands.size() == 6 &&
5935         static_cast<ARMOperand &>(*Operands[5]).isImm())))
5936     return true;
5937 
5938   return false;
5939 }
5940 
5941 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5942                                               OperandVector &Operands) {
5943   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5944   unsigned RegIdx = 3;
5945   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5946       (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
5947        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
5948     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5949         (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
5950          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
5951       RegIdx = 4;
5952 
5953     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5954         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5955              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5956          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5957              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5958       return true;
5959   }
5960   return false;
5961 }
5962 
5963 static bool isDataTypeToken(StringRef Tok) {
5964   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5965     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5966     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5967     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5968     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5969     Tok == ".f" || Tok == ".d";
5970 }
5971 
5972 // FIXME: This bit should probably be handled via an explicit match class
5973 // in the .td files that matches the suffix instead of having it be
5974 // a literal string token the way it is now.
5975 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5976   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5977 }
5978 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5979                                  unsigned VariantID);
5980 
5981 static bool RequiresVFPRegListValidation(StringRef Inst,
5982                                          bool &AcceptSinglePrecisionOnly,
5983                                          bool &AcceptDoublePrecisionOnly) {
5984   if (Inst.size() < 7)
5985     return false;
5986 
5987   if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5988     StringRef AddressingMode = Inst.substr(4, 2);
5989     if (AddressingMode == "ia" || AddressingMode == "db" ||
5990         AddressingMode == "ea" || AddressingMode == "fd") {
5991       AcceptSinglePrecisionOnly = Inst[6] == 's';
5992       AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5993       return true;
5994     }
5995   }
5996 
5997   return false;
5998 }
5999 
6000 /// Parse an arm instruction mnemonic followed by its operands.
6001 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
6002                                     SMLoc NameLoc, OperandVector &Operands) {
6003   MCAsmParser &Parser = getParser();
6004   // FIXME: Can this be done via tablegen in some fashion?
6005   bool RequireVFPRegisterListCheck;
6006   bool AcceptSinglePrecisionOnly;
6007   bool AcceptDoublePrecisionOnly;
6008   RequireVFPRegisterListCheck =
6009     RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
6010                                  AcceptDoublePrecisionOnly);
6011 
6012   // Apply mnemonic aliases before doing anything else, as the destination
6013   // mnemonic may include suffices and we want to handle them normally.
6014   // The generic tblgen'erated code does this later, at the start of
6015   // MatchInstructionImpl(), but that's too late for aliases that include
6016   // any sort of suffix.
6017   uint64_t AvailableFeatures = getAvailableFeatures();
6018   unsigned AssemblerDialect = getParser().getAssemblerDialect();
6019   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
6020 
6021   // First check for the ARM-specific .req directive.
6022   if (Parser.getTok().is(AsmToken::Identifier) &&
6023       Parser.getTok().getIdentifier() == ".req") {
6024     parseDirectiveReq(Name, NameLoc);
6025     // We always return 'error' for this, as we're done with this
6026     // statement and don't need to match the 'instruction."
6027     return true;
6028   }
6029 
6030   // Create the leading tokens for the mnemonic, split by '.' characters.
6031   size_t Start = 0, Next = Name.find('.');
6032   StringRef Mnemonic = Name.slice(Start, Next);
6033 
6034   // Split out the predication code and carry setting flag from the mnemonic.
6035   unsigned PredicationCode;
6036   unsigned ProcessorIMod;
6037   bool CarrySetting;
6038   StringRef ITMask;
6039   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
6040                            ProcessorIMod, ITMask);
6041 
6042   // In Thumb1, only the branch (B) instruction can be predicated.
6043   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
6044     return Error(NameLoc, "conditional execution not supported in Thumb1");
6045   }
6046 
6047   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
6048 
6049   // Handle the IT instruction ITMask. Convert it to a bitmask. This
6050   // is the mask as it will be for the IT encoding if the conditional
6051   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
6052   // where the conditional bit0 is zero, the instruction post-processing
6053   // will adjust the mask accordingly.
6054   if (Mnemonic == "it") {
6055     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
6056     if (ITMask.size() > 3) {
6057       return Error(Loc, "too many conditions on IT instruction");
6058     }
6059     unsigned Mask = 8;
6060     for (unsigned i = ITMask.size(); i != 0; --i) {
6061       char pos = ITMask[i - 1];
6062       if (pos != 't' && pos != 'e') {
6063         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
6064       }
6065       Mask >>= 1;
6066       if (ITMask[i - 1] == 't')
6067         Mask |= 8;
6068     }
6069     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
6070   }
6071 
6072   // FIXME: This is all a pretty gross hack. We should automatically handle
6073   // optional operands like this via tblgen.
6074 
6075   // Next, add the CCOut and ConditionCode operands, if needed.
6076   //
6077   // For mnemonics which can ever incorporate a carry setting bit or predication
6078   // code, our matching model involves us always generating CCOut and
6079   // ConditionCode operands to match the mnemonic "as written" and then we let
6080   // the matcher deal with finding the right instruction or generating an
6081   // appropriate error.
6082   bool CanAcceptCarrySet, CanAcceptPredicationCode;
6083   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
6084 
6085   // If we had a carry-set on an instruction that can't do that, issue an
6086   // error.
6087   if (!CanAcceptCarrySet && CarrySetting) {
6088     return Error(NameLoc, "instruction '" + Mnemonic +
6089                  "' can not set flags, but 's' suffix specified");
6090   }
6091   // If we had a predication code on an instruction that can't do that, issue an
6092   // error.
6093   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
6094     return Error(NameLoc, "instruction '" + Mnemonic +
6095                  "' is not predicable, but condition code specified");
6096   }
6097 
6098   // Add the carry setting operand, if necessary.
6099   if (CanAcceptCarrySet) {
6100     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
6101     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
6102                                                Loc));
6103   }
6104 
6105   // Add the predication code operand, if necessary.
6106   if (CanAcceptPredicationCode) {
6107     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
6108                                       CarrySetting);
6109     Operands.push_back(ARMOperand::CreateCondCode(
6110                          ARMCC::CondCodes(PredicationCode), Loc));
6111   }
6112 
6113   // Add the processor imod operand, if necessary.
6114   if (ProcessorIMod) {
6115     Operands.push_back(ARMOperand::CreateImm(
6116           MCConstantExpr::create(ProcessorIMod, getContext()),
6117                                  NameLoc, NameLoc));
6118   } else if (Mnemonic == "cps" && isMClass()) {
6119     return Error(NameLoc, "instruction 'cps' requires effect for M-class");
6120   }
6121 
6122   // Add the remaining tokens in the mnemonic.
6123   while (Next != StringRef::npos) {
6124     Start = Next;
6125     Next = Name.find('.', Start + 1);
6126     StringRef ExtraToken = Name.slice(Start, Next);
6127 
6128     // Some NEON instructions have an optional datatype suffix that is
6129     // completely ignored. Check for that.
6130     if (isDataTypeToken(ExtraToken) &&
6131         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
6132       continue;
6133 
6134     // For for ARM mode generate an error if the .n qualifier is used.
6135     if (ExtraToken == ".n" && !isThumb()) {
6136       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6137       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
6138                    "arm mode");
6139     }
6140 
6141     // The .n qualifier is always discarded as that is what the tables
6142     // and matcher expect.  In ARM mode the .w qualifier has no effect,
6143     // so discard it to avoid errors that can be caused by the matcher.
6144     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
6145       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6146       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
6147     }
6148   }
6149 
6150   // Read the remaining operands.
6151   if (getLexer().isNot(AsmToken::EndOfStatement)) {
6152     // Read the first operand.
6153     if (parseOperand(Operands, Mnemonic)) {
6154       return true;
6155     }
6156 
6157     while (parseOptionalToken(AsmToken::Comma)) {
6158       // Parse and remember the operand.
6159       if (parseOperand(Operands, Mnemonic)) {
6160         return true;
6161       }
6162     }
6163   }
6164 
6165   if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
6166     return true;
6167 
6168   if (RequireVFPRegisterListCheck) {
6169     ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
6170     if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
6171       return Error(Op.getStartLoc(),
6172                    "VFP/Neon single precision register expected");
6173     if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
6174       return Error(Op.getStartLoc(),
6175                    "VFP/Neon double precision register expected");
6176   }
6177 
6178   tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
6179 
6180   // Some instructions, mostly Thumb, have forms for the same mnemonic that
6181   // do and don't have a cc_out optional-def operand. With some spot-checks
6182   // of the operand list, we can figure out which variant we're trying to
6183   // parse and adjust accordingly before actually matching. We shouldn't ever
6184   // try to remove a cc_out operand that was explicitly set on the
6185   // mnemonic, of course (CarrySetting == true). Reason number #317 the
6186   // table driven matcher doesn't fit well with the ARM instruction set.
6187   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
6188     Operands.erase(Operands.begin() + 1);
6189 
6190   // Some instructions have the same mnemonic, but don't always
6191   // have a predicate. Distinguish them here and delete the
6192   // predicate if needed.
6193   if (shouldOmitPredicateOperand(Mnemonic, Operands))
6194     Operands.erase(Operands.begin() + 1);
6195 
6196   // ARM mode 'blx' need special handling, as the register operand version
6197   // is predicable, but the label operand version is not. So, we can't rely
6198   // on the Mnemonic based checking to correctly figure out when to put
6199   // a k_CondCode operand in the list. If we're trying to match the label
6200   // version, remove the k_CondCode operand here.
6201   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
6202       static_cast<ARMOperand &>(*Operands[2]).isImm())
6203     Operands.erase(Operands.begin() + 1);
6204 
6205   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
6206   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
6207   // a single GPRPair reg operand is used in the .td file to replace the two
6208   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
6209   // expressed as a GPRPair, so we have to manually merge them.
6210   // FIXME: We would really like to be able to tablegen'erate this.
6211   if (!isThumb() && Operands.size() > 4 &&
6212       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
6213        Mnemonic == "stlexd")) {
6214     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
6215     unsigned Idx = isLoad ? 2 : 3;
6216     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
6217     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
6218 
6219     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
6220     // Adjust only if Op1 and Op2 are GPRs.
6221     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
6222         MRC.contains(Op2.getReg())) {
6223       unsigned Reg1 = Op1.getReg();
6224       unsigned Reg2 = Op2.getReg();
6225       unsigned Rt = MRI->getEncodingValue(Reg1);
6226       unsigned Rt2 = MRI->getEncodingValue(Reg2);
6227 
6228       // Rt2 must be Rt + 1 and Rt must be even.
6229       if (Rt + 1 != Rt2 || (Rt & 1)) {
6230         return Error(Op2.getStartLoc(),
6231                      isLoad ? "destination operands must be sequential"
6232                             : "source operands must be sequential");
6233       }
6234       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
6235           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
6236       Operands[Idx] =
6237           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
6238       Operands.erase(Operands.begin() + Idx + 1);
6239     }
6240   }
6241 
6242   // GNU Assembler extension (compatibility)
6243   if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
6244     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
6245     ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6246     if (Op3.isMem()) {
6247       assert(Op2.isReg() && "expected register argument");
6248 
6249       unsigned SuperReg = MRI->getMatchingSuperReg(
6250           Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
6251 
6252       assert(SuperReg && "expected register pair");
6253 
6254       unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
6255 
6256       Operands.insert(
6257           Operands.begin() + 3,
6258           ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
6259     }
6260   }
6261 
6262   // FIXME: As said above, this is all a pretty gross hack.  This instruction
6263   // does not fit with other "subs" and tblgen.
6264   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
6265   // so the Mnemonic is the original name "subs" and delete the predicate
6266   // operand so it will match the table entry.
6267   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
6268       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6269       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
6270       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6271       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
6272       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6273     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
6274     Operands.erase(Operands.begin() + 1);
6275   }
6276   return false;
6277 }
6278 
6279 // Validate context-sensitive operand constraints.
6280 
6281 // return 'true' if register list contains non-low GPR registers,
6282 // 'false' otherwise. If Reg is in the register list or is HiReg, set
6283 // 'containsReg' to true.
6284 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
6285                                  unsigned Reg, unsigned HiReg,
6286                                  bool &containsReg) {
6287   containsReg = false;
6288   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6289     unsigned OpReg = Inst.getOperand(i).getReg();
6290     if (OpReg == Reg)
6291       containsReg = true;
6292     // Anything other than a low register isn't legal here.
6293     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6294       return true;
6295   }
6296   return false;
6297 }
6298 
6299 // Check if the specified regisgter is in the register list of the inst,
6300 // starting at the indicated operand number.
6301 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
6302   for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
6303     unsigned OpReg = Inst.getOperand(i).getReg();
6304     if (OpReg == Reg)
6305       return true;
6306   }
6307   return false;
6308 }
6309 
6310 // Return true if instruction has the interesting property of being
6311 // allowed in IT blocks, but not being predicable.
6312 static bool instIsBreakpoint(const MCInst &Inst) {
6313     return Inst.getOpcode() == ARM::tBKPT ||
6314            Inst.getOpcode() == ARM::BKPT ||
6315            Inst.getOpcode() == ARM::tHLT ||
6316            Inst.getOpcode() == ARM::HLT;
6317 
6318 }
6319 
6320 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
6321                                        const OperandVector &Operands,
6322                                        unsigned ListNo, bool IsARPop) {
6323   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6324   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6325 
6326   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6327   bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6328   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6329 
6330   if (!IsARPop && ListContainsSP)
6331     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6332                  "SP may not be in the register list");
6333   else if (ListContainsPC && ListContainsLR)
6334     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6335                  "PC and LR may not be in the register list simultaneously");
6336   return false;
6337 }
6338 
6339 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
6340                                        const OperandVector &Operands,
6341                                        unsigned ListNo) {
6342   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6343   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6344 
6345   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6346   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6347 
6348   if (ListContainsSP && ListContainsPC)
6349     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6350                  "SP and PC may not be in the register list");
6351   else if (ListContainsSP)
6352     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6353                  "SP may not be in the register list");
6354   else if (ListContainsPC)
6355     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6356                  "PC may not be in the register list");
6357   return false;
6358 }
6359 
6360 // FIXME: We would really like to be able to tablegen'erate this.
6361 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6362                                        const OperandVector &Operands) {
6363   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6364   SMLoc Loc = Operands[0]->getStartLoc();
6365 
6366   // Check the IT block state first.
6367   // NOTE: BKPT and HLT instructions have the interesting property of being
6368   // allowed in IT blocks, but not being predicable. They just always execute.
6369   if (inITBlock() && !instIsBreakpoint(Inst)) {
6370     // The instruction must be predicable.
6371     if (!MCID.isPredicable())
6372       return Error(Loc, "instructions in IT block must be predicable");
6373     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6374     if (Cond != currentITCond()) {
6375       // Find the condition code Operand to get its SMLoc information.
6376       SMLoc CondLoc;
6377       for (unsigned I = 1; I < Operands.size(); ++I)
6378         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6379           CondLoc = Operands[I]->getStartLoc();
6380       return Error(CondLoc, "incorrect condition in IT block; got '" +
6381                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
6382                    "', but expected '" +
6383                    ARMCondCodeToString(ARMCC::CondCodes(currentITCond())) + "'");
6384     }
6385   // Check for non-'al' condition codes outside of the IT block.
6386   } else if (isThumbTwo() && MCID.isPredicable() &&
6387              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6388              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6389              Inst.getOpcode() != ARM::t2Bcc) {
6390     return Error(Loc, "predicated instructions must be in IT block");
6391   } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
6392              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6393                  ARMCC::AL) {
6394     return Warning(Loc, "predicated instructions should be in IT block");
6395   }
6396 
6397   // PC-setting instructions in an IT block, but not the last instruction of
6398   // the block, are UNPREDICTABLE.
6399   if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
6400     return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
6401   }
6402 
6403   const unsigned Opcode = Inst.getOpcode();
6404   switch (Opcode) {
6405   case ARM::LDRD:
6406   case ARM::LDRD_PRE:
6407   case ARM::LDRD_POST: {
6408     const unsigned RtReg = Inst.getOperand(0).getReg();
6409 
6410     // Rt can't be R14.
6411     if (RtReg == ARM::LR)
6412       return Error(Operands[3]->getStartLoc(),
6413                    "Rt can't be R14");
6414 
6415     const unsigned Rt = MRI->getEncodingValue(RtReg);
6416     // Rt must be even-numbered.
6417     if ((Rt & 1) == 1)
6418       return Error(Operands[3]->getStartLoc(),
6419                    "Rt must be even-numbered");
6420 
6421     // Rt2 must be Rt + 1.
6422     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6423     if (Rt2 != Rt + 1)
6424       return Error(Operands[3]->getStartLoc(),
6425                    "destination operands must be sequential");
6426 
6427     if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
6428       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6429       // For addressing modes with writeback, the base register needs to be
6430       // different from the destination registers.
6431       if (Rn == Rt || Rn == Rt2)
6432         return Error(Operands[3]->getStartLoc(),
6433                      "base register needs to be different from destination "
6434                      "registers");
6435     }
6436 
6437     return false;
6438   }
6439   case ARM::t2LDRDi8:
6440   case ARM::t2LDRD_PRE:
6441   case ARM::t2LDRD_POST: {
6442     // Rt2 must be different from Rt.
6443     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6444     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6445     if (Rt2 == Rt)
6446       return Error(Operands[3]->getStartLoc(),
6447                    "destination operands can't be identical");
6448     return false;
6449   }
6450   case ARM::t2BXJ: {
6451     const unsigned RmReg = Inst.getOperand(0).getReg();
6452     // Rm = SP is no longer unpredictable in v8-A
6453     if (RmReg == ARM::SP && !hasV8Ops())
6454       return Error(Operands[2]->getStartLoc(),
6455                    "r13 (SP) is an unpredictable operand to BXJ");
6456     return false;
6457   }
6458   case ARM::STRD: {
6459     // Rt2 must be Rt + 1.
6460     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6461     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6462     if (Rt2 != Rt + 1)
6463       return Error(Operands[3]->getStartLoc(),
6464                    "source operands must be sequential");
6465     return false;
6466   }
6467   case ARM::STRD_PRE:
6468   case ARM::STRD_POST: {
6469     // Rt2 must be Rt + 1.
6470     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6471     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6472     if (Rt2 != Rt + 1)
6473       return Error(Operands[3]->getStartLoc(),
6474                    "source operands must be sequential");
6475     return false;
6476   }
6477   case ARM::STR_PRE_IMM:
6478   case ARM::STR_PRE_REG:
6479   case ARM::STR_POST_IMM:
6480   case ARM::STR_POST_REG:
6481   case ARM::STRH_PRE:
6482   case ARM::STRH_POST:
6483   case ARM::STRB_PRE_IMM:
6484   case ARM::STRB_PRE_REG:
6485   case ARM::STRB_POST_IMM:
6486   case ARM::STRB_POST_REG: {
6487     // Rt must be different from Rn.
6488     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6489     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6490 
6491     if (Rt == Rn)
6492       return Error(Operands[3]->getStartLoc(),
6493                    "source register and base register can't be identical");
6494     return false;
6495   }
6496   case ARM::LDR_PRE_IMM:
6497   case ARM::LDR_PRE_REG:
6498   case ARM::LDR_POST_IMM:
6499   case ARM::LDR_POST_REG:
6500   case ARM::LDRH_PRE:
6501   case ARM::LDRH_POST:
6502   case ARM::LDRSH_PRE:
6503   case ARM::LDRSH_POST:
6504   case ARM::LDRB_PRE_IMM:
6505   case ARM::LDRB_PRE_REG:
6506   case ARM::LDRB_POST_IMM:
6507   case ARM::LDRB_POST_REG:
6508   case ARM::LDRSB_PRE:
6509   case ARM::LDRSB_POST: {
6510     // Rt must be different from Rn.
6511     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6512     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6513 
6514     if (Rt == Rn)
6515       return Error(Operands[3]->getStartLoc(),
6516                    "destination register and base register can't be identical");
6517     return false;
6518   }
6519   case ARM::SBFX:
6520   case ARM::UBFX: {
6521     // Width must be in range [1, 32-lsb].
6522     unsigned LSB = Inst.getOperand(2).getImm();
6523     unsigned Widthm1 = Inst.getOperand(3).getImm();
6524     if (Widthm1 >= 32 - LSB)
6525       return Error(Operands[5]->getStartLoc(),
6526                    "bitfield width must be in range [1,32-lsb]");
6527     return false;
6528   }
6529   // Notionally handles ARM::tLDMIA_UPD too.
6530   case ARM::tLDMIA: {
6531     // If we're parsing Thumb2, the .w variant is available and handles
6532     // most cases that are normally illegal for a Thumb1 LDM instruction.
6533     // We'll make the transformation in processInstruction() if necessary.
6534     //
6535     // Thumb LDM instructions are writeback iff the base register is not
6536     // in the register list.
6537     unsigned Rn = Inst.getOperand(0).getReg();
6538     bool HasWritebackToken =
6539         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6540          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6541     bool ListContainsBase;
6542     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6543       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6544                    "registers must be in range r0-r7");
6545     // If we should have writeback, then there should be a '!' token.
6546     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6547       return Error(Operands[2]->getStartLoc(),
6548                    "writeback operator '!' expected");
6549     // If we should not have writeback, there must not be a '!'. This is
6550     // true even for the 32-bit wide encodings.
6551     if (ListContainsBase && HasWritebackToken)
6552       return Error(Operands[3]->getStartLoc(),
6553                    "writeback operator '!' not allowed when base register "
6554                    "in register list");
6555 
6556     if (validatetLDMRegList(Inst, Operands, 3))
6557       return true;
6558     break;
6559   }
6560   case ARM::LDMIA_UPD:
6561   case ARM::LDMDB_UPD:
6562   case ARM::LDMIB_UPD:
6563   case ARM::LDMDA_UPD:
6564     // ARM variants loading and updating the same register are only officially
6565     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6566     if (!hasV7Ops())
6567       break;
6568     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6569       return Error(Operands.back()->getStartLoc(),
6570                    "writeback register not allowed in register list");
6571     break;
6572   case ARM::t2LDMIA:
6573   case ARM::t2LDMDB:
6574     if (validatetLDMRegList(Inst, Operands, 3))
6575       return true;
6576     break;
6577   case ARM::t2STMIA:
6578   case ARM::t2STMDB:
6579     if (validatetSTMRegList(Inst, Operands, 3))
6580       return true;
6581     break;
6582   case ARM::t2LDMIA_UPD:
6583   case ARM::t2LDMDB_UPD:
6584   case ARM::t2STMIA_UPD:
6585   case ARM::t2STMDB_UPD: {
6586     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6587       return Error(Operands.back()->getStartLoc(),
6588                    "writeback register not allowed in register list");
6589 
6590     if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6591       if (validatetLDMRegList(Inst, Operands, 3))
6592         return true;
6593     } else {
6594       if (validatetSTMRegList(Inst, Operands, 3))
6595         return true;
6596     }
6597     break;
6598   }
6599   case ARM::sysLDMIA_UPD:
6600   case ARM::sysLDMDA_UPD:
6601   case ARM::sysLDMDB_UPD:
6602   case ARM::sysLDMIB_UPD:
6603     if (!listContainsReg(Inst, 3, ARM::PC))
6604       return Error(Operands[4]->getStartLoc(),
6605                    "writeback register only allowed on system LDM "
6606                    "if PC in register-list");
6607     break;
6608   case ARM::sysSTMIA_UPD:
6609   case ARM::sysSTMDA_UPD:
6610   case ARM::sysSTMDB_UPD:
6611   case ARM::sysSTMIB_UPD:
6612     return Error(Operands[2]->getStartLoc(),
6613                  "system STM cannot have writeback register");
6614   case ARM::tMUL: {
6615     // The second source operand must be the same register as the destination
6616     // operand.
6617     //
6618     // In this case, we must directly check the parsed operands because the
6619     // cvtThumbMultiply() function is written in such a way that it guarantees
6620     // this first statement is always true for the new Inst.  Essentially, the
6621     // destination is unconditionally copied into the second source operand
6622     // without checking to see if it matches what we actually parsed.
6623     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6624                                  ((ARMOperand &)*Operands[5]).getReg()) &&
6625         (((ARMOperand &)*Operands[3]).getReg() !=
6626          ((ARMOperand &)*Operands[4]).getReg())) {
6627       return Error(Operands[3]->getStartLoc(),
6628                    "destination register must match source register");
6629     }
6630     break;
6631   }
6632   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6633   // so only issue a diagnostic for thumb1. The instructions will be
6634   // switched to the t2 encodings in processInstruction() if necessary.
6635   case ARM::tPOP: {
6636     bool ListContainsBase;
6637     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6638         !isThumbTwo())
6639       return Error(Operands[2]->getStartLoc(),
6640                    "registers must be in range r0-r7 or pc");
6641     if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6642       return true;
6643     break;
6644   }
6645   case ARM::tPUSH: {
6646     bool ListContainsBase;
6647     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6648         !isThumbTwo())
6649       return Error(Operands[2]->getStartLoc(),
6650                    "registers must be in range r0-r7 or lr");
6651     if (validatetSTMRegList(Inst, Operands, 2))
6652       return true;
6653     break;
6654   }
6655   case ARM::tSTMIA_UPD: {
6656     bool ListContainsBase, InvalidLowList;
6657     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6658                                           0, ListContainsBase);
6659     if (InvalidLowList && !isThumbTwo())
6660       return Error(Operands[4]->getStartLoc(),
6661                    "registers must be in range r0-r7");
6662 
6663     // This would be converted to a 32-bit stm, but that's not valid if the
6664     // writeback register is in the list.
6665     if (InvalidLowList && ListContainsBase)
6666       return Error(Operands[4]->getStartLoc(),
6667                    "writeback operator '!' not allowed when base register "
6668                    "in register list");
6669 
6670     if (validatetSTMRegList(Inst, Operands, 4))
6671       return true;
6672     break;
6673   }
6674   case ARM::tADDrSP: {
6675     // If the non-SP source operand and the destination operand are not the
6676     // same, we need thumb2 (for the wide encoding), or we have an error.
6677     if (!isThumbTwo() &&
6678         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6679       return Error(Operands[4]->getStartLoc(),
6680                    "source register must be the same as destination");
6681     }
6682     break;
6683   }
6684   // Final range checking for Thumb unconditional branch instructions.
6685   case ARM::tB:
6686     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6687       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6688     break;
6689   case ARM::t2B: {
6690     int op = (Operands[2]->isImm()) ? 2 : 3;
6691     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6692       return Error(Operands[op]->getStartLoc(), "branch target out of range");
6693     break;
6694   }
6695   // Final range checking for Thumb conditional branch instructions.
6696   case ARM::tBcc:
6697     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6698       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6699     break;
6700   case ARM::t2Bcc: {
6701     int Op = (Operands[2]->isImm()) ? 2 : 3;
6702     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6703       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6704     break;
6705   }
6706   case ARM::tCBZ:
6707   case ARM::tCBNZ: {
6708     if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
6709       return Error(Operands[2]->getStartLoc(), "branch target out of range");
6710     break;
6711   }
6712   case ARM::MOVi16:
6713   case ARM::MOVTi16:
6714   case ARM::t2MOVi16:
6715   case ARM::t2MOVTi16:
6716     {
6717     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6718     // especially when we turn it into a movw and the expression <symbol> does
6719     // not have a :lower16: or :upper16 as part of the expression.  We don't
6720     // want the behavior of silently truncating, which can be unexpected and
6721     // lead to bugs that are difficult to find since this is an easy mistake
6722     // to make.
6723     int i = (Operands[3]->isImm()) ? 3 : 4;
6724     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6725     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6726     if (CE) break;
6727     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6728     if (!E) break;
6729     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6730     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6731                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6732       return Error(
6733           Op.getStartLoc(),
6734           "immediate expression for mov requires :lower16: or :upper16");
6735     break;
6736   }
6737   case ARM::HINT:
6738   case ARM::t2HINT: {
6739     if (hasRAS()) {
6740       // ESB is not predicable (pred must be AL)
6741       unsigned Imm8 = Inst.getOperand(0).getImm();
6742       unsigned Pred = Inst.getOperand(1).getImm();
6743       if (Imm8 == 0x10 && Pred != ARMCC::AL)
6744         return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
6745                                                  "predicable, but condition "
6746                                                  "code specified");
6747     }
6748     // Without the RAS extension, this behaves as any other unallocated hint.
6749     break;
6750   }
6751   }
6752 
6753   return false;
6754 }
6755 
6756 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6757   switch(Opc) {
6758   default: llvm_unreachable("unexpected opcode!");
6759   // VST1LN
6760   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6761   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6762   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6763   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
6764   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6765   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6766   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
6767   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6768   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6769 
6770   // VST2LN
6771   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6772   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6773   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6774   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6775   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6776 
6777   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
6778   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6779   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6780   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6781   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6782 
6783   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
6784   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6785   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6786   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6787   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6788 
6789   // VST3LN
6790   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6791   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6792   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6793   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6794   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6795   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
6796   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6797   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6798   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6799   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6800   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
6801   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6802   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6803   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6804   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6805 
6806   // VST3
6807   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6808   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6809   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6810   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6811   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6812   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6813   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
6814   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6815   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6816   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
6817   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6818   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6819   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
6820   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6821   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6822   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
6823   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6824   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6825 
6826   // VST4LN
6827   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6828   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6829   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6830   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6831   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6832   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
6833   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6834   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6835   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6836   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6837   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
6838   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6839   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6840   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6841   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6842 
6843   // VST4
6844   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6845   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6846   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6847   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6848   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6849   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6850   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
6851   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6852   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6853   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
6854   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6855   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6856   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
6857   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6858   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6859   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
6860   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6861   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6862   }
6863 }
6864 
6865 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6866   switch(Opc) {
6867   default: llvm_unreachable("unexpected opcode!");
6868   // VLD1LN
6869   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6870   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6871   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6872   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
6873   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6874   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6875   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
6876   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6877   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6878 
6879   // VLD2LN
6880   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6881   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6882   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6883   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6884   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6885   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
6886   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6887   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6888   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6889   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6890   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
6891   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6892   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6893   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6894   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6895 
6896   // VLD3DUP
6897   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6898   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6899   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6900   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6901   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6902   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6903   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
6904   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6905   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6906   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6907   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6908   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6909   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
6910   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6911   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6912   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6913   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6914   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6915 
6916   // VLD3LN
6917   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6918   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6919   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6920   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6921   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6922   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
6923   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6924   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6925   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6926   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6927   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
6928   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6929   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6930   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6931   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6932 
6933   // VLD3
6934   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6935   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6936   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6937   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6938   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6939   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6940   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
6941   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6942   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6943   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
6944   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6945   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6946   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
6947   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6948   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6949   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
6950   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6951   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6952 
6953   // VLD4LN
6954   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6955   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6956   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6957   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6958   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6959   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
6960   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6961   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6962   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6963   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6964   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
6965   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6966   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6967   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6968   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6969 
6970   // VLD4DUP
6971   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6972   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6973   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6974   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6975   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6976   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6977   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
6978   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6979   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6980   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6981   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6982   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6983   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
6984   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6985   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6986   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6987   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6988   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6989 
6990   // VLD4
6991   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6992   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6993   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6994   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
6995   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6996   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6997   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
6998   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6999   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
7000   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
7001   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
7002   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
7003   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
7004   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
7005   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
7006   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
7007   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
7008   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
7009   }
7010 }
7011 
7012 bool ARMAsmParser::processInstruction(MCInst &Inst,
7013                                       const OperandVector &Operands,
7014                                       MCStreamer &Out) {
7015   switch (Inst.getOpcode()) {
7016   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
7017   case ARM::LDRT_POST:
7018   case ARM::LDRBT_POST: {
7019     const unsigned Opcode =
7020       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
7021                                            : ARM::LDRBT_POST_IMM;
7022     MCInst TmpInst;
7023     TmpInst.setOpcode(Opcode);
7024     TmpInst.addOperand(Inst.getOperand(0));
7025     TmpInst.addOperand(Inst.getOperand(1));
7026     TmpInst.addOperand(Inst.getOperand(1));
7027     TmpInst.addOperand(MCOperand::createReg(0));
7028     TmpInst.addOperand(MCOperand::createImm(0));
7029     TmpInst.addOperand(Inst.getOperand(2));
7030     TmpInst.addOperand(Inst.getOperand(3));
7031     Inst = TmpInst;
7032     return true;
7033   }
7034   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
7035   case ARM::STRT_POST:
7036   case ARM::STRBT_POST: {
7037     const unsigned Opcode =
7038       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
7039                                            : ARM::STRBT_POST_IMM;
7040     MCInst TmpInst;
7041     TmpInst.setOpcode(Opcode);
7042     TmpInst.addOperand(Inst.getOperand(1));
7043     TmpInst.addOperand(Inst.getOperand(0));
7044     TmpInst.addOperand(Inst.getOperand(1));
7045     TmpInst.addOperand(MCOperand::createReg(0));
7046     TmpInst.addOperand(MCOperand::createImm(0));
7047     TmpInst.addOperand(Inst.getOperand(2));
7048     TmpInst.addOperand(Inst.getOperand(3));
7049     Inst = TmpInst;
7050     return true;
7051   }
7052   // Alias for alternate form of 'ADR Rd, #imm' instruction.
7053   case ARM::ADDri: {
7054     if (Inst.getOperand(1).getReg() != ARM::PC ||
7055         Inst.getOperand(5).getReg() != 0 ||
7056         !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
7057       return false;
7058     MCInst TmpInst;
7059     TmpInst.setOpcode(ARM::ADR);
7060     TmpInst.addOperand(Inst.getOperand(0));
7061     if (Inst.getOperand(2).isImm()) {
7062       // Immediate (mod_imm) will be in its encoded form, we must unencode it
7063       // before passing it to the ADR instruction.
7064       unsigned Enc = Inst.getOperand(2).getImm();
7065       TmpInst.addOperand(MCOperand::createImm(
7066         ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
7067     } else {
7068       // Turn PC-relative expression into absolute expression.
7069       // Reading PC provides the start of the current instruction + 8 and
7070       // the transform to adr is biased by that.
7071       MCSymbol *Dot = getContext().createTempSymbol();
7072       Out.EmitLabel(Dot);
7073       const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
7074       const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
7075                                                      MCSymbolRefExpr::VK_None,
7076                                                      getContext());
7077       const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
7078       const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
7079                                                      getContext());
7080       const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
7081                                                         getContext());
7082       TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
7083     }
7084     TmpInst.addOperand(Inst.getOperand(3));
7085     TmpInst.addOperand(Inst.getOperand(4));
7086     Inst = TmpInst;
7087     return true;
7088   }
7089   // Aliases for alternate PC+imm syntax of LDR instructions.
7090   case ARM::t2LDRpcrel:
7091     // Select the narrow version if the immediate will fit.
7092     if (Inst.getOperand(1).getImm() > 0 &&
7093         Inst.getOperand(1).getImm() <= 0xff &&
7094         !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
7095           static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
7096       Inst.setOpcode(ARM::tLDRpci);
7097     else
7098       Inst.setOpcode(ARM::t2LDRpci);
7099     return true;
7100   case ARM::t2LDRBpcrel:
7101     Inst.setOpcode(ARM::t2LDRBpci);
7102     return true;
7103   case ARM::t2LDRHpcrel:
7104     Inst.setOpcode(ARM::t2LDRHpci);
7105     return true;
7106   case ARM::t2LDRSBpcrel:
7107     Inst.setOpcode(ARM::t2LDRSBpci);
7108     return true;
7109   case ARM::t2LDRSHpcrel:
7110     Inst.setOpcode(ARM::t2LDRSHpci);
7111     return true;
7112   case ARM::LDRConstPool:
7113   case ARM::tLDRConstPool:
7114   case ARM::t2LDRConstPool: {
7115     // Pseudo instruction ldr rt, =immediate is converted to a
7116     // MOV rt, immediate if immediate is known and representable
7117     // otherwise we create a constant pool entry that we load from.
7118     MCInst TmpInst;
7119     if (Inst.getOpcode() == ARM::LDRConstPool)
7120       TmpInst.setOpcode(ARM::LDRi12);
7121     else if (Inst.getOpcode() == ARM::tLDRConstPool)
7122       TmpInst.setOpcode(ARM::tLDRpci);
7123     else if (Inst.getOpcode() == ARM::t2LDRConstPool)
7124       TmpInst.setOpcode(ARM::t2LDRpci);
7125     const ARMOperand &PoolOperand =
7126       (static_cast<ARMOperand &>(*Operands[2]).isToken() &&
7127        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w") ?
7128       static_cast<ARMOperand &>(*Operands[4]) :
7129       static_cast<ARMOperand &>(*Operands[3]);
7130     const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
7131     // If SubExprVal is a constant we may be able to use a MOV
7132     if (isa<MCConstantExpr>(SubExprVal) &&
7133         Inst.getOperand(0).getReg() != ARM::PC &&
7134         Inst.getOperand(0).getReg() != ARM::SP) {
7135       int64_t Value =
7136         (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
7137       bool UseMov  = true;
7138       bool MovHasS = true;
7139       if (Inst.getOpcode() == ARM::LDRConstPool) {
7140         // ARM Constant
7141         if (ARM_AM::getSOImmVal(Value) != -1) {
7142           Value = ARM_AM::getSOImmVal(Value);
7143           TmpInst.setOpcode(ARM::MOVi);
7144         }
7145         else if (ARM_AM::getSOImmVal(~Value) != -1) {
7146           Value = ARM_AM::getSOImmVal(~Value);
7147           TmpInst.setOpcode(ARM::MVNi);
7148         }
7149         else if (hasV6T2Ops() &&
7150                  Value >=0 && Value < 65536) {
7151           TmpInst.setOpcode(ARM::MOVi16);
7152           MovHasS = false;
7153         }
7154         else
7155           UseMov = false;
7156       }
7157       else {
7158         // Thumb/Thumb2 Constant
7159         if (hasThumb2() &&
7160             ARM_AM::getT2SOImmVal(Value) != -1)
7161           TmpInst.setOpcode(ARM::t2MOVi);
7162         else if (hasThumb2() &&
7163                  ARM_AM::getT2SOImmVal(~Value) != -1) {
7164           TmpInst.setOpcode(ARM::t2MVNi);
7165           Value = ~Value;
7166         }
7167         else if (hasV8MBaseline() &&
7168                  Value >=0 && Value < 65536) {
7169           TmpInst.setOpcode(ARM::t2MOVi16);
7170           MovHasS = false;
7171         }
7172         else
7173           UseMov = false;
7174       }
7175       if (UseMov) {
7176         TmpInst.addOperand(Inst.getOperand(0));           // Rt
7177         TmpInst.addOperand(MCOperand::createImm(Value));  // Immediate
7178         TmpInst.addOperand(Inst.getOperand(2));           // CondCode
7179         TmpInst.addOperand(Inst.getOperand(3));           // CondCode
7180         if (MovHasS)
7181           TmpInst.addOperand(MCOperand::createReg(0));    // S
7182         Inst = TmpInst;
7183         return true;
7184       }
7185     }
7186     // No opportunity to use MOV/MVN create constant pool
7187     const MCExpr *CPLoc =
7188       getTargetStreamer().addConstantPoolEntry(SubExprVal,
7189                                                PoolOperand.getStartLoc());
7190     TmpInst.addOperand(Inst.getOperand(0));           // Rt
7191     TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
7192     if (TmpInst.getOpcode() == ARM::LDRi12)
7193       TmpInst.addOperand(MCOperand::createImm(0));    // unused offset
7194     TmpInst.addOperand(Inst.getOperand(2));           // CondCode
7195     TmpInst.addOperand(Inst.getOperand(3));           // CondCode
7196     Inst = TmpInst;
7197     return true;
7198   }
7199   // Handle NEON VST complex aliases.
7200   case ARM::VST1LNdWB_register_Asm_8:
7201   case ARM::VST1LNdWB_register_Asm_16:
7202   case ARM::VST1LNdWB_register_Asm_32: {
7203     MCInst TmpInst;
7204     // Shuffle the operands around so the lane index operand is in the
7205     // right place.
7206     unsigned Spacing;
7207     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7208     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7209     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7210     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7211     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7212     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7213     TmpInst.addOperand(Inst.getOperand(1)); // lane
7214     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7215     TmpInst.addOperand(Inst.getOperand(6));
7216     Inst = TmpInst;
7217     return true;
7218   }
7219 
7220   case ARM::VST2LNdWB_register_Asm_8:
7221   case ARM::VST2LNdWB_register_Asm_16:
7222   case ARM::VST2LNdWB_register_Asm_32:
7223   case ARM::VST2LNqWB_register_Asm_16:
7224   case ARM::VST2LNqWB_register_Asm_32: {
7225     MCInst TmpInst;
7226     // Shuffle the operands around so the lane index operand is in the
7227     // right place.
7228     unsigned Spacing;
7229     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7230     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7231     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7232     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7233     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7234     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7235     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7236                                             Spacing));
7237     TmpInst.addOperand(Inst.getOperand(1)); // lane
7238     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7239     TmpInst.addOperand(Inst.getOperand(6));
7240     Inst = TmpInst;
7241     return true;
7242   }
7243 
7244   case ARM::VST3LNdWB_register_Asm_8:
7245   case ARM::VST3LNdWB_register_Asm_16:
7246   case ARM::VST3LNdWB_register_Asm_32:
7247   case ARM::VST3LNqWB_register_Asm_16:
7248   case ARM::VST3LNqWB_register_Asm_32: {
7249     MCInst TmpInst;
7250     // Shuffle the operands around so the lane index operand is in the
7251     // right place.
7252     unsigned Spacing;
7253     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7254     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7255     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7256     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7257     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7258     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7259     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7260                                             Spacing));
7261     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7262                                             Spacing * 2));
7263     TmpInst.addOperand(Inst.getOperand(1)); // lane
7264     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7265     TmpInst.addOperand(Inst.getOperand(6));
7266     Inst = TmpInst;
7267     return true;
7268   }
7269 
7270   case ARM::VST4LNdWB_register_Asm_8:
7271   case ARM::VST4LNdWB_register_Asm_16:
7272   case ARM::VST4LNdWB_register_Asm_32:
7273   case ARM::VST4LNqWB_register_Asm_16:
7274   case ARM::VST4LNqWB_register_Asm_32: {
7275     MCInst TmpInst;
7276     // Shuffle the operands around so the lane index operand is in the
7277     // right place.
7278     unsigned Spacing;
7279     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7280     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7281     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7282     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7283     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7284     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7285     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7286                                             Spacing));
7287     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7288                                             Spacing * 2));
7289     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7290                                             Spacing * 3));
7291     TmpInst.addOperand(Inst.getOperand(1)); // lane
7292     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7293     TmpInst.addOperand(Inst.getOperand(6));
7294     Inst = TmpInst;
7295     return true;
7296   }
7297 
7298   case ARM::VST1LNdWB_fixed_Asm_8:
7299   case ARM::VST1LNdWB_fixed_Asm_16:
7300   case ARM::VST1LNdWB_fixed_Asm_32: {
7301     MCInst TmpInst;
7302     // Shuffle the operands around so the lane index operand is in the
7303     // right place.
7304     unsigned Spacing;
7305     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7306     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7307     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7308     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7309     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7310     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7311     TmpInst.addOperand(Inst.getOperand(1)); // lane
7312     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7313     TmpInst.addOperand(Inst.getOperand(5));
7314     Inst = TmpInst;
7315     return true;
7316   }
7317 
7318   case ARM::VST2LNdWB_fixed_Asm_8:
7319   case ARM::VST2LNdWB_fixed_Asm_16:
7320   case ARM::VST2LNdWB_fixed_Asm_32:
7321   case ARM::VST2LNqWB_fixed_Asm_16:
7322   case ARM::VST2LNqWB_fixed_Asm_32: {
7323     MCInst TmpInst;
7324     // Shuffle the operands around so the lane index operand is in the
7325     // right place.
7326     unsigned Spacing;
7327     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7328     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7329     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7330     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7331     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7332     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7333     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7334                                             Spacing));
7335     TmpInst.addOperand(Inst.getOperand(1)); // lane
7336     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7337     TmpInst.addOperand(Inst.getOperand(5));
7338     Inst = TmpInst;
7339     return true;
7340   }
7341 
7342   case ARM::VST3LNdWB_fixed_Asm_8:
7343   case ARM::VST3LNdWB_fixed_Asm_16:
7344   case ARM::VST3LNdWB_fixed_Asm_32:
7345   case ARM::VST3LNqWB_fixed_Asm_16:
7346   case ARM::VST3LNqWB_fixed_Asm_32: {
7347     MCInst TmpInst;
7348     // Shuffle the operands around so the lane index operand is in the
7349     // right place.
7350     unsigned Spacing;
7351     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7352     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7353     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7354     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7355     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7356     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7357     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7358                                             Spacing));
7359     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7360                                             Spacing * 2));
7361     TmpInst.addOperand(Inst.getOperand(1)); // lane
7362     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7363     TmpInst.addOperand(Inst.getOperand(5));
7364     Inst = TmpInst;
7365     return true;
7366   }
7367 
7368   case ARM::VST4LNdWB_fixed_Asm_8:
7369   case ARM::VST4LNdWB_fixed_Asm_16:
7370   case ARM::VST4LNdWB_fixed_Asm_32:
7371   case ARM::VST4LNqWB_fixed_Asm_16:
7372   case ARM::VST4LNqWB_fixed_Asm_32: {
7373     MCInst TmpInst;
7374     // Shuffle the operands around so the lane index operand is in the
7375     // right place.
7376     unsigned Spacing;
7377     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7378     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7379     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7380     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7381     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7382     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7383     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7384                                             Spacing));
7385     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7386                                             Spacing * 2));
7387     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7388                                             Spacing * 3));
7389     TmpInst.addOperand(Inst.getOperand(1)); // lane
7390     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7391     TmpInst.addOperand(Inst.getOperand(5));
7392     Inst = TmpInst;
7393     return true;
7394   }
7395 
7396   case ARM::VST1LNdAsm_8:
7397   case ARM::VST1LNdAsm_16:
7398   case ARM::VST1LNdAsm_32: {
7399     MCInst TmpInst;
7400     // Shuffle the operands around so the lane index operand is in the
7401     // right place.
7402     unsigned Spacing;
7403     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7404     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7405     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7406     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7407     TmpInst.addOperand(Inst.getOperand(1)); // lane
7408     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7409     TmpInst.addOperand(Inst.getOperand(5));
7410     Inst = TmpInst;
7411     return true;
7412   }
7413 
7414   case ARM::VST2LNdAsm_8:
7415   case ARM::VST2LNdAsm_16:
7416   case ARM::VST2LNdAsm_32:
7417   case ARM::VST2LNqAsm_16:
7418   case ARM::VST2LNqAsm_32: {
7419     MCInst TmpInst;
7420     // Shuffle the operands around so the lane index operand is in the
7421     // right place.
7422     unsigned Spacing;
7423     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7424     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7425     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7426     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7427     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7428                                             Spacing));
7429     TmpInst.addOperand(Inst.getOperand(1)); // lane
7430     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7431     TmpInst.addOperand(Inst.getOperand(5));
7432     Inst = TmpInst;
7433     return true;
7434   }
7435 
7436   case ARM::VST3LNdAsm_8:
7437   case ARM::VST3LNdAsm_16:
7438   case ARM::VST3LNdAsm_32:
7439   case ARM::VST3LNqAsm_16:
7440   case ARM::VST3LNqAsm_32: {
7441     MCInst TmpInst;
7442     // Shuffle the operands around so the lane index operand is in the
7443     // right place.
7444     unsigned Spacing;
7445     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7446     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7447     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7448     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7449     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7450                                             Spacing));
7451     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7452                                             Spacing * 2));
7453     TmpInst.addOperand(Inst.getOperand(1)); // lane
7454     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7455     TmpInst.addOperand(Inst.getOperand(5));
7456     Inst = TmpInst;
7457     return true;
7458   }
7459 
7460   case ARM::VST4LNdAsm_8:
7461   case ARM::VST4LNdAsm_16:
7462   case ARM::VST4LNdAsm_32:
7463   case ARM::VST4LNqAsm_16:
7464   case ARM::VST4LNqAsm_32: {
7465     MCInst TmpInst;
7466     // Shuffle the operands around so the lane index operand is in the
7467     // right place.
7468     unsigned Spacing;
7469     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7470     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7471     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7472     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7473     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7474                                             Spacing));
7475     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7476                                             Spacing * 2));
7477     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7478                                             Spacing * 3));
7479     TmpInst.addOperand(Inst.getOperand(1)); // lane
7480     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7481     TmpInst.addOperand(Inst.getOperand(5));
7482     Inst = TmpInst;
7483     return true;
7484   }
7485 
7486   // Handle NEON VLD complex aliases.
7487   case ARM::VLD1LNdWB_register_Asm_8:
7488   case ARM::VLD1LNdWB_register_Asm_16:
7489   case ARM::VLD1LNdWB_register_Asm_32: {
7490     MCInst TmpInst;
7491     // Shuffle the operands around so the lane index operand is in the
7492     // right place.
7493     unsigned Spacing;
7494     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7495     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7496     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7497     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7498     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7499     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7500     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7501     TmpInst.addOperand(Inst.getOperand(1)); // lane
7502     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7503     TmpInst.addOperand(Inst.getOperand(6));
7504     Inst = TmpInst;
7505     return true;
7506   }
7507 
7508   case ARM::VLD2LNdWB_register_Asm_8:
7509   case ARM::VLD2LNdWB_register_Asm_16:
7510   case ARM::VLD2LNdWB_register_Asm_32:
7511   case ARM::VLD2LNqWB_register_Asm_16:
7512   case ARM::VLD2LNqWB_register_Asm_32: {
7513     MCInst TmpInst;
7514     // Shuffle the operands around so the lane index operand is in the
7515     // right place.
7516     unsigned Spacing;
7517     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7518     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7519     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7520                                             Spacing));
7521     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7522     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7523     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7524     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7525     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7526     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7527                                             Spacing));
7528     TmpInst.addOperand(Inst.getOperand(1)); // lane
7529     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7530     TmpInst.addOperand(Inst.getOperand(6));
7531     Inst = TmpInst;
7532     return true;
7533   }
7534 
7535   case ARM::VLD3LNdWB_register_Asm_8:
7536   case ARM::VLD3LNdWB_register_Asm_16:
7537   case ARM::VLD3LNdWB_register_Asm_32:
7538   case ARM::VLD3LNqWB_register_Asm_16:
7539   case ARM::VLD3LNqWB_register_Asm_32: {
7540     MCInst TmpInst;
7541     // Shuffle the operands around so the lane index operand is in the
7542     // right place.
7543     unsigned Spacing;
7544     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7545     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7546     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7547                                             Spacing));
7548     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7549                                             Spacing * 2));
7550     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7551     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7552     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7553     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7554     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7555     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7556                                             Spacing));
7557     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7558                                             Spacing * 2));
7559     TmpInst.addOperand(Inst.getOperand(1)); // lane
7560     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7561     TmpInst.addOperand(Inst.getOperand(6));
7562     Inst = TmpInst;
7563     return true;
7564   }
7565 
7566   case ARM::VLD4LNdWB_register_Asm_8:
7567   case ARM::VLD4LNdWB_register_Asm_16:
7568   case ARM::VLD4LNdWB_register_Asm_32:
7569   case ARM::VLD4LNqWB_register_Asm_16:
7570   case ARM::VLD4LNqWB_register_Asm_32: {
7571     MCInst TmpInst;
7572     // Shuffle the operands around so the lane index operand is in the
7573     // right place.
7574     unsigned Spacing;
7575     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7576     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7577     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7578                                             Spacing));
7579     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7580                                             Spacing * 2));
7581     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7582                                             Spacing * 3));
7583     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7584     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7585     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7586     TmpInst.addOperand(Inst.getOperand(4)); // Rm
7587     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7588     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7589                                             Spacing));
7590     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7591                                             Spacing * 2));
7592     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7593                                             Spacing * 3));
7594     TmpInst.addOperand(Inst.getOperand(1)); // lane
7595     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7596     TmpInst.addOperand(Inst.getOperand(6));
7597     Inst = TmpInst;
7598     return true;
7599   }
7600 
7601   case ARM::VLD1LNdWB_fixed_Asm_8:
7602   case ARM::VLD1LNdWB_fixed_Asm_16:
7603   case ARM::VLD1LNdWB_fixed_Asm_32: {
7604     MCInst TmpInst;
7605     // Shuffle the operands around so the lane index operand is in the
7606     // right place.
7607     unsigned Spacing;
7608     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7609     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7610     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7611     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7612     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7613     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7614     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7615     TmpInst.addOperand(Inst.getOperand(1)); // lane
7616     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7617     TmpInst.addOperand(Inst.getOperand(5));
7618     Inst = TmpInst;
7619     return true;
7620   }
7621 
7622   case ARM::VLD2LNdWB_fixed_Asm_8:
7623   case ARM::VLD2LNdWB_fixed_Asm_16:
7624   case ARM::VLD2LNdWB_fixed_Asm_32:
7625   case ARM::VLD2LNqWB_fixed_Asm_16:
7626   case ARM::VLD2LNqWB_fixed_Asm_32: {
7627     MCInst TmpInst;
7628     // Shuffle the operands around so the lane index operand is in the
7629     // right place.
7630     unsigned Spacing;
7631     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7632     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7633     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7634                                             Spacing));
7635     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7636     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7637     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7638     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7639     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7640     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7641                                             Spacing));
7642     TmpInst.addOperand(Inst.getOperand(1)); // lane
7643     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7644     TmpInst.addOperand(Inst.getOperand(5));
7645     Inst = TmpInst;
7646     return true;
7647   }
7648 
7649   case ARM::VLD3LNdWB_fixed_Asm_8:
7650   case ARM::VLD3LNdWB_fixed_Asm_16:
7651   case ARM::VLD3LNdWB_fixed_Asm_32:
7652   case ARM::VLD3LNqWB_fixed_Asm_16:
7653   case ARM::VLD3LNqWB_fixed_Asm_32: {
7654     MCInst TmpInst;
7655     // Shuffle the operands around so the lane index operand is in the
7656     // right place.
7657     unsigned Spacing;
7658     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7659     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7660     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7661                                             Spacing));
7662     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7663                                             Spacing * 2));
7664     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7665     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7666     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7667     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7668     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7669     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7670                                             Spacing));
7671     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7672                                             Spacing * 2));
7673     TmpInst.addOperand(Inst.getOperand(1)); // lane
7674     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7675     TmpInst.addOperand(Inst.getOperand(5));
7676     Inst = TmpInst;
7677     return true;
7678   }
7679 
7680   case ARM::VLD4LNdWB_fixed_Asm_8:
7681   case ARM::VLD4LNdWB_fixed_Asm_16:
7682   case ARM::VLD4LNdWB_fixed_Asm_32:
7683   case ARM::VLD4LNqWB_fixed_Asm_16:
7684   case ARM::VLD4LNqWB_fixed_Asm_32: {
7685     MCInst TmpInst;
7686     // Shuffle the operands around so the lane index operand is in the
7687     // right place.
7688     unsigned Spacing;
7689     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7690     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7691     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7692                                             Spacing));
7693     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7694                                             Spacing * 2));
7695     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7696                                             Spacing * 3));
7697     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7698     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7699     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7700     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7701     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7702     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7703                                             Spacing));
7704     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7705                                             Spacing * 2));
7706     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7707                                             Spacing * 3));
7708     TmpInst.addOperand(Inst.getOperand(1)); // lane
7709     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7710     TmpInst.addOperand(Inst.getOperand(5));
7711     Inst = TmpInst;
7712     return true;
7713   }
7714 
7715   case ARM::VLD1LNdAsm_8:
7716   case ARM::VLD1LNdAsm_16:
7717   case ARM::VLD1LNdAsm_32: {
7718     MCInst TmpInst;
7719     // Shuffle the operands around so the lane index operand is in the
7720     // right place.
7721     unsigned Spacing;
7722     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7723     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7724     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7725     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7726     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7727     TmpInst.addOperand(Inst.getOperand(1)); // lane
7728     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7729     TmpInst.addOperand(Inst.getOperand(5));
7730     Inst = TmpInst;
7731     return true;
7732   }
7733 
7734   case ARM::VLD2LNdAsm_8:
7735   case ARM::VLD2LNdAsm_16:
7736   case ARM::VLD2LNdAsm_32:
7737   case ARM::VLD2LNqAsm_16:
7738   case ARM::VLD2LNqAsm_32: {
7739     MCInst TmpInst;
7740     // Shuffle the operands around so the lane index operand is in the
7741     // right place.
7742     unsigned Spacing;
7743     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7744     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7745     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7746                                             Spacing));
7747     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7748     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7749     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7750     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7751                                             Spacing));
7752     TmpInst.addOperand(Inst.getOperand(1)); // lane
7753     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7754     TmpInst.addOperand(Inst.getOperand(5));
7755     Inst = TmpInst;
7756     return true;
7757   }
7758 
7759   case ARM::VLD3LNdAsm_8:
7760   case ARM::VLD3LNdAsm_16:
7761   case ARM::VLD3LNdAsm_32:
7762   case ARM::VLD3LNqAsm_16:
7763   case ARM::VLD3LNqAsm_32: {
7764     MCInst TmpInst;
7765     // Shuffle the operands around so the lane index operand is in the
7766     // right place.
7767     unsigned Spacing;
7768     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7769     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7770     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7771                                             Spacing));
7772     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7773                                             Spacing * 2));
7774     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7775     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7776     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7777     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7778                                             Spacing));
7779     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7780                                             Spacing * 2));
7781     TmpInst.addOperand(Inst.getOperand(1)); // lane
7782     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7783     TmpInst.addOperand(Inst.getOperand(5));
7784     Inst = TmpInst;
7785     return true;
7786   }
7787 
7788   case ARM::VLD4LNdAsm_8:
7789   case ARM::VLD4LNdAsm_16:
7790   case ARM::VLD4LNdAsm_32:
7791   case ARM::VLD4LNqAsm_16:
7792   case ARM::VLD4LNqAsm_32: {
7793     MCInst TmpInst;
7794     // Shuffle the operands around so the lane index operand is in the
7795     // right place.
7796     unsigned Spacing;
7797     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7798     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7799     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7800                                             Spacing));
7801     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7802                                             Spacing * 2));
7803     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7804                                             Spacing * 3));
7805     TmpInst.addOperand(Inst.getOperand(2)); // Rn
7806     TmpInst.addOperand(Inst.getOperand(3)); // alignment
7807     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7808     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7809                                             Spacing));
7810     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7811                                             Spacing * 2));
7812     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7813                                             Spacing * 3));
7814     TmpInst.addOperand(Inst.getOperand(1)); // lane
7815     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7816     TmpInst.addOperand(Inst.getOperand(5));
7817     Inst = TmpInst;
7818     return true;
7819   }
7820 
7821   // VLD3DUP single 3-element structure to all lanes instructions.
7822   case ARM::VLD3DUPdAsm_8:
7823   case ARM::VLD3DUPdAsm_16:
7824   case ARM::VLD3DUPdAsm_32:
7825   case ARM::VLD3DUPqAsm_8:
7826   case ARM::VLD3DUPqAsm_16:
7827   case ARM::VLD3DUPqAsm_32: {
7828     MCInst TmpInst;
7829     unsigned Spacing;
7830     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7831     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7832     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7833                                             Spacing));
7834     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7835                                             Spacing * 2));
7836     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7837     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7838     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7839     TmpInst.addOperand(Inst.getOperand(4));
7840     Inst = TmpInst;
7841     return true;
7842   }
7843 
7844   case ARM::VLD3DUPdWB_fixed_Asm_8:
7845   case ARM::VLD3DUPdWB_fixed_Asm_16:
7846   case ARM::VLD3DUPdWB_fixed_Asm_32:
7847   case ARM::VLD3DUPqWB_fixed_Asm_8:
7848   case ARM::VLD3DUPqWB_fixed_Asm_16:
7849   case ARM::VLD3DUPqWB_fixed_Asm_32: {
7850     MCInst TmpInst;
7851     unsigned Spacing;
7852     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7853     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7854     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7855                                             Spacing));
7856     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7857                                             Spacing * 2));
7858     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7859     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7860     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7861     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7862     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7863     TmpInst.addOperand(Inst.getOperand(4));
7864     Inst = TmpInst;
7865     return true;
7866   }
7867 
7868   case ARM::VLD3DUPdWB_register_Asm_8:
7869   case ARM::VLD3DUPdWB_register_Asm_16:
7870   case ARM::VLD3DUPdWB_register_Asm_32:
7871   case ARM::VLD3DUPqWB_register_Asm_8:
7872   case ARM::VLD3DUPqWB_register_Asm_16:
7873   case ARM::VLD3DUPqWB_register_Asm_32: {
7874     MCInst TmpInst;
7875     unsigned Spacing;
7876     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7877     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7878     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7879                                             Spacing));
7880     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7881                                             Spacing * 2));
7882     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7883     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7884     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7885     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7886     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7887     TmpInst.addOperand(Inst.getOperand(5));
7888     Inst = TmpInst;
7889     return true;
7890   }
7891 
7892   // VLD3 multiple 3-element structure instructions.
7893   case ARM::VLD3dAsm_8:
7894   case ARM::VLD3dAsm_16:
7895   case ARM::VLD3dAsm_32:
7896   case ARM::VLD3qAsm_8:
7897   case ARM::VLD3qAsm_16:
7898   case ARM::VLD3qAsm_32: {
7899     MCInst TmpInst;
7900     unsigned Spacing;
7901     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7902     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7903     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7904                                             Spacing));
7905     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7906                                             Spacing * 2));
7907     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7908     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7909     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7910     TmpInst.addOperand(Inst.getOperand(4));
7911     Inst = TmpInst;
7912     return true;
7913   }
7914 
7915   case ARM::VLD3dWB_fixed_Asm_8:
7916   case ARM::VLD3dWB_fixed_Asm_16:
7917   case ARM::VLD3dWB_fixed_Asm_32:
7918   case ARM::VLD3qWB_fixed_Asm_8:
7919   case ARM::VLD3qWB_fixed_Asm_16:
7920   case ARM::VLD3qWB_fixed_Asm_32: {
7921     MCInst TmpInst;
7922     unsigned Spacing;
7923     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7924     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7925     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7926                                             Spacing));
7927     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7928                                             Spacing * 2));
7929     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7930     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7931     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7932     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7933     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7934     TmpInst.addOperand(Inst.getOperand(4));
7935     Inst = TmpInst;
7936     return true;
7937   }
7938 
7939   case ARM::VLD3dWB_register_Asm_8:
7940   case ARM::VLD3dWB_register_Asm_16:
7941   case ARM::VLD3dWB_register_Asm_32:
7942   case ARM::VLD3qWB_register_Asm_8:
7943   case ARM::VLD3qWB_register_Asm_16:
7944   case ARM::VLD3qWB_register_Asm_32: {
7945     MCInst TmpInst;
7946     unsigned Spacing;
7947     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7948     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7949     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7950                                             Spacing));
7951     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7952                                             Spacing * 2));
7953     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7954     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7955     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7956     TmpInst.addOperand(Inst.getOperand(3)); // Rm
7957     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7958     TmpInst.addOperand(Inst.getOperand(5));
7959     Inst = TmpInst;
7960     return true;
7961   }
7962 
7963   // VLD4DUP single 3-element structure to all lanes instructions.
7964   case ARM::VLD4DUPdAsm_8:
7965   case ARM::VLD4DUPdAsm_16:
7966   case ARM::VLD4DUPdAsm_32:
7967   case ARM::VLD4DUPqAsm_8:
7968   case ARM::VLD4DUPqAsm_16:
7969   case ARM::VLD4DUPqAsm_32: {
7970     MCInst TmpInst;
7971     unsigned Spacing;
7972     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7973     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7974     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7975                                             Spacing));
7976     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7977                                             Spacing * 2));
7978     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7979                                             Spacing * 3));
7980     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7981     TmpInst.addOperand(Inst.getOperand(2)); // alignment
7982     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7983     TmpInst.addOperand(Inst.getOperand(4));
7984     Inst = TmpInst;
7985     return true;
7986   }
7987 
7988   case ARM::VLD4DUPdWB_fixed_Asm_8:
7989   case ARM::VLD4DUPdWB_fixed_Asm_16:
7990   case ARM::VLD4DUPdWB_fixed_Asm_32:
7991   case ARM::VLD4DUPqWB_fixed_Asm_8:
7992   case ARM::VLD4DUPqWB_fixed_Asm_16:
7993   case ARM::VLD4DUPqWB_fixed_Asm_32: {
7994     MCInst TmpInst;
7995     unsigned Spacing;
7996     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7997     TmpInst.addOperand(Inst.getOperand(0)); // Vd
7998     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7999                                             Spacing));
8000     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8001                                             Spacing * 2));
8002     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8003                                             Spacing * 3));
8004     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8005     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8006     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8007     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8008     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8009     TmpInst.addOperand(Inst.getOperand(4));
8010     Inst = TmpInst;
8011     return true;
8012   }
8013 
8014   case ARM::VLD4DUPdWB_register_Asm_8:
8015   case ARM::VLD4DUPdWB_register_Asm_16:
8016   case ARM::VLD4DUPdWB_register_Asm_32:
8017   case ARM::VLD4DUPqWB_register_Asm_8:
8018   case ARM::VLD4DUPqWB_register_Asm_16:
8019   case ARM::VLD4DUPqWB_register_Asm_32: {
8020     MCInst TmpInst;
8021     unsigned Spacing;
8022     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8023     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8024     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8025                                             Spacing));
8026     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8027                                             Spacing * 2));
8028     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8029                                             Spacing * 3));
8030     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8031     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8032     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8033     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8034     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8035     TmpInst.addOperand(Inst.getOperand(5));
8036     Inst = TmpInst;
8037     return true;
8038   }
8039 
8040   // VLD4 multiple 4-element structure instructions.
8041   case ARM::VLD4dAsm_8:
8042   case ARM::VLD4dAsm_16:
8043   case ARM::VLD4dAsm_32:
8044   case ARM::VLD4qAsm_8:
8045   case ARM::VLD4qAsm_16:
8046   case ARM::VLD4qAsm_32: {
8047     MCInst TmpInst;
8048     unsigned Spacing;
8049     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8050     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8051     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8052                                             Spacing));
8053     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8054                                             Spacing * 2));
8055     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8056                                             Spacing * 3));
8057     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8058     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8059     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8060     TmpInst.addOperand(Inst.getOperand(4));
8061     Inst = TmpInst;
8062     return true;
8063   }
8064 
8065   case ARM::VLD4dWB_fixed_Asm_8:
8066   case ARM::VLD4dWB_fixed_Asm_16:
8067   case ARM::VLD4dWB_fixed_Asm_32:
8068   case ARM::VLD4qWB_fixed_Asm_8:
8069   case ARM::VLD4qWB_fixed_Asm_16:
8070   case ARM::VLD4qWB_fixed_Asm_32: {
8071     MCInst TmpInst;
8072     unsigned Spacing;
8073     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8074     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8075     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8076                                             Spacing));
8077     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8078                                             Spacing * 2));
8079     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8080                                             Spacing * 3));
8081     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8082     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8083     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8084     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8085     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8086     TmpInst.addOperand(Inst.getOperand(4));
8087     Inst = TmpInst;
8088     return true;
8089   }
8090 
8091   case ARM::VLD4dWB_register_Asm_8:
8092   case ARM::VLD4dWB_register_Asm_16:
8093   case ARM::VLD4dWB_register_Asm_32:
8094   case ARM::VLD4qWB_register_Asm_8:
8095   case ARM::VLD4qWB_register_Asm_16:
8096   case ARM::VLD4qWB_register_Asm_32: {
8097     MCInst TmpInst;
8098     unsigned Spacing;
8099     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8100     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8101     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8102                                             Spacing));
8103     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8104                                             Spacing * 2));
8105     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8106                                             Spacing * 3));
8107     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8108     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8109     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8110     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8111     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8112     TmpInst.addOperand(Inst.getOperand(5));
8113     Inst = TmpInst;
8114     return true;
8115   }
8116 
8117   // VST3 multiple 3-element structure instructions.
8118   case ARM::VST3dAsm_8:
8119   case ARM::VST3dAsm_16:
8120   case ARM::VST3dAsm_32:
8121   case ARM::VST3qAsm_8:
8122   case ARM::VST3qAsm_16:
8123   case ARM::VST3qAsm_32: {
8124     MCInst TmpInst;
8125     unsigned Spacing;
8126     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8127     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8128     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8129     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8130     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8131                                             Spacing));
8132     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8133                                             Spacing * 2));
8134     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8135     TmpInst.addOperand(Inst.getOperand(4));
8136     Inst = TmpInst;
8137     return true;
8138   }
8139 
8140   case ARM::VST3dWB_fixed_Asm_8:
8141   case ARM::VST3dWB_fixed_Asm_16:
8142   case ARM::VST3dWB_fixed_Asm_32:
8143   case ARM::VST3qWB_fixed_Asm_8:
8144   case ARM::VST3qWB_fixed_Asm_16:
8145   case ARM::VST3qWB_fixed_Asm_32: {
8146     MCInst TmpInst;
8147     unsigned Spacing;
8148     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8149     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8150     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8151     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8152     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8153     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8154     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8155                                             Spacing));
8156     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8157                                             Spacing * 2));
8158     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8159     TmpInst.addOperand(Inst.getOperand(4));
8160     Inst = TmpInst;
8161     return true;
8162   }
8163 
8164   case ARM::VST3dWB_register_Asm_8:
8165   case ARM::VST3dWB_register_Asm_16:
8166   case ARM::VST3dWB_register_Asm_32:
8167   case ARM::VST3qWB_register_Asm_8:
8168   case ARM::VST3qWB_register_Asm_16:
8169   case ARM::VST3qWB_register_Asm_32: {
8170     MCInst TmpInst;
8171     unsigned Spacing;
8172     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8173     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8174     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8175     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8176     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8177     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8178     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8179                                             Spacing));
8180     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8181                                             Spacing * 2));
8182     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8183     TmpInst.addOperand(Inst.getOperand(5));
8184     Inst = TmpInst;
8185     return true;
8186   }
8187 
8188   // VST4 multiple 3-element structure instructions.
8189   case ARM::VST4dAsm_8:
8190   case ARM::VST4dAsm_16:
8191   case ARM::VST4dAsm_32:
8192   case ARM::VST4qAsm_8:
8193   case ARM::VST4qAsm_16:
8194   case ARM::VST4qAsm_32: {
8195     MCInst TmpInst;
8196     unsigned Spacing;
8197     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8198     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8199     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8200     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8201     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8202                                             Spacing));
8203     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8204                                             Spacing * 2));
8205     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8206                                             Spacing * 3));
8207     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8208     TmpInst.addOperand(Inst.getOperand(4));
8209     Inst = TmpInst;
8210     return true;
8211   }
8212 
8213   case ARM::VST4dWB_fixed_Asm_8:
8214   case ARM::VST4dWB_fixed_Asm_16:
8215   case ARM::VST4dWB_fixed_Asm_32:
8216   case ARM::VST4qWB_fixed_Asm_8:
8217   case ARM::VST4qWB_fixed_Asm_16:
8218   case ARM::VST4qWB_fixed_Asm_32: {
8219     MCInst TmpInst;
8220     unsigned Spacing;
8221     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8222     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8223     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8224     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8225     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8226     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8227     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8228                                             Spacing));
8229     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8230                                             Spacing * 2));
8231     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8232                                             Spacing * 3));
8233     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8234     TmpInst.addOperand(Inst.getOperand(4));
8235     Inst = TmpInst;
8236     return true;
8237   }
8238 
8239   case ARM::VST4dWB_register_Asm_8:
8240   case ARM::VST4dWB_register_Asm_16:
8241   case ARM::VST4dWB_register_Asm_32:
8242   case ARM::VST4qWB_register_Asm_8:
8243   case ARM::VST4qWB_register_Asm_16:
8244   case ARM::VST4qWB_register_Asm_32: {
8245     MCInst TmpInst;
8246     unsigned Spacing;
8247     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8248     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8249     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8250     TmpInst.addOperand(Inst.getOperand(2)); // alignment
8251     TmpInst.addOperand(Inst.getOperand(3)); // Rm
8252     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8253     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8254                                             Spacing));
8255     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8256                                             Spacing * 2));
8257     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8258                                             Spacing * 3));
8259     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8260     TmpInst.addOperand(Inst.getOperand(5));
8261     Inst = TmpInst;
8262     return true;
8263   }
8264 
8265   // Handle encoding choice for the shift-immediate instructions.
8266   case ARM::t2LSLri:
8267   case ARM::t2LSRri:
8268   case ARM::t2ASRri: {
8269     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8270         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8271         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8272         !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8273           static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
8274       unsigned NewOpc;
8275       switch (Inst.getOpcode()) {
8276       default: llvm_unreachable("unexpected opcode");
8277       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
8278       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
8279       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
8280       }
8281       // The Thumb1 operands aren't in the same order. Awesome, eh?
8282       MCInst TmpInst;
8283       TmpInst.setOpcode(NewOpc);
8284       TmpInst.addOperand(Inst.getOperand(0));
8285       TmpInst.addOperand(Inst.getOperand(5));
8286       TmpInst.addOperand(Inst.getOperand(1));
8287       TmpInst.addOperand(Inst.getOperand(2));
8288       TmpInst.addOperand(Inst.getOperand(3));
8289       TmpInst.addOperand(Inst.getOperand(4));
8290       Inst = TmpInst;
8291       return true;
8292     }
8293     return false;
8294   }
8295 
8296   // Handle the Thumb2 mode MOV complex aliases.
8297   case ARM::t2MOVsr:
8298   case ARM::t2MOVSsr: {
8299     // Which instruction to expand to depends on the CCOut operand and
8300     // whether we're in an IT block if the register operands are low
8301     // registers.
8302     bool isNarrow = false;
8303     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8304         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8305         isARMLowRegister(Inst.getOperand(2).getReg()) &&
8306         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8307         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
8308       isNarrow = true;
8309     MCInst TmpInst;
8310     unsigned newOpc;
8311     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
8312     default: llvm_unreachable("unexpected opcode!");
8313     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
8314     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
8315     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
8316     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
8317     }
8318     TmpInst.setOpcode(newOpc);
8319     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8320     if (isNarrow)
8321       TmpInst.addOperand(MCOperand::createReg(
8322           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8323     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8324     TmpInst.addOperand(Inst.getOperand(2)); // Rm
8325     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8326     TmpInst.addOperand(Inst.getOperand(5));
8327     if (!isNarrow)
8328       TmpInst.addOperand(MCOperand::createReg(
8329           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8330     Inst = TmpInst;
8331     return true;
8332   }
8333   case ARM::t2MOVsi:
8334   case ARM::t2MOVSsi: {
8335     // Which instruction to expand to depends on the CCOut operand and
8336     // whether we're in an IT block if the register operands are low
8337     // registers.
8338     bool isNarrow = false;
8339     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8340         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8341         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
8342       isNarrow = true;
8343     MCInst TmpInst;
8344     unsigned newOpc;
8345     unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8346     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
8347     bool isMov = false;
8348     // MOV rd, rm, LSL #0 is actually a MOV instruction
8349     if (Shift == ARM_AM::lsl && Amount == 0) {
8350       isMov = true;
8351       // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of
8352       // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
8353       // unpredictable in an IT block so the 32-bit encoding T3 has to be used
8354       // instead.
8355       if (inITBlock()) {
8356         isNarrow = false;
8357       }
8358       newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr;
8359     } else {
8360       switch(Shift) {
8361       default: llvm_unreachable("unexpected opcode!");
8362       case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
8363       case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
8364       case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
8365       case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
8366       case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
8367       }
8368     }
8369     if (Amount == 32) Amount = 0;
8370     TmpInst.setOpcode(newOpc);
8371     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8372     if (isNarrow && !isMov)
8373       TmpInst.addOperand(MCOperand::createReg(
8374           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8375     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8376     if (newOpc != ARM::t2RRX && !isMov)
8377       TmpInst.addOperand(MCOperand::createImm(Amount));
8378     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8379     TmpInst.addOperand(Inst.getOperand(4));
8380     if (!isNarrow)
8381       TmpInst.addOperand(MCOperand::createReg(
8382           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8383     Inst = TmpInst;
8384     return true;
8385   }
8386   // Handle the ARM mode MOV complex aliases.
8387   case ARM::ASRr:
8388   case ARM::LSRr:
8389   case ARM::LSLr:
8390   case ARM::RORr: {
8391     ARM_AM::ShiftOpc ShiftTy;
8392     switch(Inst.getOpcode()) {
8393     default: llvm_unreachable("unexpected opcode!");
8394     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
8395     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
8396     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
8397     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
8398     }
8399     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
8400     MCInst TmpInst;
8401     TmpInst.setOpcode(ARM::MOVsr);
8402     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8403     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8404     TmpInst.addOperand(Inst.getOperand(2)); // Rm
8405     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8406     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8407     TmpInst.addOperand(Inst.getOperand(4));
8408     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8409     Inst = TmpInst;
8410     return true;
8411   }
8412   case ARM::ASRi:
8413   case ARM::LSRi:
8414   case ARM::LSLi:
8415   case ARM::RORi: {
8416     ARM_AM::ShiftOpc ShiftTy;
8417     switch(Inst.getOpcode()) {
8418     default: llvm_unreachable("unexpected opcode!");
8419     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
8420     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
8421     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
8422     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
8423     }
8424     // A shift by zero is a plain MOVr, not a MOVsi.
8425     unsigned Amt = Inst.getOperand(2).getImm();
8426     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
8427     // A shift by 32 should be encoded as 0 when permitted
8428     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
8429       Amt = 0;
8430     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
8431     MCInst TmpInst;
8432     TmpInst.setOpcode(Opc);
8433     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8434     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8435     if (Opc == ARM::MOVsi)
8436       TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8437     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8438     TmpInst.addOperand(Inst.getOperand(4));
8439     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8440     Inst = TmpInst;
8441     return true;
8442   }
8443   case ARM::RRXi: {
8444     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8445     MCInst TmpInst;
8446     TmpInst.setOpcode(ARM::MOVsi);
8447     TmpInst.addOperand(Inst.getOperand(0)); // Rd
8448     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8449     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8450     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8451     TmpInst.addOperand(Inst.getOperand(3));
8452     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8453     Inst = TmpInst;
8454     return true;
8455   }
8456   case ARM::t2LDMIA_UPD: {
8457     // If this is a load of a single register, then we should use
8458     // a post-indexed LDR instruction instead, per the ARM ARM.
8459     if (Inst.getNumOperands() != 5)
8460       return false;
8461     MCInst TmpInst;
8462     TmpInst.setOpcode(ARM::t2LDR_POST);
8463     TmpInst.addOperand(Inst.getOperand(4)); // Rt
8464     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8465     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8466     TmpInst.addOperand(MCOperand::createImm(4));
8467     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8468     TmpInst.addOperand(Inst.getOperand(3));
8469     Inst = TmpInst;
8470     return true;
8471   }
8472   case ARM::t2STMDB_UPD: {
8473     // If this is a store of a single register, then we should use
8474     // a pre-indexed STR instruction instead, per the ARM ARM.
8475     if (Inst.getNumOperands() != 5)
8476       return false;
8477     MCInst TmpInst;
8478     TmpInst.setOpcode(ARM::t2STR_PRE);
8479     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8480     TmpInst.addOperand(Inst.getOperand(4)); // Rt
8481     TmpInst.addOperand(Inst.getOperand(1)); // Rn
8482     TmpInst.addOperand(MCOperand::createImm(-4));
8483     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8484     TmpInst.addOperand(Inst.getOperand(3));
8485     Inst = TmpInst;
8486     return true;
8487   }
8488   case ARM::LDMIA_UPD:
8489     // If this is a load of a single register via a 'pop', then we should use
8490     // a post-indexed LDR instruction instead, per the ARM ARM.
8491     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8492         Inst.getNumOperands() == 5) {
8493       MCInst TmpInst;
8494       TmpInst.setOpcode(ARM::LDR_POST_IMM);
8495       TmpInst.addOperand(Inst.getOperand(4)); // Rt
8496       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8497       TmpInst.addOperand(Inst.getOperand(1)); // Rn
8498       TmpInst.addOperand(MCOperand::createReg(0));  // am2offset
8499       TmpInst.addOperand(MCOperand::createImm(4));
8500       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8501       TmpInst.addOperand(Inst.getOperand(3));
8502       Inst = TmpInst;
8503       return true;
8504     }
8505     break;
8506   case ARM::STMDB_UPD:
8507     // If this is a store of a single register via a 'push', then we should use
8508     // a pre-indexed STR instruction instead, per the ARM ARM.
8509     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8510         Inst.getNumOperands() == 5) {
8511       MCInst TmpInst;
8512       TmpInst.setOpcode(ARM::STR_PRE_IMM);
8513       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8514       TmpInst.addOperand(Inst.getOperand(4)); // Rt
8515       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8516       TmpInst.addOperand(MCOperand::createImm(-4));
8517       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8518       TmpInst.addOperand(Inst.getOperand(3));
8519       Inst = TmpInst;
8520     }
8521     break;
8522   case ARM::t2ADDri12:
8523     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8524     // mnemonic was used (not "addw"), encoding T3 is preferred.
8525     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8526         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8527       break;
8528     Inst.setOpcode(ARM::t2ADDri);
8529     Inst.addOperand(MCOperand::createReg(0)); // cc_out
8530     break;
8531   case ARM::t2SUBri12:
8532     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8533     // mnemonic was used (not "subw"), encoding T3 is preferred.
8534     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8535         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8536       break;
8537     Inst.setOpcode(ARM::t2SUBri);
8538     Inst.addOperand(MCOperand::createReg(0)); // cc_out
8539     break;
8540   case ARM::tADDi8:
8541     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8542     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8543     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8544     // to encoding T1 if <Rd> is omitted."
8545     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8546       Inst.setOpcode(ARM::tADDi3);
8547       return true;
8548     }
8549     break;
8550   case ARM::tSUBi8:
8551     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8552     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8553     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8554     // to encoding T1 if <Rd> is omitted."
8555     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8556       Inst.setOpcode(ARM::tSUBi3);
8557       return true;
8558     }
8559     break;
8560   case ARM::t2ADDri:
8561   case ARM::t2SUBri: {
8562     // If the destination and first source operand are the same, and
8563     // the flags are compatible with the current IT status, use encoding T2
8564     // instead of T3. For compatibility with the system 'as'. Make sure the
8565     // wide encoding wasn't explicit.
8566     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8567         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8568         (unsigned)Inst.getOperand(2).getImm() > 255 ||
8569         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8570          (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8571         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8572          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8573       break;
8574     MCInst TmpInst;
8575     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8576                       ARM::tADDi8 : ARM::tSUBi8);
8577     TmpInst.addOperand(Inst.getOperand(0));
8578     TmpInst.addOperand(Inst.getOperand(5));
8579     TmpInst.addOperand(Inst.getOperand(0));
8580     TmpInst.addOperand(Inst.getOperand(2));
8581     TmpInst.addOperand(Inst.getOperand(3));
8582     TmpInst.addOperand(Inst.getOperand(4));
8583     Inst = TmpInst;
8584     return true;
8585   }
8586   case ARM::t2ADDrr: {
8587     // If the destination and first source operand are the same, and
8588     // there's no setting of the flags, use encoding T2 instead of T3.
8589     // Note that this is only for ADD, not SUB. This mirrors the system
8590     // 'as' behaviour.  Also take advantage of ADD being commutative.
8591     // Make sure the wide encoding wasn't explicit.
8592     bool Swap = false;
8593     auto DestReg = Inst.getOperand(0).getReg();
8594     bool Transform = DestReg == Inst.getOperand(1).getReg();
8595     if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
8596       Transform = true;
8597       Swap = true;
8598     }
8599     if (!Transform ||
8600         Inst.getOperand(5).getReg() != 0 ||
8601         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8602          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8603       break;
8604     MCInst TmpInst;
8605     TmpInst.setOpcode(ARM::tADDhirr);
8606     TmpInst.addOperand(Inst.getOperand(0));
8607     TmpInst.addOperand(Inst.getOperand(0));
8608     TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
8609     TmpInst.addOperand(Inst.getOperand(3));
8610     TmpInst.addOperand(Inst.getOperand(4));
8611     Inst = TmpInst;
8612     return true;
8613   }
8614   case ARM::tADDrSP: {
8615     // If the non-SP source operand and the destination operand are not the
8616     // same, we need to use the 32-bit encoding if it's available.
8617     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8618       Inst.setOpcode(ARM::t2ADDrr);
8619       Inst.addOperand(MCOperand::createReg(0)); // cc_out
8620       return true;
8621     }
8622     break;
8623   }
8624   case ARM::tB:
8625     // A Thumb conditional branch outside of an IT block is a tBcc.
8626     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8627       Inst.setOpcode(ARM::tBcc);
8628       return true;
8629     }
8630     break;
8631   case ARM::t2B:
8632     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8633     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8634       Inst.setOpcode(ARM::t2Bcc);
8635       return true;
8636     }
8637     break;
8638   case ARM::t2Bcc:
8639     // If the conditional is AL or we're in an IT block, we really want t2B.
8640     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8641       Inst.setOpcode(ARM::t2B);
8642       return true;
8643     }
8644     break;
8645   case ARM::tBcc:
8646     // If the conditional is AL, we really want tB.
8647     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8648       Inst.setOpcode(ARM::tB);
8649       return true;
8650     }
8651     break;
8652   case ARM::tLDMIA: {
8653     // If the register list contains any high registers, or if the writeback
8654     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8655     // instead if we're in Thumb2. Otherwise, this should have generated
8656     // an error in validateInstruction().
8657     unsigned Rn = Inst.getOperand(0).getReg();
8658     bool hasWritebackToken =
8659         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8660          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8661     bool listContainsBase;
8662     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8663         (!listContainsBase && !hasWritebackToken) ||
8664         (listContainsBase && hasWritebackToken)) {
8665       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8666       assert (isThumbTwo());
8667       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8668       // If we're switching to the updating version, we need to insert
8669       // the writeback tied operand.
8670       if (hasWritebackToken)
8671         Inst.insert(Inst.begin(),
8672                     MCOperand::createReg(Inst.getOperand(0).getReg()));
8673       return true;
8674     }
8675     break;
8676   }
8677   case ARM::tSTMIA_UPD: {
8678     // If the register list contains any high registers, we need to use
8679     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8680     // should have generated an error in validateInstruction().
8681     unsigned Rn = Inst.getOperand(0).getReg();
8682     bool listContainsBase;
8683     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8684       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8685       assert (isThumbTwo());
8686       Inst.setOpcode(ARM::t2STMIA_UPD);
8687       return true;
8688     }
8689     break;
8690   }
8691   case ARM::tPOP: {
8692     bool listContainsBase;
8693     // If the register list contains any high registers, we need to use
8694     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8695     // should have generated an error in validateInstruction().
8696     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8697       return false;
8698     assert (isThumbTwo());
8699     Inst.setOpcode(ARM::t2LDMIA_UPD);
8700     // Add the base register and writeback operands.
8701     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8702     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8703     return true;
8704   }
8705   case ARM::tPUSH: {
8706     bool listContainsBase;
8707     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8708       return false;
8709     assert (isThumbTwo());
8710     Inst.setOpcode(ARM::t2STMDB_UPD);
8711     // Add the base register and writeback operands.
8712     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8713     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8714     return true;
8715   }
8716   case ARM::t2MOVi: {
8717     // If we can use the 16-bit encoding and the user didn't explicitly
8718     // request the 32-bit variant, transform it here.
8719     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8720         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8721         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8722           Inst.getOperand(4).getReg() == ARM::CPSR) ||
8723          (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8724         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8725          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8726       // The operands aren't in the same order for tMOVi8...
8727       MCInst TmpInst;
8728       TmpInst.setOpcode(ARM::tMOVi8);
8729       TmpInst.addOperand(Inst.getOperand(0));
8730       TmpInst.addOperand(Inst.getOperand(4));
8731       TmpInst.addOperand(Inst.getOperand(1));
8732       TmpInst.addOperand(Inst.getOperand(2));
8733       TmpInst.addOperand(Inst.getOperand(3));
8734       Inst = TmpInst;
8735       return true;
8736     }
8737     break;
8738   }
8739   case ARM::t2MOVr: {
8740     // If we can use the 16-bit encoding and the user didn't explicitly
8741     // request the 32-bit variant, transform it here.
8742     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8743         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8744         Inst.getOperand(2).getImm() == ARMCC::AL &&
8745         Inst.getOperand(4).getReg() == ARM::CPSR &&
8746         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8747          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8748       // The operands aren't the same for tMOV[S]r... (no cc_out)
8749       MCInst TmpInst;
8750       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8751       TmpInst.addOperand(Inst.getOperand(0));
8752       TmpInst.addOperand(Inst.getOperand(1));
8753       TmpInst.addOperand(Inst.getOperand(2));
8754       TmpInst.addOperand(Inst.getOperand(3));
8755       Inst = TmpInst;
8756       return true;
8757     }
8758     break;
8759   }
8760   case ARM::t2SXTH:
8761   case ARM::t2SXTB:
8762   case ARM::t2UXTH:
8763   case ARM::t2UXTB: {
8764     // If we can use the 16-bit encoding and the user didn't explicitly
8765     // request the 32-bit variant, transform it here.
8766     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8767         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8768         Inst.getOperand(2).getImm() == 0 &&
8769         (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8770          static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8771       unsigned NewOpc;
8772       switch (Inst.getOpcode()) {
8773       default: llvm_unreachable("Illegal opcode!");
8774       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8775       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8776       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8777       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8778       }
8779       // The operands aren't the same for thumb1 (no rotate operand).
8780       MCInst TmpInst;
8781       TmpInst.setOpcode(NewOpc);
8782       TmpInst.addOperand(Inst.getOperand(0));
8783       TmpInst.addOperand(Inst.getOperand(1));
8784       TmpInst.addOperand(Inst.getOperand(3));
8785       TmpInst.addOperand(Inst.getOperand(4));
8786       Inst = TmpInst;
8787       return true;
8788     }
8789     break;
8790   }
8791   case ARM::MOVsi: {
8792     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8793     // rrx shifts and asr/lsr of #32 is encoded as 0
8794     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8795       return false;
8796     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8797       // Shifting by zero is accepted as a vanilla 'MOVr'
8798       MCInst TmpInst;
8799       TmpInst.setOpcode(ARM::MOVr);
8800       TmpInst.addOperand(Inst.getOperand(0));
8801       TmpInst.addOperand(Inst.getOperand(1));
8802       TmpInst.addOperand(Inst.getOperand(3));
8803       TmpInst.addOperand(Inst.getOperand(4));
8804       TmpInst.addOperand(Inst.getOperand(5));
8805       Inst = TmpInst;
8806       return true;
8807     }
8808     return false;
8809   }
8810   case ARM::ANDrsi:
8811   case ARM::ORRrsi:
8812   case ARM::EORrsi:
8813   case ARM::BICrsi:
8814   case ARM::SUBrsi:
8815   case ARM::ADDrsi: {
8816     unsigned newOpc;
8817     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8818     if (SOpc == ARM_AM::rrx) return false;
8819     switch (Inst.getOpcode()) {
8820     default: llvm_unreachable("unexpected opcode!");
8821     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8822     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8823     case ARM::EORrsi: newOpc = ARM::EORrr; break;
8824     case ARM::BICrsi: newOpc = ARM::BICrr; break;
8825     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8826     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8827     }
8828     // If the shift is by zero, use the non-shifted instruction definition.
8829     // The exception is for right shifts, where 0 == 32
8830     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8831         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8832       MCInst TmpInst;
8833       TmpInst.setOpcode(newOpc);
8834       TmpInst.addOperand(Inst.getOperand(0));
8835       TmpInst.addOperand(Inst.getOperand(1));
8836       TmpInst.addOperand(Inst.getOperand(2));
8837       TmpInst.addOperand(Inst.getOperand(4));
8838       TmpInst.addOperand(Inst.getOperand(5));
8839       TmpInst.addOperand(Inst.getOperand(6));
8840       Inst = TmpInst;
8841       return true;
8842     }
8843     return false;
8844   }
8845   case ARM::ITasm:
8846   case ARM::t2IT: {
8847     MCOperand &MO = Inst.getOperand(1);
8848     unsigned Mask = MO.getImm();
8849     ARMCC::CondCodes Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8850 
8851     // Set up the IT block state according to the IT instruction we just
8852     // matched.
8853     assert(!inITBlock() && "nested IT blocks?!");
8854     startExplicitITBlock(Cond, Mask);
8855     MO.setImm(getITMaskEncoding());
8856     break;
8857   }
8858   case ARM::t2LSLrr:
8859   case ARM::t2LSRrr:
8860   case ARM::t2ASRrr:
8861   case ARM::t2SBCrr:
8862   case ARM::t2RORrr:
8863   case ARM::t2BICrr:
8864   {
8865     // Assemblers should use the narrow encodings of these instructions when permissible.
8866     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8867          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8868         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8869         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8870          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8871         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8872          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8873              ".w"))) {
8874       unsigned NewOpc;
8875       switch (Inst.getOpcode()) {
8876         default: llvm_unreachable("unexpected opcode");
8877         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8878         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8879         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8880         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8881         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8882         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8883       }
8884       MCInst TmpInst;
8885       TmpInst.setOpcode(NewOpc);
8886       TmpInst.addOperand(Inst.getOperand(0));
8887       TmpInst.addOperand(Inst.getOperand(5));
8888       TmpInst.addOperand(Inst.getOperand(1));
8889       TmpInst.addOperand(Inst.getOperand(2));
8890       TmpInst.addOperand(Inst.getOperand(3));
8891       TmpInst.addOperand(Inst.getOperand(4));
8892       Inst = TmpInst;
8893       return true;
8894     }
8895     return false;
8896   }
8897   case ARM::t2ANDrr:
8898   case ARM::t2EORrr:
8899   case ARM::t2ADCrr:
8900   case ARM::t2ORRrr:
8901   {
8902     // Assemblers should use the narrow encodings of these instructions when permissible.
8903     // These instructions are special in that they are commutable, so shorter encodings
8904     // are available more often.
8905     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8906          isARMLowRegister(Inst.getOperand(2).getReg())) &&
8907         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8908          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8909         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8910          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8911         (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8912          !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8913              ".w"))) {
8914       unsigned NewOpc;
8915       switch (Inst.getOpcode()) {
8916         default: llvm_unreachable("unexpected opcode");
8917         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8918         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8919         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8920         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8921       }
8922       MCInst TmpInst;
8923       TmpInst.setOpcode(NewOpc);
8924       TmpInst.addOperand(Inst.getOperand(0));
8925       TmpInst.addOperand(Inst.getOperand(5));
8926       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8927         TmpInst.addOperand(Inst.getOperand(1));
8928         TmpInst.addOperand(Inst.getOperand(2));
8929       } else {
8930         TmpInst.addOperand(Inst.getOperand(2));
8931         TmpInst.addOperand(Inst.getOperand(1));
8932       }
8933       TmpInst.addOperand(Inst.getOperand(3));
8934       TmpInst.addOperand(Inst.getOperand(4));
8935       Inst = TmpInst;
8936       return true;
8937     }
8938     return false;
8939   }
8940   }
8941   return false;
8942 }
8943 
8944 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8945   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8946   // suffix depending on whether they're in an IT block or not.
8947   unsigned Opc = Inst.getOpcode();
8948   const MCInstrDesc &MCID = MII.get(Opc);
8949   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8950     assert(MCID.hasOptionalDef() &&
8951            "optionally flag setting instruction missing optional def operand");
8952     assert(MCID.NumOperands == Inst.getNumOperands() &&
8953            "operand count mismatch!");
8954     // Find the optional-def operand (cc_out).
8955     unsigned OpNo;
8956     for (OpNo = 0;
8957          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8958          ++OpNo)
8959       ;
8960     // If we're parsing Thumb1, reject it completely.
8961     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8962       return Match_RequiresFlagSetting;
8963     // If we're parsing Thumb2, which form is legal depends on whether we're
8964     // in an IT block.
8965     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8966         !inITBlock())
8967       return Match_RequiresITBlock;
8968     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8969         inITBlock())
8970       return Match_RequiresNotITBlock;
8971     // LSL with zero immediate is not allowed in an IT block
8972     if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
8973       return Match_RequiresNotITBlock;
8974   } else if (isThumbOne()) {
8975     // Some high-register supporting Thumb1 encodings only allow both registers
8976     // to be from r0-r7 when in Thumb2.
8977     if (Opc == ARM::tADDhirr && !hasV6MOps() &&
8978         isARMLowRegister(Inst.getOperand(1).getReg()) &&
8979         isARMLowRegister(Inst.getOperand(2).getReg()))
8980       return Match_RequiresThumb2;
8981     // Others only require ARMv6 or later.
8982     else if (Opc == ARM::tMOVr && !hasV6Ops() &&
8983              isARMLowRegister(Inst.getOperand(0).getReg()) &&
8984              isARMLowRegister(Inst.getOperand(1).getReg()))
8985       return Match_RequiresV6;
8986   }
8987 
8988   // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
8989   // than the loop below can handle, so it uses the GPRnopc register class and
8990   // we do SP handling here.
8991   if (Opc == ARM::t2MOVr && !hasV8Ops())
8992   {
8993     // SP as both source and destination is not allowed
8994     if (Inst.getOperand(0).getReg() == ARM::SP &&
8995         Inst.getOperand(1).getReg() == ARM::SP)
8996       return Match_RequiresV8;
8997     // When flags-setting SP as either source or destination is not allowed
8998     if (Inst.getOperand(4).getReg() == ARM::CPSR &&
8999         (Inst.getOperand(0).getReg() == ARM::SP ||
9000          Inst.getOperand(1).getReg() == ARM::SP))
9001       return Match_RequiresV8;
9002   }
9003 
9004   for (unsigned I = 0; I < MCID.NumOperands; ++I)
9005     if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
9006       // rGPRRegClass excludes PC, and also excluded SP before ARMv8
9007       if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
9008         return Match_RequiresV8;
9009       else if (Inst.getOperand(I).getReg() == ARM::PC)
9010         return Match_InvalidOperand;
9011     }
9012 
9013   return Match_Success;
9014 }
9015 
9016 namespace llvm {
9017 template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
9018   return true; // In an assembly source, no need to second-guess
9019 }
9020 }
9021 
9022 // Returns true if Inst is unpredictable if it is in and IT block, but is not
9023 // the last instruction in the block.
9024 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
9025   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9026 
9027   // All branch & call instructions terminate IT blocks.
9028   if (MCID.isTerminator() || MCID.isCall() || MCID.isReturn() ||
9029       MCID.isBranch() || MCID.isIndirectBranch())
9030     return true;
9031 
9032   // Any arithmetic instruction which writes to the PC also terminates the IT
9033   // block.
9034   for (unsigned OpIdx = 0; OpIdx < MCID.getNumDefs(); ++OpIdx) {
9035     MCOperand &Op = Inst.getOperand(OpIdx);
9036     if (Op.isReg() && Op.getReg() == ARM::PC)
9037       return true;
9038   }
9039 
9040   if (MCID.hasImplicitDefOfPhysReg(ARM::PC, MRI))
9041     return true;
9042 
9043   // Instructions with variable operand lists, which write to the variable
9044   // operands. We only care about Thumb instructions here, as ARM instructions
9045   // obviously can't be in an IT block.
9046   switch (Inst.getOpcode()) {
9047   case ARM::tLDMIA:
9048   case ARM::t2LDMIA:
9049   case ARM::t2LDMIA_UPD:
9050   case ARM::t2LDMDB:
9051   case ARM::t2LDMDB_UPD:
9052     if (listContainsReg(Inst, 3, ARM::PC))
9053       return true;
9054     break;
9055   case ARM::tPOP:
9056     if (listContainsReg(Inst, 2, ARM::PC))
9057       return true;
9058     break;
9059   }
9060 
9061   return false;
9062 }
9063 
9064 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
9065                                           uint64_t &ErrorInfo,
9066                                           bool MatchingInlineAsm,
9067                                           bool &EmitInITBlock,
9068                                           MCStreamer &Out) {
9069   // If we can't use an implicit IT block here, just match as normal.
9070   if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
9071     return MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
9072 
9073   // Try to match the instruction in an extension of the current IT block (if
9074   // there is one).
9075   if (inImplicitITBlock()) {
9076     extendImplicitITBlock(ITState.Cond);
9077     if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) ==
9078             Match_Success) {
9079       // The match succeded, but we still have to check that the instruction is
9080       // valid in this implicit IT block.
9081       const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9082       if (MCID.isPredicable()) {
9083         ARMCC::CondCodes InstCond =
9084             (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9085                 .getImm();
9086         ARMCC::CondCodes ITCond = currentITCond();
9087         if (InstCond == ITCond) {
9088           EmitInITBlock = true;
9089           return Match_Success;
9090         } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
9091           invertCurrentITCondition();
9092           EmitInITBlock = true;
9093           return Match_Success;
9094         }
9095       }
9096     }
9097     rewindImplicitITPosition();
9098   }
9099 
9100   // Finish the current IT block, and try to match outside any IT block.
9101   flushPendingInstructions(Out);
9102   unsigned PlainMatchResult =
9103       MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
9104   if (PlainMatchResult == Match_Success) {
9105     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9106     if (MCID.isPredicable()) {
9107       ARMCC::CondCodes InstCond =
9108           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9109               .getImm();
9110       // Some forms of the branch instruction have their own condition code
9111       // fields, so can be conditionally executed without an IT block.
9112       if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
9113         EmitInITBlock = false;
9114         return Match_Success;
9115       }
9116       if (InstCond == ARMCC::AL) {
9117         EmitInITBlock = false;
9118         return Match_Success;
9119       }
9120     } else {
9121       EmitInITBlock = false;
9122       return Match_Success;
9123     }
9124   }
9125 
9126   // Try to match in a new IT block. The matcher doesn't check the actual
9127   // condition, so we create an IT block with a dummy condition, and fix it up
9128   // once we know the actual condition.
9129   startImplicitITBlock();
9130   if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) ==
9131       Match_Success) {
9132     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
9133     if (MCID.isPredicable()) {
9134       ITState.Cond =
9135           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
9136               .getImm();
9137       EmitInITBlock = true;
9138       return Match_Success;
9139     }
9140   }
9141   discardImplicitITBlock();
9142 
9143   // If none of these succeed, return the error we got when trying to match
9144   // outside any IT blocks.
9145   EmitInITBlock = false;
9146   return PlainMatchResult;
9147 }
9148 
9149 static const char *getSubtargetFeatureName(uint64_t Val);
9150 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
9151                                            OperandVector &Operands,
9152                                            MCStreamer &Out, uint64_t &ErrorInfo,
9153                                            bool MatchingInlineAsm) {
9154   MCInst Inst;
9155   unsigned MatchResult;
9156   bool PendConditionalInstruction = false;
9157 
9158   MatchResult = MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm,
9159                                  PendConditionalInstruction, Out);
9160 
9161   switch (MatchResult) {
9162   case Match_Success:
9163     // Context sensitive operand constraints aren't handled by the matcher,
9164     // so check them here.
9165     if (validateInstruction(Inst, Operands)) {
9166       // Still progress the IT block, otherwise one wrong condition causes
9167       // nasty cascading errors.
9168       forwardITPosition();
9169       return true;
9170     }
9171 
9172     { // processInstruction() updates inITBlock state, we need to save it away
9173       bool wasInITBlock = inITBlock();
9174 
9175       // Some instructions need post-processing to, for example, tweak which
9176       // encoding is selected. Loop on it while changes happen so the
9177       // individual transformations can chain off each other. E.g.,
9178       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
9179       while (processInstruction(Inst, Operands, Out))
9180         ;
9181 
9182       // Only after the instruction is fully processed, we can validate it
9183       if (wasInITBlock && hasV8Ops() && isThumb() &&
9184           !isV8EligibleForIT(&Inst)) {
9185         Warning(IDLoc, "deprecated instruction in IT block");
9186       }
9187     }
9188 
9189     // Only move forward at the very end so that everything in validate
9190     // and process gets a consistent answer about whether we're in an IT
9191     // block.
9192     forwardITPosition();
9193 
9194     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
9195     // doesn't actually encode.
9196     if (Inst.getOpcode() == ARM::ITasm)
9197       return false;
9198 
9199     Inst.setLoc(IDLoc);
9200     if (PendConditionalInstruction) {
9201       PendingConditionalInsts.push_back(Inst);
9202       if (isITBlockFull() || isITBlockTerminator(Inst))
9203         flushPendingInstructions(Out);
9204     } else {
9205       Out.EmitInstruction(Inst, getSTI());
9206     }
9207     return false;
9208   case Match_MissingFeature: {
9209     assert(ErrorInfo && "Unknown missing feature!");
9210     // Special case the error message for the very common case where only
9211     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
9212     std::string Msg = "instruction requires:";
9213     uint64_t Mask = 1;
9214     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
9215       if (ErrorInfo & Mask) {
9216         Msg += " ";
9217         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
9218       }
9219       Mask <<= 1;
9220     }
9221     return Error(IDLoc, Msg);
9222   }
9223   case Match_InvalidOperand: {
9224     SMLoc ErrorLoc = IDLoc;
9225     if (ErrorInfo != ~0ULL) {
9226       if (ErrorInfo >= Operands.size())
9227         return Error(IDLoc, "too few operands for instruction");
9228 
9229       ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
9230       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9231     }
9232 
9233     return Error(ErrorLoc, "invalid operand for instruction");
9234   }
9235   case Match_MnemonicFail:
9236     return Error(IDLoc, "invalid instruction",
9237                  ((ARMOperand &)*Operands[0]).getLocRange());
9238   case Match_RequiresNotITBlock:
9239     return Error(IDLoc, "flag setting instruction only valid outside IT block");
9240   case Match_RequiresITBlock:
9241     return Error(IDLoc, "instruction only valid inside IT block");
9242   case Match_RequiresV6:
9243     return Error(IDLoc, "instruction variant requires ARMv6 or later");
9244   case Match_RequiresThumb2:
9245     return Error(IDLoc, "instruction variant requires Thumb2");
9246   case Match_RequiresV8:
9247     return Error(IDLoc, "instruction variant requires ARMv8 or later");
9248   case Match_RequiresFlagSetting:
9249     return Error(IDLoc, "no flag-preserving variant of this instruction available");
9250   case Match_ImmRange0_15: {
9251     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
9252     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9253     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
9254   }
9255   case Match_ImmRange0_239: {
9256     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
9257     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9258     return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
9259   }
9260   case Match_AlignedMemoryRequiresNone:
9261   case Match_DupAlignedMemoryRequiresNone:
9262   case Match_AlignedMemoryRequires16:
9263   case Match_DupAlignedMemoryRequires16:
9264   case Match_AlignedMemoryRequires32:
9265   case Match_DupAlignedMemoryRequires32:
9266   case Match_AlignedMemoryRequires64:
9267   case Match_DupAlignedMemoryRequires64:
9268   case Match_AlignedMemoryRequires64or128:
9269   case Match_DupAlignedMemoryRequires64or128:
9270   case Match_AlignedMemoryRequires64or128or256:
9271   {
9272     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
9273     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
9274     switch (MatchResult) {
9275       default:
9276         llvm_unreachable("Missing Match_Aligned type");
9277       case Match_AlignedMemoryRequiresNone:
9278       case Match_DupAlignedMemoryRequiresNone:
9279         return Error(ErrorLoc, "alignment must be omitted");
9280       case Match_AlignedMemoryRequires16:
9281       case Match_DupAlignedMemoryRequires16:
9282         return Error(ErrorLoc, "alignment must be 16 or omitted");
9283       case Match_AlignedMemoryRequires32:
9284       case Match_DupAlignedMemoryRequires32:
9285         return Error(ErrorLoc, "alignment must be 32 or omitted");
9286       case Match_AlignedMemoryRequires64:
9287       case Match_DupAlignedMemoryRequires64:
9288         return Error(ErrorLoc, "alignment must be 64 or omitted");
9289       case Match_AlignedMemoryRequires64or128:
9290       case Match_DupAlignedMemoryRequires64or128:
9291         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
9292       case Match_AlignedMemoryRequires64or128or256:
9293         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
9294     }
9295   }
9296   }
9297 
9298   llvm_unreachable("Implement any new match types added!");
9299 }
9300 
9301 /// parseDirective parses the arm specific directives
9302 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
9303   const MCObjectFileInfo::Environment Format =
9304     getContext().getObjectFileInfo()->getObjectFileType();
9305   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
9306   bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
9307 
9308   StringRef IDVal = DirectiveID.getIdentifier();
9309   if (IDVal == ".word")
9310     parseLiteralValues(4, DirectiveID.getLoc());
9311   else if (IDVal == ".short" || IDVal == ".hword")
9312     parseLiteralValues(2, DirectiveID.getLoc());
9313   else if (IDVal == ".thumb")
9314     parseDirectiveThumb(DirectiveID.getLoc());
9315   else if (IDVal == ".arm")
9316     parseDirectiveARM(DirectiveID.getLoc());
9317   else if (IDVal == ".thumb_func")
9318     parseDirectiveThumbFunc(DirectiveID.getLoc());
9319   else if (IDVal == ".code")
9320     parseDirectiveCode(DirectiveID.getLoc());
9321   else if (IDVal == ".syntax")
9322     parseDirectiveSyntax(DirectiveID.getLoc());
9323   else if (IDVal == ".unreq")
9324     parseDirectiveUnreq(DirectiveID.getLoc());
9325   else if (IDVal == ".fnend")
9326     parseDirectiveFnEnd(DirectiveID.getLoc());
9327   else if (IDVal == ".cantunwind")
9328     parseDirectiveCantUnwind(DirectiveID.getLoc());
9329   else if (IDVal == ".personality")
9330     parseDirectivePersonality(DirectiveID.getLoc());
9331   else if (IDVal == ".handlerdata")
9332     parseDirectiveHandlerData(DirectiveID.getLoc());
9333   else if (IDVal == ".setfp")
9334     parseDirectiveSetFP(DirectiveID.getLoc());
9335   else if (IDVal == ".pad")
9336     parseDirectivePad(DirectiveID.getLoc());
9337   else if (IDVal == ".save")
9338     parseDirectiveRegSave(DirectiveID.getLoc(), false);
9339   else if (IDVal == ".vsave")
9340     parseDirectiveRegSave(DirectiveID.getLoc(), true);
9341   else if (IDVal == ".ltorg" || IDVal == ".pool")
9342     parseDirectiveLtorg(DirectiveID.getLoc());
9343   else if (IDVal == ".even")
9344     parseDirectiveEven(DirectiveID.getLoc());
9345   else if (IDVal == ".personalityindex")
9346     parseDirectivePersonalityIndex(DirectiveID.getLoc());
9347   else if (IDVal == ".unwind_raw")
9348     parseDirectiveUnwindRaw(DirectiveID.getLoc());
9349   else if (IDVal == ".movsp")
9350     parseDirectiveMovSP(DirectiveID.getLoc());
9351   else if (IDVal == ".arch_extension")
9352     parseDirectiveArchExtension(DirectiveID.getLoc());
9353   else if (IDVal == ".align")
9354     return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
9355   else if (IDVal == ".thumb_set")
9356     parseDirectiveThumbSet(DirectiveID.getLoc());
9357   else if (!IsMachO && !IsCOFF) {
9358     if (IDVal == ".arch")
9359       parseDirectiveArch(DirectiveID.getLoc());
9360     else if (IDVal == ".cpu")
9361       parseDirectiveCPU(DirectiveID.getLoc());
9362     else if (IDVal == ".eabi_attribute")
9363       parseDirectiveEabiAttr(DirectiveID.getLoc());
9364     else if (IDVal == ".fpu")
9365       parseDirectiveFPU(DirectiveID.getLoc());
9366     else if (IDVal == ".fnstart")
9367       parseDirectiveFnStart(DirectiveID.getLoc());
9368     else if (IDVal == ".inst")
9369       parseDirectiveInst(DirectiveID.getLoc());
9370     else if (IDVal == ".inst.n")
9371       parseDirectiveInst(DirectiveID.getLoc(), 'n');
9372     else if (IDVal == ".inst.w")
9373       parseDirectiveInst(DirectiveID.getLoc(), 'w');
9374     else if (IDVal == ".object_arch")
9375       parseDirectiveObjectArch(DirectiveID.getLoc());
9376     else if (IDVal == ".tlsdescseq")
9377       parseDirectiveTLSDescSeq(DirectiveID.getLoc());
9378     else
9379       return true;
9380   } else
9381     return true;
9382   return false;
9383 }
9384 
9385 /// parseLiteralValues
9386 ///  ::= .hword expression [, expression]*
9387 ///  ::= .short expression [, expression]*
9388 ///  ::= .word expression [, expression]*
9389 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
9390   auto parseOne = [&]() -> bool {
9391     const MCExpr *Value;
9392     if (getParser().parseExpression(Value))
9393       return true;
9394     getParser().getStreamer().EmitValue(Value, Size, L);
9395     return false;
9396   };
9397   return (parseMany(parseOne));
9398 }
9399 
9400 /// parseDirectiveThumb
9401 ///  ::= .thumb
9402 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
9403   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
9404       check(!hasThumb(), L, "target does not support Thumb mode"))
9405     return true;
9406 
9407   if (!isThumb())
9408     SwitchMode();
9409 
9410   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9411   return false;
9412 }
9413 
9414 /// parseDirectiveARM
9415 ///  ::= .arm
9416 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
9417   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
9418       check(!hasARM(), L, "target does not support ARM mode"))
9419     return true;
9420 
9421   if (isThumb())
9422     SwitchMode();
9423   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9424   return false;
9425 }
9426 
9427 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
9428   // We need to flush the current implicit IT block on a label, because it is
9429   // not legal to branch into an IT block.
9430   flushPendingInstructions(getStreamer());
9431   if (NextSymbolIsThumb) {
9432     getParser().getStreamer().EmitThumbFunc(Symbol);
9433     NextSymbolIsThumb = false;
9434   }
9435 }
9436 
9437 /// parseDirectiveThumbFunc
9438 ///  ::= .thumbfunc symbol_name
9439 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
9440   MCAsmParser &Parser = getParser();
9441   const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
9442   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
9443 
9444   // Darwin asm has (optionally) function name after .thumb_func direction
9445   // ELF doesn't
9446 
9447   if (IsMachO) {
9448     if (Parser.getTok().is(AsmToken::Identifier) ||
9449         Parser.getTok().is(AsmToken::String)) {
9450       MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
9451           Parser.getTok().getIdentifier());
9452       getParser().getStreamer().EmitThumbFunc(Func);
9453       Parser.Lex();
9454       if (parseToken(AsmToken::EndOfStatement,
9455                      "unexpected token in '.thumb_func' directive"))
9456         return true;
9457       return false;
9458     }
9459   }
9460 
9461   if (parseToken(AsmToken::EndOfStatement,
9462                  "unexpected token in '.thumb_func' directive"))
9463     return true;
9464 
9465   NextSymbolIsThumb = true;
9466   return false;
9467 }
9468 
9469 /// parseDirectiveSyntax
9470 ///  ::= .syntax unified | divided
9471 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
9472   MCAsmParser &Parser = getParser();
9473   const AsmToken &Tok = Parser.getTok();
9474   if (Tok.isNot(AsmToken::Identifier)) {
9475     Error(L, "unexpected token in .syntax directive");
9476     return false;
9477   }
9478 
9479   StringRef Mode = Tok.getString();
9480   Parser.Lex();
9481   if (check(Mode == "divided" || Mode == "DIVIDED", L,
9482             "'.syntax divided' arm assembly not supported") ||
9483       check(Mode != "unified" && Mode != "UNIFIED", L,
9484             "unrecognized syntax mode in .syntax directive") ||
9485       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9486     return true;
9487 
9488   // TODO tell the MC streamer the mode
9489   // getParser().getStreamer().Emit???();
9490   return false;
9491 }
9492 
9493 /// parseDirectiveCode
9494 ///  ::= .code 16 | 32
9495 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
9496   MCAsmParser &Parser = getParser();
9497   const AsmToken &Tok = Parser.getTok();
9498   if (Tok.isNot(AsmToken::Integer))
9499     return Error(L, "unexpected token in .code directive");
9500   int64_t Val = Parser.getTok().getIntVal();
9501   if (Val != 16 && Val != 32) {
9502     Error(L, "invalid operand to .code directive");
9503     return false;
9504   }
9505   Parser.Lex();
9506 
9507   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9508     return true;
9509 
9510   if (Val == 16) {
9511     if (!hasThumb())
9512       return Error(L, "target does not support Thumb mode");
9513 
9514     if (!isThumb())
9515       SwitchMode();
9516     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9517   } else {
9518     if (!hasARM())
9519       return Error(L, "target does not support ARM mode");
9520 
9521     if (isThumb())
9522       SwitchMode();
9523     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9524   }
9525 
9526   return false;
9527 }
9528 
9529 /// parseDirectiveReq
9530 ///  ::= name .req registername
9531 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
9532   MCAsmParser &Parser = getParser();
9533   Parser.Lex(); // Eat the '.req' token.
9534   unsigned Reg;
9535   SMLoc SRegLoc, ERegLoc;
9536   if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
9537             "register name expected") ||
9538       parseToken(AsmToken::EndOfStatement,
9539                  "unexpected input in .req directive."))
9540     return true;
9541 
9542   if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
9543     return Error(SRegLoc,
9544                  "redefinition of '" + Name + "' does not match original.");
9545 
9546   return false;
9547 }
9548 
9549 /// parseDirectiveUneq
9550 ///  ::= .unreq registername
9551 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9552   MCAsmParser &Parser = getParser();
9553   if (Parser.getTok().isNot(AsmToken::Identifier))
9554     return Error(L, "unexpected input in .unreq directive.");
9555   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9556   Parser.Lex(); // Eat the identifier.
9557   if (parseToken(AsmToken::EndOfStatement,
9558                  "unexpected input in '.unreq' directive"))
9559     return true;
9560   return false;
9561 }
9562 
9563 // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
9564 // before, if supported by the new target, or emit mapping symbols for the mode
9565 // switch.
9566 void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
9567   if (WasThumb != isThumb()) {
9568     if (WasThumb && hasThumb()) {
9569       // Stay in Thumb mode
9570       SwitchMode();
9571     } else if (!WasThumb && hasARM()) {
9572       // Stay in ARM mode
9573       SwitchMode();
9574     } else {
9575       // Mode switch forced, because the new arch doesn't support the old mode.
9576       getParser().getStreamer().EmitAssemblerFlag(isThumb() ? MCAF_Code16
9577                                                             : MCAF_Code32);
9578       // Warn about the implcit mode switch. GAS does not switch modes here,
9579       // but instead stays in the old mode, reporting an error on any following
9580       // instructions as the mode does not exist on the target.
9581       Warning(Loc, Twine("new target does not support ") +
9582                        (WasThumb ? "thumb" : "arm") + " mode, switching to " +
9583                        (!WasThumb ? "thumb" : "arm") + " mode");
9584     }
9585   }
9586 }
9587 
9588 /// parseDirectiveArch
9589 ///  ::= .arch token
9590 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9591   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9592   unsigned ID = ARM::parseArch(Arch);
9593 
9594   if (ID == ARM::AK_INVALID)
9595     return Error(L, "Unknown arch name");
9596 
9597   bool WasThumb = isThumb();
9598   Triple T;
9599   MCSubtargetInfo &STI = copySTI();
9600   STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
9601   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9602   FixModeAfterArchChange(WasThumb, L);
9603 
9604   getTargetStreamer().emitArch(ID);
9605   return false;
9606 }
9607 
9608 /// parseDirectiveEabiAttr
9609 ///  ::= .eabi_attribute int, int [, "str"]
9610 ///  ::= .eabi_attribute Tag_name, int [, "str"]
9611 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9612   MCAsmParser &Parser = getParser();
9613   int64_t Tag;
9614   SMLoc TagLoc;
9615   TagLoc = Parser.getTok().getLoc();
9616   if (Parser.getTok().is(AsmToken::Identifier)) {
9617     StringRef Name = Parser.getTok().getIdentifier();
9618     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9619     if (Tag == -1) {
9620       Error(TagLoc, "attribute name not recognised: " + Name);
9621       return false;
9622     }
9623     Parser.Lex();
9624   } else {
9625     const MCExpr *AttrExpr;
9626 
9627     TagLoc = Parser.getTok().getLoc();
9628     if (Parser.parseExpression(AttrExpr))
9629       return true;
9630 
9631     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9632     if (check(!CE, TagLoc, "expected numeric constant"))
9633       return true;
9634 
9635     Tag = CE->getValue();
9636   }
9637 
9638   if (Parser.parseToken(AsmToken::Comma, "comma expected"))
9639     return true;
9640 
9641   StringRef StringValue = "";
9642   bool IsStringValue = false;
9643 
9644   int64_t IntegerValue = 0;
9645   bool IsIntegerValue = false;
9646 
9647   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9648     IsStringValue = true;
9649   else if (Tag == ARMBuildAttrs::compatibility) {
9650     IsStringValue = true;
9651     IsIntegerValue = true;
9652   } else if (Tag < 32 || Tag % 2 == 0)
9653     IsIntegerValue = true;
9654   else if (Tag % 2 == 1)
9655     IsStringValue = true;
9656   else
9657     llvm_unreachable("invalid tag type");
9658 
9659   if (IsIntegerValue) {
9660     const MCExpr *ValueExpr;
9661     SMLoc ValueExprLoc = Parser.getTok().getLoc();
9662     if (Parser.parseExpression(ValueExpr))
9663       return true;
9664 
9665     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9666     if (!CE)
9667       return Error(ValueExprLoc, "expected numeric constant");
9668     IntegerValue = CE->getValue();
9669   }
9670 
9671   if (Tag == ARMBuildAttrs::compatibility) {
9672     if (Parser.parseToken(AsmToken::Comma, "comma expected"))
9673       return true;
9674   }
9675 
9676   if (IsStringValue) {
9677     if (Parser.getTok().isNot(AsmToken::String))
9678       return Error(Parser.getTok().getLoc(), "bad string constant");
9679 
9680     StringValue = Parser.getTok().getStringContents();
9681     Parser.Lex();
9682   }
9683 
9684   if (Parser.parseToken(AsmToken::EndOfStatement,
9685                         "unexpected token in '.eabi_attribute' directive"))
9686     return true;
9687 
9688   if (IsIntegerValue && IsStringValue) {
9689     assert(Tag == ARMBuildAttrs::compatibility);
9690     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9691   } else if (IsIntegerValue)
9692     getTargetStreamer().emitAttribute(Tag, IntegerValue);
9693   else if (IsStringValue)
9694     getTargetStreamer().emitTextAttribute(Tag, StringValue);
9695   return false;
9696 }
9697 
9698 /// parseDirectiveCPU
9699 ///  ::= .cpu str
9700 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9701   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9702   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9703 
9704   // FIXME: This is using table-gen data, but should be moved to
9705   // ARMTargetParser once that is table-gen'd.
9706   if (!getSTI().isCPUStringValid(CPU))
9707     return Error(L, "Unknown CPU name");
9708 
9709   bool WasThumb = isThumb();
9710   MCSubtargetInfo &STI = copySTI();
9711   STI.setDefaultFeatures(CPU, "");
9712   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9713   FixModeAfterArchChange(WasThumb, L);
9714 
9715   return false;
9716 }
9717 /// parseDirectiveFPU
9718 ///  ::= .fpu str
9719 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9720   SMLoc FPUNameLoc = getTok().getLoc();
9721   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9722 
9723   unsigned ID = ARM::parseFPU(FPU);
9724   std::vector<StringRef> Features;
9725   if (!ARM::getFPUFeatures(ID, Features))
9726     return Error(FPUNameLoc, "Unknown FPU name");
9727 
9728   MCSubtargetInfo &STI = copySTI();
9729   for (auto Feature : Features)
9730     STI.ApplyFeatureFlag(Feature);
9731   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9732 
9733   getTargetStreamer().emitFPU(ID);
9734   return false;
9735 }
9736 
9737 /// parseDirectiveFnStart
9738 ///  ::= .fnstart
9739 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9740   if (parseToken(AsmToken::EndOfStatement,
9741                  "unexpected token in '.fnstart' directive"))
9742     return true;
9743 
9744   if (UC.hasFnStart()) {
9745     Error(L, ".fnstart starts before the end of previous one");
9746     UC.emitFnStartLocNotes();
9747     return true;
9748   }
9749 
9750   // Reset the unwind directives parser state
9751   UC.reset();
9752 
9753   getTargetStreamer().emitFnStart();
9754 
9755   UC.recordFnStart(L);
9756   return false;
9757 }
9758 
9759 /// parseDirectiveFnEnd
9760 ///  ::= .fnend
9761 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9762   if (parseToken(AsmToken::EndOfStatement,
9763                  "unexpected token in '.fnend' directive"))
9764     return true;
9765   // Check the ordering of unwind directives
9766   if (!UC.hasFnStart())
9767     return Error(L, ".fnstart must precede .fnend directive");
9768 
9769   // Reset the unwind directives parser state
9770   getTargetStreamer().emitFnEnd();
9771 
9772   UC.reset();
9773   return false;
9774 }
9775 
9776 /// parseDirectiveCantUnwind
9777 ///  ::= .cantunwind
9778 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9779   if (parseToken(AsmToken::EndOfStatement,
9780                  "unexpected token in '.cantunwind' directive"))
9781     return true;
9782 
9783   UC.recordCantUnwind(L);
9784   // Check the ordering of unwind directives
9785   if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
9786     return true;
9787 
9788   if (UC.hasHandlerData()) {
9789     Error(L, ".cantunwind can't be used with .handlerdata directive");
9790     UC.emitHandlerDataLocNotes();
9791     return true;
9792   }
9793   if (UC.hasPersonality()) {
9794     Error(L, ".cantunwind can't be used with .personality directive");
9795     UC.emitPersonalityLocNotes();
9796     return true;
9797   }
9798 
9799   getTargetStreamer().emitCantUnwind();
9800   return false;
9801 }
9802 
9803 /// parseDirectivePersonality
9804 ///  ::= .personality name
9805 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9806   MCAsmParser &Parser = getParser();
9807   bool HasExistingPersonality = UC.hasPersonality();
9808 
9809   // Parse the name of the personality routine
9810   if (Parser.getTok().isNot(AsmToken::Identifier))
9811     return Error(L, "unexpected input in .personality directive.");
9812   StringRef Name(Parser.getTok().getIdentifier());
9813   Parser.Lex();
9814 
9815   if (parseToken(AsmToken::EndOfStatement,
9816                  "unexpected token in '.personality' directive"))
9817     return true;
9818 
9819   UC.recordPersonality(L);
9820 
9821   // Check the ordering of unwind directives
9822   if (!UC.hasFnStart())
9823     return Error(L, ".fnstart must precede .personality directive");
9824   if (UC.cantUnwind()) {
9825     Error(L, ".personality can't be used with .cantunwind directive");
9826     UC.emitCantUnwindLocNotes();
9827     return true;
9828   }
9829   if (UC.hasHandlerData()) {
9830     Error(L, ".personality must precede .handlerdata directive");
9831     UC.emitHandlerDataLocNotes();
9832     return true;
9833   }
9834   if (HasExistingPersonality) {
9835     Error(L, "multiple personality directives");
9836     UC.emitPersonalityLocNotes();
9837     return true;
9838   }
9839 
9840   MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
9841   getTargetStreamer().emitPersonality(PR);
9842   return false;
9843 }
9844 
9845 /// parseDirectiveHandlerData
9846 ///  ::= .handlerdata
9847 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9848   if (parseToken(AsmToken::EndOfStatement,
9849                  "unexpected token in '.handlerdata' directive"))
9850     return true;
9851 
9852   UC.recordHandlerData(L);
9853   // Check the ordering of unwind directives
9854   if (!UC.hasFnStart())
9855     return Error(L, ".fnstart must precede .personality directive");
9856   if (UC.cantUnwind()) {
9857     Error(L, ".handlerdata can't be used with .cantunwind directive");
9858     UC.emitCantUnwindLocNotes();
9859     return true;
9860   }
9861 
9862   getTargetStreamer().emitHandlerData();
9863   return false;
9864 }
9865 
9866 /// parseDirectiveSetFP
9867 ///  ::= .setfp fpreg, spreg [, offset]
9868 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9869   MCAsmParser &Parser = getParser();
9870   // Check the ordering of unwind directives
9871   if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
9872       check(UC.hasHandlerData(), L,
9873             ".setfp must precede .handlerdata directive"))
9874     return true;
9875 
9876   // Parse fpreg
9877   SMLoc FPRegLoc = Parser.getTok().getLoc();
9878   int FPReg = tryParseRegister();
9879 
9880   if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
9881       Parser.parseToken(AsmToken::Comma, "comma expected"))
9882     return true;
9883 
9884   // Parse spreg
9885   SMLoc SPRegLoc = Parser.getTok().getLoc();
9886   int SPReg = tryParseRegister();
9887   if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
9888       check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
9889             "register should be either $sp or the latest fp register"))
9890     return true;
9891 
9892   // Update the frame pointer register
9893   UC.saveFPReg(FPReg);
9894 
9895   // Parse offset
9896   int64_t Offset = 0;
9897   if (Parser.parseOptionalToken(AsmToken::Comma)) {
9898     if (Parser.getTok().isNot(AsmToken::Hash) &&
9899         Parser.getTok().isNot(AsmToken::Dollar))
9900       return Error(Parser.getTok().getLoc(), "'#' expected");
9901     Parser.Lex(); // skip hash token.
9902 
9903     const MCExpr *OffsetExpr;
9904     SMLoc ExLoc = Parser.getTok().getLoc();
9905     SMLoc EndLoc;
9906     if (getParser().parseExpression(OffsetExpr, EndLoc))
9907       return Error(ExLoc, "malformed setfp offset");
9908     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9909     if (check(!CE, ExLoc, "setfp offset must be an immediate"))
9910       return true;
9911     Offset = CE->getValue();
9912   }
9913 
9914   if (Parser.parseToken(AsmToken::EndOfStatement))
9915     return true;
9916 
9917   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9918                                 static_cast<unsigned>(SPReg), Offset);
9919   return false;
9920 }
9921 
9922 /// parseDirective
9923 ///  ::= .pad offset
9924 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9925   MCAsmParser &Parser = getParser();
9926   // Check the ordering of unwind directives
9927   if (!UC.hasFnStart())
9928     return Error(L, ".fnstart must precede .pad directive");
9929   if (UC.hasHandlerData())
9930     return Error(L, ".pad must precede .handlerdata directive");
9931 
9932   // Parse the offset
9933   if (Parser.getTok().isNot(AsmToken::Hash) &&
9934       Parser.getTok().isNot(AsmToken::Dollar))
9935     return Error(Parser.getTok().getLoc(), "'#' expected");
9936   Parser.Lex(); // skip hash token.
9937 
9938   const MCExpr *OffsetExpr;
9939   SMLoc ExLoc = Parser.getTok().getLoc();
9940   SMLoc EndLoc;
9941   if (getParser().parseExpression(OffsetExpr, EndLoc))
9942     return Error(ExLoc, "malformed pad offset");
9943   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9944   if (!CE)
9945     return Error(ExLoc, "pad offset must be an immediate");
9946 
9947   if (parseToken(AsmToken::EndOfStatement,
9948                  "unexpected token in '.pad' directive"))
9949     return true;
9950 
9951   getTargetStreamer().emitPad(CE->getValue());
9952   return false;
9953 }
9954 
9955 /// parseDirectiveRegSave
9956 ///  ::= .save  { registers }
9957 ///  ::= .vsave { registers }
9958 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9959   // Check the ordering of unwind directives
9960   if (!UC.hasFnStart())
9961     return Error(L, ".fnstart must precede .save or .vsave directives");
9962   if (UC.hasHandlerData())
9963     return Error(L, ".save or .vsave must precede .handlerdata directive");
9964 
9965   // RAII object to make sure parsed operands are deleted.
9966   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9967 
9968   // Parse the register list
9969   if (parseRegisterList(Operands) ||
9970       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
9971     return true;
9972   ARMOperand &Op = (ARMOperand &)*Operands[0];
9973   if (!IsVector && !Op.isRegList())
9974     return Error(L, ".save expects GPR registers");
9975   if (IsVector && !Op.isDPRRegList())
9976     return Error(L, ".vsave expects DPR registers");
9977 
9978   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9979   return false;
9980 }
9981 
9982 /// parseDirectiveInst
9983 ///  ::= .inst opcode [, ...]
9984 ///  ::= .inst.n opcode [, ...]
9985 ///  ::= .inst.w opcode [, ...]
9986 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9987   int Width = 4;
9988 
9989   if (isThumb()) {
9990     switch (Suffix) {
9991     case 'n':
9992       Width = 2;
9993       break;
9994     case 'w':
9995       break;
9996     default:
9997       return Error(Loc, "cannot determine Thumb instruction size, "
9998                         "use inst.n/inst.w instead");
9999     }
10000   } else {
10001     if (Suffix)
10002       return Error(Loc, "width suffixes are invalid in ARM mode");
10003   }
10004 
10005   auto parseOne = [&]() -> bool {
10006     const MCExpr *Expr;
10007     if (getParser().parseExpression(Expr))
10008       return true;
10009     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
10010     if (!Value) {
10011       return Error(Loc, "expected constant expression");
10012     }
10013 
10014     switch (Width) {
10015     case 2:
10016       if (Value->getValue() > 0xffff)
10017         return Error(Loc, "inst.n operand is too big, use inst.w instead");
10018       break;
10019     case 4:
10020       if (Value->getValue() > 0xffffffff)
10021         return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") +
10022                               " operand is too big");
10023       break;
10024     default:
10025       llvm_unreachable("only supported widths are 2 and 4");
10026     }
10027 
10028     getTargetStreamer().emitInst(Value->getValue(), Suffix);
10029     return false;
10030   };
10031 
10032   if (parseOptionalToken(AsmToken::EndOfStatement))
10033     return Error(Loc, "expected expression following directive");
10034   if (parseMany(parseOne))
10035     return true;
10036   return false;
10037 }
10038 
10039 /// parseDirectiveLtorg
10040 ///  ::= .ltorg | .pool
10041 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
10042   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10043     return true;
10044   getTargetStreamer().emitCurrentConstantPool();
10045   return false;
10046 }
10047 
10048 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
10049   const MCSection *Section = getStreamer().getCurrentSectionOnly();
10050 
10051   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10052     return true;
10053 
10054   if (!Section) {
10055     getStreamer().InitSections(false);
10056     Section = getStreamer().getCurrentSectionOnly();
10057   }
10058 
10059   assert(Section && "must have section to emit alignment");
10060   if (Section->UseCodeAlign())
10061     getStreamer().EmitCodeAlignment(2);
10062   else
10063     getStreamer().EmitValueToAlignment(2);
10064 
10065   return false;
10066 }
10067 
10068 /// parseDirectivePersonalityIndex
10069 ///   ::= .personalityindex index
10070 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
10071   MCAsmParser &Parser = getParser();
10072   bool HasExistingPersonality = UC.hasPersonality();
10073 
10074   const MCExpr *IndexExpression;
10075   SMLoc IndexLoc = Parser.getTok().getLoc();
10076   if (Parser.parseExpression(IndexExpression) ||
10077       parseToken(AsmToken::EndOfStatement,
10078                  "unexpected token in '.personalityindex' directive")) {
10079     return true;
10080   }
10081 
10082   UC.recordPersonalityIndex(L);
10083 
10084   if (!UC.hasFnStart()) {
10085     return Error(L, ".fnstart must precede .personalityindex directive");
10086   }
10087   if (UC.cantUnwind()) {
10088     Error(L, ".personalityindex cannot be used with .cantunwind");
10089     UC.emitCantUnwindLocNotes();
10090     return true;
10091   }
10092   if (UC.hasHandlerData()) {
10093     Error(L, ".personalityindex must precede .handlerdata directive");
10094     UC.emitHandlerDataLocNotes();
10095     return true;
10096   }
10097   if (HasExistingPersonality) {
10098     Error(L, "multiple personality directives");
10099     UC.emitPersonalityLocNotes();
10100     return true;
10101   }
10102 
10103   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
10104   if (!CE)
10105     return Error(IndexLoc, "index must be a constant number");
10106   if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
10107     return Error(IndexLoc,
10108                  "personality routine index should be in range [0-3]");
10109 
10110   getTargetStreamer().emitPersonalityIndex(CE->getValue());
10111   return false;
10112 }
10113 
10114 /// parseDirectiveUnwindRaw
10115 ///   ::= .unwind_raw offset, opcode [, opcode...]
10116 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
10117   MCAsmParser &Parser = getParser();
10118   int64_t StackOffset;
10119   const MCExpr *OffsetExpr;
10120   SMLoc OffsetLoc = getLexer().getLoc();
10121 
10122   if (!UC.hasFnStart())
10123     return Error(L, ".fnstart must precede .unwind_raw directives");
10124   if (getParser().parseExpression(OffsetExpr))
10125     return Error(OffsetLoc, "expected expression");
10126 
10127   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
10128   if (!CE)
10129     return Error(OffsetLoc, "offset must be a constant");
10130 
10131   StackOffset = CE->getValue();
10132 
10133   if (Parser.parseToken(AsmToken::Comma, "expected comma"))
10134     return true;
10135 
10136   SmallVector<uint8_t, 16> Opcodes;
10137 
10138   auto parseOne = [&]() -> bool {
10139     const MCExpr *OE;
10140     SMLoc OpcodeLoc = getLexer().getLoc();
10141     if (check(getLexer().is(AsmToken::EndOfStatement) ||
10142                   Parser.parseExpression(OE),
10143               OpcodeLoc, "expected opcode expression"))
10144       return true;
10145     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
10146     if (!OC)
10147       return Error(OpcodeLoc, "opcode value must be a constant");
10148     const int64_t Opcode = OC->getValue();
10149     if (Opcode & ~0xff)
10150       return Error(OpcodeLoc, "invalid opcode");
10151     Opcodes.push_back(uint8_t(Opcode));
10152     return false;
10153   };
10154 
10155   // Must have at least 1 element
10156   SMLoc OpcodeLoc = getLexer().getLoc();
10157   if (parseOptionalToken(AsmToken::EndOfStatement))
10158     return Error(OpcodeLoc, "expected opcode expression");
10159   if (parseMany(parseOne))
10160     return true;
10161 
10162   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
10163   return false;
10164 }
10165 
10166 /// parseDirectiveTLSDescSeq
10167 ///   ::= .tlsdescseq tls-variable
10168 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
10169   MCAsmParser &Parser = getParser();
10170 
10171   if (getLexer().isNot(AsmToken::Identifier))
10172     return TokError("expected variable after '.tlsdescseq' directive");
10173 
10174   const MCSymbolRefExpr *SRE =
10175     MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
10176                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
10177   Lex();
10178 
10179   if (parseToken(AsmToken::EndOfStatement,
10180                  "unexpected token in '.tlsdescseq' directive"))
10181     return true;
10182 
10183   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
10184   return false;
10185 }
10186 
10187 /// parseDirectiveMovSP
10188 ///  ::= .movsp reg [, #offset]
10189 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
10190   MCAsmParser &Parser = getParser();
10191   if (!UC.hasFnStart())
10192     return Error(L, ".fnstart must precede .movsp directives");
10193   if (UC.getFPReg() != ARM::SP)
10194     return Error(L, "unexpected .movsp directive");
10195 
10196   SMLoc SPRegLoc = Parser.getTok().getLoc();
10197   int SPReg = tryParseRegister();
10198   if (SPReg == -1)
10199     return Error(SPRegLoc, "register expected");
10200   if (SPReg == ARM::SP || SPReg == ARM::PC)
10201     return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
10202 
10203   int64_t Offset = 0;
10204   if (Parser.parseOptionalToken(AsmToken::Comma)) {
10205     if (Parser.parseToken(AsmToken::Hash, "expected #constant"))
10206       return true;
10207 
10208     const MCExpr *OffsetExpr;
10209     SMLoc OffsetLoc = Parser.getTok().getLoc();
10210 
10211     if (Parser.parseExpression(OffsetExpr))
10212       return Error(OffsetLoc, "malformed offset expression");
10213 
10214     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
10215     if (!CE)
10216       return Error(OffsetLoc, "offset must be an immediate constant");
10217 
10218     Offset = CE->getValue();
10219   }
10220 
10221   if (parseToken(AsmToken::EndOfStatement,
10222                  "unexpected token in '.movsp' directive"))
10223     return true;
10224 
10225   getTargetStreamer().emitMovSP(SPReg, Offset);
10226   UC.saveFPReg(SPReg);
10227 
10228   return false;
10229 }
10230 
10231 /// parseDirectiveObjectArch
10232 ///   ::= .object_arch name
10233 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
10234   MCAsmParser &Parser = getParser();
10235   if (getLexer().isNot(AsmToken::Identifier))
10236     return Error(getLexer().getLoc(), "unexpected token");
10237 
10238   StringRef Arch = Parser.getTok().getString();
10239   SMLoc ArchLoc = Parser.getTok().getLoc();
10240   Lex();
10241 
10242   unsigned ID = ARM::parseArch(Arch);
10243 
10244   if (ID == ARM::AK_INVALID)
10245     return Error(ArchLoc, "unknown architecture '" + Arch + "'");
10246   if (parseToken(AsmToken::EndOfStatement))
10247     return true;
10248 
10249   getTargetStreamer().emitObjectArch(ID);
10250   return false;
10251 }
10252 
10253 /// parseDirectiveAlign
10254 ///   ::= .align
10255 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
10256   // NOTE: if this is not the end of the statement, fall back to the target
10257   // agnostic handling for this directive which will correctly handle this.
10258   if (parseOptionalToken(AsmToken::EndOfStatement)) {
10259     // '.align' is target specifically handled to mean 2**2 byte alignment.
10260     const MCSection *Section = getStreamer().getCurrentSectionOnly();
10261     assert(Section && "must have section to emit alignment");
10262     if (Section->UseCodeAlign())
10263       getStreamer().EmitCodeAlignment(4, 0);
10264     else
10265       getStreamer().EmitValueToAlignment(4, 0, 1, 0);
10266     return false;
10267   }
10268   return true;
10269 }
10270 
10271 /// parseDirectiveThumbSet
10272 ///  ::= .thumb_set name, value
10273 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
10274   MCAsmParser &Parser = getParser();
10275 
10276   StringRef Name;
10277   if (check(Parser.parseIdentifier(Name),
10278             "expected identifier after '.thumb_set'") ||
10279       parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'"))
10280     return true;
10281 
10282   MCSymbol *Sym;
10283   const MCExpr *Value;
10284   if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
10285                                                Parser, Sym, Value))
10286     return true;
10287 
10288   getTargetStreamer().emitThumbSet(Sym, Value);
10289   return false;
10290 }
10291 
10292 /// Force static initialization.
10293 extern "C" void LLVMInitializeARMAsmParser() {
10294   RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
10295   RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
10296   RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
10297   RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
10298 }
10299 
10300 #define GET_REGISTER_MATCHER
10301 #define GET_SUBTARGET_FEATURE_NAME
10302 #define GET_MATCHER_IMPLEMENTATION
10303 #include "ARMGenAsmMatcher.inc"
10304 
10305 // FIXME: This structure should be moved inside ARMTargetParser
10306 // when we start to table-generate them, and we can use the ARM
10307 // flags below, that were generated by table-gen.
10308 static const struct {
10309   const unsigned Kind;
10310   const uint64_t ArchCheck;
10311   const FeatureBitset Features;
10312 } Extensions[] = {
10313   { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
10314   { ARM::AEK_CRYPTO,  Feature_HasV8,
10315     {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10316   { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
10317   { (ARM::AEK_HWDIV | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
10318     {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
10319   { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
10320   { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
10321   { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
10322   // FIXME: Only available in A-class, isel not predicated
10323   { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
10324   { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
10325   { ARM::AEK_RAS, Feature_HasV8, {ARM::FeatureRAS} },
10326   // FIXME: Unsupported extensions.
10327   { ARM::AEK_OS, Feature_None, {} },
10328   { ARM::AEK_IWMMXT, Feature_None, {} },
10329   { ARM::AEK_IWMMXT2, Feature_None, {} },
10330   { ARM::AEK_MAVERICK, Feature_None, {} },
10331   { ARM::AEK_XSCALE, Feature_None, {} },
10332 };
10333 
10334 /// parseDirectiveArchExtension
10335 ///   ::= .arch_extension [no]feature
10336 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
10337   MCAsmParser &Parser = getParser();
10338 
10339   if (getLexer().isNot(AsmToken::Identifier))
10340     return Error(getLexer().getLoc(), "expected architecture extension name");
10341 
10342   StringRef Name = Parser.getTok().getString();
10343   SMLoc ExtLoc = Parser.getTok().getLoc();
10344   Lex();
10345 
10346   if (parseToken(AsmToken::EndOfStatement,
10347                  "unexpected token in '.arch_extension' directive"))
10348     return true;
10349 
10350   bool EnableFeature = true;
10351   if (Name.startswith_lower("no")) {
10352     EnableFeature = false;
10353     Name = Name.substr(2);
10354   }
10355   unsigned FeatureKind = ARM::parseArchExt(Name);
10356   if (FeatureKind == ARM::AEK_INVALID)
10357     return Error(ExtLoc, "unknown architectural extension: " + Name);
10358 
10359   for (const auto &Extension : Extensions) {
10360     if (Extension.Kind != FeatureKind)
10361       continue;
10362 
10363     if (Extension.Features.none())
10364       return Error(ExtLoc, "unsupported architectural extension: " + Name);
10365 
10366     if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck)
10367       return Error(ExtLoc, "architectural extension '" + Name +
10368                                "' is not "
10369                                "allowed for the current base architecture");
10370 
10371     MCSubtargetInfo &STI = copySTI();
10372     FeatureBitset ToggleFeatures = EnableFeature
10373       ? (~STI.getFeatureBits() & Extension.Features)
10374       : ( STI.getFeatureBits() & Extension.Features);
10375 
10376     uint64_t Features =
10377         ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
10378     setAvailableFeatures(Features);
10379     return false;
10380   }
10381 
10382   return Error(ExtLoc, "unknown architectural extension: " + Name);
10383 }
10384 
10385 // Define this matcher function after the auto-generated include so we
10386 // have the match class enum definitions.
10387 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
10388                                                   unsigned Kind) {
10389   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
10390   // If the kind is a token for a literal immediate, check if our asm
10391   // operand matches. This is for InstAliases which have a fixed-value
10392   // immediate in the syntax.
10393   switch (Kind) {
10394   default: break;
10395   case MCK__35_0:
10396     if (Op.isImm())
10397       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10398         if (CE->getValue() == 0)
10399           return Match_Success;
10400     break;
10401   case MCK_ModImm:
10402     if (Op.isImm()) {
10403       const MCExpr *SOExpr = Op.getImm();
10404       int64_t Value;
10405       if (!SOExpr->evaluateAsAbsolute(Value))
10406         return Match_Success;
10407       assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10408              "expression value must be representable in 32 bits");
10409     }
10410     break;
10411   case MCK_rGPR:
10412     if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
10413       return Match_Success;
10414     break;
10415   case MCK_GPRPair:
10416     if (Op.isReg() &&
10417         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10418       return Match_Success;
10419     break;
10420   }
10421   return Match_InvalidOperand;
10422 }
10423