1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/MC/MCTargetAsmParser.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/OwningPtr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCParser/MCAsmLexer.h"
28 #include "llvm/MC/MCParser/MCAsmParser.h"
29 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/SourceMgr.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
38 
39 using namespace llvm;
40 
41 namespace {
42 
43 class ARMOperand;
44 
45 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
46 
47 class ARMAsmParser : public MCTargetAsmParser {
48   MCSubtargetInfo &STI;
49   MCAsmParser &Parser;
50   const MCRegisterInfo *MRI;
51 
52   // Unwind directives state
53   SMLoc FnStartLoc;
54   SMLoc CantUnwindLoc;
55   SMLoc PersonalityLoc;
56   SMLoc HandlerDataLoc;
57   int FPReg;
58   void resetUnwindDirectiveParserState() {
59     FnStartLoc = SMLoc();
60     CantUnwindLoc = SMLoc();
61     PersonalityLoc = SMLoc();
62     HandlerDataLoc = SMLoc();
63     FPReg = -1;
64   }
65 
66   // Map of register aliases registers via the .req directive.
67   StringMap<unsigned> RegisterReqs;
68 
69   struct {
70     ARMCC::CondCodes Cond;    // Condition for IT block.
71     unsigned Mask:4;          // Condition mask for instructions.
72                               // Starting at first 1 (from lsb).
73                               //   '1'  condition as indicated in IT.
74                               //   '0'  inverse of condition (else).
75                               // Count of instructions in IT block is
76                               // 4 - trailingzeroes(mask)
77 
78     bool FirstCond;           // Explicit flag for when we're parsing the
79                               // First instruction in the IT block. It's
80                               // implied in the mask, so needs special
81                               // handling.
82 
83     unsigned CurPosition;     // Current position in parsing of IT
84                               // block. In range [0,3]. Initialized
85                               // according to count of instructions in block.
86                               // ~0U if no active IT block.
87   } ITState;
88   bool inITBlock() { return ITState.CurPosition != ~0U;}
89   void forwardITPosition() {
90     if (!inITBlock()) return;
91     // Move to the next instruction in the IT block, if there is one. If not,
92     // mark the block as done.
93     unsigned TZ = countTrailingZeros(ITState.Mask);
94     if (++ITState.CurPosition == 5 - TZ)
95       ITState.CurPosition = ~0U; // Done with the IT block after this.
96   }
97 
98 
99   MCAsmParser &getParser() const { return Parser; }
100   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
101 
102   bool Warning(SMLoc L, const Twine &Msg,
103                ArrayRef<SMRange> Ranges = None) {
104     return Parser.Warning(L, Msg, Ranges);
105   }
106   bool Error(SMLoc L, const Twine &Msg,
107              ArrayRef<SMRange> Ranges = None) {
108     return Parser.Error(L, Msg, Ranges);
109   }
110 
111   int tryParseRegister();
112   bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
113   int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
114   bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
115   bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
116   bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
117   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
118   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
119                               unsigned &ShiftAmount);
120   bool parseDirectiveWord(unsigned Size, SMLoc L);
121   bool parseDirectiveThumb(SMLoc L);
122   bool parseDirectiveARM(SMLoc L);
123   bool parseDirectiveThumbFunc(SMLoc L);
124   bool parseDirectiveCode(SMLoc L);
125   bool parseDirectiveSyntax(SMLoc L);
126   bool parseDirectiveReq(StringRef Name, SMLoc L);
127   bool parseDirectiveUnreq(SMLoc L);
128   bool parseDirectiveArch(SMLoc L);
129   bool parseDirectiveEabiAttr(SMLoc L);
130   bool parseDirectiveFnStart(SMLoc L);
131   bool parseDirectiveFnEnd(SMLoc L);
132   bool parseDirectiveCantUnwind(SMLoc L);
133   bool parseDirectivePersonality(SMLoc L);
134   bool parseDirectiveHandlerData(SMLoc L);
135   bool parseDirectiveSetFP(SMLoc L);
136   bool parseDirectivePad(SMLoc L);
137   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
138 
139   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
140                           bool &CarrySetting, unsigned &ProcessorIMod,
141                           StringRef &ITMask);
142   void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
143                              bool &CanAcceptPredicationCode);
144 
145   bool isThumb() const {
146     // FIXME: Can tablegen auto-generate this?
147     return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
148   }
149   bool isThumbOne() const {
150     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
151   }
152   bool isThumbTwo() const {
153     return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
154   }
155   bool hasThumb() const {
156     return STI.getFeatureBits() & ARM::HasV4TOps;
157   }
158   bool hasV6Ops() const {
159     return STI.getFeatureBits() & ARM::HasV6Ops;
160   }
161   bool hasV7Ops() const {
162     return STI.getFeatureBits() & ARM::HasV7Ops;
163   }
164   bool hasV8Ops() const {
165     return STI.getFeatureBits() & ARM::HasV8Ops;
166   }
167   bool hasARM() const {
168     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
169   }
170 
171   void SwitchMode() {
172     unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
173     setAvailableFeatures(FB);
174   }
175   bool isMClass() const {
176     return STI.getFeatureBits() & ARM::FeatureMClass;
177   }
178 
179   /// @name Auto-generated Match Functions
180   /// {
181 
182 #define GET_ASSEMBLER_HEADER
183 #include "ARMGenAsmMatcher.inc"
184 
185   /// }
186 
187   OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
188   OperandMatchResultTy parseCoprocNumOperand(
189     SmallVectorImpl<MCParsedAsmOperand*>&);
190   OperandMatchResultTy parseCoprocRegOperand(
191     SmallVectorImpl<MCParsedAsmOperand*>&);
192   OperandMatchResultTy parseCoprocOptionOperand(
193     SmallVectorImpl<MCParsedAsmOperand*>&);
194   OperandMatchResultTy parseMemBarrierOptOperand(
195     SmallVectorImpl<MCParsedAsmOperand*>&);
196   OperandMatchResultTy parseInstSyncBarrierOptOperand(
197     SmallVectorImpl<MCParsedAsmOperand*>&);
198   OperandMatchResultTy parseProcIFlagsOperand(
199     SmallVectorImpl<MCParsedAsmOperand*>&);
200   OperandMatchResultTy parseMSRMaskOperand(
201     SmallVectorImpl<MCParsedAsmOperand*>&);
202   OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
203                                    StringRef Op, int Low, int High);
204   OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
205     return parsePKHImm(O, "lsl", 0, 31);
206   }
207   OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
208     return parsePKHImm(O, "asr", 1, 32);
209   }
210   OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
211   OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
212   OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
213   OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
214   OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
215   OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
216   OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
217   OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
218   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
219                                        SMLoc &EndLoc);
220 
221   // Asm Match Converter Methods
222   void cvtThumbMultiply(MCInst &Inst,
223                         const SmallVectorImpl<MCParsedAsmOperand*> &);
224   void cvtThumbBranches(MCInst &Inst,
225                         const SmallVectorImpl<MCParsedAsmOperand*> &);
226 
227   bool validateInstruction(MCInst &Inst,
228                            const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
229   bool processInstruction(MCInst &Inst,
230                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
231   bool shouldOmitCCOutOperand(StringRef Mnemonic,
232                               SmallVectorImpl<MCParsedAsmOperand*> &Operands);
233   bool shouldOmitPredicateOperand(StringRef Mnemonic,
234                               SmallVectorImpl<MCParsedAsmOperand*> &Operands);
235   bool isDeprecated(MCInst &Inst, StringRef &Info);
236 
237 public:
238   enum ARMMatchResultTy {
239     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
240     Match_RequiresNotITBlock,
241     Match_RequiresV6,
242     Match_RequiresThumb2,
243 #define GET_OPERAND_DIAGNOSTIC_TYPES
244 #include "ARMGenAsmMatcher.inc"
245 
246   };
247 
248   ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
249     : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) {
250     MCAsmParserExtension::Initialize(_Parser);
251 
252     // Cache the MCRegisterInfo.
253     MRI = getContext().getRegisterInfo();
254 
255     // Initialize the set of available features.
256     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
257 
258     // Not in an ITBlock to start with.
259     ITState.CurPosition = ~0U;
260 
261     // Set ELF header flags.
262     // FIXME: This should eventually end up somewhere else where more
263     // intelligent flag decisions can be made. For now we are just maintaining
264     // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
265     if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
266       MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
267   }
268 
269   // Implementation of the MCTargetAsmParser interface:
270   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
271   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
272                         SMLoc NameLoc,
273                         SmallVectorImpl<MCParsedAsmOperand*> &Operands);
274   bool ParseDirective(AsmToken DirectiveID);
275 
276   unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
277   unsigned checkTargetMatchPredicate(MCInst &Inst);
278 
279   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
280                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
281                                MCStreamer &Out, unsigned &ErrorInfo,
282                                bool MatchingInlineAsm);
283 };
284 } // end anonymous namespace
285 
286 namespace {
287 
288 /// ARMOperand - Instances of this class represent a parsed ARM machine
289 /// operand.
290 class ARMOperand : public MCParsedAsmOperand {
291   enum KindTy {
292     k_CondCode,
293     k_CCOut,
294     k_ITCondMask,
295     k_CoprocNum,
296     k_CoprocReg,
297     k_CoprocOption,
298     k_Immediate,
299     k_MemBarrierOpt,
300     k_InstSyncBarrierOpt,
301     k_Memory,
302     k_PostIndexRegister,
303     k_MSRMask,
304     k_ProcIFlags,
305     k_VectorIndex,
306     k_Register,
307     k_RegisterList,
308     k_DPRRegisterList,
309     k_SPRRegisterList,
310     k_VectorList,
311     k_VectorListAllLanes,
312     k_VectorListIndexed,
313     k_ShiftedRegister,
314     k_ShiftedImmediate,
315     k_ShifterImmediate,
316     k_RotateImmediate,
317     k_BitfieldDescriptor,
318     k_Token
319   } Kind;
320 
321   SMLoc StartLoc, EndLoc;
322   SmallVector<unsigned, 8> Registers;
323 
324   struct CCOp {
325     ARMCC::CondCodes Val;
326   };
327 
328   struct CopOp {
329     unsigned Val;
330   };
331 
332   struct CoprocOptionOp {
333     unsigned Val;
334   };
335 
336   struct ITMaskOp {
337     unsigned Mask:4;
338   };
339 
340   struct MBOptOp {
341     ARM_MB::MemBOpt Val;
342   };
343 
344   struct ISBOptOp {
345     ARM_ISB::InstSyncBOpt Val;
346   };
347 
348   struct IFlagsOp {
349     ARM_PROC::IFlags Val;
350   };
351 
352   struct MMaskOp {
353     unsigned Val;
354   };
355 
356   struct TokOp {
357     const char *Data;
358     unsigned Length;
359   };
360 
361   struct RegOp {
362     unsigned RegNum;
363   };
364 
365   // A vector register list is a sequential list of 1 to 4 registers.
366   struct VectorListOp {
367     unsigned RegNum;
368     unsigned Count;
369     unsigned LaneIndex;
370     bool isDoubleSpaced;
371   };
372 
373   struct VectorIndexOp {
374     unsigned Val;
375   };
376 
377   struct ImmOp {
378     const MCExpr *Val;
379   };
380 
381   /// Combined record for all forms of ARM address expressions.
382   struct MemoryOp {
383     unsigned BaseRegNum;
384     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
385     // was specified.
386     const MCConstantExpr *OffsetImm;  // Offset immediate value
387     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
388     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
389     unsigned ShiftImm;        // shift for OffsetReg.
390     unsigned Alignment;       // 0 = no alignment specified
391     // n = alignment in bytes (2, 4, 8, 16, or 32)
392     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
393   };
394 
395   struct PostIdxRegOp {
396     unsigned RegNum;
397     bool isAdd;
398     ARM_AM::ShiftOpc ShiftTy;
399     unsigned ShiftImm;
400   };
401 
402   struct ShifterImmOp {
403     bool isASR;
404     unsigned Imm;
405   };
406 
407   struct RegShiftedRegOp {
408     ARM_AM::ShiftOpc ShiftTy;
409     unsigned SrcReg;
410     unsigned ShiftReg;
411     unsigned ShiftImm;
412   };
413 
414   struct RegShiftedImmOp {
415     ARM_AM::ShiftOpc ShiftTy;
416     unsigned SrcReg;
417     unsigned ShiftImm;
418   };
419 
420   struct RotImmOp {
421     unsigned Imm;
422   };
423 
424   struct BitfieldOp {
425     unsigned LSB;
426     unsigned Width;
427   };
428 
429   union {
430     struct CCOp CC;
431     struct CopOp Cop;
432     struct CoprocOptionOp CoprocOption;
433     struct MBOptOp MBOpt;
434     struct ISBOptOp ISBOpt;
435     struct ITMaskOp ITMask;
436     struct IFlagsOp IFlags;
437     struct MMaskOp MMask;
438     struct TokOp Tok;
439     struct RegOp Reg;
440     struct VectorListOp VectorList;
441     struct VectorIndexOp VectorIndex;
442     struct ImmOp Imm;
443     struct MemoryOp Memory;
444     struct PostIdxRegOp PostIdxReg;
445     struct ShifterImmOp ShifterImm;
446     struct RegShiftedRegOp RegShiftedReg;
447     struct RegShiftedImmOp RegShiftedImm;
448     struct RotImmOp RotImm;
449     struct BitfieldOp Bitfield;
450   };
451 
452   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
453 public:
454   ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
455     Kind = o.Kind;
456     StartLoc = o.StartLoc;
457     EndLoc = o.EndLoc;
458     switch (Kind) {
459     case k_CondCode:
460       CC = o.CC;
461       break;
462     case k_ITCondMask:
463       ITMask = o.ITMask;
464       break;
465     case k_Token:
466       Tok = o.Tok;
467       break;
468     case k_CCOut:
469     case k_Register:
470       Reg = o.Reg;
471       break;
472     case k_RegisterList:
473     case k_DPRRegisterList:
474     case k_SPRRegisterList:
475       Registers = o.Registers;
476       break;
477     case k_VectorList:
478     case k_VectorListAllLanes:
479     case k_VectorListIndexed:
480       VectorList = o.VectorList;
481       break;
482     case k_CoprocNum:
483     case k_CoprocReg:
484       Cop = o.Cop;
485       break;
486     case k_CoprocOption:
487       CoprocOption = o.CoprocOption;
488       break;
489     case k_Immediate:
490       Imm = o.Imm;
491       break;
492     case k_MemBarrierOpt:
493       MBOpt = o.MBOpt;
494       break;
495     case k_InstSyncBarrierOpt:
496       ISBOpt = o.ISBOpt;
497     case k_Memory:
498       Memory = o.Memory;
499       break;
500     case k_PostIndexRegister:
501       PostIdxReg = o.PostIdxReg;
502       break;
503     case k_MSRMask:
504       MMask = o.MMask;
505       break;
506     case k_ProcIFlags:
507       IFlags = o.IFlags;
508       break;
509     case k_ShifterImmediate:
510       ShifterImm = o.ShifterImm;
511       break;
512     case k_ShiftedRegister:
513       RegShiftedReg = o.RegShiftedReg;
514       break;
515     case k_ShiftedImmediate:
516       RegShiftedImm = o.RegShiftedImm;
517       break;
518     case k_RotateImmediate:
519       RotImm = o.RotImm;
520       break;
521     case k_BitfieldDescriptor:
522       Bitfield = o.Bitfield;
523       break;
524     case k_VectorIndex:
525       VectorIndex = o.VectorIndex;
526       break;
527     }
528   }
529 
530   /// getStartLoc - Get the location of the first token of this operand.
531   SMLoc getStartLoc() const { return StartLoc; }
532   /// getEndLoc - Get the location of the last token of this operand.
533   SMLoc getEndLoc() const { return EndLoc; }
534   /// getLocRange - Get the range between the first and last token of this
535   /// operand.
536   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
537 
538   ARMCC::CondCodes getCondCode() const {
539     assert(Kind == k_CondCode && "Invalid access!");
540     return CC.Val;
541   }
542 
543   unsigned getCoproc() const {
544     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
545     return Cop.Val;
546   }
547 
548   StringRef getToken() const {
549     assert(Kind == k_Token && "Invalid access!");
550     return StringRef(Tok.Data, Tok.Length);
551   }
552 
553   unsigned getReg() const {
554     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
555     return Reg.RegNum;
556   }
557 
558   const SmallVectorImpl<unsigned> &getRegList() const {
559     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
560             Kind == k_SPRRegisterList) && "Invalid access!");
561     return Registers;
562   }
563 
564   const MCExpr *getImm() const {
565     assert(isImm() && "Invalid access!");
566     return Imm.Val;
567   }
568 
569   unsigned getVectorIndex() const {
570     assert(Kind == k_VectorIndex && "Invalid access!");
571     return VectorIndex.Val;
572   }
573 
574   ARM_MB::MemBOpt getMemBarrierOpt() const {
575     assert(Kind == k_MemBarrierOpt && "Invalid access!");
576     return MBOpt.Val;
577   }
578 
579   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
580     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
581     return ISBOpt.Val;
582   }
583 
584   ARM_PROC::IFlags getProcIFlags() const {
585     assert(Kind == k_ProcIFlags && "Invalid access!");
586     return IFlags.Val;
587   }
588 
589   unsigned getMSRMask() const {
590     assert(Kind == k_MSRMask && "Invalid access!");
591     return MMask.Val;
592   }
593 
594   bool isCoprocNum() const { return Kind == k_CoprocNum; }
595   bool isCoprocReg() const { return Kind == k_CoprocReg; }
596   bool isCoprocOption() const { return Kind == k_CoprocOption; }
597   bool isCondCode() const { return Kind == k_CondCode; }
598   bool isCCOut() const { return Kind == k_CCOut; }
599   bool isITMask() const { return Kind == k_ITCondMask; }
600   bool isITCondCode() const { return Kind == k_CondCode; }
601   bool isImm() const { return Kind == k_Immediate; }
602   // checks whether this operand is an unsigned offset which fits is a field
603   // of specified width and scaled by a specific number of bits
604   template<unsigned width, unsigned scale>
605   bool isUnsignedOffset() const {
606     if (!isImm()) return false;
607     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
608     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
609       int64_t Val = CE->getValue();
610       int64_t Align = 1LL << scale;
611       int64_t Max = Align * ((1LL << width) - 1);
612       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
613     }
614     return false;
615   }
616   // checks whether this operand is an signed offset which fits is a field
617   // of specified width and scaled by a specific number of bits
618   template<unsigned width, unsigned scale>
619   bool isSignedOffset() const {
620     if (!isImm()) return false;
621     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
622     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
623       int64_t Val = CE->getValue();
624       int64_t Align = 1LL << scale;
625       int64_t Max = Align * ((1LL << (width-1)) - 1);
626       int64_t Min = -Align * (1LL << (width-1));
627       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
628     }
629     return false;
630   }
631 
632   // checks whether this operand is a memory operand computed as an offset
633   // applied to PC. the offset may have 8 bits of magnitude and is represented
634   // with two bits of shift. textually it may be either [pc, #imm], #imm or
635   // relocable expression...
636   bool isThumbMemPC() const {
637     int64_t Val = 0;
638     if (isImm()) {
639       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
640       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
641       if (!CE) return false;
642       Val = CE->getValue();
643     }
644     else if (isMem()) {
645       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
646       if(Memory.BaseRegNum != ARM::PC) return false;
647       Val = Memory.OffsetImm->getValue();
648     }
649     else return false;
650     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
651   }
652   bool isFPImm() const {
653     if (!isImm()) return false;
654     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
655     if (!CE) return false;
656     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
657     return Val != -1;
658   }
659   bool isFBits16() const {
660     if (!isImm()) return false;
661     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
662     if (!CE) return false;
663     int64_t Value = CE->getValue();
664     return Value >= 0 && Value <= 16;
665   }
666   bool isFBits32() const {
667     if (!isImm()) return false;
668     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
669     if (!CE) return false;
670     int64_t Value = CE->getValue();
671     return Value >= 1 && Value <= 32;
672   }
673   bool isImm8s4() const {
674     if (!isImm()) return false;
675     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676     if (!CE) return false;
677     int64_t Value = CE->getValue();
678     return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
679   }
680   bool isImm0_4() const {
681     if (!isImm()) return false;
682     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683     if (!CE) return false;
684     int64_t Value = CE->getValue();
685     return Value >= 0 && Value < 5;
686   }
687   bool isImm0_1020s4() const {
688     if (!isImm()) return false;
689     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
690     if (!CE) return false;
691     int64_t Value = CE->getValue();
692     return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
693   }
694   bool isImm0_508s4() const {
695     if (!isImm()) return false;
696     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
697     if (!CE) return false;
698     int64_t Value = CE->getValue();
699     return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
700   }
701   bool isImm0_508s4Neg() const {
702     if (!isImm()) return false;
703     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
704     if (!CE) return false;
705     int64_t Value = -CE->getValue();
706     // explicitly exclude zero. we want that to use the normal 0_508 version.
707     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
708   }
709   bool isImm0_255() const {
710     if (!isImm()) return false;
711     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
712     if (!CE) return false;
713     int64_t Value = CE->getValue();
714     return Value >= 0 && Value < 256;
715   }
716   bool isImm0_4095() const {
717     if (!isImm()) return false;
718     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
719     if (!CE) return false;
720     int64_t Value = CE->getValue();
721     return Value >= 0 && Value < 4096;
722   }
723   bool isImm0_4095Neg() const {
724     if (!isImm()) return false;
725     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
726     if (!CE) return false;
727     int64_t Value = -CE->getValue();
728     return Value > 0 && Value < 4096;
729   }
730   bool isImm0_1() const {
731     if (!isImm()) return false;
732     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
733     if (!CE) return false;
734     int64_t Value = CE->getValue();
735     return Value >= 0 && Value < 2;
736   }
737   bool isImm0_3() const {
738     if (!isImm()) return false;
739     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
740     if (!CE) return false;
741     int64_t Value = CE->getValue();
742     return Value >= 0 && Value < 4;
743   }
744   bool isImm0_7() const {
745     if (!isImm()) return false;
746     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
747     if (!CE) return false;
748     int64_t Value = CE->getValue();
749     return Value >= 0 && Value < 8;
750   }
751   bool isImm0_15() const {
752     if (!isImm()) return false;
753     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
754     if (!CE) return false;
755     int64_t Value = CE->getValue();
756     return Value >= 0 && Value < 16;
757   }
758   bool isImm0_31() const {
759     if (!isImm()) return false;
760     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
761     if (!CE) return false;
762     int64_t Value = CE->getValue();
763     return Value >= 0 && Value < 32;
764   }
765   bool isImm0_63() const {
766     if (!isImm()) return false;
767     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
768     if (!CE) return false;
769     int64_t Value = CE->getValue();
770     return Value >= 0 && Value < 64;
771   }
772   bool isImm8() const {
773     if (!isImm()) return false;
774     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
775     if (!CE) return false;
776     int64_t Value = CE->getValue();
777     return Value == 8;
778   }
779   bool isImm16() const {
780     if (!isImm()) return false;
781     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
782     if (!CE) return false;
783     int64_t Value = CE->getValue();
784     return Value == 16;
785   }
786   bool isImm32() const {
787     if (!isImm()) return false;
788     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
789     if (!CE) return false;
790     int64_t Value = CE->getValue();
791     return Value == 32;
792   }
793   bool isShrImm8() const {
794     if (!isImm()) return false;
795     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
796     if (!CE) return false;
797     int64_t Value = CE->getValue();
798     return Value > 0 && Value <= 8;
799   }
800   bool isShrImm16() const {
801     if (!isImm()) return false;
802     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
803     if (!CE) return false;
804     int64_t Value = CE->getValue();
805     return Value > 0 && Value <= 16;
806   }
807   bool isShrImm32() const {
808     if (!isImm()) return false;
809     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
810     if (!CE) return false;
811     int64_t Value = CE->getValue();
812     return Value > 0 && Value <= 32;
813   }
814   bool isShrImm64() const {
815     if (!isImm()) return false;
816     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
817     if (!CE) return false;
818     int64_t Value = CE->getValue();
819     return Value > 0 && Value <= 64;
820   }
821   bool isImm1_7() const {
822     if (!isImm()) return false;
823     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
824     if (!CE) return false;
825     int64_t Value = CE->getValue();
826     return Value > 0 && Value < 8;
827   }
828   bool isImm1_15() const {
829     if (!isImm()) return false;
830     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
831     if (!CE) return false;
832     int64_t Value = CE->getValue();
833     return Value > 0 && Value < 16;
834   }
835   bool isImm1_31() const {
836     if (!isImm()) return false;
837     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
838     if (!CE) return false;
839     int64_t Value = CE->getValue();
840     return Value > 0 && Value < 32;
841   }
842   bool isImm1_16() const {
843     if (!isImm()) return false;
844     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
845     if (!CE) return false;
846     int64_t Value = CE->getValue();
847     return Value > 0 && Value < 17;
848   }
849   bool isImm1_32() const {
850     if (!isImm()) return false;
851     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
852     if (!CE) return false;
853     int64_t Value = CE->getValue();
854     return Value > 0 && Value < 33;
855   }
856   bool isImm0_32() const {
857     if (!isImm()) return false;
858     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859     if (!CE) return false;
860     int64_t Value = CE->getValue();
861     return Value >= 0 && Value < 33;
862   }
863   bool isImm0_65535() const {
864     if (!isImm()) return false;
865     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866     if (!CE) return false;
867     int64_t Value = CE->getValue();
868     return Value >= 0 && Value < 65536;
869   }
870   bool isImm0_65535Expr() const {
871     if (!isImm()) return false;
872     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873     // If it's not a constant expression, it'll generate a fixup and be
874     // handled later.
875     if (!CE) return true;
876     int64_t Value = CE->getValue();
877     return Value >= 0 && Value < 65536;
878   }
879   bool isImm24bit() const {
880     if (!isImm()) return false;
881     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
882     if (!CE) return false;
883     int64_t Value = CE->getValue();
884     return Value >= 0 && Value <= 0xffffff;
885   }
886   bool isImmThumbSR() const {
887     if (!isImm()) return false;
888     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
889     if (!CE) return false;
890     int64_t Value = CE->getValue();
891     return Value > 0 && Value < 33;
892   }
893   bool isPKHLSLImm() const {
894     if (!isImm()) return false;
895     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
896     if (!CE) return false;
897     int64_t Value = CE->getValue();
898     return Value >= 0 && Value < 32;
899   }
900   bool isPKHASRImm() const {
901     if (!isImm()) return false;
902     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
903     if (!CE) return false;
904     int64_t Value = CE->getValue();
905     return Value > 0 && Value <= 32;
906   }
907   bool isAdrLabel() const {
908     // If we have an immediate that's not a constant, treat it as a label
909     // reference needing a fixup. If it is a constant, but it can't fit
910     // into shift immediate encoding, we reject it.
911     if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
912     else return (isARMSOImm() || isARMSOImmNeg());
913   }
914   bool isARMSOImm() const {
915     if (!isImm()) return false;
916     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
917     if (!CE) return false;
918     int64_t Value = CE->getValue();
919     return ARM_AM::getSOImmVal(Value) != -1;
920   }
921   bool isARMSOImmNot() const {
922     if (!isImm()) return false;
923     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
924     if (!CE) return false;
925     int64_t Value = CE->getValue();
926     return ARM_AM::getSOImmVal(~Value) != -1;
927   }
928   bool isARMSOImmNeg() const {
929     if (!isImm()) return false;
930     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
931     if (!CE) return false;
932     int64_t Value = CE->getValue();
933     // Only use this when not representable as a plain so_imm.
934     return ARM_AM::getSOImmVal(Value) == -1 &&
935       ARM_AM::getSOImmVal(-Value) != -1;
936   }
937   bool isT2SOImm() const {
938     if (!isImm()) return false;
939     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940     if (!CE) return false;
941     int64_t Value = CE->getValue();
942     return ARM_AM::getT2SOImmVal(Value) != -1;
943   }
944   bool isT2SOImmNot() const {
945     if (!isImm()) return false;
946     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
947     if (!CE) return false;
948     int64_t Value = CE->getValue();
949     return ARM_AM::getT2SOImmVal(Value) == -1 &&
950       ARM_AM::getT2SOImmVal(~Value) != -1;
951   }
952   bool isT2SOImmNeg() const {
953     if (!isImm()) return false;
954     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955     if (!CE) return false;
956     int64_t Value = CE->getValue();
957     // Only use this when not representable as a plain so_imm.
958     return ARM_AM::getT2SOImmVal(Value) == -1 &&
959       ARM_AM::getT2SOImmVal(-Value) != -1;
960   }
961   bool isSetEndImm() const {
962     if (!isImm()) return false;
963     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964     if (!CE) return false;
965     int64_t Value = CE->getValue();
966     return Value == 1 || Value == 0;
967   }
968   bool isReg() const { return Kind == k_Register; }
969   bool isRegList() const { return Kind == k_RegisterList; }
970   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
971   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
972   bool isToken() const { return Kind == k_Token; }
973   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
974   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
975   bool isMem() const { return Kind == k_Memory; }
976   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
977   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
978   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
979   bool isRotImm() const { return Kind == k_RotateImmediate; }
980   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
981   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
982   bool isPostIdxReg() const {
983     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
984   }
985   bool isMemNoOffset(bool alignOK = false) const {
986     if (!isMem())
987       return false;
988     // No offset of any kind.
989     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
990      (alignOK || Memory.Alignment == 0);
991   }
992   bool isMemPCRelImm12() const {
993     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
994       return false;
995     // Base register must be PC.
996     if (Memory.BaseRegNum != ARM::PC)
997       return false;
998     // Immediate offset in range [-4095, 4095].
999     if (!Memory.OffsetImm) return true;
1000     int64_t Val = Memory.OffsetImm->getValue();
1001     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1002   }
1003   bool isAlignedMemory() const {
1004     return isMemNoOffset(true);
1005   }
1006   bool isAddrMode2() const {
1007     if (!isMem() || Memory.Alignment != 0) return false;
1008     // Check for register offset.
1009     if (Memory.OffsetRegNum) return true;
1010     // Immediate offset in range [-4095, 4095].
1011     if (!Memory.OffsetImm) return true;
1012     int64_t Val = Memory.OffsetImm->getValue();
1013     return Val > -4096 && Val < 4096;
1014   }
1015   bool isAM2OffsetImm() const {
1016     if (!isImm()) return false;
1017     // Immediate offset in range [-4095, 4095].
1018     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1019     if (!CE) return false;
1020     int64_t Val = CE->getValue();
1021     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1022   }
1023   bool isAddrMode3() const {
1024     // If we have an immediate that's not a constant, treat it as a label
1025     // reference needing a fixup. If it is a constant, it's something else
1026     // and we reject it.
1027     if (isImm() && !isa<MCConstantExpr>(getImm()))
1028       return true;
1029     if (!isMem() || Memory.Alignment != 0) return false;
1030     // No shifts are legal for AM3.
1031     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1032     // Check for register offset.
1033     if (Memory.OffsetRegNum) return true;
1034     // Immediate offset in range [-255, 255].
1035     if (!Memory.OffsetImm) return true;
1036     int64_t Val = Memory.OffsetImm->getValue();
1037     // The #-0 offset is encoded as INT32_MIN, and we have to check
1038     // for this too.
1039     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1040   }
1041   bool isAM3Offset() const {
1042     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1043       return false;
1044     if (Kind == k_PostIndexRegister)
1045       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1046     // Immediate offset in range [-255, 255].
1047     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048     if (!CE) return false;
1049     int64_t Val = CE->getValue();
1050     // Special case, #-0 is INT32_MIN.
1051     return (Val > -256 && Val < 256) || Val == INT32_MIN;
1052   }
1053   bool isAddrMode5() const {
1054     // If we have an immediate that's not a constant, treat it as a label
1055     // reference needing a fixup. If it is a constant, it's something else
1056     // and we reject it.
1057     if (isImm() && !isa<MCConstantExpr>(getImm()))
1058       return true;
1059     if (!isMem() || Memory.Alignment != 0) return false;
1060     // Check for register offset.
1061     if (Memory.OffsetRegNum) return false;
1062     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1063     if (!Memory.OffsetImm) return true;
1064     int64_t Val = Memory.OffsetImm->getValue();
1065     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1066       Val == INT32_MIN;
1067   }
1068   bool isMemTBB() const {
1069     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1070         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1071       return false;
1072     return true;
1073   }
1074   bool isMemTBH() const {
1075     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1076         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1077         Memory.Alignment != 0 )
1078       return false;
1079     return true;
1080   }
1081   bool isMemRegOffset() const {
1082     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1083       return false;
1084     return true;
1085   }
1086   bool isT2MemRegOffset() const {
1087     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1088         Memory.Alignment != 0)
1089       return false;
1090     // Only lsl #{0, 1, 2, 3} allowed.
1091     if (Memory.ShiftType == ARM_AM::no_shift)
1092       return true;
1093     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1094       return false;
1095     return true;
1096   }
1097   bool isMemThumbRR() const {
1098     // Thumb reg+reg addressing is simple. Just two registers, a base and
1099     // an offset. No shifts, negations or any other complicating factors.
1100     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1101         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1102       return false;
1103     return isARMLowRegister(Memory.BaseRegNum) &&
1104       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1105   }
1106   bool isMemThumbRIs4() const {
1107     if (!isMem() || Memory.OffsetRegNum != 0 ||
1108         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1109       return false;
1110     // Immediate offset, multiple of 4 in range [0, 124].
1111     if (!Memory.OffsetImm) return true;
1112     int64_t Val = Memory.OffsetImm->getValue();
1113     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1114   }
1115   bool isMemThumbRIs2() const {
1116     if (!isMem() || Memory.OffsetRegNum != 0 ||
1117         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1118       return false;
1119     // Immediate offset, multiple of 4 in range [0, 62].
1120     if (!Memory.OffsetImm) return true;
1121     int64_t Val = Memory.OffsetImm->getValue();
1122     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1123   }
1124   bool isMemThumbRIs1() const {
1125     if (!isMem() || Memory.OffsetRegNum != 0 ||
1126         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1127       return false;
1128     // Immediate offset in range [0, 31].
1129     if (!Memory.OffsetImm) return true;
1130     int64_t Val = Memory.OffsetImm->getValue();
1131     return Val >= 0 && Val <= 31;
1132   }
1133   bool isMemThumbSPI() const {
1134     if (!isMem() || Memory.OffsetRegNum != 0 ||
1135         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1136       return false;
1137     // Immediate offset, multiple of 4 in range [0, 1020].
1138     if (!Memory.OffsetImm) return true;
1139     int64_t Val = Memory.OffsetImm->getValue();
1140     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1141   }
1142   bool isMemImm8s4Offset() const {
1143     // If we have an immediate that's not a constant, treat it as a label
1144     // reference needing a fixup. If it is a constant, it's something else
1145     // and we reject it.
1146     if (isImm() && !isa<MCConstantExpr>(getImm()))
1147       return true;
1148     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1149       return false;
1150     // Immediate offset a multiple of 4 in range [-1020, 1020].
1151     if (!Memory.OffsetImm) return true;
1152     int64_t Val = Memory.OffsetImm->getValue();
1153     // Special case, #-0 is INT32_MIN.
1154     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1155   }
1156   bool isMemImm0_1020s4Offset() const {
1157     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1158       return false;
1159     // Immediate offset a multiple of 4 in range [0, 1020].
1160     if (!Memory.OffsetImm) return true;
1161     int64_t Val = Memory.OffsetImm->getValue();
1162     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1163   }
1164   bool isMemImm8Offset() const {
1165     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1166       return false;
1167     // Base reg of PC isn't allowed for these encodings.
1168     if (Memory.BaseRegNum == ARM::PC) return false;
1169     // Immediate offset in range [-255, 255].
1170     if (!Memory.OffsetImm) return true;
1171     int64_t Val = Memory.OffsetImm->getValue();
1172     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1173   }
1174   bool isMemPosImm8Offset() const {
1175     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1176       return false;
1177     // Immediate offset in range [0, 255].
1178     if (!Memory.OffsetImm) return true;
1179     int64_t Val = Memory.OffsetImm->getValue();
1180     return Val >= 0 && Val < 256;
1181   }
1182   bool isMemNegImm8Offset() const {
1183     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1184       return false;
1185     // Base reg of PC isn't allowed for these encodings.
1186     if (Memory.BaseRegNum == ARM::PC) return false;
1187     // Immediate offset in range [-255, -1].
1188     if (!Memory.OffsetImm) return false;
1189     int64_t Val = Memory.OffsetImm->getValue();
1190     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1191   }
1192   bool isMemUImm12Offset() const {
1193     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1194       return false;
1195     // Immediate offset in range [0, 4095].
1196     if (!Memory.OffsetImm) return true;
1197     int64_t Val = Memory.OffsetImm->getValue();
1198     return (Val >= 0 && Val < 4096);
1199   }
1200   bool isMemImm12Offset() const {
1201     // If we have an immediate that's not a constant, treat it as a label
1202     // reference needing a fixup. If it is a constant, it's something else
1203     // and we reject it.
1204     if (isImm() && !isa<MCConstantExpr>(getImm()))
1205       return true;
1206 
1207     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1208       return false;
1209     // Immediate offset in range [-4095, 4095].
1210     if (!Memory.OffsetImm) return true;
1211     int64_t Val = Memory.OffsetImm->getValue();
1212     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1213   }
1214   bool isPostIdxImm8() const {
1215     if (!isImm()) return false;
1216     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1217     if (!CE) return false;
1218     int64_t Val = CE->getValue();
1219     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1220   }
1221   bool isPostIdxImm8s4() const {
1222     if (!isImm()) return false;
1223     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224     if (!CE) return false;
1225     int64_t Val = CE->getValue();
1226     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1227       (Val == INT32_MIN);
1228   }
1229 
1230   bool isMSRMask() const { return Kind == k_MSRMask; }
1231   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1232 
1233   // NEON operands.
1234   bool isSingleSpacedVectorList() const {
1235     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1236   }
1237   bool isDoubleSpacedVectorList() const {
1238     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1239   }
1240   bool isVecListOneD() const {
1241     if (!isSingleSpacedVectorList()) return false;
1242     return VectorList.Count == 1;
1243   }
1244 
1245   bool isVecListDPair() const {
1246     if (!isSingleSpacedVectorList()) return false;
1247     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1248               .contains(VectorList.RegNum));
1249   }
1250 
1251   bool isVecListThreeD() const {
1252     if (!isSingleSpacedVectorList()) return false;
1253     return VectorList.Count == 3;
1254   }
1255 
1256   bool isVecListFourD() const {
1257     if (!isSingleSpacedVectorList()) return false;
1258     return VectorList.Count == 4;
1259   }
1260 
1261   bool isVecListDPairSpaced() const {
1262     if (isSingleSpacedVectorList()) return false;
1263     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1264               .contains(VectorList.RegNum));
1265   }
1266 
1267   bool isVecListThreeQ() const {
1268     if (!isDoubleSpacedVectorList()) return false;
1269     return VectorList.Count == 3;
1270   }
1271 
1272   bool isVecListFourQ() const {
1273     if (!isDoubleSpacedVectorList()) return false;
1274     return VectorList.Count == 4;
1275   }
1276 
1277   bool isSingleSpacedVectorAllLanes() const {
1278     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1279   }
1280   bool isDoubleSpacedVectorAllLanes() const {
1281     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1282   }
1283   bool isVecListOneDAllLanes() const {
1284     if (!isSingleSpacedVectorAllLanes()) return false;
1285     return VectorList.Count == 1;
1286   }
1287 
1288   bool isVecListDPairAllLanes() const {
1289     if (!isSingleSpacedVectorAllLanes()) return false;
1290     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1291               .contains(VectorList.RegNum));
1292   }
1293 
1294   bool isVecListDPairSpacedAllLanes() const {
1295     if (!isDoubleSpacedVectorAllLanes()) return false;
1296     return VectorList.Count == 2;
1297   }
1298 
1299   bool isVecListThreeDAllLanes() const {
1300     if (!isSingleSpacedVectorAllLanes()) return false;
1301     return VectorList.Count == 3;
1302   }
1303 
1304   bool isVecListThreeQAllLanes() const {
1305     if (!isDoubleSpacedVectorAllLanes()) return false;
1306     return VectorList.Count == 3;
1307   }
1308 
1309   bool isVecListFourDAllLanes() const {
1310     if (!isSingleSpacedVectorAllLanes()) return false;
1311     return VectorList.Count == 4;
1312   }
1313 
1314   bool isVecListFourQAllLanes() const {
1315     if (!isDoubleSpacedVectorAllLanes()) return false;
1316     return VectorList.Count == 4;
1317   }
1318 
1319   bool isSingleSpacedVectorIndexed() const {
1320     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1321   }
1322   bool isDoubleSpacedVectorIndexed() const {
1323     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1324   }
1325   bool isVecListOneDByteIndexed() const {
1326     if (!isSingleSpacedVectorIndexed()) return false;
1327     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1328   }
1329 
1330   bool isVecListOneDHWordIndexed() const {
1331     if (!isSingleSpacedVectorIndexed()) return false;
1332     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1333   }
1334 
1335   bool isVecListOneDWordIndexed() const {
1336     if (!isSingleSpacedVectorIndexed()) return false;
1337     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1338   }
1339 
1340   bool isVecListTwoDByteIndexed() const {
1341     if (!isSingleSpacedVectorIndexed()) return false;
1342     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1343   }
1344 
1345   bool isVecListTwoDHWordIndexed() const {
1346     if (!isSingleSpacedVectorIndexed()) return false;
1347     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1348   }
1349 
1350   bool isVecListTwoQWordIndexed() const {
1351     if (!isDoubleSpacedVectorIndexed()) return false;
1352     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1353   }
1354 
1355   bool isVecListTwoQHWordIndexed() const {
1356     if (!isDoubleSpacedVectorIndexed()) return false;
1357     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1358   }
1359 
1360   bool isVecListTwoDWordIndexed() const {
1361     if (!isSingleSpacedVectorIndexed()) return false;
1362     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1363   }
1364 
1365   bool isVecListThreeDByteIndexed() const {
1366     if (!isSingleSpacedVectorIndexed()) return false;
1367     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1368   }
1369 
1370   bool isVecListThreeDHWordIndexed() const {
1371     if (!isSingleSpacedVectorIndexed()) return false;
1372     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1373   }
1374 
1375   bool isVecListThreeQWordIndexed() const {
1376     if (!isDoubleSpacedVectorIndexed()) return false;
1377     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1378   }
1379 
1380   bool isVecListThreeQHWordIndexed() const {
1381     if (!isDoubleSpacedVectorIndexed()) return false;
1382     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1383   }
1384 
1385   bool isVecListThreeDWordIndexed() const {
1386     if (!isSingleSpacedVectorIndexed()) return false;
1387     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1388   }
1389 
1390   bool isVecListFourDByteIndexed() const {
1391     if (!isSingleSpacedVectorIndexed()) return false;
1392     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1393   }
1394 
1395   bool isVecListFourDHWordIndexed() const {
1396     if (!isSingleSpacedVectorIndexed()) return false;
1397     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1398   }
1399 
1400   bool isVecListFourQWordIndexed() const {
1401     if (!isDoubleSpacedVectorIndexed()) return false;
1402     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1403   }
1404 
1405   bool isVecListFourQHWordIndexed() const {
1406     if (!isDoubleSpacedVectorIndexed()) return false;
1407     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1408   }
1409 
1410   bool isVecListFourDWordIndexed() const {
1411     if (!isSingleSpacedVectorIndexed()) return false;
1412     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1413   }
1414 
1415   bool isVectorIndex8() const {
1416     if (Kind != k_VectorIndex) return false;
1417     return VectorIndex.Val < 8;
1418   }
1419   bool isVectorIndex16() const {
1420     if (Kind != k_VectorIndex) return false;
1421     return VectorIndex.Val < 4;
1422   }
1423   bool isVectorIndex32() const {
1424     if (Kind != k_VectorIndex) return false;
1425     return VectorIndex.Val < 2;
1426   }
1427 
1428   bool isNEONi8splat() const {
1429     if (!isImm()) return false;
1430     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1431     // Must be a constant.
1432     if (!CE) return false;
1433     int64_t Value = CE->getValue();
1434     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1435     // value.
1436     return Value >= 0 && Value < 256;
1437   }
1438 
1439   bool isNEONi16splat() const {
1440     if (!isImm()) return false;
1441     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1442     // Must be a constant.
1443     if (!CE) return false;
1444     int64_t Value = CE->getValue();
1445     // i16 value in the range [0,255] or [0x0100, 0xff00]
1446     return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1447   }
1448 
1449   bool isNEONi32splat() const {
1450     if (!isImm()) return false;
1451     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1452     // Must be a constant.
1453     if (!CE) return false;
1454     int64_t Value = CE->getValue();
1455     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1456     return (Value >= 0 && Value < 256) ||
1457       (Value >= 0x0100 && Value <= 0xff00) ||
1458       (Value >= 0x010000 && Value <= 0xff0000) ||
1459       (Value >= 0x01000000 && Value <= 0xff000000);
1460   }
1461 
1462   bool isNEONi32vmov() const {
1463     if (!isImm()) return false;
1464     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1465     // Must be a constant.
1466     if (!CE) return false;
1467     int64_t Value = CE->getValue();
1468     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1469     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1470     return (Value >= 0 && Value < 256) ||
1471       (Value >= 0x0100 && Value <= 0xff00) ||
1472       (Value >= 0x010000 && Value <= 0xff0000) ||
1473       (Value >= 0x01000000 && Value <= 0xff000000) ||
1474       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1475       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1476   }
1477   bool isNEONi32vmovNeg() const {
1478     if (!isImm()) return false;
1479     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1480     // Must be a constant.
1481     if (!CE) return false;
1482     int64_t Value = ~CE->getValue();
1483     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1484     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1485     return (Value >= 0 && Value < 256) ||
1486       (Value >= 0x0100 && Value <= 0xff00) ||
1487       (Value >= 0x010000 && Value <= 0xff0000) ||
1488       (Value >= 0x01000000 && Value <= 0xff000000) ||
1489       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1490       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1491   }
1492 
1493   bool isNEONi64splat() const {
1494     if (!isImm()) return false;
1495     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1496     // Must be a constant.
1497     if (!CE) return false;
1498     uint64_t Value = CE->getValue();
1499     // i64 value with each byte being either 0 or 0xff.
1500     for (unsigned i = 0; i < 8; ++i)
1501       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1502     return true;
1503   }
1504 
1505   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1506     // Add as immediates when possible.  Null MCExpr = 0.
1507     if (Expr == 0)
1508       Inst.addOperand(MCOperand::CreateImm(0));
1509     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1510       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1511     else
1512       Inst.addOperand(MCOperand::CreateExpr(Expr));
1513   }
1514 
1515   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1516     assert(N == 2 && "Invalid number of operands!");
1517     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1518     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1519     Inst.addOperand(MCOperand::CreateReg(RegNum));
1520   }
1521 
1522   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1523     assert(N == 1 && "Invalid number of operands!");
1524     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1525   }
1526 
1527   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1528     assert(N == 1 && "Invalid number of operands!");
1529     Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1530   }
1531 
1532   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1533     assert(N == 1 && "Invalid number of operands!");
1534     Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1535   }
1536 
1537   void addITMaskOperands(MCInst &Inst, unsigned N) const {
1538     assert(N == 1 && "Invalid number of operands!");
1539     Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1540   }
1541 
1542   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1543     assert(N == 1 && "Invalid number of operands!");
1544     Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1545   }
1546 
1547   void addCCOutOperands(MCInst &Inst, unsigned N) const {
1548     assert(N == 1 && "Invalid number of operands!");
1549     Inst.addOperand(MCOperand::CreateReg(getReg()));
1550   }
1551 
1552   void addRegOperands(MCInst &Inst, unsigned N) const {
1553     assert(N == 1 && "Invalid number of operands!");
1554     Inst.addOperand(MCOperand::CreateReg(getReg()));
1555   }
1556 
1557   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1558     assert(N == 3 && "Invalid number of operands!");
1559     assert(isRegShiftedReg() &&
1560            "addRegShiftedRegOperands() on non RegShiftedReg!");
1561     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1562     Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1563     Inst.addOperand(MCOperand::CreateImm(
1564       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1565   }
1566 
1567   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1568     assert(N == 2 && "Invalid number of operands!");
1569     assert(isRegShiftedImm() &&
1570            "addRegShiftedImmOperands() on non RegShiftedImm!");
1571     Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1572     // Shift of #32 is encoded as 0 where permitted
1573     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1574     Inst.addOperand(MCOperand::CreateImm(
1575       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1576   }
1577 
1578   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1579     assert(N == 1 && "Invalid number of operands!");
1580     Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1581                                          ShifterImm.Imm));
1582   }
1583 
1584   void addRegListOperands(MCInst &Inst, unsigned N) const {
1585     assert(N == 1 && "Invalid number of operands!");
1586     const SmallVectorImpl<unsigned> &RegList = getRegList();
1587     for (SmallVectorImpl<unsigned>::const_iterator
1588            I = RegList.begin(), E = RegList.end(); I != E; ++I)
1589       Inst.addOperand(MCOperand::CreateReg(*I));
1590   }
1591 
1592   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1593     addRegListOperands(Inst, N);
1594   }
1595 
1596   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1597     addRegListOperands(Inst, N);
1598   }
1599 
1600   void addRotImmOperands(MCInst &Inst, unsigned N) const {
1601     assert(N == 1 && "Invalid number of operands!");
1602     // Encoded as val>>3. The printer handles display as 8, 16, 24.
1603     Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1604   }
1605 
1606   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1607     assert(N == 1 && "Invalid number of operands!");
1608     // Munge the lsb/width into a bitfield mask.
1609     unsigned lsb = Bitfield.LSB;
1610     unsigned width = Bitfield.Width;
1611     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1612     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1613                       (32 - (lsb + width)));
1614     Inst.addOperand(MCOperand::CreateImm(Mask));
1615   }
1616 
1617   void addImmOperands(MCInst &Inst, unsigned N) const {
1618     assert(N == 1 && "Invalid number of operands!");
1619     addExpr(Inst, getImm());
1620   }
1621 
1622   void addFBits16Operands(MCInst &Inst, unsigned N) const {
1623     assert(N == 1 && "Invalid number of operands!");
1624     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1625     Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1626   }
1627 
1628   void addFBits32Operands(MCInst &Inst, unsigned N) const {
1629     assert(N == 1 && "Invalid number of operands!");
1630     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1631     Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1632   }
1633 
1634   void addFPImmOperands(MCInst &Inst, unsigned N) const {
1635     assert(N == 1 && "Invalid number of operands!");
1636     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1637     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1638     Inst.addOperand(MCOperand::CreateImm(Val));
1639   }
1640 
1641   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1642     assert(N == 1 && "Invalid number of operands!");
1643     // FIXME: We really want to scale the value here, but the LDRD/STRD
1644     // instruction don't encode operands that way yet.
1645     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1646     Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1647   }
1648 
1649   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1650     assert(N == 1 && "Invalid number of operands!");
1651     // The immediate is scaled by four in the encoding and is stored
1652     // in the MCInst as such. Lop off the low two bits here.
1653     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1654     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1655   }
1656 
1657   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1658     assert(N == 1 && "Invalid number of operands!");
1659     // The immediate is scaled by four in the encoding and is stored
1660     // in the MCInst as such. Lop off the low two bits here.
1661     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1662     Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1663   }
1664 
1665   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1666     assert(N == 1 && "Invalid number of operands!");
1667     // The immediate is scaled by four in the encoding and is stored
1668     // in the MCInst as such. Lop off the low two bits here.
1669     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1670     Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1671   }
1672 
1673   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1674     assert(N == 1 && "Invalid number of operands!");
1675     // The constant encodes as the immediate-1, and we store in the instruction
1676     // the bits as encoded, so subtract off one here.
1677     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1678     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1679   }
1680 
1681   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1682     assert(N == 1 && "Invalid number of operands!");
1683     // The constant encodes as the immediate-1, and we store in the instruction
1684     // the bits as encoded, so subtract off one here.
1685     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1686     Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1687   }
1688 
1689   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1690     assert(N == 1 && "Invalid number of operands!");
1691     // The constant encodes as the immediate, except for 32, which encodes as
1692     // zero.
1693     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1694     unsigned Imm = CE->getValue();
1695     Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1696   }
1697 
1698   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1699     assert(N == 1 && "Invalid number of operands!");
1700     // An ASR value of 32 encodes as 0, so that's how we want to add it to
1701     // the instruction as well.
1702     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1703     int Val = CE->getValue();
1704     Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1705   }
1706 
1707   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1708     assert(N == 1 && "Invalid number of operands!");
1709     // The operand is actually a t2_so_imm, but we have its bitwise
1710     // negation in the assembly source, so twiddle it here.
1711     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1712     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1713   }
1714 
1715   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1716     assert(N == 1 && "Invalid number of operands!");
1717     // The operand is actually a t2_so_imm, but we have its
1718     // negation in the assembly source, so twiddle it here.
1719     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1720     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1721   }
1722 
1723   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1724     assert(N == 1 && "Invalid number of operands!");
1725     // The operand is actually an imm0_4095, but we have its
1726     // negation in the assembly source, so twiddle it here.
1727     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1728     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1729   }
1730 
1731   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1732     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1733       Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1734       return;
1735     }
1736 
1737     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1738     assert(SR && "Unknown value type!");
1739     Inst.addOperand(MCOperand::CreateExpr(SR));
1740   }
1741 
1742   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1743     assert(N == 1 && "Invalid number of operands!");
1744     if (isImm()) {
1745       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1746       if (CE) {
1747         Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1748         return;
1749       }
1750 
1751       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1752       assert(SR && "Unknown value type!");
1753       Inst.addOperand(MCOperand::CreateExpr(SR));
1754       return;
1755     }
1756 
1757     assert(isMem()  && "Unknown value type!");
1758     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1759     Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1760   }
1761 
1762   void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1763     assert(N == 1 && "Invalid number of operands!");
1764     // The operand is actually a so_imm, but we have its bitwise
1765     // negation in the assembly source, so twiddle it here.
1766     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1767     Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1768   }
1769 
1770   void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1771     assert(N == 1 && "Invalid number of operands!");
1772     // The operand is actually a so_imm, but we have its
1773     // negation in the assembly source, so twiddle it here.
1774     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1775     Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1776   }
1777 
1778   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1779     assert(N == 1 && "Invalid number of operands!");
1780     Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1781   }
1782 
1783   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1784     assert(N == 1 && "Invalid number of operands!");
1785     Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1786   }
1787 
1788   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1789     assert(N == 1 && "Invalid number of operands!");
1790     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1791   }
1792 
1793   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1794     assert(N == 1 && "Invalid number of operands!");
1795     int32_t Imm = Memory.OffsetImm->getValue();
1796     Inst.addOperand(MCOperand::CreateImm(Imm));
1797   }
1798 
1799   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1800     assert(N == 1 && "Invalid number of operands!");
1801     assert(isImm() && "Not an immediate!");
1802 
1803     // If we have an immediate that's not a constant, treat it as a label
1804     // reference needing a fixup.
1805     if (!isa<MCConstantExpr>(getImm())) {
1806       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1807       return;
1808     }
1809 
1810     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1811     int Val = CE->getValue();
1812     Inst.addOperand(MCOperand::CreateImm(Val));
1813   }
1814 
1815   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1816     assert(N == 2 && "Invalid number of operands!");
1817     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1818     Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1819   }
1820 
1821   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1822     assert(N == 3 && "Invalid number of operands!");
1823     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1824     if (!Memory.OffsetRegNum) {
1825       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1826       // Special case for #-0
1827       if (Val == INT32_MIN) Val = 0;
1828       if (Val < 0) Val = -Val;
1829       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1830     } else {
1831       // For register offset, we encode the shift type and negation flag
1832       // here.
1833       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1834                               Memory.ShiftImm, Memory.ShiftType);
1835     }
1836     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1837     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1838     Inst.addOperand(MCOperand::CreateImm(Val));
1839   }
1840 
1841   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1842     assert(N == 2 && "Invalid number of operands!");
1843     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1844     assert(CE && "non-constant AM2OffsetImm operand!");
1845     int32_t Val = CE->getValue();
1846     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1847     // Special case for #-0
1848     if (Val == INT32_MIN) Val = 0;
1849     if (Val < 0) Val = -Val;
1850     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1851     Inst.addOperand(MCOperand::CreateReg(0));
1852     Inst.addOperand(MCOperand::CreateImm(Val));
1853   }
1854 
1855   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1856     assert(N == 3 && "Invalid number of operands!");
1857     // If we have an immediate that's not a constant, treat it as a label
1858     // reference needing a fixup. If it is a constant, it's something else
1859     // and we reject it.
1860     if (isImm()) {
1861       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1862       Inst.addOperand(MCOperand::CreateReg(0));
1863       Inst.addOperand(MCOperand::CreateImm(0));
1864       return;
1865     }
1866 
1867     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1868     if (!Memory.OffsetRegNum) {
1869       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1870       // Special case for #-0
1871       if (Val == INT32_MIN) Val = 0;
1872       if (Val < 0) Val = -Val;
1873       Val = ARM_AM::getAM3Opc(AddSub, Val);
1874     } else {
1875       // For register offset, we encode the shift type and negation flag
1876       // here.
1877       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1878     }
1879     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1880     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1881     Inst.addOperand(MCOperand::CreateImm(Val));
1882   }
1883 
1884   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1885     assert(N == 2 && "Invalid number of operands!");
1886     if (Kind == k_PostIndexRegister) {
1887       int32_t Val =
1888         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1889       Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1890       Inst.addOperand(MCOperand::CreateImm(Val));
1891       return;
1892     }
1893 
1894     // Constant offset.
1895     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1896     int32_t Val = CE->getValue();
1897     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1898     // Special case for #-0
1899     if (Val == INT32_MIN) Val = 0;
1900     if (Val < 0) Val = -Val;
1901     Val = ARM_AM::getAM3Opc(AddSub, Val);
1902     Inst.addOperand(MCOperand::CreateReg(0));
1903     Inst.addOperand(MCOperand::CreateImm(Val));
1904   }
1905 
1906   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1907     assert(N == 2 && "Invalid number of operands!");
1908     // If we have an immediate that's not a constant, treat it as a label
1909     // reference needing a fixup. If it is a constant, it's something else
1910     // and we reject it.
1911     if (isImm()) {
1912       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1913       Inst.addOperand(MCOperand::CreateImm(0));
1914       return;
1915     }
1916 
1917     // The lower two bits are always zero and as such are not encoded.
1918     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1919     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1920     // Special case for #-0
1921     if (Val == INT32_MIN) Val = 0;
1922     if (Val < 0) Val = -Val;
1923     Val = ARM_AM::getAM5Opc(AddSub, Val);
1924     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1925     Inst.addOperand(MCOperand::CreateImm(Val));
1926   }
1927 
1928   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1929     assert(N == 2 && "Invalid number of operands!");
1930     // If we have an immediate that's not a constant, treat it as a label
1931     // reference needing a fixup. If it is a constant, it's something else
1932     // and we reject it.
1933     if (isImm()) {
1934       Inst.addOperand(MCOperand::CreateExpr(getImm()));
1935       Inst.addOperand(MCOperand::CreateImm(0));
1936       return;
1937     }
1938 
1939     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1940     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1941     Inst.addOperand(MCOperand::CreateImm(Val));
1942   }
1943 
1944   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1945     assert(N == 2 && "Invalid number of operands!");
1946     // The lower two bits are always zero and as such are not encoded.
1947     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1948     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1949     Inst.addOperand(MCOperand::CreateImm(Val));
1950   }
1951 
1952   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1953     assert(N == 2 && "Invalid number of operands!");
1954     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1955     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1956     Inst.addOperand(MCOperand::CreateImm(Val));
1957   }
1958 
1959   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1960     addMemImm8OffsetOperands(Inst, N);
1961   }
1962 
1963   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1964     addMemImm8OffsetOperands(Inst, N);
1965   }
1966 
1967   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1968     assert(N == 2 && "Invalid number of operands!");
1969     // If this is an immediate, it's a label reference.
1970     if (isImm()) {
1971       addExpr(Inst, getImm());
1972       Inst.addOperand(MCOperand::CreateImm(0));
1973       return;
1974     }
1975 
1976     // Otherwise, it's a normal memory reg+offset.
1977     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1978     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1979     Inst.addOperand(MCOperand::CreateImm(Val));
1980   }
1981 
1982   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1983     assert(N == 2 && "Invalid number of operands!");
1984     // If this is an immediate, it's a label reference.
1985     if (isImm()) {
1986       addExpr(Inst, getImm());
1987       Inst.addOperand(MCOperand::CreateImm(0));
1988       return;
1989     }
1990 
1991     // Otherwise, it's a normal memory reg+offset.
1992     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1993     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1994     Inst.addOperand(MCOperand::CreateImm(Val));
1995   }
1996 
1997   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1998     assert(N == 2 && "Invalid number of operands!");
1999     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2000     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2001   }
2002 
2003   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2004     assert(N == 2 && "Invalid number of operands!");
2005     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2006     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2007   }
2008 
2009   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2010     assert(N == 3 && "Invalid number of operands!");
2011     unsigned Val =
2012       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2013                         Memory.ShiftImm, Memory.ShiftType);
2014     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2015     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2016     Inst.addOperand(MCOperand::CreateImm(Val));
2017   }
2018 
2019   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2020     assert(N == 3 && "Invalid number of operands!");
2021     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2022     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2023     Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2024   }
2025 
2026   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2027     assert(N == 2 && "Invalid number of operands!");
2028     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2029     Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2030   }
2031 
2032   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2033     assert(N == 2 && "Invalid number of operands!");
2034     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2035     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2036     Inst.addOperand(MCOperand::CreateImm(Val));
2037   }
2038 
2039   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2040     assert(N == 2 && "Invalid number of operands!");
2041     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2042     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2043     Inst.addOperand(MCOperand::CreateImm(Val));
2044   }
2045 
2046   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2047     assert(N == 2 && "Invalid number of operands!");
2048     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2049     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2050     Inst.addOperand(MCOperand::CreateImm(Val));
2051   }
2052 
2053   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2054     assert(N == 2 && "Invalid number of operands!");
2055     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2056     Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2057     Inst.addOperand(MCOperand::CreateImm(Val));
2058   }
2059 
2060   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2061     assert(N == 1 && "Invalid number of operands!");
2062     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2063     assert(CE && "non-constant post-idx-imm8 operand!");
2064     int Imm = CE->getValue();
2065     bool isAdd = Imm >= 0;
2066     if (Imm == INT32_MIN) Imm = 0;
2067     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2068     Inst.addOperand(MCOperand::CreateImm(Imm));
2069   }
2070 
2071   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2072     assert(N == 1 && "Invalid number of operands!");
2073     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2074     assert(CE && "non-constant post-idx-imm8s4 operand!");
2075     int Imm = CE->getValue();
2076     bool isAdd = Imm >= 0;
2077     if (Imm == INT32_MIN) Imm = 0;
2078     // Immediate is scaled by 4.
2079     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2080     Inst.addOperand(MCOperand::CreateImm(Imm));
2081   }
2082 
2083   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2084     assert(N == 2 && "Invalid number of operands!");
2085     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2086     Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2087   }
2088 
2089   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2090     assert(N == 2 && "Invalid number of operands!");
2091     Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2092     // The sign, shift type, and shift amount are encoded in a single operand
2093     // using the AM2 encoding helpers.
2094     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2095     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2096                                      PostIdxReg.ShiftTy);
2097     Inst.addOperand(MCOperand::CreateImm(Imm));
2098   }
2099 
2100   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2101     assert(N == 1 && "Invalid number of operands!");
2102     Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2103   }
2104 
2105   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2106     assert(N == 1 && "Invalid number of operands!");
2107     Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2108   }
2109 
2110   void addVecListOperands(MCInst &Inst, unsigned N) const {
2111     assert(N == 1 && "Invalid number of operands!");
2112     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2113   }
2114 
2115   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2116     assert(N == 2 && "Invalid number of operands!");
2117     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2118     Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2119   }
2120 
2121   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2122     assert(N == 1 && "Invalid number of operands!");
2123     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2124   }
2125 
2126   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2127     assert(N == 1 && "Invalid number of operands!");
2128     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2129   }
2130 
2131   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2132     assert(N == 1 && "Invalid number of operands!");
2133     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2134   }
2135 
2136   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2137     assert(N == 1 && "Invalid number of operands!");
2138     // The immediate encodes the type of constant as well as the value.
2139     // Mask in that this is an i8 splat.
2140     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2141     Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2142   }
2143 
2144   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2145     assert(N == 1 && "Invalid number of operands!");
2146     // The immediate encodes the type of constant as well as the value.
2147     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2148     unsigned Value = CE->getValue();
2149     if (Value >= 256)
2150       Value = (Value >> 8) | 0xa00;
2151     else
2152       Value |= 0x800;
2153     Inst.addOperand(MCOperand::CreateImm(Value));
2154   }
2155 
2156   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2157     assert(N == 1 && "Invalid number of operands!");
2158     // The immediate encodes the type of constant as well as the value.
2159     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2160     unsigned Value = CE->getValue();
2161     if (Value >= 256 && Value <= 0xff00)
2162       Value = (Value >> 8) | 0x200;
2163     else if (Value > 0xffff && Value <= 0xff0000)
2164       Value = (Value >> 16) | 0x400;
2165     else if (Value > 0xffffff)
2166       Value = (Value >> 24) | 0x600;
2167     Inst.addOperand(MCOperand::CreateImm(Value));
2168   }
2169 
2170   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2171     assert(N == 1 && "Invalid number of operands!");
2172     // The immediate encodes the type of constant as well as the value.
2173     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2174     unsigned Value = CE->getValue();
2175     if (Value >= 256 && Value <= 0xffff)
2176       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2177     else if (Value > 0xffff && Value <= 0xffffff)
2178       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2179     else if (Value > 0xffffff)
2180       Value = (Value >> 24) | 0x600;
2181     Inst.addOperand(MCOperand::CreateImm(Value));
2182   }
2183 
2184   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2185     assert(N == 1 && "Invalid number of operands!");
2186     // The immediate encodes the type of constant as well as the value.
2187     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2188     unsigned Value = ~CE->getValue();
2189     if (Value >= 256 && Value <= 0xffff)
2190       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2191     else if (Value > 0xffff && Value <= 0xffffff)
2192       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2193     else if (Value > 0xffffff)
2194       Value = (Value >> 24) | 0x600;
2195     Inst.addOperand(MCOperand::CreateImm(Value));
2196   }
2197 
2198   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2199     assert(N == 1 && "Invalid number of operands!");
2200     // The immediate encodes the type of constant as well as the value.
2201     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2202     uint64_t Value = CE->getValue();
2203     unsigned Imm = 0;
2204     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2205       Imm |= (Value & 1) << i;
2206     }
2207     Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2208   }
2209 
2210   virtual void print(raw_ostream &OS) const;
2211 
2212   static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2213     ARMOperand *Op = new ARMOperand(k_ITCondMask);
2214     Op->ITMask.Mask = Mask;
2215     Op->StartLoc = S;
2216     Op->EndLoc = S;
2217     return Op;
2218   }
2219 
2220   static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2221     ARMOperand *Op = new ARMOperand(k_CondCode);
2222     Op->CC.Val = CC;
2223     Op->StartLoc = S;
2224     Op->EndLoc = S;
2225     return Op;
2226   }
2227 
2228   static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2229     ARMOperand *Op = new ARMOperand(k_CoprocNum);
2230     Op->Cop.Val = CopVal;
2231     Op->StartLoc = S;
2232     Op->EndLoc = S;
2233     return Op;
2234   }
2235 
2236   static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2237     ARMOperand *Op = new ARMOperand(k_CoprocReg);
2238     Op->Cop.Val = CopVal;
2239     Op->StartLoc = S;
2240     Op->EndLoc = S;
2241     return Op;
2242   }
2243 
2244   static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2245     ARMOperand *Op = new ARMOperand(k_CoprocOption);
2246     Op->Cop.Val = Val;
2247     Op->StartLoc = S;
2248     Op->EndLoc = E;
2249     return Op;
2250   }
2251 
2252   static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2253     ARMOperand *Op = new ARMOperand(k_CCOut);
2254     Op->Reg.RegNum = RegNum;
2255     Op->StartLoc = S;
2256     Op->EndLoc = S;
2257     return Op;
2258   }
2259 
2260   static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2261     ARMOperand *Op = new ARMOperand(k_Token);
2262     Op->Tok.Data = Str.data();
2263     Op->Tok.Length = Str.size();
2264     Op->StartLoc = S;
2265     Op->EndLoc = S;
2266     return Op;
2267   }
2268 
2269   static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2270     ARMOperand *Op = new ARMOperand(k_Register);
2271     Op->Reg.RegNum = RegNum;
2272     Op->StartLoc = S;
2273     Op->EndLoc = E;
2274     return Op;
2275   }
2276 
2277   static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2278                                            unsigned SrcReg,
2279                                            unsigned ShiftReg,
2280                                            unsigned ShiftImm,
2281                                            SMLoc S, SMLoc E) {
2282     ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2283     Op->RegShiftedReg.ShiftTy = ShTy;
2284     Op->RegShiftedReg.SrcReg = SrcReg;
2285     Op->RegShiftedReg.ShiftReg = ShiftReg;
2286     Op->RegShiftedReg.ShiftImm = ShiftImm;
2287     Op->StartLoc = S;
2288     Op->EndLoc = E;
2289     return Op;
2290   }
2291 
2292   static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2293                                             unsigned SrcReg,
2294                                             unsigned ShiftImm,
2295                                             SMLoc S, SMLoc E) {
2296     ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2297     Op->RegShiftedImm.ShiftTy = ShTy;
2298     Op->RegShiftedImm.SrcReg = SrcReg;
2299     Op->RegShiftedImm.ShiftImm = ShiftImm;
2300     Op->StartLoc = S;
2301     Op->EndLoc = E;
2302     return Op;
2303   }
2304 
2305   static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2306                                    SMLoc S, SMLoc E) {
2307     ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2308     Op->ShifterImm.isASR = isASR;
2309     Op->ShifterImm.Imm = Imm;
2310     Op->StartLoc = S;
2311     Op->EndLoc = E;
2312     return Op;
2313   }
2314 
2315   static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2316     ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2317     Op->RotImm.Imm = Imm;
2318     Op->StartLoc = S;
2319     Op->EndLoc = E;
2320     return Op;
2321   }
2322 
2323   static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2324                                     SMLoc S, SMLoc E) {
2325     ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2326     Op->Bitfield.LSB = LSB;
2327     Op->Bitfield.Width = Width;
2328     Op->StartLoc = S;
2329     Op->EndLoc = E;
2330     return Op;
2331   }
2332 
2333   static ARMOperand *
2334   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2335                 SMLoc StartLoc, SMLoc EndLoc) {
2336     assert (Regs.size() > 0 && "RegList contains no registers?");
2337     KindTy Kind = k_RegisterList;
2338 
2339     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2340       Kind = k_DPRRegisterList;
2341     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2342              contains(Regs.front().second))
2343       Kind = k_SPRRegisterList;
2344 
2345     // Sort based on the register encoding values.
2346     array_pod_sort(Regs.begin(), Regs.end());
2347 
2348     ARMOperand *Op = new ARMOperand(Kind);
2349     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2350            I = Regs.begin(), E = Regs.end(); I != E; ++I)
2351       Op->Registers.push_back(I->second);
2352     Op->StartLoc = StartLoc;
2353     Op->EndLoc = EndLoc;
2354     return Op;
2355   }
2356 
2357   static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2358                                       bool isDoubleSpaced, SMLoc S, SMLoc E) {
2359     ARMOperand *Op = new ARMOperand(k_VectorList);
2360     Op->VectorList.RegNum = RegNum;
2361     Op->VectorList.Count = Count;
2362     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2363     Op->StartLoc = S;
2364     Op->EndLoc = E;
2365     return Op;
2366   }
2367 
2368   static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2369                                               bool isDoubleSpaced,
2370                                               SMLoc S, SMLoc E) {
2371     ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2372     Op->VectorList.RegNum = RegNum;
2373     Op->VectorList.Count = Count;
2374     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2375     Op->StartLoc = S;
2376     Op->EndLoc = E;
2377     return Op;
2378   }
2379 
2380   static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2381                                              unsigned Index,
2382                                              bool isDoubleSpaced,
2383                                              SMLoc S, SMLoc E) {
2384     ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2385     Op->VectorList.RegNum = RegNum;
2386     Op->VectorList.Count = Count;
2387     Op->VectorList.LaneIndex = Index;
2388     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2389     Op->StartLoc = S;
2390     Op->EndLoc = E;
2391     return Op;
2392   }
2393 
2394   static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2395                                        MCContext &Ctx) {
2396     ARMOperand *Op = new ARMOperand(k_VectorIndex);
2397     Op->VectorIndex.Val = Idx;
2398     Op->StartLoc = S;
2399     Op->EndLoc = E;
2400     return Op;
2401   }
2402 
2403   static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2404     ARMOperand *Op = new ARMOperand(k_Immediate);
2405     Op->Imm.Val = Val;
2406     Op->StartLoc = S;
2407     Op->EndLoc = E;
2408     return Op;
2409   }
2410 
2411   static ARMOperand *CreateMem(unsigned BaseRegNum,
2412                                const MCConstantExpr *OffsetImm,
2413                                unsigned OffsetRegNum,
2414                                ARM_AM::ShiftOpc ShiftType,
2415                                unsigned ShiftImm,
2416                                unsigned Alignment,
2417                                bool isNegative,
2418                                SMLoc S, SMLoc E) {
2419     ARMOperand *Op = new ARMOperand(k_Memory);
2420     Op->Memory.BaseRegNum = BaseRegNum;
2421     Op->Memory.OffsetImm = OffsetImm;
2422     Op->Memory.OffsetRegNum = OffsetRegNum;
2423     Op->Memory.ShiftType = ShiftType;
2424     Op->Memory.ShiftImm = ShiftImm;
2425     Op->Memory.Alignment = Alignment;
2426     Op->Memory.isNegative = isNegative;
2427     Op->StartLoc = S;
2428     Op->EndLoc = E;
2429     return Op;
2430   }
2431 
2432   static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2433                                       ARM_AM::ShiftOpc ShiftTy,
2434                                       unsigned ShiftImm,
2435                                       SMLoc S, SMLoc E) {
2436     ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2437     Op->PostIdxReg.RegNum = RegNum;
2438     Op->PostIdxReg.isAdd = isAdd;
2439     Op->PostIdxReg.ShiftTy = ShiftTy;
2440     Op->PostIdxReg.ShiftImm = ShiftImm;
2441     Op->StartLoc = S;
2442     Op->EndLoc = E;
2443     return Op;
2444   }
2445 
2446   static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2447     ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2448     Op->MBOpt.Val = Opt;
2449     Op->StartLoc = S;
2450     Op->EndLoc = S;
2451     return Op;
2452   }
2453 
2454   static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2455                                               SMLoc S) {
2456     ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2457     Op->ISBOpt.Val = Opt;
2458     Op->StartLoc = S;
2459     Op->EndLoc = S;
2460     return Op;
2461   }
2462 
2463   static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2464     ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2465     Op->IFlags.Val = IFlags;
2466     Op->StartLoc = S;
2467     Op->EndLoc = S;
2468     return Op;
2469   }
2470 
2471   static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2472     ARMOperand *Op = new ARMOperand(k_MSRMask);
2473     Op->MMask.Val = MMask;
2474     Op->StartLoc = S;
2475     Op->EndLoc = S;
2476     return Op;
2477   }
2478 };
2479 
2480 } // end anonymous namespace.
2481 
2482 void ARMOperand::print(raw_ostream &OS) const {
2483   switch (Kind) {
2484   case k_CondCode:
2485     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2486     break;
2487   case k_CCOut:
2488     OS << "<ccout " << getReg() << ">";
2489     break;
2490   case k_ITCondMask: {
2491     static const char *const MaskStr[] = {
2492       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2493       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2494     };
2495     assert((ITMask.Mask & 0xf) == ITMask.Mask);
2496     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2497     break;
2498   }
2499   case k_CoprocNum:
2500     OS << "<coprocessor number: " << getCoproc() << ">";
2501     break;
2502   case k_CoprocReg:
2503     OS << "<coprocessor register: " << getCoproc() << ">";
2504     break;
2505   case k_CoprocOption:
2506     OS << "<coprocessor option: " << CoprocOption.Val << ">";
2507     break;
2508   case k_MSRMask:
2509     OS << "<mask: " << getMSRMask() << ">";
2510     break;
2511   case k_Immediate:
2512     getImm()->print(OS);
2513     break;
2514   case k_MemBarrierOpt:
2515     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2516     break;
2517   case k_InstSyncBarrierOpt:
2518     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2519     break;
2520   case k_Memory:
2521     OS << "<memory "
2522        << " base:" << Memory.BaseRegNum;
2523     OS << ">";
2524     break;
2525   case k_PostIndexRegister:
2526     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2527        << PostIdxReg.RegNum;
2528     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2529       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2530          << PostIdxReg.ShiftImm;
2531     OS << ">";
2532     break;
2533   case k_ProcIFlags: {
2534     OS << "<ARM_PROC::";
2535     unsigned IFlags = getProcIFlags();
2536     for (int i=2; i >= 0; --i)
2537       if (IFlags & (1 << i))
2538         OS << ARM_PROC::IFlagsToString(1 << i);
2539     OS << ">";
2540     break;
2541   }
2542   case k_Register:
2543     OS << "<register " << getReg() << ">";
2544     break;
2545   case k_ShifterImmediate:
2546     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2547        << " #" << ShifterImm.Imm << ">";
2548     break;
2549   case k_ShiftedRegister:
2550     OS << "<so_reg_reg "
2551        << RegShiftedReg.SrcReg << " "
2552        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2553        << " " << RegShiftedReg.ShiftReg << ">";
2554     break;
2555   case k_ShiftedImmediate:
2556     OS << "<so_reg_imm "
2557        << RegShiftedImm.SrcReg << " "
2558        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2559        << " #" << RegShiftedImm.ShiftImm << ">";
2560     break;
2561   case k_RotateImmediate:
2562     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2563     break;
2564   case k_BitfieldDescriptor:
2565     OS << "<bitfield " << "lsb: " << Bitfield.LSB
2566        << ", width: " << Bitfield.Width << ">";
2567     break;
2568   case k_RegisterList:
2569   case k_DPRRegisterList:
2570   case k_SPRRegisterList: {
2571     OS << "<register_list ";
2572 
2573     const SmallVectorImpl<unsigned> &RegList = getRegList();
2574     for (SmallVectorImpl<unsigned>::const_iterator
2575            I = RegList.begin(), E = RegList.end(); I != E; ) {
2576       OS << *I;
2577       if (++I < E) OS << ", ";
2578     }
2579 
2580     OS << ">";
2581     break;
2582   }
2583   case k_VectorList:
2584     OS << "<vector_list " << VectorList.Count << " * "
2585        << VectorList.RegNum << ">";
2586     break;
2587   case k_VectorListAllLanes:
2588     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2589        << VectorList.RegNum << ">";
2590     break;
2591   case k_VectorListIndexed:
2592     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2593        << VectorList.Count << " * " << VectorList.RegNum << ">";
2594     break;
2595   case k_Token:
2596     OS << "'" << getToken() << "'";
2597     break;
2598   case k_VectorIndex:
2599     OS << "<vectorindex " << getVectorIndex() << ">";
2600     break;
2601   }
2602 }
2603 
2604 /// @name Auto-generated Match Functions
2605 /// {
2606 
2607 static unsigned MatchRegisterName(StringRef Name);
2608 
2609 /// }
2610 
2611 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2612                                  SMLoc &StartLoc, SMLoc &EndLoc) {
2613   StartLoc = Parser.getTok().getLoc();
2614   EndLoc = Parser.getTok().getEndLoc();
2615   RegNo = tryParseRegister();
2616 
2617   return (RegNo == (unsigned)-1);
2618 }
2619 
2620 /// Try to parse a register name.  The token must be an Identifier when called,
2621 /// and if it is a register name the token is eaten and the register number is
2622 /// returned.  Otherwise return -1.
2623 ///
2624 int ARMAsmParser::tryParseRegister() {
2625   const AsmToken &Tok = Parser.getTok();
2626   if (Tok.isNot(AsmToken::Identifier)) return -1;
2627 
2628   std::string lowerCase = Tok.getString().lower();
2629   unsigned RegNum = MatchRegisterName(lowerCase);
2630   if (!RegNum) {
2631     RegNum = StringSwitch<unsigned>(lowerCase)
2632       .Case("r13", ARM::SP)
2633       .Case("r14", ARM::LR)
2634       .Case("r15", ARM::PC)
2635       .Case("ip", ARM::R12)
2636       // Additional register name aliases for 'gas' compatibility.
2637       .Case("a1", ARM::R0)
2638       .Case("a2", ARM::R1)
2639       .Case("a3", ARM::R2)
2640       .Case("a4", ARM::R3)
2641       .Case("v1", ARM::R4)
2642       .Case("v2", ARM::R5)
2643       .Case("v3", ARM::R6)
2644       .Case("v4", ARM::R7)
2645       .Case("v5", ARM::R8)
2646       .Case("v6", ARM::R9)
2647       .Case("v7", ARM::R10)
2648       .Case("v8", ARM::R11)
2649       .Case("sb", ARM::R9)
2650       .Case("sl", ARM::R10)
2651       .Case("fp", ARM::R11)
2652       .Default(0);
2653   }
2654   if (!RegNum) {
2655     // Check for aliases registered via .req. Canonicalize to lower case.
2656     // That's more consistent since register names are case insensitive, and
2657     // it's how the original entry was passed in from MC/MCParser/AsmParser.
2658     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2659     // If no match, return failure.
2660     if (Entry == RegisterReqs.end())
2661       return -1;
2662     Parser.Lex(); // Eat identifier token.
2663     return Entry->getValue();
2664   }
2665 
2666   Parser.Lex(); // Eat identifier token.
2667 
2668   return RegNum;
2669 }
2670 
2671 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2672 // If a recoverable error occurs, return 1. If an irrecoverable error
2673 // occurs, return -1. An irrecoverable error is one where tokens have been
2674 // consumed in the process of trying to parse the shifter (i.e., when it is
2675 // indeed a shifter operand, but malformed).
2676 int ARMAsmParser::tryParseShiftRegister(
2677                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2678   SMLoc S = Parser.getTok().getLoc();
2679   const AsmToken &Tok = Parser.getTok();
2680   assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2681 
2682   std::string lowerCase = Tok.getString().lower();
2683   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2684       .Case("asl", ARM_AM::lsl)
2685       .Case("lsl", ARM_AM::lsl)
2686       .Case("lsr", ARM_AM::lsr)
2687       .Case("asr", ARM_AM::asr)
2688       .Case("ror", ARM_AM::ror)
2689       .Case("rrx", ARM_AM::rrx)
2690       .Default(ARM_AM::no_shift);
2691 
2692   if (ShiftTy == ARM_AM::no_shift)
2693     return 1;
2694 
2695   Parser.Lex(); // Eat the operator.
2696 
2697   // The source register for the shift has already been added to the
2698   // operand list, so we need to pop it off and combine it into the shifted
2699   // register operand instead.
2700   OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2701   if (!PrevOp->isReg())
2702     return Error(PrevOp->getStartLoc(), "shift must be of a register");
2703   int SrcReg = PrevOp->getReg();
2704 
2705   SMLoc EndLoc;
2706   int64_t Imm = 0;
2707   int ShiftReg = 0;
2708   if (ShiftTy == ARM_AM::rrx) {
2709     // RRX Doesn't have an explicit shift amount. The encoder expects
2710     // the shift register to be the same as the source register. Seems odd,
2711     // but OK.
2712     ShiftReg = SrcReg;
2713   } else {
2714     // Figure out if this is shifted by a constant or a register (for non-RRX).
2715     if (Parser.getTok().is(AsmToken::Hash) ||
2716         Parser.getTok().is(AsmToken::Dollar)) {
2717       Parser.Lex(); // Eat hash.
2718       SMLoc ImmLoc = Parser.getTok().getLoc();
2719       const MCExpr *ShiftExpr = 0;
2720       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2721         Error(ImmLoc, "invalid immediate shift value");
2722         return -1;
2723       }
2724       // The expression must be evaluatable as an immediate.
2725       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2726       if (!CE) {
2727         Error(ImmLoc, "invalid immediate shift value");
2728         return -1;
2729       }
2730       // Range check the immediate.
2731       // lsl, ror: 0 <= imm <= 31
2732       // lsr, asr: 0 <= imm <= 32
2733       Imm = CE->getValue();
2734       if (Imm < 0 ||
2735           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2736           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2737         Error(ImmLoc, "immediate shift value out of range");
2738         return -1;
2739       }
2740       // shift by zero is a nop. Always send it through as lsl.
2741       // ('as' compatibility)
2742       if (Imm == 0)
2743         ShiftTy = ARM_AM::lsl;
2744     } else if (Parser.getTok().is(AsmToken::Identifier)) {
2745       SMLoc L = Parser.getTok().getLoc();
2746       EndLoc = Parser.getTok().getEndLoc();
2747       ShiftReg = tryParseRegister();
2748       if (ShiftReg == -1) {
2749         Error (L, "expected immediate or register in shift operand");
2750         return -1;
2751       }
2752     } else {
2753       Error (Parser.getTok().getLoc(),
2754                     "expected immediate or register in shift operand");
2755       return -1;
2756     }
2757   }
2758 
2759   if (ShiftReg && ShiftTy != ARM_AM::rrx)
2760     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2761                                                          ShiftReg, Imm,
2762                                                          S, EndLoc));
2763   else
2764     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2765                                                           S, EndLoc));
2766 
2767   return 0;
2768 }
2769 
2770 
2771 /// Try to parse a register name.  The token must be an Identifier when called.
2772 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2773 /// if there is a "writeback". 'true' if it's not a register.
2774 ///
2775 /// TODO this is likely to change to allow different register types and or to
2776 /// parse for a specific register type.
2777 bool ARMAsmParser::
2778 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2779   const AsmToken &RegTok = Parser.getTok();
2780   int RegNo = tryParseRegister();
2781   if (RegNo == -1)
2782     return true;
2783 
2784   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2785                                            RegTok.getEndLoc()));
2786 
2787   const AsmToken &ExclaimTok = Parser.getTok();
2788   if (ExclaimTok.is(AsmToken::Exclaim)) {
2789     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2790                                                ExclaimTok.getLoc()));
2791     Parser.Lex(); // Eat exclaim token
2792     return false;
2793   }
2794 
2795   // Also check for an index operand. This is only legal for vector registers,
2796   // but that'll get caught OK in operand matching, so we don't need to
2797   // explicitly filter everything else out here.
2798   if (Parser.getTok().is(AsmToken::LBrac)) {
2799     SMLoc SIdx = Parser.getTok().getLoc();
2800     Parser.Lex(); // Eat left bracket token.
2801 
2802     const MCExpr *ImmVal;
2803     if (getParser().parseExpression(ImmVal))
2804       return true;
2805     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2806     if (!MCE)
2807       return TokError("immediate value expected for vector index");
2808 
2809     if (Parser.getTok().isNot(AsmToken::RBrac))
2810       return Error(Parser.getTok().getLoc(), "']' expected");
2811 
2812     SMLoc E = Parser.getTok().getEndLoc();
2813     Parser.Lex(); // Eat right bracket token.
2814 
2815     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2816                                                      SIdx, E,
2817                                                      getContext()));
2818   }
2819 
2820   return false;
2821 }
2822 
2823 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2824 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2825 /// "c5", ...
2826 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2827   // Use the same layout as the tablegen'erated register name matcher. Ugly,
2828   // but efficient.
2829   switch (Name.size()) {
2830   default: return -1;
2831   case 2:
2832     if (Name[0] != CoprocOp)
2833       return -1;
2834     switch (Name[1]) {
2835     default:  return -1;
2836     case '0': return 0;
2837     case '1': return 1;
2838     case '2': return 2;
2839     case '3': return 3;
2840     case '4': return 4;
2841     case '5': return 5;
2842     case '6': return 6;
2843     case '7': return 7;
2844     case '8': return 8;
2845     case '9': return 9;
2846     }
2847   case 3:
2848     if (Name[0] != CoprocOp || Name[1] != '1')
2849       return -1;
2850     switch (Name[2]) {
2851     default:  return -1;
2852     case '0': return 10;
2853     case '1': return 11;
2854     case '2': return 12;
2855     case '3': return 13;
2856     case '4': return 14;
2857     case '5': return 15;
2858     }
2859   }
2860 }
2861 
2862 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2863 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2864 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2865   SMLoc S = Parser.getTok().getLoc();
2866   const AsmToken &Tok = Parser.getTok();
2867   if (!Tok.is(AsmToken::Identifier))
2868     return MatchOperand_NoMatch;
2869   unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2870     .Case("eq", ARMCC::EQ)
2871     .Case("ne", ARMCC::NE)
2872     .Case("hs", ARMCC::HS)
2873     .Case("cs", ARMCC::HS)
2874     .Case("lo", ARMCC::LO)
2875     .Case("cc", ARMCC::LO)
2876     .Case("mi", ARMCC::MI)
2877     .Case("pl", ARMCC::PL)
2878     .Case("vs", ARMCC::VS)
2879     .Case("vc", ARMCC::VC)
2880     .Case("hi", ARMCC::HI)
2881     .Case("ls", ARMCC::LS)
2882     .Case("ge", ARMCC::GE)
2883     .Case("lt", ARMCC::LT)
2884     .Case("gt", ARMCC::GT)
2885     .Case("le", ARMCC::LE)
2886     .Case("al", ARMCC::AL)
2887     .Default(~0U);
2888   if (CC == ~0U)
2889     return MatchOperand_NoMatch;
2890   Parser.Lex(); // Eat the token.
2891 
2892   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2893 
2894   return MatchOperand_Success;
2895 }
2896 
2897 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2898 /// token must be an Identifier when called, and if it is a coprocessor
2899 /// number, the token is eaten and the operand is added to the operand list.
2900 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2901 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2902   SMLoc S = Parser.getTok().getLoc();
2903   const AsmToken &Tok = Parser.getTok();
2904   if (Tok.isNot(AsmToken::Identifier))
2905     return MatchOperand_NoMatch;
2906 
2907   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2908   if (Num == -1)
2909     return MatchOperand_NoMatch;
2910 
2911   Parser.Lex(); // Eat identifier token.
2912   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2913   return MatchOperand_Success;
2914 }
2915 
2916 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2917 /// token must be an Identifier when called, and if it is a coprocessor
2918 /// number, the token is eaten and the operand is added to the operand list.
2919 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2920 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2921   SMLoc S = Parser.getTok().getLoc();
2922   const AsmToken &Tok = Parser.getTok();
2923   if (Tok.isNot(AsmToken::Identifier))
2924     return MatchOperand_NoMatch;
2925 
2926   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2927   if (Reg == -1)
2928     return MatchOperand_NoMatch;
2929 
2930   Parser.Lex(); // Eat identifier token.
2931   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2932   return MatchOperand_Success;
2933 }
2934 
2935 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2936 /// coproc_option : '{' imm0_255 '}'
2937 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2938 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2939   SMLoc S = Parser.getTok().getLoc();
2940 
2941   // If this isn't a '{', this isn't a coprocessor immediate operand.
2942   if (Parser.getTok().isNot(AsmToken::LCurly))
2943     return MatchOperand_NoMatch;
2944   Parser.Lex(); // Eat the '{'
2945 
2946   const MCExpr *Expr;
2947   SMLoc Loc = Parser.getTok().getLoc();
2948   if (getParser().parseExpression(Expr)) {
2949     Error(Loc, "illegal expression");
2950     return MatchOperand_ParseFail;
2951   }
2952   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2953   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2954     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2955     return MatchOperand_ParseFail;
2956   }
2957   int Val = CE->getValue();
2958 
2959   // Check for and consume the closing '}'
2960   if (Parser.getTok().isNot(AsmToken::RCurly))
2961     return MatchOperand_ParseFail;
2962   SMLoc E = Parser.getTok().getEndLoc();
2963   Parser.Lex(); // Eat the '}'
2964 
2965   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2966   return MatchOperand_Success;
2967 }
2968 
2969 // For register list parsing, we need to map from raw GPR register numbering
2970 // to the enumeration values. The enumeration values aren't sorted by
2971 // register number due to our using "sp", "lr" and "pc" as canonical names.
2972 static unsigned getNextRegister(unsigned Reg) {
2973   // If this is a GPR, we need to do it manually, otherwise we can rely
2974   // on the sort ordering of the enumeration since the other reg-classes
2975   // are sane.
2976   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2977     return Reg + 1;
2978   switch(Reg) {
2979   default: llvm_unreachable("Invalid GPR number!");
2980   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2981   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2982   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2983   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2984   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2985   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2986   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2987   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2988   }
2989 }
2990 
2991 // Return the low-subreg of a given Q register.
2992 static unsigned getDRegFromQReg(unsigned QReg) {
2993   switch (QReg) {
2994   default: llvm_unreachable("expected a Q register!");
2995   case ARM::Q0:  return ARM::D0;
2996   case ARM::Q1:  return ARM::D2;
2997   case ARM::Q2:  return ARM::D4;
2998   case ARM::Q3:  return ARM::D6;
2999   case ARM::Q4:  return ARM::D8;
3000   case ARM::Q5:  return ARM::D10;
3001   case ARM::Q6:  return ARM::D12;
3002   case ARM::Q7:  return ARM::D14;
3003   case ARM::Q8:  return ARM::D16;
3004   case ARM::Q9:  return ARM::D18;
3005   case ARM::Q10: return ARM::D20;
3006   case ARM::Q11: return ARM::D22;
3007   case ARM::Q12: return ARM::D24;
3008   case ARM::Q13: return ARM::D26;
3009   case ARM::Q14: return ARM::D28;
3010   case ARM::Q15: return ARM::D30;
3011   }
3012 }
3013 
3014 /// Parse a register list.
3015 bool ARMAsmParser::
3016 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3017   assert(Parser.getTok().is(AsmToken::LCurly) &&
3018          "Token is not a Left Curly Brace");
3019   SMLoc S = Parser.getTok().getLoc();
3020   Parser.Lex(); // Eat '{' token.
3021   SMLoc RegLoc = Parser.getTok().getLoc();
3022 
3023   // Check the first register in the list to see what register class
3024   // this is a list of.
3025   int Reg = tryParseRegister();
3026   if (Reg == -1)
3027     return Error(RegLoc, "register expected");
3028 
3029   // The reglist instructions have at most 16 registers, so reserve
3030   // space for that many.
3031   int EReg = 0;
3032   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3033 
3034   // Allow Q regs and just interpret them as the two D sub-registers.
3035   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3036     Reg = getDRegFromQReg(Reg);
3037     EReg = MRI->getEncodingValue(Reg);
3038     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3039     ++Reg;
3040   }
3041   const MCRegisterClass *RC;
3042   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3043     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3044   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3045     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3046   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3047     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3048   else
3049     return Error(RegLoc, "invalid register in register list");
3050 
3051   // Store the register.
3052   EReg = MRI->getEncodingValue(Reg);
3053   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3054 
3055   // This starts immediately after the first register token in the list,
3056   // so we can see either a comma or a minus (range separator) as a legal
3057   // next token.
3058   while (Parser.getTok().is(AsmToken::Comma) ||
3059          Parser.getTok().is(AsmToken::Minus)) {
3060     if (Parser.getTok().is(AsmToken::Minus)) {
3061       Parser.Lex(); // Eat the minus.
3062       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3063       int EndReg = tryParseRegister();
3064       if (EndReg == -1)
3065         return Error(AfterMinusLoc, "register expected");
3066       // Allow Q regs and just interpret them as the two D sub-registers.
3067       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3068         EndReg = getDRegFromQReg(EndReg) + 1;
3069       // If the register is the same as the start reg, there's nothing
3070       // more to do.
3071       if (Reg == EndReg)
3072         continue;
3073       // The register must be in the same register class as the first.
3074       if (!RC->contains(EndReg))
3075         return Error(AfterMinusLoc, "invalid register in register list");
3076       // Ranges must go from low to high.
3077       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3078         return Error(AfterMinusLoc, "bad range in register list");
3079 
3080       // Add all the registers in the range to the register list.
3081       while (Reg != EndReg) {
3082         Reg = getNextRegister(Reg);
3083         EReg = MRI->getEncodingValue(Reg);
3084         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3085       }
3086       continue;
3087     }
3088     Parser.Lex(); // Eat the comma.
3089     RegLoc = Parser.getTok().getLoc();
3090     int OldReg = Reg;
3091     const AsmToken RegTok = Parser.getTok();
3092     Reg = tryParseRegister();
3093     if (Reg == -1)
3094       return Error(RegLoc, "register expected");
3095     // Allow Q regs and just interpret them as the two D sub-registers.
3096     bool isQReg = false;
3097     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3098       Reg = getDRegFromQReg(Reg);
3099       isQReg = true;
3100     }
3101     // The register must be in the same register class as the first.
3102     if (!RC->contains(Reg))
3103       return Error(RegLoc, "invalid register in register list");
3104     // List must be monotonically increasing.
3105     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3106       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3107         Warning(RegLoc, "register list not in ascending order");
3108       else
3109         return Error(RegLoc, "register list not in ascending order");
3110     }
3111     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3112       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3113               ") in register list");
3114       continue;
3115     }
3116     // VFP register lists must also be contiguous.
3117     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3118         Reg != OldReg + 1)
3119       return Error(RegLoc, "non-contiguous register range");
3120     EReg = MRI->getEncodingValue(Reg);
3121     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3122     if (isQReg) {
3123       EReg = MRI->getEncodingValue(++Reg);
3124       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3125     }
3126   }
3127 
3128   if (Parser.getTok().isNot(AsmToken::RCurly))
3129     return Error(Parser.getTok().getLoc(), "'}' expected");
3130   SMLoc E = Parser.getTok().getEndLoc();
3131   Parser.Lex(); // Eat '}' token.
3132 
3133   // Push the register list operand.
3134   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3135 
3136   // The ARM system instruction variants for LDM/STM have a '^' token here.
3137   if (Parser.getTok().is(AsmToken::Caret)) {
3138     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3139     Parser.Lex(); // Eat '^' token.
3140   }
3141 
3142   return false;
3143 }
3144 
3145 // Helper function to parse the lane index for vector lists.
3146 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3147 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3148   Index = 0; // Always return a defined index value.
3149   if (Parser.getTok().is(AsmToken::LBrac)) {
3150     Parser.Lex(); // Eat the '['.
3151     if (Parser.getTok().is(AsmToken::RBrac)) {
3152       // "Dn[]" is the 'all lanes' syntax.
3153       LaneKind = AllLanes;
3154       EndLoc = Parser.getTok().getEndLoc();
3155       Parser.Lex(); // Eat the ']'.
3156       return MatchOperand_Success;
3157     }
3158 
3159     // There's an optional '#' token here. Normally there wouldn't be, but
3160     // inline assemble puts one in, and it's friendly to accept that.
3161     if (Parser.getTok().is(AsmToken::Hash))
3162       Parser.Lex(); // Eat '#' or '$'.
3163 
3164     const MCExpr *LaneIndex;
3165     SMLoc Loc = Parser.getTok().getLoc();
3166     if (getParser().parseExpression(LaneIndex)) {
3167       Error(Loc, "illegal expression");
3168       return MatchOperand_ParseFail;
3169     }
3170     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3171     if (!CE) {
3172       Error(Loc, "lane index must be empty or an integer");
3173       return MatchOperand_ParseFail;
3174     }
3175     if (Parser.getTok().isNot(AsmToken::RBrac)) {
3176       Error(Parser.getTok().getLoc(), "']' expected");
3177       return MatchOperand_ParseFail;
3178     }
3179     EndLoc = Parser.getTok().getEndLoc();
3180     Parser.Lex(); // Eat the ']'.
3181     int64_t Val = CE->getValue();
3182 
3183     // FIXME: Make this range check context sensitive for .8, .16, .32.
3184     if (Val < 0 || Val > 7) {
3185       Error(Parser.getTok().getLoc(), "lane index out of range");
3186       return MatchOperand_ParseFail;
3187     }
3188     Index = Val;
3189     LaneKind = IndexedLane;
3190     return MatchOperand_Success;
3191   }
3192   LaneKind = NoLanes;
3193   return MatchOperand_Success;
3194 }
3195 
3196 // parse a vector register list
3197 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3198 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3199   VectorLaneTy LaneKind;
3200   unsigned LaneIndex;
3201   SMLoc S = Parser.getTok().getLoc();
3202   // As an extension (to match gas), support a plain D register or Q register
3203   // (without encosing curly braces) as a single or double entry list,
3204   // respectively.
3205   if (Parser.getTok().is(AsmToken::Identifier)) {
3206     SMLoc E = Parser.getTok().getEndLoc();
3207     int Reg = tryParseRegister();
3208     if (Reg == -1)
3209       return MatchOperand_NoMatch;
3210     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3211       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3212       if (Res != MatchOperand_Success)
3213         return Res;
3214       switch (LaneKind) {
3215       case NoLanes:
3216         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3217         break;
3218       case AllLanes:
3219         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3220                                                                 S, E));
3221         break;
3222       case IndexedLane:
3223         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3224                                                                LaneIndex,
3225                                                                false, S, E));
3226         break;
3227       }
3228       return MatchOperand_Success;
3229     }
3230     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3231       Reg = getDRegFromQReg(Reg);
3232       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3233       if (Res != MatchOperand_Success)
3234         return Res;
3235       switch (LaneKind) {
3236       case NoLanes:
3237         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3238                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3239         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3240         break;
3241       case AllLanes:
3242         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3243                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3244         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3245                                                                 S, E));
3246         break;
3247       case IndexedLane:
3248         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3249                                                                LaneIndex,
3250                                                                false, S, E));
3251         break;
3252       }
3253       return MatchOperand_Success;
3254     }
3255     Error(S, "vector register expected");
3256     return MatchOperand_ParseFail;
3257   }
3258 
3259   if (Parser.getTok().isNot(AsmToken::LCurly))
3260     return MatchOperand_NoMatch;
3261 
3262   Parser.Lex(); // Eat '{' token.
3263   SMLoc RegLoc = Parser.getTok().getLoc();
3264 
3265   int Reg = tryParseRegister();
3266   if (Reg == -1) {
3267     Error(RegLoc, "register expected");
3268     return MatchOperand_ParseFail;
3269   }
3270   unsigned Count = 1;
3271   int Spacing = 0;
3272   unsigned FirstReg = Reg;
3273   // The list is of D registers, but we also allow Q regs and just interpret
3274   // them as the two D sub-registers.
3275   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3276     FirstReg = Reg = getDRegFromQReg(Reg);
3277     Spacing = 1; // double-spacing requires explicit D registers, otherwise
3278                  // it's ambiguous with four-register single spaced.
3279     ++Reg;
3280     ++Count;
3281   }
3282 
3283   SMLoc E;
3284   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3285     return MatchOperand_ParseFail;
3286 
3287   while (Parser.getTok().is(AsmToken::Comma) ||
3288          Parser.getTok().is(AsmToken::Minus)) {
3289     if (Parser.getTok().is(AsmToken::Minus)) {
3290       if (!Spacing)
3291         Spacing = 1; // Register range implies a single spaced list.
3292       else if (Spacing == 2) {
3293         Error(Parser.getTok().getLoc(),
3294               "sequential registers in double spaced list");
3295         return MatchOperand_ParseFail;
3296       }
3297       Parser.Lex(); // Eat the minus.
3298       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3299       int EndReg = tryParseRegister();
3300       if (EndReg == -1) {
3301         Error(AfterMinusLoc, "register expected");
3302         return MatchOperand_ParseFail;
3303       }
3304       // Allow Q regs and just interpret them as the two D sub-registers.
3305       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3306         EndReg = getDRegFromQReg(EndReg) + 1;
3307       // If the register is the same as the start reg, there's nothing
3308       // more to do.
3309       if (Reg == EndReg)
3310         continue;
3311       // The register must be in the same register class as the first.
3312       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3313         Error(AfterMinusLoc, "invalid register in register list");
3314         return MatchOperand_ParseFail;
3315       }
3316       // Ranges must go from low to high.
3317       if (Reg > EndReg) {
3318         Error(AfterMinusLoc, "bad range in register list");
3319         return MatchOperand_ParseFail;
3320       }
3321       // Parse the lane specifier if present.
3322       VectorLaneTy NextLaneKind;
3323       unsigned NextLaneIndex;
3324       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3325           MatchOperand_Success)
3326         return MatchOperand_ParseFail;
3327       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3328         Error(AfterMinusLoc, "mismatched lane index in register list");
3329         return MatchOperand_ParseFail;
3330       }
3331 
3332       // Add all the registers in the range to the register list.
3333       Count += EndReg - Reg;
3334       Reg = EndReg;
3335       continue;
3336     }
3337     Parser.Lex(); // Eat the comma.
3338     RegLoc = Parser.getTok().getLoc();
3339     int OldReg = Reg;
3340     Reg = tryParseRegister();
3341     if (Reg == -1) {
3342       Error(RegLoc, "register expected");
3343       return MatchOperand_ParseFail;
3344     }
3345     // vector register lists must be contiguous.
3346     // It's OK to use the enumeration values directly here rather, as the
3347     // VFP register classes have the enum sorted properly.
3348     //
3349     // The list is of D registers, but we also allow Q regs and just interpret
3350     // them as the two D sub-registers.
3351     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3352       if (!Spacing)
3353         Spacing = 1; // Register range implies a single spaced list.
3354       else if (Spacing == 2) {
3355         Error(RegLoc,
3356               "invalid register in double-spaced list (must be 'D' register')");
3357         return MatchOperand_ParseFail;
3358       }
3359       Reg = getDRegFromQReg(Reg);
3360       if (Reg != OldReg + 1) {
3361         Error(RegLoc, "non-contiguous register range");
3362         return MatchOperand_ParseFail;
3363       }
3364       ++Reg;
3365       Count += 2;
3366       // Parse the lane specifier if present.
3367       VectorLaneTy NextLaneKind;
3368       unsigned NextLaneIndex;
3369       SMLoc LaneLoc = Parser.getTok().getLoc();
3370       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3371           MatchOperand_Success)
3372         return MatchOperand_ParseFail;
3373       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3374         Error(LaneLoc, "mismatched lane index in register list");
3375         return MatchOperand_ParseFail;
3376       }
3377       continue;
3378     }
3379     // Normal D register.
3380     // Figure out the register spacing (single or double) of the list if
3381     // we don't know it already.
3382     if (!Spacing)
3383       Spacing = 1 + (Reg == OldReg + 2);
3384 
3385     // Just check that it's contiguous and keep going.
3386     if (Reg != OldReg + Spacing) {
3387       Error(RegLoc, "non-contiguous register range");
3388       return MatchOperand_ParseFail;
3389     }
3390     ++Count;
3391     // Parse the lane specifier if present.
3392     VectorLaneTy NextLaneKind;
3393     unsigned NextLaneIndex;
3394     SMLoc EndLoc = Parser.getTok().getLoc();
3395     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3396       return MatchOperand_ParseFail;
3397     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3398       Error(EndLoc, "mismatched lane index in register list");
3399       return MatchOperand_ParseFail;
3400     }
3401   }
3402 
3403   if (Parser.getTok().isNot(AsmToken::RCurly)) {
3404     Error(Parser.getTok().getLoc(), "'}' expected");
3405     return MatchOperand_ParseFail;
3406   }
3407   E = Parser.getTok().getEndLoc();
3408   Parser.Lex(); // Eat '}' token.
3409 
3410   switch (LaneKind) {
3411   case NoLanes:
3412     // Two-register operands have been converted to the
3413     // composite register classes.
3414     if (Count == 2) {
3415       const MCRegisterClass *RC = (Spacing == 1) ?
3416         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3417         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3418       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3419     }
3420 
3421     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3422                                                     (Spacing == 2), S, E));
3423     break;
3424   case AllLanes:
3425     // Two-register operands have been converted to the
3426     // composite register classes.
3427     if (Count == 2) {
3428       const MCRegisterClass *RC = (Spacing == 1) ?
3429         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3430         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3431       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3432     }
3433     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3434                                                             (Spacing == 2),
3435                                                             S, E));
3436     break;
3437   case IndexedLane:
3438     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3439                                                            LaneIndex,
3440                                                            (Spacing == 2),
3441                                                            S, E));
3442     break;
3443   }
3444   return MatchOperand_Success;
3445 }
3446 
3447 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3448 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3449 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3450   SMLoc S = Parser.getTok().getLoc();
3451   const AsmToken &Tok = Parser.getTok();
3452   unsigned Opt;
3453 
3454   if (Tok.is(AsmToken::Identifier)) {
3455     StringRef OptStr = Tok.getString();
3456 
3457     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3458       .Case("sy",    ARM_MB::SY)
3459       .Case("st",    ARM_MB::ST)
3460       .Case("sh",    ARM_MB::ISH)
3461       .Case("ish",   ARM_MB::ISH)
3462       .Case("shst",  ARM_MB::ISHST)
3463       .Case("ishst", ARM_MB::ISHST)
3464       .Case("nsh",   ARM_MB::NSH)
3465       .Case("un",    ARM_MB::NSH)
3466       .Case("nshst", ARM_MB::NSHST)
3467       .Case("unst",  ARM_MB::NSHST)
3468       .Case("osh",   ARM_MB::OSH)
3469       .Case("oshst", ARM_MB::OSHST)
3470       .Default(~0U);
3471 
3472     if (Opt == ~0U)
3473       return MatchOperand_NoMatch;
3474 
3475     Parser.Lex(); // Eat identifier token.
3476   } else if (Tok.is(AsmToken::Hash) ||
3477              Tok.is(AsmToken::Dollar) ||
3478              Tok.is(AsmToken::Integer)) {
3479     if (Parser.getTok().isNot(AsmToken::Integer))
3480       Parser.Lex(); // Eat '#' or '$'.
3481     SMLoc Loc = Parser.getTok().getLoc();
3482 
3483     const MCExpr *MemBarrierID;
3484     if (getParser().parseExpression(MemBarrierID)) {
3485       Error(Loc, "illegal expression");
3486       return MatchOperand_ParseFail;
3487     }
3488 
3489     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3490     if (!CE) {
3491       Error(Loc, "constant expression expected");
3492       return MatchOperand_ParseFail;
3493     }
3494 
3495     int Val = CE->getValue();
3496     if (Val & ~0xf) {
3497       Error(Loc, "immediate value out of range");
3498       return MatchOperand_ParseFail;
3499     }
3500 
3501     Opt = ARM_MB::RESERVED_0 + Val;
3502   } else
3503     return MatchOperand_ParseFail;
3504 
3505   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3506   return MatchOperand_Success;
3507 }
3508 
3509 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3510 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3511 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3512   SMLoc S = Parser.getTok().getLoc();
3513   const AsmToken &Tok = Parser.getTok();
3514   unsigned Opt;
3515 
3516   if (Tok.is(AsmToken::Identifier)) {
3517     StringRef OptStr = Tok.getString();
3518 
3519     if (OptStr.lower() == "sy")
3520       Opt = ARM_ISB::SY;
3521     else
3522       return MatchOperand_NoMatch;
3523 
3524     Parser.Lex(); // Eat identifier token.
3525   } else if (Tok.is(AsmToken::Hash) ||
3526              Tok.is(AsmToken::Dollar) ||
3527              Tok.is(AsmToken::Integer)) {
3528     if (Parser.getTok().isNot(AsmToken::Integer))
3529       Parser.Lex(); // Eat '#' or '$'.
3530     SMLoc Loc = Parser.getTok().getLoc();
3531 
3532     const MCExpr *ISBarrierID;
3533     if (getParser().parseExpression(ISBarrierID)) {
3534       Error(Loc, "illegal expression");
3535       return MatchOperand_ParseFail;
3536     }
3537 
3538     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3539     if (!CE) {
3540       Error(Loc, "constant expression expected");
3541       return MatchOperand_ParseFail;
3542     }
3543 
3544     int Val = CE->getValue();
3545     if (Val & ~0xf) {
3546       Error(Loc, "immediate value out of range");
3547       return MatchOperand_ParseFail;
3548     }
3549 
3550     Opt = ARM_ISB::RESERVED_0 + Val;
3551   } else
3552     return MatchOperand_ParseFail;
3553 
3554   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3555           (ARM_ISB::InstSyncBOpt)Opt, S));
3556   return MatchOperand_Success;
3557 }
3558 
3559 
3560 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3561 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3562 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3563   SMLoc S = Parser.getTok().getLoc();
3564   const AsmToken &Tok = Parser.getTok();
3565   if (!Tok.is(AsmToken::Identifier))
3566     return MatchOperand_NoMatch;
3567   StringRef IFlagsStr = Tok.getString();
3568 
3569   // An iflags string of "none" is interpreted to mean that none of the AIF
3570   // bits are set.  Not a terribly useful instruction, but a valid encoding.
3571   unsigned IFlags = 0;
3572   if (IFlagsStr != "none") {
3573         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3574       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3575         .Case("a", ARM_PROC::A)
3576         .Case("i", ARM_PROC::I)
3577         .Case("f", ARM_PROC::F)
3578         .Default(~0U);
3579 
3580       // If some specific iflag is already set, it means that some letter is
3581       // present more than once, this is not acceptable.
3582       if (Flag == ~0U || (IFlags & Flag))
3583         return MatchOperand_NoMatch;
3584 
3585       IFlags |= Flag;
3586     }
3587   }
3588 
3589   Parser.Lex(); // Eat identifier token.
3590   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3591   return MatchOperand_Success;
3592 }
3593 
3594 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3595 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3596 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3597   SMLoc S = Parser.getTok().getLoc();
3598   const AsmToken &Tok = Parser.getTok();
3599   if (!Tok.is(AsmToken::Identifier))
3600     return MatchOperand_NoMatch;
3601   StringRef Mask = Tok.getString();
3602 
3603   if (isMClass()) {
3604     // See ARMv6-M 10.1.1
3605     std::string Name = Mask.lower();
3606     unsigned FlagsVal = StringSwitch<unsigned>(Name)
3607       // Note: in the documentation:
3608       //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3609       //  for MSR APSR_nzcvq.
3610       // but we do make it an alias here.  This is so to get the "mask encoding"
3611       // bits correct on MSR APSR writes.
3612       //
3613       // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3614       // should really only be allowed when writing a special register.  Note
3615       // they get dropped in the MRS instruction reading a special register as
3616       // the SYSm field is only 8 bits.
3617       //
3618       // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3619       // includes the DSP extension but that is not checked.
3620       .Case("apsr", 0x800)
3621       .Case("apsr_nzcvq", 0x800)
3622       .Case("apsr_g", 0x400)
3623       .Case("apsr_nzcvqg", 0xc00)
3624       .Case("iapsr", 0x801)
3625       .Case("iapsr_nzcvq", 0x801)
3626       .Case("iapsr_g", 0x401)
3627       .Case("iapsr_nzcvqg", 0xc01)
3628       .Case("eapsr", 0x802)
3629       .Case("eapsr_nzcvq", 0x802)
3630       .Case("eapsr_g", 0x402)
3631       .Case("eapsr_nzcvqg", 0xc02)
3632       .Case("xpsr", 0x803)
3633       .Case("xpsr_nzcvq", 0x803)
3634       .Case("xpsr_g", 0x403)
3635       .Case("xpsr_nzcvqg", 0xc03)
3636       .Case("ipsr", 0x805)
3637       .Case("epsr", 0x806)
3638       .Case("iepsr", 0x807)
3639       .Case("msp", 0x808)
3640       .Case("psp", 0x809)
3641       .Case("primask", 0x810)
3642       .Case("basepri", 0x811)
3643       .Case("basepri_max", 0x812)
3644       .Case("faultmask", 0x813)
3645       .Case("control", 0x814)
3646       .Default(~0U);
3647 
3648     if (FlagsVal == ~0U)
3649       return MatchOperand_NoMatch;
3650 
3651     if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3652       // basepri, basepri_max and faultmask only valid for V7m.
3653       return MatchOperand_NoMatch;
3654 
3655     Parser.Lex(); // Eat identifier token.
3656     Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3657     return MatchOperand_Success;
3658   }
3659 
3660   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3661   size_t Start = 0, Next = Mask.find('_');
3662   StringRef Flags = "";
3663   std::string SpecReg = Mask.slice(Start, Next).lower();
3664   if (Next != StringRef::npos)
3665     Flags = Mask.slice(Next+1, Mask.size());
3666 
3667   // FlagsVal contains the complete mask:
3668   // 3-0: Mask
3669   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3670   unsigned FlagsVal = 0;
3671 
3672   if (SpecReg == "apsr") {
3673     FlagsVal = StringSwitch<unsigned>(Flags)
3674     .Case("nzcvq",  0x8) // same as CPSR_f
3675     .Case("g",      0x4) // same as CPSR_s
3676     .Case("nzcvqg", 0xc) // same as CPSR_fs
3677     .Default(~0U);
3678 
3679     if (FlagsVal == ~0U) {
3680       if (!Flags.empty())
3681         return MatchOperand_NoMatch;
3682       else
3683         FlagsVal = 8; // No flag
3684     }
3685   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3686     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3687     if (Flags == "all" || Flags == "")
3688       Flags = "fc";
3689     for (int i = 0, e = Flags.size(); i != e; ++i) {
3690       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3691       .Case("c", 1)
3692       .Case("x", 2)
3693       .Case("s", 4)
3694       .Case("f", 8)
3695       .Default(~0U);
3696 
3697       // If some specific flag is already set, it means that some letter is
3698       // present more than once, this is not acceptable.
3699       if (FlagsVal == ~0U || (FlagsVal & Flag))
3700         return MatchOperand_NoMatch;
3701       FlagsVal |= Flag;
3702     }
3703   } else // No match for special register.
3704     return MatchOperand_NoMatch;
3705 
3706   // Special register without flags is NOT equivalent to "fc" flags.
3707   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3708   // two lines would enable gas compatibility at the expense of breaking
3709   // round-tripping.
3710   //
3711   // if (!FlagsVal)
3712   //  FlagsVal = 0x9;
3713 
3714   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3715   if (SpecReg == "spsr")
3716     FlagsVal |= 16;
3717 
3718   Parser.Lex(); // Eat identifier token.
3719   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3720   return MatchOperand_Success;
3721 }
3722 
3723 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3724 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3725             int Low, int High) {
3726   const AsmToken &Tok = Parser.getTok();
3727   if (Tok.isNot(AsmToken::Identifier)) {
3728     Error(Parser.getTok().getLoc(), Op + " operand expected.");
3729     return MatchOperand_ParseFail;
3730   }
3731   StringRef ShiftName = Tok.getString();
3732   std::string LowerOp = Op.lower();
3733   std::string UpperOp = Op.upper();
3734   if (ShiftName != LowerOp && ShiftName != UpperOp) {
3735     Error(Parser.getTok().getLoc(), Op + " operand expected.");
3736     return MatchOperand_ParseFail;
3737   }
3738   Parser.Lex(); // Eat shift type token.
3739 
3740   // There must be a '#' and a shift amount.
3741   if (Parser.getTok().isNot(AsmToken::Hash) &&
3742       Parser.getTok().isNot(AsmToken::Dollar)) {
3743     Error(Parser.getTok().getLoc(), "'#' expected");
3744     return MatchOperand_ParseFail;
3745   }
3746   Parser.Lex(); // Eat hash token.
3747 
3748   const MCExpr *ShiftAmount;
3749   SMLoc Loc = Parser.getTok().getLoc();
3750   SMLoc EndLoc;
3751   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3752     Error(Loc, "illegal expression");
3753     return MatchOperand_ParseFail;
3754   }
3755   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3756   if (!CE) {
3757     Error(Loc, "constant expression expected");
3758     return MatchOperand_ParseFail;
3759   }
3760   int Val = CE->getValue();
3761   if (Val < Low || Val > High) {
3762     Error(Loc, "immediate value out of range");
3763     return MatchOperand_ParseFail;
3764   }
3765 
3766   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3767 
3768   return MatchOperand_Success;
3769 }
3770 
3771 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3772 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3773   const AsmToken &Tok = Parser.getTok();
3774   SMLoc S = Tok.getLoc();
3775   if (Tok.isNot(AsmToken::Identifier)) {
3776     Error(S, "'be' or 'le' operand expected");
3777     return MatchOperand_ParseFail;
3778   }
3779   int Val = StringSwitch<int>(Tok.getString().lower())
3780     .Case("be", 1)
3781     .Case("le", 0)
3782     .Default(-1);
3783   Parser.Lex(); // Eat the token.
3784 
3785   if (Val == -1) {
3786     Error(S, "'be' or 'le' operand expected");
3787     return MatchOperand_ParseFail;
3788   }
3789   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3790                                                                   getContext()),
3791                                            S, Tok.getEndLoc()));
3792   return MatchOperand_Success;
3793 }
3794 
3795 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3796 /// instructions. Legal values are:
3797 ///     lsl #n  'n' in [0,31]
3798 ///     asr #n  'n' in [1,32]
3799 ///             n == 32 encoded as n == 0.
3800 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3801 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3802   const AsmToken &Tok = Parser.getTok();
3803   SMLoc S = Tok.getLoc();
3804   if (Tok.isNot(AsmToken::Identifier)) {
3805     Error(S, "shift operator 'asr' or 'lsl' expected");
3806     return MatchOperand_ParseFail;
3807   }
3808   StringRef ShiftName = Tok.getString();
3809   bool isASR;
3810   if (ShiftName == "lsl" || ShiftName == "LSL")
3811     isASR = false;
3812   else if (ShiftName == "asr" || ShiftName == "ASR")
3813     isASR = true;
3814   else {
3815     Error(S, "shift operator 'asr' or 'lsl' expected");
3816     return MatchOperand_ParseFail;
3817   }
3818   Parser.Lex(); // Eat the operator.
3819 
3820   // A '#' and a shift amount.
3821   if (Parser.getTok().isNot(AsmToken::Hash) &&
3822       Parser.getTok().isNot(AsmToken::Dollar)) {
3823     Error(Parser.getTok().getLoc(), "'#' expected");
3824     return MatchOperand_ParseFail;
3825   }
3826   Parser.Lex(); // Eat hash token.
3827   SMLoc ExLoc = Parser.getTok().getLoc();
3828 
3829   const MCExpr *ShiftAmount;
3830   SMLoc EndLoc;
3831   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3832     Error(ExLoc, "malformed shift expression");
3833     return MatchOperand_ParseFail;
3834   }
3835   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3836   if (!CE) {
3837     Error(ExLoc, "shift amount must be an immediate");
3838     return MatchOperand_ParseFail;
3839   }
3840 
3841   int64_t Val = CE->getValue();
3842   if (isASR) {
3843     // Shift amount must be in [1,32]
3844     if (Val < 1 || Val > 32) {
3845       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3846       return MatchOperand_ParseFail;
3847     }
3848     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3849     if (isThumb() && Val == 32) {
3850       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3851       return MatchOperand_ParseFail;
3852     }
3853     if (Val == 32) Val = 0;
3854   } else {
3855     // Shift amount must be in [1,32]
3856     if (Val < 0 || Val > 31) {
3857       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3858       return MatchOperand_ParseFail;
3859     }
3860   }
3861 
3862   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3863 
3864   return MatchOperand_Success;
3865 }
3866 
3867 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3868 /// of instructions. Legal values are:
3869 ///     ror #n  'n' in {0, 8, 16, 24}
3870 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3871 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3872   const AsmToken &Tok = Parser.getTok();
3873   SMLoc S = Tok.getLoc();
3874   if (Tok.isNot(AsmToken::Identifier))
3875     return MatchOperand_NoMatch;
3876   StringRef ShiftName = Tok.getString();
3877   if (ShiftName != "ror" && ShiftName != "ROR")
3878     return MatchOperand_NoMatch;
3879   Parser.Lex(); // Eat the operator.
3880 
3881   // A '#' and a rotate amount.
3882   if (Parser.getTok().isNot(AsmToken::Hash) &&
3883       Parser.getTok().isNot(AsmToken::Dollar)) {
3884     Error(Parser.getTok().getLoc(), "'#' expected");
3885     return MatchOperand_ParseFail;
3886   }
3887   Parser.Lex(); // Eat hash token.
3888   SMLoc ExLoc = Parser.getTok().getLoc();
3889 
3890   const MCExpr *ShiftAmount;
3891   SMLoc EndLoc;
3892   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3893     Error(ExLoc, "malformed rotate expression");
3894     return MatchOperand_ParseFail;
3895   }
3896   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3897   if (!CE) {
3898     Error(ExLoc, "rotate amount must be an immediate");
3899     return MatchOperand_ParseFail;
3900   }
3901 
3902   int64_t Val = CE->getValue();
3903   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3904   // normally, zero is represented in asm by omitting the rotate operand
3905   // entirely.
3906   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3907     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3908     return MatchOperand_ParseFail;
3909   }
3910 
3911   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3912 
3913   return MatchOperand_Success;
3914 }
3915 
3916 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3917 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3918   SMLoc S = Parser.getTok().getLoc();
3919   // The bitfield descriptor is really two operands, the LSB and the width.
3920   if (Parser.getTok().isNot(AsmToken::Hash) &&
3921       Parser.getTok().isNot(AsmToken::Dollar)) {
3922     Error(Parser.getTok().getLoc(), "'#' expected");
3923     return MatchOperand_ParseFail;
3924   }
3925   Parser.Lex(); // Eat hash token.
3926 
3927   const MCExpr *LSBExpr;
3928   SMLoc E = Parser.getTok().getLoc();
3929   if (getParser().parseExpression(LSBExpr)) {
3930     Error(E, "malformed immediate expression");
3931     return MatchOperand_ParseFail;
3932   }
3933   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3934   if (!CE) {
3935     Error(E, "'lsb' operand must be an immediate");
3936     return MatchOperand_ParseFail;
3937   }
3938 
3939   int64_t LSB = CE->getValue();
3940   // The LSB must be in the range [0,31]
3941   if (LSB < 0 || LSB > 31) {
3942     Error(E, "'lsb' operand must be in the range [0,31]");
3943     return MatchOperand_ParseFail;
3944   }
3945   E = Parser.getTok().getLoc();
3946 
3947   // Expect another immediate operand.
3948   if (Parser.getTok().isNot(AsmToken::Comma)) {
3949     Error(Parser.getTok().getLoc(), "too few operands");
3950     return MatchOperand_ParseFail;
3951   }
3952   Parser.Lex(); // Eat hash token.
3953   if (Parser.getTok().isNot(AsmToken::Hash) &&
3954       Parser.getTok().isNot(AsmToken::Dollar)) {
3955     Error(Parser.getTok().getLoc(), "'#' expected");
3956     return MatchOperand_ParseFail;
3957   }
3958   Parser.Lex(); // Eat hash token.
3959 
3960   const MCExpr *WidthExpr;
3961   SMLoc EndLoc;
3962   if (getParser().parseExpression(WidthExpr, EndLoc)) {
3963     Error(E, "malformed immediate expression");
3964     return MatchOperand_ParseFail;
3965   }
3966   CE = dyn_cast<MCConstantExpr>(WidthExpr);
3967   if (!CE) {
3968     Error(E, "'width' operand must be an immediate");
3969     return MatchOperand_ParseFail;
3970   }
3971 
3972   int64_t Width = CE->getValue();
3973   // The LSB must be in the range [1,32-lsb]
3974   if (Width < 1 || Width > 32 - LSB) {
3975     Error(E, "'width' operand must be in the range [1,32-lsb]");
3976     return MatchOperand_ParseFail;
3977   }
3978 
3979   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3980 
3981   return MatchOperand_Success;
3982 }
3983 
3984 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3985 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3986   // Check for a post-index addressing register operand. Specifically:
3987   // postidx_reg := '+' register {, shift}
3988   //              | '-' register {, shift}
3989   //              | register {, shift}
3990 
3991   // This method must return MatchOperand_NoMatch without consuming any tokens
3992   // in the case where there is no match, as other alternatives take other
3993   // parse methods.
3994   AsmToken Tok = Parser.getTok();
3995   SMLoc S = Tok.getLoc();
3996   bool haveEaten = false;
3997   bool isAdd = true;
3998   if (Tok.is(AsmToken::Plus)) {
3999     Parser.Lex(); // Eat the '+' token.
4000     haveEaten = true;
4001   } else if (Tok.is(AsmToken::Minus)) {
4002     Parser.Lex(); // Eat the '-' token.
4003     isAdd = false;
4004     haveEaten = true;
4005   }
4006 
4007   SMLoc E = Parser.getTok().getEndLoc();
4008   int Reg = tryParseRegister();
4009   if (Reg == -1) {
4010     if (!haveEaten)
4011       return MatchOperand_NoMatch;
4012     Error(Parser.getTok().getLoc(), "register expected");
4013     return MatchOperand_ParseFail;
4014   }
4015 
4016   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4017   unsigned ShiftImm = 0;
4018   if (Parser.getTok().is(AsmToken::Comma)) {
4019     Parser.Lex(); // Eat the ','.
4020     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4021       return MatchOperand_ParseFail;
4022 
4023     // FIXME: Only approximates end...may include intervening whitespace.
4024     E = Parser.getTok().getLoc();
4025   }
4026 
4027   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4028                                                   ShiftImm, S, E));
4029 
4030   return MatchOperand_Success;
4031 }
4032 
4033 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4034 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4035   // Check for a post-index addressing register operand. Specifically:
4036   // am3offset := '+' register
4037   //              | '-' register
4038   //              | register
4039   //              | # imm
4040   //              | # + imm
4041   //              | # - imm
4042 
4043   // This method must return MatchOperand_NoMatch without consuming any tokens
4044   // in the case where there is no match, as other alternatives take other
4045   // parse methods.
4046   AsmToken Tok = Parser.getTok();
4047   SMLoc S = Tok.getLoc();
4048 
4049   // Do immediates first, as we always parse those if we have a '#'.
4050   if (Parser.getTok().is(AsmToken::Hash) ||
4051       Parser.getTok().is(AsmToken::Dollar)) {
4052     Parser.Lex(); // Eat '#' or '$'.
4053     // Explicitly look for a '-', as we need to encode negative zero
4054     // differently.
4055     bool isNegative = Parser.getTok().is(AsmToken::Minus);
4056     const MCExpr *Offset;
4057     SMLoc E;
4058     if (getParser().parseExpression(Offset, E))
4059       return MatchOperand_ParseFail;
4060     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4061     if (!CE) {
4062       Error(S, "constant expression expected");
4063       return MatchOperand_ParseFail;
4064     }
4065     // Negative zero is encoded as the flag value INT32_MIN.
4066     int32_t Val = CE->getValue();
4067     if (isNegative && Val == 0)
4068       Val = INT32_MIN;
4069 
4070     Operands.push_back(
4071       ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4072 
4073     return MatchOperand_Success;
4074   }
4075 
4076 
4077   bool haveEaten = false;
4078   bool isAdd = true;
4079   if (Tok.is(AsmToken::Plus)) {
4080     Parser.Lex(); // Eat the '+' token.
4081     haveEaten = true;
4082   } else if (Tok.is(AsmToken::Minus)) {
4083     Parser.Lex(); // Eat the '-' token.
4084     isAdd = false;
4085     haveEaten = true;
4086   }
4087 
4088   Tok = Parser.getTok();
4089   int Reg = tryParseRegister();
4090   if (Reg == -1) {
4091     if (!haveEaten)
4092       return MatchOperand_NoMatch;
4093     Error(Tok.getLoc(), "register expected");
4094     return MatchOperand_ParseFail;
4095   }
4096 
4097   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4098                                                   0, S, Tok.getEndLoc()));
4099 
4100   return MatchOperand_Success;
4101 }
4102 
4103 /// Convert parsed operands to MCInst.  Needed here because this instruction
4104 /// only has two register operands, but multiplication is commutative so
4105 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4106 void ARMAsmParser::
4107 cvtThumbMultiply(MCInst &Inst,
4108            const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4109   ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4110   ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4111   // If we have a three-operand form, make sure to set Rn to be the operand
4112   // that isn't the same as Rd.
4113   unsigned RegOp = 4;
4114   if (Operands.size() == 6 &&
4115       ((ARMOperand*)Operands[4])->getReg() ==
4116         ((ARMOperand*)Operands[3])->getReg())
4117     RegOp = 5;
4118   ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4119   Inst.addOperand(Inst.getOperand(0));
4120   ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4121 }
4122 
4123 void ARMAsmParser::
4124 cvtThumbBranches(MCInst &Inst,
4125            const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4126   int CondOp = -1, ImmOp = -1;
4127   switch(Inst.getOpcode()) {
4128     case ARM::tB:
4129     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
4130 
4131     case ARM::t2B:
4132     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4133 
4134     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4135   }
4136   // first decide whether or not the branch should be conditional
4137   // by looking at it's location relative to an IT block
4138   if(inITBlock()) {
4139     // inside an IT block we cannot have any conditional branches. any
4140     // such instructions needs to be converted to unconditional form
4141     switch(Inst.getOpcode()) {
4142       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4143       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4144     }
4145   } else {
4146     // outside IT blocks we can only have unconditional branches with AL
4147     // condition code or conditional branches with non-AL condition code
4148     unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4149     switch(Inst.getOpcode()) {
4150       case ARM::tB:
4151       case ARM::tBcc:
4152         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4153         break;
4154       case ARM::t2B:
4155       case ARM::t2Bcc:
4156         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4157         break;
4158     }
4159   }
4160 
4161   // now decide on encoding size based on branch target range
4162   switch(Inst.getOpcode()) {
4163     // classify tB as either t2B or t1B based on range of immediate operand
4164     case ARM::tB: {
4165       ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4166       if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4167         Inst.setOpcode(ARM::t2B);
4168       break;
4169     }
4170     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4171     case ARM::tBcc: {
4172       ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4173       if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4174         Inst.setOpcode(ARM::t2Bcc);
4175       break;
4176     }
4177   }
4178   ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4179   ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4180 }
4181 
4182 /// Parse an ARM memory expression, return false if successful else return true
4183 /// or an error.  The first token must be a '[' when called.
4184 bool ARMAsmParser::
4185 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4186   SMLoc S, E;
4187   assert(Parser.getTok().is(AsmToken::LBrac) &&
4188          "Token is not a Left Bracket");
4189   S = Parser.getTok().getLoc();
4190   Parser.Lex(); // Eat left bracket token.
4191 
4192   const AsmToken &BaseRegTok = Parser.getTok();
4193   int BaseRegNum = tryParseRegister();
4194   if (BaseRegNum == -1)
4195     return Error(BaseRegTok.getLoc(), "register expected");
4196 
4197   // The next token must either be a comma, a colon or a closing bracket.
4198   const AsmToken &Tok = Parser.getTok();
4199   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4200       !Tok.is(AsmToken::RBrac))
4201     return Error(Tok.getLoc(), "malformed memory operand");
4202 
4203   if (Tok.is(AsmToken::RBrac)) {
4204     E = Tok.getEndLoc();
4205     Parser.Lex(); // Eat right bracket token.
4206 
4207     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4208                                              0, 0, false, S, E));
4209 
4210     // If there's a pre-indexing writeback marker, '!', just add it as a token
4211     // operand. It's rather odd, but syntactically valid.
4212     if (Parser.getTok().is(AsmToken::Exclaim)) {
4213       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4214       Parser.Lex(); // Eat the '!'.
4215     }
4216 
4217     return false;
4218   }
4219 
4220   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4221          "Lost colon or comma in memory operand?!");
4222   if (Tok.is(AsmToken::Comma)) {
4223     Parser.Lex(); // Eat the comma.
4224   }
4225 
4226   // If we have a ':', it's an alignment specifier.
4227   if (Parser.getTok().is(AsmToken::Colon)) {
4228     Parser.Lex(); // Eat the ':'.
4229     E = Parser.getTok().getLoc();
4230 
4231     const MCExpr *Expr;
4232     if (getParser().parseExpression(Expr))
4233      return true;
4234 
4235     // The expression has to be a constant. Memory references with relocations
4236     // don't come through here, as they use the <label> forms of the relevant
4237     // instructions.
4238     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4239     if (!CE)
4240       return Error (E, "constant expression expected");
4241 
4242     unsigned Align = 0;
4243     switch (CE->getValue()) {
4244     default:
4245       return Error(E,
4246                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4247     case 16:  Align = 2; break;
4248     case 32:  Align = 4; break;
4249     case 64:  Align = 8; break;
4250     case 128: Align = 16; break;
4251     case 256: Align = 32; break;
4252     }
4253 
4254     // Now we should have the closing ']'
4255     if (Parser.getTok().isNot(AsmToken::RBrac))
4256       return Error(Parser.getTok().getLoc(), "']' expected");
4257     E = Parser.getTok().getEndLoc();
4258     Parser.Lex(); // Eat right bracket token.
4259 
4260     // Don't worry about range checking the value here. That's handled by
4261     // the is*() predicates.
4262     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4263                                              ARM_AM::no_shift, 0, Align,
4264                                              false, S, E));
4265 
4266     // If there's a pre-indexing writeback marker, '!', just add it as a token
4267     // operand.
4268     if (Parser.getTok().is(AsmToken::Exclaim)) {
4269       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4270       Parser.Lex(); // Eat the '!'.
4271     }
4272 
4273     return false;
4274   }
4275 
4276   // If we have a '#', it's an immediate offset, else assume it's a register
4277   // offset. Be friendly and also accept a plain integer (without a leading
4278   // hash) for gas compatibility.
4279   if (Parser.getTok().is(AsmToken::Hash) ||
4280       Parser.getTok().is(AsmToken::Dollar) ||
4281       Parser.getTok().is(AsmToken::Integer)) {
4282     if (Parser.getTok().isNot(AsmToken::Integer))
4283       Parser.Lex(); // Eat '#' or '$'.
4284     E = Parser.getTok().getLoc();
4285 
4286     bool isNegative = getParser().getTok().is(AsmToken::Minus);
4287     const MCExpr *Offset;
4288     if (getParser().parseExpression(Offset))
4289      return true;
4290 
4291     // The expression has to be a constant. Memory references with relocations
4292     // don't come through here, as they use the <label> forms of the relevant
4293     // instructions.
4294     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4295     if (!CE)
4296       return Error (E, "constant expression expected");
4297 
4298     // If the constant was #-0, represent it as INT32_MIN.
4299     int32_t Val = CE->getValue();
4300     if (isNegative && Val == 0)
4301       CE = MCConstantExpr::Create(INT32_MIN, getContext());
4302 
4303     // Now we should have the closing ']'
4304     if (Parser.getTok().isNot(AsmToken::RBrac))
4305       return Error(Parser.getTok().getLoc(), "']' expected");
4306     E = Parser.getTok().getEndLoc();
4307     Parser.Lex(); // Eat right bracket token.
4308 
4309     // Don't worry about range checking the value here. That's handled by
4310     // the is*() predicates.
4311     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4312                                              ARM_AM::no_shift, 0, 0,
4313                                              false, S, E));
4314 
4315     // If there's a pre-indexing writeback marker, '!', just add it as a token
4316     // operand.
4317     if (Parser.getTok().is(AsmToken::Exclaim)) {
4318       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4319       Parser.Lex(); // Eat the '!'.
4320     }
4321 
4322     return false;
4323   }
4324 
4325   // The register offset is optionally preceded by a '+' or '-'
4326   bool isNegative = false;
4327   if (Parser.getTok().is(AsmToken::Minus)) {
4328     isNegative = true;
4329     Parser.Lex(); // Eat the '-'.
4330   } else if (Parser.getTok().is(AsmToken::Plus)) {
4331     // Nothing to do.
4332     Parser.Lex(); // Eat the '+'.
4333   }
4334 
4335   E = Parser.getTok().getLoc();
4336   int OffsetRegNum = tryParseRegister();
4337   if (OffsetRegNum == -1)
4338     return Error(E, "register expected");
4339 
4340   // If there's a shift operator, handle it.
4341   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4342   unsigned ShiftImm = 0;
4343   if (Parser.getTok().is(AsmToken::Comma)) {
4344     Parser.Lex(); // Eat the ','.
4345     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4346       return true;
4347   }
4348 
4349   // Now we should have the closing ']'
4350   if (Parser.getTok().isNot(AsmToken::RBrac))
4351     return Error(Parser.getTok().getLoc(), "']' expected");
4352   E = Parser.getTok().getEndLoc();
4353   Parser.Lex(); // Eat right bracket token.
4354 
4355   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4356                                            ShiftType, ShiftImm, 0, isNegative,
4357                                            S, E));
4358 
4359   // If there's a pre-indexing writeback marker, '!', just add it as a token
4360   // operand.
4361   if (Parser.getTok().is(AsmToken::Exclaim)) {
4362     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4363     Parser.Lex(); // Eat the '!'.
4364   }
4365 
4366   return false;
4367 }
4368 
4369 /// parseMemRegOffsetShift - one of these two:
4370 ///   ( lsl | lsr | asr | ror ) , # shift_amount
4371 ///   rrx
4372 /// return true if it parses a shift otherwise it returns false.
4373 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4374                                           unsigned &Amount) {
4375   SMLoc Loc = Parser.getTok().getLoc();
4376   const AsmToken &Tok = Parser.getTok();
4377   if (Tok.isNot(AsmToken::Identifier))
4378     return true;
4379   StringRef ShiftName = Tok.getString();
4380   if (ShiftName == "lsl" || ShiftName == "LSL" ||
4381       ShiftName == "asl" || ShiftName == "ASL")
4382     St = ARM_AM::lsl;
4383   else if (ShiftName == "lsr" || ShiftName == "LSR")
4384     St = ARM_AM::lsr;
4385   else if (ShiftName == "asr" || ShiftName == "ASR")
4386     St = ARM_AM::asr;
4387   else if (ShiftName == "ror" || ShiftName == "ROR")
4388     St = ARM_AM::ror;
4389   else if (ShiftName == "rrx" || ShiftName == "RRX")
4390     St = ARM_AM::rrx;
4391   else
4392     return Error(Loc, "illegal shift operator");
4393   Parser.Lex(); // Eat shift type token.
4394 
4395   // rrx stands alone.
4396   Amount = 0;
4397   if (St != ARM_AM::rrx) {
4398     Loc = Parser.getTok().getLoc();
4399     // A '#' and a shift amount.
4400     const AsmToken &HashTok = Parser.getTok();
4401     if (HashTok.isNot(AsmToken::Hash) &&
4402         HashTok.isNot(AsmToken::Dollar))
4403       return Error(HashTok.getLoc(), "'#' expected");
4404     Parser.Lex(); // Eat hash token.
4405 
4406     const MCExpr *Expr;
4407     if (getParser().parseExpression(Expr))
4408       return true;
4409     // Range check the immediate.
4410     // lsl, ror: 0 <= imm <= 31
4411     // lsr, asr: 0 <= imm <= 32
4412     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4413     if (!CE)
4414       return Error(Loc, "shift amount must be an immediate");
4415     int64_t Imm = CE->getValue();
4416     if (Imm < 0 ||
4417         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4418         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4419       return Error(Loc, "immediate shift value out of range");
4420     // If <ShiftTy> #0, turn it into a no_shift.
4421     if (Imm == 0)
4422       St = ARM_AM::lsl;
4423     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4424     if (Imm == 32)
4425       Imm = 0;
4426     Amount = Imm;
4427   }
4428 
4429   return false;
4430 }
4431 
4432 /// parseFPImm - A floating point immediate expression operand.
4433 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4434 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4435   // Anything that can accept a floating point constant as an operand
4436   // needs to go through here, as the regular parseExpression is
4437   // integer only.
4438   //
4439   // This routine still creates a generic Immediate operand, containing
4440   // a bitcast of the 64-bit floating point value. The various operands
4441   // that accept floats can check whether the value is valid for them
4442   // via the standard is*() predicates.
4443 
4444   SMLoc S = Parser.getTok().getLoc();
4445 
4446   if (Parser.getTok().isNot(AsmToken::Hash) &&
4447       Parser.getTok().isNot(AsmToken::Dollar))
4448     return MatchOperand_NoMatch;
4449 
4450   // Disambiguate the VMOV forms that can accept an FP immediate.
4451   // vmov.f32 <sreg>, #imm
4452   // vmov.f64 <dreg>, #imm
4453   // vmov.f32 <dreg>, #imm  @ vector f32x2
4454   // vmov.f32 <qreg>, #imm  @ vector f32x4
4455   //
4456   // There are also the NEON VMOV instructions which expect an
4457   // integer constant. Make sure we don't try to parse an FPImm
4458   // for these:
4459   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4460   ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4461   if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4462                            TyOp->getToken() != ".f64"))
4463     return MatchOperand_NoMatch;
4464 
4465   Parser.Lex(); // Eat '#' or '$'.
4466 
4467   // Handle negation, as that still comes through as a separate token.
4468   bool isNegative = false;
4469   if (Parser.getTok().is(AsmToken::Minus)) {
4470     isNegative = true;
4471     Parser.Lex();
4472   }
4473   const AsmToken &Tok = Parser.getTok();
4474   SMLoc Loc = Tok.getLoc();
4475   if (Tok.is(AsmToken::Real)) {
4476     APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4477     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4478     // If we had a '-' in front, toggle the sign bit.
4479     IntVal ^= (uint64_t)isNegative << 31;
4480     Parser.Lex(); // Eat the token.
4481     Operands.push_back(ARMOperand::CreateImm(
4482           MCConstantExpr::Create(IntVal, getContext()),
4483           S, Parser.getTok().getLoc()));
4484     return MatchOperand_Success;
4485   }
4486   // Also handle plain integers. Instructions which allow floating point
4487   // immediates also allow a raw encoded 8-bit value.
4488   if (Tok.is(AsmToken::Integer)) {
4489     int64_t Val = Tok.getIntVal();
4490     Parser.Lex(); // Eat the token.
4491     if (Val > 255 || Val < 0) {
4492       Error(Loc, "encoded floating point value out of range");
4493       return MatchOperand_ParseFail;
4494     }
4495     double RealVal = ARM_AM::getFPImmFloat(Val);
4496     Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4497     Operands.push_back(ARMOperand::CreateImm(
4498         MCConstantExpr::Create(Val, getContext()), S,
4499         Parser.getTok().getLoc()));
4500     return MatchOperand_Success;
4501   }
4502 
4503   Error(Loc, "invalid floating point immediate");
4504   return MatchOperand_ParseFail;
4505 }
4506 
4507 /// Parse a arm instruction operand.  For now this parses the operand regardless
4508 /// of the mnemonic.
4509 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4510                                 StringRef Mnemonic) {
4511   SMLoc S, E;
4512 
4513   // Check if the current operand has a custom associated parser, if so, try to
4514   // custom parse the operand, or fallback to the general approach.
4515   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4516   if (ResTy == MatchOperand_Success)
4517     return false;
4518   // If there wasn't a custom match, try the generic matcher below. Otherwise,
4519   // there was a match, but an error occurred, in which case, just return that
4520   // the operand parsing failed.
4521   if (ResTy == MatchOperand_ParseFail)
4522     return true;
4523 
4524   switch (getLexer().getKind()) {
4525   default:
4526     Error(Parser.getTok().getLoc(), "unexpected token in operand");
4527     return true;
4528   case AsmToken::Identifier: {
4529     // If we've seen a branch mnemonic, the next operand must be a label.  This
4530     // is true even if the label is a register name.  So "br r1" means branch to
4531     // label "r1".
4532     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4533     if (!ExpectLabel) {
4534       if (!tryParseRegisterWithWriteBack(Operands))
4535         return false;
4536       int Res = tryParseShiftRegister(Operands);
4537       if (Res == 0) // success
4538         return false;
4539       else if (Res == -1) // irrecoverable error
4540         return true;
4541       // If this is VMRS, check for the apsr_nzcv operand.
4542       if (Mnemonic == "vmrs" &&
4543           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4544         S = Parser.getTok().getLoc();
4545         Parser.Lex();
4546         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4547         return false;
4548       }
4549     }
4550 
4551     // Fall though for the Identifier case that is not a register or a
4552     // special name.
4553   }
4554   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4555   case AsmToken::Integer: // things like 1f and 2b as a branch targets
4556   case AsmToken::String:  // quoted label names.
4557   case AsmToken::Dot: {   // . as a branch target
4558     // This was not a register so parse other operands that start with an
4559     // identifier (like labels) as expressions and create them as immediates.
4560     const MCExpr *IdVal;
4561     S = Parser.getTok().getLoc();
4562     if (getParser().parseExpression(IdVal))
4563       return true;
4564     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4565     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4566     return false;
4567   }
4568   case AsmToken::LBrac:
4569     return parseMemory(Operands);
4570   case AsmToken::LCurly:
4571     return parseRegisterList(Operands);
4572   case AsmToken::Dollar:
4573   case AsmToken::Hash: {
4574     // #42 -> immediate.
4575     S = Parser.getTok().getLoc();
4576     Parser.Lex();
4577 
4578     if (Parser.getTok().isNot(AsmToken::Colon)) {
4579       bool isNegative = Parser.getTok().is(AsmToken::Minus);
4580       const MCExpr *ImmVal;
4581       if (getParser().parseExpression(ImmVal))
4582         return true;
4583       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4584       if (CE) {
4585         int32_t Val = CE->getValue();
4586         if (isNegative && Val == 0)
4587           ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4588       }
4589       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4590       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4591 
4592       // There can be a trailing '!' on operands that we want as a separate
4593       // '!' Token operand. Handle that here. For example, the compatibilty
4594       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4595       if (Parser.getTok().is(AsmToken::Exclaim)) {
4596         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4597                                                    Parser.getTok().getLoc()));
4598         Parser.Lex(); // Eat exclaim token
4599       }
4600       return false;
4601     }
4602     // w/ a ':' after the '#', it's just like a plain ':'.
4603     // FALLTHROUGH
4604   }
4605   case AsmToken::Colon: {
4606     // ":lower16:" and ":upper16:" expression prefixes
4607     // FIXME: Check it's an expression prefix,
4608     // e.g. (FOO - :lower16:BAR) isn't legal.
4609     ARMMCExpr::VariantKind RefKind;
4610     if (parsePrefix(RefKind))
4611       return true;
4612 
4613     const MCExpr *SubExprVal;
4614     if (getParser().parseExpression(SubExprVal))
4615       return true;
4616 
4617     const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4618                                               getContext());
4619     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4620     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4621     return false;
4622   }
4623   }
4624 }
4625 
4626 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4627 //  :lower16: and :upper16:.
4628 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4629   RefKind = ARMMCExpr::VK_ARM_None;
4630 
4631   // :lower16: and :upper16: modifiers
4632   assert(getLexer().is(AsmToken::Colon) && "expected a :");
4633   Parser.Lex(); // Eat ':'
4634 
4635   if (getLexer().isNot(AsmToken::Identifier)) {
4636     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4637     return true;
4638   }
4639 
4640   StringRef IDVal = Parser.getTok().getIdentifier();
4641   if (IDVal == "lower16") {
4642     RefKind = ARMMCExpr::VK_ARM_LO16;
4643   } else if (IDVal == "upper16") {
4644     RefKind = ARMMCExpr::VK_ARM_HI16;
4645   } else {
4646     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4647     return true;
4648   }
4649   Parser.Lex();
4650 
4651   if (getLexer().isNot(AsmToken::Colon)) {
4652     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4653     return true;
4654   }
4655   Parser.Lex(); // Eat the last ':'
4656   return false;
4657 }
4658 
4659 /// \brief Given a mnemonic, split out possible predication code and carry
4660 /// setting letters to form a canonical mnemonic and flags.
4661 //
4662 // FIXME: Would be nice to autogen this.
4663 // FIXME: This is a bit of a maze of special cases.
4664 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4665                                       unsigned &PredicationCode,
4666                                       bool &CarrySetting,
4667                                       unsigned &ProcessorIMod,
4668                                       StringRef &ITMask) {
4669   PredicationCode = ARMCC::AL;
4670   CarrySetting = false;
4671   ProcessorIMod = 0;
4672 
4673   // Ignore some mnemonics we know aren't predicated forms.
4674   //
4675   // FIXME: Would be nice to autogen this.
4676   if ((Mnemonic == "movs" && isThumb()) ||
4677       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4678       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4679       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4680       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4681       Mnemonic == "vaclt" || Mnemonic == "vacle"  ||
4682       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4683       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4684       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4685       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4686       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
4687       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4688       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4689     return Mnemonic;
4690 
4691   // First, split out any predication code. Ignore mnemonics we know aren't
4692   // predicated but do have a carry-set and so weren't caught above.
4693   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4694       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4695       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4696       Mnemonic != "sbcs" && Mnemonic != "rscs") {
4697     unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4698       .Case("eq", ARMCC::EQ)
4699       .Case("ne", ARMCC::NE)
4700       .Case("hs", ARMCC::HS)
4701       .Case("cs", ARMCC::HS)
4702       .Case("lo", ARMCC::LO)
4703       .Case("cc", ARMCC::LO)
4704       .Case("mi", ARMCC::MI)
4705       .Case("pl", ARMCC::PL)
4706       .Case("vs", ARMCC::VS)
4707       .Case("vc", ARMCC::VC)
4708       .Case("hi", ARMCC::HI)
4709       .Case("ls", ARMCC::LS)
4710       .Case("ge", ARMCC::GE)
4711       .Case("lt", ARMCC::LT)
4712       .Case("gt", ARMCC::GT)
4713       .Case("le", ARMCC::LE)
4714       .Case("al", ARMCC::AL)
4715       .Default(~0U);
4716     if (CC != ~0U) {
4717       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4718       PredicationCode = CC;
4719     }
4720   }
4721 
4722   // Next, determine if we have a carry setting bit. We explicitly ignore all
4723   // the instructions we know end in 's'.
4724   if (Mnemonic.endswith("s") &&
4725       !(Mnemonic == "cps" || Mnemonic == "mls" ||
4726         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4727         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4728         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4729         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4730         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4731         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4732         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4733         Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4734         (Mnemonic == "movs" && isThumb()))) {
4735     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4736     CarrySetting = true;
4737   }
4738 
4739   // The "cps" instruction can have a interrupt mode operand which is glued into
4740   // the mnemonic. Check if this is the case, split it and parse the imod op
4741   if (Mnemonic.startswith("cps")) {
4742     // Split out any imod code.
4743     unsigned IMod =
4744       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4745       .Case("ie", ARM_PROC::IE)
4746       .Case("id", ARM_PROC::ID)
4747       .Default(~0U);
4748     if (IMod != ~0U) {
4749       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4750       ProcessorIMod = IMod;
4751     }
4752   }
4753 
4754   // The "it" instruction has the condition mask on the end of the mnemonic.
4755   if (Mnemonic.startswith("it")) {
4756     ITMask = Mnemonic.slice(2, Mnemonic.size());
4757     Mnemonic = Mnemonic.slice(0, 2);
4758   }
4759 
4760   return Mnemonic;
4761 }
4762 
4763 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4764 /// inclusion of carry set or predication code operands.
4765 //
4766 // FIXME: It would be nice to autogen this.
4767 void ARMAsmParser::
4768 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4769                       bool &CanAcceptPredicationCode) {
4770   if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4771       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4772       Mnemonic == "add" || Mnemonic == "adc" ||
4773       Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4774       Mnemonic == "orr" || Mnemonic == "mvn" ||
4775       Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4776       Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4777       Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4778       (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4779                       Mnemonic == "mla" || Mnemonic == "smlal" ||
4780                       Mnemonic == "umlal" || Mnemonic == "umull"))) {
4781     CanAcceptCarrySet = true;
4782   } else
4783     CanAcceptCarrySet = false;
4784 
4785   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4786       Mnemonic == "cps" ||  Mnemonic == "it" ||  Mnemonic == "cbz" ||
4787       Mnemonic == "trap" || Mnemonic == "setend" ||
4788       Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4789       Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4790       Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4791       Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4792       Mnemonic == "vrintm") {
4793     // These mnemonics are never predicable
4794     CanAcceptPredicationCode = false;
4795   } else if (!isThumb()) {
4796     // Some instructions are only predicable in Thumb mode
4797     CanAcceptPredicationCode
4798       = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4799         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4800         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4801         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4802         Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4803         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4804         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4805   } else if (isThumbOne()) {
4806     CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4807   } else
4808     CanAcceptPredicationCode = true;
4809 }
4810 
4811 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4812                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4813   // FIXME: This is all horribly hacky. We really need a better way to deal
4814   // with optional operands like this in the matcher table.
4815 
4816   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4817   // another does not. Specifically, the MOVW instruction does not. So we
4818   // special case it here and remove the defaulted (non-setting) cc_out
4819   // operand if that's the instruction we're trying to match.
4820   //
4821   // We do this as post-processing of the explicit operands rather than just
4822   // conditionally adding the cc_out in the first place because we need
4823   // to check the type of the parsed immediate operand.
4824   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4825       !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4826       static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4827       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4828     return true;
4829 
4830   // Register-register 'add' for thumb does not have a cc_out operand
4831   // when there are only two register operands.
4832   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4833       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4834       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4835       static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4836     return true;
4837   // Register-register 'add' for thumb does not have a cc_out operand
4838   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4839   // have to check the immediate range here since Thumb2 has a variant
4840   // that can handle a different range and has a cc_out operand.
4841   if (((isThumb() && Mnemonic == "add") ||
4842        (isThumbTwo() && Mnemonic == "sub")) &&
4843       Operands.size() == 6 &&
4844       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4845       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4846       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4847       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4848       ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4849        static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4850     return true;
4851   // For Thumb2, add/sub immediate does not have a cc_out operand for the
4852   // imm0_4095 variant. That's the least-preferred variant when
4853   // selecting via the generic "add" mnemonic, so to know that we
4854   // should remove the cc_out operand, we have to explicitly check that
4855   // it's not one of the other variants. Ugh.
4856   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4857       Operands.size() == 6 &&
4858       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4859       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4860       static_cast<ARMOperand*>(Operands[5])->isImm()) {
4861     // Nest conditions rather than one big 'if' statement for readability.
4862     //
4863     // If both registers are low, we're in an IT block, and the immediate is
4864     // in range, we should use encoding T1 instead, which has a cc_out.
4865     if (inITBlock() &&
4866         isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4867         isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4868         static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4869       return false;
4870     // Check against T3. If the second register is the PC, this is an
4871     // alternate form of ADR, which uses encoding T4, so check for that too.
4872     if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4873         static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4874       return false;
4875 
4876     // Otherwise, we use encoding T4, which does not have a cc_out
4877     // operand.
4878     return true;
4879   }
4880 
4881   // The thumb2 multiply instruction doesn't have a CCOut register, so
4882   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4883   // use the 16-bit encoding or not.
4884   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4885       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4886       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4887       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4888       static_cast<ARMOperand*>(Operands[5])->isReg() &&
4889       // If the registers aren't low regs, the destination reg isn't the
4890       // same as one of the source regs, or the cc_out operand is zero
4891       // outside of an IT block, we have to use the 32-bit encoding, so
4892       // remove the cc_out operand.
4893       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4894        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4895        !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4896        !inITBlock() ||
4897        (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4898         static_cast<ARMOperand*>(Operands[5])->getReg() &&
4899         static_cast<ARMOperand*>(Operands[3])->getReg() !=
4900         static_cast<ARMOperand*>(Operands[4])->getReg())))
4901     return true;
4902 
4903   // Also check the 'mul' syntax variant that doesn't specify an explicit
4904   // destination register.
4905   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4906       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4907       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4908       static_cast<ARMOperand*>(Operands[4])->isReg() &&
4909       // If the registers aren't low regs  or the cc_out operand is zero
4910       // outside of an IT block, we have to use the 32-bit encoding, so
4911       // remove the cc_out operand.
4912       (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4913        !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4914        !inITBlock()))
4915     return true;
4916 
4917 
4918 
4919   // Register-register 'add/sub' for thumb does not have a cc_out operand
4920   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4921   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4922   // right, this will result in better diagnostics (which operand is off)
4923   // anyway.
4924   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4925       (Operands.size() == 5 || Operands.size() == 6) &&
4926       static_cast<ARMOperand*>(Operands[3])->isReg() &&
4927       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4928       static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4929       (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4930        (Operands.size() == 6 &&
4931         static_cast<ARMOperand*>(Operands[5])->isImm())))
4932     return true;
4933 
4934   return false;
4935 }
4936 
4937 bool ARMAsmParser::shouldOmitPredicateOperand(
4938     StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
4939   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
4940   unsigned RegIdx = 3;
4941   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
4942       static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
4943     if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
4944         static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
4945       RegIdx = 4;
4946 
4947     if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
4948         (ARMMCRegisterClasses[ARM::DPRRegClassID]
4949              .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4950          ARMMCRegisterClasses[ARM::QPRRegClassID]
4951              .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
4952       return true;
4953   }
4954   return false;
4955 }
4956 
4957 bool ARMAsmParser::isDeprecated(MCInst &Inst, StringRef &Info) {
4958   if (hasV8Ops() && Inst.getOpcode() == ARM::SETEND) {
4959     Info = "armv8";
4960     return true;
4961   }
4962   return false;
4963 }
4964 
4965 static bool isDataTypeToken(StringRef Tok) {
4966   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4967     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4968     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4969     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4970     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4971     Tok == ".f" || Tok == ".d";
4972 }
4973 
4974 // FIXME: This bit should probably be handled via an explicit match class
4975 // in the .td files that matches the suffix instead of having it be
4976 // a literal string token the way it is now.
4977 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4978   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4979 }
4980 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
4981                                  unsigned VariantID);
4982 /// Parse an arm instruction mnemonic followed by its operands.
4983 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4984                                     SMLoc NameLoc,
4985                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4986   // Apply mnemonic aliases before doing anything else, as the destination
4987   // mnemnonic may include suffices and we want to handle them normally.
4988   // The generic tblgen'erated code does this later, at the start of
4989   // MatchInstructionImpl(), but that's too late for aliases that include
4990   // any sort of suffix.
4991   unsigned AvailableFeatures = getAvailableFeatures();
4992   unsigned AssemblerDialect = getParser().getAssemblerDialect();
4993   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
4994 
4995   // First check for the ARM-specific .req directive.
4996   if (Parser.getTok().is(AsmToken::Identifier) &&
4997       Parser.getTok().getIdentifier() == ".req") {
4998     parseDirectiveReq(Name, NameLoc);
4999     // We always return 'error' for this, as we're done with this
5000     // statement and don't need to match the 'instruction."
5001     return true;
5002   }
5003 
5004   // Create the leading tokens for the mnemonic, split by '.' characters.
5005   size_t Start = 0, Next = Name.find('.');
5006   StringRef Mnemonic = Name.slice(Start, Next);
5007 
5008   // Split out the predication code and carry setting flag from the mnemonic.
5009   unsigned PredicationCode;
5010   unsigned ProcessorIMod;
5011   bool CarrySetting;
5012   StringRef ITMask;
5013   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5014                            ProcessorIMod, ITMask);
5015 
5016   // In Thumb1, only the branch (B) instruction can be predicated.
5017   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5018     Parser.eatToEndOfStatement();
5019     return Error(NameLoc, "conditional execution not supported in Thumb1");
5020   }
5021 
5022   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5023 
5024   // Handle the IT instruction ITMask. Convert it to a bitmask. This
5025   // is the mask as it will be for the IT encoding if the conditional
5026   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5027   // where the conditional bit0 is zero, the instruction post-processing
5028   // will adjust the mask accordingly.
5029   if (Mnemonic == "it") {
5030     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5031     if (ITMask.size() > 3) {
5032       Parser.eatToEndOfStatement();
5033       return Error(Loc, "too many conditions on IT instruction");
5034     }
5035     unsigned Mask = 8;
5036     for (unsigned i = ITMask.size(); i != 0; --i) {
5037       char pos = ITMask[i - 1];
5038       if (pos != 't' && pos != 'e') {
5039         Parser.eatToEndOfStatement();
5040         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5041       }
5042       Mask >>= 1;
5043       if (ITMask[i - 1] == 't')
5044         Mask |= 8;
5045     }
5046     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5047   }
5048 
5049   // FIXME: This is all a pretty gross hack. We should automatically handle
5050   // optional operands like this via tblgen.
5051 
5052   // Next, add the CCOut and ConditionCode operands, if needed.
5053   //
5054   // For mnemonics which can ever incorporate a carry setting bit or predication
5055   // code, our matching model involves us always generating CCOut and
5056   // ConditionCode operands to match the mnemonic "as written" and then we let
5057   // the matcher deal with finding the right instruction or generating an
5058   // appropriate error.
5059   bool CanAcceptCarrySet, CanAcceptPredicationCode;
5060   getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5061 
5062   // If we had a carry-set on an instruction that can't do that, issue an
5063   // error.
5064   if (!CanAcceptCarrySet && CarrySetting) {
5065     Parser.eatToEndOfStatement();
5066     return Error(NameLoc, "instruction '" + Mnemonic +
5067                  "' can not set flags, but 's' suffix specified");
5068   }
5069   // If we had a predication code on an instruction that can't do that, issue an
5070   // error.
5071   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5072     Parser.eatToEndOfStatement();
5073     return Error(NameLoc, "instruction '" + Mnemonic +
5074                  "' is not predicable, but condition code specified");
5075   }
5076 
5077   // Add the carry setting operand, if necessary.
5078   if (CanAcceptCarrySet) {
5079     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5080     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5081                                                Loc));
5082   }
5083 
5084   // Add the predication code operand, if necessary.
5085   if (CanAcceptPredicationCode) {
5086     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5087                                       CarrySetting);
5088     Operands.push_back(ARMOperand::CreateCondCode(
5089                          ARMCC::CondCodes(PredicationCode), Loc));
5090   }
5091 
5092   // Add the processor imod operand, if necessary.
5093   if (ProcessorIMod) {
5094     Operands.push_back(ARMOperand::CreateImm(
5095           MCConstantExpr::Create(ProcessorIMod, getContext()),
5096                                  NameLoc, NameLoc));
5097   }
5098 
5099   // Add the remaining tokens in the mnemonic.
5100   while (Next != StringRef::npos) {
5101     Start = Next;
5102     Next = Name.find('.', Start + 1);
5103     StringRef ExtraToken = Name.slice(Start, Next);
5104 
5105     // Some NEON instructions have an optional datatype suffix that is
5106     // completely ignored. Check for that.
5107     if (isDataTypeToken(ExtraToken) &&
5108         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5109       continue;
5110 
5111     // For for ARM mode generate an error if the .n qualifier is used.
5112     if (ExtraToken == ".n" && !isThumb()) {
5113       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5114       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5115                    "arm mode");
5116     }
5117 
5118     // The .n qualifier is always discarded as that is what the tables
5119     // and matcher expect.  In ARM mode the .w qualifier has no effect,
5120     // so discard it to avoid errors that can be caused by the matcher.
5121     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5122       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5123       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5124     }
5125   }
5126 
5127   // Read the remaining operands.
5128   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5129     // Read the first operand.
5130     if (parseOperand(Operands, Mnemonic)) {
5131       Parser.eatToEndOfStatement();
5132       return true;
5133     }
5134 
5135     while (getLexer().is(AsmToken::Comma)) {
5136       Parser.Lex();  // Eat the comma.
5137 
5138       // Parse and remember the operand.
5139       if (parseOperand(Operands, Mnemonic)) {
5140         Parser.eatToEndOfStatement();
5141         return true;
5142       }
5143     }
5144   }
5145 
5146   if (getLexer().isNot(AsmToken::EndOfStatement)) {
5147     SMLoc Loc = getLexer().getLoc();
5148     Parser.eatToEndOfStatement();
5149     return Error(Loc, "unexpected token in argument list");
5150   }
5151 
5152   Parser.Lex(); // Consume the EndOfStatement
5153 
5154   // Some instructions, mostly Thumb, have forms for the same mnemonic that
5155   // do and don't have a cc_out optional-def operand. With some spot-checks
5156   // of the operand list, we can figure out which variant we're trying to
5157   // parse and adjust accordingly before actually matching. We shouldn't ever
5158   // try to remove a cc_out operand that was explicitly set on the the
5159   // mnemonic, of course (CarrySetting == true). Reason number #317 the
5160   // table driven matcher doesn't fit well with the ARM instruction set.
5161   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5162     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5163     Operands.erase(Operands.begin() + 1);
5164     delete Op;
5165   }
5166 
5167   // Some instructions have the same mnemonic, but don't always
5168   // have a predicate. Distinguish them here and delete the
5169   // predicate if needed.
5170   if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5171     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5172     Operands.erase(Operands.begin() + 1);
5173     delete Op;
5174   }
5175 
5176   // ARM mode 'blx' need special handling, as the register operand version
5177   // is predicable, but the label operand version is not. So, we can't rely
5178   // on the Mnemonic based checking to correctly figure out when to put
5179   // a k_CondCode operand in the list. If we're trying to match the label
5180   // version, remove the k_CondCode operand here.
5181   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5182       static_cast<ARMOperand*>(Operands[2])->isImm()) {
5183     ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5184     Operands.erase(Operands.begin() + 1);
5185     delete Op;
5186   }
5187 
5188   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5189   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5190   // a single GPRPair reg operand is used in the .td file to replace the two
5191   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5192   // expressed as a GPRPair, so we have to manually merge them.
5193   // FIXME: We would really like to be able to tablegen'erate this.
5194   if (!isThumb() && Operands.size() > 4 &&
5195       (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5196     bool isLoad = (Mnemonic == "ldrexd");
5197     unsigned Idx = isLoad ? 2 : 3;
5198     ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5199     ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5200 
5201     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5202     // Adjust only if Op1 and Op2 are GPRs.
5203     if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5204         MRC.contains(Op2->getReg())) {
5205       unsigned Reg1 = Op1->getReg();
5206       unsigned Reg2 = Op2->getReg();
5207       unsigned Rt = MRI->getEncodingValue(Reg1);
5208       unsigned Rt2 = MRI->getEncodingValue(Reg2);
5209 
5210       // Rt2 must be Rt + 1 and Rt must be even.
5211       if (Rt + 1 != Rt2 || (Rt & 1)) {
5212         Error(Op2->getStartLoc(), isLoad ?
5213             "destination operands must be sequential" :
5214             "source operands must be sequential");
5215         return true;
5216       }
5217       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5218           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5219       Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5220       Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5221             NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5222       delete Op1;
5223       delete Op2;
5224     }
5225   }
5226 
5227   // FIXME: As said above, this is all a pretty gross hack.  This instruction
5228   // does not fit with other "subs" and tblgen.
5229   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5230   // so the Mnemonic is the original name "subs" and delete the predicate
5231   // operand so it will match the table entry.
5232   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5233       static_cast<ARMOperand*>(Operands[3])->isReg() &&
5234       static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5235       static_cast<ARMOperand*>(Operands[4])->isReg() &&
5236       static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5237       static_cast<ARMOperand*>(Operands[5])->isImm()) {
5238     ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5239     Operands.erase(Operands.begin());
5240     delete Op0;
5241     Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5242 
5243     ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5244     Operands.erase(Operands.begin() + 1);
5245     delete Op1;
5246   }
5247   return false;
5248 }
5249 
5250 // Validate context-sensitive operand constraints.
5251 
5252 // return 'true' if register list contains non-low GPR registers,
5253 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5254 // 'containsReg' to true.
5255 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5256                                  unsigned HiReg, bool &containsReg) {
5257   containsReg = false;
5258   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5259     unsigned OpReg = Inst.getOperand(i).getReg();
5260     if (OpReg == Reg)
5261       containsReg = true;
5262     // Anything other than a low register isn't legal here.
5263     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5264       return true;
5265   }
5266   return false;
5267 }
5268 
5269 // Check if the specified regisgter is in the register list of the inst,
5270 // starting at the indicated operand number.
5271 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5272   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5273     unsigned OpReg = Inst.getOperand(i).getReg();
5274     if (OpReg == Reg)
5275       return true;
5276   }
5277   return false;
5278 }
5279 
5280 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5281 // the ARMInsts array) instead. Getting that here requires awkward
5282 // API changes, though. Better way?
5283 namespace llvm {
5284 extern const MCInstrDesc ARMInsts[];
5285 }
5286 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5287   return ARMInsts[Opcode];
5288 }
5289 
5290 // FIXME: We would really like to be able to tablegen'erate this.
5291 bool ARMAsmParser::
5292 validateInstruction(MCInst &Inst,
5293                     const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5294   const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5295   SMLoc Loc = Operands[0]->getStartLoc();
5296 
5297   // Check the IT block state first.
5298   // NOTE: BKPT instruction has the interesting property of being
5299   // allowed in IT blocks, but not being predicable.  It just always
5300   // executes.
5301   if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5302       Inst.getOpcode() != ARM::BKPT) {
5303     unsigned bit = 1;
5304     if (ITState.FirstCond)
5305       ITState.FirstCond = false;
5306     else
5307       bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5308     // The instruction must be predicable.
5309     if (!MCID.isPredicable())
5310       return Error(Loc, "instructions in IT block must be predicable");
5311     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5312     unsigned ITCond = bit ? ITState.Cond :
5313       ARMCC::getOppositeCondition(ITState.Cond);
5314     if (Cond != ITCond) {
5315       // Find the condition code Operand to get its SMLoc information.
5316       SMLoc CondLoc;
5317       for (unsigned i = 1; i < Operands.size(); ++i)
5318         if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5319           CondLoc = Operands[i]->getStartLoc();
5320       return Error(CondLoc, "incorrect condition in IT block; got '" +
5321                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5322                    "', but expected '" +
5323                    ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5324     }
5325   // Check for non-'al' condition codes outside of the IT block.
5326   } else if (isThumbTwo() && MCID.isPredicable() &&
5327              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5328              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5329              Inst.getOpcode() != ARM::t2Bcc)
5330     return Error(Loc, "predicated instructions must be in IT block");
5331 
5332   switch (Inst.getOpcode()) {
5333   case ARM::LDRD:
5334   case ARM::LDRD_PRE:
5335   case ARM::LDRD_POST: {
5336     // Rt2 must be Rt + 1.
5337     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5338     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5339     if (Rt2 != Rt + 1)
5340       return Error(Operands[3]->getStartLoc(),
5341                    "destination operands must be sequential");
5342     return false;
5343   }
5344   case ARM::STRD: {
5345     // Rt2 must be Rt + 1.
5346     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5347     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5348     if (Rt2 != Rt + 1)
5349       return Error(Operands[3]->getStartLoc(),
5350                    "source operands must be sequential");
5351     return false;
5352   }
5353   case ARM::STRD_PRE:
5354   case ARM::STRD_POST: {
5355     // Rt2 must be Rt + 1.
5356     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5357     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5358     if (Rt2 != Rt + 1)
5359       return Error(Operands[3]->getStartLoc(),
5360                    "source operands must be sequential");
5361     return false;
5362   }
5363   case ARM::SBFX:
5364   case ARM::UBFX: {
5365     // width must be in range [1, 32-lsb]
5366     unsigned lsb = Inst.getOperand(2).getImm();
5367     unsigned widthm1 = Inst.getOperand(3).getImm();
5368     if (widthm1 >= 32 - lsb)
5369       return Error(Operands[5]->getStartLoc(),
5370                    "bitfield width must be in range [1,32-lsb]");
5371     return false;
5372   }
5373   case ARM::tLDMIA: {
5374     // If we're parsing Thumb2, the .w variant is available and handles
5375     // most cases that are normally illegal for a Thumb1 LDM
5376     // instruction. We'll make the transformation in processInstruction()
5377     // if necessary.
5378     //
5379     // Thumb LDM instructions are writeback iff the base register is not
5380     // in the register list.
5381     unsigned Rn = Inst.getOperand(0).getReg();
5382     bool hasWritebackToken =
5383       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5384        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5385     bool listContainsBase;
5386     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5387       return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5388                    "registers must be in range r0-r7");
5389     // If we should have writeback, then there should be a '!' token.
5390     if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5391       return Error(Operands[2]->getStartLoc(),
5392                    "writeback operator '!' expected");
5393     // If we should not have writeback, there must not be a '!'. This is
5394     // true even for the 32-bit wide encodings.
5395     if (listContainsBase && hasWritebackToken)
5396       return Error(Operands[3]->getStartLoc(),
5397                    "writeback operator '!' not allowed when base register "
5398                    "in register list");
5399 
5400     break;
5401   }
5402   case ARM::t2LDMIA_UPD: {
5403     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5404       return Error(Operands[4]->getStartLoc(),
5405                    "writeback operator '!' not allowed when base register "
5406                    "in register list");
5407     break;
5408   }
5409   case ARM::tMUL: {
5410     // The second source operand must be the same register as the destination
5411     // operand.
5412     //
5413     // In this case, we must directly check the parsed operands because the
5414     // cvtThumbMultiply() function is written in such a way that it guarantees
5415     // this first statement is always true for the new Inst.  Essentially, the
5416     // destination is unconditionally copied into the second source operand
5417     // without checking to see if it matches what we actually parsed.
5418     if (Operands.size() == 6 &&
5419         (((ARMOperand*)Operands[3])->getReg() !=
5420          ((ARMOperand*)Operands[5])->getReg()) &&
5421         (((ARMOperand*)Operands[3])->getReg() !=
5422          ((ARMOperand*)Operands[4])->getReg())) {
5423       return Error(Operands[3]->getStartLoc(),
5424                    "destination register must match source register");
5425     }
5426     break;
5427   }
5428   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5429   // so only issue a diagnostic for thumb1. The instructions will be
5430   // switched to the t2 encodings in processInstruction() if necessary.
5431   case ARM::tPOP: {
5432     bool listContainsBase;
5433     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5434         !isThumbTwo())
5435       return Error(Operands[2]->getStartLoc(),
5436                    "registers must be in range r0-r7 or pc");
5437     break;
5438   }
5439   case ARM::tPUSH: {
5440     bool listContainsBase;
5441     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5442         !isThumbTwo())
5443       return Error(Operands[2]->getStartLoc(),
5444                    "registers must be in range r0-r7 or lr");
5445     break;
5446   }
5447   case ARM::tSTMIA_UPD: {
5448     bool listContainsBase;
5449     if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5450       return Error(Operands[4]->getStartLoc(),
5451                    "registers must be in range r0-r7");
5452     break;
5453   }
5454   case ARM::tADDrSP: {
5455     // If the non-SP source operand and the destination operand are not the
5456     // same, we need thumb2 (for the wide encoding), or we have an error.
5457     if (!isThumbTwo() &&
5458         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5459       return Error(Operands[4]->getStartLoc(),
5460                    "source register must be the same as destination");
5461     }
5462     break;
5463   }
5464   // final range checking for Thumb unconditional branch instructions
5465   case ARM::tB:
5466     if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5467       return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5468     break;
5469   case ARM::t2B: {
5470     int op = (Operands[2]->isImm()) ? 2 : 3;
5471     if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5472       return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5473     break;
5474   }
5475   // final range checking for Thumb conditional branch instructions
5476   case ARM::tBcc:
5477     if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5478       return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5479     break;
5480   case ARM::t2Bcc: {
5481     int op = (Operands[2]->isImm()) ? 2 : 3;
5482     if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<20, 1>())
5483       return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5484     break;
5485   }
5486   }
5487 
5488   StringRef DepInfo;
5489   if (isDeprecated(Inst, DepInfo))
5490     Warning(Loc, "deprecated on " + DepInfo);
5491 
5492   return false;
5493 }
5494 
5495 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5496   switch(Opc) {
5497   default: llvm_unreachable("unexpected opcode!");
5498   // VST1LN
5499   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5500   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5501   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5502   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5503   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5504   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5505   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5506   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5507   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5508 
5509   // VST2LN
5510   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5511   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5512   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5513   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5514   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5515 
5516   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5517   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5518   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5519   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5520   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5521 
5522   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5523   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5524   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5525   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5526   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5527 
5528   // VST3LN
5529   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5530   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5531   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5532   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5533   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5534   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5535   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5536   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5537   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5538   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5539   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5540   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5541   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5542   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5543   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5544 
5545   // VST3
5546   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5547   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5548   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5549   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5550   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5551   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5552   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5553   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5554   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5555   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5556   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5557   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5558   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5559   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5560   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5561   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5562   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5563   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5564 
5565   // VST4LN
5566   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5567   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5568   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5569   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5570   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5571   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5572   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5573   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5574   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5575   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5576   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5577   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5578   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5579   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5580   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5581 
5582   // VST4
5583   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5584   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5585   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5586   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5587   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5588   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5589   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5590   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5591   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5592   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5593   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5594   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5595   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5596   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5597   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5598   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5599   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5600   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5601   }
5602 }
5603 
5604 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5605   switch(Opc) {
5606   default: llvm_unreachable("unexpected opcode!");
5607   // VLD1LN
5608   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5609   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5610   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5611   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5612   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5613   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5614   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5615   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5616   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5617 
5618   // VLD2LN
5619   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5620   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5621   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5622   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5623   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5624   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5625   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5626   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5627   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5628   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5629   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5630   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5631   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5632   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5633   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5634 
5635   // VLD3DUP
5636   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5637   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5638   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5639   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5640   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5641   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5642   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5643   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5644   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5645   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5646   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5647   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5648   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5649   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5650   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5651   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5652   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5653   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5654 
5655   // VLD3LN
5656   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5657   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5658   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5659   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5660   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5661   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5662   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5663   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5664   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5665   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5666   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5667   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5668   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5669   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5670   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5671 
5672   // VLD3
5673   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5674   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5675   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5676   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5677   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5678   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5679   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5680   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5681   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5682   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5683   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5684   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5685   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5686   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5687   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5688   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5689   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5690   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5691 
5692   // VLD4LN
5693   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5694   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5695   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5696   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5697   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5698   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5699   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5700   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5701   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5702   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5703   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5704   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5705   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5706   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5707   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5708 
5709   // VLD4DUP
5710   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5711   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5712   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5713   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5714   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5715   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5716   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5717   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5718   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5719   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5720   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5721   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5722   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5723   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5724   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5725   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5726   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5727   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5728 
5729   // VLD4
5730   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5731   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5732   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5733   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5734   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5735   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5736   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5737   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5738   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5739   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5740   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5741   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5742   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5743   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5744   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5745   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5746   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5747   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5748   }
5749 }
5750 
5751 bool ARMAsmParser::
5752 processInstruction(MCInst &Inst,
5753                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5754   switch (Inst.getOpcode()) {
5755   // Alias for alternate form of 'ADR Rd, #imm' instruction.
5756   case ARM::ADDri: {
5757     if (Inst.getOperand(1).getReg() != ARM::PC ||
5758         Inst.getOperand(5).getReg() != 0)
5759       return false;
5760     MCInst TmpInst;
5761     TmpInst.setOpcode(ARM::ADR);
5762     TmpInst.addOperand(Inst.getOperand(0));
5763     TmpInst.addOperand(Inst.getOperand(2));
5764     TmpInst.addOperand(Inst.getOperand(3));
5765     TmpInst.addOperand(Inst.getOperand(4));
5766     Inst = TmpInst;
5767     return true;
5768   }
5769   // Aliases for alternate PC+imm syntax of LDR instructions.
5770   case ARM::t2LDRpcrel:
5771     // Select the narrow version if the immediate will fit.
5772     if (Inst.getOperand(1).getImm() > 0 &&
5773         Inst.getOperand(1).getImm() <= 0xff &&
5774         !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5775          static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5776       Inst.setOpcode(ARM::tLDRpci);
5777     else
5778       Inst.setOpcode(ARM::t2LDRpci);
5779     return true;
5780   case ARM::t2LDRBpcrel:
5781     Inst.setOpcode(ARM::t2LDRBpci);
5782     return true;
5783   case ARM::t2LDRHpcrel:
5784     Inst.setOpcode(ARM::t2LDRHpci);
5785     return true;
5786   case ARM::t2LDRSBpcrel:
5787     Inst.setOpcode(ARM::t2LDRSBpci);
5788     return true;
5789   case ARM::t2LDRSHpcrel:
5790     Inst.setOpcode(ARM::t2LDRSHpci);
5791     return true;
5792   // Handle NEON VST complex aliases.
5793   case ARM::VST1LNdWB_register_Asm_8:
5794   case ARM::VST1LNdWB_register_Asm_16:
5795   case ARM::VST1LNdWB_register_Asm_32: {
5796     MCInst TmpInst;
5797     // Shuffle the operands around so the lane index operand is in the
5798     // right place.
5799     unsigned Spacing;
5800     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5801     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5802     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5803     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5804     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5805     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5806     TmpInst.addOperand(Inst.getOperand(1)); // lane
5807     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5808     TmpInst.addOperand(Inst.getOperand(6));
5809     Inst = TmpInst;
5810     return true;
5811   }
5812 
5813   case ARM::VST2LNdWB_register_Asm_8:
5814   case ARM::VST2LNdWB_register_Asm_16:
5815   case ARM::VST2LNdWB_register_Asm_32:
5816   case ARM::VST2LNqWB_register_Asm_16:
5817   case ARM::VST2LNqWB_register_Asm_32: {
5818     MCInst TmpInst;
5819     // Shuffle the operands around so the lane index operand is in the
5820     // right place.
5821     unsigned Spacing;
5822     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5823     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5824     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5825     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5826     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5827     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5828     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5829                                             Spacing));
5830     TmpInst.addOperand(Inst.getOperand(1)); // lane
5831     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5832     TmpInst.addOperand(Inst.getOperand(6));
5833     Inst = TmpInst;
5834     return true;
5835   }
5836 
5837   case ARM::VST3LNdWB_register_Asm_8:
5838   case ARM::VST3LNdWB_register_Asm_16:
5839   case ARM::VST3LNdWB_register_Asm_32:
5840   case ARM::VST3LNqWB_register_Asm_16:
5841   case ARM::VST3LNqWB_register_Asm_32: {
5842     MCInst TmpInst;
5843     // Shuffle the operands around so the lane index operand is in the
5844     // right place.
5845     unsigned Spacing;
5846     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5847     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5848     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5849     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5850     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5851     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5852     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5853                                             Spacing));
5854     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5855                                             Spacing * 2));
5856     TmpInst.addOperand(Inst.getOperand(1)); // lane
5857     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5858     TmpInst.addOperand(Inst.getOperand(6));
5859     Inst = TmpInst;
5860     return true;
5861   }
5862 
5863   case ARM::VST4LNdWB_register_Asm_8:
5864   case ARM::VST4LNdWB_register_Asm_16:
5865   case ARM::VST4LNdWB_register_Asm_32:
5866   case ARM::VST4LNqWB_register_Asm_16:
5867   case ARM::VST4LNqWB_register_Asm_32: {
5868     MCInst TmpInst;
5869     // Shuffle the operands around so the lane index operand is in the
5870     // right place.
5871     unsigned Spacing;
5872     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5873     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5874     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5875     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5876     TmpInst.addOperand(Inst.getOperand(4)); // Rm
5877     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5878     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5879                                             Spacing));
5880     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5881                                             Spacing * 2));
5882     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5883                                             Spacing * 3));
5884     TmpInst.addOperand(Inst.getOperand(1)); // lane
5885     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5886     TmpInst.addOperand(Inst.getOperand(6));
5887     Inst = TmpInst;
5888     return true;
5889   }
5890 
5891   case ARM::VST1LNdWB_fixed_Asm_8:
5892   case ARM::VST1LNdWB_fixed_Asm_16:
5893   case ARM::VST1LNdWB_fixed_Asm_32: {
5894     MCInst TmpInst;
5895     // Shuffle the operands around so the lane index operand is in the
5896     // right place.
5897     unsigned Spacing;
5898     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5899     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5900     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5901     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5902     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5903     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5904     TmpInst.addOperand(Inst.getOperand(1)); // lane
5905     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5906     TmpInst.addOperand(Inst.getOperand(5));
5907     Inst = TmpInst;
5908     return true;
5909   }
5910 
5911   case ARM::VST2LNdWB_fixed_Asm_8:
5912   case ARM::VST2LNdWB_fixed_Asm_16:
5913   case ARM::VST2LNdWB_fixed_Asm_32:
5914   case ARM::VST2LNqWB_fixed_Asm_16:
5915   case ARM::VST2LNqWB_fixed_Asm_32: {
5916     MCInst TmpInst;
5917     // Shuffle the operands around so the lane index operand is in the
5918     // right place.
5919     unsigned Spacing;
5920     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5921     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5922     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5923     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5924     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5925     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5926     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5927                                             Spacing));
5928     TmpInst.addOperand(Inst.getOperand(1)); // lane
5929     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5930     TmpInst.addOperand(Inst.getOperand(5));
5931     Inst = TmpInst;
5932     return true;
5933   }
5934 
5935   case ARM::VST3LNdWB_fixed_Asm_8:
5936   case ARM::VST3LNdWB_fixed_Asm_16:
5937   case ARM::VST3LNdWB_fixed_Asm_32:
5938   case ARM::VST3LNqWB_fixed_Asm_16:
5939   case ARM::VST3LNqWB_fixed_Asm_32: {
5940     MCInst TmpInst;
5941     // Shuffle the operands around so the lane index operand is in the
5942     // right place.
5943     unsigned Spacing;
5944     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5945     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5946     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5947     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5948     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5949     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5950     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5951                                             Spacing));
5952     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5953                                             Spacing * 2));
5954     TmpInst.addOperand(Inst.getOperand(1)); // lane
5955     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5956     TmpInst.addOperand(Inst.getOperand(5));
5957     Inst = TmpInst;
5958     return true;
5959   }
5960 
5961   case ARM::VST4LNdWB_fixed_Asm_8:
5962   case ARM::VST4LNdWB_fixed_Asm_16:
5963   case ARM::VST4LNdWB_fixed_Asm_32:
5964   case ARM::VST4LNqWB_fixed_Asm_16:
5965   case ARM::VST4LNqWB_fixed_Asm_32: {
5966     MCInst TmpInst;
5967     // Shuffle the operands around so the lane index operand is in the
5968     // right place.
5969     unsigned Spacing;
5970     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5971     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5972     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5973     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5974     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5975     TmpInst.addOperand(Inst.getOperand(0)); // Vd
5976     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5977                                             Spacing));
5978     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5979                                             Spacing * 2));
5980     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5981                                             Spacing * 3));
5982     TmpInst.addOperand(Inst.getOperand(1)); // lane
5983     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5984     TmpInst.addOperand(Inst.getOperand(5));
5985     Inst = TmpInst;
5986     return true;
5987   }
5988 
5989   case ARM::VST1LNdAsm_8:
5990   case ARM::VST1LNdAsm_16:
5991   case ARM::VST1LNdAsm_32: {
5992     MCInst TmpInst;
5993     // Shuffle the operands around so the lane index operand is in the
5994     // right place.
5995     unsigned Spacing;
5996     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5997     TmpInst.addOperand(Inst.getOperand(2)); // Rn
5998     TmpInst.addOperand(Inst.getOperand(3)); // alignment
5999     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6000     TmpInst.addOperand(Inst.getOperand(1)); // lane
6001     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6002     TmpInst.addOperand(Inst.getOperand(5));
6003     Inst = TmpInst;
6004     return true;
6005   }
6006 
6007   case ARM::VST2LNdAsm_8:
6008   case ARM::VST2LNdAsm_16:
6009   case ARM::VST2LNdAsm_32:
6010   case ARM::VST2LNqAsm_16:
6011   case ARM::VST2LNqAsm_32: {
6012     MCInst TmpInst;
6013     // Shuffle the operands around so the lane index operand is in the
6014     // right place.
6015     unsigned Spacing;
6016     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6017     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6018     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6019     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6020     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6021                                             Spacing));
6022     TmpInst.addOperand(Inst.getOperand(1)); // lane
6023     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6024     TmpInst.addOperand(Inst.getOperand(5));
6025     Inst = TmpInst;
6026     return true;
6027   }
6028 
6029   case ARM::VST3LNdAsm_8:
6030   case ARM::VST3LNdAsm_16:
6031   case ARM::VST3LNdAsm_32:
6032   case ARM::VST3LNqAsm_16:
6033   case ARM::VST3LNqAsm_32: {
6034     MCInst TmpInst;
6035     // Shuffle the operands around so the lane index operand is in the
6036     // right place.
6037     unsigned Spacing;
6038     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6039     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6040     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6041     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6042     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6043                                             Spacing));
6044     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6045                                             Spacing * 2));
6046     TmpInst.addOperand(Inst.getOperand(1)); // lane
6047     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6048     TmpInst.addOperand(Inst.getOperand(5));
6049     Inst = TmpInst;
6050     return true;
6051   }
6052 
6053   case ARM::VST4LNdAsm_8:
6054   case ARM::VST4LNdAsm_16:
6055   case ARM::VST4LNdAsm_32:
6056   case ARM::VST4LNqAsm_16:
6057   case ARM::VST4LNqAsm_32: {
6058     MCInst TmpInst;
6059     // Shuffle the operands around so the lane index operand is in the
6060     // right place.
6061     unsigned Spacing;
6062     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6063     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6064     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6065     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6066     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6067                                             Spacing));
6068     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6069                                             Spacing * 2));
6070     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6071                                             Spacing * 3));
6072     TmpInst.addOperand(Inst.getOperand(1)); // lane
6073     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6074     TmpInst.addOperand(Inst.getOperand(5));
6075     Inst = TmpInst;
6076     return true;
6077   }
6078 
6079   // Handle NEON VLD complex aliases.
6080   case ARM::VLD1LNdWB_register_Asm_8:
6081   case ARM::VLD1LNdWB_register_Asm_16:
6082   case ARM::VLD1LNdWB_register_Asm_32: {
6083     MCInst TmpInst;
6084     // Shuffle the operands around so the lane index operand is in the
6085     // right place.
6086     unsigned Spacing;
6087     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6088     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6089     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6090     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6091     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6092     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6093     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6094     TmpInst.addOperand(Inst.getOperand(1)); // lane
6095     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6096     TmpInst.addOperand(Inst.getOperand(6));
6097     Inst = TmpInst;
6098     return true;
6099   }
6100 
6101   case ARM::VLD2LNdWB_register_Asm_8:
6102   case ARM::VLD2LNdWB_register_Asm_16:
6103   case ARM::VLD2LNdWB_register_Asm_32:
6104   case ARM::VLD2LNqWB_register_Asm_16:
6105   case ARM::VLD2LNqWB_register_Asm_32: {
6106     MCInst TmpInst;
6107     // Shuffle the operands around so the lane index operand is in the
6108     // right place.
6109     unsigned Spacing;
6110     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6111     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6112     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6113                                             Spacing));
6114     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6115     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6116     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6117     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6118     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6119     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6120                                             Spacing));
6121     TmpInst.addOperand(Inst.getOperand(1)); // lane
6122     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6123     TmpInst.addOperand(Inst.getOperand(6));
6124     Inst = TmpInst;
6125     return true;
6126   }
6127 
6128   case ARM::VLD3LNdWB_register_Asm_8:
6129   case ARM::VLD3LNdWB_register_Asm_16:
6130   case ARM::VLD3LNdWB_register_Asm_32:
6131   case ARM::VLD3LNqWB_register_Asm_16:
6132   case ARM::VLD3LNqWB_register_Asm_32: {
6133     MCInst TmpInst;
6134     // Shuffle the operands around so the lane index operand is in the
6135     // right place.
6136     unsigned Spacing;
6137     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6138     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6139     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6140                                             Spacing));
6141     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6142                                             Spacing * 2));
6143     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6144     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6145     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6146     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6147     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6148     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6149                                             Spacing));
6150     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6151                                             Spacing * 2));
6152     TmpInst.addOperand(Inst.getOperand(1)); // lane
6153     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6154     TmpInst.addOperand(Inst.getOperand(6));
6155     Inst = TmpInst;
6156     return true;
6157   }
6158 
6159   case ARM::VLD4LNdWB_register_Asm_8:
6160   case ARM::VLD4LNdWB_register_Asm_16:
6161   case ARM::VLD4LNdWB_register_Asm_32:
6162   case ARM::VLD4LNqWB_register_Asm_16:
6163   case ARM::VLD4LNqWB_register_Asm_32: {
6164     MCInst TmpInst;
6165     // Shuffle the operands around so the lane index operand is in the
6166     // right place.
6167     unsigned Spacing;
6168     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6169     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6170     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6171                                             Spacing));
6172     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6173                                             Spacing * 2));
6174     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6175                                             Spacing * 3));
6176     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6177     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6178     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6179     TmpInst.addOperand(Inst.getOperand(4)); // Rm
6180     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6181     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6182                                             Spacing));
6183     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6184                                             Spacing * 2));
6185     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6186                                             Spacing * 3));
6187     TmpInst.addOperand(Inst.getOperand(1)); // lane
6188     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6189     TmpInst.addOperand(Inst.getOperand(6));
6190     Inst = TmpInst;
6191     return true;
6192   }
6193 
6194   case ARM::VLD1LNdWB_fixed_Asm_8:
6195   case ARM::VLD1LNdWB_fixed_Asm_16:
6196   case ARM::VLD1LNdWB_fixed_Asm_32: {
6197     MCInst TmpInst;
6198     // Shuffle the operands around so the lane index operand is in the
6199     // right place.
6200     unsigned Spacing;
6201     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6202     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6203     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6204     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6205     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6206     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6207     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6208     TmpInst.addOperand(Inst.getOperand(1)); // lane
6209     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6210     TmpInst.addOperand(Inst.getOperand(5));
6211     Inst = TmpInst;
6212     return true;
6213   }
6214 
6215   case ARM::VLD2LNdWB_fixed_Asm_8:
6216   case ARM::VLD2LNdWB_fixed_Asm_16:
6217   case ARM::VLD2LNdWB_fixed_Asm_32:
6218   case ARM::VLD2LNqWB_fixed_Asm_16:
6219   case ARM::VLD2LNqWB_fixed_Asm_32: {
6220     MCInst TmpInst;
6221     // Shuffle the operands around so the lane index operand is in the
6222     // right place.
6223     unsigned Spacing;
6224     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6225     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6226     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6227                                             Spacing));
6228     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6229     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6230     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6231     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6232     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6233     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6234                                             Spacing));
6235     TmpInst.addOperand(Inst.getOperand(1)); // lane
6236     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6237     TmpInst.addOperand(Inst.getOperand(5));
6238     Inst = TmpInst;
6239     return true;
6240   }
6241 
6242   case ARM::VLD3LNdWB_fixed_Asm_8:
6243   case ARM::VLD3LNdWB_fixed_Asm_16:
6244   case ARM::VLD3LNdWB_fixed_Asm_32:
6245   case ARM::VLD3LNqWB_fixed_Asm_16:
6246   case ARM::VLD3LNqWB_fixed_Asm_32: {
6247     MCInst TmpInst;
6248     // Shuffle the operands around so the lane index operand is in the
6249     // right place.
6250     unsigned Spacing;
6251     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6252     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6253     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6254                                             Spacing));
6255     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6256                                             Spacing * 2));
6257     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6258     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6259     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6260     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6261     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6262     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6263                                             Spacing));
6264     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6265                                             Spacing * 2));
6266     TmpInst.addOperand(Inst.getOperand(1)); // lane
6267     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6268     TmpInst.addOperand(Inst.getOperand(5));
6269     Inst = TmpInst;
6270     return true;
6271   }
6272 
6273   case ARM::VLD4LNdWB_fixed_Asm_8:
6274   case ARM::VLD4LNdWB_fixed_Asm_16:
6275   case ARM::VLD4LNdWB_fixed_Asm_32:
6276   case ARM::VLD4LNqWB_fixed_Asm_16:
6277   case ARM::VLD4LNqWB_fixed_Asm_32: {
6278     MCInst TmpInst;
6279     // Shuffle the operands around so the lane index operand is in the
6280     // right place.
6281     unsigned Spacing;
6282     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6283     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6284     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6285                                             Spacing));
6286     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6287                                             Spacing * 2));
6288     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6289                                             Spacing * 3));
6290     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6291     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6292     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6293     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6294     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6295     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6296                                             Spacing));
6297     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6298                                             Spacing * 2));
6299     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6300                                             Spacing * 3));
6301     TmpInst.addOperand(Inst.getOperand(1)); // lane
6302     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6303     TmpInst.addOperand(Inst.getOperand(5));
6304     Inst = TmpInst;
6305     return true;
6306   }
6307 
6308   case ARM::VLD1LNdAsm_8:
6309   case ARM::VLD1LNdAsm_16:
6310   case ARM::VLD1LNdAsm_32: {
6311     MCInst TmpInst;
6312     // Shuffle the operands around so the lane index operand is in the
6313     // right place.
6314     unsigned Spacing;
6315     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6316     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6317     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6318     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6319     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6320     TmpInst.addOperand(Inst.getOperand(1)); // lane
6321     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6322     TmpInst.addOperand(Inst.getOperand(5));
6323     Inst = TmpInst;
6324     return true;
6325   }
6326 
6327   case ARM::VLD2LNdAsm_8:
6328   case ARM::VLD2LNdAsm_16:
6329   case ARM::VLD2LNdAsm_32:
6330   case ARM::VLD2LNqAsm_16:
6331   case ARM::VLD2LNqAsm_32: {
6332     MCInst TmpInst;
6333     // Shuffle the operands around so the lane index operand is in the
6334     // right place.
6335     unsigned Spacing;
6336     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6337     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6338     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6339                                             Spacing));
6340     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6341     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6342     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6343     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6344                                             Spacing));
6345     TmpInst.addOperand(Inst.getOperand(1)); // lane
6346     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6347     TmpInst.addOperand(Inst.getOperand(5));
6348     Inst = TmpInst;
6349     return true;
6350   }
6351 
6352   case ARM::VLD3LNdAsm_8:
6353   case ARM::VLD3LNdAsm_16:
6354   case ARM::VLD3LNdAsm_32:
6355   case ARM::VLD3LNqAsm_16:
6356   case ARM::VLD3LNqAsm_32: {
6357     MCInst TmpInst;
6358     // Shuffle the operands around so the lane index operand is in the
6359     // right place.
6360     unsigned Spacing;
6361     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6362     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6363     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6364                                             Spacing));
6365     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6366                                             Spacing * 2));
6367     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6368     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6369     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6370     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6371                                             Spacing));
6372     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6373                                             Spacing * 2));
6374     TmpInst.addOperand(Inst.getOperand(1)); // lane
6375     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6376     TmpInst.addOperand(Inst.getOperand(5));
6377     Inst = TmpInst;
6378     return true;
6379   }
6380 
6381   case ARM::VLD4LNdAsm_8:
6382   case ARM::VLD4LNdAsm_16:
6383   case ARM::VLD4LNdAsm_32:
6384   case ARM::VLD4LNqAsm_16:
6385   case ARM::VLD4LNqAsm_32: {
6386     MCInst TmpInst;
6387     // Shuffle the operands around so the lane index operand is in the
6388     // right place.
6389     unsigned Spacing;
6390     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6391     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6392     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6393                                             Spacing));
6394     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6395                                             Spacing * 2));
6396     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6397                                             Spacing * 3));
6398     TmpInst.addOperand(Inst.getOperand(2)); // Rn
6399     TmpInst.addOperand(Inst.getOperand(3)); // alignment
6400     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6401     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6402                                             Spacing));
6403     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404                                             Spacing * 2));
6405     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6406                                             Spacing * 3));
6407     TmpInst.addOperand(Inst.getOperand(1)); // lane
6408     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6409     TmpInst.addOperand(Inst.getOperand(5));
6410     Inst = TmpInst;
6411     return true;
6412   }
6413 
6414   // VLD3DUP single 3-element structure to all lanes instructions.
6415   case ARM::VLD3DUPdAsm_8:
6416   case ARM::VLD3DUPdAsm_16:
6417   case ARM::VLD3DUPdAsm_32:
6418   case ARM::VLD3DUPqAsm_8:
6419   case ARM::VLD3DUPqAsm_16:
6420   case ARM::VLD3DUPqAsm_32: {
6421     MCInst TmpInst;
6422     unsigned Spacing;
6423     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6424     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6425     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6426                                             Spacing));
6427     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6428                                             Spacing * 2));
6429     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6430     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6431     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6432     TmpInst.addOperand(Inst.getOperand(4));
6433     Inst = TmpInst;
6434     return true;
6435   }
6436 
6437   case ARM::VLD3DUPdWB_fixed_Asm_8:
6438   case ARM::VLD3DUPdWB_fixed_Asm_16:
6439   case ARM::VLD3DUPdWB_fixed_Asm_32:
6440   case ARM::VLD3DUPqWB_fixed_Asm_8:
6441   case ARM::VLD3DUPqWB_fixed_Asm_16:
6442   case ARM::VLD3DUPqWB_fixed_Asm_32: {
6443     MCInst TmpInst;
6444     unsigned Spacing;
6445     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6446     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6447     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6448                                             Spacing));
6449     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6450                                             Spacing * 2));
6451     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6452     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6453     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6454     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6455     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6456     TmpInst.addOperand(Inst.getOperand(4));
6457     Inst = TmpInst;
6458     return true;
6459   }
6460 
6461   case ARM::VLD3DUPdWB_register_Asm_8:
6462   case ARM::VLD3DUPdWB_register_Asm_16:
6463   case ARM::VLD3DUPdWB_register_Asm_32:
6464   case ARM::VLD3DUPqWB_register_Asm_8:
6465   case ARM::VLD3DUPqWB_register_Asm_16:
6466   case ARM::VLD3DUPqWB_register_Asm_32: {
6467     MCInst TmpInst;
6468     unsigned Spacing;
6469     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6470     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6471     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6472                                             Spacing));
6473     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6474                                             Spacing * 2));
6475     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6476     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6477     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6478     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6479     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6480     TmpInst.addOperand(Inst.getOperand(5));
6481     Inst = TmpInst;
6482     return true;
6483   }
6484 
6485   // VLD3 multiple 3-element structure instructions.
6486   case ARM::VLD3dAsm_8:
6487   case ARM::VLD3dAsm_16:
6488   case ARM::VLD3dAsm_32:
6489   case ARM::VLD3qAsm_8:
6490   case ARM::VLD3qAsm_16:
6491   case ARM::VLD3qAsm_32: {
6492     MCInst TmpInst;
6493     unsigned Spacing;
6494     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6495     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6496     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6497                                             Spacing));
6498     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6499                                             Spacing * 2));
6500     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6501     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6502     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6503     TmpInst.addOperand(Inst.getOperand(4));
6504     Inst = TmpInst;
6505     return true;
6506   }
6507 
6508   case ARM::VLD3dWB_fixed_Asm_8:
6509   case ARM::VLD3dWB_fixed_Asm_16:
6510   case ARM::VLD3dWB_fixed_Asm_32:
6511   case ARM::VLD3qWB_fixed_Asm_8:
6512   case ARM::VLD3qWB_fixed_Asm_16:
6513   case ARM::VLD3qWB_fixed_Asm_32: {
6514     MCInst TmpInst;
6515     unsigned Spacing;
6516     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6517     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6518     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6519                                             Spacing));
6520     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6521                                             Spacing * 2));
6522     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6523     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6524     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6525     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6526     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6527     TmpInst.addOperand(Inst.getOperand(4));
6528     Inst = TmpInst;
6529     return true;
6530   }
6531 
6532   case ARM::VLD3dWB_register_Asm_8:
6533   case ARM::VLD3dWB_register_Asm_16:
6534   case ARM::VLD3dWB_register_Asm_32:
6535   case ARM::VLD3qWB_register_Asm_8:
6536   case ARM::VLD3qWB_register_Asm_16:
6537   case ARM::VLD3qWB_register_Asm_32: {
6538     MCInst TmpInst;
6539     unsigned Spacing;
6540     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6541     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6542     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543                                             Spacing));
6544     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6545                                             Spacing * 2));
6546     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6547     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6548     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6549     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6550     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6551     TmpInst.addOperand(Inst.getOperand(5));
6552     Inst = TmpInst;
6553     return true;
6554   }
6555 
6556   // VLD4DUP single 3-element structure to all lanes instructions.
6557   case ARM::VLD4DUPdAsm_8:
6558   case ARM::VLD4DUPdAsm_16:
6559   case ARM::VLD4DUPdAsm_32:
6560   case ARM::VLD4DUPqAsm_8:
6561   case ARM::VLD4DUPqAsm_16:
6562   case ARM::VLD4DUPqAsm_32: {
6563     MCInst TmpInst;
6564     unsigned Spacing;
6565     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6566     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6567     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6568                                             Spacing));
6569     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6570                                             Spacing * 2));
6571     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572                                             Spacing * 3));
6573     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6574     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6575     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6576     TmpInst.addOperand(Inst.getOperand(4));
6577     Inst = TmpInst;
6578     return true;
6579   }
6580 
6581   case ARM::VLD4DUPdWB_fixed_Asm_8:
6582   case ARM::VLD4DUPdWB_fixed_Asm_16:
6583   case ARM::VLD4DUPdWB_fixed_Asm_32:
6584   case ARM::VLD4DUPqWB_fixed_Asm_8:
6585   case ARM::VLD4DUPqWB_fixed_Asm_16:
6586   case ARM::VLD4DUPqWB_fixed_Asm_32: {
6587     MCInst TmpInst;
6588     unsigned Spacing;
6589     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6590     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6591     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6592                                             Spacing));
6593     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6594                                             Spacing * 2));
6595     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6596                                             Spacing * 3));
6597     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6598     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6599     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6600     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6601     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6602     TmpInst.addOperand(Inst.getOperand(4));
6603     Inst = TmpInst;
6604     return true;
6605   }
6606 
6607   case ARM::VLD4DUPdWB_register_Asm_8:
6608   case ARM::VLD4DUPdWB_register_Asm_16:
6609   case ARM::VLD4DUPdWB_register_Asm_32:
6610   case ARM::VLD4DUPqWB_register_Asm_8:
6611   case ARM::VLD4DUPqWB_register_Asm_16:
6612   case ARM::VLD4DUPqWB_register_Asm_32: {
6613     MCInst TmpInst;
6614     unsigned Spacing;
6615     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6616     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6617     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6618                                             Spacing));
6619     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6620                                             Spacing * 2));
6621     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6622                                             Spacing * 3));
6623     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6624     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6625     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6626     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6627     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6628     TmpInst.addOperand(Inst.getOperand(5));
6629     Inst = TmpInst;
6630     return true;
6631   }
6632 
6633   // VLD4 multiple 4-element structure instructions.
6634   case ARM::VLD4dAsm_8:
6635   case ARM::VLD4dAsm_16:
6636   case ARM::VLD4dAsm_32:
6637   case ARM::VLD4qAsm_8:
6638   case ARM::VLD4qAsm_16:
6639   case ARM::VLD4qAsm_32: {
6640     MCInst TmpInst;
6641     unsigned Spacing;
6642     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6643     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6644     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6645                                             Spacing));
6646     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6647                                             Spacing * 2));
6648     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6649                                             Spacing * 3));
6650     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6651     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6652     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6653     TmpInst.addOperand(Inst.getOperand(4));
6654     Inst = TmpInst;
6655     return true;
6656   }
6657 
6658   case ARM::VLD4dWB_fixed_Asm_8:
6659   case ARM::VLD4dWB_fixed_Asm_16:
6660   case ARM::VLD4dWB_fixed_Asm_32:
6661   case ARM::VLD4qWB_fixed_Asm_8:
6662   case ARM::VLD4qWB_fixed_Asm_16:
6663   case ARM::VLD4qWB_fixed_Asm_32: {
6664     MCInst TmpInst;
6665     unsigned Spacing;
6666     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6667     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6668     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6669                                             Spacing));
6670     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6671                                             Spacing * 2));
6672     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6673                                             Spacing * 3));
6674     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6675     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6676     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6677     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6678     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6679     TmpInst.addOperand(Inst.getOperand(4));
6680     Inst = TmpInst;
6681     return true;
6682   }
6683 
6684   case ARM::VLD4dWB_register_Asm_8:
6685   case ARM::VLD4dWB_register_Asm_16:
6686   case ARM::VLD4dWB_register_Asm_32:
6687   case ARM::VLD4qWB_register_Asm_8:
6688   case ARM::VLD4qWB_register_Asm_16:
6689   case ARM::VLD4qWB_register_Asm_32: {
6690     MCInst TmpInst;
6691     unsigned Spacing;
6692     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6693     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6694     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6695                                             Spacing));
6696     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6697                                             Spacing * 2));
6698     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6699                                             Spacing * 3));
6700     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6701     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6702     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6703     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6704     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6705     TmpInst.addOperand(Inst.getOperand(5));
6706     Inst = TmpInst;
6707     return true;
6708   }
6709 
6710   // VST3 multiple 3-element structure instructions.
6711   case ARM::VST3dAsm_8:
6712   case ARM::VST3dAsm_16:
6713   case ARM::VST3dAsm_32:
6714   case ARM::VST3qAsm_8:
6715   case ARM::VST3qAsm_16:
6716   case ARM::VST3qAsm_32: {
6717     MCInst TmpInst;
6718     unsigned Spacing;
6719     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6720     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6721     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6722     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6723     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6724                                             Spacing));
6725     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6726                                             Spacing * 2));
6727     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6728     TmpInst.addOperand(Inst.getOperand(4));
6729     Inst = TmpInst;
6730     return true;
6731   }
6732 
6733   case ARM::VST3dWB_fixed_Asm_8:
6734   case ARM::VST3dWB_fixed_Asm_16:
6735   case ARM::VST3dWB_fixed_Asm_32:
6736   case ARM::VST3qWB_fixed_Asm_8:
6737   case ARM::VST3qWB_fixed_Asm_16:
6738   case ARM::VST3qWB_fixed_Asm_32: {
6739     MCInst TmpInst;
6740     unsigned Spacing;
6741     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6742     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6743     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6744     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6745     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6746     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6747     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6748                                             Spacing));
6749     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6750                                             Spacing * 2));
6751     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6752     TmpInst.addOperand(Inst.getOperand(4));
6753     Inst = TmpInst;
6754     return true;
6755   }
6756 
6757   case ARM::VST3dWB_register_Asm_8:
6758   case ARM::VST3dWB_register_Asm_16:
6759   case ARM::VST3dWB_register_Asm_32:
6760   case ARM::VST3qWB_register_Asm_8:
6761   case ARM::VST3qWB_register_Asm_16:
6762   case ARM::VST3qWB_register_Asm_32: {
6763     MCInst TmpInst;
6764     unsigned Spacing;
6765     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6766     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6767     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6768     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6769     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6770     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6771     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6772                                             Spacing));
6773     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6774                                             Spacing * 2));
6775     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6776     TmpInst.addOperand(Inst.getOperand(5));
6777     Inst = TmpInst;
6778     return true;
6779   }
6780 
6781   // VST4 multiple 3-element structure instructions.
6782   case ARM::VST4dAsm_8:
6783   case ARM::VST4dAsm_16:
6784   case ARM::VST4dAsm_32:
6785   case ARM::VST4qAsm_8:
6786   case ARM::VST4qAsm_16:
6787   case ARM::VST4qAsm_32: {
6788     MCInst TmpInst;
6789     unsigned Spacing;
6790     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6791     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6792     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6793     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6794     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6795                                             Spacing));
6796     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6797                                             Spacing * 2));
6798     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6799                                             Spacing * 3));
6800     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6801     TmpInst.addOperand(Inst.getOperand(4));
6802     Inst = TmpInst;
6803     return true;
6804   }
6805 
6806   case ARM::VST4dWB_fixed_Asm_8:
6807   case ARM::VST4dWB_fixed_Asm_16:
6808   case ARM::VST4dWB_fixed_Asm_32:
6809   case ARM::VST4qWB_fixed_Asm_8:
6810   case ARM::VST4qWB_fixed_Asm_16:
6811   case ARM::VST4qWB_fixed_Asm_32: {
6812     MCInst TmpInst;
6813     unsigned Spacing;
6814     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6815     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6816     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6817     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6818     TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6819     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6820     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6821                                             Spacing));
6822     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6823                                             Spacing * 2));
6824     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6825                                             Spacing * 3));
6826     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6827     TmpInst.addOperand(Inst.getOperand(4));
6828     Inst = TmpInst;
6829     return true;
6830   }
6831 
6832   case ARM::VST4dWB_register_Asm_8:
6833   case ARM::VST4dWB_register_Asm_16:
6834   case ARM::VST4dWB_register_Asm_32:
6835   case ARM::VST4qWB_register_Asm_8:
6836   case ARM::VST4qWB_register_Asm_16:
6837   case ARM::VST4qWB_register_Asm_32: {
6838     MCInst TmpInst;
6839     unsigned Spacing;
6840     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6841     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6842     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6843     TmpInst.addOperand(Inst.getOperand(2)); // alignment
6844     TmpInst.addOperand(Inst.getOperand(3)); // Rm
6845     TmpInst.addOperand(Inst.getOperand(0)); // Vd
6846     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6847                                             Spacing));
6848     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6849                                             Spacing * 2));
6850     TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6851                                             Spacing * 3));
6852     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6853     TmpInst.addOperand(Inst.getOperand(5));
6854     Inst = TmpInst;
6855     return true;
6856   }
6857 
6858   // Handle encoding choice for the shift-immediate instructions.
6859   case ARM::t2LSLri:
6860   case ARM::t2LSRri:
6861   case ARM::t2ASRri: {
6862     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6863         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6864         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6865         !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6866          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6867       unsigned NewOpc;
6868       switch (Inst.getOpcode()) {
6869       default: llvm_unreachable("unexpected opcode");
6870       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6871       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6872       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6873       }
6874       // The Thumb1 operands aren't in the same order. Awesome, eh?
6875       MCInst TmpInst;
6876       TmpInst.setOpcode(NewOpc);
6877       TmpInst.addOperand(Inst.getOperand(0));
6878       TmpInst.addOperand(Inst.getOperand(5));
6879       TmpInst.addOperand(Inst.getOperand(1));
6880       TmpInst.addOperand(Inst.getOperand(2));
6881       TmpInst.addOperand(Inst.getOperand(3));
6882       TmpInst.addOperand(Inst.getOperand(4));
6883       Inst = TmpInst;
6884       return true;
6885     }
6886     return false;
6887   }
6888 
6889   // Handle the Thumb2 mode MOV complex aliases.
6890   case ARM::t2MOVsr:
6891   case ARM::t2MOVSsr: {
6892     // Which instruction to expand to depends on the CCOut operand and
6893     // whether we're in an IT block if the register operands are low
6894     // registers.
6895     bool isNarrow = false;
6896     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6897         isARMLowRegister(Inst.getOperand(1).getReg()) &&
6898         isARMLowRegister(Inst.getOperand(2).getReg()) &&
6899         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6900         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6901       isNarrow = true;
6902     MCInst TmpInst;
6903     unsigned newOpc;
6904     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6905     default: llvm_unreachable("unexpected opcode!");
6906     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6907     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6908     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6909     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6910     }
6911     TmpInst.setOpcode(newOpc);
6912     TmpInst.addOperand(Inst.getOperand(0)); // Rd
6913     if (isNarrow)
6914       TmpInst.addOperand(MCOperand::CreateReg(
6915           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6916     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6917     TmpInst.addOperand(Inst.getOperand(2)); // Rm
6918     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6919     TmpInst.addOperand(Inst.getOperand(5));
6920     if (!isNarrow)
6921       TmpInst.addOperand(MCOperand::CreateReg(
6922           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6923     Inst = TmpInst;
6924     return true;
6925   }
6926   case ARM::t2MOVsi:
6927   case ARM::t2MOVSsi: {
6928     // Which instruction to expand to depends on the CCOut operand and
6929     // whether we're in an IT block if the register operands are low
6930     // registers.
6931     bool isNarrow = false;
6932     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6933         isARMLowRegister(Inst.getOperand(1).getReg()) &&
6934         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6935       isNarrow = true;
6936     MCInst TmpInst;
6937     unsigned newOpc;
6938     switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6939     default: llvm_unreachable("unexpected opcode!");
6940     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6941     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6942     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6943     case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6944     case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6945     }
6946     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6947     if (Amount == 32) Amount = 0;
6948     TmpInst.setOpcode(newOpc);
6949     TmpInst.addOperand(Inst.getOperand(0)); // Rd
6950     if (isNarrow)
6951       TmpInst.addOperand(MCOperand::CreateReg(
6952           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6953     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6954     if (newOpc != ARM::t2RRX)
6955       TmpInst.addOperand(MCOperand::CreateImm(Amount));
6956     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6957     TmpInst.addOperand(Inst.getOperand(4));
6958     if (!isNarrow)
6959       TmpInst.addOperand(MCOperand::CreateReg(
6960           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6961     Inst = TmpInst;
6962     return true;
6963   }
6964   // Handle the ARM mode MOV complex aliases.
6965   case ARM::ASRr:
6966   case ARM::LSRr:
6967   case ARM::LSLr:
6968   case ARM::RORr: {
6969     ARM_AM::ShiftOpc ShiftTy;
6970     switch(Inst.getOpcode()) {
6971     default: llvm_unreachable("unexpected opcode!");
6972     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6973     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6974     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6975     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6976     }
6977     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6978     MCInst TmpInst;
6979     TmpInst.setOpcode(ARM::MOVsr);
6980     TmpInst.addOperand(Inst.getOperand(0)); // Rd
6981     TmpInst.addOperand(Inst.getOperand(1)); // Rn
6982     TmpInst.addOperand(Inst.getOperand(2)); // Rm
6983     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6984     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6985     TmpInst.addOperand(Inst.getOperand(4));
6986     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6987     Inst = TmpInst;
6988     return true;
6989   }
6990   case ARM::ASRi:
6991   case ARM::LSRi:
6992   case ARM::LSLi:
6993   case ARM::RORi: {
6994     ARM_AM::ShiftOpc ShiftTy;
6995     switch(Inst.getOpcode()) {
6996     default: llvm_unreachable("unexpected opcode!");
6997     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6998     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6999     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7000     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7001     }
7002     // A shift by zero is a plain MOVr, not a MOVsi.
7003     unsigned Amt = Inst.getOperand(2).getImm();
7004     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7005     // A shift by 32 should be encoded as 0 when permitted
7006     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7007       Amt = 0;
7008     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7009     MCInst TmpInst;
7010     TmpInst.setOpcode(Opc);
7011     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7012     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7013     if (Opc == ARM::MOVsi)
7014       TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7015     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7016     TmpInst.addOperand(Inst.getOperand(4));
7017     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7018     Inst = TmpInst;
7019     return true;
7020   }
7021   case ARM::RRXi: {
7022     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7023     MCInst TmpInst;
7024     TmpInst.setOpcode(ARM::MOVsi);
7025     TmpInst.addOperand(Inst.getOperand(0)); // Rd
7026     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7027     TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7028     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7029     TmpInst.addOperand(Inst.getOperand(3));
7030     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7031     Inst = TmpInst;
7032     return true;
7033   }
7034   case ARM::t2LDMIA_UPD: {
7035     // If this is a load of a single register, then we should use
7036     // a post-indexed LDR instruction instead, per the ARM ARM.
7037     if (Inst.getNumOperands() != 5)
7038       return false;
7039     MCInst TmpInst;
7040     TmpInst.setOpcode(ARM::t2LDR_POST);
7041     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7042     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7043     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7044     TmpInst.addOperand(MCOperand::CreateImm(4));
7045     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7046     TmpInst.addOperand(Inst.getOperand(3));
7047     Inst = TmpInst;
7048     return true;
7049   }
7050   case ARM::t2STMDB_UPD: {
7051     // If this is a store of a single register, then we should use
7052     // a pre-indexed STR instruction instead, per the ARM ARM.
7053     if (Inst.getNumOperands() != 5)
7054       return false;
7055     MCInst TmpInst;
7056     TmpInst.setOpcode(ARM::t2STR_PRE);
7057     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7058     TmpInst.addOperand(Inst.getOperand(4)); // Rt
7059     TmpInst.addOperand(Inst.getOperand(1)); // Rn
7060     TmpInst.addOperand(MCOperand::CreateImm(-4));
7061     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7062     TmpInst.addOperand(Inst.getOperand(3));
7063     Inst = TmpInst;
7064     return true;
7065   }
7066   case ARM::LDMIA_UPD:
7067     // If this is a load of a single register via a 'pop', then we should use
7068     // a post-indexed LDR instruction instead, per the ARM ARM.
7069     if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7070         Inst.getNumOperands() == 5) {
7071       MCInst TmpInst;
7072       TmpInst.setOpcode(ARM::LDR_POST_IMM);
7073       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7074       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7075       TmpInst.addOperand(Inst.getOperand(1)); // Rn
7076       TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
7077       TmpInst.addOperand(MCOperand::CreateImm(4));
7078       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7079       TmpInst.addOperand(Inst.getOperand(3));
7080       Inst = TmpInst;
7081       return true;
7082     }
7083     break;
7084   case ARM::STMDB_UPD:
7085     // If this is a store of a single register via a 'push', then we should use
7086     // a pre-indexed STR instruction instead, per the ARM ARM.
7087     if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7088         Inst.getNumOperands() == 5) {
7089       MCInst TmpInst;
7090       TmpInst.setOpcode(ARM::STR_PRE_IMM);
7091       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7092       TmpInst.addOperand(Inst.getOperand(4)); // Rt
7093       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7094       TmpInst.addOperand(MCOperand::CreateImm(-4));
7095       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7096       TmpInst.addOperand(Inst.getOperand(3));
7097       Inst = TmpInst;
7098     }
7099     break;
7100   case ARM::t2ADDri12:
7101     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7102     // mnemonic was used (not "addw"), encoding T3 is preferred.
7103     if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7104         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7105       break;
7106     Inst.setOpcode(ARM::t2ADDri);
7107     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7108     break;
7109   case ARM::t2SUBri12:
7110     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7111     // mnemonic was used (not "subw"), encoding T3 is preferred.
7112     if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7113         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7114       break;
7115     Inst.setOpcode(ARM::t2SUBri);
7116     Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7117     break;
7118   case ARM::tADDi8:
7119     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7120     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7121     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7122     // to encoding T1 if <Rd> is omitted."
7123     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7124       Inst.setOpcode(ARM::tADDi3);
7125       return true;
7126     }
7127     break;
7128   case ARM::tSUBi8:
7129     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7130     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7131     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7132     // to encoding T1 if <Rd> is omitted."
7133     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7134       Inst.setOpcode(ARM::tSUBi3);
7135       return true;
7136     }
7137     break;
7138   case ARM::t2ADDri:
7139   case ARM::t2SUBri: {
7140     // If the destination and first source operand are the same, and
7141     // the flags are compatible with the current IT status, use encoding T2
7142     // instead of T3. For compatibility with the system 'as'. Make sure the
7143     // wide encoding wasn't explicit.
7144     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7145         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7146         (unsigned)Inst.getOperand(2).getImm() > 255 ||
7147         ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7148         (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7149         (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7150          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7151       break;
7152     MCInst TmpInst;
7153     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7154                       ARM::tADDi8 : ARM::tSUBi8);
7155     TmpInst.addOperand(Inst.getOperand(0));
7156     TmpInst.addOperand(Inst.getOperand(5));
7157     TmpInst.addOperand(Inst.getOperand(0));
7158     TmpInst.addOperand(Inst.getOperand(2));
7159     TmpInst.addOperand(Inst.getOperand(3));
7160     TmpInst.addOperand(Inst.getOperand(4));
7161     Inst = TmpInst;
7162     return true;
7163   }
7164   case ARM::t2ADDrr: {
7165     // If the destination and first source operand are the same, and
7166     // there's no setting of the flags, use encoding T2 instead of T3.
7167     // Note that this is only for ADD, not SUB. This mirrors the system
7168     // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7169     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7170         Inst.getOperand(5).getReg() != 0 ||
7171         (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7172          static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7173       break;
7174     MCInst TmpInst;
7175     TmpInst.setOpcode(ARM::tADDhirr);
7176     TmpInst.addOperand(Inst.getOperand(0));
7177     TmpInst.addOperand(Inst.getOperand(0));
7178     TmpInst.addOperand(Inst.getOperand(2));
7179     TmpInst.addOperand(Inst.getOperand(3));
7180     TmpInst.addOperand(Inst.getOperand(4));
7181     Inst = TmpInst;
7182     return true;
7183   }
7184   case ARM::tADDrSP: {
7185     // If the non-SP source operand and the destination operand are not the
7186     // same, we need to use the 32-bit encoding if it's available.
7187     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7188       Inst.setOpcode(ARM::t2ADDrr);
7189       Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7190       return true;
7191     }
7192     break;
7193   }
7194   case ARM::tB:
7195     // A Thumb conditional branch outside of an IT block is a tBcc.
7196     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7197       Inst.setOpcode(ARM::tBcc);
7198       return true;
7199     }
7200     break;
7201   case ARM::t2B:
7202     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7203     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7204       Inst.setOpcode(ARM::t2Bcc);
7205       return true;
7206     }
7207     break;
7208   case ARM::t2Bcc:
7209     // If the conditional is AL or we're in an IT block, we really want t2B.
7210     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7211       Inst.setOpcode(ARM::t2B);
7212       return true;
7213     }
7214     break;
7215   case ARM::tBcc:
7216     // If the conditional is AL, we really want tB.
7217     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7218       Inst.setOpcode(ARM::tB);
7219       return true;
7220     }
7221     break;
7222   case ARM::tLDMIA: {
7223     // If the register list contains any high registers, or if the writeback
7224     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7225     // instead if we're in Thumb2. Otherwise, this should have generated
7226     // an error in validateInstruction().
7227     unsigned Rn = Inst.getOperand(0).getReg();
7228     bool hasWritebackToken =
7229       (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7230        static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7231     bool listContainsBase;
7232     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7233         (!listContainsBase && !hasWritebackToken) ||
7234         (listContainsBase && hasWritebackToken)) {
7235       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7236       assert (isThumbTwo());
7237       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7238       // If we're switching to the updating version, we need to insert
7239       // the writeback tied operand.
7240       if (hasWritebackToken)
7241         Inst.insert(Inst.begin(),
7242                     MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7243       return true;
7244     }
7245     break;
7246   }
7247   case ARM::tSTMIA_UPD: {
7248     // If the register list contains any high registers, we need to use
7249     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7250     // should have generated an error in validateInstruction().
7251     unsigned Rn = Inst.getOperand(0).getReg();
7252     bool listContainsBase;
7253     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7254       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7255       assert (isThumbTwo());
7256       Inst.setOpcode(ARM::t2STMIA_UPD);
7257       return true;
7258     }
7259     break;
7260   }
7261   case ARM::tPOP: {
7262     bool listContainsBase;
7263     // If the register list contains any high registers, we need to use
7264     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7265     // should have generated an error in validateInstruction().
7266     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7267       return false;
7268     assert (isThumbTwo());
7269     Inst.setOpcode(ARM::t2LDMIA_UPD);
7270     // Add the base register and writeback operands.
7271     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7272     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7273     return true;
7274   }
7275   case ARM::tPUSH: {
7276     bool listContainsBase;
7277     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7278       return false;
7279     assert (isThumbTwo());
7280     Inst.setOpcode(ARM::t2STMDB_UPD);
7281     // Add the base register and writeback operands.
7282     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7283     Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7284     return true;
7285   }
7286   case ARM::t2MOVi: {
7287     // If we can use the 16-bit encoding and the user didn't explicitly
7288     // request the 32-bit variant, transform it here.
7289     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7290         (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7291         ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7292          Inst.getOperand(4).getReg() == ARM::CPSR) ||
7293         (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7294         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7295          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7296       // The operands aren't in the same order for tMOVi8...
7297       MCInst TmpInst;
7298       TmpInst.setOpcode(ARM::tMOVi8);
7299       TmpInst.addOperand(Inst.getOperand(0));
7300       TmpInst.addOperand(Inst.getOperand(4));
7301       TmpInst.addOperand(Inst.getOperand(1));
7302       TmpInst.addOperand(Inst.getOperand(2));
7303       TmpInst.addOperand(Inst.getOperand(3));
7304       Inst = TmpInst;
7305       return true;
7306     }
7307     break;
7308   }
7309   case ARM::t2MOVr: {
7310     // If we can use the 16-bit encoding and the user didn't explicitly
7311     // request the 32-bit variant, transform it here.
7312     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7313         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7314         Inst.getOperand(2).getImm() == ARMCC::AL &&
7315         Inst.getOperand(4).getReg() == ARM::CPSR &&
7316         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7317          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7318       // The operands aren't the same for tMOV[S]r... (no cc_out)
7319       MCInst TmpInst;
7320       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7321       TmpInst.addOperand(Inst.getOperand(0));
7322       TmpInst.addOperand(Inst.getOperand(1));
7323       TmpInst.addOperand(Inst.getOperand(2));
7324       TmpInst.addOperand(Inst.getOperand(3));
7325       Inst = TmpInst;
7326       return true;
7327     }
7328     break;
7329   }
7330   case ARM::t2SXTH:
7331   case ARM::t2SXTB:
7332   case ARM::t2UXTH:
7333   case ARM::t2UXTB: {
7334     // If we can use the 16-bit encoding and the user didn't explicitly
7335     // request the 32-bit variant, transform it here.
7336     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7337         isARMLowRegister(Inst.getOperand(1).getReg()) &&
7338         Inst.getOperand(2).getImm() == 0 &&
7339         (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7340          static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7341       unsigned NewOpc;
7342       switch (Inst.getOpcode()) {
7343       default: llvm_unreachable("Illegal opcode!");
7344       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7345       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7346       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7347       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7348       }
7349       // The operands aren't the same for thumb1 (no rotate operand).
7350       MCInst TmpInst;
7351       TmpInst.setOpcode(NewOpc);
7352       TmpInst.addOperand(Inst.getOperand(0));
7353       TmpInst.addOperand(Inst.getOperand(1));
7354       TmpInst.addOperand(Inst.getOperand(3));
7355       TmpInst.addOperand(Inst.getOperand(4));
7356       Inst = TmpInst;
7357       return true;
7358     }
7359     break;
7360   }
7361   case ARM::MOVsi: {
7362     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7363     // rrx shifts and asr/lsr of #32 is encoded as 0
7364     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7365       return false;
7366     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7367       // Shifting by zero is accepted as a vanilla 'MOVr'
7368       MCInst TmpInst;
7369       TmpInst.setOpcode(ARM::MOVr);
7370       TmpInst.addOperand(Inst.getOperand(0));
7371       TmpInst.addOperand(Inst.getOperand(1));
7372       TmpInst.addOperand(Inst.getOperand(3));
7373       TmpInst.addOperand(Inst.getOperand(4));
7374       TmpInst.addOperand(Inst.getOperand(5));
7375       Inst = TmpInst;
7376       return true;
7377     }
7378     return false;
7379   }
7380   case ARM::ANDrsi:
7381   case ARM::ORRrsi:
7382   case ARM::EORrsi:
7383   case ARM::BICrsi:
7384   case ARM::SUBrsi:
7385   case ARM::ADDrsi: {
7386     unsigned newOpc;
7387     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7388     if (SOpc == ARM_AM::rrx) return false;
7389     switch (Inst.getOpcode()) {
7390     default: llvm_unreachable("unexpected opcode!");
7391     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7392     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7393     case ARM::EORrsi: newOpc = ARM::EORrr; break;
7394     case ARM::BICrsi: newOpc = ARM::BICrr; break;
7395     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7396     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7397     }
7398     // If the shift is by zero, use the non-shifted instruction definition.
7399     // The exception is for right shifts, where 0 == 32
7400     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7401         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7402       MCInst TmpInst;
7403       TmpInst.setOpcode(newOpc);
7404       TmpInst.addOperand(Inst.getOperand(0));
7405       TmpInst.addOperand(Inst.getOperand(1));
7406       TmpInst.addOperand(Inst.getOperand(2));
7407       TmpInst.addOperand(Inst.getOperand(4));
7408       TmpInst.addOperand(Inst.getOperand(5));
7409       TmpInst.addOperand(Inst.getOperand(6));
7410       Inst = TmpInst;
7411       return true;
7412     }
7413     return false;
7414   }
7415   case ARM::ITasm:
7416   case ARM::t2IT: {
7417     // The mask bits for all but the first condition are represented as
7418     // the low bit of the condition code value implies 't'. We currently
7419     // always have 1 implies 't', so XOR toggle the bits if the low bit
7420     // of the condition code is zero.
7421     MCOperand &MO = Inst.getOperand(1);
7422     unsigned Mask = MO.getImm();
7423     unsigned OrigMask = Mask;
7424     unsigned TZ = countTrailingZeros(Mask);
7425     if ((Inst.getOperand(0).getImm() & 1) == 0) {
7426       assert(Mask && TZ <= 3 && "illegal IT mask value!");
7427       Mask ^= (0xE << TZ) & 0xF;
7428     }
7429     MO.setImm(Mask);
7430 
7431     // Set up the IT block state according to the IT instruction we just
7432     // matched.
7433     assert(!inITBlock() && "nested IT blocks?!");
7434     ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7435     ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7436     ITState.CurPosition = 0;
7437     ITState.FirstCond = true;
7438     break;
7439   }
7440   case ARM::t2LSLrr:
7441   case ARM::t2LSRrr:
7442   case ARM::t2ASRrr:
7443   case ARM::t2SBCrr:
7444   case ARM::t2RORrr:
7445   case ARM::t2BICrr:
7446   {
7447     // Assemblers should use the narrow encodings of these instructions when permissible.
7448     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7449          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7450         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7451         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7452          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7453         (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7454          !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7455       unsigned NewOpc;
7456       switch (Inst.getOpcode()) {
7457         default: llvm_unreachable("unexpected opcode");
7458         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7459         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7460         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7461         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7462         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7463         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7464       }
7465       MCInst TmpInst;
7466       TmpInst.setOpcode(NewOpc);
7467       TmpInst.addOperand(Inst.getOperand(0));
7468       TmpInst.addOperand(Inst.getOperand(5));
7469       TmpInst.addOperand(Inst.getOperand(1));
7470       TmpInst.addOperand(Inst.getOperand(2));
7471       TmpInst.addOperand(Inst.getOperand(3));
7472       TmpInst.addOperand(Inst.getOperand(4));
7473       Inst = TmpInst;
7474       return true;
7475     }
7476     return false;
7477   }
7478   case ARM::t2ANDrr:
7479   case ARM::t2EORrr:
7480   case ARM::t2ADCrr:
7481   case ARM::t2ORRrr:
7482   {
7483     // Assemblers should use the narrow encodings of these instructions when permissible.
7484     // These instructions are special in that they are commutable, so shorter encodings
7485     // are available more often.
7486     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7487          isARMLowRegister(Inst.getOperand(2).getReg())) &&
7488         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7489          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7490         ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7491          (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7492         (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7493          !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7494       unsigned NewOpc;
7495       switch (Inst.getOpcode()) {
7496         default: llvm_unreachable("unexpected opcode");
7497         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7498         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7499         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7500         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7501       }
7502       MCInst TmpInst;
7503       TmpInst.setOpcode(NewOpc);
7504       TmpInst.addOperand(Inst.getOperand(0));
7505       TmpInst.addOperand(Inst.getOperand(5));
7506       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7507         TmpInst.addOperand(Inst.getOperand(1));
7508         TmpInst.addOperand(Inst.getOperand(2));
7509       } else {
7510         TmpInst.addOperand(Inst.getOperand(2));
7511         TmpInst.addOperand(Inst.getOperand(1));
7512       }
7513       TmpInst.addOperand(Inst.getOperand(3));
7514       TmpInst.addOperand(Inst.getOperand(4));
7515       Inst = TmpInst;
7516       return true;
7517     }
7518     return false;
7519   }
7520   }
7521   return false;
7522 }
7523 
7524 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7525   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7526   // suffix depending on whether they're in an IT block or not.
7527   unsigned Opc = Inst.getOpcode();
7528   const MCInstrDesc &MCID = getInstDesc(Opc);
7529   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7530     assert(MCID.hasOptionalDef() &&
7531            "optionally flag setting instruction missing optional def operand");
7532     assert(MCID.NumOperands == Inst.getNumOperands() &&
7533            "operand count mismatch!");
7534     // Find the optional-def operand (cc_out).
7535     unsigned OpNo;
7536     for (OpNo = 0;
7537          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7538          ++OpNo)
7539       ;
7540     // If we're parsing Thumb1, reject it completely.
7541     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7542       return Match_MnemonicFail;
7543     // If we're parsing Thumb2, which form is legal depends on whether we're
7544     // in an IT block.
7545     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7546         !inITBlock())
7547       return Match_RequiresITBlock;
7548     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7549         inITBlock())
7550       return Match_RequiresNotITBlock;
7551   }
7552   // Some high-register supporting Thumb1 encodings only allow both registers
7553   // to be from r0-r7 when in Thumb2.
7554   else if (Opc == ARM::tADDhirr && isThumbOne() &&
7555            isARMLowRegister(Inst.getOperand(1).getReg()) &&
7556            isARMLowRegister(Inst.getOperand(2).getReg()))
7557     return Match_RequiresThumb2;
7558   // Others only require ARMv6 or later.
7559   else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7560            isARMLowRegister(Inst.getOperand(0).getReg()) &&
7561            isARMLowRegister(Inst.getOperand(1).getReg()))
7562     return Match_RequiresV6;
7563   return Match_Success;
7564 }
7565 
7566 static const char *getSubtargetFeatureName(unsigned Val);
7567 bool ARMAsmParser::
7568 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7569                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7570                         MCStreamer &Out, unsigned &ErrorInfo,
7571                         bool MatchingInlineAsm) {
7572   MCInst Inst;
7573   unsigned MatchResult;
7574 
7575   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7576                                      MatchingInlineAsm);
7577   switch (MatchResult) {
7578   default: break;
7579   case Match_Success:
7580     // Context sensitive operand constraints aren't handled by the matcher,
7581     // so check them here.
7582     if (validateInstruction(Inst, Operands)) {
7583       // Still progress the IT block, otherwise one wrong condition causes
7584       // nasty cascading errors.
7585       forwardITPosition();
7586       return true;
7587     }
7588 
7589     // Some instructions need post-processing to, for example, tweak which
7590     // encoding is selected. Loop on it while changes happen so the
7591     // individual transformations can chain off each other. E.g.,
7592     // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7593     while (processInstruction(Inst, Operands))
7594       ;
7595 
7596     // Only move forward at the very end so that everything in validate
7597     // and process gets a consistent answer about whether we're in an IT
7598     // block.
7599     forwardITPosition();
7600 
7601     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7602     // doesn't actually encode.
7603     if (Inst.getOpcode() == ARM::ITasm)
7604       return false;
7605 
7606     Inst.setLoc(IDLoc);
7607     Out.EmitInstruction(Inst);
7608     return false;
7609   case Match_MissingFeature: {
7610     assert(ErrorInfo && "Unknown missing feature!");
7611     // Special case the error message for the very common case where only
7612     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7613     std::string Msg = "instruction requires:";
7614     unsigned Mask = 1;
7615     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7616       if (ErrorInfo & Mask) {
7617         Msg += " ";
7618         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7619       }
7620       Mask <<= 1;
7621     }
7622     return Error(IDLoc, Msg);
7623   }
7624   case Match_InvalidOperand: {
7625     SMLoc ErrorLoc = IDLoc;
7626     if (ErrorInfo != ~0U) {
7627       if (ErrorInfo >= Operands.size())
7628         return Error(IDLoc, "too few operands for instruction");
7629 
7630       ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7631       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7632     }
7633 
7634     return Error(ErrorLoc, "invalid operand for instruction");
7635   }
7636   case Match_MnemonicFail:
7637     return Error(IDLoc, "invalid instruction",
7638                  ((ARMOperand*)Operands[0])->getLocRange());
7639   case Match_RequiresNotITBlock:
7640     return Error(IDLoc, "flag setting instruction only valid outside IT block");
7641   case Match_RequiresITBlock:
7642     return Error(IDLoc, "instruction only valid inside IT block");
7643   case Match_RequiresV6:
7644     return Error(IDLoc, "instruction variant requires ARMv6 or later");
7645   case Match_RequiresThumb2:
7646     return Error(IDLoc, "instruction variant requires Thumb2");
7647   case Match_ImmRange0_4: {
7648     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7649     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7650     return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7651   }
7652   case Match_ImmRange0_15: {
7653     SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7654     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7655     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7656   }
7657   }
7658 
7659   llvm_unreachable("Implement any new match types added!");
7660 }
7661 
7662 /// parseDirective parses the arm specific directives
7663 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7664   StringRef IDVal = DirectiveID.getIdentifier();
7665   if (IDVal == ".word")
7666     return parseDirectiveWord(4, DirectiveID.getLoc());
7667   else if (IDVal == ".thumb")
7668     return parseDirectiveThumb(DirectiveID.getLoc());
7669   else if (IDVal == ".arm")
7670     return parseDirectiveARM(DirectiveID.getLoc());
7671   else if (IDVal == ".thumb_func")
7672     return parseDirectiveThumbFunc(DirectiveID.getLoc());
7673   else if (IDVal == ".code")
7674     return parseDirectiveCode(DirectiveID.getLoc());
7675   else if (IDVal == ".syntax")
7676     return parseDirectiveSyntax(DirectiveID.getLoc());
7677   else if (IDVal == ".unreq")
7678     return parseDirectiveUnreq(DirectiveID.getLoc());
7679   else if (IDVal == ".arch")
7680     return parseDirectiveArch(DirectiveID.getLoc());
7681   else if (IDVal == ".eabi_attribute")
7682     return parseDirectiveEabiAttr(DirectiveID.getLoc());
7683   else if (IDVal == ".fnstart")
7684     return parseDirectiveFnStart(DirectiveID.getLoc());
7685   else if (IDVal == ".fnend")
7686     return parseDirectiveFnEnd(DirectiveID.getLoc());
7687   else if (IDVal == ".cantunwind")
7688     return parseDirectiveCantUnwind(DirectiveID.getLoc());
7689   else if (IDVal == ".personality")
7690     return parseDirectivePersonality(DirectiveID.getLoc());
7691   else if (IDVal == ".handlerdata")
7692     return parseDirectiveHandlerData(DirectiveID.getLoc());
7693   else if (IDVal == ".setfp")
7694     return parseDirectiveSetFP(DirectiveID.getLoc());
7695   else if (IDVal == ".pad")
7696     return parseDirectivePad(DirectiveID.getLoc());
7697   else if (IDVal == ".save")
7698     return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7699   else if (IDVal == ".vsave")
7700     return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7701   return true;
7702 }
7703 
7704 /// parseDirectiveWord
7705 ///  ::= .word [ expression (, expression)* ]
7706 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7707   if (getLexer().isNot(AsmToken::EndOfStatement)) {
7708     for (;;) {
7709       const MCExpr *Value;
7710       if (getParser().parseExpression(Value))
7711         return true;
7712 
7713       getParser().getStreamer().EmitValue(Value, Size);
7714 
7715       if (getLexer().is(AsmToken::EndOfStatement))
7716         break;
7717 
7718       // FIXME: Improve diagnostic.
7719       if (getLexer().isNot(AsmToken::Comma))
7720         return Error(L, "unexpected token in directive");
7721       Parser.Lex();
7722     }
7723   }
7724 
7725   Parser.Lex();
7726   return false;
7727 }
7728 
7729 /// parseDirectiveThumb
7730 ///  ::= .thumb
7731 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7732   if (getLexer().isNot(AsmToken::EndOfStatement))
7733     return Error(L, "unexpected token in directive");
7734   Parser.Lex();
7735 
7736   if (!hasThumb())
7737     return Error(L, "target does not support Thumb mode");
7738 
7739   if (!isThumb())
7740     SwitchMode();
7741   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7742   return false;
7743 }
7744 
7745 /// parseDirectiveARM
7746 ///  ::= .arm
7747 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7748   if (getLexer().isNot(AsmToken::EndOfStatement))
7749     return Error(L, "unexpected token in directive");
7750   Parser.Lex();
7751 
7752   if (!hasARM())
7753     return Error(L, "target does not support ARM mode");
7754 
7755   if (isThumb())
7756     SwitchMode();
7757   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7758   return false;
7759 }
7760 
7761 /// parseDirectiveThumbFunc
7762 ///  ::= .thumbfunc symbol_name
7763 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7764   const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7765   bool isMachO = MAI->hasSubsectionsViaSymbols();
7766   StringRef Name;
7767   bool needFuncName = true;
7768 
7769   // Darwin asm has (optionally) function name after .thumb_func direction
7770   // ELF doesn't
7771   if (isMachO) {
7772     const AsmToken &Tok = Parser.getTok();
7773     if (Tok.isNot(AsmToken::EndOfStatement)) {
7774       if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7775         return Error(L, "unexpected token in .thumb_func directive");
7776       Name = Tok.getIdentifier();
7777       Parser.Lex(); // Consume the identifier token.
7778       needFuncName = false;
7779     }
7780   }
7781 
7782   if (getLexer().isNot(AsmToken::EndOfStatement))
7783     return Error(L, "unexpected token in directive");
7784 
7785   // Eat the end of statement and any blank lines that follow.
7786   while (getLexer().is(AsmToken::EndOfStatement))
7787     Parser.Lex();
7788 
7789   // FIXME: assuming function name will be the line following .thumb_func
7790   // We really should be checking the next symbol definition even if there's
7791   // stuff in between.
7792   if (needFuncName) {
7793     Name = Parser.getTok().getIdentifier();
7794   }
7795 
7796   // Mark symbol as a thumb symbol.
7797   MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7798   getParser().getStreamer().EmitThumbFunc(Func);
7799   return false;
7800 }
7801 
7802 /// parseDirectiveSyntax
7803 ///  ::= .syntax unified | divided
7804 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7805   const AsmToken &Tok = Parser.getTok();
7806   if (Tok.isNot(AsmToken::Identifier))
7807     return Error(L, "unexpected token in .syntax directive");
7808   StringRef Mode = Tok.getString();
7809   if (Mode == "unified" || Mode == "UNIFIED")
7810     Parser.Lex();
7811   else if (Mode == "divided" || Mode == "DIVIDED")
7812     return Error(L, "'.syntax divided' arm asssembly not supported");
7813   else
7814     return Error(L, "unrecognized syntax mode in .syntax directive");
7815 
7816   if (getLexer().isNot(AsmToken::EndOfStatement))
7817     return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7818   Parser.Lex();
7819 
7820   // TODO tell the MC streamer the mode
7821   // getParser().getStreamer().Emit???();
7822   return false;
7823 }
7824 
7825 /// parseDirectiveCode
7826 ///  ::= .code 16 | 32
7827 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7828   const AsmToken &Tok = Parser.getTok();
7829   if (Tok.isNot(AsmToken::Integer))
7830     return Error(L, "unexpected token in .code directive");
7831   int64_t Val = Parser.getTok().getIntVal();
7832   if (Val == 16)
7833     Parser.Lex();
7834   else if (Val == 32)
7835     Parser.Lex();
7836   else
7837     return Error(L, "invalid operand to .code directive");
7838 
7839   if (getLexer().isNot(AsmToken::EndOfStatement))
7840     return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7841   Parser.Lex();
7842 
7843   if (Val == 16) {
7844     if (!hasThumb())
7845       return Error(L, "target does not support Thumb mode");
7846 
7847     if (!isThumb())
7848       SwitchMode();
7849     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7850   } else {
7851     if (!hasARM())
7852       return Error(L, "target does not support ARM mode");
7853 
7854     if (isThumb())
7855       SwitchMode();
7856     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7857   }
7858 
7859   return false;
7860 }
7861 
7862 /// parseDirectiveReq
7863 ///  ::= name .req registername
7864 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7865   Parser.Lex(); // Eat the '.req' token.
7866   unsigned Reg;
7867   SMLoc SRegLoc, ERegLoc;
7868   if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7869     Parser.eatToEndOfStatement();
7870     return Error(SRegLoc, "register name expected");
7871   }
7872 
7873   // Shouldn't be anything else.
7874   if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7875     Parser.eatToEndOfStatement();
7876     return Error(Parser.getTok().getLoc(),
7877                  "unexpected input in .req directive.");
7878   }
7879 
7880   Parser.Lex(); // Consume the EndOfStatement
7881 
7882   if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7883     return Error(SRegLoc, "redefinition of '" + Name +
7884                           "' does not match original.");
7885 
7886   return false;
7887 }
7888 
7889 /// parseDirectiveUneq
7890 ///  ::= .unreq registername
7891 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7892   if (Parser.getTok().isNot(AsmToken::Identifier)) {
7893     Parser.eatToEndOfStatement();
7894     return Error(L, "unexpected input in .unreq directive.");
7895   }
7896   RegisterReqs.erase(Parser.getTok().getIdentifier());
7897   Parser.Lex(); // Eat the identifier.
7898   return false;
7899 }
7900 
7901 /// parseDirectiveArch
7902 ///  ::= .arch token
7903 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7904   return true;
7905 }
7906 
7907 /// parseDirectiveEabiAttr
7908 ///  ::= .eabi_attribute int, int
7909 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7910   return true;
7911 }
7912 
7913 /// parseDirectiveFnStart
7914 ///  ::= .fnstart
7915 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
7916   if (FnStartLoc.isValid()) {
7917     Error(L, ".fnstart starts before the end of previous one");
7918     Error(FnStartLoc, "previous .fnstart starts here");
7919     return true;
7920   }
7921 
7922   FnStartLoc = L;
7923   getParser().getStreamer().EmitFnStart();
7924   return false;
7925 }
7926 
7927 /// parseDirectiveFnEnd
7928 ///  ::= .fnend
7929 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
7930   // Check the ordering of unwind directives
7931   if (!FnStartLoc.isValid())
7932     return Error(L, ".fnstart must precede .fnend directive");
7933 
7934   // Reset the unwind directives parser state
7935   resetUnwindDirectiveParserState();
7936 
7937   getParser().getStreamer().EmitFnEnd();
7938   return false;
7939 }
7940 
7941 /// parseDirectiveCantUnwind
7942 ///  ::= .cantunwind
7943 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
7944   // Check the ordering of unwind directives
7945   CantUnwindLoc = L;
7946   if (!FnStartLoc.isValid())
7947     return Error(L, ".fnstart must precede .cantunwind directive");
7948   if (HandlerDataLoc.isValid()) {
7949     Error(L, ".cantunwind can't be used with .handlerdata directive");
7950     Error(HandlerDataLoc, ".handlerdata was specified here");
7951     return true;
7952   }
7953   if (PersonalityLoc.isValid()) {
7954     Error(L, ".cantunwind can't be used with .personality directive");
7955     Error(PersonalityLoc, ".personality was specified here");
7956     return true;
7957   }
7958 
7959   getParser().getStreamer().EmitCantUnwind();
7960   return false;
7961 }
7962 
7963 /// parseDirectivePersonality
7964 ///  ::= .personality name
7965 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
7966   // Check the ordering of unwind directives
7967   PersonalityLoc = L;
7968   if (!FnStartLoc.isValid())
7969     return Error(L, ".fnstart must precede .personality directive");
7970   if (CantUnwindLoc.isValid()) {
7971     Error(L, ".personality can't be used with .cantunwind directive");
7972     Error(CantUnwindLoc, ".cantunwind was specified here");
7973     return true;
7974   }
7975   if (HandlerDataLoc.isValid()) {
7976     Error(L, ".personality must precede .handlerdata directive");
7977     Error(HandlerDataLoc, ".handlerdata was specified here");
7978     return true;
7979   }
7980 
7981   // Parse the name of the personality routine
7982   if (Parser.getTok().isNot(AsmToken::Identifier)) {
7983     Parser.eatToEndOfStatement();
7984     return Error(L, "unexpected input in .personality directive.");
7985   }
7986   StringRef Name(Parser.getTok().getIdentifier());
7987   Parser.Lex();
7988 
7989   MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
7990   getParser().getStreamer().EmitPersonality(PR);
7991   return false;
7992 }
7993 
7994 /// parseDirectiveHandlerData
7995 ///  ::= .handlerdata
7996 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
7997   // Check the ordering of unwind directives
7998   HandlerDataLoc = L;
7999   if (!FnStartLoc.isValid())
8000     return Error(L, ".fnstart must precede .personality directive");
8001   if (CantUnwindLoc.isValid()) {
8002     Error(L, ".handlerdata can't be used with .cantunwind directive");
8003     Error(CantUnwindLoc, ".cantunwind was specified here");
8004     return true;
8005   }
8006 
8007   getParser().getStreamer().EmitHandlerData();
8008   return false;
8009 }
8010 
8011 /// parseDirectiveSetFP
8012 ///  ::= .setfp fpreg, spreg [, offset]
8013 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8014   // Check the ordering of unwind directives
8015   if (!FnStartLoc.isValid())
8016     return Error(L, ".fnstart must precede .setfp directive");
8017   if (HandlerDataLoc.isValid())
8018     return Error(L, ".setfp must precede .handlerdata directive");
8019 
8020   // Parse fpreg
8021   SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8022   int NewFPReg = tryParseRegister();
8023   if (NewFPReg == -1)
8024     return Error(NewFPRegLoc, "frame pointer register expected");
8025 
8026   // Consume comma
8027   if (!Parser.getTok().is(AsmToken::Comma))
8028     return Error(Parser.getTok().getLoc(), "comma expected");
8029   Parser.Lex(); // skip comma
8030 
8031   // Parse spreg
8032   SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8033   int NewSPReg = tryParseRegister();
8034   if (NewSPReg == -1)
8035     return Error(NewSPRegLoc, "stack pointer register expected");
8036 
8037   if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8038     return Error(NewSPRegLoc,
8039                  "register should be either $sp or the latest fp register");
8040 
8041   // Update the frame pointer register
8042   FPReg = NewFPReg;
8043 
8044   // Parse offset
8045   int64_t Offset = 0;
8046   if (Parser.getTok().is(AsmToken::Comma)) {
8047     Parser.Lex(); // skip comma
8048 
8049     if (Parser.getTok().isNot(AsmToken::Hash) &&
8050         Parser.getTok().isNot(AsmToken::Dollar)) {
8051       return Error(Parser.getTok().getLoc(), "'#' expected");
8052     }
8053     Parser.Lex(); // skip hash token.
8054 
8055     const MCExpr *OffsetExpr;
8056     SMLoc ExLoc = Parser.getTok().getLoc();
8057     SMLoc EndLoc;
8058     if (getParser().parseExpression(OffsetExpr, EndLoc))
8059       return Error(ExLoc, "malformed setfp offset");
8060     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8061     if (!CE)
8062       return Error(ExLoc, "setfp offset must be an immediate");
8063 
8064     Offset = CE->getValue();
8065   }
8066 
8067   getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8068                                       static_cast<unsigned>(NewSPReg),
8069                                       Offset);
8070   return false;
8071 }
8072 
8073 /// parseDirective
8074 ///  ::= .pad offset
8075 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8076   // Check the ordering of unwind directives
8077   if (!FnStartLoc.isValid())
8078     return Error(L, ".fnstart must precede .pad directive");
8079   if (HandlerDataLoc.isValid())
8080     return Error(L, ".pad must precede .handlerdata directive");
8081 
8082   // Parse the offset
8083   if (Parser.getTok().isNot(AsmToken::Hash) &&
8084       Parser.getTok().isNot(AsmToken::Dollar)) {
8085     return Error(Parser.getTok().getLoc(), "'#' expected");
8086   }
8087   Parser.Lex(); // skip hash token.
8088 
8089   const MCExpr *OffsetExpr;
8090   SMLoc ExLoc = Parser.getTok().getLoc();
8091   SMLoc EndLoc;
8092   if (getParser().parseExpression(OffsetExpr, EndLoc))
8093     return Error(ExLoc, "malformed pad offset");
8094   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8095   if (!CE)
8096     return Error(ExLoc, "pad offset must be an immediate");
8097 
8098   getParser().getStreamer().EmitPad(CE->getValue());
8099   return false;
8100 }
8101 
8102 /// parseDirectiveRegSave
8103 ///  ::= .save  { registers }
8104 ///  ::= .vsave { registers }
8105 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8106   // Check the ordering of unwind directives
8107   if (!FnStartLoc.isValid())
8108     return Error(L, ".fnstart must precede .save or .vsave directives");
8109   if (HandlerDataLoc.isValid())
8110     return Error(L, ".save or .vsave must precede .handlerdata directive");
8111 
8112   // RAII object to make sure parsed operands are deleted.
8113   struct CleanupObject {
8114     SmallVector<MCParsedAsmOperand *, 1> Operands;
8115     ~CleanupObject() {
8116       for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8117         delete Operands[I];
8118     }
8119   } CO;
8120 
8121   // Parse the register list
8122   if (parseRegisterList(CO.Operands))
8123     return true;
8124   ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8125   if (!IsVector && !Op->isRegList())
8126     return Error(L, ".save expects GPR registers");
8127   if (IsVector && !Op->isDPRRegList())
8128     return Error(L, ".vsave expects DPR registers");
8129 
8130   getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8131   return false;
8132 }
8133 
8134 /// Force static initialization.
8135 extern "C" void LLVMInitializeARMAsmParser() {
8136   RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8137   RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8138 }
8139 
8140 #define GET_REGISTER_MATCHER
8141 #define GET_SUBTARGET_FEATURE_NAME
8142 #define GET_MATCHER_IMPLEMENTATION
8143 #include "ARMGenAsmMatcher.inc"
8144 
8145 // Define this matcher function after the auto-generated include so we
8146 // have the match class enum definitions.
8147 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8148                                                   unsigned Kind) {
8149   ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8150   // If the kind is a token for a literal immediate, check if our asm
8151   // operand matches. This is for InstAliases which have a fixed-value
8152   // immediate in the syntax.
8153   if (Kind == MCK__35_0 && Op->isImm()) {
8154     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8155     if (!CE)
8156       return Match_InvalidOperand;
8157     if (CE->getValue() == 0)
8158       return Match_Success;
8159   }
8160   return Match_InvalidOperand;
8161 }
8162