1 //===- ARMTargetTransformInfo.cpp - ARM specific TTI ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMTargetTransformInfo.h" 10 #include "ARMSubtarget.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "llvm/ADT/APInt.h" 13 #include "llvm/ADT/SmallVector.h" 14 #include "llvm/Analysis/LoopInfo.h" 15 #include "llvm/CodeGen/CostTable.h" 16 #include "llvm/CodeGen/ISDOpcodes.h" 17 #include "llvm/CodeGen/ValueTypes.h" 18 #include "llvm/IR/BasicBlock.h" 19 #include "llvm/IR/CallSite.h" 20 #include "llvm/IR/DataLayout.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Instruction.h" 23 #include "llvm/IR/Instructions.h" 24 #include "llvm/IR/IntrinsicInst.h" 25 #include "llvm/IR/Type.h" 26 #include "llvm/MC/SubtargetFeature.h" 27 #include "llvm/Support/Casting.h" 28 #include "llvm/Support/MachineValueType.h" 29 #include "llvm/Target/TargetMachine.h" 30 #include <algorithm> 31 #include <cassert> 32 #include <cstdint> 33 #include <utility> 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "armtti" 38 39 bool ARMTTIImpl::areInlineCompatible(const Function *Caller, 40 const Function *Callee) const { 41 const TargetMachine &TM = getTLI()->getTargetMachine(); 42 const FeatureBitset &CallerBits = 43 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 44 const FeatureBitset &CalleeBits = 45 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 46 47 // To inline a callee, all features not in the whitelist must match exactly. 48 bool MatchExact = (CallerBits & ~InlineFeatureWhitelist) == 49 (CalleeBits & ~InlineFeatureWhitelist); 50 // For features in the whitelist, the callee's features must be a subset of 51 // the callers'. 52 bool MatchSubset = ((CallerBits & CalleeBits) & InlineFeatureWhitelist) == 53 (CalleeBits & InlineFeatureWhitelist); 54 return MatchExact && MatchSubset; 55 } 56 57 int ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 58 assert(Ty->isIntegerTy()); 59 60 unsigned Bits = Ty->getPrimitiveSizeInBits(); 61 if (Bits == 0 || Imm.getActiveBits() >= 64) 62 return 4; 63 64 int64_t SImmVal = Imm.getSExtValue(); 65 uint64_t ZImmVal = Imm.getZExtValue(); 66 if (!ST->isThumb()) { 67 if ((SImmVal >= 0 && SImmVal < 65536) || 68 (ARM_AM::getSOImmVal(ZImmVal) != -1) || 69 (ARM_AM::getSOImmVal(~ZImmVal) != -1)) 70 return 1; 71 return ST->hasV6T2Ops() ? 2 : 3; 72 } 73 if (ST->isThumb2()) { 74 if ((SImmVal >= 0 && SImmVal < 65536) || 75 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) || 76 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1)) 77 return 1; 78 return ST->hasV6T2Ops() ? 2 : 3; 79 } 80 // Thumb1, any i8 imm cost 1. 81 if (Bits == 8 || (SImmVal >= 0 && SImmVal < 256)) 82 return 1; 83 if ((~SImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal)) 84 return 2; 85 // Load from constantpool. 86 return 3; 87 } 88 89 // Constants smaller than 256 fit in the immediate field of 90 // Thumb1 instructions so we return a zero cost and 1 otherwise. 91 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, 92 const APInt &Imm, Type *Ty) { 93 if (Imm.isNonNegative() && Imm.getLimitedValue() < 256) 94 return 0; 95 96 return 1; 97 } 98 99 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 100 Type *Ty) { 101 // Division by a constant can be turned into multiplication, but only if we 102 // know it's constant. So it's not so much that the immediate is cheap (it's 103 // not), but that the alternative is worse. 104 // FIXME: this is probably unneeded with GlobalISel. 105 if ((Opcode == Instruction::SDiv || Opcode == Instruction::UDiv || 106 Opcode == Instruction::SRem || Opcode == Instruction::URem) && 107 Idx == 1) 108 return 0; 109 110 if (Opcode == Instruction::And) { 111 // UXTB/UXTH 112 if (Imm == 255 || Imm == 65535) 113 return 0; 114 // Conversion to BIC is free, and means we can use ~Imm instead. 115 return std::min(getIntImmCost(Imm, Ty), getIntImmCost(~Imm, Ty)); 116 } 117 118 if (Opcode == Instruction::Add) 119 // Conversion to SUB is free, and means we can use -Imm instead. 120 return std::min(getIntImmCost(Imm, Ty), getIntImmCost(-Imm, Ty)); 121 122 if (Opcode == Instruction::ICmp && Imm.isNegative() && 123 Ty->getIntegerBitWidth() == 32) { 124 int64_t NegImm = -Imm.getSExtValue(); 125 if (ST->isThumb2() && NegImm < 1<<12) 126 // icmp X, #-C -> cmn X, #C 127 return 0; 128 if (ST->isThumb() && NegImm < 1<<8) 129 // icmp X, #-C -> adds X, #C 130 return 0; 131 } 132 133 // xor a, -1 can always be folded to MVN 134 if (Opcode == Instruction::Xor && Imm.isAllOnesValue()) 135 return 0; 136 137 return getIntImmCost(Imm, Ty); 138 } 139 140 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 141 const Instruction *I) { 142 int ISD = TLI->InstructionOpcodeToISD(Opcode); 143 assert(ISD && "Invalid opcode"); 144 145 // Single to/from double precision conversions. 146 static const CostTblEntry NEONFltDblTbl[] = { 147 // Vector fptrunc/fpext conversions. 148 { ISD::FP_ROUND, MVT::v2f64, 2 }, 149 { ISD::FP_EXTEND, MVT::v2f32, 2 }, 150 { ISD::FP_EXTEND, MVT::v4f32, 4 } 151 }; 152 153 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || 154 ISD == ISD::FP_EXTEND)) { 155 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 156 if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second)) 157 return LT.first * Entry->Cost; 158 } 159 160 EVT SrcTy = TLI->getValueType(DL, Src); 161 EVT DstTy = TLI->getValueType(DL, Dst); 162 163 if (!SrcTy.isSimple() || !DstTy.isSimple()) 164 return BaseT::getCastInstrCost(Opcode, Dst, Src); 165 166 // Some arithmetic, load and store operations have specific instructions 167 // to cast up/down their types automatically at no extra cost. 168 // TODO: Get these tables to know at least what the related operations are. 169 static const TypeConversionCostTblEntry NEONVectorConversionTbl[] = { 170 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 171 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 172 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 173 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 174 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 175 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 176 177 // The number of vmovl instructions for the extension. 178 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 179 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 180 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 181 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 182 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, 183 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, 184 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, 185 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, 186 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 187 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 188 189 // Operations that we legalize using splitting. 190 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 191 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 192 193 // Vector float <-> i32 conversions. 194 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 195 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 196 197 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 198 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 199 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 200 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 201 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 202 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 203 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 204 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 205 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 206 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 207 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 208 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 209 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 210 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 211 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 212 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 213 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, 214 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, 215 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, 216 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, 217 218 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 219 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 220 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 221 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 222 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 223 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 224 225 // Vector double <-> i32 conversions. 226 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 227 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 228 229 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 230 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 231 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, 232 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, 233 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 234 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 235 236 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, 237 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, 238 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, 239 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, 240 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, 241 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } 242 }; 243 244 if (SrcTy.isVector() && ST->hasNEON()) { 245 if (const auto *Entry = ConvertCostTableLookup(NEONVectorConversionTbl, ISD, 246 DstTy.getSimpleVT(), 247 SrcTy.getSimpleVT())) 248 return Entry->Cost; 249 } 250 251 // Scalar float to integer conversions. 252 static const TypeConversionCostTblEntry NEONFloatConversionTbl[] = { 253 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, 254 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 }, 255 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, 256 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 }, 257 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, 258 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 }, 259 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, 260 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 }, 261 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 }, 262 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 }, 263 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 }, 264 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 }, 265 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 }, 266 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 }, 267 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 }, 268 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 }, 269 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 }, 270 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 }, 271 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 }, 272 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 } 273 }; 274 if (SrcTy.isFloatingPoint() && ST->hasNEON()) { 275 if (const auto *Entry = ConvertCostTableLookup(NEONFloatConversionTbl, ISD, 276 DstTy.getSimpleVT(), 277 SrcTy.getSimpleVT())) 278 return Entry->Cost; 279 } 280 281 // Scalar integer to float conversions. 282 static const TypeConversionCostTblEntry NEONIntegerConversionTbl[] = { 283 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 }, 284 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 }, 285 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 }, 286 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 }, 287 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, 288 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 }, 289 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, 290 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 }, 291 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, 292 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 }, 293 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, 294 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 }, 295 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 }, 296 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 }, 297 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 }, 298 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 }, 299 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 }, 300 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 }, 301 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 }, 302 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 } 303 }; 304 305 if (SrcTy.isInteger() && ST->hasNEON()) { 306 if (const auto *Entry = ConvertCostTableLookup(NEONIntegerConversionTbl, 307 ISD, DstTy.getSimpleVT(), 308 SrcTy.getSimpleVT())) 309 return Entry->Cost; 310 } 311 312 // Scalar integer conversion costs. 313 static const TypeConversionCostTblEntry ARMIntegerConversionTbl[] = { 314 // i16 -> i64 requires two dependent operations. 315 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 }, 316 317 // Truncates on i64 are assumed to be free. 318 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 }, 319 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 }, 320 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 }, 321 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 } 322 }; 323 324 if (SrcTy.isInteger()) { 325 if (const auto *Entry = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD, 326 DstTy.getSimpleVT(), 327 SrcTy.getSimpleVT())) 328 return Entry->Cost; 329 } 330 331 return BaseT::getCastInstrCost(Opcode, Dst, Src); 332 } 333 334 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, 335 unsigned Index) { 336 // Penalize inserting into an D-subregister. We end up with a three times 337 // lower estimated throughput on swift. 338 if (ST->hasSlowLoadDSubregister() && Opcode == Instruction::InsertElement && 339 ValTy->isVectorTy() && ValTy->getScalarSizeInBits() <= 32) 340 return 3; 341 342 if ((Opcode == Instruction::InsertElement || 343 Opcode == Instruction::ExtractElement)) { 344 // Cross-class copies are expensive on many microarchitectures, 345 // so assume they are expensive by default. 346 if (ValTy->getVectorElementType()->isIntegerTy()) 347 return 3; 348 349 // Even if it's not a cross class copy, this likely leads to mixing 350 // of NEON and VFP code and should be therefore penalized. 351 if (ValTy->isVectorTy() && 352 ValTy->getScalarSizeInBits() <= 32) 353 return std::max(BaseT::getVectorInstrCost(Opcode, ValTy, Index), 2U); 354 } 355 356 return BaseT::getVectorInstrCost(Opcode, ValTy, Index); 357 } 358 359 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 360 const Instruction *I) { 361 int ISD = TLI->InstructionOpcodeToISD(Opcode); 362 // On NEON a vector select gets lowered to vbsl. 363 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) { 364 // Lowering of some vector selects is currently far from perfect. 365 static const TypeConversionCostTblEntry NEONVectorSelectTbl[] = { 366 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, 367 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, 368 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 } 369 }; 370 371 EVT SelCondTy = TLI->getValueType(DL, CondTy); 372 EVT SelValTy = TLI->getValueType(DL, ValTy); 373 if (SelCondTy.isSimple() && SelValTy.isSimple()) { 374 if (const auto *Entry = ConvertCostTableLookup(NEONVectorSelectTbl, ISD, 375 SelCondTy.getSimpleVT(), 376 SelValTy.getSimpleVT())) 377 return Entry->Cost; 378 } 379 380 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 381 return LT.first; 382 } 383 384 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 385 } 386 387 int ARMTTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 388 const SCEV *Ptr) { 389 // Address computations in vectorized code with non-consecutive addresses will 390 // likely result in more instructions compared to scalar code where the 391 // computation can more often be merged into the index mode. The resulting 392 // extra micro-ops can significantly decrease throughput. 393 unsigned NumVectorInstToHideOverhead = 10; 394 int MaxMergeDistance = 64; 395 396 if (Ty->isVectorTy() && SE && 397 !BaseT::isConstantStridedAccessLessThan(SE, Ptr, MaxMergeDistance + 1)) 398 return NumVectorInstToHideOverhead; 399 400 // In many cases the address computation is not merged into the instruction 401 // addressing mode. 402 return 1; 403 } 404 405 int ARMTTIImpl::getMemcpyCost(const Instruction *I) { 406 const MemCpyInst *MI = dyn_cast<MemCpyInst>(I); 407 assert(MI && "MemcpyInst expected"); 408 ConstantInt *C = dyn_cast<ConstantInt>(MI->getLength()); 409 410 // To model the cost of a library call, we assume 1 for the call, and 411 // 3 for the argument setup. 412 const unsigned LibCallCost = 4; 413 414 // If 'size' is not a constant, a library call will be generated. 415 if (!C) 416 return LibCallCost; 417 418 const unsigned Size = C->getValue().getZExtValue(); 419 const unsigned DstAlign = MI->getDestAlignment(); 420 const unsigned SrcAlign = MI->getSourceAlignment(); 421 const Function *F = I->getParent()->getParent(); 422 const unsigned Limit = TLI->getMaxStoresPerMemmove(F->hasMinSize()); 423 std::vector<EVT> MemOps; 424 425 // MemOps will be poplulated with a list of data types that needs to be 426 // loaded and stored. That's why we multiply the number of elements by 2 to 427 // get the cost for this memcpy. 428 if (getTLI()->findOptimalMemOpLowering( 429 MemOps, Limit, Size, DstAlign, SrcAlign, false /*IsMemset*/, 430 false /*ZeroMemset*/, false /*MemcpyStrSrc*/, false /*AllowOverlap*/, 431 MI->getDestAddressSpace(), MI->getSourceAddressSpace(), 432 F->getAttributes())) 433 return MemOps.size() * 2; 434 435 // If we can't find an optimal memop lowering, return the default cost 436 return LibCallCost; 437 } 438 439 int ARMTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 440 Type *SubTp) { 441 if (Kind == TTI::SK_Broadcast) { 442 static const CostTblEntry NEONDupTbl[] = { 443 // VDUP handles these cases. 444 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, 445 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, 446 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 447 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 448 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, 449 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, 450 451 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, 452 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, 453 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, 454 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}; 455 456 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 457 458 if (const auto *Entry = CostTableLookup(NEONDupTbl, ISD::VECTOR_SHUFFLE, 459 LT.second)) 460 return LT.first * Entry->Cost; 461 462 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 463 } 464 if (Kind == TTI::SK_Reverse) { 465 static const CostTblEntry NEONShuffleTbl[] = { 466 // Reverse shuffle cost one instruction if we are shuffling within a 467 // double word (vrev) or two if we shuffle a quad word (vrev, vext). 468 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, 469 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, 470 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 471 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 472 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, 473 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, 474 475 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, 476 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, 477 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 2}, 478 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}}; 479 480 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 481 482 if (const auto *Entry = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, 483 LT.second)) 484 return LT.first * Entry->Cost; 485 486 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 487 } 488 if (Kind == TTI::SK_Select) { 489 static const CostTblEntry NEONSelShuffleTbl[] = { 490 // Select shuffle cost table for ARM. Cost is the number of instructions 491 // required to create the shuffled vector. 492 493 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, 494 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 495 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 496 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, 497 498 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, 499 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, 500 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 2}, 501 502 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 16}, 503 504 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}}; 505 506 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 507 if (const auto *Entry = CostTableLookup(NEONSelShuffleTbl, 508 ISD::VECTOR_SHUFFLE, LT.second)) 509 return LT.first * Entry->Cost; 510 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 511 } 512 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 513 } 514 515 int ARMTTIImpl::getArithmeticInstrCost( 516 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, 517 TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo, 518 TTI::OperandValueProperties Opd2PropInfo, 519 ArrayRef<const Value *> Args) { 520 int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode); 521 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 522 523 const unsigned FunctionCallDivCost = 20; 524 const unsigned ReciprocalDivCost = 10; 525 static const CostTblEntry CostTbl[] = { 526 // Division. 527 // These costs are somewhat random. Choose a cost of 20 to indicate that 528 // vectorizing devision (added function call) is going to be very expensive. 529 // Double registers types. 530 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, 531 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, 532 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, 533 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, 534 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, 535 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost}, 536 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, 537 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, 538 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, 539 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost}, 540 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, 541 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, 542 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, 543 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost}, 544 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, 545 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, 546 // Quad register types. 547 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, 548 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost}, 549 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, 550 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, 551 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, 552 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost}, 553 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, 554 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, 555 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, 556 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost}, 557 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, 558 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, 559 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, 560 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost}, 561 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, 562 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, 563 // Multiplication. 564 }; 565 566 if (ST->hasNEON()) 567 if (const auto *Entry = CostTableLookup(CostTbl, ISDOpcode, LT.second)) 568 return LT.first * Entry->Cost; 569 570 int Cost = BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info, 571 Opd1PropInfo, Opd2PropInfo); 572 573 // This is somewhat of a hack. The problem that we are facing is that SROA 574 // creates a sequence of shift, and, or instructions to construct values. 575 // These sequences are recognized by the ISel and have zero-cost. Not so for 576 // the vectorized code. Because we have support for v2i64 but not i64 those 577 // sequences look particularly beneficial to vectorize. 578 // To work around this we increase the cost of v2i64 operations to make them 579 // seem less beneficial. 580 if (LT.second == MVT::v2i64 && 581 Op2Info == TargetTransformInfo::OK_UniformConstantValue) 582 Cost += 4; 583 584 return Cost; 585 } 586 587 int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 588 unsigned AddressSpace, const Instruction *I) { 589 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 590 591 if (Src->isVectorTy() && Alignment != 16 && 592 Src->getVectorElementType()->isDoubleTy()) { 593 // Unaligned loads/stores are extremely inefficient. 594 // We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr. 595 return LT.first * 4; 596 } 597 return LT.first; 598 } 599 600 int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 601 unsigned Factor, 602 ArrayRef<unsigned> Indices, 603 unsigned Alignment, 604 unsigned AddressSpace, 605 bool UseMaskForCond, 606 bool UseMaskForGaps) { 607 assert(Factor >= 2 && "Invalid interleave factor"); 608 assert(isa<VectorType>(VecTy) && "Expect a vector type"); 609 610 // vldN/vstN doesn't support vector types of i64/f64 element. 611 bool EltIs64Bits = DL.getTypeSizeInBits(VecTy->getScalarType()) == 64; 612 613 if (Factor <= TLI->getMaxSupportedInterleaveFactor() && !EltIs64Bits && 614 !UseMaskForCond && !UseMaskForGaps) { 615 unsigned NumElts = VecTy->getVectorNumElements(); 616 auto *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor); 617 618 // vldN/vstN only support legal vector types of size 64 or 128 in bits. 619 // Accesses having vector types that are a multiple of 128 bits can be 620 // matched to more than one vldN/vstN instruction. 621 if (NumElts % Factor == 0 && 622 TLI->isLegalInterleavedAccessType(SubVecTy, DL)) 623 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL); 624 } 625 626 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 627 Alignment, AddressSpace, 628 UseMaskForCond, UseMaskForGaps); 629 } 630 631 void ARMTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 632 TTI::UnrollingPreferences &UP) { 633 // Only currently enable these preferences for M-Class cores. 634 if (!ST->isMClass()) 635 return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP); 636 637 // Disable loop unrolling for Oz and Os. 638 UP.OptSizeThreshold = 0; 639 UP.PartialOptSizeThreshold = 0; 640 if (L->getHeader()->getParent()->hasOptSize()) 641 return; 642 643 // Only enable on Thumb-2 targets. 644 if (!ST->isThumb2()) 645 return; 646 647 SmallVector<BasicBlock*, 4> ExitingBlocks; 648 L->getExitingBlocks(ExitingBlocks); 649 LLVM_DEBUG(dbgs() << "Loop has:\n" 650 << "Blocks: " << L->getNumBlocks() << "\n" 651 << "Exit blocks: " << ExitingBlocks.size() << "\n"); 652 653 // Only allow another exit other than the latch. This acts as an early exit 654 // as it mirrors the profitability calculation of the runtime unroller. 655 if (ExitingBlocks.size() > 2) 656 return; 657 658 // Limit the CFG of the loop body for targets with a branch predictor. 659 // Allowing 4 blocks permits if-then-else diamonds in the body. 660 if (ST->hasBranchPredictor() && L->getNumBlocks() > 4) 661 return; 662 663 // Scan the loop: don't unroll loops with calls as this could prevent 664 // inlining. 665 unsigned Cost = 0; 666 for (auto *BB : L->getBlocks()) { 667 for (auto &I : *BB) { 668 if (isa<CallInst>(I) || isa<InvokeInst>(I)) { 669 ImmutableCallSite CS(&I); 670 if (const Function *F = CS.getCalledFunction()) { 671 if (!isLoweredToCall(F)) 672 continue; 673 } 674 return; 675 } 676 SmallVector<const Value*, 4> Operands(I.value_op_begin(), 677 I.value_op_end()); 678 Cost += getUserCost(&I, Operands); 679 } 680 } 681 682 LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n"); 683 684 UP.Partial = true; 685 UP.Runtime = true; 686 UP.UnrollRemainder = true; 687 UP.DefaultUnrollRuntimeCount = 4; 688 UP.UnrollAndJam = true; 689 UP.UnrollAndJamInnerLoopThreshold = 60; 690 691 // Force unrolling small loops can be very useful because of the branch 692 // taken cost of the backedge. 693 if (Cost < 12) 694 UP.Force = true; 695 } 696