1 //===- ARMTargetTransformInfo.cpp - ARM specific TTI ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMTargetTransformInfo.h" 10 #include "ARMSubtarget.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "llvm/ADT/APInt.h" 13 #include "llvm/ADT/SmallVector.h" 14 #include "llvm/Analysis/LoopInfo.h" 15 #include "llvm/CodeGen/CostTable.h" 16 #include "llvm/CodeGen/ISDOpcodes.h" 17 #include "llvm/CodeGen/ValueTypes.h" 18 #include "llvm/IR/BasicBlock.h" 19 #include "llvm/IR/CallSite.h" 20 #include "llvm/IR/DataLayout.h" 21 #include "llvm/IR/DerivedTypes.h" 22 #include "llvm/IR/Instruction.h" 23 #include "llvm/IR/Instructions.h" 24 #include "llvm/IR/Type.h" 25 #include "llvm/MC/SubtargetFeature.h" 26 #include "llvm/Support/Casting.h" 27 #include "llvm/Support/MachineValueType.h" 28 #include "llvm/Target/TargetMachine.h" 29 #include <algorithm> 30 #include <cassert> 31 #include <cstdint> 32 #include <utility> 33 34 using namespace llvm; 35 36 #define DEBUG_TYPE "armtti" 37 38 bool ARMTTIImpl::areInlineCompatible(const Function *Caller, 39 const Function *Callee) const { 40 const TargetMachine &TM = getTLI()->getTargetMachine(); 41 const FeatureBitset &CallerBits = 42 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 43 const FeatureBitset &CalleeBits = 44 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 45 46 // To inline a callee, all features not in the whitelist must match exactly. 47 bool MatchExact = (CallerBits & ~InlineFeatureWhitelist) == 48 (CalleeBits & ~InlineFeatureWhitelist); 49 // For features in the whitelist, the callee's features must be a subset of 50 // the callers'. 51 bool MatchSubset = ((CallerBits & CalleeBits) & InlineFeatureWhitelist) == 52 (CalleeBits & InlineFeatureWhitelist); 53 return MatchExact && MatchSubset; 54 } 55 56 int ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 57 assert(Ty->isIntegerTy()); 58 59 unsigned Bits = Ty->getPrimitiveSizeInBits(); 60 if (Bits == 0 || Imm.getActiveBits() >= 64) 61 return 4; 62 63 int64_t SImmVal = Imm.getSExtValue(); 64 uint64_t ZImmVal = Imm.getZExtValue(); 65 if (!ST->isThumb()) { 66 if ((SImmVal >= 0 && SImmVal < 65536) || 67 (ARM_AM::getSOImmVal(ZImmVal) != -1) || 68 (ARM_AM::getSOImmVal(~ZImmVal) != -1)) 69 return 1; 70 return ST->hasV6T2Ops() ? 2 : 3; 71 } 72 if (ST->isThumb2()) { 73 if ((SImmVal >= 0 && SImmVal < 65536) || 74 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) || 75 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1)) 76 return 1; 77 return ST->hasV6T2Ops() ? 2 : 3; 78 } 79 // Thumb1, any i8 imm cost 1. 80 if (Bits == 8 || (SImmVal >= 0 && SImmVal < 256)) 81 return 1; 82 if ((~SImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal)) 83 return 2; 84 // Load from constantpool. 85 return 3; 86 } 87 88 // Constants smaller than 256 fit in the immediate field of 89 // Thumb1 instructions so we return a zero cost and 1 otherwise. 90 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, 91 const APInt &Imm, Type *Ty) { 92 if (Imm.isNonNegative() && Imm.getLimitedValue() < 256) 93 return 0; 94 95 return 1; 96 } 97 98 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 99 Type *Ty) { 100 // Division by a constant can be turned into multiplication, but only if we 101 // know it's constant. So it's not so much that the immediate is cheap (it's 102 // not), but that the alternative is worse. 103 // FIXME: this is probably unneeded with GlobalISel. 104 if ((Opcode == Instruction::SDiv || Opcode == Instruction::UDiv || 105 Opcode == Instruction::SRem || Opcode == Instruction::URem) && 106 Idx == 1) 107 return 0; 108 109 if (Opcode == Instruction::And) { 110 // UXTB/UXTH 111 if (Imm == 255 || Imm == 65535) 112 return 0; 113 // Conversion to BIC is free, and means we can use ~Imm instead. 114 return std::min(getIntImmCost(Imm, Ty), getIntImmCost(~Imm, Ty)); 115 } 116 117 if (Opcode == Instruction::Add) 118 // Conversion to SUB is free, and means we can use -Imm instead. 119 return std::min(getIntImmCost(Imm, Ty), getIntImmCost(-Imm, Ty)); 120 121 if (Opcode == Instruction::ICmp && Imm.isNegative() && 122 Ty->getIntegerBitWidth() == 32) { 123 int64_t NegImm = -Imm.getSExtValue(); 124 if (ST->isThumb2() && NegImm < 1<<12) 125 // icmp X, #-C -> cmn X, #C 126 return 0; 127 if (ST->isThumb() && NegImm < 1<<8) 128 // icmp X, #-C -> adds X, #C 129 return 0; 130 } 131 132 // xor a, -1 can always be folded to MVN 133 if (Opcode == Instruction::Xor && Imm.isAllOnesValue()) 134 return 0; 135 136 return getIntImmCost(Imm, Ty); 137 } 138 139 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 140 const Instruction *I) { 141 int ISD = TLI->InstructionOpcodeToISD(Opcode); 142 assert(ISD && "Invalid opcode"); 143 144 // Single to/from double precision conversions. 145 static const CostTblEntry NEONFltDblTbl[] = { 146 // Vector fptrunc/fpext conversions. 147 { ISD::FP_ROUND, MVT::v2f64, 2 }, 148 { ISD::FP_EXTEND, MVT::v2f32, 2 }, 149 { ISD::FP_EXTEND, MVT::v4f32, 4 } 150 }; 151 152 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || 153 ISD == ISD::FP_EXTEND)) { 154 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 155 if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second)) 156 return LT.first * Entry->Cost; 157 } 158 159 EVT SrcTy = TLI->getValueType(DL, Src); 160 EVT DstTy = TLI->getValueType(DL, Dst); 161 162 if (!SrcTy.isSimple() || !DstTy.isSimple()) 163 return BaseT::getCastInstrCost(Opcode, Dst, Src); 164 165 // Some arithmetic, load and store operations have specific instructions 166 // to cast up/down their types automatically at no extra cost. 167 // TODO: Get these tables to know at least what the related operations are. 168 static const TypeConversionCostTblEntry NEONVectorConversionTbl[] = { 169 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 170 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 171 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 172 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 173 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 174 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 175 176 // The number of vmovl instructions for the extension. 177 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 178 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 179 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 180 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 181 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, 182 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, 183 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, 184 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, 185 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 186 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, 187 188 // Operations that we legalize using splitting. 189 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 190 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 191 192 // Vector float <-> i32 conversions. 193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 194 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 195 196 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 197 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, 198 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 199 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 200 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 201 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 202 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 203 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 204 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 205 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 206 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 207 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 208 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 209 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 210 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 211 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 212 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, 213 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, 214 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, 215 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, 216 217 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 218 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 219 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, 220 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 }, 221 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 222 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 223 224 // Vector double <-> i32 conversions. 225 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 226 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 227 228 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 229 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, 230 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, 231 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, 232 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 233 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 234 235 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, 236 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, 237 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, 238 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, 239 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, 240 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } 241 }; 242 243 if (SrcTy.isVector() && ST->hasNEON()) { 244 if (const auto *Entry = ConvertCostTableLookup(NEONVectorConversionTbl, ISD, 245 DstTy.getSimpleVT(), 246 SrcTy.getSimpleVT())) 247 return Entry->Cost; 248 } 249 250 // Scalar float to integer conversions. 251 static const TypeConversionCostTblEntry NEONFloatConversionTbl[] = { 252 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, 253 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 }, 254 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, 255 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 }, 256 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, 257 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 }, 258 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, 259 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 }, 260 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 }, 261 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 }, 262 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 }, 263 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 }, 264 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 }, 265 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 }, 266 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 }, 267 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 }, 268 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 }, 269 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 }, 270 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 }, 271 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 } 272 }; 273 if (SrcTy.isFloatingPoint() && ST->hasNEON()) { 274 if (const auto *Entry = ConvertCostTableLookup(NEONFloatConversionTbl, ISD, 275 DstTy.getSimpleVT(), 276 SrcTy.getSimpleVT())) 277 return Entry->Cost; 278 } 279 280 // Scalar integer to float conversions. 281 static const TypeConversionCostTblEntry NEONIntegerConversionTbl[] = { 282 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 }, 283 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 }, 284 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 }, 285 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 }, 286 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 }, 287 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 }, 288 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 }, 289 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 }, 290 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 }, 291 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 }, 292 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 }, 293 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 }, 294 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 }, 295 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 }, 296 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 }, 297 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 }, 298 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 }, 299 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 }, 300 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 }, 301 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 } 302 }; 303 304 if (SrcTy.isInteger() && ST->hasNEON()) { 305 if (const auto *Entry = ConvertCostTableLookup(NEONIntegerConversionTbl, 306 ISD, DstTy.getSimpleVT(), 307 SrcTy.getSimpleVT())) 308 return Entry->Cost; 309 } 310 311 // Scalar integer conversion costs. 312 static const TypeConversionCostTblEntry ARMIntegerConversionTbl[] = { 313 // i16 -> i64 requires two dependent operations. 314 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 }, 315 316 // Truncates on i64 are assumed to be free. 317 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 }, 318 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 }, 319 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 }, 320 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 } 321 }; 322 323 if (SrcTy.isInteger()) { 324 if (const auto *Entry = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD, 325 DstTy.getSimpleVT(), 326 SrcTy.getSimpleVT())) 327 return Entry->Cost; 328 } 329 330 return BaseT::getCastInstrCost(Opcode, Dst, Src); 331 } 332 333 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy, 334 unsigned Index) { 335 // Penalize inserting into an D-subregister. We end up with a three times 336 // lower estimated throughput on swift. 337 if (ST->hasSlowLoadDSubregister() && Opcode == Instruction::InsertElement && 338 ValTy->isVectorTy() && ValTy->getScalarSizeInBits() <= 32) 339 return 3; 340 341 if ((Opcode == Instruction::InsertElement || 342 Opcode == Instruction::ExtractElement)) { 343 // Cross-class copies are expensive on many microarchitectures, 344 // so assume they are expensive by default. 345 if (ValTy->getVectorElementType()->isIntegerTy()) 346 return 3; 347 348 // Even if it's not a cross class copy, this likely leads to mixing 349 // of NEON and VFP code and should be therefore penalized. 350 if (ValTy->isVectorTy() && 351 ValTy->getScalarSizeInBits() <= 32) 352 return std::max(BaseT::getVectorInstrCost(Opcode, ValTy, Index), 2U); 353 } 354 355 return BaseT::getVectorInstrCost(Opcode, ValTy, Index); 356 } 357 358 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 359 const Instruction *I) { 360 int ISD = TLI->InstructionOpcodeToISD(Opcode); 361 // On NEON a vector select gets lowered to vbsl. 362 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) { 363 // Lowering of some vector selects is currently far from perfect. 364 static const TypeConversionCostTblEntry NEONVectorSelectTbl[] = { 365 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, 366 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, 367 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 } 368 }; 369 370 EVT SelCondTy = TLI->getValueType(DL, CondTy); 371 EVT SelValTy = TLI->getValueType(DL, ValTy); 372 if (SelCondTy.isSimple() && SelValTy.isSimple()) { 373 if (const auto *Entry = ConvertCostTableLookup(NEONVectorSelectTbl, ISD, 374 SelCondTy.getSimpleVT(), 375 SelValTy.getSimpleVT())) 376 return Entry->Cost; 377 } 378 379 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 380 return LT.first; 381 } 382 383 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 384 } 385 386 int ARMTTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 387 const SCEV *Ptr) { 388 // Address computations in vectorized code with non-consecutive addresses will 389 // likely result in more instructions compared to scalar code where the 390 // computation can more often be merged into the index mode. The resulting 391 // extra micro-ops can significantly decrease throughput. 392 unsigned NumVectorInstToHideOverhead = 10; 393 int MaxMergeDistance = 64; 394 395 if (Ty->isVectorTy() && SE && 396 !BaseT::isConstantStridedAccessLessThan(SE, Ptr, MaxMergeDistance + 1)) 397 return NumVectorInstToHideOverhead; 398 399 // In many cases the address computation is not merged into the instruction 400 // addressing mode. 401 return 1; 402 } 403 404 int ARMTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 405 Type *SubTp) { 406 if (Kind == TTI::SK_Broadcast) { 407 static const CostTblEntry NEONDupTbl[] = { 408 // VDUP handles these cases. 409 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, 410 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, 411 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 412 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 413 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, 414 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, 415 416 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, 417 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, 418 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, 419 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 1}}; 420 421 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 422 423 if (const auto *Entry = CostTableLookup(NEONDupTbl, ISD::VECTOR_SHUFFLE, 424 LT.second)) 425 return LT.first * Entry->Cost; 426 427 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 428 } 429 if (Kind == TTI::SK_Reverse) { 430 static const CostTblEntry NEONShuffleTbl[] = { 431 // Reverse shuffle cost one instruction if we are shuffling within a 432 // double word (vrev) or two if we shuffle a quad word (vrev, vext). 433 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, 434 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, 435 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 436 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 437 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, 438 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, 439 440 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, 441 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, 442 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 2}, 443 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 2}}; 444 445 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 446 447 if (const auto *Entry = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE, 448 LT.second)) 449 return LT.first * Entry->Cost; 450 451 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 452 } 453 if (Kind == TTI::SK_Select) { 454 static const CostTblEntry NEONSelShuffleTbl[] = { 455 // Select shuffle cost table for ARM. Cost is the number of instructions 456 // required to create the shuffled vector. 457 458 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, 459 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, 460 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, 461 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, 462 463 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, 464 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, 465 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 2}, 466 467 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 16}, 468 469 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 32}}; 470 471 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 472 if (const auto *Entry = CostTableLookup(NEONSelShuffleTbl, 473 ISD::VECTOR_SHUFFLE, LT.second)) 474 return LT.first * Entry->Cost; 475 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 476 } 477 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 478 } 479 480 int ARMTTIImpl::getArithmeticInstrCost( 481 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info, 482 TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo, 483 TTI::OperandValueProperties Opd2PropInfo, 484 ArrayRef<const Value *> Args) { 485 int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode); 486 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 487 488 const unsigned FunctionCallDivCost = 20; 489 const unsigned ReciprocalDivCost = 10; 490 static const CostTblEntry CostTbl[] = { 491 // Division. 492 // These costs are somewhat random. Choose a cost of 20 to indicate that 493 // vectorizing devision (added function call) is going to be very expensive. 494 // Double registers types. 495 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, 496 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, 497 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, 498 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, 499 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, 500 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost}, 501 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, 502 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, 503 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, 504 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost}, 505 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, 506 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, 507 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, 508 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost}, 509 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, 510 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, 511 // Quad register types. 512 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, 513 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost}, 514 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, 515 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, 516 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, 517 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost}, 518 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, 519 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, 520 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, 521 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost}, 522 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, 523 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, 524 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, 525 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost}, 526 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, 527 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, 528 // Multiplication. 529 }; 530 531 if (ST->hasNEON()) 532 if (const auto *Entry = CostTableLookup(CostTbl, ISDOpcode, LT.second)) 533 return LT.first * Entry->Cost; 534 535 int Cost = BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info, 536 Opd1PropInfo, Opd2PropInfo); 537 538 // This is somewhat of a hack. The problem that we are facing is that SROA 539 // creates a sequence of shift, and, or instructions to construct values. 540 // These sequences are recognized by the ISel and have zero-cost. Not so for 541 // the vectorized code. Because we have support for v2i64 but not i64 those 542 // sequences look particularly beneficial to vectorize. 543 // To work around this we increase the cost of v2i64 operations to make them 544 // seem less beneficial. 545 if (LT.second == MVT::v2i64 && 546 Op2Info == TargetTransformInfo::OK_UniformConstantValue) 547 Cost += 4; 548 549 return Cost; 550 } 551 552 int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 553 unsigned AddressSpace, const Instruction *I) { 554 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 555 556 if (Src->isVectorTy() && Alignment != 16 && 557 Src->getVectorElementType()->isDoubleTy()) { 558 // Unaligned loads/stores are extremely inefficient. 559 // We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr. 560 return LT.first * 4; 561 } 562 return LT.first; 563 } 564 565 int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 566 unsigned Factor, 567 ArrayRef<unsigned> Indices, 568 unsigned Alignment, 569 unsigned AddressSpace, 570 bool UseMaskForCond, 571 bool UseMaskForGaps) { 572 assert(Factor >= 2 && "Invalid interleave factor"); 573 assert(isa<VectorType>(VecTy) && "Expect a vector type"); 574 575 // vldN/vstN doesn't support vector types of i64/f64 element. 576 bool EltIs64Bits = DL.getTypeSizeInBits(VecTy->getScalarType()) == 64; 577 578 if (Factor <= TLI->getMaxSupportedInterleaveFactor() && !EltIs64Bits && 579 !UseMaskForCond && !UseMaskForGaps) { 580 unsigned NumElts = VecTy->getVectorNumElements(); 581 auto *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor); 582 583 // vldN/vstN only support legal vector types of size 64 or 128 in bits. 584 // Accesses having vector types that are a multiple of 128 bits can be 585 // matched to more than one vldN/vstN instruction. 586 if (NumElts % Factor == 0 && 587 TLI->isLegalInterleavedAccessType(SubVecTy, DL)) 588 return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL); 589 } 590 591 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 592 Alignment, AddressSpace, 593 UseMaskForCond, UseMaskForGaps); 594 } 595 596 void ARMTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 597 TTI::UnrollingPreferences &UP) { 598 // Only currently enable these preferences for M-Class cores. 599 if (!ST->isMClass()) 600 return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP); 601 602 // Disable loop unrolling for Oz and Os. 603 UP.OptSizeThreshold = 0; 604 UP.PartialOptSizeThreshold = 0; 605 if (L->getHeader()->getParent()->optForSize()) 606 return; 607 608 // Only enable on Thumb-2 targets. 609 if (!ST->isThumb2()) 610 return; 611 612 SmallVector<BasicBlock*, 4> ExitingBlocks; 613 L->getExitingBlocks(ExitingBlocks); 614 LLVM_DEBUG(dbgs() << "Loop has:\n" 615 << "Blocks: " << L->getNumBlocks() << "\n" 616 << "Exit blocks: " << ExitingBlocks.size() << "\n"); 617 618 // Only allow another exit other than the latch. This acts as an early exit 619 // as it mirrors the profitability calculation of the runtime unroller. 620 if (ExitingBlocks.size() > 2) 621 return; 622 623 // Limit the CFG of the loop body for targets with a branch predictor. 624 // Allowing 4 blocks permits if-then-else diamonds in the body. 625 if (ST->hasBranchPredictor() && L->getNumBlocks() > 4) 626 return; 627 628 // Scan the loop: don't unroll loops with calls as this could prevent 629 // inlining. 630 unsigned Cost = 0; 631 for (auto *BB : L->getBlocks()) { 632 for (auto &I : *BB) { 633 if (isa<CallInst>(I) || isa<InvokeInst>(I)) { 634 ImmutableCallSite CS(&I); 635 if (const Function *F = CS.getCalledFunction()) { 636 if (!isLoweredToCall(F)) 637 continue; 638 } 639 return; 640 } 641 SmallVector<const Value*, 4> Operands(I.value_op_begin(), 642 I.value_op_end()); 643 Cost += getUserCost(&I, Operands); 644 } 645 } 646 647 LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n"); 648 649 UP.Partial = true; 650 UP.Runtime = true; 651 UP.UnrollRemainder = true; 652 UP.DefaultUnrollRuntimeCount = 4; 653 UP.UnrollAndJam = true; 654 UP.UnrollAndJamInnerLoopThreshold = 60; 655 656 // Force unrolling small loops can be very useful because of the branch 657 // taken cost of the backedge. 658 if (Cost < 12) 659 UP.Force = true; 660 } 661