1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the ARM specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
16 
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetData.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMFrameInfo.h"
21 #include "ARMJITInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMISelLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 
27 namespace llvm {
28 
29 class ARMBaseTargetMachine : public LLVMTargetMachine {
30 protected:
31   ARMSubtarget        Subtarget;
32 
33 private:
34   ARMFrameInfo        FrameInfo;
35   ARMJITInfo          JITInfo;
36   InstrItineraryData  InstrItins;
37   Reloc::Model        DefRelocModel;    // Reloc model before it's overridden.
38 
39 public:
40   ARMBaseTargetMachine(const Target &T, const std::string &TT,
41                        const std::string &FS, bool isThumb);
42 
43   virtual const ARMFrameInfo     *getFrameInfo() const { return &FrameInfo; }
44   virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
45   virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
46   virtual const InstrItineraryData getInstrItineraryData() const {
47     return InstrItins;
48   }
49 
50   virtual const TargetAsmInfo *createTargetAsmInfo() const;
51 
52   // Pass Pipeline Configuration
53   virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54   virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55   virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
57                               MachineCodeEmitter &MCE);
58   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
59                               JITCodeEmitter &MCE);
60   virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
61                               ObjectCodeEmitter &OCE);
62   virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
63                                     CodeGenOpt::Level OptLevel,
64                                     MachineCodeEmitter &MCE);
65   virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
66                                     CodeGenOpt::Level OptLevel,
67                                     JITCodeEmitter &MCE);
68   virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
69                                     CodeGenOpt::Level OptLevel,
70                                     ObjectCodeEmitter &OCE);
71 };
72 
73 /// ARMTargetMachine - ARM target machine.
74 ///
75 class ARMTargetMachine : public ARMBaseTargetMachine {
76   ARMInstrInfo        InstrInfo;
77   const TargetData    DataLayout;       // Calculates type size & alignment
78   ARMTargetLowering   TLInfo;
79 public:
80   ARMTargetMachine(const Target &T, const std::string &TT,
81                    const std::string &FS);
82 
83   virtual const ARMRegisterInfo  *getRegisterInfo() const {
84     return &InstrInfo.getRegisterInfo();
85   }
86 
87   virtual       ARMTargetLowering *getTargetLowering() const {
88     return const_cast<ARMTargetLowering*>(&TLInfo);
89   }
90 
91   virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
92   virtual const TargetData       *getTargetData() const { return &DataLayout; }
93 };
94 
95 /// ThumbTargetMachine - Thumb target machine.
96 /// Due to the way architectures are handled, this represents both
97 ///   Thumb-1 and Thumb-2.
98 ///
99 class ThumbTargetMachine : public ARMBaseTargetMachine {
100   ARMBaseInstrInfo    *InstrInfo;   // either Thumb1InstrInfo or Thumb2InstrInfo
101   const TargetData    DataLayout;   // Calculates type size & alignment
102   ARMTargetLowering   TLInfo;
103 public:
104   ThumbTargetMachine(const Target &T, const std::string &TT,
105                      const std::string &FS);
106 
107   /// returns either Thumb1RegisterInfo of Thumb2RegisterInfo
108   virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
109     return &InstrInfo->getRegisterInfo();
110   }
111 
112   virtual ARMTargetLowering *getTargetLowering() const {
113     return const_cast<ARMTargetLowering*>(&TLInfo);
114   }
115 
116   /// returns either Thumb1InstrInfo or Thumb2InstrInfo
117   virtual const ARMBaseInstrInfo *getInstrInfo() const { return InstrInfo; }
118   virtual const TargetData       *getTargetData() const { return &DataLayout; }
119 };
120 
121 } // end namespace llvm
122 
123 #endif
124