1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the ARM specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
16 
17 #include "ARMInstrInfo.h"
18 #include "ARMELFWriterInfo.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMJITInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMISelLowering.h"
23 #include "ARMSelectionDAGInfo.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/ADT/OwningPtr.h"
31 
32 namespace llvm {
33 
34 class ARMBaseTargetMachine : public LLVMTargetMachine {
35 protected:
36   ARMSubtarget        Subtarget;
37 private:
38   ARMJITInfo          JITInfo;
39   InstrItineraryData  InstrItins;
40 
41 public:
42   ARMBaseTargetMachine(const Target &T, StringRef TT,
43                        StringRef CPU, StringRef FS,
44                        Reloc::Model RM, CodeModel::Model CM,
45                        CodeGenOpt::Level OL);
46 
47   virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
48   virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
49   virtual const InstrItineraryData *getInstrItineraryData() const {
50     return &InstrItins;
51   }
52 
53   // Pass Pipeline Configuration
54   virtual bool addPreISel(PassManagerBase &PM);
55   virtual bool addInstSelector(PassManagerBase &PM);
56   virtual bool addPreRegAlloc(PassManagerBase &PM);
57   virtual bool addPreSched2(PassManagerBase &PM);
58   virtual bool addPreEmitPass(PassManagerBase &PM);
59   virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
60 };
61 
62 /// ARMTargetMachine - ARM target machine.
63 ///
64 class ARMTargetMachine : public ARMBaseTargetMachine {
65   ARMInstrInfo        InstrInfo;
66   const TargetData    DataLayout;       // Calculates type size & alignment
67   ARMELFWriterInfo    ELFWriterInfo;
68   ARMTargetLowering   TLInfo;
69   ARMSelectionDAGInfo TSInfo;
70   ARMFrameLowering    FrameLowering;
71  public:
72   ARMTargetMachine(const Target &T, StringRef TT,
73                    StringRef CPU, StringRef FS,
74                    Reloc::Model RM, CodeModel::Model CM,
75                    CodeGenOpt::Level OL);
76 
77   virtual const ARMRegisterInfo  *getRegisterInfo() const {
78     return &InstrInfo.getRegisterInfo();
79   }
80 
81   virtual const ARMTargetLowering *getTargetLowering() const {
82     return &TLInfo;
83   }
84 
85   virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
86     return &TSInfo;
87   }
88   virtual const ARMFrameLowering *getFrameLowering() const {
89     return &FrameLowering;
90   }
91 
92   virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
93   virtual const TargetData       *getTargetData() const { return &DataLayout; }
94   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
95     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
96   }
97 };
98 
99 /// ThumbTargetMachine - Thumb target machine.
100 /// Due to the way architectures are handled, this represents both
101 ///   Thumb-1 and Thumb-2.
102 ///
103 class ThumbTargetMachine : public ARMBaseTargetMachine {
104   // Either Thumb1InstrInfo or Thumb2InstrInfo.
105   OwningPtr<ARMBaseInstrInfo> InstrInfo;
106   const TargetData    DataLayout;   // Calculates type size & alignment
107   ARMELFWriterInfo    ELFWriterInfo;
108   ARMTargetLowering   TLInfo;
109   ARMSelectionDAGInfo TSInfo;
110   // Either Thumb1FrameLowering or ARMFrameLowering.
111   OwningPtr<ARMFrameLowering> FrameLowering;
112 public:
113   ThumbTargetMachine(const Target &T, StringRef TT,
114                      StringRef CPU, StringRef FS,
115                      Reloc::Model RM, CodeModel::Model CM,
116                      CodeGenOpt::Level OL);
117 
118   /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
119   virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
120     return &InstrInfo->getRegisterInfo();
121   }
122 
123   virtual const ARMTargetLowering *getTargetLowering() const {
124     return &TLInfo;
125   }
126 
127   virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
128     return &TSInfo;
129   }
130 
131   /// returns either Thumb1InstrInfo or Thumb2InstrInfo
132   virtual const ARMBaseInstrInfo *getInstrInfo() const {
133     return InstrInfo.get();
134   }
135   /// returns either Thumb1FrameLowering or ARMFrameLowering
136   virtual const ARMFrameLowering *getFrameLowering() const {
137     return FrameLowering.get();
138   }
139   virtual const TargetData       *getTargetData() const { return &DataLayout; }
140   virtual const ARMELFWriterInfo *getELFWriterInfo() const {
141     return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
142   }
143 };
144 
145 } // end namespace llvm
146 
147 #endif
148