1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMTargetMachine.h" 14 #include "ARMFrameLowering.h" 15 #include "ARM.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/CodeGen/Passes.h" 18 #include "llvm/Support/CommandLine.h" 19 #include "llvm/Support/FormattedStream.h" 20 #include "llvm/Support/TargetRegistry.h" 21 #include "llvm/Target/TargetOptions.h" 22 using namespace llvm; 23 24 static cl::opt<bool> 25 EnableGlobalMerge("global-merge", cl::Hidden, 26 cl::desc("Enable global merge pass"), 27 cl::init(true)); 28 29 extern "C" void LLVMInitializeARMTarget() { 30 // Register the target. 31 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget); 32 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget); 33 } 34 35 /// TargetMachine ctor - Create an ARM architecture model. 36 /// 37 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, 38 StringRef CPU, StringRef FS, 39 Reloc::Model RM, CodeModel::Model CM) 40 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), 41 Subtarget(TT, CPU, FS), 42 JITInfo(), 43 InstrItins(Subtarget.getInstrItineraryData()) { 44 // Default to soft float ABI 45 if (FloatABIType == FloatABI::Default) 46 FloatABIType = FloatABI::Soft; 47 } 48 49 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, 50 StringRef CPU, StringRef FS, 51 Reloc::Model RM, CodeModel::Model CM) 52 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget), 53 DataLayout(Subtarget.isAPCS_ABI() ? 54 std::string("e-p:32:32-f64:32:64-i64:32:64-" 55 "v128:32:128-v64:32:64-n32") : 56 std::string("e-p:32:32-f64:64:64-i64:64:64-" 57 "v128:64:128-v64:64:64-n32")), 58 ELFWriterInfo(*this), 59 TLInfo(*this), 60 TSInfo(*this), 61 FrameLowering(Subtarget) { 62 if (!Subtarget.hasARMOps()) 63 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " 64 "support ARM mode execution!"); 65 } 66 67 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, 68 StringRef CPU, StringRef FS, 69 Reloc::Model RM, CodeModel::Model CM) 70 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), 71 InstrInfo(Subtarget.hasThumb2() 72 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) 73 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), 74 DataLayout(Subtarget.isAPCS_ABI() ? 75 std::string("e-p:32:32-f64:32:64-i64:32:64-" 76 "i16:16:32-i8:8:32-i1:8:32-" 77 "v128:32:128-v64:32:64-a:0:32-n32") : 78 std::string("e-p:32:32-f64:64:64-i64:64:64-" 79 "i16:16:32-i8:8:32-i1:8:32-" 80 "v128:64:128-v64:64:64-a:0:32-n32")), 81 ELFWriterInfo(*this), 82 TLInfo(*this), 83 TSInfo(*this), 84 FrameLowering(Subtarget.hasThumb2() 85 ? new ARMFrameLowering(Subtarget) 86 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) { 87 } 88 89 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM, 90 CodeGenOpt::Level OptLevel) { 91 if (OptLevel != CodeGenOpt::None && EnableGlobalMerge) 92 PM.add(createARMGlobalMergePass(getTargetLowering())); 93 94 return false; 95 } 96 97 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM, 98 CodeGenOpt::Level OptLevel) { 99 PM.add(createARMISelDag(*this, OptLevel)); 100 return false; 101 } 102 103 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, 104 CodeGenOpt::Level OptLevel) { 105 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 106 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) 107 PM.add(createARMLoadStoreOptimizationPass(true)); 108 if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9()) 109 PM.add(createMLxExpansionPass()); 110 111 return true; 112 } 113 114 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, 115 CodeGenOpt::Level OptLevel) { 116 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 117 if (OptLevel != CodeGenOpt::None) { 118 if (!Subtarget.isThumb1Only()) 119 PM.add(createARMLoadStoreOptimizationPass()); 120 if (Subtarget.hasNEON()) 121 PM.add(createNEONMoveFixPass()); 122 } 123 124 // Expand some pseudo instructions into multiple instructions to allow 125 // proper scheduling. 126 PM.add(createARMExpandPseudoPass()); 127 128 if (OptLevel != CodeGenOpt::None) { 129 if (!Subtarget.isThumb1Only()) 130 PM.add(createIfConverterPass()); 131 } 132 if (Subtarget.isThumb2()) 133 PM.add(createThumb2ITBlockPass()); 134 135 return true; 136 } 137 138 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, 139 CodeGenOpt::Level OptLevel) { 140 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb()) 141 PM.add(createThumb2SizeReductionPass()); 142 143 PM.add(createARMConstantIslandPass()); 144 return true; 145 } 146 147 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 148 CodeGenOpt::Level OptLevel, 149 JITCodeEmitter &JCE) { 150 // Machine code emitter pass for ARM. 151 PM.add(createARMJITCodeEmitterPass(*this, JCE)); 152 return false; 153 } 154