1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "MCTargetDesc/ARMMCTargetDesc.h"
19 #include "TargetInfo/ARMTargetInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/ExecutionDomainFix.h"
26 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/TargetParser.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include "llvm/Transforms/Scalar.h"
51 #include <cassert>
52 #include <memory>
53 #include <string>
54 
55 using namespace llvm;
56 
57 static cl::opt<bool>
58 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
59                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
60                    cl::init(false));
61 
62 static cl::opt<bool>
63 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
64                  cl::desc("Run SimplifyCFG after expanding atomic operations"
65                           " to make use of cmpxchg flow-based information"),
66                  cl::init(true));
67 
68 static cl::opt<bool>
69 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
70                       cl::desc("Enable ARM load/store optimization pass"),
71                       cl::init(true));
72 
73 // FIXME: Unify control over GlobalMerge.
74 static cl::opt<cl::boolOrDefault>
75 EnableGlobalMerge("arm-global-merge", cl::Hidden,
76                   cl::desc("Enable the global merge pass"));
77 
78 namespace llvm {
79   void initializeARMExecutionDomainFixPass(PassRegistry&);
80 }
81 
82 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
83   // Register the target.
84   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
85   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
86   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
87   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
88 
89   PassRegistry &Registry = *PassRegistry::getPassRegistry();
90   initializeGlobalISel(Registry);
91   initializeARMLoadStoreOptPass(Registry);
92   initializeARMPreAllocLoadStoreOptPass(Registry);
93   initializeARMParallelDSPPass(Registry);
94   initializeARMConstantIslandsPass(Registry);
95   initializeARMExecutionDomainFixPass(Registry);
96   initializeARMExpandPseudoPass(Registry);
97   initializeThumb2SizeReducePass(Registry);
98   initializeMVEVPTBlockPass(Registry);
99   initializeMVETPAndVPTOptimisationsPass(Registry);
100   initializeMVETailPredicationPass(Registry);
101   initializeARMLowOverheadLoopsPass(Registry);
102   initializeARMBlockPlacementPass(Registry);
103   initializeMVEGatherScatterLoweringPass(Registry);
104   initializeARMSLSHardeningPass(Registry);
105   initializeMVELaneInterleavingPass(Registry);
106 }
107 
108 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
109   if (TT.isOSBinFormatMachO())
110     return std::make_unique<TargetLoweringObjectFileMachO>();
111   if (TT.isOSWindows())
112     return std::make_unique<TargetLoweringObjectFileCOFF>();
113   return std::make_unique<ARMElfTargetObjectFile>();
114 }
115 
116 static ARMBaseTargetMachine::ARMABI
117 computeTargetABI(const Triple &TT, StringRef CPU,
118                  const TargetOptions &Options) {
119   StringRef ABIName = Options.MCOptions.getABIName();
120 
121   if (ABIName.empty())
122     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
123 
124   if (ABIName == "aapcs16")
125     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
126   else if (ABIName.startswith("aapcs"))
127     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
128   else if (ABIName.startswith("apcs"))
129     return ARMBaseTargetMachine::ARM_ABI_APCS;
130 
131   llvm_unreachable("Unhandled/unknown ABI Name!");
132   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
133 }
134 
135 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
136                                      const TargetOptions &Options,
137                                      bool isLittle) {
138   auto ABI = computeTargetABI(TT, CPU, Options);
139   std::string Ret;
140 
141   if (isLittle)
142     // Little endian.
143     Ret += "e";
144   else
145     // Big endian.
146     Ret += "E";
147 
148   Ret += DataLayout::getManglingComponent(TT);
149 
150   // Pointers are 32 bits and aligned to 32 bits.
151   Ret += "-p:32:32";
152 
153   // Function pointers are aligned to 8 bits (because the LSB stores the
154   // ARM/Thumb state).
155   Ret += "-Fi8";
156 
157   // ABIs other than APCS have 64 bit integers with natural alignment.
158   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
159     Ret += "-i64:64";
160 
161   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
162   // bits, others to 64 bits. We always try to align to 64 bits.
163   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
164     Ret += "-f64:32:64";
165 
166   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
167   // to 64. We always ty to give them natural alignment.
168   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
169     Ret += "-v64:32:64-v128:32:128";
170   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
171     Ret += "-v128:64:128";
172 
173   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
174   // particular hardware support on 32-bit ARM).
175   Ret += "-a:0:32";
176 
177   // Integer registers are 32 bits.
178   Ret += "-n32";
179 
180   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
181   // aligned everywhere else.
182   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
183     Ret += "-S128";
184   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
185     Ret += "-S64";
186   else
187     Ret += "-S32";
188 
189   return Ret;
190 }
191 
192 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
193                                            Optional<Reloc::Model> RM) {
194   if (!RM.hasValue())
195     // Default relocation model on Darwin is PIC.
196     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
197 
198   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
199     assert(TT.isOSBinFormatELF() &&
200            "ROPI/RWPI currently only supported for ELF");
201 
202   // DynamicNoPIC is only used on darwin.
203   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
204     return Reloc::Static;
205 
206   return *RM;
207 }
208 
209 /// Create an ARM architecture model.
210 ///
211 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
212                                            StringRef CPU, StringRef FS,
213                                            const TargetOptions &Options,
214                                            Optional<Reloc::Model> RM,
215                                            Optional<CodeModel::Model> CM,
216                                            CodeGenOpt::Level OL, bool isLittle)
217     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
218                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
219                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
220       TargetABI(computeTargetABI(TT, CPU, Options)),
221       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
222 
223   // Default to triple-appropriate float ABI
224   if (Options.FloatABIType == FloatABI::Default) {
225     if (isTargetHardFloat())
226       this->Options.FloatABIType = FloatABI::Hard;
227     else
228       this->Options.FloatABIType = FloatABI::Soft;
229   }
230 
231   // Default to triple-appropriate EABI
232   if (Options.EABIVersion == EABI::Default ||
233       Options.EABIVersion == EABI::Unknown) {
234     // musl is compatible with glibc with regard to EABI version
235     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
236          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
237          TargetTriple.getEnvironment() == Triple::MuslEABI ||
238          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
239         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
240       this->Options.EABIVersion = EABI::GNU;
241     else
242       this->Options.EABIVersion = EABI::EABI5;
243   }
244 
245   if (TT.isOSBinFormatMachO()) {
246     this->Options.TrapUnreachable = true;
247     this->Options.NoTrapAfterNoreturn = true;
248   }
249 
250   // ARM supports the debug entry values.
251   setSupportsDebugEntryValues(true);
252 
253   initAsmInfo();
254 
255   // ARM supports the MachineOutliner.
256   setMachineOutliner(true);
257   setSupportsDefaultOutlining(true);
258 }
259 
260 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
261 
262 const ARMSubtarget *
263 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
264   Attribute CPUAttr = F.getFnAttribute("target-cpu");
265   Attribute FSAttr = F.getFnAttribute("target-features");
266 
267   std::string CPU =
268       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
269   std::string FS =
270       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
271 
272   // FIXME: This is related to the code below to reset the target options,
273   // we need to know whether or not the soft float flag is set on the
274   // function before we can generate a subtarget. We also need to use
275   // it as a key for the subtarget since that can be the only difference
276   // between two functions.
277   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
278   // If the soft float attribute is set on the function turn on the soft float
279   // subtarget feature.
280   if (SoftFloat)
281     FS += FS.empty() ? "+soft-float" : ",+soft-float";
282 
283   // Use the optminsize to identify the subtarget, but don't use it in the
284   // feature string.
285   std::string Key = CPU + FS;
286   if (F.hasMinSize())
287     Key += "+minsize";
288 
289   auto &I = SubtargetMap[Key];
290   if (!I) {
291     // This needs to be done before we create a new subtarget since any
292     // creation will depend on the TM and the code generation flags on the
293     // function that reside in TargetOptions.
294     resetTargetOptions(F);
295     I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
296                                         F.hasMinSize());
297 
298     if (!I->isThumb() && !I->hasARMOps())
299       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
300           "instructions, but the target does not support ARM mode execution.");
301   }
302 
303   return I.get();
304 }
305 
306 TargetTransformInfo
307 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) {
308   return TargetTransformInfo(ARMTTIImpl(this, F));
309 }
310 
311 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
312                                        StringRef CPU, StringRef FS,
313                                        const TargetOptions &Options,
314                                        Optional<Reloc::Model> RM,
315                                        Optional<CodeModel::Model> CM,
316                                        CodeGenOpt::Level OL, bool JIT)
317     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
318 
319 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
320                                        StringRef CPU, StringRef FS,
321                                        const TargetOptions &Options,
322                                        Optional<Reloc::Model> RM,
323                                        Optional<CodeModel::Model> CM,
324                                        CodeGenOpt::Level OL, bool JIT)
325     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
326 
327 namespace {
328 
329 /// ARM Code Generator Pass Configuration Options.
330 class ARMPassConfig : public TargetPassConfig {
331 public:
332   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
333       : TargetPassConfig(TM, PM) {}
334 
335   ARMBaseTargetMachine &getARMTargetMachine() const {
336     return getTM<ARMBaseTargetMachine>();
337   }
338 
339   ScheduleDAGInstrs *
340   createMachineScheduler(MachineSchedContext *C) const override {
341     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
342     // add DAG Mutations here.
343     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
344     if (ST.hasFusion())
345       DAG->addMutation(createARMMacroFusionDAGMutation());
346     return DAG;
347   }
348 
349   ScheduleDAGInstrs *
350   createPostMachineScheduler(MachineSchedContext *C) const override {
351     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
352     // add DAG Mutations here.
353     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
354     if (ST.hasFusion())
355       DAG->addMutation(createARMMacroFusionDAGMutation());
356     return DAG;
357   }
358 
359   void addIRPasses() override;
360   void addCodeGenPrepare() override;
361   bool addPreISel() override;
362   bool addInstSelector() override;
363   bool addIRTranslator() override;
364   bool addLegalizeMachineIR() override;
365   bool addRegBankSelect() override;
366   bool addGlobalInstructionSelect() override;
367   void addPreRegAlloc() override;
368   void addPreSched2() override;
369   void addPreEmitPass() override;
370   void addPreEmitPass2() override;
371 
372   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
373 };
374 
375 class ARMExecutionDomainFix : public ExecutionDomainFix {
376 public:
377   static char ID;
378   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
379   StringRef getPassName() const override {
380     return "ARM Execution Domain Fix";
381   }
382 };
383 char ARMExecutionDomainFix::ID;
384 
385 } // end anonymous namespace
386 
387 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
388   "ARM Execution Domain Fix", false, false)
389 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
390 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
391   "ARM Execution Domain Fix", false, false)
392 
393 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
394   return new ARMPassConfig(*this, PM);
395 }
396 
397 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
398   return getStandardCSEConfigForOpt(TM->getOptLevel());
399 }
400 
401 void ARMPassConfig::addIRPasses() {
402   if (TM->Options.ThreadModel == ThreadModel::Single)
403     addPass(createLowerAtomicPass());
404   else
405     addPass(createAtomicExpandPass());
406 
407   // Cmpxchg instructions are often used with a subsequent comparison to
408   // determine whether it succeeded. We can exploit existing control-flow in
409   // ldrex/strex loops to simplify this, but it needs tidying up.
410   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
411     addPass(createCFGSimplificationPass(
412         SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
413         [this](const Function &F) {
414           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
415           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
416         }));
417 
418   addPass(createMVEGatherScatterLoweringPass());
419   addPass(createMVELaneInterleavingPass());
420 
421   TargetPassConfig::addIRPasses();
422 
423   // Run the parallel DSP pass.
424   if (getOptLevel() == CodeGenOpt::Aggressive)
425     addPass(createARMParallelDSPPass());
426 
427   // Match interleaved memory accesses to ldN/stN intrinsics.
428   if (TM->getOptLevel() != CodeGenOpt::None)
429     addPass(createInterleavedAccessPass());
430 
431   // Add Control Flow Guard checks.
432   if (TM->getTargetTriple().isOSWindows())
433     addPass(createCFGuardCheckPass());
434 }
435 
436 void ARMPassConfig::addCodeGenPrepare() {
437   if (getOptLevel() != CodeGenOpt::None)
438     addPass(createTypePromotionPass());
439   TargetPassConfig::addCodeGenPrepare();
440 }
441 
442 bool ARMPassConfig::addPreISel() {
443   if ((TM->getOptLevel() != CodeGenOpt::None &&
444        EnableGlobalMerge == cl::BOU_UNSET) ||
445       EnableGlobalMerge == cl::BOU_TRUE) {
446     // FIXME: This is using the thumb1 only constant value for
447     // maximal global offset for merging globals. We may want
448     // to look into using the old value for non-thumb1 code of
449     // 4095 based on the TargetMachine, but this starts to become
450     // tricky when doing code gen per function.
451     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
452                                (EnableGlobalMerge == cl::BOU_UNSET);
453     // Merging of extern globals is enabled by default on non-Mach-O as we
454     // expect it to be generally either beneficial or harmless. On Mach-O it
455     // is disabled as we emit the .subsections_via_symbols directive which
456     // means that merging extern globals is not safe.
457     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
458     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
459                                   MergeExternalByDefault));
460   }
461 
462   if (TM->getOptLevel() != CodeGenOpt::None) {
463     addPass(createHardwareLoopsPass());
464     addPass(createMVETailPredicationPass());
465   }
466 
467   return false;
468 }
469 
470 bool ARMPassConfig::addInstSelector() {
471   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
472   return false;
473 }
474 
475 bool ARMPassConfig::addIRTranslator() {
476   addPass(new IRTranslator(getOptLevel()));
477   return false;
478 }
479 
480 bool ARMPassConfig::addLegalizeMachineIR() {
481   addPass(new Legalizer());
482   return false;
483 }
484 
485 bool ARMPassConfig::addRegBankSelect() {
486   addPass(new RegBankSelect());
487   return false;
488 }
489 
490 bool ARMPassConfig::addGlobalInstructionSelect() {
491   addPass(new InstructionSelect(getOptLevel()));
492   return false;
493 }
494 
495 void ARMPassConfig::addPreRegAlloc() {
496   if (getOptLevel() != CodeGenOpt::None) {
497     addPass(createMVETPAndVPTOptimisationsPass());
498 
499     addPass(createMLxExpansionPass());
500 
501     if (EnableARMLoadStoreOpt)
502       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
503 
504     if (!DisableA15SDOptimization)
505       addPass(createA15SDOptimizerPass());
506   }
507 }
508 
509 void ARMPassConfig::addPreSched2() {
510   if (getOptLevel() != CodeGenOpt::None) {
511     if (EnableARMLoadStoreOpt)
512       addPass(createARMLoadStoreOptimizationPass());
513 
514     addPass(new ARMExecutionDomainFix());
515     addPass(createBreakFalseDeps());
516   }
517 
518   // Expand some pseudo instructions into multiple instructions to allow
519   // proper scheduling.
520   addPass(createARMExpandPseudoPass());
521 
522   if (getOptLevel() != CodeGenOpt::None) {
523     // When optimising for size, always run the Thumb2SizeReduction pass before
524     // IfConversion. Otherwise, check whether IT blocks are restricted
525     // (e.g. in v8, IfConversion depends on Thumb instruction widths)
526     addPass(createThumb2SizeReductionPass([this](const Function &F) {
527       return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
528              this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
529     }));
530 
531     addPass(createIfConverter([](const MachineFunction &MF) {
532       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
533     }));
534   }
535   addPass(createMVEVPTBlockPass());
536   addPass(createThumb2ITBlockPass());
537 
538   // Add both scheduling passes to give the subtarget an opportunity to pick
539   // between them.
540   if (getOptLevel() != CodeGenOpt::None) {
541     addPass(&PostMachineSchedulerID);
542     addPass(&PostRASchedulerID);
543   }
544 
545   addPass(createARMIndirectThunks());
546   addPass(createARMSLSHardeningPass());
547 }
548 
549 void ARMPassConfig::addPreEmitPass() {
550   addPass(createThumb2SizeReductionPass());
551 
552   // Constant island pass work on unbundled instructions.
553   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
554     return MF.getSubtarget<ARMSubtarget>().isThumb2();
555   }));
556 
557   // Don't optimize barriers or block placement at -O0.
558   if (getOptLevel() != CodeGenOpt::None) {
559     addPass(createARMBlockPlacementPass());
560     addPass(createARMOptimizeBarriersPass());
561   }
562 }
563 
564 void ARMPassConfig::addPreEmitPass2() {
565   addPass(createARMConstantIslandPass());
566   addPass(createARMLowOverheadLoopsPass());
567 
568   if (TM->getTargetTriple().isOSWindows()) {
569     // Identify valid longjmp targets for Windows Control Flow Guard.
570     addPass(createCFGuardLongjmpPass());
571     // Identify valid eh continuation targets for Windows EHCont Guard.
572     addPass(createEHContGuardCatchretPass());
573   }
574 }
575