1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "MCTargetDesc/ARMMCTargetDesc.h"
19 #include "TargetInfo/ARMTargetInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/ExecutionDomainFix.h"
26 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
27 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
28 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
30 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
31 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
32 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
33 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/RegisterBankInfo.h"
38 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/MC/TargetRegistry.h"
43 #include "llvm/Pass.h"
44 #include "llvm/Support/ARMTargetParser.h"
45 #include "llvm/Support/CodeGen.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/TargetParser.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
51 #include "llvm/Transforms/CFGuard.h"
52 #include "llvm/Transforms/IPO.h"
53 #include "llvm/Transforms/Scalar.h"
54 #include <cassert>
55 #include <memory>
56 #include <string>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool>
61 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
62                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
63                    cl::init(false));
64 
65 static cl::opt<bool>
66 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
67                  cl::desc("Run SimplifyCFG after expanding atomic operations"
68                           " to make use of cmpxchg flow-based information"),
69                  cl::init(true));
70 
71 static cl::opt<bool>
72 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
73                       cl::desc("Enable ARM load/store optimization pass"),
74                       cl::init(true));
75 
76 // FIXME: Unify control over GlobalMerge.
77 static cl::opt<cl::boolOrDefault>
78 EnableGlobalMerge("arm-global-merge", cl::Hidden,
79                   cl::desc("Enable the global merge pass"));
80 
81 namespace llvm {
82   void initializeARMExecutionDomainFixPass(PassRegistry&);
83 }
84 
85 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
86   // Register the target.
87   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
88   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
89   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
90   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
91 
92   PassRegistry &Registry = *PassRegistry::getPassRegistry();
93   initializeGlobalISel(Registry);
94   initializeARMLoadStoreOptPass(Registry);
95   initializeARMPreAllocLoadStoreOptPass(Registry);
96   initializeARMParallelDSPPass(Registry);
97   initializeARMBranchTargetsPass(Registry);
98   initializeARMConstantIslandsPass(Registry);
99   initializeARMExecutionDomainFixPass(Registry);
100   initializeARMExpandPseudoPass(Registry);
101   initializeThumb2SizeReducePass(Registry);
102   initializeMVEVPTBlockPass(Registry);
103   initializeMVETPAndVPTOptimisationsPass(Registry);
104   initializeMVETailPredicationPass(Registry);
105   initializeARMLowOverheadLoopsPass(Registry);
106   initializeARMBlockPlacementPass(Registry);
107   initializeMVEGatherScatterLoweringPass(Registry);
108   initializeARMSLSHardeningPass(Registry);
109   initializeMVELaneInterleavingPass(Registry);
110 }
111 
112 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
113   if (TT.isOSBinFormatMachO())
114     return std::make_unique<TargetLoweringObjectFileMachO>();
115   if (TT.isOSWindows())
116     return std::make_unique<TargetLoweringObjectFileCOFF>();
117   return std::make_unique<ARMElfTargetObjectFile>();
118 }
119 
120 static ARMBaseTargetMachine::ARMABI
121 computeTargetABI(const Triple &TT, StringRef CPU,
122                  const TargetOptions &Options) {
123   StringRef ABIName = Options.MCOptions.getABIName();
124 
125   if (ABIName.empty())
126     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
127 
128   if (ABIName == "aapcs16")
129     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
130   else if (ABIName.startswith("aapcs"))
131     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
132   else if (ABIName.startswith("apcs"))
133     return ARMBaseTargetMachine::ARM_ABI_APCS;
134 
135   llvm_unreachable("Unhandled/unknown ABI Name!");
136   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
137 }
138 
139 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
140                                      const TargetOptions &Options,
141                                      bool isLittle) {
142   auto ABI = computeTargetABI(TT, CPU, Options);
143   std::string Ret;
144 
145   if (isLittle)
146     // Little endian.
147     Ret += "e";
148   else
149     // Big endian.
150     Ret += "E";
151 
152   Ret += DataLayout::getManglingComponent(TT);
153 
154   // Pointers are 32 bits and aligned to 32 bits.
155   Ret += "-p:32:32";
156 
157   // Function pointers are aligned to 8 bits (because the LSB stores the
158   // ARM/Thumb state).
159   Ret += "-Fi8";
160 
161   // ABIs other than APCS have 64 bit integers with natural alignment.
162   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
163     Ret += "-i64:64";
164 
165   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
166   // bits, others to 64 bits. We always try to align to 64 bits.
167   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
168     Ret += "-f64:32:64";
169 
170   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
171   // to 64. We always ty to give them natural alignment.
172   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
173     Ret += "-v64:32:64-v128:32:128";
174   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
175     Ret += "-v128:64:128";
176 
177   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
178   // particular hardware support on 32-bit ARM).
179   Ret += "-a:0:32";
180 
181   // Integer registers are 32 bits.
182   Ret += "-n32";
183 
184   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
185   // aligned everywhere else.
186   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
187     Ret += "-S128";
188   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
189     Ret += "-S64";
190   else
191     Ret += "-S32";
192 
193   return Ret;
194 }
195 
196 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
197                                            Optional<Reloc::Model> RM) {
198   if (!RM.hasValue())
199     // Default relocation model on Darwin is PIC.
200     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
201 
202   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
203     assert(TT.isOSBinFormatELF() &&
204            "ROPI/RWPI currently only supported for ELF");
205 
206   // DynamicNoPIC is only used on darwin.
207   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
208     return Reloc::Static;
209 
210   return *RM;
211 }
212 
213 /// Create an ARM architecture model.
214 ///
215 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
216                                            StringRef CPU, StringRef FS,
217                                            const TargetOptions &Options,
218                                            Optional<Reloc::Model> RM,
219                                            Optional<CodeModel::Model> CM,
220                                            CodeGenOpt::Level OL, bool isLittle)
221     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
222                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
223                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
224       TargetABI(computeTargetABI(TT, CPU, Options)),
225       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
226 
227   // Default to triple-appropriate float ABI
228   if (Options.FloatABIType == FloatABI::Default) {
229     if (isTargetHardFloat())
230       this->Options.FloatABIType = FloatABI::Hard;
231     else
232       this->Options.FloatABIType = FloatABI::Soft;
233   }
234 
235   // Default to triple-appropriate EABI
236   if (Options.EABIVersion == EABI::Default ||
237       Options.EABIVersion == EABI::Unknown) {
238     // musl is compatible with glibc with regard to EABI version
239     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
240          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
241          TargetTriple.getEnvironment() == Triple::MuslEABI ||
242          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
243         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
244       this->Options.EABIVersion = EABI::GNU;
245     else
246       this->Options.EABIVersion = EABI::EABI5;
247   }
248 
249   if (TT.isOSBinFormatMachO()) {
250     this->Options.TrapUnreachable = true;
251     this->Options.NoTrapAfterNoreturn = true;
252   }
253 
254   // ARM supports the debug entry values.
255   setSupportsDebugEntryValues(true);
256 
257   initAsmInfo();
258 
259   // ARM supports the MachineOutliner.
260   setMachineOutliner(true);
261   setSupportsDefaultOutlining(true);
262 }
263 
264 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
265 
266 const ARMSubtarget *
267 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
268   Attribute CPUAttr = F.getFnAttribute("target-cpu");
269   Attribute FSAttr = F.getFnAttribute("target-features");
270 
271   std::string CPU =
272       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
273   std::string FS =
274       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
275 
276   // FIXME: This is related to the code below to reset the target options,
277   // we need to know whether or not the soft float flag is set on the
278   // function before we can generate a subtarget. We also need to use
279   // it as a key for the subtarget since that can be the only difference
280   // between two functions.
281   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
282   // If the soft float attribute is set on the function turn on the soft float
283   // subtarget feature.
284   if (SoftFloat)
285     FS += FS.empty() ? "+soft-float" : ",+soft-float";
286 
287   // Use the optminsize to identify the subtarget, but don't use it in the
288   // feature string.
289   std::string Key = CPU + FS;
290   if (F.hasMinSize())
291     Key += "+minsize";
292 
293   auto &I = SubtargetMap[Key];
294   if (!I) {
295     // This needs to be done before we create a new subtarget since any
296     // creation will depend on the TM and the code generation flags on the
297     // function that reside in TargetOptions.
298     resetTargetOptions(F);
299     I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
300                                         F.hasMinSize());
301 
302     if (!I->isThumb() && !I->hasARMOps())
303       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
304           "instructions, but the target does not support ARM mode execution.");
305   }
306 
307   return I.get();
308 }
309 
310 TargetTransformInfo
311 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
312   return TargetTransformInfo(ARMTTIImpl(this, F));
313 }
314 
315 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
316                                        StringRef CPU, StringRef FS,
317                                        const TargetOptions &Options,
318                                        Optional<Reloc::Model> RM,
319                                        Optional<CodeModel::Model> CM,
320                                        CodeGenOpt::Level OL, bool JIT)
321     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
322 
323 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
324                                        StringRef CPU, StringRef FS,
325                                        const TargetOptions &Options,
326                                        Optional<Reloc::Model> RM,
327                                        Optional<CodeModel::Model> CM,
328                                        CodeGenOpt::Level OL, bool JIT)
329     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
330 
331 namespace {
332 
333 /// ARM Code Generator Pass Configuration Options.
334 class ARMPassConfig : public TargetPassConfig {
335 public:
336   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
337       : TargetPassConfig(TM, PM) {}
338 
339   ARMBaseTargetMachine &getARMTargetMachine() const {
340     return getTM<ARMBaseTargetMachine>();
341   }
342 
343   ScheduleDAGInstrs *
344   createMachineScheduler(MachineSchedContext *C) const override {
345     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
346     // add DAG Mutations here.
347     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
348     if (ST.hasFusion())
349       DAG->addMutation(createARMMacroFusionDAGMutation());
350     return DAG;
351   }
352 
353   ScheduleDAGInstrs *
354   createPostMachineScheduler(MachineSchedContext *C) const override {
355     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
356     // add DAG Mutations here.
357     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
358     if (ST.hasFusion())
359       DAG->addMutation(createARMMacroFusionDAGMutation());
360     return DAG;
361   }
362 
363   void addIRPasses() override;
364   void addCodeGenPrepare() override;
365   bool addPreISel() override;
366   bool addInstSelector() override;
367   bool addIRTranslator() override;
368   bool addLegalizeMachineIR() override;
369   bool addRegBankSelect() override;
370   bool addGlobalInstructionSelect() override;
371   void addPreRegAlloc() override;
372   void addPreSched2() override;
373   void addPreEmitPass() override;
374   void addPreEmitPass2() override;
375 
376   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
377 };
378 
379 class ARMExecutionDomainFix : public ExecutionDomainFix {
380 public:
381   static char ID;
382   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
383   StringRef getPassName() const override {
384     return "ARM Execution Domain Fix";
385   }
386 };
387 char ARMExecutionDomainFix::ID;
388 
389 } // end anonymous namespace
390 
391 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
392   "ARM Execution Domain Fix", false, false)
393 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
394 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
395   "ARM Execution Domain Fix", false, false)
396 
397 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
398   return new ARMPassConfig(*this, PM);
399 }
400 
401 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
402   return getStandardCSEConfigForOpt(TM->getOptLevel());
403 }
404 
405 void ARMPassConfig::addIRPasses() {
406   if (TM->Options.ThreadModel == ThreadModel::Single)
407     addPass(createLowerAtomicPass());
408   else
409     addPass(createAtomicExpandPass());
410 
411   // Cmpxchg instructions are often used with a subsequent comparison to
412   // determine whether it succeeded. We can exploit existing control-flow in
413   // ldrex/strex loops to simplify this, but it needs tidying up.
414   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
415     addPass(createCFGSimplificationPass(
416         SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
417         [this](const Function &F) {
418           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
419           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
420         }));
421 
422   addPass(createMVEGatherScatterLoweringPass());
423   addPass(createMVELaneInterleavingPass());
424 
425   TargetPassConfig::addIRPasses();
426 
427   // Run the parallel DSP pass.
428   if (getOptLevel() == CodeGenOpt::Aggressive)
429     addPass(createARMParallelDSPPass());
430 
431   // Match interleaved memory accesses to ldN/stN intrinsics.
432   if (TM->getOptLevel() != CodeGenOpt::None)
433     addPass(createInterleavedAccessPass());
434 
435   // Add Control Flow Guard checks.
436   if (TM->getTargetTriple().isOSWindows())
437     addPass(createCFGuardCheckPass());
438 
439   if (TM->Options.JMCInstrument)
440     addPass(createJMCInstrumenterPass());
441 }
442 
443 void ARMPassConfig::addCodeGenPrepare() {
444   if (getOptLevel() != CodeGenOpt::None)
445     addPass(createTypePromotionPass());
446   TargetPassConfig::addCodeGenPrepare();
447 }
448 
449 bool ARMPassConfig::addPreISel() {
450   if ((TM->getOptLevel() != CodeGenOpt::None &&
451        EnableGlobalMerge == cl::BOU_UNSET) ||
452       EnableGlobalMerge == cl::BOU_TRUE) {
453     // FIXME: This is using the thumb1 only constant value for
454     // maximal global offset for merging globals. We may want
455     // to look into using the old value for non-thumb1 code of
456     // 4095 based on the TargetMachine, but this starts to become
457     // tricky when doing code gen per function.
458     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
459                                (EnableGlobalMerge == cl::BOU_UNSET);
460     // Merging of extern globals is enabled by default on non-Mach-O as we
461     // expect it to be generally either beneficial or harmless. On Mach-O it
462     // is disabled as we emit the .subsections_via_symbols directive which
463     // means that merging extern globals is not safe.
464     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
465     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
466                                   MergeExternalByDefault));
467   }
468 
469   if (TM->getOptLevel() != CodeGenOpt::None) {
470     addPass(createHardwareLoopsPass());
471     addPass(createMVETailPredicationPass());
472     // FIXME: IR passes can delete address-taken basic blocks, deleting
473     // corresponding blockaddresses. ARMConstantPoolConstant holds references to
474     // address-taken basic blocks which can be invalidated if the function
475     // containing the blockaddress has already been codegen'd and the basic
476     // block is removed. Work around this by forcing all IR passes to run before
477     // any ISel takes place. We should have a more principled way of handling
478     // this. See D99707 for more details.
479     addPass(createBarrierNoopPass());
480   }
481 
482   return false;
483 }
484 
485 bool ARMPassConfig::addInstSelector() {
486   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
487   return false;
488 }
489 
490 bool ARMPassConfig::addIRTranslator() {
491   addPass(new IRTranslator(getOptLevel()));
492   return false;
493 }
494 
495 bool ARMPassConfig::addLegalizeMachineIR() {
496   addPass(new Legalizer());
497   return false;
498 }
499 
500 bool ARMPassConfig::addRegBankSelect() {
501   addPass(new RegBankSelect());
502   return false;
503 }
504 
505 bool ARMPassConfig::addGlobalInstructionSelect() {
506   addPass(new InstructionSelect(getOptLevel()));
507   return false;
508 }
509 
510 void ARMPassConfig::addPreRegAlloc() {
511   if (getOptLevel() != CodeGenOpt::None) {
512     addPass(createMVETPAndVPTOptimisationsPass());
513 
514     addPass(createMLxExpansionPass());
515 
516     if (EnableARMLoadStoreOpt)
517       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
518 
519     if (!DisableA15SDOptimization)
520       addPass(createA15SDOptimizerPass());
521   }
522 }
523 
524 void ARMPassConfig::addPreSched2() {
525   if (getOptLevel() != CodeGenOpt::None) {
526     if (EnableARMLoadStoreOpt)
527       addPass(createARMLoadStoreOptimizationPass());
528 
529     addPass(new ARMExecutionDomainFix());
530     addPass(createBreakFalseDeps());
531   }
532 
533   // Expand some pseudo instructions into multiple instructions to allow
534   // proper scheduling.
535   addPass(createARMExpandPseudoPass());
536 
537   if (getOptLevel() != CodeGenOpt::None) {
538     // When optimising for size, always run the Thumb2SizeReduction pass before
539     // IfConversion. Otherwise, check whether IT blocks are restricted
540     // (e.g. in v8, IfConversion depends on Thumb instruction widths)
541     addPass(createThumb2SizeReductionPass([this](const Function &F) {
542       return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
543              this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
544     }));
545 
546     addPass(createIfConverter([](const MachineFunction &MF) {
547       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
548     }));
549   }
550   addPass(createThumb2ITBlockPass());
551 
552   // Add both scheduling passes to give the subtarget an opportunity to pick
553   // between them.
554   if (getOptLevel() != CodeGenOpt::None) {
555     addPass(&PostMachineSchedulerID);
556     addPass(&PostRASchedulerID);
557   }
558 
559   addPass(createMVEVPTBlockPass());
560   addPass(createARMIndirectThunks());
561   addPass(createARMSLSHardeningPass());
562 }
563 
564 void ARMPassConfig::addPreEmitPass() {
565   addPass(createThumb2SizeReductionPass());
566 
567   // Constant island pass work on unbundled instructions.
568   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
569     return MF.getSubtarget<ARMSubtarget>().isThumb2();
570   }));
571 
572   // Don't optimize barriers or block placement at -O0.
573   if (getOptLevel() != CodeGenOpt::None) {
574     addPass(createARMBlockPlacementPass());
575     addPass(createARMOptimizeBarriersPass());
576   }
577 }
578 
579 void ARMPassConfig::addPreEmitPass2() {
580   addPass(createARMBranchTargetsPass());
581   addPass(createARMConstantIslandPass());
582   addPass(createARMLowOverheadLoopsPass());
583 
584   if (TM->getTargetTriple().isOSWindows()) {
585     // Identify valid longjmp targets for Windows Control Flow Guard.
586     addPass(createCFGuardLongjmpPass());
587     // Identify valid eh continuation targets for Windows EHCont Guard.
588     addPass(createEHContGuardCatchretPass());
589   }
590 }
591