1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMTargetMachine.h"
14 #include "ARMFrameLowering.h"
15 #include "ARM.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Target/TargetRegistry.h"
22 using namespace llvm;
23 
24 extern "C" void LLVMInitializeARMTarget() {
25   // Register the target.
26   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
27   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
28 }
29 
30 /// TargetMachine ctor - Create an ARM architecture model.
31 ///
32 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
33                                            StringRef CPU, StringRef FS,
34                                            Reloc::Model RM, CodeModel::Model CM)
35   : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
36     Subtarget(TT, CPU, FS),
37     JITInfo(),
38     InstrItins(Subtarget.getInstrItineraryData()) {
39   // Default to soft float ABI
40   if (FloatABIType == FloatABI::Default)
41     FloatABIType = FloatABI::Soft;
42 }
43 
44 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
45                                    StringRef CPU, StringRef FS,
46                                    Reloc::Model RM, CodeModel::Model CM)
47   : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget),
48     DataLayout(Subtarget.isAPCS_ABI() ?
49                std::string("e-p:32:32-f64:32:64-i64:32:64-"
50                            "v128:32:128-v64:32:64-n32") :
51                std::string("e-p:32:32-f64:64:64-i64:64:64-"
52                            "v128:64:128-v64:64:64-n32")),
53     ELFWriterInfo(*this),
54     TLInfo(*this),
55     TSInfo(*this),
56     FrameLowering(Subtarget) {
57   if (!Subtarget.hasARMOps())
58     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
59                        "support ARM mode execution!");
60 }
61 
62 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
63                                        StringRef CPU, StringRef FS,
64                                        Reloc::Model RM, CodeModel::Model CM)
65   : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM),
66     InstrInfo(Subtarget.hasThumb2()
67               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
68               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
69     DataLayout(Subtarget.isAPCS_ABI() ?
70                std::string("e-p:32:32-f64:32:64-i64:32:64-"
71                            "i16:16:32-i8:8:32-i1:8:32-"
72                            "v128:32:128-v64:32:64-a:0:32-n32") :
73                std::string("e-p:32:32-f64:64:64-i64:64:64-"
74                            "i16:16:32-i8:8:32-i1:8:32-"
75                            "v128:64:128-v64:64:64-a:0:32-n32")),
76     ELFWriterInfo(*this),
77     TLInfo(*this),
78     TSInfo(*this),
79     FrameLowering(Subtarget.hasThumb2()
80               ? new ARMFrameLowering(Subtarget)
81               : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
82 }
83 
84 // Pass Pipeline Configuration
85 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
86                                       CodeGenOpt::Level OptLevel) {
87   if (OptLevel != CodeGenOpt::None)
88     PM.add(createARMGlobalMergePass(getTargetLowering()));
89 
90   return false;
91 }
92 
93 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
94                                            CodeGenOpt::Level OptLevel) {
95   PM.add(createARMISelDag(*this, OptLevel));
96   return false;
97 }
98 
99 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
100                                           CodeGenOpt::Level OptLevel) {
101   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
102   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
103     PM.add(createARMLoadStoreOptimizationPass(true));
104   if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
105     PM.add(createMLxExpansionPass());
106 
107   return true;
108 }
109 
110 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
111                                         CodeGenOpt::Level OptLevel) {
112   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
113   if (OptLevel != CodeGenOpt::None) {
114     if (!Subtarget.isThumb1Only())
115       PM.add(createARMLoadStoreOptimizationPass());
116     if (Subtarget.hasNEON())
117       PM.add(createNEONMoveFixPass());
118   }
119 
120   // Expand some pseudo instructions into multiple instructions to allow
121   // proper scheduling.
122   PM.add(createARMExpandPseudoPass());
123 
124   if (OptLevel != CodeGenOpt::None) {
125     if (!Subtarget.isThumb1Only())
126       PM.add(createIfConverterPass());
127   }
128   if (Subtarget.isThumb2())
129     PM.add(createThumb2ITBlockPass());
130 
131   return true;
132 }
133 
134 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
135                                           CodeGenOpt::Level OptLevel) {
136   if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
137     PM.add(createThumb2SizeReductionPass());
138 
139   PM.add(createARMConstantIslandPass());
140   return true;
141 }
142 
143 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
144                                           CodeGenOpt::Level OptLevel,
145                                           JITCodeEmitter &JCE) {
146   // Machine code emitter pass for ARM.
147   PM.add(createARMJITCodeEmitterPass(*this, JCE));
148   return false;
149 }
150