1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMTargetMachine.h" 14 #include "ARMFrameLowering.h" 15 #include "ARM.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/CodeGen/Passes.h" 18 #include "llvm/MC/MCAsmInfo.h" 19 #include "llvm/Support/CommandLine.h" 20 #include "llvm/Support/FormattedStream.h" 21 #include "llvm/Support/TargetRegistry.h" 22 #include "llvm/Target/TargetOptions.h" 23 #include "llvm/Transforms/Scalar.h" 24 using namespace llvm; 25 26 static cl::opt<bool> 27 EnableGlobalMerge("global-merge", cl::Hidden, 28 cl::desc("Enable global merge pass"), 29 cl::init(true)); 30 31 extern "C" void LLVMInitializeARMTarget() { 32 // Register the target. 33 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget); 34 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget); 35 } 36 37 38 /// TargetMachine ctor - Create an ARM architecture model. 39 /// 40 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, 41 StringRef CPU, StringRef FS, 42 const TargetOptions &Options, 43 Reloc::Model RM, CodeModel::Model CM, 44 CodeGenOpt::Level OL) 45 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 46 Subtarget(TT, CPU, FS), 47 JITInfo(), 48 InstrItins(Subtarget.getInstrItineraryData()) { 49 // Default to soft float ABI 50 if (Options.FloatABIType == FloatABI::Default) 51 this->Options.FloatABIType = FloatABI::Soft; 52 } 53 54 void ARMTargetMachine::anchor() { } 55 56 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, 57 StringRef CPU, StringRef FS, 58 const TargetOptions &Options, 59 Reloc::Model RM, CodeModel::Model CM, 60 CodeGenOpt::Level OL) 61 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 62 InstrInfo(Subtarget), 63 DataLayout(Subtarget.isAPCS_ABI() ? 64 std::string("e-p:32:32-f64:32:64-i64:32:64-" 65 "v128:32:128-v64:32:64-n32-S32") : 66 Subtarget.isAAPCS_ABI() ? 67 std::string("e-p:32:32-f64:64:64-i64:64:64-" 68 "v128:64:128-v64:64:64-n32-S64") : 69 std::string("e-p:32:32-f64:64:64-i64:64:64-" 70 "v128:64:128-v64:64:64-n32-S32")), 71 ELFWriterInfo(*this), 72 TLInfo(*this), 73 TSInfo(*this), 74 FrameLowering(Subtarget) { 75 if (!Subtarget.hasARMOps()) 76 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " 77 "support ARM mode execution!"); 78 } 79 80 void ThumbTargetMachine::anchor() { } 81 82 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, 83 StringRef CPU, StringRef FS, 84 const TargetOptions &Options, 85 Reloc::Model RM, CodeModel::Model CM, 86 CodeGenOpt::Level OL) 87 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 88 InstrInfo(Subtarget.hasThumb2() 89 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) 90 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), 91 DataLayout(Subtarget.isAPCS_ABI() ? 92 std::string("e-p:32:32-f64:32:64-i64:32:64-" 93 "i16:16:32-i8:8:32-i1:8:32-" 94 "v128:32:128-v64:32:64-a:0:32-n32-S32") : 95 Subtarget.isAAPCS_ABI() ? 96 std::string("e-p:32:32-f64:64:64-i64:64:64-" 97 "i16:16:32-i8:8:32-i1:8:32-" 98 "v128:64:128-v64:64:64-a:0:32-n32-S64") : 99 std::string("e-p:32:32-f64:64:64-i64:64:64-" 100 "i16:16:32-i8:8:32-i1:8:32-" 101 "v128:64:128-v64:64:64-a:0:32-n32-S32")), 102 ELFWriterInfo(*this), 103 TLInfo(*this), 104 TSInfo(*this), 105 FrameLowering(Subtarget.hasThumb2() 106 ? new ARMFrameLowering(Subtarget) 107 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) { 108 } 109 110 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM) { 111 if (getOptLevel() != CodeGenOpt::None && EnableGlobalMerge) 112 PM.add(createGlobalMergePass(getTargetLowering())); 113 114 return false; 115 } 116 117 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM) { 118 PM.add(createARMISelDag(*this, getOptLevel())); 119 return false; 120 } 121 122 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM) { 123 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 124 if (getOptLevel() != CodeGenOpt::None && !Subtarget.isThumb1Only()) 125 PM.add(createARMLoadStoreOptimizationPass(true)); 126 if (getOptLevel() != CodeGenOpt::None && Subtarget.isCortexA9()) 127 PM.add(createMLxExpansionPass()); 128 return true; 129 } 130 131 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM) { 132 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 133 if (getOptLevel() != CodeGenOpt::None) { 134 if (!Subtarget.isThumb1Only()) 135 PM.add(createARMLoadStoreOptimizationPass()); 136 if (Subtarget.hasNEON()) 137 PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass)); 138 } 139 140 // Expand some pseudo instructions into multiple instructions to allow 141 // proper scheduling. 142 PM.add(createARMExpandPseudoPass()); 143 144 if (getOptLevel() != CodeGenOpt::None) { 145 if (!Subtarget.isThumb1Only()) 146 PM.add(createIfConverterPass()); 147 } 148 if (Subtarget.isThumb2()) 149 PM.add(createThumb2ITBlockPass()); 150 151 return true; 152 } 153 154 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM) { 155 if (Subtarget.isThumb2()) { 156 if (!Subtarget.prefers32BitThumb()) 157 PM.add(createThumb2SizeReductionPass()); 158 159 // Constant island pass work on unbundled instructions. 160 PM.add(createUnpackMachineBundlesPass()); 161 } 162 163 PM.add(createARMConstantIslandPass()); 164 165 return true; 166 } 167 168 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 169 JITCodeEmitter &JCE) { 170 // Machine code emitter pass for ARM. 171 PM.add(createARMJITCodeEmitterPass(*this, JCE)); 172 return false; 173 } 174