1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "MCTargetDesc/ARMMCTargetDesc.h"
19 #include "TargetInfo/ARMTargetInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/ExecutionDomainFix.h"
26 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/TargetParser.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include "llvm/Transforms/Scalar.h"
51 #include <cassert>
52 #include <memory>
53 #include <string>
54 
55 using namespace llvm;
56 
57 static cl::opt<bool>
58 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
59                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
60                    cl::init(false));
61 
62 static cl::opt<bool>
63 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
64                  cl::desc("Run SimplifyCFG after expanding atomic operations"
65                           " to make use of cmpxchg flow-based information"),
66                  cl::init(true));
67 
68 static cl::opt<bool>
69 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
70                       cl::desc("Enable ARM load/store optimization pass"),
71                       cl::init(true));
72 
73 // FIXME: Unify control over GlobalMerge.
74 static cl::opt<cl::boolOrDefault>
75 EnableGlobalMerge("arm-global-merge", cl::Hidden,
76                   cl::desc("Enable the global merge pass"));
77 
78 namespace llvm {
79   void initializeARMExecutionDomainFixPass(PassRegistry&);
80 }
81 
82 extern "C" void LLVMInitializeARMTarget() {
83   // Register the target.
84   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
85   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
86   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
87   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
88 
89   PassRegistry &Registry = *PassRegistry::getPassRegistry();
90   initializeGlobalISel(Registry);
91   initializeARMLoadStoreOptPass(Registry);
92   initializeARMPreAllocLoadStoreOptPass(Registry);
93   initializeARMParallelDSPPass(Registry);
94   initializeARMCodeGenPreparePass(Registry);
95   initializeARMConstantIslandsPass(Registry);
96   initializeARMExecutionDomainFixPass(Registry);
97   initializeARMExpandPseudoPass(Registry);
98   initializeThumb2SizeReducePass(Registry);
99   initializeMVEVPTBlockPass(Registry);
100   initializeMVETailPredicationPass(Registry);
101   initializeARMLowOverheadLoopsPass(Registry);
102 }
103 
104 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
105   if (TT.isOSBinFormatMachO())
106     return std::make_unique<TargetLoweringObjectFileMachO>();
107   if (TT.isOSWindows())
108     return std::make_unique<TargetLoweringObjectFileCOFF>();
109   return std::make_unique<ARMElfTargetObjectFile>();
110 }
111 
112 static ARMBaseTargetMachine::ARMABI
113 computeTargetABI(const Triple &TT, StringRef CPU,
114                  const TargetOptions &Options) {
115   StringRef ABIName = Options.MCOptions.getABIName();
116 
117   if (ABIName.empty())
118     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
119 
120   if (ABIName == "aapcs16")
121     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
122   else if (ABIName.startswith("aapcs"))
123     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
124   else if (ABIName.startswith("apcs"))
125     return ARMBaseTargetMachine::ARM_ABI_APCS;
126 
127   llvm_unreachable("Unhandled/unknown ABI Name!");
128   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
129 }
130 
131 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
132                                      const TargetOptions &Options,
133                                      bool isLittle) {
134   auto ABI = computeTargetABI(TT, CPU, Options);
135   std::string Ret;
136 
137   if (isLittle)
138     // Little endian.
139     Ret += "e";
140   else
141     // Big endian.
142     Ret += "E";
143 
144   Ret += DataLayout::getManglingComponent(TT);
145 
146   // Pointers are 32 bits and aligned to 32 bits.
147   Ret += "-p:32:32";
148 
149   // Function pointers are aligned to 8 bits (because the LSB stores the
150   // ARM/Thumb state).
151   Ret += "-Fi8";
152 
153   // ABIs other than APCS have 64 bit integers with natural alignment.
154   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
155     Ret += "-i64:64";
156 
157   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
158   // bits, others to 64 bits. We always try to align to 64 bits.
159   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
160     Ret += "-f64:32:64";
161 
162   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
163   // to 64. We always ty to give them natural alignment.
164   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
165     Ret += "-v64:32:64-v128:32:128";
166   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
167     Ret += "-v128:64:128";
168 
169   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
170   // particular hardware support on 32-bit ARM).
171   Ret += "-a:0:32";
172 
173   // Integer registers are 32 bits.
174   Ret += "-n32";
175 
176   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
177   // aligned everywhere else.
178   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
179     Ret += "-S128";
180   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
181     Ret += "-S64";
182   else
183     Ret += "-S32";
184 
185   return Ret;
186 }
187 
188 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
189                                            Optional<Reloc::Model> RM) {
190   if (!RM.hasValue())
191     // Default relocation model on Darwin is PIC.
192     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
193 
194   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
195     assert(TT.isOSBinFormatELF() &&
196            "ROPI/RWPI currently only supported for ELF");
197 
198   // DynamicNoPIC is only used on darwin.
199   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
200     return Reloc::Static;
201 
202   return *RM;
203 }
204 
205 /// Create an ARM architecture model.
206 ///
207 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
208                                            StringRef CPU, StringRef FS,
209                                            const TargetOptions &Options,
210                                            Optional<Reloc::Model> RM,
211                                            Optional<CodeModel::Model> CM,
212                                            CodeGenOpt::Level OL, bool isLittle)
213     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
214                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
215                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
216       TargetABI(computeTargetABI(TT, CPU, Options)),
217       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
218 
219   // Default to triple-appropriate float ABI
220   if (Options.FloatABIType == FloatABI::Default) {
221     if (isTargetHardFloat())
222       this->Options.FloatABIType = FloatABI::Hard;
223     else
224       this->Options.FloatABIType = FloatABI::Soft;
225   }
226 
227   // Default to triple-appropriate EABI
228   if (Options.EABIVersion == EABI::Default ||
229       Options.EABIVersion == EABI::Unknown) {
230     // musl is compatible with glibc with regard to EABI version
231     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
232          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
233          TargetTriple.getEnvironment() == Triple::MuslEABI ||
234          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
235         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
236       this->Options.EABIVersion = EABI::GNU;
237     else
238       this->Options.EABIVersion = EABI::EABI5;
239   }
240 
241   if (TT.isOSBinFormatMachO()) {
242     this->Options.TrapUnreachable = true;
243     this->Options.NoTrapAfterNoreturn = true;
244   }
245 
246   initAsmInfo();
247 }
248 
249 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
250 
251 const ARMSubtarget *
252 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
253   Attribute CPUAttr = F.getFnAttribute("target-cpu");
254   Attribute FSAttr = F.getFnAttribute("target-features");
255 
256   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
257                         ? CPUAttr.getValueAsString().str()
258                         : TargetCPU;
259   std::string FS = !FSAttr.hasAttribute(Attribute::None)
260                        ? FSAttr.getValueAsString().str()
261                        : TargetFS;
262 
263   // FIXME: This is related to the code below to reset the target options,
264   // we need to know whether or not the soft float flag is set on the
265   // function before we can generate a subtarget. We also need to use
266   // it as a key for the subtarget since that can be the only difference
267   // between two functions.
268   bool SoftFloat =
269       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
270   // If the soft float attribute is set on the function turn on the soft float
271   // subtarget feature.
272   if (SoftFloat)
273     FS += FS.empty() ? "+soft-float" : ",+soft-float";
274 
275   // Use the optminsize to identify the subtarget, but don't use it in the
276   // feature string.
277   std::string Key = CPU + FS;
278   if (F.hasMinSize())
279     Key += "+minsize";
280 
281   auto &I = SubtargetMap[Key];
282   if (!I) {
283     // This needs to be done before we create a new subtarget since any
284     // creation will depend on the TM and the code generation flags on the
285     // function that reside in TargetOptions.
286     resetTargetOptions(F);
287     I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
288                                         F.hasMinSize());
289 
290     if (!I->isThumb() && !I->hasARMOps())
291       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
292           "instructions, but the target does not support ARM mode execution.");
293   }
294 
295   return I.get();
296 }
297 
298 TargetTransformInfo
299 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) {
300   return TargetTransformInfo(ARMTTIImpl(this, F));
301 }
302 
303 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
304                                        StringRef CPU, StringRef FS,
305                                        const TargetOptions &Options,
306                                        Optional<Reloc::Model> RM,
307                                        Optional<CodeModel::Model> CM,
308                                        CodeGenOpt::Level OL, bool JIT)
309     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
310 
311 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
312                                        StringRef CPU, StringRef FS,
313                                        const TargetOptions &Options,
314                                        Optional<Reloc::Model> RM,
315                                        Optional<CodeModel::Model> CM,
316                                        CodeGenOpt::Level OL, bool JIT)
317     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
318 
319 namespace {
320 
321 /// ARM Code Generator Pass Configuration Options.
322 class ARMPassConfig : public TargetPassConfig {
323 public:
324   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
325       : TargetPassConfig(TM, PM) {}
326 
327   ARMBaseTargetMachine &getARMTargetMachine() const {
328     return getTM<ARMBaseTargetMachine>();
329   }
330 
331   ScheduleDAGInstrs *
332   createMachineScheduler(MachineSchedContext *C) const override {
333     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
334     // add DAG Mutations here.
335     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
336     if (ST.hasFusion())
337       DAG->addMutation(createARMMacroFusionDAGMutation());
338     return DAG;
339   }
340 
341   ScheduleDAGInstrs *
342   createPostMachineScheduler(MachineSchedContext *C) const override {
343     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
344     // add DAG Mutations here.
345     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
346     if (ST.hasFusion())
347       DAG->addMutation(createARMMacroFusionDAGMutation());
348     return DAG;
349   }
350 
351   void addIRPasses() override;
352   void addCodeGenPrepare() override;
353   bool addPreISel() override;
354   bool addInstSelector() override;
355   bool addIRTranslator() override;
356   bool addLegalizeMachineIR() override;
357   bool addRegBankSelect() override;
358   bool addGlobalInstructionSelect() override;
359   void addPreRegAlloc() override;
360   void addPreSched2() override;
361   void addPreEmitPass() override;
362 
363   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
364 };
365 
366 class ARMExecutionDomainFix : public ExecutionDomainFix {
367 public:
368   static char ID;
369   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
370   StringRef getPassName() const override {
371     return "ARM Execution Domain Fix";
372   }
373 };
374 char ARMExecutionDomainFix::ID;
375 
376 } // end anonymous namespace
377 
378 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
379   "ARM Execution Domain Fix", false, false)
380 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
381 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
382   "ARM Execution Domain Fix", false, false)
383 
384 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
385   return new ARMPassConfig(*this, PM);
386 }
387 
388 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
389   return getStandardCSEConfigForOpt(TM->getOptLevel());
390 }
391 
392 void ARMPassConfig::addIRPasses() {
393   if (TM->Options.ThreadModel == ThreadModel::Single)
394     addPass(createLowerAtomicPass());
395   else
396     addPass(createAtomicExpandPass());
397 
398   // Cmpxchg instructions are often used with a subsequent comparison to
399   // determine whether it succeeded. We can exploit existing control-flow in
400   // ldrex/strex loops to simplify this, but it needs tidying up.
401   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
402     addPass(createCFGSimplificationPass(
403         1, false, false, true, true, [this](const Function &F) {
404           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
405           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
406         }));
407 
408   TargetPassConfig::addIRPasses();
409 
410   // Run the parallel DSP pass.
411   if (getOptLevel() == CodeGenOpt::Aggressive)
412     addPass(createARMParallelDSPPass());
413 
414   // Match interleaved memory accesses to ldN/stN intrinsics.
415   if (TM->getOptLevel() != CodeGenOpt::None)
416     addPass(createInterleavedAccessPass());
417 
418   // Add Control Flow Guard checks.
419   if (TM->getTargetTriple().isOSWindows())
420     addPass(createCFGuardCheckPass());
421 }
422 
423 void ARMPassConfig::addCodeGenPrepare() {
424   if (getOptLevel() != CodeGenOpt::None)
425     addPass(createARMCodeGenPreparePass());
426   TargetPassConfig::addCodeGenPrepare();
427 }
428 
429 bool ARMPassConfig::addPreISel() {
430   if ((TM->getOptLevel() != CodeGenOpt::None &&
431        EnableGlobalMerge == cl::BOU_UNSET) ||
432       EnableGlobalMerge == cl::BOU_TRUE) {
433     // FIXME: This is using the thumb1 only constant value for
434     // maximal global offset for merging globals. We may want
435     // to look into using the old value for non-thumb1 code of
436     // 4095 based on the TargetMachine, but this starts to become
437     // tricky when doing code gen per function.
438     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
439                                (EnableGlobalMerge == cl::BOU_UNSET);
440     // Merging of extern globals is enabled by default on non-Mach-O as we
441     // expect it to be generally either beneficial or harmless. On Mach-O it
442     // is disabled as we emit the .subsections_via_symbols directive which
443     // means that merging extern globals is not safe.
444     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
445     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
446                                   MergeExternalByDefault));
447   }
448 
449   if (TM->getOptLevel() != CodeGenOpt::None) {
450     addPass(createHardwareLoopsPass());
451     addPass(createMVETailPredicationPass());
452   }
453 
454   return false;
455 }
456 
457 bool ARMPassConfig::addInstSelector() {
458   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
459   return false;
460 }
461 
462 bool ARMPassConfig::addIRTranslator() {
463   addPass(new IRTranslator());
464   return false;
465 }
466 
467 bool ARMPassConfig::addLegalizeMachineIR() {
468   addPass(new Legalizer());
469   return false;
470 }
471 
472 bool ARMPassConfig::addRegBankSelect() {
473   addPass(new RegBankSelect());
474   return false;
475 }
476 
477 bool ARMPassConfig::addGlobalInstructionSelect() {
478   addPass(new InstructionSelect());
479   return false;
480 }
481 
482 void ARMPassConfig::addPreRegAlloc() {
483   if (getOptLevel() != CodeGenOpt::None) {
484     addPass(createMLxExpansionPass());
485 
486     if (EnableARMLoadStoreOpt)
487       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
488 
489     if (!DisableA15SDOptimization)
490       addPass(createA15SDOptimizerPass());
491   }
492 }
493 
494 void ARMPassConfig::addPreSched2() {
495   if (getOptLevel() != CodeGenOpt::None) {
496     if (EnableARMLoadStoreOpt)
497       addPass(createARMLoadStoreOptimizationPass());
498 
499     addPass(new ARMExecutionDomainFix());
500     addPass(createBreakFalseDeps());
501   }
502 
503   // Expand some pseudo instructions into multiple instructions to allow
504   // proper scheduling.
505   addPass(createARMExpandPseudoPass());
506 
507   if (getOptLevel() != CodeGenOpt::None) {
508     // in v8, IfConversion depends on Thumb instruction widths
509     addPass(createThumb2SizeReductionPass([this](const Function &F) {
510       return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
511     }));
512 
513     addPass(createIfConverter([](const MachineFunction &MF) {
514       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
515     }));
516   }
517   addPass(createMVEVPTBlockPass());
518   addPass(createThumb2ITBlockPass());
519 
520   // Add both scheduling passes to give the subtarget an opportunity to pick
521   // between them.
522   if (getOptLevel() != CodeGenOpt::None) {
523     addPass(&PostMachineSchedulerID);
524     addPass(&PostRASchedulerID);
525   }
526 }
527 
528 void ARMPassConfig::addPreEmitPass() {
529   addPass(createThumb2SizeReductionPass());
530 
531   // Constant island pass work on unbundled instructions.
532   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
533     return MF.getSubtarget<ARMSubtarget>().isThumb2();
534   }));
535 
536   // Don't optimize barriers at -O0.
537   if (getOptLevel() != CodeGenOpt::None)
538     addPass(createARMOptimizeBarriersPass());
539 
540   addPass(createARMConstantIslandPass());
541   addPass(createARMLowOverheadLoopsPass());
542 
543   // Identify valid longjmp targets for Windows Control Flow Guard.
544   if (TM->getTargetTriple().isOSWindows())
545     addPass(createCFGuardLongjmpPass());
546 }
547