1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMTargetMachine.h" 14 #include "ARMTargetAsmInfo.h" 15 #include "ARMFrameInfo.h" 16 #include "ARM.h" 17 #include "llvm/PassManager.h" 18 #include "llvm/CodeGen/Passes.h" 19 #include "llvm/Support/CommandLine.h" 20 #include "llvm/Support/FormattedStream.h" 21 #include "llvm/Target/TargetOptions.h" 22 #include "llvm/Target/TargetRegistry.h" 23 using namespace llvm; 24 25 static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden, 26 cl::desc("Disable load store optimization pass")); 27 static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden, 28 cl::desc("Disable if-conversion pass")); 29 30 extern "C" void LLVMInitializeARMTarget() { 31 // Register the target. 32 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget); 33 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget); 34 } 35 36 /// TargetMachine ctor - Create an ARM architecture model. 37 /// 38 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, 39 const std::string &TT, 40 const std::string &FS, 41 bool isThumb) 42 : LLVMTargetMachine(T), 43 Subtarget(TT, FS, isThumb), 44 FrameInfo(Subtarget), 45 JITInfo(), 46 InstrItins(Subtarget.getInstrItineraryData()) { 47 DefRelocModel = getRelocationModel(); 48 } 49 50 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, 51 const std::string &FS) 52 : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget), 53 DataLayout(Subtarget.isAPCS_ABI() ? 54 std::string("e-p:32:32-f64:32:32-i64:32:32") : 55 std::string("e-p:32:32-f64:64:64-i64:64:64")), 56 TLInfo(*this) { 57 } 58 59 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, 60 const std::string &FS) 61 : ARMBaseTargetMachine(T, TT, FS, true), 62 DataLayout(Subtarget.isAPCS_ABI() ? 63 std::string("e-p:32:32-f64:32:32-i64:32:32-" 64 "i16:16:32-i8:8:32-i1:8:32-a:0:32") : 65 std::string("e-p:32:32-f64:64:64-i64:64:64-" 66 "i16:16:32-i8:8:32-i1:8:32-a:0:32")), 67 TLInfo(*this) { 68 // Create the approriate type of Thumb InstrInfo 69 if (Subtarget.hasThumb2()) 70 InstrInfo = new Thumb2InstrInfo(Subtarget); 71 else 72 InstrInfo = new Thumb1InstrInfo(Subtarget); 73 } 74 75 76 const TargetAsmInfo *ARMBaseTargetMachine::createTargetAsmInfo() const { 77 switch (Subtarget.TargetType) { 78 default: llvm_unreachable("Unknown ARM subtarget kind"); 79 case ARMSubtarget::isDarwin: 80 return new ARMDarwinTargetAsmInfo(); 81 case ARMSubtarget::isELF: 82 return new ARMELFTargetAsmInfo(); 83 } 84 } 85 86 87 // Pass Pipeline Configuration 88 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM, 89 CodeGenOpt::Level OptLevel) { 90 PM.add(createARMISelDag(*this)); 91 return false; 92 } 93 94 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, 95 CodeGenOpt::Level OptLevel) { 96 // FIXME: temporarily disabling load / store optimization pass for Thumb mode. 97 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb()) 98 PM.add(createARMLoadStoreOptimizationPass(true)); 99 return true; 100 } 101 102 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, 103 CodeGenOpt::Level OptLevel) { 104 // FIXME: temporarily disabling load / store optimization pass for Thumb mode. 105 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb()) 106 PM.add(createARMLoadStoreOptimizationPass()); 107 108 if (OptLevel != CodeGenOpt::None && 109 !DisableIfConversion && !Subtarget.isThumb()) 110 PM.add(createIfConverterPass()); 111 112 if (Subtarget.isThumb2()) 113 PM.add(createThumb2ITBlockPass()); 114 115 PM.add(createARMConstantIslandPass()); 116 return true; 117 } 118 119 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 120 CodeGenOpt::Level OptLevel, 121 MachineCodeEmitter &MCE) { 122 // FIXME: Move this to TargetJITInfo! 123 if (DefRelocModel == Reloc::Default) 124 setRelocationModel(Reloc::Static); 125 126 // Machine code emitter pass for ARM. 127 PM.add(createARMCodeEmitterPass(*this, MCE)); 128 return false; 129 } 130 131 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 132 CodeGenOpt::Level OptLevel, 133 JITCodeEmitter &JCE) { 134 // FIXME: Move this to TargetJITInfo! 135 if (DefRelocModel == Reloc::Default) 136 setRelocationModel(Reloc::Static); 137 138 // Machine code emitter pass for ARM. 139 PM.add(createARMJITCodeEmitterPass(*this, JCE)); 140 return false; 141 } 142 143 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 144 CodeGenOpt::Level OptLevel, 145 ObjectCodeEmitter &OCE) { 146 // FIXME: Move this to TargetJITInfo! 147 if (DefRelocModel == Reloc::Default) 148 setRelocationModel(Reloc::Static); 149 150 // Machine code emitter pass for ARM. 151 PM.add(createARMObjectCodeEmitterPass(*this, OCE)); 152 return false; 153 } 154 155 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, 156 CodeGenOpt::Level OptLevel, 157 MachineCodeEmitter &MCE) { 158 // Machine code emitter pass for ARM. 159 PM.add(createARMCodeEmitterPass(*this, MCE)); 160 return false; 161 } 162 163 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, 164 CodeGenOpt::Level OptLevel, 165 JITCodeEmitter &JCE) { 166 // Machine code emitter pass for ARM. 167 PM.add(createARMJITCodeEmitterPass(*this, JCE)); 168 return false; 169 } 170 171 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, 172 CodeGenOpt::Level OptLevel, 173 ObjectCodeEmitter &OCE) { 174 // Machine code emitter pass for ARM. 175 PM.add(createARMObjectCodeEmitterPass(*this, OCE)); 176 return false; 177 } 178 179