1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMTargetMachine.h" 14 #include "ARMFrameLowering.h" 15 #include "ARM.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/CodeGen/Passes.h" 18 #include "llvm/MC/MCAsmInfo.h" 19 #include "llvm/Support/CommandLine.h" 20 #include "llvm/Support/FormattedStream.h" 21 #include "llvm/Support/TargetRegistry.h" 22 #include "llvm/Target/TargetOptions.h" 23 #include "llvm/Transforms/Scalar.h" 24 using namespace llvm; 25 26 static cl::opt<bool> 27 EnableGlobalMerge("global-merge", cl::Hidden, 28 cl::desc("Enable global merge pass"), 29 cl::init(true)); 30 31 extern "C" void LLVMInitializeARMTarget() { 32 // Register the target. 33 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget); 34 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget); 35 } 36 37 /// TargetMachine ctor - Create an ARM architecture model. 38 /// 39 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, 40 StringRef CPU, StringRef FS, 41 Reloc::Model RM, CodeModel::Model CM, 42 CodeGenOpt::Level OL) 43 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL), 44 Subtarget(TT, CPU, FS), 45 JITInfo(), 46 InstrItins(Subtarget.getInstrItineraryData()) { 47 // Default to soft float ABI 48 if (FloatABIType == FloatABI::Default) 49 FloatABIType = FloatABI::Soft; 50 } 51 52 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, 53 StringRef CPU, StringRef FS, 54 Reloc::Model RM, CodeModel::Model CM, 55 CodeGenOpt::Level OL) 56 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL), InstrInfo(Subtarget), 57 DataLayout(Subtarget.isAPCS_ABI() ? 58 std::string("e-p:32:32-f64:32:64-i64:32:64-" 59 "v128:32:128-v64:32:64-n32-S32") : 60 Subtarget.isAAPCS_ABI() ? 61 std::string("e-p:32:32-f64:64:64-i64:64:64-" 62 "v128:64:128-v64:64:64-n32-S64") : 63 std::string("e-p:32:32-f64:64:64-i64:64:64-" 64 "v128:64:128-v64:64:64-n32-S32")), 65 ELFWriterInfo(*this), 66 TLInfo(*this), 67 TSInfo(*this), 68 FrameLowering(Subtarget) { 69 if (!Subtarget.hasARMOps()) 70 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " 71 "support ARM mode execution!"); 72 } 73 74 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, 75 StringRef CPU, StringRef FS, 76 Reloc::Model RM, CodeModel::Model CM, 77 CodeGenOpt::Level OL) 78 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM, OL), 79 InstrInfo(Subtarget.hasThumb2() 80 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) 81 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), 82 DataLayout(Subtarget.isAPCS_ABI() ? 83 std::string("e-p:32:32-f64:32:64-i64:32:64-" 84 "i16:16:32-i8:8:32-i1:8:32-" 85 "v128:32:128-v64:32:64-a:0:32-n32-S32") : 86 Subtarget.isAAPCS_ABI() ? 87 std::string("e-p:32:32-f64:64:64-i64:64:64-" 88 "i16:16:32-i8:8:32-i1:8:32-" 89 "v128:64:128-v64:64:64-a:0:32-n32-S64") : 90 std::string("e-p:32:32-f64:64:64-i64:64:64-" 91 "i16:16:32-i8:8:32-i1:8:32-" 92 "v128:64:128-v64:64:64-a:0:32-n32-S32")), 93 ELFWriterInfo(*this), 94 TLInfo(*this), 95 TSInfo(*this), 96 FrameLowering(Subtarget.hasThumb2() 97 ? new ARMFrameLowering(Subtarget) 98 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) { 99 } 100 101 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM) { 102 if (getOptLevel() != CodeGenOpt::None && EnableGlobalMerge) 103 PM.add(createGlobalMergePass(getTargetLowering())); 104 105 return false; 106 } 107 108 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM) { 109 PM.add(createARMISelDag(*this, getOptLevel())); 110 return false; 111 } 112 113 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM) { 114 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 115 if (getOptLevel() != CodeGenOpt::None && !Subtarget.isThumb1Only()) 116 PM.add(createARMLoadStoreOptimizationPass(true)); 117 if (getOptLevel() != CodeGenOpt::None && Subtarget.isCortexA9()) 118 PM.add(createMLxExpansionPass()); 119 return true; 120 } 121 122 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM) { 123 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 124 if (getOptLevel() != CodeGenOpt::None) { 125 if (!Subtarget.isThumb1Only()) 126 PM.add(createARMLoadStoreOptimizationPass()); 127 if (Subtarget.hasNEON()) 128 PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass)); 129 } 130 131 // Expand some pseudo instructions into multiple instructions to allow 132 // proper scheduling. 133 PM.add(createARMExpandPseudoPass()); 134 135 if (getOptLevel() != CodeGenOpt::None) { 136 if (!Subtarget.isThumb1Only()) 137 PM.add(createIfConverterPass()); 138 } 139 if (Subtarget.isThumb2()) 140 PM.add(createThumb2ITBlockPass()); 141 142 return true; 143 } 144 145 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM) { 146 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb()) 147 PM.add(createThumb2SizeReductionPass()); 148 149 PM.add(createARMConstantIslandPass()); 150 return true; 151 } 152 153 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 154 JITCodeEmitter &JCE) { 155 // Machine code emitter pass for ARM. 156 PM.add(createARMJITCodeEmitterPass(*this, JCE)); 157 return false; 158 } 159