1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARM.h"
14 #include "ARMFrameLowering.h"
15 #include "ARMTargetMachine.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
27 using namespace llvm;
28 
29 static cl::opt<bool>
30 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
31                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
32                    cl::init(false));
33 
34 static cl::opt<bool>
35 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
36                  cl::desc("Run SimplifyCFG after expanding atomic operations"
37                           " to make use of cmpxchg flow-based information"),
38                  cl::init(true));
39 
40 static cl::opt<bool>
41 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
42                       cl::desc("Enable ARM load/store optimization pass"),
43                       cl::init(true));
44 
45 // FIXME: Unify control over GlobalMerge.
46 static cl::opt<cl::boolOrDefault>
47 EnableGlobalMerge("arm-global-merge", cl::Hidden,
48                   cl::desc("Enable the global merge pass"));
49 
50 extern "C" void LLVMInitializeARMTarget() {
51   // Register the target.
52   RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
53   RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
54   RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
55   RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
56 }
57 
58 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
59   if (TT.isOSBinFormatMachO())
60     return make_unique<TargetLoweringObjectFileMachO>();
61   if (TT.isOSWindows())
62     return make_unique<TargetLoweringObjectFileCOFF>();
63   return make_unique<ARMElfTargetObjectFile>();
64 }
65 
66 static ARMBaseTargetMachine::ARMABI
67 computeTargetABI(const Triple &TT, StringRef CPU,
68                  const TargetOptions &Options) {
69   if (Options.MCOptions.getABIName() == "aapcs16")
70     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
71   else if (Options.MCOptions.getABIName().startswith("aapcs"))
72     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
73   else if (Options.MCOptions.getABIName().startswith("apcs"))
74     return ARMBaseTargetMachine::ARM_ABI_APCS;
75 
76   assert(Options.MCOptions.getABIName().empty() &&
77          "Unknown target-abi option!");
78 
79   ARMBaseTargetMachine::ARMABI TargetABI =
80       ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
81 
82   // FIXME: This is duplicated code from the front end and should be unified.
83   if (TT.isOSBinFormatMachO()) {
84     if (TT.getEnvironment() == llvm::Triple::EABI ||
85         (TT.getOS() == llvm::Triple::UnknownOS && TT.isOSBinFormatMachO()) ||
86         CPU.startswith("cortex-m")) {
87       TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
88     } else if (TT.isWatchABI()) {
89       TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS16;
90     } else {
91       TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
92     }
93   } else if (TT.isOSWindows()) {
94     // FIXME: this is invalid for WindowsCE
95     TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
96   } else {
97     // Select the default based on the platform.
98     switch (TT.getEnvironment()) {
99     case llvm::Triple::Android:
100     case llvm::Triple::GNUEABI:
101     case llvm::Triple::GNUEABIHF:
102     case llvm::Triple::EABIHF:
103     case llvm::Triple::EABI:
104       TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
105       break;
106     case llvm::Triple::GNU:
107       TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
108       break;
109     default:
110       if (TT.isOSNetBSD())
111         TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
112       else
113         TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
114       break;
115     }
116   }
117 
118   return TargetABI;
119 }
120 
121 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
122                                      const TargetOptions &Options,
123                                      bool isLittle) {
124   auto ABI = computeTargetABI(TT, CPU, Options);
125   std::string Ret = "";
126 
127   if (isLittle)
128     // Little endian.
129     Ret += "e";
130   else
131     // Big endian.
132     Ret += "E";
133 
134   Ret += DataLayout::getManglingComponent(TT);
135 
136   // Pointers are 32 bits and aligned to 32 bits.
137   Ret += "-p:32:32";
138 
139   // ABIs other than APCS have 64 bit integers with natural alignment.
140   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
141     Ret += "-i64:64";
142 
143   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
144   // bits, others to 64 bits. We always try to align to 64 bits.
145   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
146     Ret += "-f64:32:64";
147 
148   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
149   // to 64. We always ty to give them natural alignment.
150   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
151     Ret += "-v64:32:64-v128:32:128";
152   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
153     Ret += "-v128:64:128";
154 
155   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
156   // particular hardware support on 32-bit ARM).
157   Ret += "-a:0:32";
158 
159   // Integer registers are 32 bits.
160   Ret += "-n32";
161 
162   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
163   // aligned everywhere else.
164   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
165     Ret += "-S128";
166   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
167     Ret += "-S64";
168   else
169     Ret += "-S32";
170 
171   return Ret;
172 }
173 
174 /// TargetMachine ctor - Create an ARM architecture model.
175 ///
176 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
177                                            StringRef CPU, StringRef FS,
178                                            const TargetOptions &Options,
179                                            Reloc::Model RM, CodeModel::Model CM,
180                                            CodeGenOpt::Level OL, bool isLittle)
181     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
182                         CPU, FS, Options, RM, CM, OL),
183       TargetABI(computeTargetABI(TT, CPU, Options)),
184       TLOF(createTLOF(getTargetTriple())),
185       Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
186 
187   // Default to triple-appropriate float ABI
188   if (Options.FloatABIType == FloatABI::Default)
189     this->Options.FloatABIType =
190         Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
191 
192   // Default to triple-appropriate EABI
193   if (Options.EABIVersion == EABI::Default ||
194       Options.EABIVersion == EABI::Unknown) {
195     if (Subtarget.isTargetGNUAEABI())
196       this->Options.EABIVersion = EABI::GNU;
197     else
198       this->Options.EABIVersion = EABI::EABI5;
199   }
200 }
201 
202 ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
203 
204 const ARMSubtarget *
205 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
206   Attribute CPUAttr = F.getFnAttribute("target-cpu");
207   Attribute FSAttr = F.getFnAttribute("target-features");
208 
209   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
210                         ? CPUAttr.getValueAsString().str()
211                         : TargetCPU;
212   std::string FS = !FSAttr.hasAttribute(Attribute::None)
213                        ? FSAttr.getValueAsString().str()
214                        : TargetFS;
215 
216   // FIXME: This is related to the code below to reset the target options,
217   // we need to know whether or not the soft float flag is set on the
218   // function before we can generate a subtarget. We also need to use
219   // it as a key for the subtarget since that can be the only difference
220   // between two functions.
221   bool SoftFloat =
222       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
223   // If the soft float attribute is set on the function turn on the soft float
224   // subtarget feature.
225   if (SoftFloat)
226     FS += FS.empty() ? "+soft-float" : ",+soft-float";
227 
228   auto &I = SubtargetMap[CPU + FS];
229   if (!I) {
230     // This needs to be done before we create a new subtarget since any
231     // creation will depend on the TM and the code generation flags on the
232     // function that reside in TargetOptions.
233     resetTargetOptions(F);
234     I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
235   }
236   return I.get();
237 }
238 
239 TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
240   return TargetIRAnalysis([this](const Function &F) {
241     return TargetTransformInfo(ARMTTIImpl(this, F));
242   });
243 }
244 
245 void ARMTargetMachine::anchor() {}
246 
247 ARMTargetMachine::ARMTargetMachine(const Target &T, const Triple &TT,
248                                    StringRef CPU, StringRef FS,
249                                    const TargetOptions &Options,
250                                    Reloc::Model RM, CodeModel::Model CM,
251                                    CodeGenOpt::Level OL, bool isLittle)
252     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
253   initAsmInfo();
254   if (!Subtarget.hasARMOps())
255     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
256                        "support ARM mode execution!");
257 }
258 
259 void ARMLETargetMachine::anchor() {}
260 
261 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
262                                        StringRef CPU, StringRef FS,
263                                        const TargetOptions &Options,
264                                        Reloc::Model RM, CodeModel::Model CM,
265                                        CodeGenOpt::Level OL)
266     : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
267 
268 void ARMBETargetMachine::anchor() {}
269 
270 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
271                                        StringRef CPU, StringRef FS,
272                                        const TargetOptions &Options,
273                                        Reloc::Model RM, CodeModel::Model CM,
274                                        CodeGenOpt::Level OL)
275     : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
276 
277 void ThumbTargetMachine::anchor() {}
278 
279 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const Triple &TT,
280                                        StringRef CPU, StringRef FS,
281                                        const TargetOptions &Options,
282                                        Reloc::Model RM, CodeModel::Model CM,
283                                        CodeGenOpt::Level OL, bool isLittle)
284     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
285   initAsmInfo();
286 }
287 
288 void ThumbLETargetMachine::anchor() {}
289 
290 ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, const Triple &TT,
291                                            StringRef CPU, StringRef FS,
292                                            const TargetOptions &Options,
293                                            Reloc::Model RM, CodeModel::Model CM,
294                                            CodeGenOpt::Level OL)
295     : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
296 
297 void ThumbBETargetMachine::anchor() {}
298 
299 ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, const Triple &TT,
300                                            StringRef CPU, StringRef FS,
301                                            const TargetOptions &Options,
302                                            Reloc::Model RM, CodeModel::Model CM,
303                                            CodeGenOpt::Level OL)
304     : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
305 
306 namespace {
307 /// ARM Code Generator Pass Configuration Options.
308 class ARMPassConfig : public TargetPassConfig {
309 public:
310   ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
311     : TargetPassConfig(TM, PM) {}
312 
313   ARMBaseTargetMachine &getARMTargetMachine() const {
314     return getTM<ARMBaseTargetMachine>();
315   }
316 
317   void addIRPasses() override;
318   bool addPreISel() override;
319   bool addInstSelector() override;
320   void addPreRegAlloc() override;
321   void addPreSched2() override;
322   void addPreEmitPass() override;
323 };
324 } // namespace
325 
326 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
327   return new ARMPassConfig(this, PM);
328 }
329 
330 void ARMPassConfig::addIRPasses() {
331   if (TM->Options.ThreadModel == ThreadModel::Single)
332     addPass(createLowerAtomicPass());
333   else
334     addPass(createAtomicExpandPass(TM));
335 
336   // Cmpxchg instructions are often used with a subsequent comparison to
337   // determine whether it succeeded. We can exploit existing control-flow in
338   // ldrex/strex loops to simplify this, but it needs tidying up.
339   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
340     addPass(createCFGSimplificationPass(-1, [this](const Function &F) {
341       const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
342       return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
343     }));
344 
345   TargetPassConfig::addIRPasses();
346 
347   // Match interleaved memory accesses to ldN/stN intrinsics.
348   if (TM->getOptLevel() != CodeGenOpt::None)
349     addPass(createInterleavedAccessPass(TM));
350 }
351 
352 bool ARMPassConfig::addPreISel() {
353   if ((TM->getOptLevel() != CodeGenOpt::None &&
354        EnableGlobalMerge == cl::BOU_UNSET) ||
355       EnableGlobalMerge == cl::BOU_TRUE) {
356     // FIXME: This is using the thumb1 only constant value for
357     // maximal global offset for merging globals. We may want
358     // to look into using the old value for non-thumb1 code of
359     // 4095 based on the TargetMachine, but this starts to become
360     // tricky when doing code gen per function.
361     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
362                                (EnableGlobalMerge == cl::BOU_UNSET);
363     // Merging of extern globals is enabled by default on non-Mach-O as we
364     // expect it to be generally either beneficial or harmless. On Mach-O it
365     // is disabled as we emit the .subsections_via_symbols directive which
366     // means that merging extern globals is not safe.
367     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
368     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
369                                   MergeExternalByDefault));
370   }
371 
372   return false;
373 }
374 
375 bool ARMPassConfig::addInstSelector() {
376   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
377   return false;
378 }
379 
380 void ARMPassConfig::addPreRegAlloc() {
381   if (getOptLevel() != CodeGenOpt::None) {
382     addPass(createMLxExpansionPass());
383 
384     if (EnableARMLoadStoreOpt)
385       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
386 
387     if (!DisableA15SDOptimization)
388       addPass(createA15SDOptimizerPass());
389   }
390 }
391 
392 void ARMPassConfig::addPreSched2() {
393   if (getOptLevel() != CodeGenOpt::None) {
394     if (EnableARMLoadStoreOpt)
395       addPass(createARMLoadStoreOptimizationPass());
396 
397     addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
398   }
399 
400   // Expand some pseudo instructions into multiple instructions to allow
401   // proper scheduling.
402   addPass(createARMExpandPseudoPass());
403 
404   if (getOptLevel() != CodeGenOpt::None) {
405     // in v8, IfConversion depends on Thumb instruction widths
406     addPass(createThumb2SizeReductionPass([this](const Function &F) {
407       return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
408     }));
409 
410     addPass(createIfConverter([this](const Function &F) {
411       return !this->TM->getSubtarget<ARMSubtarget>(F).isThumb1Only();
412     }));
413   }
414   addPass(createThumb2ITBlockPass());
415 }
416 
417 void ARMPassConfig::addPreEmitPass() {
418   addPass(createThumb2SizeReductionPass());
419 
420   // Constant island pass work on unbundled instructions.
421   addPass(createUnpackMachineBundles([this](const Function &F) {
422     return this->TM->getSubtarget<ARMSubtarget>(F).isThumb2();
423   }));
424 
425   // Don't optimize barriers at -O0.
426   if (getOptLevel() != CodeGenOpt::None)
427     addPass(createARMOptimizeBarriersPass());
428 
429   addPass(createARMConstantIslandPass());
430 }
431