1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARM.h"
14 #include "ARMSubtarget.h"
15 #include "ARMMacroFusion.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMTargetObjectFile.h"
18 #include "ARMTargetTransformInfo.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/ExecutionDepsFix.h"
26 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/TargetParser.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/Scalar.h"
50 #include <cassert>
51 #include <memory>
52 #include <string>
53 
54 using namespace llvm;
55 
56 static cl::opt<bool>
57 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
58                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
59                    cl::init(false));
60 
61 static cl::opt<bool>
62 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
63                  cl::desc("Run SimplifyCFG after expanding atomic operations"
64                           " to make use of cmpxchg flow-based information"),
65                  cl::init(true));
66 
67 static cl::opt<bool>
68 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
69                       cl::desc("Enable ARM load/store optimization pass"),
70                       cl::init(true));
71 
72 // FIXME: Unify control over GlobalMerge.
73 static cl::opt<cl::boolOrDefault>
74 EnableGlobalMerge("arm-global-merge", cl::Hidden,
75                   cl::desc("Enable the global merge pass"));
76 
77 namespace llvm {
78   void initializeARMExecutionDepsFixPass(PassRegistry&);
79 }
80 
81 extern "C" void LLVMInitializeARMTarget() {
82   // Register the target.
83   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
84   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
85   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
86   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
87 
88   PassRegistry &Registry = *PassRegistry::getPassRegistry();
89   initializeGlobalISel(Registry);
90   initializeARMLoadStoreOptPass(Registry);
91   initializeARMPreAllocLoadStoreOptPass(Registry);
92   initializeARMConstantIslandsPass(Registry);
93   initializeARMExecutionDepsFixPass(Registry);
94   initializeARMExpandPseudoPass(Registry);
95 }
96 
97 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
98   if (TT.isOSBinFormatMachO())
99     return llvm::make_unique<TargetLoweringObjectFileMachO>();
100   if (TT.isOSWindows())
101     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
102   return llvm::make_unique<ARMElfTargetObjectFile>();
103 }
104 
105 static ARMBaseTargetMachine::ARMABI
106 computeTargetABI(const Triple &TT, StringRef CPU,
107                  const TargetOptions &Options) {
108   StringRef ABIName = Options.MCOptions.getABIName();
109 
110   if (ABIName.empty())
111     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
112 
113   if (ABIName == "aapcs16")
114     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
115   else if (ABIName.startswith("aapcs"))
116     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
117   else if (ABIName.startswith("apcs"))
118     return ARMBaseTargetMachine::ARM_ABI_APCS;
119 
120   llvm_unreachable("Unhandled/unknown ABI Name!");
121   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
122 }
123 
124 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
125                                      const TargetOptions &Options,
126                                      bool isLittle) {
127   auto ABI = computeTargetABI(TT, CPU, Options);
128   std::string Ret;
129 
130   if (isLittle)
131     // Little endian.
132     Ret += "e";
133   else
134     // Big endian.
135     Ret += "E";
136 
137   Ret += DataLayout::getManglingComponent(TT);
138 
139   // Pointers are 32 bits and aligned to 32 bits.
140   Ret += "-p:32:32";
141 
142   // ABIs other than APCS have 64 bit integers with natural alignment.
143   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
144     Ret += "-i64:64";
145 
146   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
147   // bits, others to 64 bits. We always try to align to 64 bits.
148   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
149     Ret += "-f64:32:64";
150 
151   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
152   // to 64. We always ty to give them natural alignment.
153   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
154     Ret += "-v64:32:64-v128:32:128";
155   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
156     Ret += "-v128:64:128";
157 
158   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
159   // particular hardware support on 32-bit ARM).
160   Ret += "-a:0:32";
161 
162   // Integer registers are 32 bits.
163   Ret += "-n32";
164 
165   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
166   // aligned everywhere else.
167   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
168     Ret += "-S128";
169   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
170     Ret += "-S64";
171   else
172     Ret += "-S32";
173 
174   return Ret;
175 }
176 
177 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
178                                            Optional<Reloc::Model> RM) {
179   if (!RM.hasValue())
180     // Default relocation model on Darwin is PIC.
181     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
182 
183   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
184     assert(TT.isOSBinFormatELF() &&
185            "ROPI/RWPI currently only supported for ELF");
186 
187   // DynamicNoPIC is only used on darwin.
188   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
189     return Reloc::Static;
190 
191   return *RM;
192 }
193 
194 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
195   if (CM)
196     return *CM;
197   return CodeModel::Small;
198 }
199 
200 /// Create an ARM architecture model.
201 ///
202 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
203                                            StringRef CPU, StringRef FS,
204                                            const TargetOptions &Options,
205                                            Optional<Reloc::Model> RM,
206                                            Optional<CodeModel::Model> CM,
207                                            CodeGenOpt::Level OL, bool isLittle)
208     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
209                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
210                         getEffectiveCodeModel(CM), OL),
211       TargetABI(computeTargetABI(TT, CPU, Options)),
212       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
213 
214   // Default to triple-appropriate float ABI
215   if (Options.FloatABIType == FloatABI::Default) {
216     if (TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
217         TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
218         TargetTriple.getEnvironment() == Triple::EABIHF ||
219         TargetTriple.isOSWindows() ||
220         TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
221       this->Options.FloatABIType = FloatABI::Hard;
222     else
223       this->Options.FloatABIType = FloatABI::Soft;
224   }
225 
226   // Default to triple-appropriate EABI
227   if (Options.EABIVersion == EABI::Default ||
228       Options.EABIVersion == EABI::Unknown) {
229     // musl is compatible with glibc with regard to EABI version
230     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
231          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
232          TargetTriple.getEnvironment() == Triple::MuslEABI ||
233          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
234         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
235       this->Options.EABIVersion = EABI::GNU;
236     else
237       this->Options.EABIVersion = EABI::EABI5;
238   }
239 
240   initAsmInfo();
241 }
242 
243 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
244 
245 const ARMSubtarget *
246 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
247   Attribute CPUAttr = F.getFnAttribute("target-cpu");
248   Attribute FSAttr = F.getFnAttribute("target-features");
249 
250   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
251                         ? CPUAttr.getValueAsString().str()
252                         : TargetCPU;
253   std::string FS = !FSAttr.hasAttribute(Attribute::None)
254                        ? FSAttr.getValueAsString().str()
255                        : TargetFS;
256 
257   // FIXME: This is related to the code below to reset the target options,
258   // we need to know whether or not the soft float flag is set on the
259   // function before we can generate a subtarget. We also need to use
260   // it as a key for the subtarget since that can be the only difference
261   // between two functions.
262   bool SoftFloat =
263       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
264   // If the soft float attribute is set on the function turn on the soft float
265   // subtarget feature.
266   if (SoftFloat)
267     FS += FS.empty() ? "+soft-float" : ",+soft-float";
268 
269   auto &I = SubtargetMap[CPU + FS];
270   if (!I) {
271     // This needs to be done before we create a new subtarget since any
272     // creation will depend on the TM and the code generation flags on the
273     // function that reside in TargetOptions.
274     resetTargetOptions(F);
275     I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
276 
277     if (!I->isThumb() && !I->hasARMOps())
278       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
279           "instructions, but the target does not support ARM mode execution.");
280   }
281 
282   return I.get();
283 }
284 
285 TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
286   return TargetIRAnalysis([this](const Function &F) {
287     return TargetTransformInfo(ARMTTIImpl(this, F));
288   });
289 }
290 
291 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
292                                        StringRef CPU, StringRef FS,
293                                        const TargetOptions &Options,
294                                        Optional<Reloc::Model> RM,
295                                        Optional<CodeModel::Model> CM,
296                                        CodeGenOpt::Level OL, bool JIT)
297     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
298 
299 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
300                                        StringRef CPU, StringRef FS,
301                                        const TargetOptions &Options,
302                                        Optional<Reloc::Model> RM,
303                                        Optional<CodeModel::Model> CM,
304                                        CodeGenOpt::Level OL, bool JIT)
305     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
306 
307 namespace {
308 
309 /// ARM Code Generator Pass Configuration Options.
310 class ARMPassConfig : public TargetPassConfig {
311 public:
312   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
313       : TargetPassConfig(TM, PM) {
314     if (TM.getOptLevel() != CodeGenOpt::None) {
315       ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(),
316                               TM.getTargetFeatureString());
317       if (STI.hasFeature(ARM::FeatureUseMISched))
318         substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
319     }
320   }
321 
322   ARMBaseTargetMachine &getARMTargetMachine() const {
323     return getTM<ARMBaseTargetMachine>();
324   }
325 
326   ScheduleDAGInstrs *
327   createMachineScheduler(MachineSchedContext *C) const override {
328     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
329     // add DAG Mutations here.
330     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
331     if (ST.hasFusion())
332       DAG->addMutation(createARMMacroFusionDAGMutation());
333     return DAG;
334   }
335 
336   ScheduleDAGInstrs *
337   createPostMachineScheduler(MachineSchedContext *C) const override {
338     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
339     // add DAG Mutations here.
340     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
341     if (ST.hasFusion())
342       DAG->addMutation(createARMMacroFusionDAGMutation());
343     return DAG;
344   }
345 
346   void addIRPasses() override;
347   bool addPreISel() override;
348   bool addInstSelector() override;
349   bool addIRTranslator() override;
350   bool addLegalizeMachineIR() override;
351   bool addRegBankSelect() override;
352   bool addGlobalInstructionSelect() override;
353   void addPreRegAlloc() override;
354   void addPreSched2() override;
355   void addPreEmitPass() override;
356 };
357 
358 class ARMExecutionDepsFix : public ExecutionDepsFix {
359 public:
360   static char ID;
361   ARMExecutionDepsFix() : ExecutionDepsFix(ID, ARM::DPRRegClass) {}
362   StringRef getPassName() const override {
363     return "ARM Execution Dependency Fix";
364   }
365 };
366 char ARMExecutionDepsFix::ID;
367 
368 } // end anonymous namespace
369 
370 INITIALIZE_PASS(ARMExecutionDepsFix, "arm-execution-deps-fix",
371                 "ARM Execution Dependency Fix", false, false)
372 
373 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
374   return new ARMPassConfig(*this, PM);
375 }
376 
377 void ARMPassConfig::addIRPasses() {
378   if (TM->Options.ThreadModel == ThreadModel::Single)
379     addPass(createLowerAtomicPass());
380   else
381     addPass(createAtomicExpandPass());
382 
383   // Cmpxchg instructions are often used with a subsequent comparison to
384   // determine whether it succeeded. We can exploit existing control-flow in
385   // ldrex/strex loops to simplify this, but it needs tidying up.
386   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
387     addPass(createCFGSimplificationPass(
388         1, false, false, true, [this](const Function &F) {
389           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
390           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
391         }));
392 
393   TargetPassConfig::addIRPasses();
394 
395   // Match interleaved memory accesses to ldN/stN intrinsics.
396   if (TM->getOptLevel() != CodeGenOpt::None)
397     addPass(createInterleavedAccessPass());
398 }
399 
400 bool ARMPassConfig::addPreISel() {
401   if ((TM->getOptLevel() != CodeGenOpt::None &&
402        EnableGlobalMerge == cl::BOU_UNSET) ||
403       EnableGlobalMerge == cl::BOU_TRUE) {
404     // FIXME: This is using the thumb1 only constant value for
405     // maximal global offset for merging globals. We may want
406     // to look into using the old value for non-thumb1 code of
407     // 4095 based on the TargetMachine, but this starts to become
408     // tricky when doing code gen per function.
409     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
410                                (EnableGlobalMerge == cl::BOU_UNSET);
411     // Merging of extern globals is enabled by default on non-Mach-O as we
412     // expect it to be generally either beneficial or harmless. On Mach-O it
413     // is disabled as we emit the .subsections_via_symbols directive which
414     // means that merging extern globals is not safe.
415     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
416     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
417                                   MergeExternalByDefault));
418   }
419 
420   return false;
421 }
422 
423 bool ARMPassConfig::addInstSelector() {
424   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
425   return false;
426 }
427 
428 bool ARMPassConfig::addIRTranslator() {
429   addPass(new IRTranslator());
430   return false;
431 }
432 
433 bool ARMPassConfig::addLegalizeMachineIR() {
434   addPass(new Legalizer());
435   return false;
436 }
437 
438 bool ARMPassConfig::addRegBankSelect() {
439   addPass(new RegBankSelect());
440   return false;
441 }
442 
443 bool ARMPassConfig::addGlobalInstructionSelect() {
444   addPass(new InstructionSelect());
445   return false;
446 }
447 
448 void ARMPassConfig::addPreRegAlloc() {
449   if (getOptLevel() != CodeGenOpt::None) {
450     addPass(createMLxExpansionPass());
451 
452     if (EnableARMLoadStoreOpt)
453       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
454 
455     if (!DisableA15SDOptimization)
456       addPass(createA15SDOptimizerPass());
457   }
458 }
459 
460 void ARMPassConfig::addPreSched2() {
461   if (getOptLevel() != CodeGenOpt::None) {
462     if (EnableARMLoadStoreOpt)
463       addPass(createARMLoadStoreOptimizationPass());
464 
465     addPass(new ARMExecutionDepsFix());
466   }
467 
468   // Expand some pseudo instructions into multiple instructions to allow
469   // proper scheduling.
470   addPass(createARMExpandPseudoPass());
471 
472   if (getOptLevel() != CodeGenOpt::None) {
473     // in v8, IfConversion depends on Thumb instruction widths
474     addPass(createThumb2SizeReductionPass([this](const Function &F) {
475       return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
476     }));
477 
478     addPass(createIfConverter([](const MachineFunction &MF) {
479       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
480     }));
481   }
482   addPass(createThumb2ITBlockPass());
483 }
484 
485 void ARMPassConfig::addPreEmitPass() {
486   addPass(createThumb2SizeReductionPass());
487 
488   // Constant island pass work on unbundled instructions.
489   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
490     return MF.getSubtarget<ARMSubtarget>().isThumb2();
491   }));
492 
493   // Don't optimize barriers at -O0.
494   if (getOptLevel() != CodeGenOpt::None)
495     addPass(createARMOptimizeBarriersPass());
496 
497   addPass(createARMConstantIslandPass());
498 }
499