1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARM.h"
14 #include "ARMFrameLowering.h"
15 #include "ARMTargetMachine.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
27 using namespace llvm;
28 
29 static cl::opt<bool>
30 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
31                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
32                    cl::init(false));
33 
34 static cl::opt<bool>
35 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
36                  cl::desc("Run SimplifyCFG after expanding atomic operations"
37                           " to make use of cmpxchg flow-based information"),
38                  cl::init(true));
39 
40 static cl::opt<bool>
41 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
42                       cl::desc("Enable ARM load/store optimization pass"),
43                       cl::init(true));
44 
45 // FIXME: Unify control over GlobalMerge.
46 static cl::opt<cl::boolOrDefault>
47 EnableGlobalMerge("arm-global-merge", cl::Hidden,
48                   cl::desc("Enable the global merge pass"));
49 
50 extern "C" void LLVMInitializeARMTarget() {
51   // Register the target.
52   RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
53   RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
54   RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
55   RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
56 }
57 
58 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
59   if (TT.isOSBinFormatMachO())
60     return make_unique<TargetLoweringObjectFileMachO>();
61   if (TT.isOSWindows())
62     return make_unique<TargetLoweringObjectFileCOFF>();
63   return make_unique<ARMElfTargetObjectFile>();
64 }
65 
66 static ARMBaseTargetMachine::ARMABI
67 computeTargetABI(const Triple &TT, StringRef CPU,
68                  const TargetOptions &Options) {
69   if (Options.MCOptions.getABIName().startswith("aapcs"))
70     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
71   else if (Options.MCOptions.getABIName().startswith("apcs"))
72     return ARMBaseTargetMachine::ARM_ABI_APCS;
73 
74   assert(Options.MCOptions.getABIName().empty() &&
75          "Unknown target-abi option!");
76 
77   ARMBaseTargetMachine::ARMABI TargetABI =
78       ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
79 
80   // FIXME: This is duplicated code from the front end and should be unified.
81   if (TT.isOSBinFormatMachO()) {
82     if (TT.getEnvironment() == llvm::Triple::EABI ||
83         (TT.getOS() == llvm::Triple::UnknownOS &&
84          TT.getObjectFormat() == llvm::Triple::MachO) ||
85         CPU.startswith("cortex-m")) {
86       TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
87     } else {
88       TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
89     }
90   } else if (TT.isOSWindows()) {
91     // FIXME: this is invalid for WindowsCE
92     TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
93   } else {
94     // Select the default based on the platform.
95     switch (TT.getEnvironment()) {
96     case llvm::Triple::Android:
97     case llvm::Triple::GNUEABI:
98     case llvm::Triple::GNUEABIHF:
99     case llvm::Triple::EABIHF:
100     case llvm::Triple::EABI:
101       TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
102       break;
103     case llvm::Triple::GNU:
104       TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
105       break;
106     default:
107       if (TT.getOS() == llvm::Triple::NetBSD)
108 	TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
109       else
110 	TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
111       break;
112     }
113   }
114 
115   return TargetABI;
116 }
117 
118 static std::string computeDataLayout(StringRef TT, StringRef CPU,
119                                      const TargetOptions &Options,
120                                      bool isLittle) {
121   const Triple Triple(TT);
122   auto ABI = computeTargetABI(Triple, CPU, Options);
123   std::string Ret = "";
124 
125   if (isLittle)
126     // Little endian.
127     Ret += "e";
128   else
129     // Big endian.
130     Ret += "E";
131 
132   Ret += DataLayout::getManglingComponent(Triple);
133 
134   // Pointers are 32 bits and aligned to 32 bits.
135   Ret += "-p:32:32";
136 
137   // ABIs other than APCS have 64 bit integers with natural alignment.
138   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
139     Ret += "-i64:64";
140 
141   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
142   // bits, others to 64 bits. We always try to align to 64 bits.
143   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
144     Ret += "-f64:32:64";
145 
146   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
147   // to 64. We always ty to give them natural alignment.
148   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
149     Ret += "-v64:32:64-v128:32:128";
150   else
151     Ret += "-v128:64:128";
152 
153   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
154   // particular hardware support on 32-bit ARM).
155   Ret += "-a:0:32";
156 
157   // Integer registers are 32 bits.
158   Ret += "-n32";
159 
160   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
161   // aligned everywhere else.
162   if (Triple.isOSNaCl())
163     Ret += "-S128";
164   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
165     Ret += "-S64";
166   else
167     Ret += "-S32";
168 
169   return Ret;
170 }
171 
172 /// TargetMachine ctor - Create an ARM architecture model.
173 ///
174 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
175                                            StringRef CPU, StringRef FS,
176                                            const TargetOptions &Options,
177                                            Reloc::Model RM, CodeModel::Model CM,
178                                            CodeGenOpt::Level OL, bool isLittle)
179     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
180                         CPU, FS, Options, RM, CM, OL),
181       TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
182       TLOF(createTLOF(Triple(getTargetTriple()))),
183       Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
184 
185   // Default to triple-appropriate float ABI
186   if (Options.FloatABIType == FloatABI::Default)
187     this->Options.FloatABIType =
188         Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
189 }
190 
191 ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
192 
193 const ARMSubtarget *
194 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
195   Attribute CPUAttr = F.getFnAttribute("target-cpu");
196   Attribute FSAttr = F.getFnAttribute("target-features");
197 
198   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
199                         ? CPUAttr.getValueAsString().str()
200                         : TargetCPU;
201   std::string FS = !FSAttr.hasAttribute(Attribute::None)
202                        ? FSAttr.getValueAsString().str()
203                        : TargetFS;
204 
205   // FIXME: This is related to the code below to reset the target options,
206   // we need to know whether or not the soft float flag is set on the
207   // function before we can generate a subtarget. We also need to use
208   // it as a key for the subtarget since that can be the only difference
209   // between two functions.
210   Attribute SFAttr = F.getFnAttribute("use-soft-float");
211   bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)
212                        ? SFAttr.getValueAsString() == "true"
213                        : Options.UseSoftFloat;
214 
215   auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"
216                                                : "use-soft-float=false")];
217   if (!I) {
218     // This needs to be done before we create a new subtarget since any
219     // creation will depend on the TM and the code generation flags on the
220     // function that reside in TargetOptions.
221     resetTargetOptions(F);
222     I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
223   }
224   return I.get();
225 }
226 
227 TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
228   return TargetIRAnalysis(
229       [this](Function &F) { return TargetTransformInfo(ARMTTIImpl(this, F)); });
230 }
231 
232 
233 void ARMTargetMachine::anchor() { }
234 
235 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU,
236                                    StringRef FS, const TargetOptions &Options,
237                                    Reloc::Model RM, CodeModel::Model CM,
238                                    CodeGenOpt::Level OL, bool isLittle)
239     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
240   initAsmInfo();
241   if (!Subtarget.hasARMOps())
242     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
243                        "support ARM mode execution!");
244 }
245 
246 void ARMLETargetMachine::anchor() { }
247 
248 ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT,
249                                        StringRef CPU, StringRef FS,
250                                        const TargetOptions &Options,
251                                        Reloc::Model RM, CodeModel::Model CM,
252                                        CodeGenOpt::Level OL)
253     : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
254 
255 void ARMBETargetMachine::anchor() { }
256 
257 ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT,
258                                        StringRef CPU, StringRef FS,
259                                        const TargetOptions &Options,
260                                        Reloc::Model RM, CodeModel::Model CM,
261                                        CodeGenOpt::Level OL)
262     : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
263 
264 void ThumbTargetMachine::anchor() { }
265 
266 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
267                                        StringRef CPU, StringRef FS,
268                                        const TargetOptions &Options,
269                                        Reloc::Model RM, CodeModel::Model CM,
270                                        CodeGenOpt::Level OL, bool isLittle)
271     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL,
272                            isLittle) {
273   initAsmInfo();
274 }
275 
276 void ThumbLETargetMachine::anchor() { }
277 
278 ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT,
279                                            StringRef CPU, StringRef FS,
280                                            const TargetOptions &Options,
281                                            Reloc::Model RM, CodeModel::Model CM,
282                                            CodeGenOpt::Level OL)
283     : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
284 
285 void ThumbBETargetMachine::anchor() { }
286 
287 ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, StringRef TT,
288                                            StringRef CPU, StringRef FS,
289                                            const TargetOptions &Options,
290                                            Reloc::Model RM, CodeModel::Model CM,
291                                            CodeGenOpt::Level OL)
292     : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
293 
294 namespace {
295 /// ARM Code Generator Pass Configuration Options.
296 class ARMPassConfig : public TargetPassConfig {
297 public:
298   ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
299     : TargetPassConfig(TM, PM) {}
300 
301   ARMBaseTargetMachine &getARMTargetMachine() const {
302     return getTM<ARMBaseTargetMachine>();
303   }
304 
305   const ARMSubtarget &getARMSubtarget() const {
306     return *getARMTargetMachine().getSubtargetImpl();
307   }
308 
309   void addIRPasses() override;
310   bool addPreISel() override;
311   bool addInstSelector() override;
312   void addPreRegAlloc() override;
313   void addPreSched2() override;
314   void addPreEmitPass() override;
315 };
316 } // namespace
317 
318 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
319   return new ARMPassConfig(this, PM);
320 }
321 
322 void ARMPassConfig::addIRPasses() {
323   if (TM->Options.ThreadModel == ThreadModel::Single)
324     addPass(createLowerAtomicPass());
325   else
326     addPass(createAtomicExpandPass(TM));
327 
328   // Cmpxchg instructions are often used with a subsequent comparison to
329   // determine whether it succeeded. We can exploit existing control-flow in
330   // ldrex/strex loops to simplify this, but it needs tidying up.
331   const ARMSubtarget *Subtarget = &getARMSubtarget();
332   if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only())
333     if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
334       addPass(createCFGSimplificationPass());
335 
336   TargetPassConfig::addIRPasses();
337 }
338 
339 bool ARMPassConfig::addPreISel() {
340   if ((TM->getOptLevel() == CodeGenOpt::Aggressive &&
341        EnableGlobalMerge == cl::BOU_UNSET) ||
342       EnableGlobalMerge == cl::BOU_TRUE)
343     // FIXME: This is using the thumb1 only constant value for
344     // maximal global offset for merging globals. We may want
345     // to look into using the old value for non-thumb1 code of
346     // 4095 based on the TargetMachine, but this starts to become
347     // tricky when doing code gen per function.
348     addPass(createGlobalMergePass(TM, 127));
349 
350   return false;
351 }
352 
353 bool ARMPassConfig::addInstSelector() {
354   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
355 
356   if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
357       TM->Options.EnableFastISel)
358     addPass(createARMGlobalBaseRegPass());
359   return false;
360 }
361 
362 void ARMPassConfig::addPreRegAlloc() {
363   if (getOptLevel() != CodeGenOpt::None) {
364     addPass(createMLxExpansionPass());
365 
366     if (EnableARMLoadStoreOpt)
367       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
368 
369     if (!DisableA15SDOptimization)
370       addPass(createA15SDOptimizerPass());
371   }
372 }
373 
374 void ARMPassConfig::addPreSched2() {
375   if (getOptLevel() != CodeGenOpt::None) {
376     if (EnableARMLoadStoreOpt)
377       addPass(createARMLoadStoreOptimizationPass());
378 
379     addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
380   }
381 
382   // Expand some pseudo instructions into multiple instructions to allow
383   // proper scheduling.
384   addPass(createARMExpandPseudoPass());
385 
386   if (getOptLevel() != CodeGenOpt::None) {
387     // in v8, IfConversion depends on Thumb instruction widths
388     if (getARMSubtarget().restrictIT())
389       addPass(createThumb2SizeReductionPass());
390     if (!getARMSubtarget().isThumb1Only())
391       addPass(&IfConverterID);
392   }
393   addPass(createThumb2ITBlockPass());
394 }
395 
396 void ARMPassConfig::addPreEmitPass() {
397   addPass(createThumb2SizeReductionPass());
398 
399   // Constant island pass work on unbundled instructions.
400   if (getARMSubtarget().isThumb2())
401     addPass(&UnpackMachineBundlesID);
402 
403   addPass(createARMOptimizeBarriersPass());
404   addPass(createARMConstantIslandPass());
405 }
406