1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMTargetMachine.h" 14 #include "ARMMCAsmInfo.h" 15 #include "ARMFrameLowering.h" 16 #include "ARM.h" 17 #include "llvm/PassManager.h" 18 #include "llvm/CodeGen/Passes.h" 19 #include "llvm/Support/CommandLine.h" 20 #include "llvm/Support/FormattedStream.h" 21 #include "llvm/Target/TargetOptions.h" 22 #include "llvm/Target/TargetRegistry.h" 23 using namespace llvm; 24 25 static cl::opt<bool>ExpandMLx("expand-fp-mlx", cl::init(false), cl::Hidden); 26 27 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) { 28 Triple TheTriple(TT); 29 switch (TheTriple.getOS()) { 30 case Triple::Darwin: 31 return new ARMMCAsmInfoDarwin(); 32 default: 33 return new ARMELFMCAsmInfo(); 34 } 35 } 36 37 // This is duplicated code. Refactor this. 38 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, 39 MCContext &Ctx, TargetAsmBackend &TAB, 40 raw_ostream &OS, 41 MCCodeEmitter *Emitter, 42 bool RelaxAll) { 43 switch (Triple(TT).getOS()) { 44 case Triple::Darwin: 45 return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll); 46 case Triple::MinGW32: 47 case Triple::MinGW64: 48 case Triple::Cygwin: 49 case Triple::Win32: 50 llvm_unreachable("ARM does not support Windows COFF format"); 51 return NULL; 52 default: 53 return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll); 54 } 55 } 56 57 extern "C" void LLVMInitializeARMTarget() { 58 // Register the target. 59 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget); 60 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget); 61 62 // Register the target asm info. 63 RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo); 64 RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo); 65 66 // Register the MC Code Emitter 67 TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter); 68 TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter); 69 70 // Register the asm backend. 71 TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend); 72 TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend); 73 74 // Register the object streamer. 75 TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer); 76 TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer); 77 78 } 79 80 /// TargetMachine ctor - Create an ARM architecture model. 81 /// 82 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, 83 const std::string &TT, 84 const std::string &FS, 85 bool isThumb) 86 : LLVMTargetMachine(T, TT), 87 Subtarget(TT, FS, isThumb), 88 JITInfo(), 89 InstrItins(Subtarget.getInstrItineraryData()) 90 { 91 DefRelocModel = getRelocationModel(); 92 } 93 94 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, 95 const std::string &FS) 96 : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget), 97 DataLayout(Subtarget.isAPCS_ABI() ? 98 std::string("e-p:32:32-f64:32:64-i64:32:64-" 99 "v128:32:128-v64:32:64-n32") : 100 std::string("e-p:32:32-f64:64:64-i64:64:64-" 101 "v128:64:128-v64:64:64-n32")), 102 ELFWriterInfo(*this), 103 TLInfo(*this), 104 TSInfo(*this), 105 FrameLowering(Subtarget) { 106 if (!Subtarget.hasARMOps()) 107 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " 108 "support ARM mode execution!"); 109 } 110 111 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, 112 const std::string &FS) 113 : ARMBaseTargetMachine(T, TT, FS, true), 114 InstrInfo(Subtarget.hasThumb2() 115 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) 116 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), 117 DataLayout(Subtarget.isAPCS_ABI() ? 118 std::string("e-p:32:32-f64:32:64-i64:32:64-" 119 "i16:16:32-i8:8:32-i1:8:32-" 120 "v128:32:128-v64:32:64-a:0:32-n32") : 121 std::string("e-p:32:32-f64:64:64-i64:64:64-" 122 "i16:16:32-i8:8:32-i1:8:32-" 123 "v128:64:128-v64:64:64-a:0:32-n32")), 124 ELFWriterInfo(*this), 125 TLInfo(*this), 126 TSInfo(*this), 127 FrameLowering(Subtarget.hasThumb2() 128 ? new ARMFrameLowering(Subtarget) 129 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) { 130 } 131 132 // Pass Pipeline Configuration 133 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM, 134 CodeGenOpt::Level OptLevel) { 135 if (OptLevel != CodeGenOpt::None) 136 PM.add(createARMGlobalMergePass(getTargetLowering())); 137 138 return false; 139 } 140 141 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM, 142 CodeGenOpt::Level OptLevel) { 143 PM.add(createARMISelDag(*this, OptLevel)); 144 return false; 145 } 146 147 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, 148 CodeGenOpt::Level OptLevel) { 149 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 150 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) 151 PM.add(createARMLoadStoreOptimizationPass(true)); 152 if (ExpandMLx && 153 OptLevel != CodeGenOpt::None && Subtarget.hasVFP2()) 154 PM.add(createMLxExpansionPass()); 155 156 return true; 157 } 158 159 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, 160 CodeGenOpt::Level OptLevel) { 161 // FIXME: temporarily disabling load / store optimization pass for Thumb1. 162 if (OptLevel != CodeGenOpt::None) { 163 if (!Subtarget.isThumb1Only()) 164 PM.add(createARMLoadStoreOptimizationPass()); 165 if (Subtarget.hasNEON()) 166 PM.add(createNEONMoveFixPass()); 167 } 168 169 // Expand some pseudo instructions into multiple instructions to allow 170 // proper scheduling. 171 PM.add(createARMExpandPseudoPass()); 172 173 if (OptLevel != CodeGenOpt::None) { 174 if (!Subtarget.isThumb1Only()) 175 PM.add(createIfConverterPass()); 176 } 177 if (Subtarget.isThumb2()) 178 PM.add(createThumb2ITBlockPass()); 179 180 return true; 181 } 182 183 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, 184 CodeGenOpt::Level OptLevel) { 185 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb()) 186 PM.add(createThumb2SizeReductionPass()); 187 188 PM.add(createARMConstantIslandPass()); 189 return true; 190 } 191 192 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 193 CodeGenOpt::Level OptLevel, 194 JITCodeEmitter &JCE) { 195 // FIXME: Move this to TargetJITInfo! 196 if (DefRelocModel == Reloc::Default) 197 setRelocationModel(Reloc::Static); 198 199 // Machine code emitter pass for ARM. 200 PM.add(createARMJITCodeEmitterPass(*this, JCE)); 201 return false; 202 } 203