1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMTargetMachine.h"
14 #include "ARM.h"
15 #include "ARMFrameLowering.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
24 using namespace llvm;
25 
26 static cl::opt<bool>
27 EnableGlobalMerge("global-merge", cl::Hidden,
28                   cl::desc("Enable global merge pass"),
29                   cl::init(true));
30 
31 static cl::opt<bool>
32 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
33                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
34                    cl::init(false));
35 
36 extern "C" void LLVMInitializeARMTarget() {
37   // Register the target.
38   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
39   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
40 }
41 
42 
43 /// TargetMachine ctor - Create an ARM architecture model.
44 ///
45 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
46                                            StringRef CPU, StringRef FS,
47                                            const TargetOptions &Options,
48                                            Reloc::Model RM, CodeModel::Model CM,
49                                            CodeGenOpt::Level OL)
50   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
51     Subtarget(TT, CPU, FS, Options),
52     JITInfo(),
53     InstrItins(Subtarget.getInstrItineraryData()) {
54 
55   // Default to triple-appropriate float ABI
56   if (Options.FloatABIType == FloatABI::Default)
57     this->Options.FloatABIType =
58         Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
59 }
60 
61 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
62   // Add first the target-independent BasicTTI pass, then our ARM pass. This
63   // allows the ARM pass to delegate to the target independent layer when
64   // appropriate.
65   PM.add(createBasicTargetTransformInfoPass(this));
66   PM.add(createARMTargetTransformInfoPass(this));
67 }
68 
69 
70 void ARMTargetMachine::anchor() { }
71 
72 static std::string computeDataLayout(ARMSubtarget &ST) {
73   // Little endian.
74   std::string Ret = "e";
75 
76   Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
77 
78   // Pointers are 32 bits and aligned to 32 bits.
79   Ret += "-p:32:32";
80 
81   // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
82   // align to 32.
83   if (ST.isThumb())
84     Ret += "-i1:8:32-i8:8:32-i16:16:32";
85 
86   // ABIs other than APC have 64 bit integers with natural alignment.
87   if (!ST.isAPCS_ABI())
88     Ret += "-i64:64";
89 
90   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
91   // bits, others to 64 bits. We always try to align to 64 bits.
92   if (ST.isAPCS_ABI())
93     Ret += "-f64:32:64";
94 
95   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
96   // to 64. We always ty to give them natural alignment.
97   if (ST.isAPCS_ABI())
98     Ret += "-v64:32:64-v128:32:128";
99   else
100     Ret += "-v128:64:128";
101 
102   // On thumb and APCS, only try to align aggregates to 32 bits (the default is
103   // 64 bits).
104   if (ST.isThumb() || ST.isAPCS_ABI())
105     Ret += "-a:0:32";
106 
107   // Integer registers are 32 bits.
108   Ret += "-n32";
109 
110   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
111   // aligned everywhere else.
112   if (ST.isTargetNaCl())
113     Ret += "-S128";
114   else if (ST.isAAPCS_ABI())
115     Ret += "-S64";
116   else
117     Ret += "-S32";
118 
119   return Ret;
120 }
121 
122 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
123                                    StringRef CPU, StringRef FS,
124                                    const TargetOptions &Options,
125                                    Reloc::Model RM, CodeModel::Model CM,
126                                    CodeGenOpt::Level OL)
127   : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
128     InstrInfo(Subtarget),
129     DL(computeDataLayout(Subtarget)),
130     TLInfo(*this),
131     TSInfo(*this),
132     FrameLowering(Subtarget) {
133   initAsmInfo();
134   if (!Subtarget.hasARMOps())
135     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
136                        "support ARM mode execution!");
137 }
138 
139 void ThumbTargetMachine::anchor() { }
140 
141 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
142                                        StringRef CPU, StringRef FS,
143                                        const TargetOptions &Options,
144                                        Reloc::Model RM, CodeModel::Model CM,
145                                        CodeGenOpt::Level OL)
146   : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
147     InstrInfo(Subtarget.hasThumb2()
148               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
149               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
150     DL(computeDataLayout(Subtarget)),
151     TLInfo(*this),
152     TSInfo(*this),
153     FrameLowering(Subtarget.hasThumb2()
154               ? new ARMFrameLowering(Subtarget)
155               : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
156   initAsmInfo();
157 }
158 
159 namespace {
160 /// ARM Code Generator Pass Configuration Options.
161 class ARMPassConfig : public TargetPassConfig {
162 public:
163   ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
164     : TargetPassConfig(TM, PM) {}
165 
166   ARMBaseTargetMachine &getARMTargetMachine() const {
167     return getTM<ARMBaseTargetMachine>();
168   }
169 
170   const ARMSubtarget &getARMSubtarget() const {
171     return *getARMTargetMachine().getSubtargetImpl();
172   }
173 
174   virtual bool addPreISel();
175   virtual bool addInstSelector();
176   virtual bool addPreRegAlloc();
177   virtual bool addPreSched2();
178   virtual bool addPreEmitPass();
179 };
180 } // namespace
181 
182 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
183   return new ARMPassConfig(this, PM);
184 }
185 
186 bool ARMPassConfig::addPreISel() {
187   if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
188     addPass(createGlobalMergePass(TM));
189 
190   return false;
191 }
192 
193 bool ARMPassConfig::addInstSelector() {
194   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
195 
196   const ARMSubtarget *Subtarget = &getARMSubtarget();
197   if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
198       TM->Options.EnableFastISel)
199     addPass(createARMGlobalBaseRegPass());
200   return false;
201 }
202 
203 bool ARMPassConfig::addPreRegAlloc() {
204   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
205   if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
206     addPass(createARMLoadStoreOptimizationPass(true));
207   if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
208     addPass(createMLxExpansionPass());
209   // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
210   // enabled when NEON is available.
211   if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
212     getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
213     addPass(createA15SDOptimizerPass());
214   }
215   return true;
216 }
217 
218 bool ARMPassConfig::addPreSched2() {
219   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
220   if (getOptLevel() != CodeGenOpt::None) {
221     if (!getARMSubtarget().isThumb1Only()) {
222       addPass(createARMLoadStoreOptimizationPass());
223       printAndVerify("After ARM load / store optimizer");
224     }
225     if (getARMSubtarget().hasNEON())
226       addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
227   }
228 
229   // Expand some pseudo instructions into multiple instructions to allow
230   // proper scheduling.
231   addPass(createARMExpandPseudoPass());
232 
233   if (getOptLevel() != CodeGenOpt::None) {
234     if (!getARMSubtarget().isThumb1Only()) {
235       // in v8, IfConversion depends on Thumb instruction widths
236       if (getARMSubtarget().restrictIT() &&
237           !getARMSubtarget().prefers32BitThumb())
238         addPass(createThumb2SizeReductionPass());
239       addPass(&IfConverterID);
240     }
241   }
242   if (getARMSubtarget().isThumb2())
243     addPass(createThumb2ITBlockPass());
244 
245   return true;
246 }
247 
248 bool ARMPassConfig::addPreEmitPass() {
249   if (getARMSubtarget().isThumb2()) {
250     if (!getARMSubtarget().prefers32BitThumb())
251       addPass(createThumb2SizeReductionPass());
252 
253     // Constant island pass work on unbundled instructions.
254     addPass(&UnpackMachineBundlesID);
255   }
256 
257   addPass(createARMConstantIslandPass());
258 
259   return true;
260 }
261 
262 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
263                                           JITCodeEmitter &JCE) {
264   // Machine code emitter pass for ARM.
265   PM.add(createARMJITCodeEmitterPass(*this, JCE));
266   return false;
267 }
268