1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARM.h"
14 #include "ARMSubtarget.h"
15 #include "ARMMacroFusion.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMTargetObjectFile.h"
18 #include "ARMTargetTransformInfo.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/ExecutionDepsFix.h"
26 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/TargetParser.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/Scalar.h"
50 #include <cassert>
51 #include <memory>
52 #include <string>
53 
54 using namespace llvm;
55 
56 static cl::opt<bool>
57 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
58                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
59                    cl::init(false));
60 
61 static cl::opt<bool>
62 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
63                  cl::desc("Run SimplifyCFG after expanding atomic operations"
64                           " to make use of cmpxchg flow-based information"),
65                  cl::init(true));
66 
67 static cl::opt<bool>
68 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
69                       cl::desc("Enable ARM load/store optimization pass"),
70                       cl::init(true));
71 
72 // FIXME: Unify control over GlobalMerge.
73 static cl::opt<cl::boolOrDefault>
74 EnableGlobalMerge("arm-global-merge", cl::Hidden,
75                   cl::desc("Enable the global merge pass"));
76 
77 namespace llvm {
78   void initializeARMExecutionDepsFixPass(PassRegistry&);
79 }
80 
81 extern "C" void LLVMInitializeARMTarget() {
82   // Register the target.
83   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
84   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
85   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
86   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
87 
88   PassRegistry &Registry = *PassRegistry::getPassRegistry();
89   initializeGlobalISel(Registry);
90   initializeARMLoadStoreOptPass(Registry);
91   initializeARMPreAllocLoadStoreOptPass(Registry);
92   initializeARMConstantIslandsPass(Registry);
93   initializeARMExecutionDepsFixPass(Registry);
94 }
95 
96 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
97   if (TT.isOSBinFormatMachO())
98     return llvm::make_unique<TargetLoweringObjectFileMachO>();
99   if (TT.isOSWindows())
100     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
101   return llvm::make_unique<ARMElfTargetObjectFile>();
102 }
103 
104 static ARMBaseTargetMachine::ARMABI
105 computeTargetABI(const Triple &TT, StringRef CPU,
106                  const TargetOptions &Options) {
107   StringRef ABIName = Options.MCOptions.getABIName();
108 
109   if (ABIName.empty())
110     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
111 
112   if (ABIName == "aapcs16")
113     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
114   else if (ABIName.startswith("aapcs"))
115     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
116   else if (ABIName.startswith("apcs"))
117     return ARMBaseTargetMachine::ARM_ABI_APCS;
118 
119   llvm_unreachable("Unhandled/unknown ABI Name!");
120   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
121 }
122 
123 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
124                                      const TargetOptions &Options,
125                                      bool isLittle) {
126   auto ABI = computeTargetABI(TT, CPU, Options);
127   std::string Ret;
128 
129   if (isLittle)
130     // Little endian.
131     Ret += "e";
132   else
133     // Big endian.
134     Ret += "E";
135 
136   Ret += DataLayout::getManglingComponent(TT);
137 
138   // Pointers are 32 bits and aligned to 32 bits.
139   Ret += "-p:32:32";
140 
141   // ABIs other than APCS have 64 bit integers with natural alignment.
142   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
143     Ret += "-i64:64";
144 
145   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
146   // bits, others to 64 bits. We always try to align to 64 bits.
147   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
148     Ret += "-f64:32:64";
149 
150   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
151   // to 64. We always ty to give them natural alignment.
152   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
153     Ret += "-v64:32:64-v128:32:128";
154   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
155     Ret += "-v128:64:128";
156 
157   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
158   // particular hardware support on 32-bit ARM).
159   Ret += "-a:0:32";
160 
161   // Integer registers are 32 bits.
162   Ret += "-n32";
163 
164   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
165   // aligned everywhere else.
166   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
167     Ret += "-S128";
168   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
169     Ret += "-S64";
170   else
171     Ret += "-S32";
172 
173   return Ret;
174 }
175 
176 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
177                                            Optional<Reloc::Model> RM) {
178   if (!RM.hasValue())
179     // Default relocation model on Darwin is PIC.
180     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
181 
182   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
183     assert(TT.isOSBinFormatELF() &&
184            "ROPI/RWPI currently only supported for ELF");
185 
186   // DynamicNoPIC is only used on darwin.
187   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
188     return Reloc::Static;
189 
190   return *RM;
191 }
192 
193 /// Create an ARM architecture model.
194 ///
195 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
196                                            StringRef CPU, StringRef FS,
197                                            const TargetOptions &Options,
198                                            Optional<Reloc::Model> RM,
199                                            CodeModel::Model CM,
200                                            CodeGenOpt::Level OL, bool isLittle)
201     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
202                         CPU, FS, Options, getEffectiveRelocModel(TT, RM), CM,
203                         OL),
204       TargetABI(computeTargetABI(TT, CPU, Options)),
205       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
206 
207   // Default to triple-appropriate float ABI
208   if (Options.FloatABIType == FloatABI::Default) {
209     if (TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
210         TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
211         TargetTriple.getEnvironment() == Triple::EABIHF ||
212         TargetTriple.isOSWindows() ||
213         TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
214       this->Options.FloatABIType = FloatABI::Hard;
215     else
216       this->Options.FloatABIType = FloatABI::Soft;
217   }
218 
219   // Default to triple-appropriate EABI
220   if (Options.EABIVersion == EABI::Default ||
221       Options.EABIVersion == EABI::Unknown) {
222     // musl is compatible with glibc with regard to EABI version
223     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
224 	 TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
225 	 TargetTriple.getEnvironment() == Triple::MuslEABI ||
226 	 TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
227 	!(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
228       this->Options.EABIVersion = EABI::GNU;
229     else
230       this->Options.EABIVersion = EABI::EABI5;
231   }
232 
233   initAsmInfo();
234 }
235 
236 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
237 
238 const ARMSubtarget *
239 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
240   Attribute CPUAttr = F.getFnAttribute("target-cpu");
241   Attribute FSAttr = F.getFnAttribute("target-features");
242 
243   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
244                         ? CPUAttr.getValueAsString().str()
245                         : TargetCPU;
246   std::string FS = !FSAttr.hasAttribute(Attribute::None)
247                        ? FSAttr.getValueAsString().str()
248                        : TargetFS;
249 
250   // FIXME: This is related to the code below to reset the target options,
251   // we need to know whether or not the soft float flag is set on the
252   // function before we can generate a subtarget. We also need to use
253   // it as a key for the subtarget since that can be the only difference
254   // between two functions.
255   bool SoftFloat =
256       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
257   // If the soft float attribute is set on the function turn on the soft float
258   // subtarget feature.
259   if (SoftFloat)
260     FS += FS.empty() ? "+soft-float" : ",+soft-float";
261 
262   auto &I = SubtargetMap[CPU + FS];
263   if (!I) {
264     // This needs to be done before we create a new subtarget since any
265     // creation will depend on the TM and the code generation flags on the
266     // function that reside in TargetOptions.
267     resetTargetOptions(F);
268     I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
269   }
270   return I.get();
271 }
272 
273 TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
274   return TargetIRAnalysis([this](const Function &F) {
275     return TargetTransformInfo(ARMTTIImpl(this, F));
276   });
277 }
278 
279 
280 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
281                                        StringRef CPU, StringRef FS,
282                                        const TargetOptions &Options,
283                                        Optional<Reloc::Model> RM,
284                                        CodeModel::Model CM,
285                                        CodeGenOpt::Level OL)
286     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
287 
288 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
289                                        StringRef CPU, StringRef FS,
290                                        const TargetOptions &Options,
291                                        Optional<Reloc::Model> RM,
292                                        CodeModel::Model CM,
293                                        CodeGenOpt::Level OL)
294     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
295 
296 namespace {
297 
298 /// ARM Code Generator Pass Configuration Options.
299 class ARMPassConfig : public TargetPassConfig {
300 public:
301   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
302     : TargetPassConfig(TM, PM) {}
303 
304   ARMBaseTargetMachine &getARMTargetMachine() const {
305     return getTM<ARMBaseTargetMachine>();
306   }
307 
308   ScheduleDAGInstrs *
309   createMachineScheduler(MachineSchedContext *C) const override {
310     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
311     // add DAG Mutations here.
312     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
313     if (ST.hasFusion())
314       DAG->addMutation(createARMMacroFusionDAGMutation());
315     return DAG;
316   }
317 
318   ScheduleDAGInstrs *
319   createPostMachineScheduler(MachineSchedContext *C) const override {
320     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
321     // add DAG Mutations here.
322     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
323     if (ST.hasFusion())
324       DAG->addMutation(createARMMacroFusionDAGMutation());
325     return DAG;
326   }
327 
328   void addIRPasses() override;
329   bool addPreISel() override;
330   bool addInstSelector() override;
331 #ifdef LLVM_BUILD_GLOBAL_ISEL
332   bool addIRTranslator() override;
333   bool addLegalizeMachineIR() override;
334   bool addRegBankSelect() override;
335   bool addGlobalInstructionSelect() override;
336 #endif
337   void addPreRegAlloc() override;
338   void addPreSched2() override;
339   void addPreEmitPass() override;
340 };
341 
342 class ARMExecutionDepsFix : public ExecutionDepsFix {
343 public:
344   static char ID;
345   ARMExecutionDepsFix() : ExecutionDepsFix(ID, ARM::DPRRegClass) {}
346   StringRef getPassName() const override {
347     return "ARM Execution Dependency Fix";
348   }
349 };
350 char ARMExecutionDepsFix::ID;
351 
352 } // end anonymous namespace
353 
354 INITIALIZE_PASS(ARMExecutionDepsFix, "arm-execution-deps-fix",
355                 "ARM Execution Dependency Fix", false, false)
356 
357 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
358   return new ARMPassConfig(*this, PM);
359 }
360 
361 void ARMPassConfig::addIRPasses() {
362   if (TM->Options.ThreadModel == ThreadModel::Single)
363     addPass(createLowerAtomicPass());
364   else
365     addPass(createAtomicExpandPass());
366 
367   // Cmpxchg instructions are often used with a subsequent comparison to
368   // determine whether it succeeded. We can exploit existing control-flow in
369   // ldrex/strex loops to simplify this, but it needs tidying up.
370   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
371     addPass(createCFGSimplificationPass(-1, [this](const Function &F) {
372       const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
373       return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
374     }));
375 
376   TargetPassConfig::addIRPasses();
377 
378   // Match interleaved memory accesses to ldN/stN intrinsics.
379   if (TM->getOptLevel() != CodeGenOpt::None)
380     addPass(createInterleavedAccessPass());
381 }
382 
383 bool ARMPassConfig::addPreISel() {
384   if ((TM->getOptLevel() != CodeGenOpt::None &&
385        EnableGlobalMerge == cl::BOU_UNSET) ||
386       EnableGlobalMerge == cl::BOU_TRUE) {
387     // FIXME: This is using the thumb1 only constant value for
388     // maximal global offset for merging globals. We may want
389     // to look into using the old value for non-thumb1 code of
390     // 4095 based on the TargetMachine, but this starts to become
391     // tricky when doing code gen per function.
392     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
393                                (EnableGlobalMerge == cl::BOU_UNSET);
394     // Merging of extern globals is enabled by default on non-Mach-O as we
395     // expect it to be generally either beneficial or harmless. On Mach-O it
396     // is disabled as we emit the .subsections_via_symbols directive which
397     // means that merging extern globals is not safe.
398     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
399     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
400                                   MergeExternalByDefault));
401   }
402 
403   return false;
404 }
405 
406 bool ARMPassConfig::addInstSelector() {
407   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
408   return false;
409 }
410 
411 #ifdef LLVM_BUILD_GLOBAL_ISEL
412 bool ARMPassConfig::addIRTranslator() {
413   addPass(new IRTranslator());
414   return false;
415 }
416 
417 bool ARMPassConfig::addLegalizeMachineIR() {
418   addPass(new Legalizer());
419   return false;
420 }
421 
422 bool ARMPassConfig::addRegBankSelect() {
423   addPass(new RegBankSelect());
424   return false;
425 }
426 
427 bool ARMPassConfig::addGlobalInstructionSelect() {
428   addPass(new InstructionSelect());
429   return false;
430 }
431 #endif
432 
433 void ARMPassConfig::addPreRegAlloc() {
434   if (getOptLevel() != CodeGenOpt::None) {
435     addPass(createMLxExpansionPass());
436 
437     if (EnableARMLoadStoreOpt)
438       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
439 
440     if (!DisableA15SDOptimization)
441       addPass(createA15SDOptimizerPass());
442   }
443 }
444 
445 void ARMPassConfig::addPreSched2() {
446   if (getOptLevel() != CodeGenOpt::None) {
447     if (EnableARMLoadStoreOpt)
448       addPass(createARMLoadStoreOptimizationPass());
449 
450     addPass(new ARMExecutionDepsFix());
451   }
452 
453   // Expand some pseudo instructions into multiple instructions to allow
454   // proper scheduling.
455   addPass(createARMExpandPseudoPass());
456 
457   if (getOptLevel() != CodeGenOpt::None) {
458     // in v8, IfConversion depends on Thumb instruction widths
459     addPass(createThumb2SizeReductionPass([this](const Function &F) {
460       return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
461     }));
462 
463     addPass(createIfConverter([](const MachineFunction &MF) {
464       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
465     }));
466   }
467   addPass(createThumb2ITBlockPass());
468 }
469 
470 void ARMPassConfig::addPreEmitPass() {
471   addPass(createThumb2SizeReductionPass());
472 
473   // Constant island pass work on unbundled instructions.
474   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
475     return MF.getSubtarget<ARMSubtarget>().isThumb2();
476   }));
477 
478   // Don't optimize barriers at -O0.
479   if (getOptLevel() != CodeGenOpt::None)
480     addPass(createARMOptimizeBarriersPass());
481 
482   addPass(createARMConstantIslandPass());
483 }
484