1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMTargetMachine.h" 14 #include "ARMTargetAsmInfo.h" 15 #include "ARMFrameInfo.h" 16 #include "ARM.h" 17 #include "llvm/Module.h" 18 #include "llvm/PassManager.h" 19 #include "llvm/CodeGen/Passes.h" 20 #include "llvm/Support/CommandLine.h" 21 #include "llvm/Support/raw_ostream.h" 22 #include "llvm/Target/TargetMachineRegistry.h" 23 #include "llvm/Target/TargetOptions.h" 24 using namespace llvm; 25 26 static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden, 27 cl::desc("Disable load store optimization pass")); 28 static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden, 29 cl::desc("Disable if-conversion pass")); 30 31 /// ARMTargetMachineModule - Note that this is used on hosts that cannot link 32 /// in a library unless there are references into the library. In particular, 33 /// it seems that it is not possible to get things to work on Win32 without 34 /// this. Though it is unused, do not remove it. 35 extern "C" int ARMTargetMachineModule; 36 int ARMTargetMachineModule = 0; 37 38 // Register the target. 39 static RegisterTarget<ARMTargetMachine> X("arm", "ARM"); 40 static RegisterTarget<ThumbTargetMachine> Y("thumb", "Thumb"); 41 42 // Force static initialization. 43 extern "C" void LLVMInitializeARMTarget() { } 44 45 // No assembler printer by default 46 ARMBaseTargetMachine::AsmPrinterCtorFn ARMBaseTargetMachine::AsmPrinterCtor = 0; 47 48 /// ThumbTargetMachine - Create an Thumb architecture model. 49 /// 50 unsigned ThumbTargetMachine::getJITMatchQuality() { 51 #if defined(__thumb__) 52 return 10; 53 #endif 54 return 0; 55 } 56 57 unsigned ThumbTargetMachine::getModuleMatchQuality(const Module &M) { 58 std::string TT = M.getTargetTriple(); 59 // Match thumb-foo-bar, as well as things like thumbv5blah-* 60 if (TT.size() >= 6 && 61 (TT.substr(0, 6) == "thumb-" || TT.substr(0, 6) == "thumbv")) 62 return 20; 63 64 // If the target triple is something non-thumb, we don't match. 65 if (!TT.empty()) return 0; 66 67 if (M.getEndianness() == Module::LittleEndian && 68 M.getPointerSize() == Module::Pointer32) 69 return 10; // Weak match 70 else if (M.getEndianness() != Module::AnyEndianness || 71 M.getPointerSize() != Module::AnyPointerSize) 72 return 0; // Match for some other target 73 74 return getJITMatchQuality()/2; 75 } 76 77 /// TargetMachine ctor - Create an ARM architecture model. 78 /// 79 ARMBaseTargetMachine::ARMBaseTargetMachine(const Module &M, 80 const std::string &FS, 81 bool isThumb) 82 : Subtarget(M, FS, isThumb), 83 FrameInfo(Subtarget), 84 JITInfo(), 85 InstrItins(Subtarget.getInstrItineraryData()) { 86 DefRelocModel = getRelocationModel(); 87 } 88 89 ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS) 90 : ARMBaseTargetMachine(M, FS, false), InstrInfo(Subtarget), 91 DataLayout(Subtarget.isAPCS_ABI() ? 92 std::string("e-p:32:32-f64:32:32-i64:32:32") : 93 std::string("e-p:32:32-f64:64:64-i64:64:64")), 94 TLInfo(*this) { 95 } 96 97 ThumbTargetMachine::ThumbTargetMachine(const Module &M, const std::string &FS) 98 : ARMBaseTargetMachine(M, FS, true), 99 DataLayout(Subtarget.isAPCS_ABI() ? 100 std::string("e-p:32:32-f64:32:32-i64:32:32-" 101 "i16:16:32-i8:8:32-i1:8:32-a:0:32") : 102 std::string("e-p:32:32-f64:64:64-i64:64:64-" 103 "i16:16:32-i8:8:32-i1:8:32-a:0:32")), 104 TLInfo(*this) { 105 // Create the approriate type of Thumb InstrInfo 106 if (Subtarget.hasThumb2()) 107 InstrInfo = new Thumb2InstrInfo(Subtarget); 108 else 109 InstrInfo = new Thumb1InstrInfo(Subtarget); 110 } 111 112 unsigned ARMTargetMachine::getJITMatchQuality() { 113 #if defined(__arm__) 114 return 10; 115 #endif 116 return 0; 117 } 118 119 unsigned ARMTargetMachine::getModuleMatchQuality(const Module &M) { 120 std::string TT = M.getTargetTriple(); 121 // Match arm-foo-bar, as well as things like armv5blah-* 122 if (TT.size() >= 4 && 123 (TT.substr(0, 4) == "arm-" || TT.substr(0, 4) == "armv")) 124 return 20; 125 // If the target triple is something non-arm, we don't match. 126 if (!TT.empty()) return 0; 127 128 if (M.getEndianness() == Module::LittleEndian && 129 M.getPointerSize() == Module::Pointer32) 130 return 10; // Weak match 131 else if (M.getEndianness() != Module::AnyEndianness || 132 M.getPointerSize() != Module::AnyPointerSize) 133 return 0; // Match for some other target 134 135 return getJITMatchQuality()/2; 136 } 137 138 139 const TargetAsmInfo *ARMBaseTargetMachine::createTargetAsmInfo() const { 140 switch (Subtarget.TargetType) { 141 case ARMSubtarget::isDarwin: 142 return new ARMDarwinTargetAsmInfo(*this); 143 case ARMSubtarget::isELF: 144 return new ARMELFTargetAsmInfo(*this); 145 default: 146 return new ARMGenericTargetAsmInfo(*this); 147 } 148 } 149 150 151 // Pass Pipeline Configuration 152 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM, 153 CodeGenOpt::Level OptLevel) { 154 PM.add(createARMISelDag(*this)); 155 return false; 156 } 157 158 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, 159 CodeGenOpt::Level OptLevel) { 160 // FIXME: temporarily disabling load / store optimization pass for Thumb mode. 161 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb()) 162 PM.add(createARMLoadStoreOptimizationPass(true)); 163 return true; 164 } 165 166 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, 167 CodeGenOpt::Level OptLevel) { 168 // FIXME: temporarily disabling load / store optimization pass for Thumb mode. 169 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb()) 170 PM.add(createARMLoadStoreOptimizationPass()); 171 172 if (OptLevel != CodeGenOpt::None && 173 !DisableIfConversion && !Subtarget.isThumb()) 174 PM.add(createIfConverterPass()); 175 176 PM.add(createARMConstantIslandPass()); 177 return true; 178 } 179 180 bool ARMBaseTargetMachine::addAssemblyEmitter(PassManagerBase &PM, 181 CodeGenOpt::Level OptLevel, 182 bool Verbose, 183 raw_ostream &Out) { 184 // Output assembly language. 185 assert(AsmPrinterCtor && "AsmPrinter was not linked in"); 186 if (AsmPrinterCtor) 187 PM.add(AsmPrinterCtor(Out, *this, Verbose)); 188 189 return false; 190 } 191 192 193 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 194 CodeGenOpt::Level OptLevel, 195 bool DumpAsm, 196 MachineCodeEmitter &MCE) { 197 // FIXME: Move this to TargetJITInfo! 198 if (DefRelocModel == Reloc::Default) 199 setRelocationModel(Reloc::Static); 200 201 // Machine code emitter pass for ARM. 202 PM.add(createARMCodeEmitterPass(*this, MCE)); 203 if (DumpAsm) { 204 assert(AsmPrinterCtor && "AsmPrinter was not linked in"); 205 if (AsmPrinterCtor) 206 PM.add(AsmPrinterCtor(errs(), *this, true)); 207 } 208 209 return false; 210 } 211 212 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 213 CodeGenOpt::Level OptLevel, 214 bool DumpAsm, 215 JITCodeEmitter &JCE) { 216 // FIXME: Move this to TargetJITInfo! 217 if (DefRelocModel == Reloc::Default) 218 setRelocationModel(Reloc::Static); 219 220 // Machine code emitter pass for ARM. 221 PM.add(createARMJITCodeEmitterPass(*this, JCE)); 222 if (DumpAsm) { 223 assert(AsmPrinterCtor && "AsmPrinter was not linked in"); 224 if (AsmPrinterCtor) 225 PM.add(AsmPrinterCtor(errs(), *this, true)); 226 } 227 228 return false; 229 } 230 231 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, 232 CodeGenOpt::Level OptLevel, 233 bool DumpAsm, 234 ObjectCodeEmitter &OCE) { 235 // FIXME: Move this to TargetJITInfo! 236 if (DefRelocModel == Reloc::Default) 237 setRelocationModel(Reloc::Static); 238 239 // Machine code emitter pass for ARM. 240 PM.add(createARMObjectCodeEmitterPass(*this, OCE)); 241 if (DumpAsm) { 242 assert(AsmPrinterCtor && "AsmPrinter was not linked in"); 243 if (AsmPrinterCtor) 244 PM.add(AsmPrinterCtor(errs(), *this, true)); 245 } 246 247 return false; 248 } 249 250 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, 251 CodeGenOpt::Level OptLevel, 252 bool DumpAsm, 253 MachineCodeEmitter &MCE) { 254 // Machine code emitter pass for ARM. 255 PM.add(createARMCodeEmitterPass(*this, MCE)); 256 if (DumpAsm) { 257 assert(AsmPrinterCtor && "AsmPrinter was not linked in"); 258 if (AsmPrinterCtor) 259 PM.add(AsmPrinterCtor(errs(), *this, true)); 260 } 261 262 return false; 263 } 264 265 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, 266 CodeGenOpt::Level OptLevel, 267 bool DumpAsm, 268 JITCodeEmitter &JCE) { 269 // Machine code emitter pass for ARM. 270 PM.add(createARMJITCodeEmitterPass(*this, JCE)); 271 if (DumpAsm) { 272 assert(AsmPrinterCtor && "AsmPrinter was not linked in"); 273 if (AsmPrinterCtor) 274 PM.add(AsmPrinterCtor(errs(), *this, true)); 275 } 276 277 return false; 278 } 279 280 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, 281 CodeGenOpt::Level OptLevel, 282 bool DumpAsm, 283 ObjectCodeEmitter &OCE) { 284 // Machine code emitter pass for ARM. 285 PM.add(createARMObjectCodeEmitterPass(*this, OCE)); 286 if (DumpAsm) { 287 assert(AsmPrinterCtor && "AsmPrinter was not linked in"); 288 if (AsmPrinterCtor) 289 PM.add(AsmPrinterCtor(errs(), *this, true)); 290 } 291 292 return false; 293 } 294 295