1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the ARM specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 16 17 18 #include "ARMFrameLowering.h" 19 #include "ARMISelLowering.h" 20 #include "ARMInstrInfo.h" 21 #include "ARMSelectionDAGInfo.h" 22 #include "ARMSubtarget.h" 23 #include "MCTargetDesc/ARMMCTargetDesc.h" 24 #include "Thumb1FrameLowering.h" 25 #include "Thumb1InstrInfo.h" 26 #include "Thumb2InstrInfo.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h" 29 #include "llvm/IR/DataLayout.h" 30 #include "llvm/MC/MCInstrItineraries.h" 31 #include "llvm/Target/TargetSubtargetInfo.h" 32 #include <string> 33 34 #define GET_SUBTARGETINFO_HEADER 35 #include "ARMGenSubtargetInfo.inc" 36 37 namespace llvm { 38 class GlobalValue; 39 class StringRef; 40 class TargetOptions; 41 class ARMBaseTargetMachine; 42 43 class ARMSubtarget : public ARMGenSubtargetInfo { 44 protected: 45 enum ARMProcFamilyEnum { 46 Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, 47 CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexR52, CortexM3, 48 CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73, 49 Krait, Swift, ExynosM1 50 }; 51 enum ARMProcClassEnum { 52 None, AClass, RClass, MClass 53 }; 54 enum ARMArchEnum { 55 ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te, 56 ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r, 57 ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline, 58 ARMv8r 59 }; 60 61 public: 62 /// What kind of timing do load multiple/store multiple instructions have. 63 enum ARMLdStMultipleTiming { 64 /// Can load/store 2 registers/cycle. 65 DoubleIssue, 66 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access 67 /// is not 64-bit aligned. 68 DoubleIssueCheckUnalignedAccess, 69 /// Can load/store 1 register/cycle. 70 SingleIssue, 71 /// Can load/store 1 register/cycle, but needs an extra cycle for address 72 /// computation and potentially also for register writeback. 73 SingleIssuePlusExtras, 74 }; 75 76 protected: 77 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 78 ARMProcFamilyEnum ARMProcFamily = Others; 79 80 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass. 81 ARMProcClassEnum ARMProcClass = None; 82 83 /// ARMArch - ARM architecture 84 ARMArchEnum ARMArch = ARMv4t; 85 86 /// HasV4TOps, HasV5TOps, HasV5TEOps, 87 /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - 88 /// Specify whether target support specific ARM ISA variants. 89 bool HasV4TOps = false; 90 bool HasV5TOps = false; 91 bool HasV5TEOps = false; 92 bool HasV6Ops = false; 93 bool HasV6MOps = false; 94 bool HasV6KOps = false; 95 bool HasV6T2Ops = false; 96 bool HasV7Ops = false; 97 bool HasV8Ops = false; 98 bool HasV8_1aOps = false; 99 bool HasV8_2aOps = false; 100 bool HasV8MBaselineOps = false; 101 bool HasV8MMainlineOps = false; 102 103 /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what 104 /// floating point ISAs are supported. 105 bool HasVFPv2 = false; 106 bool HasVFPv3 = false; 107 bool HasVFPv4 = false; 108 bool HasFPARMv8 = false; 109 bool HasNEON = false; 110 111 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 112 /// specified. Use the method useNEONForSinglePrecisionFP() to 113 /// determine if NEON should actually be used. 114 bool UseNEONForSinglePrecisionFP = false; 115 116 /// UseMulOps - True if non-microcoded fused integer multiply-add and 117 /// multiply-subtract instructions should be used. 118 bool UseMulOps = false; 119 120 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates 121 /// whether the FP VML[AS] instructions are slow (if so, don't use them). 122 bool SlowFPVMLx = false; 123 124 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator 125 /// forwarding to allow mul + mla being issued back to back. 126 bool HasVMLxForwarding = false; 127 128 /// SlowFPBrcc - True if floating point compare + branch is slow. 129 bool SlowFPBrcc = false; 130 131 /// InThumbMode - True if compiling for Thumb, false for ARM. 132 bool InThumbMode = false; 133 134 /// UseSoftFloat - True if we're using software floating point features. 135 bool UseSoftFloat = false; 136 137 /// HasThumb2 - True if Thumb2 instructions are supported. 138 bool HasThumb2 = false; 139 140 /// NoARM - True if subtarget does not support ARM mode execution. 141 bool NoARM = false; 142 143 /// ReserveR9 - True if R9 is not available as a general purpose register. 144 bool ReserveR9 = false; 145 146 /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of 147 /// 32-bit imms (including global addresses). 148 bool NoMovt = false; 149 150 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker 151 /// must be able to synthesize call stubs for interworking between ARM and 152 /// Thumb. 153 bool SupportsTailCall = false; 154 155 /// HasFP16 - True if subtarget supports half-precision FP conversions 156 bool HasFP16 = false; 157 158 /// HasFullFP16 - True if subtarget supports half-precision FP operations 159 bool HasFullFP16 = false; 160 161 /// HasD16 - True if subtarget is limited to 16 double precision 162 /// FP registers for VFPv3. 163 bool HasD16 = false; 164 165 /// HasHardwareDivide - True if subtarget supports [su]div 166 bool HasHardwareDivide = false; 167 168 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode 169 bool HasHardwareDivideInARM = false; 170 171 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 172 /// instructions. 173 bool HasT2ExtractPack = false; 174 175 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier 176 /// instructions. 177 bool HasDataBarrier = false; 178 179 /// HasV7Clrex - True if the subtarget supports CLREX instructions 180 bool HasV7Clrex = false; 181 182 /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) 183 /// instructions 184 bool HasAcquireRelease = false; 185 186 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions 187 /// over 16-bit ones. 188 bool Pref32BitThumb = false; 189 190 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions 191 /// that partially update CPSR and add false dependency on the previous 192 /// CPSR setting instruction. 193 bool AvoidCPSRPartialUpdate = false; 194 195 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting 196 /// movs with shifter operand (i.e. asr, lsl, lsr). 197 bool AvoidMOVsShifterOperand = false; 198 199 /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should 200 /// avoid issue "normal" call instructions to callees which do not return. 201 bool HasRetAddrStack = false; 202 203 /// HasMPExtension - True if the subtarget supports Multiprocessing 204 /// extension (ARMv7 only). 205 bool HasMPExtension = false; 206 207 /// HasVirtualization - True if the subtarget supports the Virtualization 208 /// extension. 209 bool HasVirtualization = false; 210 211 /// FPOnlySP - If true, the floating point unit only supports single 212 /// precision. 213 bool FPOnlySP = false; 214 215 /// If true, the processor supports the Performance Monitor Extensions. These 216 /// include a generic cycle-counter as well as more fine-grained (often 217 /// implementation-specific) events. 218 bool HasPerfMon = false; 219 220 /// HasTrustZone - if true, processor supports TrustZone security extensions 221 bool HasTrustZone = false; 222 223 /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions 224 bool Has8MSecExt = false; 225 226 /// HasCrypto - if true, processor supports Cryptography extensions 227 bool HasCrypto = false; 228 229 /// HasCRC - if true, processor supports CRC instructions 230 bool HasCRC = false; 231 232 /// HasRAS - if true, the processor supports RAS extensions 233 bool HasRAS = false; 234 235 /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are 236 /// particularly effective at zeroing a VFP register. 237 bool HasZeroCycleZeroing = false; 238 239 /// HasFPAO - if true, processor does positive address offset computation faster 240 bool HasFPAO = false; 241 242 /// If true, if conversion may decide to leave some instructions unpredicated. 243 bool IsProfitableToUnpredicate = false; 244 245 /// If true, VMOV will be favored over VGETLNi32. 246 bool HasSlowVGETLNi32 = false; 247 248 /// If true, VMOV will be favored over VDUP. 249 bool HasSlowVDUP32 = false; 250 251 /// If true, VMOVSR will be favored over VMOVDRR. 252 bool PreferVMOVSR = false; 253 254 /// If true, ISHST barriers will be used for Release semantics. 255 bool PreferISHST = false; 256 257 /// If true, a VLDM/VSTM starting with an odd register number is considered to 258 /// take more microops than single VLDRS/VSTRS. 259 bool SlowOddRegister = false; 260 261 /// If true, loading into a D subregister will be penalized. 262 bool SlowLoadDSubregister = false; 263 264 /// If true, the AGU and NEON/FPU units are multiplexed. 265 bool HasMuxedUnits = false; 266 267 /// If true, VMOVS will never be widened to VMOVD 268 bool DontWidenVMOVS = false; 269 270 /// If true, run the MLx expansion pass. 271 bool ExpandMLx = false; 272 273 /// If true, VFP/NEON VMLA/VMLS have special RAW hazards. 274 bool HasVMLxHazards = false; 275 276 /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON. 277 bool UseNEONForFPMovs = false; 278 279 /// If true, VLDn instructions take an extra cycle for unaligned accesses. 280 bool CheckVLDnAlign = false; 281 282 /// If true, VFP instructions are not pipelined. 283 bool NonpipelinedVFP = false; 284 285 /// StrictAlign - If true, the subtarget disallows unaligned memory 286 /// accesses for some types. For details, see 287 /// ARMTargetLowering::allowsMisalignedMemoryAccesses(). 288 bool StrictAlign = false; 289 290 /// RestrictIT - If true, the subtarget disallows generation of deprecated IT 291 /// blocks to conform to ARMv8 rule. 292 bool RestrictIT = false; 293 294 /// HasDSP - If true, the subtarget supports the DSP (saturating arith 295 /// and such) instructions. 296 bool HasDSP = false; 297 298 /// NaCl TRAP instruction is generated instead of the regular TRAP. 299 bool UseNaClTrap = false; 300 301 /// Generate calls via indirect call instructions. 302 bool GenLongCalls = false; 303 304 /// Target machine allowed unsafe FP math (such as use of NEON fp) 305 bool UnsafeFPMath = false; 306 307 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS). 308 bool UseSjLjEH = false; 309 310 /// stackAlignment - The minimum alignment known to hold of the stack frame on 311 /// entry to the function and which must be maintained by every function. 312 unsigned stackAlignment = 4; 313 314 /// CPUString - String name of used CPU. 315 std::string CPUString; 316 317 unsigned MaxInterleaveFactor = 1; 318 319 /// Clearance before partial register updates (in number of instructions) 320 unsigned PartialUpdateClearance = 0; 321 322 /// What kind of timing do load multiple/store multiple have (double issue, 323 /// single issue etc). 324 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue; 325 326 /// The adjustment that we need to apply to get the operand latency from the 327 /// operand cycle returned by the itinerary data for pre-ISel operands. 328 int PreISelOperandLatencyAdjustment = 2; 329 330 /// IsLittle - The target is Little Endian 331 bool IsLittle; 332 333 /// TargetTriple - What processor and OS we're targeting. 334 Triple TargetTriple; 335 336 /// SchedModel - Processor specific instruction costs. 337 MCSchedModel SchedModel; 338 339 /// Selected instruction itineraries (one entry per itinerary class.) 340 InstrItineraryData InstrItins; 341 342 /// Options passed via command line that could influence the target 343 const TargetOptions &Options; 344 345 const ARMBaseTargetMachine &TM; 346 347 public: 348 /// This constructor initializes the data members to match that 349 /// of the specified triple. 350 /// 351 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, 352 const ARMBaseTargetMachine &TM, bool IsLittle); 353 354 /// This object will take onwership of \p GISelAccessor. 355 void setGISelAccessor(GISelAccessor &GISel) { this->GISel.reset(&GISel); } 356 357 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 358 /// that still makes it profitable to inline the call. 359 unsigned getMaxInlineSizeThreshold() const { 360 return 64; 361 } 362 /// ParseSubtargetFeatures - Parses features string setting specified 363 /// subtarget options. Definition of function is auto generated by tblgen. 364 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 365 366 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 367 /// so that we can use initializer lists for subtarget initialization. 368 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 369 370 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override { 371 return &TSInfo; 372 } 373 const ARMBaseInstrInfo *getInstrInfo() const override { 374 return InstrInfo.get(); 375 } 376 const ARMTargetLowering *getTargetLowering() const override { 377 return &TLInfo; 378 } 379 const ARMFrameLowering *getFrameLowering() const override { 380 return FrameLowering.get(); 381 } 382 const ARMBaseRegisterInfo *getRegisterInfo() const override { 383 return &InstrInfo->getRegisterInfo(); 384 } 385 386 const CallLowering *getCallLowering() const override; 387 const InstructionSelector *getInstructionSelector() const override; 388 const LegalizerInfo *getLegalizerInfo() const override; 389 const RegisterBankInfo *getRegBankInfo() const override; 390 391 private: 392 ARMSelectionDAGInfo TSInfo; 393 // Either Thumb1FrameLowering or ARMFrameLowering. 394 std::unique_ptr<ARMFrameLowering> FrameLowering; 395 // Either Thumb1InstrInfo or Thumb2InstrInfo. 396 std::unique_ptr<ARMBaseInstrInfo> InstrInfo; 397 ARMTargetLowering TLInfo; 398 399 /// Gather the accessor points to GlobalISel-related APIs. 400 /// This is used to avoid ifndefs spreading around while GISel is 401 /// an optional library. 402 std::unique_ptr<GISelAccessor> GISel; 403 404 void initializeEnvironment(); 405 void initSubtargetFeatures(StringRef CPU, StringRef FS); 406 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS); 407 408 public: 409 void computeIssueWidth(); 410 411 bool hasV4TOps() const { return HasV4TOps; } 412 bool hasV5TOps() const { return HasV5TOps; } 413 bool hasV5TEOps() const { return HasV5TEOps; } 414 bool hasV6Ops() const { return HasV6Ops; } 415 bool hasV6MOps() const { return HasV6MOps; } 416 bool hasV6KOps() const { return HasV6KOps; } 417 bool hasV6T2Ops() const { return HasV6T2Ops; } 418 bool hasV7Ops() const { return HasV7Ops; } 419 bool hasV8Ops() const { return HasV8Ops; } 420 bool hasV8_1aOps() const { return HasV8_1aOps; } 421 bool hasV8_2aOps() const { return HasV8_2aOps; } 422 bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } 423 bool hasV8MMainlineOps() const { return HasV8MMainlineOps; } 424 425 /// @{ 426 /// These functions are obsolete, please consider adding subtarget features 427 /// or properties instead of calling them. 428 bool isCortexA5() const { return ARMProcFamily == CortexA5; } 429 bool isCortexA7() const { return ARMProcFamily == CortexA7; } 430 bool isCortexA8() const { return ARMProcFamily == CortexA8; } 431 bool isCortexA9() const { return ARMProcFamily == CortexA9; } 432 bool isCortexA15() const { return ARMProcFamily == CortexA15; } 433 bool isSwift() const { return ARMProcFamily == Swift; } 434 bool isCortexM3() const { return ARMProcFamily == CortexM3; } 435 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); } 436 bool isCortexR5() const { return ARMProcFamily == CortexR5; } 437 bool isKrait() const { return ARMProcFamily == Krait; } 438 /// @} 439 440 bool hasARMOps() const { return !NoARM; } 441 442 bool hasVFP2() const { return HasVFPv2; } 443 bool hasVFP3() const { return HasVFPv3; } 444 bool hasVFP4() const { return HasVFPv4; } 445 bool hasFPARMv8() const { return HasFPARMv8; } 446 bool hasNEON() const { return HasNEON; } 447 bool hasCrypto() const { return HasCrypto; } 448 bool hasCRC() const { return HasCRC; } 449 bool hasRAS() const { return HasRAS; } 450 bool hasVirtualization() const { return HasVirtualization; } 451 bool useNEONForSinglePrecisionFP() const { 452 return hasNEON() && UseNEONForSinglePrecisionFP; 453 } 454 455 bool hasDivide() const { return HasHardwareDivide; } 456 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; } 457 bool hasT2ExtractPack() const { return HasT2ExtractPack; } 458 bool hasDataBarrier() const { return HasDataBarrier; } 459 bool hasV7Clrex() const { return HasV7Clrex; } 460 bool hasAcquireRelease() const { return HasAcquireRelease; } 461 bool hasAnyDataBarrier() const { 462 return HasDataBarrier || (hasV6Ops() && !isThumb()); 463 } 464 bool useMulOps() const { return UseMulOps; } 465 bool useFPVMLx() const { return !SlowFPVMLx; } 466 bool hasVMLxForwarding() const { return HasVMLxForwarding; } 467 bool isFPBrccSlow() const { return SlowFPBrcc; } 468 bool isFPOnlySP() const { return FPOnlySP; } 469 bool hasPerfMon() const { return HasPerfMon; } 470 bool hasTrustZone() const { return HasTrustZone; } 471 bool has8MSecExt() const { return Has8MSecExt; } 472 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; } 473 bool hasFPAO() const { return HasFPAO; } 474 bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; } 475 bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; } 476 bool hasSlowVDUP32() const { return HasSlowVDUP32; } 477 bool preferVMOVSR() const { return PreferVMOVSR; } 478 bool preferISHSTBarriers() const { return PreferISHST; } 479 bool expandMLx() const { return ExpandMLx; } 480 bool hasVMLxHazards() const { return HasVMLxHazards; } 481 bool hasSlowOddRegister() const { return SlowOddRegister; } 482 bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; } 483 bool hasMuxedUnits() const { return HasMuxedUnits; } 484 bool dontWidenVMOVS() const { return DontWidenVMOVS; } 485 bool useNEONForFPMovs() const { return UseNEONForFPMovs; } 486 bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; } 487 bool nonpipelinedVFP() const { return NonpipelinedVFP; } 488 bool prefers32BitThumb() const { return Pref32BitThumb; } 489 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } 490 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; } 491 bool hasRetAddrStack() const { return HasRetAddrStack; } 492 bool hasMPExtension() const { return HasMPExtension; } 493 bool hasDSP() const { return HasDSP; } 494 bool useNaClTrap() const { return UseNaClTrap; } 495 bool useSjLjEH() const { return UseSjLjEH; } 496 bool genLongCalls() const { return GenLongCalls; } 497 498 bool hasFP16() const { return HasFP16; } 499 bool hasD16() const { return HasD16; } 500 bool hasFullFP16() const { return HasFullFP16; } 501 502 const Triple &getTargetTriple() const { return TargetTriple; } 503 504 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 505 bool isTargetIOS() const { return TargetTriple.isiOS(); } 506 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); } 507 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); } 508 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } 509 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 510 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); } 511 bool isTargetWindows() const { return TargetTriple.isOSWindows(); } 512 513 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 514 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 515 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 516 517 // ARM EABI is the bare-metal EABI described in ARM ABI documents and 518 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI. 519 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI 520 // even for GNUEABI, so we can make a distinction here and still conform to 521 // the EABI on GNU (and Android) mode. This requires change in Clang, too. 522 // FIXME: The Darwin exception is temporary, while we move users to 523 // "*-*-*-macho" triples as quickly as possible. 524 bool isTargetAEABI() const { 525 return (TargetTriple.getEnvironment() == Triple::EABI || 526 TargetTriple.getEnvironment() == Triple::EABIHF) && 527 !isTargetDarwin() && !isTargetWindows(); 528 } 529 bool isTargetGNUAEABI() const { 530 return (TargetTriple.getEnvironment() == Triple::GNUEABI || 531 TargetTriple.getEnvironment() == Triple::GNUEABIHF) && 532 !isTargetDarwin() && !isTargetWindows(); 533 } 534 bool isTargetMuslAEABI() const { 535 return (TargetTriple.getEnvironment() == Triple::MuslEABI || 536 TargetTriple.getEnvironment() == Triple::MuslEABIHF) && 537 !isTargetDarwin() && !isTargetWindows(); 538 } 539 540 // ARM Targets that support EHABI exception handling standard 541 // Darwin uses SjLj. Other targets might need more checks. 542 bool isTargetEHABICompatible() const { 543 return (TargetTriple.getEnvironment() == Triple::EABI || 544 TargetTriple.getEnvironment() == Triple::GNUEABI || 545 TargetTriple.getEnvironment() == Triple::MuslEABI || 546 TargetTriple.getEnvironment() == Triple::EABIHF || 547 TargetTriple.getEnvironment() == Triple::GNUEABIHF || 548 TargetTriple.getEnvironment() == Triple::MuslEABIHF || 549 isTargetAndroid()) && 550 !isTargetDarwin() && !isTargetWindows(); 551 } 552 553 bool isTargetHardFloat() const { 554 // FIXME: this is invalid for WindowsCE 555 return TargetTriple.getEnvironment() == Triple::GNUEABIHF || 556 TargetTriple.getEnvironment() == Triple::MuslEABIHF || 557 TargetTriple.getEnvironment() == Triple::EABIHF || 558 isTargetWindows() || isAAPCS16_ABI(); 559 } 560 bool isTargetAndroid() const { return TargetTriple.isAndroid(); } 561 562 virtual bool isXRaySupported() const override; 563 564 bool isAPCS_ABI() const; 565 bool isAAPCS_ABI() const; 566 bool isAAPCS16_ABI() const; 567 568 bool isROPI() const; 569 bool isRWPI() const; 570 571 bool useSoftFloat() const { return UseSoftFloat; } 572 bool isThumb() const { return InThumbMode; } 573 bool isThumb1Only() const { return InThumbMode && !HasThumb2; } 574 bool isThumb2() const { return InThumbMode && HasThumb2; } 575 bool hasThumb2() const { return HasThumb2; } 576 bool isMClass() const { return ARMProcClass == MClass; } 577 bool isRClass() const { return ARMProcClass == RClass; } 578 bool isAClass() const { return ARMProcClass == AClass; } 579 580 bool isR9Reserved() const { 581 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9; 582 } 583 584 bool useR7AsFramePointer() const { 585 return isTargetDarwin() || (!isTargetWindows() && isThumb()); 586 } 587 /// Returns true if the frame setup is split into two separate pushes (first 588 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent 589 /// to lr. This is always required on Thumb1-only targets, as the push and 590 /// pop instructions can't access the high registers. 591 bool splitFramePushPop(const MachineFunction &MF) const { 592 return (useR7AsFramePointer() && 593 MF.getTarget().Options.DisableFramePointerElim(MF)) || 594 isThumb1Only(); 595 } 596 597 bool useStride4VFPs(const MachineFunction &MF) const; 598 599 bool useMovt(const MachineFunction &MF) const; 600 601 bool supportsTailCall() const { return SupportsTailCall; } 602 603 bool allowsUnalignedMem() const { return !StrictAlign; } 604 605 bool restrictIT() const { return RestrictIT; } 606 607 const std::string & getCPUString() const { return CPUString; } 608 609 bool isLittle() const { return IsLittle; } 610 611 unsigned getMispredictionPenalty() const; 612 613 /// This function returns true if the target has sincos() routine in its 614 /// compiler runtime or math libraries. 615 bool hasSinCos() const; 616 617 /// Returns true if machine scheduler should be enabled. 618 bool enableMachineScheduler() const override; 619 620 /// True for some subtargets at > -O0. 621 bool enablePostRAScheduler() const override; 622 623 // enableAtomicExpand- True if we need to expand our atomics. 624 bool enableAtomicExpand() const override; 625 626 /// getInstrItins - Return the instruction itineraries based on subtarget 627 /// selection. 628 const InstrItineraryData *getInstrItineraryData() const override { 629 return &InstrItins; 630 } 631 632 /// getStackAlignment - Returns the minimum alignment known to hold of the 633 /// stack frame on entry to the function and which must be maintained by every 634 /// function for this subtarget. 635 unsigned getStackAlignment() const { return stackAlignment; } 636 637 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; } 638 639 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; } 640 641 ARMLdStMultipleTiming getLdStMultipleTiming() const { 642 return LdStMultipleTiming; 643 } 644 645 int getPreISelOperandLatencyAdjustment() const { 646 return PreISelOperandLatencyAdjustment; 647 } 648 649 /// True if the GV will be accessed via an indirect symbol. 650 bool isGVIndirectSymbol(const GlobalValue *GV) const; 651 652 /// True if fast-isel is used. 653 bool useFastISel() const; 654 }; 655 } // End llvm namespace 656 657 #endif // ARMSUBTARGET_H 658