1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/GlobalValue.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "arm-subtarget"
39 
40 #define GET_SUBTARGETINFO_TARGET_DESC
41 #define GET_SUBTARGETINFO_CTOR
42 #include "ARMGenSubtargetInfo.inc"
43 
44 static cl::opt<bool>
45 UseFusedMulOps("arm-use-mulops",
46                cl::init(true), cl::Hidden);
47 
48 enum ITMode {
49   DefaultIT,
50   RestrictedIT,
51   NoRestrictedIT
52 };
53 
54 static cl::opt<ITMode>
55 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
56    cl::ZeroOrMore,
57    cl::values(clEnumValN(DefaultIT, "arm-default-it",
58                          "Generate IT block based on arch"),
59               clEnumValN(RestrictedIT, "arm-restrict-it",
60                          "Disallow deprecated IT based on ARMv8"),
61               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
62                          "Allow IT blocks based on ARMv7"),
63               clEnumValEnd));
64 
65 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
66 /// currently supported (for testing only).
67 static cl::opt<bool>
68 ForceFastISel("arm-force-fast-isel",
69                cl::init(false), cl::Hidden);
70 
71 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
72 /// so that we can use initializer lists for subtarget initialization.
73 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
74                                                             StringRef FS) {
75   initializeEnvironment();
76   initSubtargetFeatures(CPU, FS);
77   return *this;
78 }
79 
80 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
81                                                         StringRef FS) {
82   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
83   if (STI.isThumb1Only())
84     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
85 
86   return new ARMFrameLowering(STI);
87 }
88 
89 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
90                            const std::string &FS,
91                            const ARMBaseTargetMachine &TM, bool IsLittle)
92     : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
93       CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
94       TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
95       // At this point initializeSubtargetDependencies has been called so
96       // we can query directly.
97       InstrInfo(isThumb1Only()
98                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
99                     : !isThumb()
100                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
101                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
102       TLInfo(TM, *this) {}
103 
104 void ARMSubtarget::initializeEnvironment() {
105   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
106   // directly from it, but we can try to make sure they're consistent when both
107   // available.
108   UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
109   assert((!TM.getMCAsmInfo() ||
110           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
111            ExceptionHandling::SjLj) == UseSjLjEH) &&
112          "inconsistent sjlj choice between CodeGen and MC");
113 }
114 
115 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
116   if (CPUString.empty()) {
117     CPUString = "generic";
118 
119     if (isTargetDarwin()) {
120       StringRef ArchName = TargetTriple.getArchName();
121       if (ArchName.endswith("v7s"))
122         // Default to the Swift CPU when targeting armv7s/thumbv7s.
123         CPUString = "swift";
124       else if (ArchName.endswith("v7k"))
125         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
126         // ARMv7k does not use SjLj exception handling.
127         CPUString = "cortex-a7";
128     }
129   }
130 
131   // Insert the architecture feature derived from the target triple into the
132   // feature string. This is important for setting features that are implied
133   // based on the architecture version.
134   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
135   if (!FS.empty()) {
136     if (!ArchFS.empty())
137       ArchFS = (Twine(ArchFS) + "," + FS).str();
138     else
139       ArchFS = FS;
140   }
141   ParseSubtargetFeatures(CPUString, ArchFS);
142 
143   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
144   // Assert this for now to make the change obvious.
145   assert(hasV6T2Ops() || !hasThumb2());
146 
147   // Keep a pointer to static instruction cost data for the specified CPU.
148   SchedModel = getSchedModelForCPU(CPUString);
149 
150   // Initialize scheduling itinerary for the specified CPU.
151   InstrItins = getInstrItineraryForCPU(CPUString);
152 
153   // FIXME: this is invalid for WindowsCE
154   if (isTargetWindows())
155     NoARM = true;
156 
157   if (isAAPCS_ABI())
158     stackAlignment = 8;
159   if (isTargetNaCl() || isAAPCS16_ABI())
160     stackAlignment = 16;
161 
162   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
163   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
164   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
165   // support in the assembler and linker to be used. This would need to be
166   // fixed to fully support tail calls in Thumb1.
167   //
168   // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
169   // LR.  This means if we need to reload LR, it takes an extra instructions,
170   // which outweighs the value of the tail call; but here we don't know yet
171   // whether LR is going to be used.  Probably the right approach is to
172   // generate the tail call here and turn it back into CALL/RET in
173   // emitEpilogue if LR is used.
174 
175   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
176   // but we need to make sure there are enough registers; the only valid
177   // registers are the 4 used for parameters.  We don't currently do this
178   // case.
179 
180   SupportsTailCall = !isThumb() || hasV8MBaselineOps();
181 
182   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
183     SupportsTailCall = false;
184 
185   switch (IT) {
186   case DefaultIT:
187     RestrictIT = hasV8Ops();
188     break;
189   case RestrictedIT:
190     RestrictIT = true;
191     break;
192   case NoRestrictedIT:
193     RestrictIT = false;
194     break;
195   }
196 
197   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
198   const FeatureBitset &Bits = getFeatureBits();
199   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
200       (Options.UnsafeFPMath || isTargetDarwin()))
201     UseNEONForSinglePrecisionFP = true;
202 
203   // FIXME: Teach TableGen to deal with these instead of doing it manually here.
204   switch (ARMProcFamily) {
205   case Others:
206   case CortexA5:
207     break;
208   case CortexA7:
209     LdStMultipleTiming = DoubleIssue;
210     break;
211   case CortexA8:
212     LdStMultipleTiming = DoubleIssue;
213     break;
214   case CortexA9:
215     LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
216     PreISelOperandLatencyAdjustment = 1;
217     break;
218   case CortexA12:
219     break;
220   case CortexA15:
221     MaxInterleaveFactor = 2;
222     PreISelOperandLatencyAdjustment = 1;
223     break;
224   case CortexA17:
225   case CortexA32:
226   case CortexA35:
227   case CortexA53:
228   case CortexA57:
229   case CortexA72:
230   case CortexA73:
231   case CortexR4:
232   case CortexR4F:
233   case CortexR5:
234   case CortexR7:
235   case CortexM3:
236   case ExynosM1:
237     break;
238   case Krait:
239     PreISelOperandLatencyAdjustment = 1;
240     break;
241   case Swift:
242     MaxInterleaveFactor = 2;
243     LdStMultipleTiming = SingleIssuePlusExtras;
244     PreISelOperandLatencyAdjustment = 1;
245     break;
246   }
247 }
248 
249 bool ARMSubtarget::isAPCS_ABI() const {
250   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
251   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
252 }
253 bool ARMSubtarget::isAAPCS_ABI() const {
254   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
255   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
256          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
257 }
258 bool ARMSubtarget::isAAPCS16_ABI() const {
259   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
260   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
261 }
262 
263 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
264   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
265     return true;
266 
267   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
268   // the section that is being relocated. This means we have to use o load even
269   // for GVs that are known to be local to the dso.
270   if (isTargetDarwin() && TM.isPositionIndependent() &&
271       (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
272     return true;
273 
274   return false;
275 }
276 
277 unsigned ARMSubtarget::getMispredictionPenalty() const {
278   return SchedModel.MispredictPenalty;
279 }
280 
281 bool ARMSubtarget::hasSinCos() const {
282   return isTargetWatchOS() ||
283     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
284 }
285 
286 bool ARMSubtarget::enableMachineScheduler() const {
287   // Enable the MachineScheduler before register allocation for out-of-order
288   // architectures where we do not use the PostRA scheduler anymore (for now
289   // restricted to swift).
290   return getSchedModel().isOutOfOrder() && isSwift();
291 }
292 
293 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
294 bool ARMSubtarget::enablePostRAScheduler() const {
295   // No need for PostRA scheduling on out of order CPUs (for now restricted to
296   // swift).
297   if (getSchedModel().isOutOfOrder() && isSwift())
298     return false;
299   return (!isThumb() || hasThumb2());
300 }
301 
302 bool ARMSubtarget::enableAtomicExpand() const {
303   return hasAnyDataBarrier() && (!isThumb() || hasV8MBaselineOps());
304 }
305 
306 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
307   // For general targets, the prologue can grow when VFPs are allocated with
308   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
309   // format which it's more important to get right.
310   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
311 }
312 
313 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
314   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
315   // immediates as it is inherently position independent, and may be out of
316   // range otherwise.
317   return !NoMovt && hasV8MBaselineOps() &&
318          (isTargetWindows() || !MF.getFunction()->optForMinSize());
319 }
320 
321 bool ARMSubtarget::useFastISel() const {
322   // Enable fast-isel for any target, for testing only.
323   if (ForceFastISel)
324     return true;
325 
326   // Limit fast-isel to the targets that are or have been tested.
327   if (!hasV6Ops())
328     return false;
329 
330   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
331   return TM.Options.EnableFastISel &&
332          ((isTargetMachO() && !isThumb1Only()) ||
333           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
334 }
335