1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 
16 #ifdef LLVM_BUILD_GLOBAL_ISEL
17 #include "ARMCallLowering.h"
18 #include "ARMLegalizerInfo.h"
19 #include "ARMRegisterBankInfo.h"
20 #endif
21 #include "ARMSubtarget.h"
22 #include "ARMFrameLowering.h"
23 #include "ARMInstrInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "MCTargetDesc/ARMMCTargetDesc.h"
27 #include "Thumb1FrameLowering.h"
28 #include "Thumb1InstrInfo.h"
29 #include "Thumb2InstrInfo.h"
30 #include "llvm/ADT/StringRef.h"
31 #include "llvm/ADT/Triple.h"
32 #include "llvm/ADT/Twine.h"
33 #ifdef LLVM_BUILD_GLOBAL_ISEL
34 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
35 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
36 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
37 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
38 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
39 #endif
40 #include "llvm/CodeGen/MachineFunction.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalValue.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCTargetOptions.h"
45 #include "llvm/Support/CodeGen.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/TargetParser.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include <cassert>
50 #include <string>
51 
52 using namespace llvm;
53 
54 #define DEBUG_TYPE "arm-subtarget"
55 
56 #define GET_SUBTARGETINFO_TARGET_DESC
57 #define GET_SUBTARGETINFO_CTOR
58 #include "ARMGenSubtargetInfo.inc"
59 
60 static cl::opt<bool>
61 UseFusedMulOps("arm-use-mulops",
62                cl::init(true), cl::Hidden);
63 
64 enum ITMode {
65   DefaultIT,
66   RestrictedIT,
67   NoRestrictedIT
68 };
69 
70 static cl::opt<ITMode>
71 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
72    cl::ZeroOrMore,
73    cl::values(clEnumValN(DefaultIT, "arm-default-it",
74                          "Generate IT block based on arch"),
75               clEnumValN(RestrictedIT, "arm-restrict-it",
76                          "Disallow deprecated IT based on ARMv8"),
77               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
78                          "Allow IT blocks based on ARMv7")));
79 
80 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
81 /// currently supported (for testing only).
82 static cl::opt<bool>
83 ForceFastISel("arm-force-fast-isel",
84                cl::init(false), cl::Hidden);
85 
86 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
87 /// so that we can use initializer lists for subtarget initialization.
88 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
89                                                             StringRef FS) {
90   initializeEnvironment();
91   initSubtargetFeatures(CPU, FS);
92   return *this;
93 }
94 
95 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
96                                                         StringRef FS) {
97   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
98   if (STI.isThumb1Only())
99     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
100 
101   return new ARMFrameLowering(STI);
102 }
103 
104 #ifdef LLVM_BUILD_GLOBAL_ISEL
105 namespace {
106 
107 struct ARMGISelActualAccessor : public GISelAccessor {
108   std::unique_ptr<CallLowering> CallLoweringInfo;
109   std::unique_ptr<InstructionSelector> InstSelector;
110   std::unique_ptr<LegalizerInfo> Legalizer;
111   std::unique_ptr<RegisterBankInfo> RegBankInfo;
112 
113   const CallLowering *getCallLowering() const override {
114     return CallLoweringInfo.get();
115   }
116 
117   const InstructionSelector *getInstructionSelector() const override {
118     return InstSelector.get();
119   }
120 
121   const LegalizerInfo *getLegalizerInfo() const override {
122     return Legalizer.get();
123   }
124 
125   const RegisterBankInfo *getRegBankInfo() const override {
126     return RegBankInfo.get();
127   }
128 };
129 
130 } // end anonymous namespace
131 #endif
132 
133 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
134                            const std::string &FS,
135                            const ARMBaseTargetMachine &TM, bool IsLittle)
136     : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
137       CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
138       TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
139       // At this point initializeSubtargetDependencies has been called so
140       // we can query directly.
141       InstrInfo(isThumb1Only()
142                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
143                     : !isThumb()
144                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
145                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
146       TLInfo(TM, *this) {
147   assert((isThumb() || hasARMOps()) &&
148          "Target must either be thumb or support ARM operations!");
149 
150 #ifndef LLVM_BUILD_GLOBAL_ISEL
151   GISelAccessor *GISel = new GISelAccessor();
152 #else
153   ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor();
154   GISel->CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
155   GISel->Legalizer.reset(new ARMLegalizerInfo(*this));
156 
157   auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
158 
159   // FIXME: At this point, we can't rely on Subtarget having RBI.
160   // It's awkward to mix passing RBI and the Subtarget; should we pass
161   // TII/TRI as well?
162   GISel->InstSelector.reset(createARMInstructionSelector(
163       *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
164 
165   GISel->RegBankInfo.reset(RBI);
166 #endif
167   setGISelAccessor(*GISel);
168 }
169 
170 const CallLowering *ARMSubtarget::getCallLowering() const {
171   assert(GISel && "Access to GlobalISel APIs not set");
172   return GISel->getCallLowering();
173 }
174 
175 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
176   assert(GISel && "Access to GlobalISel APIs not set");
177   return GISel->getInstructionSelector();
178 }
179 
180 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
181   assert(GISel && "Access to GlobalISel APIs not set");
182   return GISel->getLegalizerInfo();
183 }
184 
185 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
186   assert(GISel && "Access to GlobalISel APIs not set");
187   return GISel->getRegBankInfo();
188 }
189 
190 bool ARMSubtarget::isXRaySupported() const {
191   // We don't currently suppport Thumb, but Windows requires Thumb.
192   return hasV6Ops() && hasARMOps() && !isTargetWindows();
193 }
194 
195 void ARMSubtarget::initializeEnvironment() {
196   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
197   // directly from it, but we can try to make sure they're consistent when both
198   // available.
199   UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
200   assert((!TM.getMCAsmInfo() ||
201           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
202            ExceptionHandling::SjLj) == UseSjLjEH) &&
203          "inconsistent sjlj choice between CodeGen and MC");
204 }
205 
206 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
207   if (CPUString.empty()) {
208     CPUString = "generic";
209 
210     if (isTargetDarwin()) {
211       StringRef ArchName = TargetTriple.getArchName();
212       unsigned ArchKind = ARM::parseArch(ArchName);
213       if (ArchKind == ARM::AK_ARMV7S)
214         // Default to the Swift CPU when targeting armv7s/thumbv7s.
215         CPUString = "swift";
216       else if (ArchKind == ARM::AK_ARMV7K)
217         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
218         // ARMv7k does not use SjLj exception handling.
219         CPUString = "cortex-a7";
220     }
221   }
222 
223   // Insert the architecture feature derived from the target triple into the
224   // feature string. This is important for setting features that are implied
225   // based on the architecture version.
226   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
227   if (!FS.empty()) {
228     if (!ArchFS.empty())
229       ArchFS = (Twine(ArchFS) + "," + FS).str();
230     else
231       ArchFS = FS;
232   }
233   ParseSubtargetFeatures(CPUString, ArchFS);
234 
235   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
236   // Assert this for now to make the change obvious.
237   assert(hasV6T2Ops() || !hasThumb2());
238 
239   // Execute only support requires movt support
240   if (genExecuteOnly())
241     assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
242 
243   // Keep a pointer to static instruction cost data for the specified CPU.
244   SchedModel = getSchedModelForCPU(CPUString);
245 
246   // Initialize scheduling itinerary for the specified CPU.
247   InstrItins = getInstrItineraryForCPU(CPUString);
248 
249   // FIXME: this is invalid for WindowsCE
250   if (isTargetWindows())
251     NoARM = true;
252 
253   if (isAAPCS_ABI())
254     stackAlignment = 8;
255   if (isTargetNaCl() || isAAPCS16_ABI())
256     stackAlignment = 16;
257 
258   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
259   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
260   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
261   // support in the assembler and linker to be used. This would need to be
262   // fixed to fully support tail calls in Thumb1.
263   //
264   // For ARMv8-M, we /do/ implement tail calls.  Doing this is tricky for v8-M
265   // baseline, since the LDM/POP instruction on Thumb doesn't take LR.  This
266   // means if we need to reload LR, it takes extra instructions, which outweighs
267   // the value of the tail call; but here we don't know yet whether LR is going
268   // to be used. We generate the tail call here and turn it back into CALL/RET
269   // in emitEpilogue if LR is used.
270 
271   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
272   // but we need to make sure there are enough registers; the only valid
273   // registers are the 4 used for parameters.  We don't currently do this
274   // case.
275 
276   SupportsTailCall = !isThumb() || hasV8MBaselineOps();
277 
278   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
279     SupportsTailCall = false;
280 
281   switch (IT) {
282   case DefaultIT:
283     RestrictIT = hasV8Ops();
284     break;
285   case RestrictedIT:
286     RestrictIT = true;
287     break;
288   case NoRestrictedIT:
289     RestrictIT = false;
290     break;
291   }
292 
293   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
294   const FeatureBitset &Bits = getFeatureBits();
295   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
296       (Options.UnsafeFPMath || isTargetDarwin()))
297     UseNEONForSinglePrecisionFP = true;
298 
299   if (isRWPI())
300     ReserveR9 = true;
301 
302   // FIXME: Teach TableGen to deal with these instead of doing it manually here.
303   switch (ARMProcFamily) {
304   case Others:
305   case CortexA5:
306     break;
307   case CortexA7:
308     LdStMultipleTiming = DoubleIssue;
309     break;
310   case CortexA8:
311     LdStMultipleTiming = DoubleIssue;
312     break;
313   case CortexA9:
314     LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
315     PreISelOperandLatencyAdjustment = 1;
316     break;
317   case CortexA12:
318     break;
319   case CortexA15:
320     MaxInterleaveFactor = 2;
321     PreISelOperandLatencyAdjustment = 1;
322     PartialUpdateClearance = 12;
323     break;
324   case CortexA17:
325   case CortexA32:
326   case CortexA35:
327   case CortexA53:
328   case CortexA57:
329   case CortexA72:
330   case CortexA73:
331   case CortexR4:
332   case CortexR4F:
333   case CortexR5:
334   case CortexR7:
335   case CortexM3:
336   case ExynosM1:
337   case CortexR52:
338   case Kryo:
339     break;
340   case Krait:
341     PreISelOperandLatencyAdjustment = 1;
342     break;
343   case Swift:
344     MaxInterleaveFactor = 2;
345     LdStMultipleTiming = SingleIssuePlusExtras;
346     PreISelOperandLatencyAdjustment = 1;
347     PartialUpdateClearance = 12;
348     break;
349   }
350 }
351 
352 bool ARMSubtarget::isAPCS_ABI() const {
353   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
354   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
355 }
356 bool ARMSubtarget::isAAPCS_ABI() const {
357   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
358   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
359          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
360 }
361 bool ARMSubtarget::isAAPCS16_ABI() const {
362   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
363   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
364 }
365 
366 bool ARMSubtarget::isROPI() const {
367   return TM.getRelocationModel() == Reloc::ROPI ||
368          TM.getRelocationModel() == Reloc::ROPI_RWPI;
369 }
370 bool ARMSubtarget::isRWPI() const {
371   return TM.getRelocationModel() == Reloc::RWPI ||
372          TM.getRelocationModel() == Reloc::ROPI_RWPI;
373 }
374 
375 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
376   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
377     return true;
378 
379   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
380   // the section that is being relocated. This means we have to use o load even
381   // for GVs that are known to be local to the dso.
382   if (isTargetMachO() && TM.isPositionIndependent() &&
383       (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
384     return true;
385 
386   return false;
387 }
388 
389 unsigned ARMSubtarget::getMispredictionPenalty() const {
390   return SchedModel.MispredictPenalty;
391 }
392 
393 bool ARMSubtarget::hasSinCos() const {
394   return isTargetWatchOS() ||
395     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
396 }
397 
398 bool ARMSubtarget::enableMachineScheduler() const {
399   // Enable the MachineScheduler before register allocation for out-of-order
400   // architectures where we do not use the PostRA scheduler anymore (for now
401   // restricted to swift).
402   return getSchedModel().isOutOfOrder() && isSwift();
403 }
404 
405 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
406 bool ARMSubtarget::enablePostRAScheduler() const {
407   // No need for PostRA scheduling on out of order CPUs (for now restricted to
408   // swift).
409   if (getSchedModel().isOutOfOrder() && isSwift())
410     return false;
411   return (!isThumb() || hasThumb2());
412 }
413 
414 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
415 
416 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
417   // For general targets, the prologue can grow when VFPs are allocated with
418   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
419   // format which it's more important to get right.
420   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
421 }
422 
423 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
424   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
425   // immediates as it is inherently position independent, and may be out of
426   // range otherwise.
427   return !NoMovt && hasV8MBaselineOps() &&
428          (isTargetWindows() || !MF.getFunction()->optForMinSize() || genExecuteOnly());
429 }
430 
431 bool ARMSubtarget::useFastISel() const {
432   // Enable fast-isel for any target, for testing only.
433   if (ForceFastISel)
434     return true;
435 
436   // Limit fast-isel to the targets that are or have been tested.
437   if (!hasV6Ops())
438     return false;
439 
440   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
441   return TM.Options.EnableFastISel &&
442          ((isTargetMachO() && !isThumb1Only()) ||
443           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
444 }
445