1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 
16 #include "ARMCallLowering.h"
17 #include "ARMLegalizerInfo.h"
18 #include "ARMRegisterBankInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMFrameLowering.h"
21 #include "ARMInstrInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "MCTargetDesc/ARMMCTargetDesc.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb1InstrInfo.h"
27 #include "Thumb2InstrInfo.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCTargetOptions.h"
40 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/TargetParser.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include <cassert>
45 #include <string>
46 
47 using namespace llvm;
48 
49 #define DEBUG_TYPE "arm-subtarget"
50 
51 #define GET_SUBTARGETINFO_TARGET_DESC
52 #define GET_SUBTARGETINFO_CTOR
53 #include "ARMGenSubtargetInfo.inc"
54 
55 static cl::opt<bool>
56 UseFusedMulOps("arm-use-mulops",
57                cl::init(true), cl::Hidden);
58 
59 enum ITMode {
60   DefaultIT,
61   RestrictedIT,
62   NoRestrictedIT
63 };
64 
65 static cl::opt<ITMode>
66 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
67    cl::ZeroOrMore,
68    cl::values(clEnumValN(DefaultIT, "arm-default-it",
69                          "Generate IT block based on arch"),
70               clEnumValN(RestrictedIT, "arm-restrict-it",
71                          "Disallow deprecated IT based on ARMv8"),
72               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
73                          "Allow IT blocks based on ARMv7")));
74 
75 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
76 /// currently supported (for testing only).
77 static cl::opt<bool>
78 ForceFastISel("arm-force-fast-isel",
79                cl::init(false), cl::Hidden);
80 
81 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
82 /// so that we can use initializer lists for subtarget initialization.
83 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
84                                                             StringRef FS) {
85   initializeEnvironment();
86   initSubtargetFeatures(CPU, FS);
87   return *this;
88 }
89 
90 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
91                                                         StringRef FS) {
92   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
93   if (STI.isThumb1Only())
94     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
95 
96   return new ARMFrameLowering(STI);
97 }
98 
99 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
100                            const std::string &FS,
101                            const ARMBaseTargetMachine &TM, bool IsLittle)
102     : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
103       CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options),
104       TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)),
105       // At this point initializeSubtargetDependencies has been called so
106       // we can query directly.
107       InstrInfo(isThumb1Only()
108                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
109                     : !isThumb()
110                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
111                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
112       TLInfo(TM, *this) {
113 
114   CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
115   Legalizer.reset(new ARMLegalizerInfo(*this));
116 
117   auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
118 
119   // FIXME: At this point, we can't rely on Subtarget having RBI.
120   // It's awkward to mix passing RBI and the Subtarget; should we pass
121   // TII/TRI as well?
122   InstSelector.reset(createARMInstructionSelector(
123       *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
124 
125   RegBankInfo.reset(RBI);
126 }
127 
128 const CallLowering *ARMSubtarget::getCallLowering() const {
129   return CallLoweringInfo.get();
130 }
131 
132 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
133   return InstSelector.get();
134 }
135 
136 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
137   return Legalizer.get();
138 }
139 
140 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
141   return RegBankInfo.get();
142 }
143 
144 bool ARMSubtarget::isXRaySupported() const {
145   // We don't currently suppport Thumb, but Windows requires Thumb.
146   return hasV6Ops() && hasARMOps() && !isTargetWindows();
147 }
148 
149 void ARMSubtarget::initializeEnvironment() {
150   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
151   // directly from it, but we can try to make sure they're consistent when both
152   // available.
153   UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
154   assert((!TM.getMCAsmInfo() ||
155           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
156            ExceptionHandling::SjLj) == UseSjLjEH) &&
157          "inconsistent sjlj choice between CodeGen and MC");
158 }
159 
160 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
161   if (CPUString.empty()) {
162     CPUString = "generic";
163 
164     if (isTargetDarwin()) {
165       StringRef ArchName = TargetTriple.getArchName();
166       ARM::ArchKind AK = ARM::parseArch(ArchName);
167       if (AK == ARM::ArchKind::ARMV7S)
168         // Default to the Swift CPU when targeting armv7s/thumbv7s.
169         CPUString = "swift";
170       else if (AK == ARM::ArchKind::ARMV7K)
171         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
172         // ARMv7k does not use SjLj exception handling.
173         CPUString = "cortex-a7";
174     }
175   }
176 
177   // Insert the architecture feature derived from the target triple into the
178   // feature string. This is important for setting features that are implied
179   // based on the architecture version.
180   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
181   if (!FS.empty()) {
182     if (!ArchFS.empty())
183       ArchFS = (Twine(ArchFS) + "," + FS).str();
184     else
185       ArchFS = FS;
186   }
187   ParseSubtargetFeatures(CPUString, ArchFS);
188 
189   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
190   // Assert this for now to make the change obvious.
191   assert(hasV6T2Ops() || !hasThumb2());
192 
193   // Execute only support requires movt support
194   if (genExecuteOnly())
195     assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
196 
197   // Keep a pointer to static instruction cost data for the specified CPU.
198   SchedModel = getSchedModelForCPU(CPUString);
199 
200   // Initialize scheduling itinerary for the specified CPU.
201   InstrItins = getInstrItineraryForCPU(CPUString);
202 
203   // FIXME: this is invalid for WindowsCE
204   if (isTargetWindows())
205     NoARM = true;
206 
207   if (isAAPCS_ABI())
208     stackAlignment = 8;
209   if (isTargetNaCl() || isAAPCS16_ABI())
210     stackAlignment = 16;
211 
212   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
213   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
214   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
215   // support in the assembler and linker to be used. This would need to be
216   // fixed to fully support tail calls in Thumb1.
217   //
218   // For ARMv8-M, we /do/ implement tail calls.  Doing this is tricky for v8-M
219   // baseline, since the LDM/POP instruction on Thumb doesn't take LR.  This
220   // means if we need to reload LR, it takes extra instructions, which outweighs
221   // the value of the tail call; but here we don't know yet whether LR is going
222   // to be used. We generate the tail call here and turn it back into CALL/RET
223   // in emitEpilogue if LR is used.
224 
225   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
226   // but we need to make sure there are enough registers; the only valid
227   // registers are the 4 used for parameters.  We don't currently do this
228   // case.
229 
230   SupportsTailCall = !isThumb() || hasV8MBaselineOps();
231 
232   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
233     SupportsTailCall = false;
234 
235   switch (IT) {
236   case DefaultIT:
237     RestrictIT = hasV8Ops();
238     break;
239   case RestrictedIT:
240     RestrictIT = true;
241     break;
242   case NoRestrictedIT:
243     RestrictIT = false;
244     break;
245   }
246 
247   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
248   const FeatureBitset &Bits = getFeatureBits();
249   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
250       (Options.UnsafeFPMath || isTargetDarwin()))
251     UseNEONForSinglePrecisionFP = true;
252 
253   if (isRWPI())
254     ReserveR9 = true;
255 
256   // FIXME: Teach TableGen to deal with these instead of doing it manually here.
257   switch (ARMProcFamily) {
258   case Others:
259   case CortexA5:
260     break;
261   case CortexA7:
262     LdStMultipleTiming = DoubleIssue;
263     break;
264   case CortexA8:
265     LdStMultipleTiming = DoubleIssue;
266     break;
267   case CortexA9:
268     LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
269     PreISelOperandLatencyAdjustment = 1;
270     break;
271   case CortexA12:
272     break;
273   case CortexA15:
274     MaxInterleaveFactor = 2;
275     PreISelOperandLatencyAdjustment = 1;
276     PartialUpdateClearance = 12;
277     break;
278   case CortexA17:
279   case CortexA32:
280   case CortexA35:
281   case CortexA53:
282   case CortexA55:
283   case CortexA57:
284   case CortexA72:
285   case CortexA73:
286   case CortexA75:
287   case CortexR4:
288   case CortexR4F:
289   case CortexR5:
290   case CortexR7:
291   case CortexM3:
292   case CortexR52:
293   case ExynosM1:
294   case Kryo:
295     break;
296   case Krait:
297     PreISelOperandLatencyAdjustment = 1;
298     break;
299   case Swift:
300     MaxInterleaveFactor = 2;
301     LdStMultipleTiming = SingleIssuePlusExtras;
302     PreISelOperandLatencyAdjustment = 1;
303     PartialUpdateClearance = 12;
304     break;
305   }
306 }
307 
308 bool ARMSubtarget::isAPCS_ABI() const {
309   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
310   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
311 }
312 bool ARMSubtarget::isAAPCS_ABI() const {
313   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
314   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
315          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
316 }
317 bool ARMSubtarget::isAAPCS16_ABI() const {
318   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
319   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
320 }
321 
322 bool ARMSubtarget::isROPI() const {
323   return TM.getRelocationModel() == Reloc::ROPI ||
324          TM.getRelocationModel() == Reloc::ROPI_RWPI;
325 }
326 bool ARMSubtarget::isRWPI() const {
327   return TM.getRelocationModel() == Reloc::RWPI ||
328          TM.getRelocationModel() == Reloc::ROPI_RWPI;
329 }
330 
331 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
332   if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
333     return true;
334 
335   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
336   // the section that is being relocated. This means we have to use o load even
337   // for GVs that are known to be local to the dso.
338   if (isTargetMachO() && TM.isPositionIndependent() &&
339       (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
340     return true;
341 
342   return false;
343 }
344 
345 ARMCP::ARMCPModifier ARMSubtarget::getCPModifier(const GlobalValue *GV) const {
346   if (isTargetELF() && TM.isPositionIndependent() &&
347       !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
348     return ARMCP::GOT_PREL;
349   return ARMCP::no_modifier;
350 }
351 
352 unsigned ARMSubtarget::getMispredictionPenalty() const {
353   return SchedModel.MispredictPenalty;
354 }
355 
356 bool ARMSubtarget::hasSinCos() const {
357   return isTargetWatchOS() ||
358     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
359 }
360 
361 bool ARMSubtarget::enableMachineScheduler() const {
362   // Enable the MachineScheduler before register allocation for subtargets
363   // with the use-misched feature.
364   return useMachineScheduler();
365 }
366 
367 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
368 bool ARMSubtarget::enablePostRAScheduler() const {
369   if (disablePostRAScheduler())
370     return false;
371   // Don't reschedule potential IT blocks.
372   return !isThumb1Only();
373 }
374 
375 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }
376 
377 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
378   // For general targets, the prologue can grow when VFPs are allocated with
379   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
380   // format which it's more important to get right.
381   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
382 }
383 
384 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
385   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
386   // immediates as it is inherently position independent, and may be out of
387   // range otherwise.
388   return !NoMovt && hasV8MBaselineOps() &&
389          (isTargetWindows() || !MF.getFunction()->optForMinSize() || genExecuteOnly());
390 }
391 
392 bool ARMSubtarget::useFastISel() const {
393   // Enable fast-isel for any target, for testing only.
394   if (ForceFastISel)
395     return true;
396 
397   // Limit fast-isel to the targets that are or have been tested.
398   if (!hasV6Ops())
399     return false;
400 
401   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
402   return TM.Options.EnableFastISel &&
403          ((isTargetMachO() && !isThumb1Only()) ||
404           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
405 }
406