1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/GlobalValue.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "arm-subtarget"
39 
40 #define GET_SUBTARGETINFO_TARGET_DESC
41 #define GET_SUBTARGETINFO_CTOR
42 #include "ARMGenSubtargetInfo.inc"
43 
44 static cl::opt<bool>
45 UseFusedMulOps("arm-use-mulops",
46                cl::init(true), cl::Hidden);
47 
48 enum ITMode {
49   DefaultIT,
50   RestrictedIT,
51   NoRestrictedIT
52 };
53 
54 static cl::opt<ITMode>
55 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
56    cl::ZeroOrMore,
57    cl::values(clEnumValN(DefaultIT, "arm-default-it",
58                          "Generate IT block based on arch"),
59               clEnumValN(RestrictedIT, "arm-restrict-it",
60                          "Disallow deprecated IT based on ARMv8"),
61               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
62                          "Allow IT blocks based on ARMv7"),
63               clEnumValEnd));
64 
65 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
66 /// currently supported (for testing only).
67 static cl::opt<bool>
68 ForceFastISel("arm-force-fast-isel",
69                cl::init(false), cl::Hidden);
70 
71 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
72 /// so that we can use initializer lists for subtarget initialization.
73 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
74                                                             StringRef FS) {
75   initializeEnvironment();
76   initSubtargetFeatures(CPU, FS);
77   return *this;
78 }
79 
80 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
81                                                         StringRef FS) {
82   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
83   if (STI.isThumb1Only())
84     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
85 
86   return new ARMFrameLowering(STI);
87 }
88 
89 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
90                            const std::string &FS,
91                            const ARMBaseTargetMachine &TM, bool IsLittle)
92     : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
93       ARMProcClass(None), ARMArch(ARMv4t), stackAlignment(4), CPUString(CPU),
94       IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
95       FrameLowering(initializeFrameLowering(CPU, FS)),
96       // At this point initializeSubtargetDependencies has been called so
97       // we can query directly.
98       InstrInfo(isThumb1Only()
99                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
100                     : !isThumb()
101                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
102                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
103       TLInfo(TM, *this) {}
104 
105 void ARMSubtarget::initializeEnvironment() {
106   HasV4TOps = false;
107   HasV5TOps = false;
108   HasV5TEOps = false;
109   HasV6Ops = false;
110   HasV6MOps = false;
111   HasV6KOps = false;
112   HasV6T2Ops = false;
113   HasV7Ops = false;
114   HasV8Ops = false;
115   HasV8_1aOps = false;
116   HasV8_2aOps = false;
117   HasV8MBaselineOps = false;
118   HasV8MMainlineOps = false;
119   HasVFPv2 = false;
120   HasVFPv3 = false;
121   HasVFPv4 = false;
122   HasFPARMv8 = false;
123   HasNEON = false;
124   UseNEONForSinglePrecisionFP = false;
125   UseMulOps = UseFusedMulOps;
126   SlowFPVMLx = false;
127   HasVMLxForwarding = false;
128   SlowFPBrcc = false;
129   InThumbMode = false;
130   UseSoftFloat = false;
131   HasThumb2 = false;
132   NoARM = false;
133   ReserveR9 = false;
134   NoMovt = false;
135   SupportsTailCall = false;
136   HasFP16 = false;
137   HasFullFP16 = false;
138   HasD16 = false;
139   HasHardwareDivide = false;
140   HasHardwareDivideInARM = false;
141   HasT2ExtractPack = false;
142   HasDataBarrier = false;
143   Pref32BitThumb = false;
144   AvoidCPSRPartialUpdate = false;
145   AvoidMOVsShifterOperand = false;
146   HasRetAddrStack = false;
147   HasMPExtension = false;
148   HasVirtualization = false;
149   FPOnlySP = false;
150   HasPerfMon = false;
151   HasTrustZone = false;
152   Has8MSecExt = false;
153   HasCrypto = false;
154   HasCRC = false;
155   HasRAS = false;
156   HasZeroCycleZeroing = false;
157   StrictAlign = false;
158   HasDSP = false;
159   UseNaClTrap = false;
160   GenLongCalls = false;
161   UnsafeFPMath = false;
162   HasV7Clrex = false;
163   HasAcquireRelease = false;
164 
165   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
166   // directly from it, but we can try to make sure they're consistent when both
167   // available.
168   UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
169   assert((!TM.getMCAsmInfo() ||
170           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
171            ExceptionHandling::SjLj) == UseSjLjEH) &&
172          "inconsistent sjlj choice between CodeGen and MC");
173 }
174 
175 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
176   if (CPUString.empty()) {
177     CPUString = "generic";
178 
179     if (isTargetDarwin()) {
180       StringRef ArchName = TargetTriple.getArchName();
181       if (ArchName.endswith("v7s"))
182         // Default to the Swift CPU when targeting armv7s/thumbv7s.
183         CPUString = "swift";
184       else if (ArchName.endswith("v7k"))
185         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
186         // ARMv7k does not use SjLj exception handling.
187         CPUString = "cortex-a7";
188     }
189   }
190 
191   // Insert the architecture feature derived from the target triple into the
192   // feature string. This is important for setting features that are implied
193   // based on the architecture version.
194   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
195   if (!FS.empty()) {
196     if (!ArchFS.empty())
197       ArchFS = (Twine(ArchFS) + "," + FS).str();
198     else
199       ArchFS = FS;
200   }
201   ParseSubtargetFeatures(CPUString, ArchFS);
202 
203   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
204   // Assert this for now to make the change obvious.
205   assert(hasV6T2Ops() || !hasThumb2());
206 
207   // Keep a pointer to static instruction cost data for the specified CPU.
208   SchedModel = getSchedModelForCPU(CPUString);
209 
210   // Initialize scheduling itinerary for the specified CPU.
211   InstrItins = getInstrItineraryForCPU(CPUString);
212 
213   // FIXME: this is invalid for WindowsCE
214   if (isTargetWindows())
215     NoARM = true;
216 
217   if (isAAPCS_ABI())
218     stackAlignment = 8;
219   if (isTargetNaCl() || isAAPCS16_ABI())
220     stackAlignment = 16;
221 
222   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
223   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
224   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
225   // support in the assembler and linker to be used. This would need to be
226   // fixed to fully support tail calls in Thumb1.
227   //
228   // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
229   // LR.  This means if we need to reload LR, it takes an extra instructions,
230   // which outweighs the value of the tail call; but here we don't know yet
231   // whether LR is going to be used.  Probably the right approach is to
232   // generate the tail call here and turn it back into CALL/RET in
233   // emitEpilogue if LR is used.
234 
235   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
236   // but we need to make sure there are enough registers; the only valid
237   // registers are the 4 used for parameters.  We don't currently do this
238   // case.
239 
240   SupportsTailCall = !isThumb() || hasV8MBaselineOps();
241 
242   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
243     SupportsTailCall = false;
244 
245   switch (IT) {
246   case DefaultIT:
247     RestrictIT = hasV8Ops();
248     break;
249   case RestrictedIT:
250     RestrictIT = true;
251     break;
252   case NoRestrictedIT:
253     RestrictIT = false;
254     break;
255   }
256 
257   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
258   const FeatureBitset &Bits = getFeatureBits();
259   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
260       (Options.UnsafeFPMath || isTargetDarwin()))
261     UseNEONForSinglePrecisionFP = true;
262 }
263 
264 bool ARMSubtarget::isAPCS_ABI() const {
265   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
266   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
267 }
268 bool ARMSubtarget::isAAPCS_ABI() const {
269   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
270   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
271          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
272 }
273 bool ARMSubtarget::isAAPCS16_ABI() const {
274   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
275   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
276 }
277 
278 /// true if the GV will be accessed via an indirect symbol.
279 bool
280 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
281                                  Reloc::Model RelocM) const {
282   if (!shouldAssumeDSOLocal(RelocM, TargetTriple, *GV->getParent(), GV))
283     return true;
284 
285   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
286   // the section that is being relocated. This means we have to use o load even
287   // for GVs that are known to be local to the dso.
288   if (isTargetDarwin() && RelocM == Reloc::PIC_ &&
289       (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
290     return true;
291 
292   return false;
293 }
294 
295 unsigned ARMSubtarget::getMispredictionPenalty() const {
296   return SchedModel.MispredictPenalty;
297 }
298 
299 bool ARMSubtarget::hasSinCos() const {
300   return isTargetWatchOS() ||
301     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
302 }
303 
304 bool ARMSubtarget::enableMachineScheduler() const {
305   // Enable the MachineScheduler before register allocation for out-of-order
306   // architectures where we do not use the PostRA scheduler anymore (for now
307   // restricted to swift).
308   return getSchedModel().isOutOfOrder() && isSwift();
309 }
310 
311 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
312 bool ARMSubtarget::enablePostRAScheduler() const {
313   // No need for PostRA scheduling on out of order CPUs (for now restricted to
314   // swift).
315   if (getSchedModel().isOutOfOrder() && isSwift())
316     return false;
317   return (!isThumb() || hasThumb2());
318 }
319 
320 bool ARMSubtarget::enableAtomicExpand() const {
321   return hasAnyDataBarrier() && (!isThumb() || hasV8MBaselineOps());
322 }
323 
324 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
325   // For general targets, the prologue can grow when VFPs are allocated with
326   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
327   // format which it's more important to get right.
328   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
329 }
330 
331 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
332   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
333   // immediates as it is inherently position independent, and may be out of
334   // range otherwise.
335   return !NoMovt && hasV8MBaselineOps() &&
336          (isTargetWindows() || !MF.getFunction()->optForMinSize());
337 }
338 
339 bool ARMSubtarget::useFastISel() const {
340   // Enable fast-isel for any target, for testing only.
341   if (ForceFastISel)
342     return true;
343 
344   // Limit fast-isel to the targets that are or have been tested.
345   if (!hasV6Ops())
346     return false;
347 
348   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
349   return TM.Options.EnableFastISel &&
350          ((isTargetMachO() && !isThumb1Only()) ||
351           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
352 }
353