1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "arm-subtarget"
38 
39 #define GET_SUBTARGETINFO_TARGET_DESC
40 #define GET_SUBTARGETINFO_CTOR
41 #include "ARMGenSubtargetInfo.inc"
42 
43 static cl::opt<bool>
44 UseFusedMulOps("arm-use-mulops",
45                cl::init(true), cl::Hidden);
46 
47 enum ITMode {
48   DefaultIT,
49   RestrictedIT,
50   NoRestrictedIT
51 };
52 
53 static cl::opt<ITMode>
54 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
55    cl::ZeroOrMore,
56    cl::values(clEnumValN(DefaultIT, "arm-default-it",
57                          "Generate IT block based on arch"),
58               clEnumValN(RestrictedIT, "arm-restrict-it",
59                          "Disallow deprecated IT based on ARMv8"),
60               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
61                          "Allow IT blocks based on ARMv7"),
62               clEnumValEnd));
63 
64 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
65 /// currently supported (for testing only).
66 static cl::opt<bool>
67 ForceFastISel("arm-force-fast-isel",
68                cl::init(false), cl::Hidden);
69 
70 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
71 /// so that we can use initializer lists for subtarget initialization.
72 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
73                                                             StringRef FS) {
74   initializeEnvironment();
75   initSubtargetFeatures(CPU, FS);
76   return *this;
77 }
78 
79 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
80                                                         StringRef FS) {
81   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
82   if (STI.isThumb1Only())
83     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
84 
85   return new ARMFrameLowering(STI);
86 }
87 
88 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
89                            const std::string &FS,
90                            const ARMBaseTargetMachine &TM, bool IsLittle)
91     : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
92       ARMProcClass(None), ARMArch(ARMv4t), stackAlignment(4), CPUString(CPU),
93       IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
94       FrameLowering(initializeFrameLowering(CPU, FS)),
95       // At this point initializeSubtargetDependencies has been called so
96       // we can query directly.
97       InstrInfo(isThumb1Only()
98                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
99                     : !isThumb()
100                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
101                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
102       TLInfo(TM, *this) {}
103 
104 void ARMSubtarget::initializeEnvironment() {
105   HasV4TOps = false;
106   HasV5TOps = false;
107   HasV5TEOps = false;
108   HasV6Ops = false;
109   HasV6MOps = false;
110   HasV6KOps = false;
111   HasV6T2Ops = false;
112   HasV7Ops = false;
113   HasV8Ops = false;
114   HasV8_1aOps = false;
115   HasVFPv2 = false;
116   HasVFPv3 = false;
117   HasVFPv4 = false;
118   HasFPARMv8 = false;
119   HasNEON = false;
120   UseNEONForSinglePrecisionFP = false;
121   UseMulOps = UseFusedMulOps;
122   SlowFPVMLx = false;
123   HasVMLxForwarding = false;
124   SlowFPBrcc = false;
125   InThumbMode = false;
126   UseSoftFloat = false;
127   HasThumb2 = false;
128   NoARM = false;
129   ReserveR9 = false;
130   NoMovt = false;
131   SupportsTailCall = false;
132   HasFP16 = false;
133   HasD16 = false;
134   HasHardwareDivide = false;
135   HasHardwareDivideInARM = false;
136   HasT2ExtractPack = false;
137   HasDataBarrier = false;
138   Pref32BitThumb = false;
139   AvoidCPSRPartialUpdate = false;
140   AvoidMOVsShifterOperand = false;
141   HasRAS = false;
142   HasMPExtension = false;
143   HasVirtualization = false;
144   FPOnlySP = false;
145   HasPerfMon = false;
146   HasTrustZone = false;
147   HasCrypto = false;
148   HasCRC = false;
149   HasZeroCycleZeroing = false;
150   StrictAlign = false;
151   HasDSP = false;
152   UseNaClTrap = false;
153   GenLongCalls = false;
154   UnsafeFPMath = false;
155 
156   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
157   // directly from it, but we can try to make sure they're consistent when both
158   // available.
159   UseSjLjEH = isTargetDarwin() && !isTargetWatchOS();
160   assert((!TM.getMCAsmInfo() ||
161           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
162            ExceptionHandling::SjLj) == UseSjLjEH) &&
163          "inconsistent sjlj choice between CodeGen and MC");
164 }
165 
166 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
167   if (CPUString.empty()) {
168     CPUString = "generic";
169 
170     if (isTargetDarwin()) {
171       StringRef ArchName = TargetTriple.getArchName();
172       if (ArchName.endswith("v7s"))
173         // Default to the Swift CPU when targeting armv7s/thumbv7s.
174         CPUString = "swift";
175       else if (ArchName.endswith("v7k"))
176         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
177         // ARMv7k does not use SjLj exception handling.
178         CPUString = "cortex-a7";
179     }
180   }
181 
182   // Insert the architecture feature derived from the target triple into the
183   // feature string. This is important for setting features that are implied
184   // based on the architecture version.
185   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
186   if (!FS.empty()) {
187     if (!ArchFS.empty())
188       ArchFS = (Twine(ArchFS) + "," + FS).str();
189     else
190       ArchFS = FS;
191   }
192   ParseSubtargetFeatures(CPUString, ArchFS);
193 
194   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
195   // Assert this for now to make the change obvious.
196   assert(hasV6T2Ops() || !hasThumb2());
197 
198   // Keep a pointer to static instruction cost data for the specified CPU.
199   SchedModel = getSchedModelForCPU(CPUString);
200 
201   // Initialize scheduling itinerary for the specified CPU.
202   InstrItins = getInstrItineraryForCPU(CPUString);
203 
204   // FIXME: this is invalid for WindowsCE
205   if (isTargetWindows())
206     NoARM = true;
207 
208   if (isAAPCS_ABI())
209     stackAlignment = 8;
210   if (isTargetNaCl() || isAAPCS16_ABI())
211     stackAlignment = 16;
212 
213   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
214   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
215   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
216   // support in the assembler and linker to be used. This would need to be
217   // fixed to fully support tail calls in Thumb1.
218   //
219   // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
220   // LR.  This means if we need to reload LR, it takes an extra instructions,
221   // which outweighs the value of the tail call; but here we don't know yet
222   // whether LR is going to be used.  Probably the right approach is to
223   // generate the tail call here and turn it back into CALL/RET in
224   // emitEpilogue if LR is used.
225 
226   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
227   // but we need to make sure there are enough registers; the only valid
228   // registers are the 4 used for parameters.  We don't currently do this
229   // case.
230 
231   SupportsTailCall = !isThumb1Only();
232 
233   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
234     SupportsTailCall = false;
235 
236   switch (IT) {
237   case DefaultIT:
238     RestrictIT = hasV8Ops();
239     break;
240   case RestrictedIT:
241     RestrictIT = true;
242     break;
243   case NoRestrictedIT:
244     RestrictIT = false;
245     break;
246   }
247 
248   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
249   const FeatureBitset &Bits = getFeatureBits();
250   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
251       (Options.UnsafeFPMath || isTargetDarwin()))
252     UseNEONForSinglePrecisionFP = true;
253 }
254 
255 bool ARMSubtarget::isAPCS_ABI() const {
256   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
257   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
258 }
259 bool ARMSubtarget::isAAPCS_ABI() const {
260   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
261   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
262          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
263 }
264 bool ARMSubtarget::isAAPCS16_ABI() const {
265   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
266   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
267 }
268 
269 
270 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
271 bool
272 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
273                                  Reloc::Model RelocM) const {
274   if (RelocM == Reloc::Static)
275     return false;
276 
277   bool isDef = GV->isStrongDefinitionForLinker();
278 
279   if (!isTargetMachO()) {
280     // Extra load is needed for all externally visible.
281     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
282       return false;
283     return true;
284   } else {
285     // If this is a strong reference to a definition, it is definitely not
286     // through a stub.
287     if (isDef)
288       return false;
289 
290     // Unless we have a symbol with hidden visibility, we have to go through a
291     // normal $non_lazy_ptr stub because this symbol might be resolved late.
292     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
293       return true;
294 
295     if (RelocM == Reloc::PIC_) {
296       // If symbol visibility is hidden, we have a stub for common symbol
297       // references and external declarations.
298       if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
299         // Hidden $non_lazy_ptr reference.
300         return true;
301     }
302   }
303 
304   return false;
305 }
306 
307 unsigned ARMSubtarget::getMispredictionPenalty() const {
308   return SchedModel.MispredictPenalty;
309 }
310 
311 bool ARMSubtarget::hasSinCos() const {
312   return isTargetWatchOS() ||
313     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
314 }
315 
316 bool ARMSubtarget::enableMachineScheduler() const {
317   // Enable the MachineScheduler before register allocation for out-of-order
318   // architectures where we do not use the PostRA scheduler anymore (for now
319   // restricted to swift).
320   return getSchedModel().isOutOfOrder() && isSwift();
321 }
322 
323 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
324 bool ARMSubtarget::enablePostRAScheduler() const {
325   // No need for PostRA scheduling on out of order CPUs (for now restricted to
326   // swift).
327   if (getSchedModel().isOutOfOrder() && isSwift())
328     return false;
329   return (!isThumb() || hasThumb2());
330 }
331 
332 bool ARMSubtarget::enableAtomicExpand() const {
333   return hasAnyDataBarrier() && !isThumb1Only();
334 }
335 
336 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
337   // For general targets, the prologue can grow when VFPs are allocated with
338   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
339   // format which it's more important to get right.
340   return isTargetWatchOS() || (isSwift() && !MF.getFunction()->optForMinSize());
341 }
342 
343 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
344   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
345   // immediates as it is inherently position independent, and may be out of
346   // range otherwise.
347   return !NoMovt && hasV6T2Ops() &&
348          (isTargetWindows() || !MF.getFunction()->optForMinSize());
349 }
350 
351 bool ARMSubtarget::useFastISel() const {
352   // Enable fast-isel for any target, for testing only.
353   if (ForceFastISel)
354     return true;
355 
356   // Limit fast-isel to the targets that are or have been tested.
357   if (!hasV6Ops())
358     return false;
359 
360   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
361   return TM.Options.EnableFastISel &&
362          ((isTargetMachO() && !isThumb1Only()) ||
363           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
364 }
365