1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "arm-subtarget"
38 
39 #define GET_SUBTARGETINFO_TARGET_DESC
40 #define GET_SUBTARGETINFO_CTOR
41 #include "ARMGenSubtargetInfo.inc"
42 
43 static cl::opt<bool>
44 UseFusedMulOps("arm-use-mulops",
45                cl::init(true), cl::Hidden);
46 
47 enum ITMode {
48   DefaultIT,
49   RestrictedIT,
50   NoRestrictedIT
51 };
52 
53 static cl::opt<ITMode>
54 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
55    cl::ZeroOrMore,
56    cl::values(clEnumValN(DefaultIT, "arm-default-it",
57                          "Generate IT block based on arch"),
58               clEnumValN(RestrictedIT, "arm-restrict-it",
59                          "Disallow deprecated IT based on ARMv8"),
60               clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
61                          "Allow IT blocks based on ARMv7"),
62               clEnumValEnd));
63 
64 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
65 /// currently supported (for testing only).
66 static cl::opt<bool>
67 ForceFastISel("arm-force-fast-isel",
68                cl::init(false), cl::Hidden);
69 
70 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
71 /// so that we can use initializer lists for subtarget initialization.
72 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
73                                                             StringRef FS) {
74   initializeEnvironment();
75   initSubtargetFeatures(CPU, FS);
76   return *this;
77 }
78 
79 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
80                                                         StringRef FS) {
81   ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
82   if (STI.isThumb1Only())
83     return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
84 
85   return new ARMFrameLowering(STI);
86 }
87 
88 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
89                            const std::string &FS,
90                            const ARMBaseTargetMachine &TM, bool IsLittle)
91     : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
92       ARMProcClass(None), ARMArch(ARMv4t), stackAlignment(4), CPUString(CPU),
93       IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
94       FrameLowering(initializeFrameLowering(CPU, FS)),
95       // At this point initializeSubtargetDependencies has been called so
96       // we can query directly.
97       InstrInfo(isThumb1Only()
98                     ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
99                     : !isThumb()
100                           ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
101                           : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
102       TLInfo(TM, *this) {}
103 
104 void ARMSubtarget::initializeEnvironment() {
105   HasV4TOps = false;
106   HasV5TOps = false;
107   HasV5TEOps = false;
108   HasV6Ops = false;
109   HasV6MOps = false;
110   HasV6KOps = false;
111   HasV6T2Ops = false;
112   HasV7Ops = false;
113   HasV8Ops = false;
114   HasV8_1aOps = false;
115   HasV8_2aOps = false;
116   HasV8MBaselineOps = false;
117   HasV8MMainlineOps = false;
118   HasVFPv2 = false;
119   HasVFPv3 = false;
120   HasVFPv4 = false;
121   HasFPARMv8 = false;
122   HasNEON = false;
123   UseNEONForSinglePrecisionFP = false;
124   UseMulOps = UseFusedMulOps;
125   SlowFPVMLx = false;
126   HasVMLxForwarding = false;
127   SlowFPBrcc = false;
128   InThumbMode = false;
129   UseSoftFloat = false;
130   HasThumb2 = false;
131   NoARM = false;
132   ReserveR9 = false;
133   NoMovt = false;
134   SupportsTailCall = false;
135   HasFP16 = false;
136   HasFullFP16 = false;
137   HasD16 = false;
138   HasHardwareDivide = false;
139   HasHardwareDivideInARM = false;
140   HasT2ExtractPack = false;
141   HasDataBarrier = false;
142   Pref32BitThumb = false;
143   AvoidCPSRPartialUpdate = false;
144   AvoidMOVsShifterOperand = false;
145   HasRAS = false;
146   HasMPExtension = false;
147   HasVirtualization = false;
148   FPOnlySP = false;
149   HasPerfMon = false;
150   HasTrustZone = false;
151   Has8MSecExt = false;
152   HasCrypto = false;
153   HasCRC = false;
154   HasZeroCycleZeroing = false;
155   StrictAlign = false;
156   HasDSP = false;
157   UseNaClTrap = false;
158   GenLongCalls = false;
159   UnsafeFPMath = false;
160   HasV7Clrex = false;
161   HasAcquireRelease = false;
162 
163   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
164   // directly from it, but we can try to make sure they're consistent when both
165   // available.
166   UseSjLjEH = isTargetDarwin() && !isTargetWatchABI();
167   assert((!TM.getMCAsmInfo() ||
168           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
169            ExceptionHandling::SjLj) == UseSjLjEH) &&
170          "inconsistent sjlj choice between CodeGen and MC");
171 }
172 
173 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
174   if (CPUString.empty()) {
175     CPUString = "generic";
176 
177     if (isTargetDarwin()) {
178       StringRef ArchName = TargetTriple.getArchName();
179       if (ArchName.endswith("v7s"))
180         // Default to the Swift CPU when targeting armv7s/thumbv7s.
181         CPUString = "swift";
182       else if (ArchName.endswith("v7k"))
183         // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
184         // ARMv7k does not use SjLj exception handling.
185         CPUString = "cortex-a7";
186     }
187   }
188 
189   // Insert the architecture feature derived from the target triple into the
190   // feature string. This is important for setting features that are implied
191   // based on the architecture version.
192   std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
193   if (!FS.empty()) {
194     if (!ArchFS.empty())
195       ArchFS = (Twine(ArchFS) + "," + FS).str();
196     else
197       ArchFS = FS;
198   }
199   ParseSubtargetFeatures(CPUString, ArchFS);
200 
201   // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
202   // Assert this for now to make the change obvious.
203   assert(hasV6T2Ops() || !hasThumb2());
204 
205   // Keep a pointer to static instruction cost data for the specified CPU.
206   SchedModel = getSchedModelForCPU(CPUString);
207 
208   // Initialize scheduling itinerary for the specified CPU.
209   InstrItins = getInstrItineraryForCPU(CPUString);
210 
211   // FIXME: this is invalid for WindowsCE
212   if (isTargetWindows())
213     NoARM = true;
214 
215   if (isAAPCS_ABI())
216     stackAlignment = 8;
217   if (isTargetNaCl() || isAAPCS16_ABI())
218     stackAlignment = 16;
219 
220   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
221   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
222   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
223   // support in the assembler and linker to be used. This would need to be
224   // fixed to fully support tail calls in Thumb1.
225   //
226   // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
227   // LR.  This means if we need to reload LR, it takes an extra instructions,
228   // which outweighs the value of the tail call; but here we don't know yet
229   // whether LR is going to be used.  Probably the right approach is to
230   // generate the tail call here and turn it back into CALL/RET in
231   // emitEpilogue if LR is used.
232 
233   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
234   // but we need to make sure there are enough registers; the only valid
235   // registers are the 4 used for parameters.  We don't currently do this
236   // case.
237 
238   SupportsTailCall = !isThumb() || hasV8MBaselineOps();
239 
240   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
241     SupportsTailCall = false;
242 
243   switch (IT) {
244   case DefaultIT:
245     RestrictIT = hasV8Ops();
246     break;
247   case RestrictedIT:
248     RestrictIT = true;
249     break;
250   case NoRestrictedIT:
251     RestrictIT = false;
252     break;
253   }
254 
255   // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
256   const FeatureBitset &Bits = getFeatureBits();
257   if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
258       (Options.UnsafeFPMath || isTargetDarwin()))
259     UseNEONForSinglePrecisionFP = true;
260 }
261 
262 bool ARMSubtarget::isAPCS_ABI() const {
263   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
264   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
265 }
266 bool ARMSubtarget::isAAPCS_ABI() const {
267   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
268   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
269          TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
270 }
271 bool ARMSubtarget::isAAPCS16_ABI() const {
272   assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
273   return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
274 }
275 
276 
277 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
278 bool
279 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
280                                  Reloc::Model RelocM) const {
281   if (RelocM == Reloc::Static)
282     return false;
283 
284   bool isDef = GV->isStrongDefinitionForLinker();
285 
286   if (!isTargetMachO()) {
287     // Extra load is needed for all externally visible.
288     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
289       return false;
290     return true;
291   } else {
292     // If this is a strong reference to a definition, it is definitely not
293     // through a stub.
294     if (isDef)
295       return false;
296 
297     // Unless we have a symbol with hidden visibility, we have to go through a
298     // normal $non_lazy_ptr stub because this symbol might be resolved late.
299     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
300       return true;
301 
302     if (RelocM == Reloc::PIC_) {
303       // If symbol visibility is hidden, we have a stub for common symbol
304       // references and external declarations.
305       if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
306         // Hidden $non_lazy_ptr reference.
307         return true;
308     }
309   }
310 
311   return false;
312 }
313 
314 unsigned ARMSubtarget::getMispredictionPenalty() const {
315   return SchedModel.MispredictPenalty;
316 }
317 
318 bool ARMSubtarget::hasSinCos() const {
319   return isTargetWatchOS() ||
320     (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
321 }
322 
323 bool ARMSubtarget::enableMachineScheduler() const {
324   // Enable the MachineScheduler before register allocation for out-of-order
325   // architectures where we do not use the PostRA scheduler anymore (for now
326   // restricted to swift).
327   return getSchedModel().isOutOfOrder() && isSwift();
328 }
329 
330 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
331 bool ARMSubtarget::enablePostRAScheduler() const {
332   // No need for PostRA scheduling on out of order CPUs (for now restricted to
333   // swift).
334   if (getSchedModel().isOutOfOrder() && isSwift())
335     return false;
336   return (!isThumb() || hasThumb2());
337 }
338 
339 bool ARMSubtarget::enableAtomicExpand() const {
340   return hasAnyDataBarrier() && (!isThumb() || hasV8MBaselineOps());
341 }
342 
343 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
344   // For general targets, the prologue can grow when VFPs are allocated with
345   // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
346   // format which it's more important to get right.
347   return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
348 }
349 
350 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
351   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
352   // immediates as it is inherently position independent, and may be out of
353   // range otherwise.
354   return !NoMovt && hasV8MBaselineOps() &&
355          (isTargetWindows() || !MF.getFunction()->optForMinSize());
356 }
357 
358 bool ARMSubtarget::useFastISel() const {
359   // Enable fast-isel for any target, for testing only.
360   if (ForceFastISel)
361     return true;
362 
363   // Limit fast-isel to the targets that are or have been tested.
364   if (!hasV6Ops())
365     return false;
366 
367   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
368   return TM.Options.EnableFastISel &&
369          ((isTargetMachO() && !isThumb1Only()) ||
370           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
371 }
372